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1470 lines
51 KiB
C
1470 lines
51 KiB
C
/*
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* NVDIMM ACPI Implementation
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*
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* Copyright(C) 2015 Intel Corporation.
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*
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* Author:
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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*
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* NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
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* and the DSM specification can be found at:
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* http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
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*
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* Currently, it only supports PMEM Virtualization.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "qemu/uuid.h"
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#include "qapi/error.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/bios-linker-loader.h"
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#include "hw/nvram/fw_cfg.h"
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#include "hw/mem/nvdimm.h"
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#include "qemu/nvdimm-utils.h"
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#include "trace.h"
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/*
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* define Byte Addressable Persistent Memory (PM) Region according to
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* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
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*/
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static const uint8_t nvdimm_nfit_spa_uuid[] =
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UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
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0x18, 0xb7, 0x8c, 0xdb);
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/*
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* define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
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* Interface Table (NFIT).
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*/
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/*
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* System Physical Address Range Structure
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*
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* It describes the system physical address ranges occupied by NVDIMMs and
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* the types of the regions.
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*/
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struct NvdimmNfitSpa {
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uint16_t type;
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uint16_t length;
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uint16_t spa_index;
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uint16_t flags;
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uint32_t reserved;
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uint32_t proximity_domain;
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uint8_t type_guid[16];
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uint64_t spa_base;
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uint64_t spa_length;
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uint64_t mem_attr;
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} QEMU_PACKED;
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typedef struct NvdimmNfitSpa NvdimmNfitSpa;
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/*
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* Memory Device to System Physical Address Range Mapping Structure
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*
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* It enables identifying each NVDIMM region and the corresponding SPA
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* describing the memory interleave
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*/
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struct NvdimmNfitMemDev {
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uint16_t type;
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uint16_t length;
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uint32_t nfit_handle;
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uint16_t phys_id;
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uint16_t region_id;
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uint16_t spa_index;
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uint16_t dcr_index;
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uint64_t region_len;
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uint64_t region_offset;
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uint64_t region_dpa;
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uint16_t interleave_index;
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uint16_t interleave_ways;
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uint16_t flags;
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uint16_t reserved;
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} QEMU_PACKED;
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typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
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#define ACPI_NFIT_MEM_NOT_ARMED (1 << 3)
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/*
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* NVDIMM Control Region Structure
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*
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* It describes the NVDIMM and if applicable, Block Control Window.
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*/
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struct NvdimmNfitControlRegion {
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uint16_t type;
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uint16_t length;
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uint16_t dcr_index;
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uint16_t vendor_id;
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uint16_t device_id;
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uint16_t revision_id;
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uint16_t sub_vendor_id;
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uint16_t sub_device_id;
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uint16_t sub_revision_id;
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uint8_t reserved[6];
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uint32_t serial_number;
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uint16_t fic;
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uint16_t num_bcw;
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uint64_t bcw_size;
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uint64_t cmd_offset;
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uint64_t cmd_size;
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uint64_t status_offset;
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uint64_t status_size;
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uint16_t flags;
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uint8_t reserved2[6];
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} QEMU_PACKED;
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typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
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/*
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* NVDIMM Platform Capabilities Structure
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*
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* Defined in section 5.2.25.9 of ACPI 6.2 Errata A, September 2017
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*/
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struct NvdimmNfitPlatformCaps {
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uint16_t type;
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uint16_t length;
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uint8_t highest_cap;
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uint8_t reserved[3];
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uint32_t capabilities;
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uint8_t reserved2[4];
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} QEMU_PACKED;
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typedef struct NvdimmNfitPlatformCaps NvdimmNfitPlatformCaps;
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/*
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* Module serial number is a unique number for each device. We use the
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* slot id of NVDIMM device to generate this number so that each device
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* associates with a different number.
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*
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* 0x123456 is a magic number we arbitrarily chose.
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*/
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static uint32_t nvdimm_slot_to_sn(int slot)
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{
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return 0x123456 + slot;
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}
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/*
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* handle is used to uniquely associate nfit_memdev structure with NVDIMM
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* ACPI device - nfit_memdev.nfit_handle matches with the value returned
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* by ACPI device _ADR method.
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*
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* We generate the handle with the slot id of NVDIMM device and reserve
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* 0 for NVDIMM root device.
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*/
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static uint32_t nvdimm_slot_to_handle(int slot)
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{
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return slot + 1;
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}
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/*
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* index uniquely identifies the structure, 0 is reserved which indicates
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* that the structure is not valid or the associated structure is not
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* present.
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*
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* Each NVDIMM device needs two indexes, one for nfit_spa and another for
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* nfit_dc which are generated by the slot id of NVDIMM device.
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*/
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static uint16_t nvdimm_slot_to_spa_index(int slot)
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{
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return (slot + 1) << 1;
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}
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/* See the comments of nvdimm_slot_to_spa_index(). */
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static uint32_t nvdimm_slot_to_dcr_index(int slot)
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{
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return nvdimm_slot_to_spa_index(slot) + 1;
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}
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static NVDIMMDevice *nvdimm_get_device_by_handle(uint32_t handle)
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{
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NVDIMMDevice *nvdimm = NULL;
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GSList *list, *device_list = nvdimm_get_device_list();
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for (list = device_list; list; list = list->next) {
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NVDIMMDevice *nvd = list->data;
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int slot = object_property_get_int(OBJECT(nvd), PC_DIMM_SLOT_PROP,
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NULL);
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if (nvdimm_slot_to_handle(slot) == handle) {
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nvdimm = nvd;
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break;
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}
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}
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g_slist_free(device_list);
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return nvdimm;
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}
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/* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
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static void
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nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitSpa *nfit_spa;
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uint64_t addr = object_property_get_uint(OBJECT(dev), PC_DIMM_ADDR_PROP,
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NULL);
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uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP,
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NULL);
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uint32_t node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP,
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NULL);
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
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nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
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Structure */);
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nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
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nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
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/*
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* Control region is strict as all the device info, such as SN, index,
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* is associated with slot id.
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*/
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nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
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management during hot add/online
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operation */ |
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2 /* Data in Proximity Domain field is
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valid*/);
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/* NUMA node. */
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nfit_spa->proximity_domain = cpu_to_le32(node);
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/* the region reported as PMEM. */
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memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
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sizeof(nvdimm_nfit_spa_uuid));
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nfit_spa->spa_base = cpu_to_le64(addr);
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nfit_spa->spa_length = cpu_to_le64(size);
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/* It is the PMEM and can be cached as writeback. */
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nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
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0x8000ULL /* EFI_MEMORY_NV */);
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}
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/*
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* ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
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* Structure
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*/
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static void
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nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitMemDev *nfit_memdev;
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NVDIMMDevice *nvdimm = NVDIMM(OBJECT(dev));
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uint64_t size = object_property_get_uint(OBJECT(dev), PC_DIMM_SIZE_PROP,
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NULL);
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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uint32_t handle = nvdimm_slot_to_handle(slot);
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nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
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nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
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Range Map Structure*/);
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nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
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nfit_memdev->nfit_handle = cpu_to_le32(handle);
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/*
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* associate memory device with System Physical Address Range
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* Structure.
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*/
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nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
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/* associate memory device with Control Region Structure. */
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nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
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/* The memory region on the device. */
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nfit_memdev->region_len = cpu_to_le64(size);
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/* The device address starts from 0. */
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nfit_memdev->region_dpa = cpu_to_le64(0);
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/* Only one interleave for PMEM. */
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nfit_memdev->interleave_ways = cpu_to_le16(1);
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if (nvdimm->unarmed) {
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nfit_memdev->flags |= cpu_to_le16(ACPI_NFIT_MEM_NOT_ARMED);
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}
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}
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/*
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* ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
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*/
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static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
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{
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NvdimmNfitControlRegion *nfit_dcr;
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int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
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NULL);
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uint32_t sn = nvdimm_slot_to_sn(slot);
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nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
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nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
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nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
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nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
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/* vendor: Intel. */
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nfit_dcr->vendor_id = cpu_to_le16(0x8086);
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nfit_dcr->device_id = cpu_to_le16(1);
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/* The _DSM method is following Intel's DSM specification. */
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nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
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in ACPI 6.0 is 1. */);
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nfit_dcr->serial_number = cpu_to_le32(sn);
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nfit_dcr->fic = cpu_to_le16(0x301 /* Format Interface Code:
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Byte addressable, no energy backed.
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See ACPI 6.2, sect 5.2.25.6 and
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JEDEC Annex L Release 3. */);
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}
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/*
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* ACPI 6.2 Errata A: 5.2.25.9 NVDIMM Platform Capabilities Structure
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*/
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static void
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nvdimm_build_structure_caps(GArray *structures, uint32_t capabilities)
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{
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NvdimmNfitPlatformCaps *nfit_caps;
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nfit_caps = acpi_data_push(structures, sizeof(*nfit_caps));
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nfit_caps->type = cpu_to_le16(7 /* NVDIMM Platform Capabilities */);
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nfit_caps->length = cpu_to_le16(sizeof(*nfit_caps));
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nfit_caps->highest_cap = 31 - clz32(capabilities);
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nfit_caps->capabilities = cpu_to_le32(capabilities);
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}
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static GArray *nvdimm_build_device_structure(NVDIMMState *state)
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{
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GSList *device_list, *list = nvdimm_get_device_list();
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GArray *structures = g_array_new(false, true /* clear */, 1);
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for (device_list = list; device_list; device_list = device_list->next) {
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DeviceState *dev = device_list->data;
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/* build System Physical Address Range Structure. */
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nvdimm_build_structure_spa(structures, dev);
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/*
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* build Memory Device to System Physical Address Range Mapping
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* Structure.
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*/
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nvdimm_build_structure_memdev(structures, dev);
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/* build NVDIMM Control Region Structure. */
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nvdimm_build_structure_dcr(structures, dev);
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}
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g_slist_free(list);
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if (state->persistence) {
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nvdimm_build_structure_caps(structures, state->persistence);
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}
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return structures;
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}
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static void nvdimm_init_fit_buffer(NvdimmFitBuffer *fit_buf)
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{
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fit_buf->fit = g_array_new(false, true /* clear */, 1);
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}
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static void nvdimm_build_fit_buffer(NVDIMMState *state)
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{
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NvdimmFitBuffer *fit_buf = &state->fit_buf;
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g_array_free(fit_buf->fit, true);
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fit_buf->fit = nvdimm_build_device_structure(state);
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fit_buf->dirty = true;
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}
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void nvdimm_plug(NVDIMMState *state)
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{
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nvdimm_build_fit_buffer(state);
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}
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/*
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* NVDIMM Firmware Interface Table
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* @signature: "NFIT"
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*
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* It provides information that allows OSPM to enumerate NVDIMM present in
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* the platform and associate system physical address ranges created by the
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* NVDIMMs.
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*
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* It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
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*/
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static void nvdimm_build_nfit(NVDIMMState *state, GArray *table_offsets,
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GArray *table_data, BIOSLinker *linker,
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const char *oem_id, const char *oem_table_id)
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{
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NvdimmFitBuffer *fit_buf = &state->fit_buf;
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AcpiTable table = { .sig = "NFIT", .rev = 1,
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.oem_id = oem_id, .oem_table_id = oem_table_id };
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acpi_add_table(table_offsets, table_data);
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acpi_table_begin(&table, table_data);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 4);
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/* NVDIMM device structures. */
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g_array_append_vals(table_data, fit_buf->fit->data, fit_buf->fit->len);
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acpi_table_end(linker, &table);
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}
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#define NVDIMM_DSM_MEMORY_SIZE 4096
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struct NvdimmDsmIn {
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uint32_t handle;
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uint32_t revision;
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uint32_t function;
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/* the remaining size in the page is used by arg3. */
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union {
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uint8_t arg3[4084];
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};
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} QEMU_PACKED;
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typedef struct NvdimmDsmIn NvdimmDsmIn;
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QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) != NVDIMM_DSM_MEMORY_SIZE);
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struct NvdimmDsmOut {
|
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/* the size of buffer filled by QEMU. */
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uint32_t len;
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uint8_t data[4092];
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} QEMU_PACKED;
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typedef struct NvdimmDsmOut NvdimmDsmOut;
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QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmOut) != NVDIMM_DSM_MEMORY_SIZE);
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struct NvdimmDsmFunc0Out {
|
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/* the size of buffer filled by QEMU. */
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uint32_t len;
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uint32_t supported_func;
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} QEMU_PACKED;
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typedef struct NvdimmDsmFunc0Out NvdimmDsmFunc0Out;
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struct NvdimmDsmFuncNoPayloadOut {
|
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/* the size of buffer filled by QEMU. */
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uint32_t len;
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uint32_t func_ret_status;
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} QEMU_PACKED;
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typedef struct NvdimmDsmFuncNoPayloadOut NvdimmDsmFuncNoPayloadOut;
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struct NvdimmFuncGetLabelSizeOut {
|
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/* the size of buffer filled by QEMU. */
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uint32_t len;
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uint32_t func_ret_status; /* return status code. */
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uint32_t label_size; /* the size of label data area. */
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/*
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* Maximum size of the namespace label data length supported by
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* the platform in Get/Set Namespace Label Data functions.
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*/
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uint32_t max_xfer;
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} QEMU_PACKED;
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typedef struct NvdimmFuncGetLabelSizeOut NvdimmFuncGetLabelSizeOut;
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QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelSizeOut) > NVDIMM_DSM_MEMORY_SIZE);
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|
|
struct NvdimmFuncGetLabelDataIn {
|
|
uint32_t offset; /* the offset in the namespace label data area. */
|
|
uint32_t length; /* the size of data is to be read via the function. */
|
|
} QEMU_PACKED;
|
|
typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn;
|
|
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) +
|
|
offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
struct NvdimmFuncGetLabelDataOut {
|
|
/* the size of buffer filled by QEMU. */
|
|
uint32_t len;
|
|
uint32_t func_ret_status; /* return status code. */
|
|
uint8_t out_buf[]; /* the data got via Get Namespace Label function. */
|
|
} QEMU_PACKED;
|
|
typedef struct NvdimmFuncGetLabelDataOut NvdimmFuncGetLabelDataOut;
|
|
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataOut) > NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
struct NvdimmFuncSetLabelDataIn {
|
|
uint32_t offset; /* the offset in the namespace label data area. */
|
|
uint32_t length; /* the size of data is to be written via the function. */
|
|
uint8_t in_buf[]; /* the data written to label data area. */
|
|
} QEMU_PACKED;
|
|
typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn;
|
|
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) +
|
|
offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
struct NvdimmFuncReadFITIn {
|
|
uint32_t offset; /* the offset into FIT buffer. */
|
|
} QEMU_PACKED;
|
|
typedef struct NvdimmFuncReadFITIn NvdimmFuncReadFITIn;
|
|
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITIn) +
|
|
offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
struct NvdimmFuncReadFITOut {
|
|
/* the size of buffer filled by QEMU. */
|
|
uint32_t len;
|
|
uint32_t func_ret_status; /* return status code. */
|
|
uint8_t fit[]; /* the FIT data. */
|
|
} QEMU_PACKED;
|
|
typedef struct NvdimmFuncReadFITOut NvdimmFuncReadFITOut;
|
|
QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITOut) > NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
static void
|
|
nvdimm_dsm_function0(uint32_t supported_func, hwaddr dsm_mem_addr)
|
|
{
|
|
NvdimmDsmFunc0Out func0 = {
|
|
.len = cpu_to_le32(sizeof(func0)),
|
|
.supported_func = cpu_to_le32(supported_func),
|
|
};
|
|
cpu_physical_memory_write(dsm_mem_addr, &func0, sizeof(func0));
|
|
}
|
|
|
|
static void
|
|
nvdimm_dsm_no_payload(uint32_t func_ret_status, hwaddr dsm_mem_addr)
|
|
{
|
|
NvdimmDsmFuncNoPayloadOut out = {
|
|
.len = cpu_to_le32(sizeof(out)),
|
|
.func_ret_status = cpu_to_le32(func_ret_status),
|
|
};
|
|
cpu_physical_memory_write(dsm_mem_addr, &out, sizeof(out));
|
|
}
|
|
|
|
#define NVDIMM_DSM_RET_STATUS_SUCCESS 0 /* Success */
|
|
#define NVDIMM_DSM_RET_STATUS_UNSUPPORT 1 /* Not Supported */
|
|
#define NVDIMM_DSM_RET_STATUS_NOMEMDEV 2 /* Non-Existing Memory Device */
|
|
#define NVDIMM_DSM_RET_STATUS_INVALID 3 /* Invalid Input Parameters */
|
|
#define NVDIMM_DSM_RET_STATUS_FIT_CHANGED 0x100 /* FIT Changed */
|
|
|
|
#define NVDIMM_QEMU_RSVD_HANDLE_ROOT 0x10000
|
|
|
|
/* Read FIT data, defined in docs/specs/acpi_nvdimm.txt. */
|
|
static void nvdimm_dsm_func_read_fit(NVDIMMState *state, NvdimmDsmIn *in,
|
|
hwaddr dsm_mem_addr)
|
|
{
|
|
NvdimmFitBuffer *fit_buf = &state->fit_buf;
|
|
NvdimmFuncReadFITIn *read_fit;
|
|
NvdimmFuncReadFITOut *read_fit_out;
|
|
GArray *fit;
|
|
uint32_t read_len = 0, func_ret_status;
|
|
int size;
|
|
|
|
read_fit = (NvdimmFuncReadFITIn *)in->arg3;
|
|
read_fit->offset = le32_to_cpu(read_fit->offset);
|
|
|
|
fit = fit_buf->fit;
|
|
|
|
trace_acpi_nvdimm_read_fit(read_fit->offset, fit->len,
|
|
fit_buf->dirty ? "Yes" : "No");
|
|
|
|
if (read_fit->offset > fit->len) {
|
|
func_ret_status = NVDIMM_DSM_RET_STATUS_INVALID;
|
|
goto exit;
|
|
}
|
|
|
|
/* It is the first time to read FIT. */
|
|
if (!read_fit->offset) {
|
|
fit_buf->dirty = false;
|
|
} else if (fit_buf->dirty) { /* FIT has been changed during RFIT. */
|
|
func_ret_status = NVDIMM_DSM_RET_STATUS_FIT_CHANGED;
|
|
goto exit;
|
|
}
|
|
|
|
func_ret_status = NVDIMM_DSM_RET_STATUS_SUCCESS;
|
|
read_len = MIN(fit->len - read_fit->offset,
|
|
NVDIMM_DSM_MEMORY_SIZE - sizeof(NvdimmFuncReadFITOut));
|
|
|
|
exit:
|
|
size = sizeof(NvdimmFuncReadFITOut) + read_len;
|
|
read_fit_out = g_malloc(size);
|
|
|
|
read_fit_out->len = cpu_to_le32(size);
|
|
read_fit_out->func_ret_status = cpu_to_le32(func_ret_status);
|
|
memcpy(read_fit_out->fit, fit->data + read_fit->offset, read_len);
|
|
|
|
cpu_physical_memory_write(dsm_mem_addr, read_fit_out, size);
|
|
|
|
g_free(read_fit_out);
|
|
}
|
|
|
|
static void
|
|
nvdimm_dsm_handle_reserved_root_method(NVDIMMState *state,
|
|
NvdimmDsmIn *in, hwaddr dsm_mem_addr)
|
|
{
|
|
switch (in->function) {
|
|
case 0x0:
|
|
nvdimm_dsm_function0(0x1 | 1 << 1 /* Read FIT */, dsm_mem_addr);
|
|
return;
|
|
case 0x1 /* Read FIT */:
|
|
nvdimm_dsm_func_read_fit(state, in, dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
|
|
}
|
|
|
|
static void nvdimm_dsm_root(NvdimmDsmIn *in, hwaddr dsm_mem_addr)
|
|
{
|
|
/*
|
|
* function 0 is called to inquire which functions are supported by
|
|
* OSPM
|
|
*/
|
|
if (!in->function) {
|
|
nvdimm_dsm_function0(0 /* No function supported other than
|
|
function 0 */, dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
/* No function except function 0 is supported yet. */
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
|
|
}
|
|
|
|
/*
|
|
* the max transfer size is the max size transferred by both a
|
|
* 'Get Namespace Label Data' function and a 'Set Namespace Label Data'
|
|
* function.
|
|
*/
|
|
static uint32_t nvdimm_get_max_xfer_label_size(void)
|
|
{
|
|
uint32_t max_get_size, max_set_size, dsm_memory_size;
|
|
|
|
dsm_memory_size = NVDIMM_DSM_MEMORY_SIZE;
|
|
|
|
/*
|
|
* the max data ACPI can read one time which is transferred by
|
|
* the response of 'Get Namespace Label Data' function.
|
|
*/
|
|
max_get_size = dsm_memory_size - sizeof(NvdimmFuncGetLabelDataOut);
|
|
|
|
/*
|
|
* the max data ACPI can write one time which is transferred by
|
|
* 'Set Namespace Label Data' function.
|
|
*/
|
|
max_set_size = dsm_memory_size - offsetof(NvdimmDsmIn, arg3) -
|
|
sizeof(NvdimmFuncSetLabelDataIn);
|
|
|
|
return MIN(max_get_size, max_set_size);
|
|
}
|
|
|
|
/*
|
|
* DSM Spec Rev1 4.4 Get Namespace Label Size (Function Index 4).
|
|
*
|
|
* It gets the size of Namespace Label data area and the max data size
|
|
* that Get/Set Namespace Label Data functions can transfer.
|
|
*/
|
|
static void nvdimm_dsm_label_size(NVDIMMDevice *nvdimm, hwaddr dsm_mem_addr)
|
|
{
|
|
NvdimmFuncGetLabelSizeOut label_size_out = {
|
|
.len = cpu_to_le32(sizeof(label_size_out)),
|
|
};
|
|
uint32_t label_size, mxfer;
|
|
|
|
label_size = nvdimm->label_size;
|
|
mxfer = nvdimm_get_max_xfer_label_size();
|
|
|
|
trace_acpi_nvdimm_label_info(label_size, mxfer);
|
|
|
|
label_size_out.func_ret_status = cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
|
|
label_size_out.label_size = cpu_to_le32(label_size);
|
|
label_size_out.max_xfer = cpu_to_le32(mxfer);
|
|
|
|
cpu_physical_memory_write(dsm_mem_addr, &label_size_out,
|
|
sizeof(label_size_out));
|
|
}
|
|
|
|
static uint32_t nvdimm_rw_label_data_check(NVDIMMDevice *nvdimm,
|
|
uint32_t offset, uint32_t length)
|
|
{
|
|
uint32_t ret = NVDIMM_DSM_RET_STATUS_INVALID;
|
|
|
|
if (offset + length < offset) {
|
|
trace_acpi_nvdimm_label_overflow(offset, length);
|
|
return ret;
|
|
}
|
|
|
|
if (nvdimm->label_size < offset + length) {
|
|
trace_acpi_nvdimm_label_oversize(offset + length, nvdimm->label_size);
|
|
return ret;
|
|
}
|
|
|
|
if (length > nvdimm_get_max_xfer_label_size()) {
|
|
trace_acpi_nvdimm_label_xfer_exceed(length,
|
|
nvdimm_get_max_xfer_label_size());
|
|
return ret;
|
|
}
|
|
|
|
return NVDIMM_DSM_RET_STATUS_SUCCESS;
|
|
}
|
|
|
|
/*
|
|
* DSM Spec Rev1 4.5 Get Namespace Label Data (Function Index 5).
|
|
*/
|
|
static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in,
|
|
hwaddr dsm_mem_addr)
|
|
{
|
|
NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm);
|
|
NvdimmFuncGetLabelDataIn *get_label_data;
|
|
NvdimmFuncGetLabelDataOut *get_label_data_out;
|
|
uint32_t status;
|
|
int size;
|
|
|
|
get_label_data = (NvdimmFuncGetLabelDataIn *)in->arg3;
|
|
get_label_data->offset = le32_to_cpu(get_label_data->offset);
|
|
get_label_data->length = le32_to_cpu(get_label_data->length);
|
|
|
|
trace_acpi_nvdimm_read_label(get_label_data->offset,
|
|
get_label_data->length);
|
|
|
|
status = nvdimm_rw_label_data_check(nvdimm, get_label_data->offset,
|
|
get_label_data->length);
|
|
if (status != NVDIMM_DSM_RET_STATUS_SUCCESS) {
|
|
nvdimm_dsm_no_payload(status, dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
size = sizeof(*get_label_data_out) + get_label_data->length;
|
|
assert(size <= NVDIMM_DSM_MEMORY_SIZE);
|
|
get_label_data_out = g_malloc(size);
|
|
|
|
get_label_data_out->len = cpu_to_le32(size);
|
|
get_label_data_out->func_ret_status =
|
|
cpu_to_le32(NVDIMM_DSM_RET_STATUS_SUCCESS);
|
|
nvc->read_label_data(nvdimm, get_label_data_out->out_buf,
|
|
get_label_data->length, get_label_data->offset);
|
|
|
|
cpu_physical_memory_write(dsm_mem_addr, get_label_data_out, size);
|
|
g_free(get_label_data_out);
|
|
}
|
|
|
|
/*
|
|
* DSM Spec Rev1 4.6 Set Namespace Label Data (Function Index 6).
|
|
*/
|
|
static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *in,
|
|
hwaddr dsm_mem_addr)
|
|
{
|
|
NVDIMMClass *nvc = NVDIMM_GET_CLASS(nvdimm);
|
|
NvdimmFuncSetLabelDataIn *set_label_data;
|
|
uint32_t status;
|
|
|
|
set_label_data = (NvdimmFuncSetLabelDataIn *)in->arg3;
|
|
|
|
set_label_data->offset = le32_to_cpu(set_label_data->offset);
|
|
set_label_data->length = le32_to_cpu(set_label_data->length);
|
|
|
|
trace_acpi_nvdimm_write_label(set_label_data->offset,
|
|
set_label_data->length);
|
|
|
|
status = nvdimm_rw_label_data_check(nvdimm, set_label_data->offset,
|
|
set_label_data->length);
|
|
if (status != NVDIMM_DSM_RET_STATUS_SUCCESS) {
|
|
nvdimm_dsm_no_payload(status, dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
assert(offsetof(NvdimmDsmIn, arg3) + sizeof(*set_label_data) +
|
|
set_label_data->length <= NVDIMM_DSM_MEMORY_SIZE);
|
|
|
|
nvc->write_label_data(nvdimm, set_label_data->in_buf,
|
|
set_label_data->length, set_label_data->offset);
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_SUCCESS, dsm_mem_addr);
|
|
}
|
|
|
|
static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr)
|
|
{
|
|
NVDIMMDevice *nvdimm = nvdimm_get_device_by_handle(in->handle);
|
|
|
|
/* See the comments in nvdimm_dsm_root(). */
|
|
if (!in->function) {
|
|
uint32_t supported_func = 0;
|
|
|
|
if (nvdimm && nvdimm->label_size) {
|
|
supported_func |= 0x1 /* Bit 0 indicates whether there is
|
|
support for any functions other
|
|
than function 0. */ |
|
|
1 << 4 /* Get Namespace Label Size */ |
|
|
1 << 5 /* Get Namespace Label Data */ |
|
|
1 << 6 /* Set Namespace Label Data */;
|
|
}
|
|
nvdimm_dsm_function0(supported_func, dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
if (!nvdimm) {
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_NOMEMDEV,
|
|
dsm_mem_addr);
|
|
return;
|
|
}
|
|
|
|
/* Encode DSM function according to DSM Spec Rev1. */
|
|
switch (in->function) {
|
|
case 4 /* Get Namespace Label Size */:
|
|
if (nvdimm->label_size) {
|
|
nvdimm_dsm_label_size(nvdimm, dsm_mem_addr);
|
|
return;
|
|
}
|
|
break;
|
|
case 5 /* Get Namespace Label Data */:
|
|
if (nvdimm->label_size) {
|
|
nvdimm_dsm_get_label_data(nvdimm, in, dsm_mem_addr);
|
|
return;
|
|
}
|
|
break;
|
|
case 0x6 /* Set Namespace Label Data */:
|
|
if (nvdimm->label_size) {
|
|
nvdimm_dsm_set_label_data(nvdimm, in, dsm_mem_addr);
|
|
return;
|
|
}
|
|
break;
|
|
}
|
|
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
|
|
}
|
|
|
|
static uint64_t
|
|
nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
trace_acpi_nvdimm_read_io_port();
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
|
|
{
|
|
NVDIMMState *state = opaque;
|
|
NvdimmDsmIn *in;
|
|
hwaddr dsm_mem_addr = val;
|
|
|
|
trace_acpi_nvdimm_dsm_mem_addr(dsm_mem_addr);
|
|
|
|
/*
|
|
* The DSM memory is mapped to guest address space so an evil guest
|
|
* can change its content while we are doing DSM emulation. Avoid
|
|
* this by copying DSM memory to QEMU local memory.
|
|
*/
|
|
in = g_new(NvdimmDsmIn, 1);
|
|
cpu_physical_memory_read(dsm_mem_addr, in, sizeof(*in));
|
|
|
|
in->revision = le32_to_cpu(in->revision);
|
|
in->function = le32_to_cpu(in->function);
|
|
in->handle = le32_to_cpu(in->handle);
|
|
|
|
trace_acpi_nvdimm_dsm_info(in->revision, in->handle, in->function);
|
|
|
|
if (in->revision != 0x1 /* Currently we only support DSM Spec Rev1. */) {
|
|
trace_acpi_nvdimm_invalid_revision(in->revision);
|
|
nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_addr);
|
|
goto exit;
|
|
}
|
|
|
|
if (in->handle == NVDIMM_QEMU_RSVD_HANDLE_ROOT) {
|
|
nvdimm_dsm_handle_reserved_root_method(state, in, dsm_mem_addr);
|
|
goto exit;
|
|
}
|
|
|
|
/* Handle 0 is reserved for NVDIMM Root Device. */
|
|
if (!in->handle) {
|
|
nvdimm_dsm_root(in, dsm_mem_addr);
|
|
goto exit;
|
|
}
|
|
|
|
nvdimm_dsm_device(in, dsm_mem_addr);
|
|
|
|
exit:
|
|
g_free(in);
|
|
}
|
|
|
|
static const MemoryRegionOps nvdimm_dsm_ops = {
|
|
.read = nvdimm_dsm_read,
|
|
.write = nvdimm_dsm_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 4,
|
|
},
|
|
};
|
|
|
|
void nvdimm_acpi_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev)
|
|
{
|
|
if (dev->hotplugged) {
|
|
acpi_send_event(DEVICE(hotplug_dev), ACPI_NVDIMM_HOTPLUG_STATUS);
|
|
}
|
|
}
|
|
|
|
void nvdimm_init_acpi_state(NVDIMMState *state, MemoryRegion *io,
|
|
struct AcpiGenericAddress dsm_io,
|
|
FWCfgState *fw_cfg, Object *owner)
|
|
{
|
|
state->dsm_io = dsm_io;
|
|
memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state,
|
|
"nvdimm-acpi-io", dsm_io.bit_width >> 3);
|
|
memory_region_add_subregion(io, dsm_io.address, &state->io_mr);
|
|
|
|
state->dsm_mem = g_array_new(false, true /* clear */, 1);
|
|
acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn));
|
|
fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data,
|
|
state->dsm_mem->len);
|
|
|
|
nvdimm_init_fit_buffer(&state->fit_buf);
|
|
}
|
|
|
|
#define NVDIMM_COMMON_DSM "NCAL"
|
|
#define NVDIMM_ACPI_MEM_ADDR "MEMA"
|
|
|
|
#define NVDIMM_DSM_MEMORY "NRAM"
|
|
#define NVDIMM_DSM_IOPORT "NPIO"
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#define NVDIMM_DSM_NOTIFY "NTFI"
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#define NVDIMM_DSM_HANDLE "HDLE"
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#define NVDIMM_DSM_REVISION "REVS"
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#define NVDIMM_DSM_FUNCTION "FUNC"
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#define NVDIMM_DSM_ARG3 "FARG"
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#define NVDIMM_DSM_OUT_BUF_SIZE "RLEN"
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#define NVDIMM_DSM_OUT_BUF "ODAT"
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#define NVDIMM_DSM_RFIT_STATUS "RSTA"
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#define NVDIMM_QEMU_RSVD_UUID "648B9CF2-CDA1-4312-8AD9-49C4AF32BD62"
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#define NVDIMM_DEVICE_DSM_UUID "4309AC30-0D11-11E4-9191-0800200C9A66"
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static void nvdimm_build_common_dsm(Aml *dev,
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NVDIMMState *nvdimm_state)
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{
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Aml *method, *ifctx, *function, *handle, *uuid, *dsm_mem, *elsectx2;
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Aml *elsectx, *unsupport, *unpatched, *expected_uuid, *uuid_invalid;
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Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_size;
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Aml *whilectx, *offset;
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uint8_t byte_list[1];
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AmlRegionSpace rs;
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method = aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED);
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uuid = aml_arg(0);
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function = aml_arg(2);
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handle = aml_arg(4);
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dsm_mem = aml_local(6);
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dsm_out_buf = aml_local(7);
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aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem));
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if (nvdimm_state->dsm_io.space_id == AML_AS_SYSTEM_IO) {
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rs = AML_SYSTEM_IO;
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} else {
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rs = AML_SYSTEM_MEMORY;
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}
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/* map DSM memory and IO into ACPI namespace. */
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aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs,
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aml_int(nvdimm_state->dsm_io.address),
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nvdimm_state->dsm_io.bit_width >> 3));
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aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY,
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AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn)));
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/*
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* DSM notifier:
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* NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU to
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* emulate the access.
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*
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* It is the IO port so that accessing them will cause VM-exit, the
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* control will be transferred to QEMU.
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*/
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field = aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK,
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AML_PRESERVE);
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aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY,
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nvdimm_state->dsm_io.bit_width));
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aml_append(method, field);
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/*
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* DSM input:
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* NVDIMM_DSM_HANDLE: store device's handle, it's zero if the _DSM call
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* happens on NVDIMM Root Device.
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* NVDIMM_DSM_REVISION: store the Arg1 of _DSM call.
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* NVDIMM_DSM_FUNCTION: store the Arg2 of _DSM call.
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* NVDIMM_DSM_ARG3: store the Arg3 of _DSM call which is a Package
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* containing function-specific arguments.
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*
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* They are RAM mapping on host so that these accesses never cause
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* VM-EXIT.
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*/
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field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
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AML_PRESERVE);
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aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE,
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sizeof(typeof_field(NvdimmDsmIn, handle)) * BITS_PER_BYTE));
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aml_append(field, aml_named_field(NVDIMM_DSM_REVISION,
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sizeof(typeof_field(NvdimmDsmIn, revision)) * BITS_PER_BYTE));
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aml_append(field, aml_named_field(NVDIMM_DSM_FUNCTION,
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sizeof(typeof_field(NvdimmDsmIn, function)) * BITS_PER_BYTE));
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aml_append(field, aml_named_field(NVDIMM_DSM_ARG3,
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(sizeof(NvdimmDsmIn) - offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BYTE));
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aml_append(method, field);
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/*
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* DSM output:
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* NVDIMM_DSM_OUT_BUF_SIZE: the size of the buffer filled by QEMU.
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* NVDIMM_DSM_OUT_BUF: the buffer QEMU uses to store the result.
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*
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* Since the page is reused by both input and out, the input data
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* will be lost after storing new result into ODAT so we should fetch
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* all the input data before writing the result.
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*/
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field = aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK,
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AML_PRESERVE);
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aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE,
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sizeof(typeof_field(NvdimmDsmOut, len)) * BITS_PER_BYTE));
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aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF,
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(sizeof(NvdimmDsmOut) - offsetof(NvdimmDsmOut, data)) * BITS_PER_BYTE));
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aml_append(method, field);
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/*
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* do not support any method if DSM memory address has not been
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* patched.
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*/
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unpatched = aml_equal(dsm_mem, aml_int(0x0));
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expected_uuid = aml_local(0);
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ifctx = aml_if(aml_equal(handle, aml_int(0x0)));
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aml_append(ifctx, aml_store(
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aml_touuid("2F10E7A4-9E91-11E4-89D3-123B93F75CBA")
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/* UUID for NVDIMM Root Device */, expected_uuid));
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aml_append(method, ifctx);
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elsectx = aml_else();
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ifctx = aml_if(aml_equal(handle, aml_int(NVDIMM_QEMU_RSVD_HANDLE_ROOT)));
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aml_append(ifctx, aml_store(aml_touuid(NVDIMM_QEMU_RSVD_UUID
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/* UUID for QEMU internal use */), expected_uuid));
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aml_append(elsectx, ifctx);
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elsectx2 = aml_else();
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aml_append(elsectx2, aml_store(aml_touuid(NVDIMM_DEVICE_DSM_UUID)
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/* UUID for NVDIMM Devices */, expected_uuid));
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aml_append(elsectx, elsectx2);
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aml_append(method, elsectx);
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uuid_invalid = aml_lnot(aml_equal(uuid, expected_uuid));
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unsupport = aml_if(aml_lor(unpatched, uuid_invalid));
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/*
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* function 0 is called to inquire what functions are supported by
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* OSPM
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*/
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ifctx = aml_if(aml_equal(function, aml_int(0)));
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byte_list[0] = 0 /* No function Supported */;
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aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
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aml_append(unsupport, ifctx);
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/* No function is supported yet. */
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byte_list[0] = NVDIMM_DSM_RET_STATUS_UNSUPPORT;
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aml_append(unsupport, aml_return(aml_buffer(1, byte_list)));
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aml_append(method, unsupport);
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/*
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* The HDLE indicates the DSM function is issued from which device,
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* it reserves 0 for root device and is the handle for NVDIMM devices.
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* See the comments in nvdimm_slot_to_handle().
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*/
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aml_append(method, aml_store(handle, aml_name(NVDIMM_DSM_HANDLE)));
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aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_REVISION)));
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aml_append(method, aml_store(function, aml_name(NVDIMM_DSM_FUNCTION)));
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/*
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* The fourth parameter (Arg3) of _DSM is a package which contains
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* a buffer, the layout of the buffer is specified by UUID (Arg0),
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* Revision ID (Arg1) and Function Index (Arg2) which are documented
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* in the DSM Spec.
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*/
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pckg = aml_arg(3);
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ifctx = aml_if(aml_land(aml_equal(aml_object_type(pckg),
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aml_int(4 /* Package */)) /* It is a Package? */,
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aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */));
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pckg_index = aml_local(2);
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pckg_buf = aml_local(3);
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aml_append(ifctx, aml_store(aml_index(pckg, aml_int(0)), pckg_index));
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aml_append(ifctx, aml_store(aml_derefof(pckg_index), pckg_buf));
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aml_append(ifctx, aml_store(pckg_buf, aml_name(NVDIMM_DSM_ARG3)));
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aml_append(method, ifctx);
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/*
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* tell QEMU about the real address of DSM memory, then QEMU
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* gets the control and fills the result in DSM memory.
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*/
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aml_append(method, aml_store(dsm_mem, aml_name(NVDIMM_DSM_NOTIFY)));
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dsm_out_buf_size = aml_local(1);
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/* RLEN is not included in the payload returned to guest. */
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aml_append(method, aml_subtract(aml_name(NVDIMM_DSM_OUT_BUF_SIZE),
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aml_int(4), dsm_out_buf_size));
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/*
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* As per ACPI spec 6.3, Table 19-419 Object Conversion Rules, if
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* the Buffer Field <= to the size of an Integer (in bits), it will
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* be treated as an integer. Moreover, the integer size depends on
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* DSDT tables revision number. If revision number is < 2, integer
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* size is 32 bits, otherwise it is 64 bits.
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* Because of this CreateField() canot be used if RLEN < Integer Size.
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*
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* Also please note that APCI ASL operator SizeOf() doesn't support
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* Integer and there isn't any other way to figure out the Integer
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* size. Hence we assume 8 byte as Integer size and if RLEN < 8 bytes,
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* build dsm_out_buf byte by byte.
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*/
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ifctx = aml_if(aml_lless(dsm_out_buf_size, aml_int(8)));
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offset = aml_local(2);
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aml_append(ifctx, aml_store(aml_int(0), offset));
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aml_append(ifctx, aml_name_decl("TBUF", aml_buffer(1, NULL)));
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aml_append(ifctx, aml_store(aml_buffer(0, NULL), dsm_out_buf));
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whilectx = aml_while(aml_lless(offset, dsm_out_buf_size));
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/* Copy 1 byte at offset from ODAT to temporary buffer(TBUF). */
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aml_append(whilectx, aml_store(aml_derefof(aml_index(
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aml_name(NVDIMM_DSM_OUT_BUF), offset)),
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aml_index(aml_name("TBUF"), aml_int(0))));
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aml_append(whilectx, aml_concatenate(dsm_out_buf, aml_name("TBUF"),
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dsm_out_buf));
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aml_append(whilectx, aml_increment(offset));
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aml_append(ifctx, whilectx);
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aml_append(ifctx, aml_return(dsm_out_buf));
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aml_append(method, ifctx);
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/* If RLEN >= Integer size, just use CreateField() operator */
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aml_append(method, aml_store(aml_shiftleft(dsm_out_buf_size, aml_int(3)),
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dsm_out_buf_size));
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aml_append(method, aml_create_field(aml_name(NVDIMM_DSM_OUT_BUF),
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aml_int(0), dsm_out_buf_size, "OBUF"));
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aml_append(method, aml_return(aml_name("OBUF")));
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aml_append(dev, method);
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}
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static void nvdimm_build_device_dsm(Aml *dev, uint32_t handle)
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{
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Aml *method;
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method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_call5(NVDIMM_COMMON_DSM, aml_arg(0),
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aml_arg(1), aml_arg(2), aml_arg(3),
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aml_int(handle))));
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aml_append(dev, method);
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}
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static void nvdimm_build_fit(Aml *dev)
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{
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Aml *method, *pkg, *buf, *buf_size, *offset, *call_result;
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Aml *whilectx, *ifcond, *ifctx, *elsectx, *fit;
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buf = aml_local(0);
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buf_size = aml_local(1);
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fit = aml_local(2);
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aml_append(dev, aml_name_decl(NVDIMM_DSM_RFIT_STATUS, aml_int(0)));
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/* build helper function, RFIT. */
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method = aml_method("RFIT", 1, AML_SERIALIZED);
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aml_append(method, aml_name_decl("OFST", aml_int(0)));
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/* prepare input package. */
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pkg = aml_package(1);
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aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
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aml_append(pkg, aml_name("OFST"));
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/* call Read_FIT function. */
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call_result = aml_call5(NVDIMM_COMMON_DSM,
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aml_touuid(NVDIMM_QEMU_RSVD_UUID),
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aml_int(1) /* Revision 1 */,
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aml_int(0x1) /* Read FIT */,
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pkg, aml_int(NVDIMM_QEMU_RSVD_HANDLE_ROOT));
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aml_append(method, aml_store(call_result, buf));
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/* handle _DSM result. */
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aml_append(method, aml_create_dword_field(buf,
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aml_int(0) /* offset at byte 0 */, "STAU"));
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aml_append(method, aml_store(aml_name("STAU"),
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aml_name(NVDIMM_DSM_RFIT_STATUS)));
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/* if something is wrong during _DSM. */
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ifcond = aml_equal(aml_int(NVDIMM_DSM_RET_STATUS_SUCCESS),
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aml_name("STAU"));
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ifctx = aml_if(aml_lnot(ifcond));
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aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
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aml_append(method, ifctx);
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aml_append(method, aml_store(aml_sizeof(buf), buf_size));
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aml_append(method, aml_subtract(buf_size,
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aml_int(4) /* the size of "STAU" */,
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buf_size));
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/* if we read the end of fit. */
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ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
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aml_append(ifctx, aml_return(aml_buffer(0, NULL)));
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aml_append(method, ifctx);
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aml_append(method, aml_create_field(buf,
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aml_int(4 * BITS_PER_BYTE), /* offset at byte 4.*/
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aml_shiftleft(buf_size, aml_int(3)), "BUFF"));
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aml_append(method, aml_return(aml_name("BUFF")));
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aml_append(dev, method);
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/* build _FIT. */
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method = aml_method("_FIT", 0, AML_SERIALIZED);
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offset = aml_local(3);
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aml_append(method, aml_store(aml_buffer(0, NULL), fit));
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aml_append(method, aml_store(aml_int(0), offset));
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whilectx = aml_while(aml_int(1));
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aml_append(whilectx, aml_store(aml_call1("RFIT", offset), buf));
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aml_append(whilectx, aml_store(aml_sizeof(buf), buf_size));
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/*
|
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* if fit buffer was changed during RFIT, read from the beginning
|
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* again.
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*/
|
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ifctx = aml_if(aml_equal(aml_name(NVDIMM_DSM_RFIT_STATUS),
|
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aml_int(NVDIMM_DSM_RET_STATUS_FIT_CHANGED)));
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aml_append(ifctx, aml_store(aml_buffer(0, NULL), fit));
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aml_append(ifctx, aml_store(aml_int(0), offset));
|
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aml_append(whilectx, ifctx);
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|
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elsectx = aml_else();
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|
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/* finish fit read if no data is read out. */
|
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ifctx = aml_if(aml_equal(buf_size, aml_int(0)));
|
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aml_append(ifctx, aml_return(fit));
|
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aml_append(elsectx, ifctx);
|
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|
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/* update the offset. */
|
|
aml_append(elsectx, aml_add(offset, buf_size, offset));
|
|
/* append the data we read out to the fit buffer. */
|
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aml_append(elsectx, aml_concatenate(fit, buf, fit));
|
|
aml_append(whilectx, elsectx);
|
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aml_append(method, whilectx);
|
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|
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aml_append(dev, method);
|
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}
|
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|
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static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots)
|
|
{
|
|
uint32_t slot;
|
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Aml *method, *pkg, *field, *com_call;
|
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|
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for (slot = 0; slot < ram_slots; slot++) {
|
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uint32_t handle = nvdimm_slot_to_handle(slot);
|
|
Aml *nvdimm_dev;
|
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|
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nvdimm_dev = aml_device("NV%02X", slot);
|
|
|
|
/*
|
|
* ACPI 6.0: 9.20 NVDIMM Devices:
|
|
*
|
|
* _ADR object that is used to supply OSPM with unique address
|
|
* of the NVDIMM device. This is done by returning the NFIT Device
|
|
* handle that is used to identify the associated entries in ACPI
|
|
* table NFIT or _FIT.
|
|
*/
|
|
aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
|
|
|
|
/*
|
|
* ACPI v6.4: Section 6.5.10 NVDIMM Label Methods
|
|
*/
|
|
/* _LSI */
|
|
method = aml_method("_LSI", 0, AML_SERIALIZED);
|
|
com_call = aml_call5(NVDIMM_COMMON_DSM,
|
|
aml_touuid(NVDIMM_DEVICE_DSM_UUID),
|
|
aml_int(1), aml_int(4), aml_int(0),
|
|
aml_int(handle));
|
|
aml_append(method, aml_store(com_call, aml_local(0)));
|
|
|
|
aml_append(method, aml_create_dword_field(aml_local(0),
|
|
aml_int(0), "STTS"));
|
|
aml_append(method, aml_create_dword_field(aml_local(0), aml_int(4),
|
|
"SLSA"));
|
|
aml_append(method, aml_create_dword_field(aml_local(0), aml_int(8),
|
|
"MAXT"));
|
|
|
|
pkg = aml_package(3);
|
|
aml_append(pkg, aml_name("STTS"));
|
|
aml_append(pkg, aml_name("SLSA"));
|
|
aml_append(pkg, aml_name("MAXT"));
|
|
aml_append(method, aml_store(pkg, aml_local(1)));
|
|
aml_append(method, aml_return(aml_local(1)));
|
|
|
|
aml_append(nvdimm_dev, method);
|
|
|
|
/* _LSR */
|
|
method = aml_method("_LSR", 2, AML_SERIALIZED);
|
|
aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL)));
|
|
|
|
aml_append(method, aml_create_dword_field(aml_name("INPT"),
|
|
aml_int(0), "OFST"));
|
|
aml_append(method, aml_create_dword_field(aml_name("INPT"),
|
|
aml_int(4), "LEN"));
|
|
aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
|
|
aml_append(method, aml_store(aml_arg(1), aml_name("LEN")));
|
|
|
|
pkg = aml_package(1);
|
|
aml_append(pkg, aml_name("INPT"));
|
|
aml_append(method, aml_store(pkg, aml_local(0)));
|
|
|
|
com_call = aml_call5(NVDIMM_COMMON_DSM,
|
|
aml_touuid(NVDIMM_DEVICE_DSM_UUID),
|
|
aml_int(1), aml_int(5), aml_local(0),
|
|
aml_int(handle));
|
|
aml_append(method, aml_store(com_call, aml_local(3)));
|
|
field = aml_create_dword_field(aml_local(3), aml_int(0), "STTS");
|
|
aml_append(method, field);
|
|
field = aml_create_field(aml_local(3), aml_int(32),
|
|
aml_shiftleft(aml_name("LEN"), aml_int(3)),
|
|
"LDAT");
|
|
aml_append(method, field);
|
|
aml_append(method, aml_name_decl("LSA", aml_buffer(0, NULL)));
|
|
aml_append(method, aml_to_buffer(aml_name("LDAT"), aml_name("LSA")));
|
|
|
|
pkg = aml_package(2);
|
|
aml_append(pkg, aml_name("STTS"));
|
|
aml_append(pkg, aml_name("LSA"));
|
|
|
|
aml_append(method, aml_store(pkg, aml_local(1)));
|
|
aml_append(method, aml_return(aml_local(1)));
|
|
|
|
aml_append(nvdimm_dev, method);
|
|
|
|
/* _LSW */
|
|
method = aml_method("_LSW", 3, AML_SERIALIZED);
|
|
aml_append(method, aml_store(aml_arg(2), aml_local(2)));
|
|
aml_append(method, aml_name_decl("INPT", aml_buffer(8, NULL)));
|
|
field = aml_create_dword_field(aml_name("INPT"),
|
|
aml_int(0), "OFST");
|
|
aml_append(method, field);
|
|
field = aml_create_dword_field(aml_name("INPT"),
|
|
aml_int(4), "TLEN");
|
|
aml_append(method, field);
|
|
aml_append(method, aml_store(aml_arg(0), aml_name("OFST")));
|
|
aml_append(method, aml_store(aml_arg(1), aml_name("TLEN")));
|
|
|
|
aml_append(method, aml_concatenate(aml_name("INPT"), aml_local(2),
|
|
aml_name("INPT")));
|
|
pkg = aml_package(1);
|
|
aml_append(pkg, aml_name("INPT"));
|
|
aml_append(method, aml_store(pkg, aml_local(0)));
|
|
com_call = aml_call5(NVDIMM_COMMON_DSM,
|
|
aml_touuid(NVDIMM_DEVICE_DSM_UUID),
|
|
aml_int(1), aml_int(6), aml_local(0),
|
|
aml_int(handle));
|
|
aml_append(method, aml_store(com_call, aml_local(3)));
|
|
field = aml_create_dword_field(aml_local(3), aml_int(0), "STTS");
|
|
aml_append(method, field);
|
|
aml_append(method, aml_return(aml_name("STTS")));
|
|
|
|
aml_append(nvdimm_dev, method);
|
|
|
|
nvdimm_build_device_dsm(nvdimm_dev, handle);
|
|
aml_append(root_dev, nvdimm_dev);
|
|
}
|
|
}
|
|
|
|
static void nvdimm_build_ssdt(GArray *table_offsets, GArray *table_data,
|
|
BIOSLinker *linker,
|
|
NVDIMMState *nvdimm_state,
|
|
uint32_t ram_slots, const char *oem_id)
|
|
{
|
|
int mem_addr_offset;
|
|
Aml *ssdt, *sb_scope, *dev;
|
|
AcpiTable table = { .sig = "SSDT", .rev = 1,
|
|
.oem_id = oem_id, .oem_table_id = "NVDIMM" };
|
|
|
|
acpi_add_table(table_offsets, table_data);
|
|
|
|
acpi_table_begin(&table, table_data);
|
|
ssdt = init_aml_allocator();
|
|
sb_scope = aml_scope("\\_SB");
|
|
|
|
dev = aml_device("NVDR");
|
|
|
|
/*
|
|
* ACPI 6.0: 9.20 NVDIMM Devices:
|
|
*
|
|
* The ACPI Name Space device uses _HID of ACPI0012 to identify the root
|
|
* NVDIMM interface device. Platform firmware is required to contain one
|
|
* such device in _SB scope if NVDIMMs support is exposed by platform to
|
|
* OSPM.
|
|
* For each NVDIMM present or intended to be supported by platform,
|
|
* platform firmware also exposes an ACPI Namespace Device under the
|
|
* root device.
|
|
*/
|
|
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
|
|
|
|
nvdimm_build_common_dsm(dev, nvdimm_state);
|
|
|
|
/* 0 is reserved for root device. */
|
|
nvdimm_build_device_dsm(dev, 0);
|
|
nvdimm_build_fit(dev);
|
|
|
|
nvdimm_build_nvdimm_devices(dev, ram_slots);
|
|
|
|
aml_append(sb_scope, dev);
|
|
aml_append(ssdt, sb_scope);
|
|
|
|
/* copy AML table into ACPI tables blob and patch header there */
|
|
g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
|
|
mem_addr_offset = build_append_named_dword(table_data,
|
|
NVDIMM_ACPI_MEM_ADDR);
|
|
|
|
bios_linker_loader_alloc(linker,
|
|
NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem,
|
|
sizeof(NvdimmDsmIn), false /* high memory */);
|
|
bios_linker_loader_add_pointer(linker,
|
|
ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t),
|
|
NVDIMM_DSM_MEM_FILE, 0);
|
|
free_aml_allocator();
|
|
/*
|
|
* must be executed as the last so that pointer patching command above
|
|
* would be executed by guest before it recalculated checksum which were
|
|
* scheduled by acpi_table_end()
|
|
*/
|
|
acpi_table_end(linker, &table);
|
|
}
|
|
|
|
void nvdimm_build_srat(GArray *table_data)
|
|
{
|
|
GSList *device_list, *list = nvdimm_get_device_list();
|
|
|
|
for (device_list = list; device_list; device_list = device_list->next) {
|
|
DeviceState *dev = device_list->data;
|
|
Object *obj = OBJECT(dev);
|
|
uint64_t addr, size;
|
|
int node;
|
|
|
|
node = object_property_get_int(obj, PC_DIMM_NODE_PROP, &error_abort);
|
|
addr = object_property_get_uint(obj, PC_DIMM_ADDR_PROP, &error_abort);
|
|
size = object_property_get_uint(obj, PC_DIMM_SIZE_PROP, &error_abort);
|
|
|
|
build_srat_memory(table_data, addr, size, node,
|
|
MEM_AFFINITY_ENABLED | MEM_AFFINITY_NON_VOLATILE);
|
|
}
|
|
g_slist_free(list);
|
|
}
|
|
|
|
void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
|
|
BIOSLinker *linker, NVDIMMState *state,
|
|
uint32_t ram_slots, const char *oem_id,
|
|
const char *oem_table_id)
|
|
{
|
|
GSList *device_list;
|
|
|
|
/* no nvdimm device can be plugged. */
|
|
if (!ram_slots) {
|
|
return;
|
|
}
|
|
|
|
nvdimm_build_ssdt(table_offsets, table_data, linker, state,
|
|
ram_slots, oem_id);
|
|
|
|
device_list = nvdimm_get_device_list();
|
|
/* no NVDIMM device is plugged. */
|
|
if (!device_list) {
|
|
return;
|
|
}
|
|
|
|
nvdimm_build_nfit(state, table_offsets, table_data, linker,
|
|
oem_id, oem_table_id);
|
|
g_slist_free(device_list);
|
|
}
|