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90 lines
3.6 KiB
Plaintext
90 lines
3.6 KiB
Plaintext
BYPASS IOMMU PROPERTY
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=====================
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Description
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===========
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Traditionally, there is a global switch to enable/disable vIOMMU. All
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devices in the system can only support go through vIOMMU or not, which
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is not flexible. We introduce this bypass iommu property to support
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coexist of devices go through vIOMMU and devices not. This is useful to
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passthrough devices with no-iommu mode and devices go through vIOMMU in
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the same virtual machine.
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PCI host bridges have a bypass_iommu property. This property is used to
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determine whether the devices attached on the PCI host bridge will bypass
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virtual iommu. The bypass_iommu property is valid only when there is a
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virtual iommu in the system, it is implemented to allow some devices to
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bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
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the attached devices will go through vIOMMU by default.
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Usage
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=====
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The bypass iommu feature support PXB host bridge and default main host
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bridge, we add a bypass_iommu property for PXB and default_bus_bypass_iommu
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for machine. Note that default_bus_bypass_iommu is available only when
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the 'q35' machine type on x86 architecture and the 'virt' machine type
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on AArch64. Other machine types do not support bypass iommu for default
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root bus.
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1. The following is the bypass iommu options:
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(1) PCI expander bridge
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qemu -device pxb-pcie,bus_nr=0x10,addr=0x1,bypass_iommu=true
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(2) Arm default host bridge
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qemu -machine virt,iommu=smmuv3,default_bus_bypass_iommu=true
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(3) X86 default root bus bypass iommu:
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qemu -machine q35,default_bus_bypass_iommu=true
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2. Here is the detailed qemu command line for 'virt' machine with PXB on
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AArch64:
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qemu-system-aarch64 \
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-machine virt,kernel_irqchip=on,iommu=smmuv3,default_bus_bypass_iommu=true \
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-device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3.0x1 \
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-device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x3.0x2,bypass_iommu=true \
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And we got:
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- a default host bridge which bypass SMMUv3
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- a pxb host bridge which go through SMMUv3
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- a pxb host bridge which bypass SMMUv3
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3. Here is the detailed qemu command line for 'q35' machine with PXB on
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x86 architecture:
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qemu-system-x86_64 \
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-machine q35,accel=kvm,default_bus_bypass_iommu=true \
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-device pxb-pcie,bus_nr=0x10,id=pci.10,bus=pcie.0,addr=0x3 \
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-device pxb-pcie,bus_nr=0x20,id=pci.20,bus=pcie.0,addr=0x4,bypass_iommu=true \
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-device intel-iommu \
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And we got:
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- a default host bridge which bypass iommu
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- a pxb host bridge which go through iommu
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- a pxb host bridge which bypass iommu
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Limitations
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===========
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There might be potential security risk when devices bypass iommu, because
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devices might send malicious dma request to virtual machine if there is no
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iommu isolation. So it would be necessary to only bypass iommu for trusted
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device.
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Implementation
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==============
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The bypass iommu feature includes:
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- Address space
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Add bypass iommu property check of PCI Host and do not get iommu address
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space for devices bypass iommu.
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- Arm SMMUv3 support
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We traverse all PCI root bus and get bus number ranges, then build explicit
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RID mapping for devices which do not bypass iommu.
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- X86 IOMMU support
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To support Intel iommu, we traverse all PCI host bridge and get information
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of devices which do not bypass iommu, then fill the DMAR drhd struct with
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explicit device scope info. To support AMD iommu, add check of bypass iommu
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when traverse the PCI hsot bridge.
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- Machine and PXB options
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We add bypass iommu options in machine option for default root bus, and add
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option for PXB also. Note that the default value of bypass iommu is false,
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so that the devices will by default go through iommu if there exist one.
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