e1000e.c (8020B)
1 /* 2 * libqos driver framework 3 * 4 * Copyright (c) 2018 Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License version 2.1 as published by the Free Software Foundation. 9 * 10 * This library is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * Lesser General Public License for more details. 14 * 15 * You should have received a copy of the GNU Lesser General Public 16 * License along with this library; if not, see <http://www.gnu.org/licenses/> 17 */ 18 19 #include "qemu/osdep.h" 20 #include "hw/net/e1000_regs.h" 21 #include "hw/pci/pci_ids.h" 22 #include "../libqtest.h" 23 #include "pci-pc.h" 24 #include "qemu/sockets.h" 25 #include "qemu/iov.h" 26 #include "qemu/module.h" 27 #include "qemu/bitops.h" 28 #include "libqos-malloc.h" 29 #include "qgraph.h" 30 #include "e1000e.h" 31 32 #define E1000E_IVAR_TEST_CFG \ 33 (((E1000E_RX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_RXQ0_SHIFT) | \ 34 ((E1000E_TX0_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_TXQ0_SHIFT) | \ 35 ((E1000E_OTHER_MSG_ID | E1000_IVAR_INT_ALLOC_VALID) << E1000_IVAR_OTHER_SHIFT) | \ 36 E1000_IVAR_TX_INT_EVERY_WB) 37 38 #define E1000E_RING_LEN (0x1000) 39 40 static void e1000e_macreg_write(QE1000E *d, uint32_t reg, uint32_t val) 41 { 42 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 43 qpci_io_writel(&d_pci->pci_dev, d_pci->mac_regs, reg, val); 44 } 45 46 static uint32_t e1000e_macreg_read(QE1000E *d, uint32_t reg) 47 { 48 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 49 return qpci_io_readl(&d_pci->pci_dev, d_pci->mac_regs, reg); 50 } 51 52 void e1000e_tx_ring_push(QE1000E *d, void *descr) 53 { 54 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 55 uint32_t tail = e1000e_macreg_read(d, E1000E_TDT); 56 uint32_t len = e1000e_macreg_read(d, E1000E_TDLEN) / E1000_RING_DESC_LEN; 57 58 qtest_memwrite(d_pci->pci_dev.bus->qts, 59 d->tx_ring + tail * E1000_RING_DESC_LEN, 60 descr, E1000_RING_DESC_LEN); 61 e1000e_macreg_write(d, E1000E_TDT, (tail + 1) % len); 62 63 /* Read WB data for the packet transmitted */ 64 qtest_memread(d_pci->pci_dev.bus->qts, 65 d->tx_ring + tail * E1000_RING_DESC_LEN, 66 descr, E1000_RING_DESC_LEN); 67 } 68 69 void e1000e_rx_ring_push(QE1000E *d, void *descr) 70 { 71 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 72 uint32_t tail = e1000e_macreg_read(d, E1000E_RDT); 73 uint32_t len = e1000e_macreg_read(d, E1000E_RDLEN) / E1000_RING_DESC_LEN; 74 75 qtest_memwrite(d_pci->pci_dev.bus->qts, 76 d->rx_ring + tail * E1000_RING_DESC_LEN, 77 descr, E1000_RING_DESC_LEN); 78 e1000e_macreg_write(d, E1000E_RDT, (tail + 1) % len); 79 80 /* Read WB data for the packet received */ 81 qtest_memread(d_pci->pci_dev.bus->qts, 82 d->rx_ring + tail * E1000_RING_DESC_LEN, 83 descr, E1000_RING_DESC_LEN); 84 } 85 86 static void e1000e_foreach_callback(QPCIDevice *dev, int devfn, void *data) 87 { 88 QPCIDevice *res = data; 89 memcpy(res, dev, sizeof(QPCIDevice)); 90 g_free(dev); 91 } 92 93 void e1000e_wait_isr(QE1000E *d, uint16_t msg_id) 94 { 95 QE1000E_PCI *d_pci = container_of(d, QE1000E_PCI, e1000e); 96 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; 97 98 do { 99 if (qpci_msix_pending(&d_pci->pci_dev, msg_id)) { 100 return; 101 } 102 qtest_clock_step(d_pci->pci_dev.bus->qts, 10000); 103 } while (g_get_monotonic_time() < end_time); 104 105 g_error("Timeout expired"); 106 } 107 108 static void e1000e_pci_destructor(QOSGraphObject *obj) 109 { 110 QE1000E_PCI *epci = (QE1000E_PCI *) obj; 111 qpci_iounmap(&epci->pci_dev, epci->mac_regs); 112 qpci_msix_disable(&epci->pci_dev); 113 } 114 115 static void e1000e_pci_start_hw(QOSGraphObject *obj) 116 { 117 QE1000E_PCI *d = (QE1000E_PCI *) obj; 118 uint32_t val; 119 120 /* Enable the device */ 121 qpci_device_enable(&d->pci_dev); 122 123 /* Reset the device */ 124 val = e1000e_macreg_read(&d->e1000e, E1000_CTRL); 125 e1000e_macreg_write(&d->e1000e, E1000_CTRL, val | E1000_CTRL_RST | E1000_CTRL_SLU); 126 127 /* Enable and configure MSI-X */ 128 qpci_msix_enable(&d->pci_dev); 129 e1000e_macreg_write(&d->e1000e, E1000_IVAR, E1000E_IVAR_TEST_CFG); 130 131 /* Check the device status - link and speed */ 132 val = e1000e_macreg_read(&d->e1000e, E1000_STATUS); 133 g_assert_cmphex(val & (E1000_STATUS_LU | E1000_STATUS_ASDV_1000), 134 ==, E1000_STATUS_LU | E1000_STATUS_ASDV_1000); 135 136 /* Initialize TX/RX logic */ 137 e1000e_macreg_write(&d->e1000e, E1000_RCTL, 0); 138 e1000e_macreg_write(&d->e1000e, E1000_TCTL, 0); 139 140 /* Notify the device that the driver is ready */ 141 val = e1000e_macreg_read(&d->e1000e, E1000_CTRL_EXT); 142 e1000e_macreg_write(&d->e1000e, E1000_CTRL_EXT, 143 val | E1000_CTRL_EXT_DRV_LOAD); 144 145 e1000e_macreg_write(&d->e1000e, E1000_TDBAL, 146 (uint32_t) d->e1000e.tx_ring); 147 e1000e_macreg_write(&d->e1000e, E1000_TDBAH, 148 (uint32_t) (d->e1000e.tx_ring >> 32)); 149 e1000e_macreg_write(&d->e1000e, E1000E_TDLEN, E1000E_RING_LEN); 150 e1000e_macreg_write(&d->e1000e, E1000E_TDT, 0); 151 e1000e_macreg_write(&d->e1000e, E1000_TDH, 0); 152 153 /* Enable transmit */ 154 e1000e_macreg_write(&d->e1000e, E1000_TCTL, E1000_TCTL_EN); 155 e1000e_macreg_write(&d->e1000e, E1000_RDBAL, 156 (uint32_t)d->e1000e.rx_ring); 157 e1000e_macreg_write(&d->e1000e, E1000_RDBAH, 158 (uint32_t)(d->e1000e.rx_ring >> 32)); 159 e1000e_macreg_write(&d->e1000e, E1000E_RDLEN, E1000E_RING_LEN); 160 e1000e_macreg_write(&d->e1000e, E1000E_RDT, 0); 161 e1000e_macreg_write(&d->e1000e, E1000_RDH, 0); 162 163 /* Enable receive */ 164 e1000e_macreg_write(&d->e1000e, E1000_RFCTL, E1000_RFCTL_EXTEN); 165 e1000e_macreg_write(&d->e1000e, E1000_RCTL, E1000_RCTL_EN | 166 E1000_RCTL_UPE | 167 E1000_RCTL_MPE); 168 169 /* Enable all interrupts */ 170 e1000e_macreg_write(&d->e1000e, E1000_IMS, 0xFFFFFFFF); 171 172 } 173 174 static void *e1000e_pci_get_driver(void *obj, const char *interface) 175 { 176 QE1000E_PCI *epci = obj; 177 if (!g_strcmp0(interface, "e1000e-if")) { 178 return &epci->e1000e; 179 } 180 181 /* implicit contains */ 182 if (!g_strcmp0(interface, "pci-device")) { 183 return &epci->pci_dev; 184 } 185 186 fprintf(stderr, "%s not present in e1000e\n", interface); 187 g_assert_not_reached(); 188 } 189 190 static void *e1000e_pci_create(void *pci_bus, QGuestAllocator *alloc, 191 void *addr) 192 { 193 QE1000E_PCI *d = g_new0(QE1000E_PCI, 1); 194 QPCIBus *bus = pci_bus; 195 QPCIAddress *address = addr; 196 197 qpci_device_foreach(bus, address->vendor_id, address->device_id, 198 e1000e_foreach_callback, &d->pci_dev); 199 200 /* Map BAR0 (mac registers) */ 201 d->mac_regs = qpci_iomap(&d->pci_dev, 0, NULL); 202 203 /* Allocate and setup TX ring */ 204 d->e1000e.tx_ring = guest_alloc(alloc, E1000E_RING_LEN); 205 g_assert(d->e1000e.tx_ring != 0); 206 207 /* Allocate and setup RX ring */ 208 d->e1000e.rx_ring = guest_alloc(alloc, E1000E_RING_LEN); 209 g_assert(d->e1000e.rx_ring != 0); 210 211 d->obj.get_driver = e1000e_pci_get_driver; 212 d->obj.start_hw = e1000e_pci_start_hw; 213 d->obj.destructor = e1000e_pci_destructor; 214 215 return &d->obj; 216 } 217 218 static void e1000e_register_nodes(void) 219 { 220 QPCIAddress addr = { 221 .vendor_id = PCI_VENDOR_ID_INTEL, 222 .device_id = E1000_DEV_ID_82574L, 223 }; 224 225 /* FIXME: every test using this node needs to setup a -netdev socket,id=hs0 226 * otherwise QEMU is not going to start */ 227 QOSGraphEdgeOptions opts = { 228 .extra_device_opts = "netdev=hs0", 229 }; 230 add_qpci_address(&opts, &addr); 231 232 qos_node_create_driver("e1000e", e1000e_pci_create); 233 qos_node_consumes("e1000e", "pci-bus", &opts); 234 } 235 236 libqos_init(e1000e_register_nodes);