aspeed_hace-test.c (21640B)
1 /* 2 * QTest testcase for the ASPEED Hash and Crypto Engine 3 * 4 * SPDX-License-Identifier: GPL-2.0-or-later 5 * Copyright 2021 IBM Corp. 6 */ 7 8 #include "qemu/osdep.h" 9 10 #include "libqtest.h" 11 #include "qemu/bitops.h" 12 13 #define HACE_CMD 0x10 14 #define HACE_SHA_BE_EN BIT(3) 15 #define HACE_MD5_LE_EN BIT(2) 16 #define HACE_ALGO_MD5 0 17 #define HACE_ALGO_SHA1 BIT(5) 18 #define HACE_ALGO_SHA224 BIT(6) 19 #define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) 20 #define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) 21 #define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) 22 #define HACE_SG_EN BIT(18) 23 #define HACE_ACCUM_EN BIT(8) 24 25 #define HACE_STS 0x1c 26 #define HACE_RSA_ISR BIT(13) 27 #define HACE_CRYPTO_ISR BIT(12) 28 #define HACE_HASH_ISR BIT(9) 29 #define HACE_RSA_BUSY BIT(2) 30 #define HACE_CRYPTO_BUSY BIT(1) 31 #define HACE_HASH_BUSY BIT(0) 32 #define HACE_HASH_SRC 0x20 33 #define HACE_HASH_DIGEST 0x24 34 #define HACE_HASH_KEY_BUFF 0x28 35 #define HACE_HASH_DATA_LEN 0x2c 36 #define HACE_HASH_CMD 0x30 37 /* Scatter-Gather Hash */ 38 #define SG_LIST_LEN_LAST BIT(31) 39 struct AspeedSgList { 40 uint32_t len; 41 uint32_t addr; 42 } __attribute__ ((__packed__)); 43 44 /* 45 * Test vector is the ascii "abc" 46 * 47 * Expected results were generated using command line utitiles: 48 * 49 * echo -n -e 'abc' | dd of=/tmp/test 50 * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done 51 * 52 */ 53 static const uint8_t test_vector[] = {0x61, 0x62, 0x63}; 54 55 static const uint8_t test_result_sha512[] = { 56 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 57 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 58 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, 59 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, 60 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 61 0xa5, 0x4c, 0xa4, 0x9f}; 62 63 static const uint8_t test_result_sha256[] = { 64 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 65 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 66 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; 67 68 static const uint8_t test_result_md5[] = { 69 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, 70 0x28, 0xe1, 0x7f, 0x72}; 71 72 /* 73 * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken 74 * into blocks of 3 characters as shown 75 * 76 * Expected results were generated using command line utitiles: 77 * 78 * echo -n -e 'abcdefghijkl' | dd of=/tmp/test 79 * for hash in sha512sum sha256sum; do $hash /tmp/test; done 80 * 81 */ 82 static const uint8_t test_vector_sg1[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66}; 83 static const uint8_t test_vector_sg2[] = {0x67, 0x68, 0x69}; 84 static const uint8_t test_vector_sg3[] = {0x6a, 0x6b, 0x6c}; 85 86 static const uint8_t test_result_sg_sha512[] = { 87 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, 88 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, 89 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, 90 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, 91 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, 92 0xf8, 0x6d, 0xda, 0x2e}; 93 94 static const uint8_t test_result_sg_sha256[] = { 95 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, 96 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, 97 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; 98 99 /* 100 * The accumulative mode requires firmware to provide internal initial state 101 * and message padding (including length L at the end of padding). 102 * 103 * This test vector is a ascii text "abc" with padding message. 104 * 105 * Expected results were generated using command line utitiles: 106 * 107 * echo -n -e 'abc' | dd of=/tmp/test 108 * for hash in sha512sum sha256sum; do $hash /tmp/test; done 109 */ 110 static const uint8_t test_vector_accum_512[] = { 111 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 112 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 113 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 114 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 115 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 116 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 117 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 118 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 120 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 122 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 127 128 static const uint8_t test_vector_accum_256[] = { 129 0x61, 0x62, 0x63, 0x80, 0x00, 0x00, 0x00, 0x00, 130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18}; 137 138 static const uint8_t test_result_accum_sha512[] = { 139 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, 140 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, 141 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, 142 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, 143 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, 144 0xa5, 0x4c, 0xa4, 0x9f}; 145 146 static const uint8_t test_result_accum_sha256[] = { 147 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, 148 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, 149 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; 150 151 static void write_regs(QTestState *s, uint32_t base, uint32_t src, 152 uint32_t length, uint32_t out, uint32_t method) 153 { 154 qtest_writel(s, base + HACE_HASH_SRC, src); 155 qtest_writel(s, base + HACE_HASH_DIGEST, out); 156 qtest_writel(s, base + HACE_HASH_DATA_LEN, length); 157 qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); 158 } 159 160 static void test_md5(const char *machine, const uint32_t base, 161 const uint32_t src_addr) 162 163 { 164 QTestState *s = qtest_init(machine); 165 166 uint32_t digest_addr = src_addr + 0x01000000; 167 uint8_t digest[16] = {0}; 168 169 /* Check engine is idle, no busy or irq bits set */ 170 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 171 172 /* Write test vector into memory */ 173 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 174 175 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5); 176 177 /* Check hash IRQ status is asserted */ 178 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 179 180 /* Clear IRQ status and check status is deasserted */ 181 qtest_writel(s, base + HACE_STS, 0x00000200); 182 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 183 184 /* Read computed digest from memory */ 185 qtest_memread(s, digest_addr, digest, sizeof(digest)); 186 187 /* Check result of computation */ 188 g_assert_cmpmem(digest, sizeof(digest), 189 test_result_md5, sizeof(digest)); 190 191 qtest_quit(s); 192 } 193 194 static void test_sha256(const char *machine, const uint32_t base, 195 const uint32_t src_addr) 196 { 197 QTestState *s = qtest_init(machine); 198 199 const uint32_t digest_addr = src_addr + 0x1000000; 200 uint8_t digest[32] = {0}; 201 202 /* Check engine is idle, no busy or irq bits set */ 203 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 204 205 /* Write test vector into memory */ 206 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 207 208 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256); 209 210 /* Check hash IRQ status is asserted */ 211 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 212 213 /* Clear IRQ status and check status is deasserted */ 214 qtest_writel(s, base + HACE_STS, 0x00000200); 215 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 216 217 /* Read computed digest from memory */ 218 qtest_memread(s, digest_addr, digest, sizeof(digest)); 219 220 /* Check result of computation */ 221 g_assert_cmpmem(digest, sizeof(digest), 222 test_result_sha256, sizeof(digest)); 223 224 qtest_quit(s); 225 } 226 227 static void test_sha512(const char *machine, const uint32_t base, 228 const uint32_t src_addr) 229 { 230 QTestState *s = qtest_init(machine); 231 232 const uint32_t digest_addr = src_addr + 0x1000000; 233 uint8_t digest[64] = {0}; 234 235 /* Check engine is idle, no busy or irq bits set */ 236 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 237 238 /* Write test vector into memory */ 239 qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); 240 241 write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512); 242 243 /* Check hash IRQ status is asserted */ 244 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 245 246 /* Clear IRQ status and check status is deasserted */ 247 qtest_writel(s, base + HACE_STS, 0x00000200); 248 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 249 250 /* Read computed digest from memory */ 251 qtest_memread(s, digest_addr, digest, sizeof(digest)); 252 253 /* Check result of computation */ 254 g_assert_cmpmem(digest, sizeof(digest), 255 test_result_sha512, sizeof(digest)); 256 257 qtest_quit(s); 258 } 259 260 static void test_sha256_sg(const char *machine, const uint32_t base, 261 const uint32_t src_addr) 262 { 263 QTestState *s = qtest_init(machine); 264 265 const uint32_t src_addr_1 = src_addr + 0x1000000; 266 const uint32_t src_addr_2 = src_addr + 0x2000000; 267 const uint32_t src_addr_3 = src_addr + 0x3000000; 268 const uint32_t digest_addr = src_addr + 0x4000000; 269 uint8_t digest[32] = {0}; 270 struct AspeedSgList array[] = { 271 { cpu_to_le32(sizeof(test_vector_sg1)), 272 cpu_to_le32(src_addr_1) }, 273 { cpu_to_le32(sizeof(test_vector_sg2)), 274 cpu_to_le32(src_addr_2) }, 275 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 276 cpu_to_le32(src_addr_3) }, 277 }; 278 279 /* Check engine is idle, no busy or irq bits set */ 280 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 281 282 /* Write test vector into memory */ 283 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 284 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 285 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 286 qtest_memwrite(s, src_addr, array, sizeof(array)); 287 288 write_regs(s, base, src_addr, 289 (sizeof(test_vector_sg1) 290 + sizeof(test_vector_sg2) 291 + sizeof(test_vector_sg3)), 292 digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); 293 294 /* Check hash IRQ status is asserted */ 295 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 296 297 /* Clear IRQ status and check status is deasserted */ 298 qtest_writel(s, base + HACE_STS, 0x00000200); 299 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 300 301 /* Read computed digest from memory */ 302 qtest_memread(s, digest_addr, digest, sizeof(digest)); 303 304 /* Check result of computation */ 305 g_assert_cmpmem(digest, sizeof(digest), 306 test_result_sg_sha256, sizeof(digest)); 307 308 qtest_quit(s); 309 } 310 311 static void test_sha512_sg(const char *machine, const uint32_t base, 312 const uint32_t src_addr) 313 { 314 QTestState *s = qtest_init(machine); 315 316 const uint32_t src_addr_1 = src_addr + 0x1000000; 317 const uint32_t src_addr_2 = src_addr + 0x2000000; 318 const uint32_t src_addr_3 = src_addr + 0x3000000; 319 const uint32_t digest_addr = src_addr + 0x4000000; 320 uint8_t digest[64] = {0}; 321 struct AspeedSgList array[] = { 322 { cpu_to_le32(sizeof(test_vector_sg1)), 323 cpu_to_le32(src_addr_1) }, 324 { cpu_to_le32(sizeof(test_vector_sg2)), 325 cpu_to_le32(src_addr_2) }, 326 { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), 327 cpu_to_le32(src_addr_3) }, 328 }; 329 330 /* Check engine is idle, no busy or irq bits set */ 331 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 332 333 /* Write test vector into memory */ 334 qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); 335 qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); 336 qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); 337 qtest_memwrite(s, src_addr, array, sizeof(array)); 338 339 write_regs(s, base, src_addr, 340 (sizeof(test_vector_sg1) 341 + sizeof(test_vector_sg2) 342 + sizeof(test_vector_sg3)), 343 digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); 344 345 /* Check hash IRQ status is asserted */ 346 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 347 348 /* Clear IRQ status and check status is deasserted */ 349 qtest_writel(s, base + HACE_STS, 0x00000200); 350 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 351 352 /* Read computed digest from memory */ 353 qtest_memread(s, digest_addr, digest, sizeof(digest)); 354 355 /* Check result of computation */ 356 g_assert_cmpmem(digest, sizeof(digest), 357 test_result_sg_sha512, sizeof(digest)); 358 359 qtest_quit(s); 360 } 361 362 static void test_sha256_accum(const char *machine, const uint32_t base, 363 const uint32_t src_addr) 364 { 365 QTestState *s = qtest_init(machine); 366 367 const uint32_t buffer_addr = src_addr + 0x1000000; 368 const uint32_t digest_addr = src_addr + 0x4000000; 369 uint8_t digest[32] = {0}; 370 struct AspeedSgList array[] = { 371 { cpu_to_le32(sizeof(test_vector_accum_256) | SG_LIST_LEN_LAST), 372 cpu_to_le32(buffer_addr) }, 373 }; 374 375 /* Check engine is idle, no busy or irq bits set */ 376 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 377 378 /* Write test vector into memory */ 379 qtest_memwrite(s, buffer_addr, test_vector_accum_256, 380 sizeof(test_vector_accum_256)); 381 qtest_memwrite(s, src_addr, array, sizeof(array)); 382 383 write_regs(s, base, src_addr, sizeof(test_vector_accum_256), 384 digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN | HACE_ACCUM_EN); 385 386 /* Check hash IRQ status is asserted */ 387 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 388 389 /* Clear IRQ status and check status is deasserted */ 390 qtest_writel(s, base + HACE_STS, 0x00000200); 391 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 392 393 /* Read computed digest from memory */ 394 qtest_memread(s, digest_addr, digest, sizeof(digest)); 395 396 /* Check result of computation */ 397 g_assert_cmpmem(digest, sizeof(digest), 398 test_result_accum_sha256, sizeof(digest)); 399 400 qtest_quit(s); 401 } 402 403 static void test_sha512_accum(const char *machine, const uint32_t base, 404 const uint32_t src_addr) 405 { 406 QTestState *s = qtest_init(machine); 407 408 const uint32_t buffer_addr = src_addr + 0x1000000; 409 const uint32_t digest_addr = src_addr + 0x4000000; 410 uint8_t digest[64] = {0}; 411 struct AspeedSgList array[] = { 412 { cpu_to_le32(sizeof(test_vector_accum_512) | SG_LIST_LEN_LAST), 413 cpu_to_le32(buffer_addr) }, 414 }; 415 416 /* Check engine is idle, no busy or irq bits set */ 417 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 418 419 /* Write test vector into memory */ 420 qtest_memwrite(s, buffer_addr, test_vector_accum_512, 421 sizeof(test_vector_accum_512)); 422 qtest_memwrite(s, src_addr, array, sizeof(array)); 423 424 write_regs(s, base, src_addr, sizeof(test_vector_accum_512), 425 digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN | HACE_ACCUM_EN); 426 427 /* Check hash IRQ status is asserted */ 428 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); 429 430 /* Clear IRQ status and check status is deasserted */ 431 qtest_writel(s, base + HACE_STS, 0x00000200); 432 g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); 433 434 /* Read computed digest from memory */ 435 qtest_memread(s, digest_addr, digest, sizeof(digest)); 436 437 /* Check result of computation */ 438 g_assert_cmpmem(digest, sizeof(digest), 439 test_result_accum_sha512, sizeof(digest)); 440 441 qtest_quit(s); 442 } 443 444 struct masks { 445 uint32_t src; 446 uint32_t dest; 447 uint32_t len; 448 }; 449 450 static const struct masks ast2600_masks = { 451 .src = 0x7fffffff, 452 .dest = 0x7ffffff8, 453 .len = 0x0fffffff, 454 }; 455 456 static const struct masks ast2500_masks = { 457 .src = 0x3fffffff, 458 .dest = 0x3ffffff8, 459 .len = 0x0fffffff, 460 }; 461 462 static const struct masks ast2400_masks = { 463 .src = 0x0fffffff, 464 .dest = 0x0ffffff8, 465 .len = 0x0fffffff, 466 }; 467 468 static void test_addresses(const char *machine, const uint32_t base, 469 const struct masks *expected) 470 { 471 QTestState *s = qtest_init(machine); 472 473 /* 474 * Check command mode is zero, meaning engine is in direct access mode, 475 * as this affects the masking behavior of the HASH_SRC register. 476 */ 477 g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); 478 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 479 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 480 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 481 482 483 /* Check that the address masking is correct */ 484 qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); 485 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); 486 487 qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); 488 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest); 489 490 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); 491 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); 492 493 /* Reset to zero */ 494 qtest_writel(s, base + HACE_HASH_SRC, 0); 495 qtest_writel(s, base + HACE_HASH_DIGEST, 0); 496 qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); 497 498 /* Check that all bits are now zero */ 499 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); 500 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); 501 g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); 502 503 qtest_quit(s); 504 } 505 506 /* ast2600 */ 507 static void test_md5_ast2600(void) 508 { 509 test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 510 } 511 512 static void test_sha256_ast2600(void) 513 { 514 test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 515 } 516 517 static void test_sha256_sg_ast2600(void) 518 { 519 test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 520 } 521 522 static void test_sha512_ast2600(void) 523 { 524 test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 525 } 526 527 static void test_sha512_sg_ast2600(void) 528 { 529 test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 530 } 531 532 static void test_sha256_accum_ast2600(void) 533 { 534 test_sha256_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 535 } 536 537 static void test_sha512_accum_ast2600(void) 538 { 539 test_sha512_accum("-machine ast2600-evb", 0x1e6d0000, 0x80000000); 540 } 541 542 static void test_addresses_ast2600(void) 543 { 544 test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); 545 } 546 547 /* ast2500 */ 548 static void test_md5_ast2500(void) 549 { 550 test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 551 } 552 553 static void test_sha256_ast2500(void) 554 { 555 test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 556 } 557 558 static void test_sha512_ast2500(void) 559 { 560 test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); 561 } 562 563 static void test_addresses_ast2500(void) 564 { 565 test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); 566 } 567 568 /* ast2400 */ 569 static void test_md5_ast2400(void) 570 { 571 test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 572 } 573 574 static void test_sha256_ast2400(void) 575 { 576 test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 577 } 578 579 static void test_sha512_ast2400(void) 580 { 581 test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); 582 } 583 584 static void test_addresses_ast2400(void) 585 { 586 test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); 587 } 588 589 int main(int argc, char **argv) 590 { 591 g_test_init(&argc, &argv, NULL); 592 593 qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); 594 qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); 595 qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); 596 qtest_add_func("ast2600/hace/md5", test_md5_ast2600); 597 598 qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); 599 qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); 600 601 qtest_add_func("ast2600/hace/sha512_accum", test_sha512_accum_ast2600); 602 qtest_add_func("ast2600/hace/sha256_accum", test_sha256_accum_ast2600); 603 604 qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); 605 qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); 606 qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); 607 qtest_add_func("ast2500/hace/md5", test_md5_ast2500); 608 609 qtest_add_func("ast2400/hace/addresses", test_addresses_ast2400); 610 qtest_add_func("ast2400/hace/sha512", test_sha512_ast2400); 611 qtest_add_func("ast2400/hace/sha256", test_sha256_ast2400); 612 qtest_add_func("ast2400/hace/md5", test_md5_ast2400); 613 614 return g_test_run(); 615 }