tcg-target.c.inc (93348B)
1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "../tcg-ldst.c.inc" 28 29 #if HOST_BIG_ENDIAN 30 # define MIPS_BE 1 31 #else 32 # define MIPS_BE 0 33 #endif 34 35 #if TCG_TARGET_REG_BITS == 32 36 # define LO_OFF (MIPS_BE * 4) 37 # define HI_OFF (4 - LO_OFF) 38 #else 39 /* To assert at compile-time that these values are never used 40 for TCG_TARGET_REG_BITS == 64. */ 41 int link_error(void); 42 # define LO_OFF link_error() 43 # define HI_OFF link_error() 44 #endif 45 46 #ifdef CONFIG_DEBUG_TCG 47 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 48 "zero", 49 "at", 50 "v0", 51 "v1", 52 "a0", 53 "a1", 54 "a2", 55 "a3", 56 "t0", 57 "t1", 58 "t2", 59 "t3", 60 "t4", 61 "t5", 62 "t6", 63 "t7", 64 "s0", 65 "s1", 66 "s2", 67 "s3", 68 "s4", 69 "s5", 70 "s6", 71 "s7", 72 "t8", 73 "t9", 74 "k0", 75 "k1", 76 "gp", 77 "sp", 78 "s8", 79 "ra", 80 }; 81 #endif 82 83 #define TCG_TMP0 TCG_REG_AT 84 #define TCG_TMP1 TCG_REG_T9 85 #define TCG_TMP2 TCG_REG_T8 86 #define TCG_TMP3 TCG_REG_T7 87 88 #ifndef CONFIG_SOFTMMU 89 #define TCG_GUEST_BASE_REG TCG_REG_S1 90 #endif 91 92 /* check if we really need so many registers :P */ 93 static const int tcg_target_reg_alloc_order[] = { 94 /* Call saved registers. */ 95 TCG_REG_S0, 96 TCG_REG_S1, 97 TCG_REG_S2, 98 TCG_REG_S3, 99 TCG_REG_S4, 100 TCG_REG_S5, 101 TCG_REG_S6, 102 TCG_REG_S7, 103 TCG_REG_S8, 104 105 /* Call clobbered registers. */ 106 TCG_REG_T4, 107 TCG_REG_T5, 108 TCG_REG_T6, 109 TCG_REG_T7, 110 TCG_REG_T8, 111 TCG_REG_T9, 112 TCG_REG_V1, 113 TCG_REG_V0, 114 115 /* Argument registers, opposite order of allocation. */ 116 TCG_REG_T3, 117 TCG_REG_T2, 118 TCG_REG_T1, 119 TCG_REG_T0, 120 TCG_REG_A3, 121 TCG_REG_A2, 122 TCG_REG_A1, 123 TCG_REG_A0, 124 }; 125 126 static const TCGReg tcg_target_call_iarg_regs[] = { 127 TCG_REG_A0, 128 TCG_REG_A1, 129 TCG_REG_A2, 130 TCG_REG_A3, 131 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 132 TCG_REG_T0, 133 TCG_REG_T1, 134 TCG_REG_T2, 135 TCG_REG_T3, 136 #endif 137 }; 138 139 static const TCGReg tcg_target_call_oarg_regs[2] = { 140 TCG_REG_V0, 141 TCG_REG_V1 142 }; 143 144 static const tcg_insn_unit *tb_ret_addr; 145 static const tcg_insn_unit *bswap32_addr; 146 static const tcg_insn_unit *bswap32u_addr; 147 static const tcg_insn_unit *bswap64_addr; 148 149 static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 150 { 151 /* Let the compiler perform the right-shift as part of the arithmetic. */ 152 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 153 ptrdiff_t disp = target - (src_rx + 1); 154 if (disp == (int16_t)disp) { 155 *src_rw = deposit32(*src_rw, 0, 16, disp); 156 return true; 157 } 158 return false; 159 } 160 161 static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 162 intptr_t value, intptr_t addend) 163 { 164 tcg_debug_assert(type == R_MIPS_PC16); 165 tcg_debug_assert(addend == 0); 166 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 167 } 168 169 #define TCG_CT_CONST_ZERO 0x100 170 #define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 171 #define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 172 #define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 173 #define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 174 #define TCG_CT_CONST_WSZ 0x2000 /* word size */ 175 176 #define ALL_GENERAL_REGS 0xffffffffu 177 #define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) 178 179 #ifdef CONFIG_SOFTMMU 180 #define ALL_QLOAD_REGS \ 181 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) 182 #define ALL_QSTORE_REGS \ 183 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ 184 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ 185 : (1 << TCG_REG_A1))) 186 #else 187 #define ALL_QLOAD_REGS NOA0_REGS 188 #define ALL_QSTORE_REGS NOA0_REGS 189 #endif 190 191 192 static bool is_p2m1(tcg_target_long val) 193 { 194 return val && ((val + 1) & val) == 0; 195 } 196 197 /* test if a constant matches the constraint */ 198 static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 199 { 200 if (ct & TCG_CT_CONST) { 201 return 1; 202 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 203 return 1; 204 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_P2M1) 211 && use_mips32r2_instructions && is_p2m1(val)) { 212 return 1; 213 } else if ((ct & TCG_CT_CONST_WSZ) 214 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 215 return 1; 216 } 217 return 0; 218 } 219 220 /* instruction opcodes */ 221 typedef enum { 222 OPC_J = 002 << 26, 223 OPC_JAL = 003 << 26, 224 OPC_BEQ = 004 << 26, 225 OPC_BNE = 005 << 26, 226 OPC_BLEZ = 006 << 26, 227 OPC_BGTZ = 007 << 26, 228 OPC_ADDIU = 011 << 26, 229 OPC_SLTI = 012 << 26, 230 OPC_SLTIU = 013 << 26, 231 OPC_ANDI = 014 << 26, 232 OPC_ORI = 015 << 26, 233 OPC_XORI = 016 << 26, 234 OPC_LUI = 017 << 26, 235 OPC_BNEL = 025 << 26, 236 OPC_BNEZALC_R6 = 030 << 26, 237 OPC_DADDIU = 031 << 26, 238 OPC_LDL = 032 << 26, 239 OPC_LDR = 033 << 26, 240 OPC_LB = 040 << 26, 241 OPC_LH = 041 << 26, 242 OPC_LWL = 042 << 26, 243 OPC_LW = 043 << 26, 244 OPC_LBU = 044 << 26, 245 OPC_LHU = 045 << 26, 246 OPC_LWR = 046 << 26, 247 OPC_LWU = 047 << 26, 248 OPC_SB = 050 << 26, 249 OPC_SH = 051 << 26, 250 OPC_SWL = 052 << 26, 251 OPC_SW = 053 << 26, 252 OPC_SDL = 054 << 26, 253 OPC_SDR = 055 << 26, 254 OPC_SWR = 056 << 26, 255 OPC_LD = 067 << 26, 256 OPC_SD = 077 << 26, 257 258 OPC_SPECIAL = 000 << 26, 259 OPC_SLL = OPC_SPECIAL | 000, 260 OPC_SRL = OPC_SPECIAL | 002, 261 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 262 OPC_SRA = OPC_SPECIAL | 003, 263 OPC_SLLV = OPC_SPECIAL | 004, 264 OPC_SRLV = OPC_SPECIAL | 006, 265 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 266 OPC_SRAV = OPC_SPECIAL | 007, 267 OPC_JR_R5 = OPC_SPECIAL | 010, 268 OPC_JALR = OPC_SPECIAL | 011, 269 OPC_MOVZ = OPC_SPECIAL | 012, 270 OPC_MOVN = OPC_SPECIAL | 013, 271 OPC_SYNC = OPC_SPECIAL | 017, 272 OPC_MFHI = OPC_SPECIAL | 020, 273 OPC_MFLO = OPC_SPECIAL | 022, 274 OPC_DSLLV = OPC_SPECIAL | 024, 275 OPC_DSRLV = OPC_SPECIAL | 026, 276 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 277 OPC_DSRAV = OPC_SPECIAL | 027, 278 OPC_MULT = OPC_SPECIAL | 030, 279 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 280 OPC_MUH = OPC_SPECIAL | 030 | 0300, 281 OPC_MULTU = OPC_SPECIAL | 031, 282 OPC_MULU = OPC_SPECIAL | 031 | 0200, 283 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 284 OPC_DIV = OPC_SPECIAL | 032, 285 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 286 OPC_MOD = OPC_SPECIAL | 032 | 0300, 287 OPC_DIVU = OPC_SPECIAL | 033, 288 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 289 OPC_MODU = OPC_SPECIAL | 033 | 0300, 290 OPC_DMULT = OPC_SPECIAL | 034, 291 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 292 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 293 OPC_DMULTU = OPC_SPECIAL | 035, 294 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 295 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 296 OPC_DDIV = OPC_SPECIAL | 036, 297 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 298 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 299 OPC_DDIVU = OPC_SPECIAL | 037, 300 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 301 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 302 OPC_ADDU = OPC_SPECIAL | 041, 303 OPC_SUBU = OPC_SPECIAL | 043, 304 OPC_AND = OPC_SPECIAL | 044, 305 OPC_OR = OPC_SPECIAL | 045, 306 OPC_XOR = OPC_SPECIAL | 046, 307 OPC_NOR = OPC_SPECIAL | 047, 308 OPC_SLT = OPC_SPECIAL | 052, 309 OPC_SLTU = OPC_SPECIAL | 053, 310 OPC_DADDU = OPC_SPECIAL | 055, 311 OPC_DSUBU = OPC_SPECIAL | 057, 312 OPC_SELEQZ = OPC_SPECIAL | 065, 313 OPC_SELNEZ = OPC_SPECIAL | 067, 314 OPC_DSLL = OPC_SPECIAL | 070, 315 OPC_DSRL = OPC_SPECIAL | 072, 316 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 317 OPC_DSRA = OPC_SPECIAL | 073, 318 OPC_DSLL32 = OPC_SPECIAL | 074, 319 OPC_DSRL32 = OPC_SPECIAL | 076, 320 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 321 OPC_DSRA32 = OPC_SPECIAL | 077, 322 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 323 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 324 325 OPC_REGIMM = 001 << 26, 326 OPC_BLTZ = OPC_REGIMM | (000 << 16), 327 OPC_BGEZ = OPC_REGIMM | (001 << 16), 328 329 OPC_SPECIAL2 = 034 << 26, 330 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 331 OPC_CLZ = OPC_SPECIAL2 | 040, 332 OPC_DCLZ = OPC_SPECIAL2 | 044, 333 334 OPC_SPECIAL3 = 037 << 26, 335 OPC_EXT = OPC_SPECIAL3 | 000, 336 OPC_DEXTM = OPC_SPECIAL3 | 001, 337 OPC_DEXTU = OPC_SPECIAL3 | 002, 338 OPC_DEXT = OPC_SPECIAL3 | 003, 339 OPC_INS = OPC_SPECIAL3 | 004, 340 OPC_DINSM = OPC_SPECIAL3 | 005, 341 OPC_DINSU = OPC_SPECIAL3 | 006, 342 OPC_DINS = OPC_SPECIAL3 | 007, 343 OPC_WSBH = OPC_SPECIAL3 | 00240, 344 OPC_DSBH = OPC_SPECIAL3 | 00244, 345 OPC_DSHD = OPC_SPECIAL3 | 00544, 346 OPC_SEB = OPC_SPECIAL3 | 02040, 347 OPC_SEH = OPC_SPECIAL3 | 03040, 348 349 /* MIPS r6 doesn't have JR, JALR should be used instead */ 350 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 351 352 /* 353 * MIPS r6 replaces MUL with an alternative encoding which is 354 * backwards-compatible at the assembly level. 355 */ 356 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 357 358 /* MIPS r6 introduced names for weaker variants of SYNC. These are 359 backward compatible to previous architecture revisions. */ 360 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 361 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 362 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 363 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 364 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 365 366 /* Aliases for convenience. */ 367 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 368 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 369 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 370 ? OPC_SRL : OPC_DSRL, 371 } MIPSInsn; 372 373 /* 374 * Type reg 375 */ 376 static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378 { 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386 } 387 388 /* 389 * Type immediate 390 */ 391 static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393 { 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401 } 402 403 /* 404 * Type bitfield 405 */ 406 static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408 { 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417 } 418 419 static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422 { 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432 } 433 434 /* 435 * Type branch 436 */ 437 static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438 { 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440 } 441 442 /* 443 * Type sa 444 */ 445 static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447 { 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456 } 457 458 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460 { 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468 } 469 470 /* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474 static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475 { 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491 } 492 493 static void tcg_out_nop(TCGContext *s) 494 { 495 tcg_out32(s, 0); 496 } 497 498 static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 499 { 500 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 501 } 502 503 static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504 { 505 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 506 } 507 508 static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509 { 510 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 511 } 512 513 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 514 { 515 /* Simple reg-reg move, optimising out the 'do nothing' case */ 516 if (ret != arg) { 517 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 518 } 519 return true; 520 } 521 522 static void tcg_out_movi(TCGContext *s, TCGType type, 523 TCGReg ret, tcg_target_long arg) 524 { 525 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 526 arg = (int32_t)arg; 527 } 528 if (arg == (int16_t)arg) { 529 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 530 return; 531 } 532 if (arg == (uint16_t)arg) { 533 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 534 return; 535 } 536 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 537 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 538 } else { 539 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 540 if (arg & 0xffff0000ull) { 541 tcg_out_dsll(s, ret, ret, 16); 542 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 543 tcg_out_dsll(s, ret, ret, 16); 544 } else { 545 tcg_out_dsll(s, ret, ret, 32); 546 } 547 } 548 if (arg & 0xffff) { 549 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 550 } 551 } 552 553 static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 554 { 555 /* ret and arg can't be register tmp0 */ 556 tcg_debug_assert(ret != TCG_TMP0); 557 tcg_debug_assert(arg != TCG_TMP0); 558 559 /* With arg = abcd: */ 560 if (use_mips32r2_instructions) { 561 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 562 if (flags & TCG_BSWAP_OS) { 563 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 564 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 565 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 566 } 567 return; 568 } 569 570 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 571 if (!(flags & TCG_BSWAP_IZ)) { 572 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 573 } 574 if (flags & TCG_BSWAP_OS) { 575 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 576 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 577 } else { 578 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 579 if (flags & TCG_BSWAP_OZ) { 580 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 581 } 582 } 583 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 584 } 585 586 static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 587 { 588 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 589 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 590 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 591 } 592 } 593 594 static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 595 { 596 if (use_mips32r2_instructions) { 597 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 598 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 599 if (flags & TCG_BSWAP_OZ) { 600 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 601 } 602 } else { 603 if (flags & TCG_BSWAP_OZ) { 604 tcg_out_bswap_subr(s, bswap32u_addr); 605 } else { 606 tcg_out_bswap_subr(s, bswap32_addr); 607 } 608 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 610 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 611 } 612 } 613 614 static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 615 { 616 if (use_mips32r2_instructions) { 617 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 618 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 619 } else { 620 tcg_out_bswap_subr(s, bswap64_addr); 621 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 622 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 623 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 624 } 625 } 626 627 static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 628 { 629 if (use_mips32r2_instructions) { 630 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 631 } else { 632 tcg_out_dsll(s, ret, arg, 32); 633 tcg_out_dsrl(s, ret, ret, 32); 634 } 635 } 636 637 static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 638 TCGReg addr, intptr_t ofs) 639 { 640 int16_t lo = ofs; 641 if (ofs != lo) { 642 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 643 if (addr != TCG_REG_ZERO) { 644 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 645 } 646 addr = TCG_TMP0; 647 } 648 tcg_out_opc_imm(s, opc, data, addr, lo); 649 } 650 651 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 652 TCGReg arg1, intptr_t arg2) 653 { 654 MIPSInsn opc = OPC_LD; 655 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 656 opc = OPC_LW; 657 } 658 tcg_out_ldst(s, opc, arg, arg1, arg2); 659 } 660 661 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 662 TCGReg arg1, intptr_t arg2) 663 { 664 MIPSInsn opc = OPC_SD; 665 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 666 opc = OPC_SW; 667 } 668 tcg_out_ldst(s, opc, arg, arg1, arg2); 669 } 670 671 static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 672 TCGReg base, intptr_t ofs) 673 { 674 if (val == 0) { 675 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 676 return true; 677 } 678 return false; 679 } 680 681 static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 682 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 683 bool cbh, bool is_sub) 684 { 685 TCGReg th = TCG_TMP1; 686 687 /* If we have a negative constant such that negating it would 688 make the high part zero, we can (usually) eliminate one insn. */ 689 if (cbl && cbh && bh == -1 && bl != 0) { 690 bl = -bl; 691 bh = 0; 692 is_sub = !is_sub; 693 } 694 695 /* By operating on the high part first, we get to use the final 696 carry operation to move back from the temporary. */ 697 if (!cbh) { 698 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 699 } else if (bh != 0 || ah == rl) { 700 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 701 } else { 702 th = ah; 703 } 704 705 /* Note that tcg optimization should eliminate the bl == 0 case. */ 706 if (is_sub) { 707 if (cbl) { 708 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 709 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 710 } else { 711 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 712 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 713 } 714 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 715 } else { 716 if (cbl) { 717 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 718 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 719 } else if (rl == al && rl == bl) { 720 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 721 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 722 } else { 723 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 724 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 725 } 726 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 727 } 728 } 729 730 /* Bit 0 set if inversion required; bit 1 set if swapping required. */ 731 #define MIPS_CMP_INV 1 732 #define MIPS_CMP_SWAP 2 733 734 static const uint8_t mips_cmp_map[16] = { 735 [TCG_COND_LT] = 0, 736 [TCG_COND_LTU] = 0, 737 [TCG_COND_GE] = MIPS_CMP_INV, 738 [TCG_COND_GEU] = MIPS_CMP_INV, 739 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 740 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 741 [TCG_COND_GT] = MIPS_CMP_SWAP, 742 [TCG_COND_GTU] = MIPS_CMP_SWAP, 743 }; 744 745 static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 746 TCGReg arg1, TCGReg arg2) 747 { 748 MIPSInsn s_opc = OPC_SLTU; 749 int cmp_map; 750 751 switch (cond) { 752 case TCG_COND_EQ: 753 if (arg2 != 0) { 754 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 755 arg1 = ret; 756 } 757 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 758 break; 759 760 case TCG_COND_NE: 761 if (arg2 != 0) { 762 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 763 arg1 = ret; 764 } 765 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 766 break; 767 768 case TCG_COND_LT: 769 case TCG_COND_GE: 770 case TCG_COND_LE: 771 case TCG_COND_GT: 772 s_opc = OPC_SLT; 773 /* FALLTHRU */ 774 775 case TCG_COND_LTU: 776 case TCG_COND_GEU: 777 case TCG_COND_LEU: 778 case TCG_COND_GTU: 779 cmp_map = mips_cmp_map[cond]; 780 if (cmp_map & MIPS_CMP_SWAP) { 781 TCGReg t = arg1; 782 arg1 = arg2; 783 arg2 = t; 784 } 785 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 786 if (cmp_map & MIPS_CMP_INV) { 787 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 788 } 789 break; 790 791 default: 792 tcg_abort(); 793 break; 794 } 795 } 796 797 static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 798 TCGReg arg2, TCGLabel *l) 799 { 800 static const MIPSInsn b_zero[16] = { 801 [TCG_COND_LT] = OPC_BLTZ, 802 [TCG_COND_GT] = OPC_BGTZ, 803 [TCG_COND_LE] = OPC_BLEZ, 804 [TCG_COND_GE] = OPC_BGEZ, 805 }; 806 807 MIPSInsn s_opc = OPC_SLTU; 808 MIPSInsn b_opc; 809 int cmp_map; 810 811 switch (cond) { 812 case TCG_COND_EQ: 813 b_opc = OPC_BEQ; 814 break; 815 case TCG_COND_NE: 816 b_opc = OPC_BNE; 817 break; 818 819 case TCG_COND_LT: 820 case TCG_COND_GT: 821 case TCG_COND_LE: 822 case TCG_COND_GE: 823 if (arg2 == 0) { 824 b_opc = b_zero[cond]; 825 arg2 = arg1; 826 arg1 = 0; 827 break; 828 } 829 s_opc = OPC_SLT; 830 /* FALLTHRU */ 831 832 case TCG_COND_LTU: 833 case TCG_COND_GTU: 834 case TCG_COND_LEU: 835 case TCG_COND_GEU: 836 cmp_map = mips_cmp_map[cond]; 837 if (cmp_map & MIPS_CMP_SWAP) { 838 TCGReg t = arg1; 839 arg1 = arg2; 840 arg2 = t; 841 } 842 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 843 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 844 arg1 = TCG_TMP0; 845 arg2 = TCG_REG_ZERO; 846 break; 847 848 default: 849 tcg_abort(); 850 break; 851 } 852 853 tcg_out_opc_br(s, b_opc, arg1, arg2); 854 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 855 tcg_out_nop(s); 856 } 857 858 static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 859 TCGReg al, TCGReg ah, 860 TCGReg bl, TCGReg bh) 861 { 862 /* Merge highpart comparison into AH. */ 863 if (bh != 0) { 864 if (ah != 0) { 865 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 866 ah = tmp0; 867 } else { 868 ah = bh; 869 } 870 } 871 /* Merge lowpart comparison into AL. */ 872 if (bl != 0) { 873 if (al != 0) { 874 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 875 al = tmp1; 876 } else { 877 al = bl; 878 } 879 } 880 /* Merge high and low part comparisons into AL. */ 881 if (ah != 0) { 882 if (al != 0) { 883 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 884 al = tmp0; 885 } else { 886 al = ah; 887 } 888 } 889 return al; 890 } 891 892 static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 893 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 894 { 895 TCGReg tmp0 = TCG_TMP0; 896 TCGReg tmp1 = ret; 897 898 tcg_debug_assert(ret != TCG_TMP0); 899 if (ret == ah || ret == bh) { 900 tcg_debug_assert(ret != TCG_TMP1); 901 tmp1 = TCG_TMP1; 902 } 903 904 switch (cond) { 905 case TCG_COND_EQ: 906 case TCG_COND_NE: 907 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 908 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 909 break; 910 911 default: 912 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 913 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 914 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 915 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 916 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 917 break; 918 } 919 } 920 921 static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 922 TCGReg bl, TCGReg bh, TCGLabel *l) 923 { 924 TCGCond b_cond = TCG_COND_NE; 925 TCGReg tmp = TCG_TMP1; 926 927 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 928 With setcond, we emit between 3 and 10 insns and only 1 branch, 929 which ought to get better branch prediction. */ 930 switch (cond) { 931 case TCG_COND_EQ: 932 case TCG_COND_NE: 933 b_cond = cond; 934 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 935 break; 936 937 default: 938 /* Minimize code size by preferring a compare not requiring INV. */ 939 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 940 cond = tcg_invert_cond(cond); 941 b_cond = TCG_COND_EQ; 942 } 943 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 944 break; 945 } 946 947 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 948 } 949 950 static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 951 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 952 { 953 bool eqz = false; 954 955 /* If one of the values is zero, put it last to match SEL*Z instructions */ 956 if (use_mips32r6_instructions && v1 == 0) { 957 v1 = v2; 958 v2 = 0; 959 cond = tcg_invert_cond(cond); 960 } 961 962 switch (cond) { 963 case TCG_COND_EQ: 964 eqz = true; 965 /* FALLTHRU */ 966 case TCG_COND_NE: 967 if (c2 != 0) { 968 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 969 c1 = TCG_TMP0; 970 } 971 break; 972 973 default: 974 /* Minimize code size by preferring a compare not requiring INV. */ 975 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 976 cond = tcg_invert_cond(cond); 977 eqz = true; 978 } 979 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 980 c1 = TCG_TMP0; 981 break; 982 } 983 984 if (use_mips32r6_instructions) { 985 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 986 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 987 988 if (v2 != 0) { 989 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 990 } 991 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 992 if (v2 != 0) { 993 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 994 } 995 } else { 996 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 997 998 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 999 1000 /* This should be guaranteed via constraints */ 1001 tcg_debug_assert(v2 == ret); 1002 } 1003 } 1004 1005 static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1006 { 1007 /* Note that the ABI requires the called function's address to be 1008 loaded into T9, even if a direct branch is in range. */ 1009 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1010 1011 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1012 if (tail) { 1013 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1014 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1015 } 1016 } else { 1017 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1018 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1019 } 1020 } 1021 } 1022 1023 static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1024 { 1025 tcg_out_call_int(s, arg, false); 1026 tcg_out_nop(s); 1027 } 1028 1029 #if defined(CONFIG_SOFTMMU) 1030 static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = { 1031 [MO_UB] = helper_ret_ldub_mmu, 1032 [MO_SB] = helper_ret_ldsb_mmu, 1033 [MO_LEUW] = helper_le_lduw_mmu, 1034 [MO_LESW] = helper_le_ldsw_mmu, 1035 [MO_LEUL] = helper_le_ldul_mmu, 1036 [MO_LEUQ] = helper_le_ldq_mmu, 1037 [MO_BEUW] = helper_be_lduw_mmu, 1038 [MO_BESW] = helper_be_ldsw_mmu, 1039 [MO_BEUL] = helper_be_ldul_mmu, 1040 [MO_BEUQ] = helper_be_ldq_mmu, 1041 #if TCG_TARGET_REG_BITS == 64 1042 [MO_LESL] = helper_le_ldsl_mmu, 1043 [MO_BESL] = helper_be_ldsl_mmu, 1044 #endif 1045 }; 1046 1047 static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1048 [MO_UB] = helper_ret_stb_mmu, 1049 [MO_LEUW] = helper_le_stw_mmu, 1050 [MO_LEUL] = helper_le_stl_mmu, 1051 [MO_LEUQ] = helper_le_stq_mmu, 1052 [MO_BEUW] = helper_be_stw_mmu, 1053 [MO_BEUL] = helper_be_stl_mmu, 1054 [MO_BEUQ] = helper_be_stq_mmu, 1055 }; 1056 1057 /* Helper routines for marshalling helper function arguments into 1058 * the correct registers and stack. 1059 * I is where we want to put this argument, and is updated and returned 1060 * for the next call. ARG is the argument itself. 1061 * 1062 * We provide routines for arguments which are: immediate, 32 bit 1063 * value in register, 16 and 8 bit values in register (which must be zero 1064 * extended before use) and 64 bit value in a lo:hi register pair. 1065 */ 1066 1067 static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1068 { 1069 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1070 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1071 } else { 1072 /* For N32 and N64, the initial offset is different. But there 1073 we also have 8 argument register so we don't run out here. */ 1074 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1075 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1076 } 1077 return i + 1; 1078 } 1079 1080 static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1081 { 1082 TCGReg tmp = TCG_TMP0; 1083 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1084 tmp = tcg_target_call_iarg_regs[i]; 1085 } 1086 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1087 return tcg_out_call_iarg_reg(s, i, tmp); 1088 } 1089 1090 static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1091 { 1092 TCGReg tmp = TCG_TMP0; 1093 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1094 tmp = tcg_target_call_iarg_regs[i]; 1095 } 1096 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1097 return tcg_out_call_iarg_reg(s, i, tmp); 1098 } 1099 1100 static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1101 { 1102 TCGReg tmp = TCG_TMP0; 1103 if (arg == 0) { 1104 tmp = TCG_REG_ZERO; 1105 } else { 1106 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1107 tmp = tcg_target_call_iarg_regs[i]; 1108 } 1109 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1110 } 1111 return tcg_out_call_iarg_reg(s, i, tmp); 1112 } 1113 1114 static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1115 { 1116 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1117 i = (i + 1) & ~1; 1118 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1119 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1120 return i; 1121 } 1122 1123 /* We expect to use a 16-bit negative offset from ENV. */ 1124 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1125 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1126 1127 /* 1128 * Perform the tlb comparison operation. 1129 * The complete host address is placed in BASE. 1130 * Clobbers TMP0, TMP1, TMP2, TMP3. 1131 */ 1132 static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1133 TCGReg addrh, MemOpIdx oi, 1134 tcg_insn_unit *label_ptr[2], bool is_load) 1135 { 1136 MemOp opc = get_memop(oi); 1137 unsigned a_bits = get_alignment_bits(opc); 1138 unsigned s_bits = opc & MO_SIZE; 1139 unsigned a_mask = (1 << a_bits) - 1; 1140 unsigned s_mask = (1 << s_bits) - 1; 1141 int mem_index = get_mmuidx(oi); 1142 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1143 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1144 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1145 int add_off = offsetof(CPUTLBEntry, addend); 1146 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1147 : offsetof(CPUTLBEntry, addr_write)); 1148 target_ulong tlb_mask; 1149 1150 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1151 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1152 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1153 1154 /* Extract the TLB index from the address into TMP3. */ 1155 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1156 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1157 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1158 1159 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1160 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1161 1162 /* Load the (low-half) tlb comparator. */ 1163 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1164 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1165 } else { 1166 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1167 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1168 TCG_TMP0, TCG_TMP3, cmp_off); 1169 } 1170 1171 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1172 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1173 tcg_out_ext32u(s, base, addrl); 1174 addrl = base; 1175 } 1176 1177 /* 1178 * Mask the page bits, keeping the alignment bits to compare against. 1179 * For unaligned accesses, compare against the end of the access to 1180 * verify that it does not cross a page boundary. 1181 */ 1182 tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; 1183 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); 1184 if (a_mask >= s_mask) { 1185 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1186 } else { 1187 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); 1188 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1189 } 1190 1191 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 1192 /* Load the tlb addend for the fast path. */ 1193 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1194 } 1195 1196 label_ptr[0] = s->code_ptr; 1197 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1198 1199 /* Load and test the high half tlb comparator. */ 1200 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1201 /* delay slot */ 1202 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1203 1204 /* Load the tlb addend for the fast path. */ 1205 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1206 1207 label_ptr[1] = s->code_ptr; 1208 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1209 } 1210 1211 /* delay slot */ 1212 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1213 } 1214 1215 static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, 1216 TCGType ext, 1217 TCGReg datalo, TCGReg datahi, 1218 TCGReg addrlo, TCGReg addrhi, 1219 void *raddr, tcg_insn_unit *label_ptr[2]) 1220 { 1221 TCGLabelQemuLdst *label = new_ldst_label(s); 1222 1223 label->is_ld = is_ld; 1224 label->oi = oi; 1225 label->type = ext; 1226 label->datalo_reg = datalo; 1227 label->datahi_reg = datahi; 1228 label->addrlo_reg = addrlo; 1229 label->addrhi_reg = addrhi; 1230 label->raddr = tcg_splitwx_to_rx(raddr); 1231 label->label_ptr[0] = label_ptr[0]; 1232 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1233 label->label_ptr[1] = label_ptr[1]; 1234 } 1235 } 1236 1237 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1238 { 1239 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1240 MemOpIdx oi = l->oi; 1241 MemOp opc = get_memop(oi); 1242 TCGReg v0; 1243 int i; 1244 1245 /* resolve label address */ 1246 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1247 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1248 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1249 return false; 1250 } 1251 1252 i = 1; 1253 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1254 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1255 } else { 1256 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1257 } 1258 i = tcg_out_call_iarg_imm(s, i, oi); 1259 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1260 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1261 /* delay slot */ 1262 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1263 1264 v0 = l->datalo_reg; 1265 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1266 /* We eliminated V0 from the possible output registers, so it 1267 cannot be clobbered here. So we must move V1 first. */ 1268 if (MIPS_BE) { 1269 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1270 v0 = l->datahi_reg; 1271 } else { 1272 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1273 } 1274 } 1275 1276 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1277 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1278 return false; 1279 } 1280 1281 /* delay slot */ 1282 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1283 /* we always sign-extend 32-bit loads */ 1284 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1285 } else { 1286 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1287 } 1288 return true; 1289 } 1290 1291 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1292 { 1293 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1294 MemOpIdx oi = l->oi; 1295 MemOp opc = get_memop(oi); 1296 MemOp s_bits = opc & MO_SIZE; 1297 int i; 1298 1299 /* resolve label address */ 1300 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1301 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1302 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1303 return false; 1304 } 1305 1306 i = 1; 1307 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1308 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1309 } else { 1310 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1311 } 1312 switch (s_bits) { 1313 case MO_8: 1314 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1315 break; 1316 case MO_16: 1317 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1318 break; 1319 case MO_32: 1320 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1321 break; 1322 case MO_64: 1323 if (TCG_TARGET_REG_BITS == 32) { 1324 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1325 } else { 1326 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1327 } 1328 break; 1329 default: 1330 tcg_abort(); 1331 } 1332 i = tcg_out_call_iarg_imm(s, i, oi); 1333 1334 /* Tail call to the store helper. Thus force the return address 1335 computation to take place in the return address register. */ 1336 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1337 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1338 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1339 /* delay slot */ 1340 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1341 return true; 1342 } 1343 1344 #else 1345 1346 static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, 1347 TCGReg addrhi, unsigned a_bits) 1348 { 1349 unsigned a_mask = (1 << a_bits) - 1; 1350 TCGLabelQemuLdst *l = new_ldst_label(s); 1351 1352 l->is_ld = is_ld; 1353 l->addrlo_reg = addrlo; 1354 l->addrhi_reg = addrhi; 1355 1356 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1357 tcg_debug_assert(a_bits < 16); 1358 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1359 1360 l->label_ptr[0] = s->code_ptr; 1361 if (use_mips32r6_instructions) { 1362 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1363 } else { 1364 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1365 tcg_out_nop(s); 1366 } 1367 1368 l->raddr = tcg_splitwx_to_rx(s->code_ptr); 1369 } 1370 1371 static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1372 { 1373 void *target; 1374 1375 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1376 return false; 1377 } 1378 1379 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1380 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */ 1381 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg; 1382 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg; 1383 1384 if (a3 != TCG_REG_A2) { 1385 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); 1386 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); 1387 } else if (a2 != TCG_REG_A3) { 1388 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); 1389 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); 1390 } else { 1391 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2); 1392 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3); 1393 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0); 1394 } 1395 } else { 1396 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); 1397 } 1398 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 1399 1400 /* 1401 * Tail call to the helper, with the return address back inline. 1402 * We have arrived here via BNEL, so $31 is already set. 1403 */ 1404 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st); 1405 tcg_out_call_int(s, target, true); 1406 return true; 1407 } 1408 1409 static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1410 { 1411 return tcg_out_fail_alignment(s, l); 1412 } 1413 1414 static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1415 { 1416 return tcg_out_fail_alignment(s, l); 1417 } 1418 #endif /* SOFTMMU */ 1419 1420 static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1421 TCGReg base, MemOp opc, bool is_64) 1422 { 1423 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1424 case MO_UB: 1425 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1426 break; 1427 case MO_SB: 1428 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1429 break; 1430 case MO_UW | MO_BSWAP: 1431 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1432 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1433 break; 1434 case MO_UW: 1435 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1436 break; 1437 case MO_SW | MO_BSWAP: 1438 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1439 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); 1440 break; 1441 case MO_SW: 1442 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1443 break; 1444 case MO_UL | MO_BSWAP: 1445 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1446 if (use_mips32r2_instructions) { 1447 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1448 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1449 } else { 1450 tcg_out_bswap_subr(s, bswap32u_addr); 1451 /* delay slot */ 1452 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1453 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1454 } 1455 break; 1456 } 1457 /* FALLTHRU */ 1458 case MO_SL | MO_BSWAP: 1459 if (use_mips32r2_instructions) { 1460 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1461 tcg_out_bswap32(s, lo, lo, 0); 1462 } else { 1463 tcg_out_bswap_subr(s, bswap32_addr); 1464 /* delay slot */ 1465 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1466 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1467 } 1468 break; 1469 case MO_UL: 1470 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1471 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1472 break; 1473 } 1474 /* FALLTHRU */ 1475 case MO_SL: 1476 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1477 break; 1478 case MO_UQ | MO_BSWAP: 1479 if (TCG_TARGET_REG_BITS == 64) { 1480 if (use_mips32r2_instructions) { 1481 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1482 tcg_out_bswap64(s, lo, lo); 1483 } else { 1484 tcg_out_bswap_subr(s, bswap64_addr); 1485 /* delay slot */ 1486 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1487 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1488 } 1489 } else if (use_mips32r2_instructions) { 1490 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1491 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1492 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1493 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1494 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1495 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1496 } else { 1497 tcg_out_bswap_subr(s, bswap32_addr); 1498 /* delay slot */ 1499 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1500 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1501 tcg_out_bswap_subr(s, bswap32_addr); 1502 /* delay slot */ 1503 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1504 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1505 } 1506 break; 1507 case MO_UQ: 1508 /* Prefer to load from offset 0 first, but allow for overlap. */ 1509 if (TCG_TARGET_REG_BITS == 64) { 1510 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1511 } else if (MIPS_BE ? hi != base : lo == base) { 1512 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1513 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1514 } else { 1515 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1516 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1517 } 1518 break; 1519 default: 1520 tcg_abort(); 1521 } 1522 } 1523 1524 static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1525 TCGReg base, MemOp opc, bool is_64) 1526 { 1527 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; 1528 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; 1529 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR; 1530 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL; 1531 1532 bool sgn = (opc & MO_SIGN); 1533 1534 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1535 case MO_SW | MO_BE: 1536 case MO_UW | MO_BE: 1537 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1538 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1539 if (use_mips32r2_instructions) { 1540 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1541 } else { 1542 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1543 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1544 } 1545 break; 1546 1547 case MO_SW | MO_LE: 1548 case MO_UW | MO_LE: 1549 if (use_mips32r2_instructions && lo != base) { 1550 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1551 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1552 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1553 } else { 1554 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1555 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1556 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1557 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1558 } 1559 break; 1560 1561 case MO_SL: 1562 case MO_UL: 1563 tcg_out_opc_imm(s, lw1, lo, base, 0); 1564 tcg_out_opc_imm(s, lw2, lo, base, 3); 1565 if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) { 1566 tcg_out_ext32u(s, lo, lo); 1567 } 1568 break; 1569 1570 case MO_UL | MO_BSWAP: 1571 case MO_SL | MO_BSWAP: 1572 if (use_mips32r2_instructions) { 1573 tcg_out_opc_imm(s, lw1, lo, base, 0); 1574 tcg_out_opc_imm(s, lw2, lo, base, 3); 1575 tcg_out_bswap32(s, lo, lo, 1576 TCG_TARGET_REG_BITS == 64 && is_64 1577 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); 1578 } else { 1579 const tcg_insn_unit *subr = 1580 (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn 1581 ? bswap32u_addr : bswap32_addr); 1582 1583 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); 1584 tcg_out_bswap_subr(s, subr); 1585 /* delay slot */ 1586 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); 1587 tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3); 1588 } 1589 break; 1590 1591 case MO_UQ: 1592 if (TCG_TARGET_REG_BITS == 64) { 1593 tcg_out_opc_imm(s, ld1, lo, base, 0); 1594 tcg_out_opc_imm(s, ld2, lo, base, 7); 1595 } else { 1596 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); 1597 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); 1598 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); 1599 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); 1600 } 1601 break; 1602 1603 case MO_UQ | MO_BSWAP: 1604 if (TCG_TARGET_REG_BITS == 64) { 1605 if (use_mips32r2_instructions) { 1606 tcg_out_opc_imm(s, ld1, lo, base, 0); 1607 tcg_out_opc_imm(s, ld2, lo, base, 7); 1608 tcg_out_bswap64(s, lo, lo); 1609 } else { 1610 tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); 1611 tcg_out_bswap_subr(s, bswap64_addr); 1612 /* delay slot */ 1613 tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); 1614 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1615 } 1616 } else if (use_mips32r2_instructions) { 1617 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); 1618 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); 1619 tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); 1620 tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); 1621 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1622 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1623 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1624 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1625 } else { 1626 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); 1627 tcg_out_bswap_subr(s, bswap32_addr); 1628 /* delay slot */ 1629 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); 1630 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); 1631 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1632 tcg_out_bswap_subr(s, bswap32_addr); 1633 /* delay slot */ 1634 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); 1635 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1636 } 1637 break; 1638 1639 default: 1640 g_assert_not_reached(); 1641 } 1642 } 1643 1644 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1645 { 1646 TCGReg addr_regl, addr_regh __attribute__((unused)); 1647 TCGReg data_regl, data_regh; 1648 MemOpIdx oi; 1649 MemOp opc; 1650 #if defined(CONFIG_SOFTMMU) 1651 tcg_insn_unit *label_ptr[2]; 1652 #else 1653 #endif 1654 unsigned a_bits, s_bits; 1655 TCGReg base = TCG_REG_A0; 1656 1657 data_regl = *args++; 1658 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1659 addr_regl = *args++; 1660 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1661 oi = *args++; 1662 opc = get_memop(oi); 1663 a_bits = get_alignment_bits(opc); 1664 s_bits = opc & MO_SIZE; 1665 1666 /* 1667 * R6 removes the left/right instructions but requires the 1668 * system to support misaligned memory accesses. 1669 */ 1670 #if defined(CONFIG_SOFTMMU) 1671 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1672 if (use_mips32r6_instructions || a_bits >= s_bits) { 1673 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1674 } else { 1675 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); 1676 } 1677 add_qemu_ldst_label(s, 1, oi, 1678 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1679 data_regl, data_regh, addr_regl, addr_regh, 1680 s->code_ptr, label_ptr); 1681 #else 1682 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1683 tcg_out_ext32u(s, base, addr_regl); 1684 addr_regl = base; 1685 } 1686 if (guest_base == 0 && data_regl != addr_regl) { 1687 base = addr_regl; 1688 } else if (guest_base == (int16_t)guest_base) { 1689 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1690 } else { 1691 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1692 } 1693 if (use_mips32r6_instructions) { 1694 if (a_bits) { 1695 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1696 } 1697 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1698 } else { 1699 if (a_bits && a_bits != s_bits) { 1700 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1701 } 1702 if (a_bits >= s_bits) { 1703 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1704 } else { 1705 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); 1706 } 1707 } 1708 #endif 1709 } 1710 1711 static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1712 TCGReg base, MemOp opc) 1713 { 1714 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1715 if ((lo | hi) == 0) { 1716 opc &= ~MO_BSWAP; 1717 } 1718 1719 switch (opc & (MO_SIZE | MO_BSWAP)) { 1720 case MO_8: 1721 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1722 break; 1723 1724 case MO_16 | MO_BSWAP: 1725 tcg_out_bswap16(s, TCG_TMP1, lo, 0); 1726 lo = TCG_TMP1; 1727 /* FALLTHRU */ 1728 case MO_16: 1729 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1730 break; 1731 1732 case MO_32 | MO_BSWAP: 1733 tcg_out_bswap32(s, TCG_TMP3, lo, 0); 1734 lo = TCG_TMP3; 1735 /* FALLTHRU */ 1736 case MO_32: 1737 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1738 break; 1739 1740 case MO_64 | MO_BSWAP: 1741 if (TCG_TARGET_REG_BITS == 64) { 1742 tcg_out_bswap64(s, TCG_TMP3, lo); 1743 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1744 } else if (use_mips32r2_instructions) { 1745 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1746 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1747 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1748 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1749 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1750 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1751 } else { 1752 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); 1753 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1754 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); 1755 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1756 } 1757 break; 1758 case MO_64: 1759 if (TCG_TARGET_REG_BITS == 64) { 1760 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1761 } else { 1762 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1763 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1764 } 1765 break; 1766 1767 default: 1768 tcg_abort(); 1769 } 1770 } 1771 1772 static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1773 TCGReg base, MemOp opc) 1774 { 1775 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; 1776 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL; 1777 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR; 1778 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL; 1779 1780 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1781 if ((lo | hi) == 0) { 1782 opc &= ~MO_BSWAP; 1783 } 1784 1785 switch (opc & (MO_SIZE | MO_BSWAP)) { 1786 case MO_16 | MO_BE: 1787 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1788 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); 1789 tcg_out_opc_imm(s, OPC_SB, lo, base, 1); 1790 break; 1791 1792 case MO_16 | MO_LE: 1793 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1794 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1795 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); 1796 break; 1797 1798 case MO_32 | MO_BSWAP: 1799 tcg_out_bswap32(s, TCG_TMP3, lo, 0); 1800 lo = TCG_TMP3; 1801 /* fall through */ 1802 case MO_32: 1803 tcg_out_opc_imm(s, sw1, lo, base, 0); 1804 tcg_out_opc_imm(s, sw2, lo, base, 3); 1805 break; 1806 1807 case MO_64 | MO_BSWAP: 1808 if (TCG_TARGET_REG_BITS == 64) { 1809 tcg_out_bswap64(s, TCG_TMP3, lo); 1810 lo = TCG_TMP3; 1811 } else if (use_mips32r2_instructions) { 1812 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); 1813 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); 1814 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1815 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1816 hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1; 1817 lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0; 1818 } else { 1819 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); 1820 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0); 1821 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3); 1822 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); 1823 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0); 1824 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3); 1825 break; 1826 } 1827 /* fall through */ 1828 case MO_64: 1829 if (TCG_TARGET_REG_BITS == 64) { 1830 tcg_out_opc_imm(s, sd1, lo, base, 0); 1831 tcg_out_opc_imm(s, sd2, lo, base, 7); 1832 } else { 1833 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0); 1834 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3); 1835 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0); 1836 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3); 1837 } 1838 break; 1839 1840 default: 1841 tcg_abort(); 1842 } 1843 } 1844 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1845 { 1846 TCGReg addr_regl, addr_regh __attribute__((unused)); 1847 TCGReg data_regl, data_regh; 1848 MemOpIdx oi; 1849 MemOp opc; 1850 #if defined(CONFIG_SOFTMMU) 1851 tcg_insn_unit *label_ptr[2]; 1852 #endif 1853 unsigned a_bits, s_bits; 1854 TCGReg base = TCG_REG_A0; 1855 1856 data_regl = *args++; 1857 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1858 addr_regl = *args++; 1859 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1860 oi = *args++; 1861 opc = get_memop(oi); 1862 a_bits = get_alignment_bits(opc); 1863 s_bits = opc & MO_SIZE; 1864 1865 /* 1866 * R6 removes the left/right instructions but requires the 1867 * system to support misaligned memory accesses. 1868 */ 1869 #if defined(CONFIG_SOFTMMU) 1870 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1871 if (use_mips32r6_instructions || a_bits >= s_bits) { 1872 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1873 } else { 1874 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); 1875 } 1876 add_qemu_ldst_label(s, 0, oi, 1877 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1878 data_regl, data_regh, addr_regl, addr_regh, 1879 s->code_ptr, label_ptr); 1880 #else 1881 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1882 tcg_out_ext32u(s, base, addr_regl); 1883 addr_regl = base; 1884 } 1885 if (guest_base == 0) { 1886 base = addr_regl; 1887 } else if (guest_base == (int16_t)guest_base) { 1888 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1889 } else { 1890 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1891 } 1892 if (use_mips32r6_instructions) { 1893 if (a_bits) { 1894 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1895 } 1896 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1897 } else { 1898 if (a_bits && a_bits != s_bits) { 1899 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1900 } 1901 if (a_bits >= s_bits) { 1902 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1903 } else { 1904 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); 1905 } 1906 } 1907 #endif 1908 } 1909 1910 static void tcg_out_mb(TCGContext *s, TCGArg a0) 1911 { 1912 static const MIPSInsn sync[] = { 1913 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1914 as the former is an ordering barrier and the latter 1915 is a completion barrier. */ 1916 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1917 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1918 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1919 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1920 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1921 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1922 }; 1923 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1924 } 1925 1926 static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1927 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1928 { 1929 if (use_mips32r6_instructions) { 1930 if (a2 == width) { 1931 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1932 } else { 1933 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1934 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1935 } 1936 } else { 1937 if (a2 == width) { 1938 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1939 } else if (a0 == a2) { 1940 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1941 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1942 } else if (a0 != a1) { 1943 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1944 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1945 } else { 1946 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1947 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1948 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1949 } 1950 } 1951 } 1952 1953 static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1954 const TCGArg args[TCG_MAX_OP_ARGS], 1955 const int const_args[TCG_MAX_OP_ARGS]) 1956 { 1957 MIPSInsn i1, i2; 1958 TCGArg a0, a1, a2; 1959 int c2; 1960 1961 /* 1962 * Note that many operands use the constraint set "rZ". 1963 * We make use of the fact that 0 is the ZERO register, 1964 * and hence such cases need not check for const_args. 1965 */ 1966 a0 = args[0]; 1967 a1 = args[1]; 1968 a2 = args[2]; 1969 c2 = const_args[2]; 1970 1971 switch (opc) { 1972 case INDEX_op_exit_tb: 1973 { 1974 TCGReg b0 = TCG_REG_ZERO; 1975 1976 a0 = (intptr_t)a0; 1977 if (a0 & ~0xffff) { 1978 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1979 b0 = TCG_REG_V0; 1980 } 1981 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1982 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1983 (uintptr_t)tb_ret_addr); 1984 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1985 } 1986 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1987 } 1988 break; 1989 case INDEX_op_goto_tb: 1990 /* indirect jump method */ 1991 tcg_debug_assert(s->tb_jmp_insn_offset == 0); 1992 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1993 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1994 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1995 tcg_out_nop(s); 1996 set_jmp_reset_offset(s, a0); 1997 break; 1998 case INDEX_op_goto_ptr: 1999 /* jmp to the given host address (could be epilogue) */ 2000 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2001 tcg_out_nop(s); 2002 break; 2003 case INDEX_op_br: 2004 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 2005 arg_label(a0)); 2006 break; 2007 2008 case INDEX_op_ld8u_i32: 2009 case INDEX_op_ld8u_i64: 2010 i1 = OPC_LBU; 2011 goto do_ldst; 2012 case INDEX_op_ld8s_i32: 2013 case INDEX_op_ld8s_i64: 2014 i1 = OPC_LB; 2015 goto do_ldst; 2016 case INDEX_op_ld16u_i32: 2017 case INDEX_op_ld16u_i64: 2018 i1 = OPC_LHU; 2019 goto do_ldst; 2020 case INDEX_op_ld16s_i32: 2021 case INDEX_op_ld16s_i64: 2022 i1 = OPC_LH; 2023 goto do_ldst; 2024 case INDEX_op_ld_i32: 2025 case INDEX_op_ld32s_i64: 2026 i1 = OPC_LW; 2027 goto do_ldst; 2028 case INDEX_op_ld32u_i64: 2029 i1 = OPC_LWU; 2030 goto do_ldst; 2031 case INDEX_op_ld_i64: 2032 i1 = OPC_LD; 2033 goto do_ldst; 2034 case INDEX_op_st8_i32: 2035 case INDEX_op_st8_i64: 2036 i1 = OPC_SB; 2037 goto do_ldst; 2038 case INDEX_op_st16_i32: 2039 case INDEX_op_st16_i64: 2040 i1 = OPC_SH; 2041 goto do_ldst; 2042 case INDEX_op_st_i32: 2043 case INDEX_op_st32_i64: 2044 i1 = OPC_SW; 2045 goto do_ldst; 2046 case INDEX_op_st_i64: 2047 i1 = OPC_SD; 2048 do_ldst: 2049 tcg_out_ldst(s, i1, a0, a1, a2); 2050 break; 2051 2052 case INDEX_op_add_i32: 2053 i1 = OPC_ADDU, i2 = OPC_ADDIU; 2054 goto do_binary; 2055 case INDEX_op_add_i64: 2056 i1 = OPC_DADDU, i2 = OPC_DADDIU; 2057 goto do_binary; 2058 case INDEX_op_or_i32: 2059 case INDEX_op_or_i64: 2060 i1 = OPC_OR, i2 = OPC_ORI; 2061 goto do_binary; 2062 case INDEX_op_xor_i32: 2063 case INDEX_op_xor_i64: 2064 i1 = OPC_XOR, i2 = OPC_XORI; 2065 do_binary: 2066 if (c2) { 2067 tcg_out_opc_imm(s, i2, a0, a1, a2); 2068 break; 2069 } 2070 do_binaryv: 2071 tcg_out_opc_reg(s, i1, a0, a1, a2); 2072 break; 2073 2074 case INDEX_op_sub_i32: 2075 i1 = OPC_SUBU, i2 = OPC_ADDIU; 2076 goto do_subtract; 2077 case INDEX_op_sub_i64: 2078 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 2079 do_subtract: 2080 if (c2) { 2081 tcg_out_opc_imm(s, i2, a0, a1, -a2); 2082 break; 2083 } 2084 goto do_binaryv; 2085 case INDEX_op_and_i32: 2086 if (c2 && a2 != (uint16_t)a2) { 2087 int msb = ctz32(~a2) - 1; 2088 tcg_debug_assert(use_mips32r2_instructions); 2089 tcg_debug_assert(is_p2m1(a2)); 2090 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 2091 break; 2092 } 2093 i1 = OPC_AND, i2 = OPC_ANDI; 2094 goto do_binary; 2095 case INDEX_op_and_i64: 2096 if (c2 && a2 != (uint16_t)a2) { 2097 int msb = ctz64(~a2) - 1; 2098 tcg_debug_assert(use_mips32r2_instructions); 2099 tcg_debug_assert(is_p2m1(a2)); 2100 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 2101 break; 2102 } 2103 i1 = OPC_AND, i2 = OPC_ANDI; 2104 goto do_binary; 2105 case INDEX_op_nor_i32: 2106 case INDEX_op_nor_i64: 2107 i1 = OPC_NOR; 2108 goto do_binaryv; 2109 2110 case INDEX_op_mul_i32: 2111 if (use_mips32_instructions) { 2112 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 2113 break; 2114 } 2115 i1 = OPC_MULT, i2 = OPC_MFLO; 2116 goto do_hilo1; 2117 case INDEX_op_mulsh_i32: 2118 if (use_mips32r6_instructions) { 2119 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 2120 break; 2121 } 2122 i1 = OPC_MULT, i2 = OPC_MFHI; 2123 goto do_hilo1; 2124 case INDEX_op_muluh_i32: 2125 if (use_mips32r6_instructions) { 2126 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 2127 break; 2128 } 2129 i1 = OPC_MULTU, i2 = OPC_MFHI; 2130 goto do_hilo1; 2131 case INDEX_op_div_i32: 2132 if (use_mips32r6_instructions) { 2133 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 2134 break; 2135 } 2136 i1 = OPC_DIV, i2 = OPC_MFLO; 2137 goto do_hilo1; 2138 case INDEX_op_divu_i32: 2139 if (use_mips32r6_instructions) { 2140 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 2141 break; 2142 } 2143 i1 = OPC_DIVU, i2 = OPC_MFLO; 2144 goto do_hilo1; 2145 case INDEX_op_rem_i32: 2146 if (use_mips32r6_instructions) { 2147 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 2148 break; 2149 } 2150 i1 = OPC_DIV, i2 = OPC_MFHI; 2151 goto do_hilo1; 2152 case INDEX_op_remu_i32: 2153 if (use_mips32r6_instructions) { 2154 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 2155 break; 2156 } 2157 i1 = OPC_DIVU, i2 = OPC_MFHI; 2158 goto do_hilo1; 2159 case INDEX_op_mul_i64: 2160 if (use_mips32r6_instructions) { 2161 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 2162 break; 2163 } 2164 i1 = OPC_DMULT, i2 = OPC_MFLO; 2165 goto do_hilo1; 2166 case INDEX_op_mulsh_i64: 2167 if (use_mips32r6_instructions) { 2168 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 2169 break; 2170 } 2171 i1 = OPC_DMULT, i2 = OPC_MFHI; 2172 goto do_hilo1; 2173 case INDEX_op_muluh_i64: 2174 if (use_mips32r6_instructions) { 2175 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 2176 break; 2177 } 2178 i1 = OPC_DMULTU, i2 = OPC_MFHI; 2179 goto do_hilo1; 2180 case INDEX_op_div_i64: 2181 if (use_mips32r6_instructions) { 2182 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 2183 break; 2184 } 2185 i1 = OPC_DDIV, i2 = OPC_MFLO; 2186 goto do_hilo1; 2187 case INDEX_op_divu_i64: 2188 if (use_mips32r6_instructions) { 2189 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 2190 break; 2191 } 2192 i1 = OPC_DDIVU, i2 = OPC_MFLO; 2193 goto do_hilo1; 2194 case INDEX_op_rem_i64: 2195 if (use_mips32r6_instructions) { 2196 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 2197 break; 2198 } 2199 i1 = OPC_DDIV, i2 = OPC_MFHI; 2200 goto do_hilo1; 2201 case INDEX_op_remu_i64: 2202 if (use_mips32r6_instructions) { 2203 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 2204 break; 2205 } 2206 i1 = OPC_DDIVU, i2 = OPC_MFHI; 2207 do_hilo1: 2208 tcg_out_opc_reg(s, i1, 0, a1, a2); 2209 tcg_out_opc_reg(s, i2, a0, 0, 0); 2210 break; 2211 2212 case INDEX_op_muls2_i32: 2213 i1 = OPC_MULT; 2214 goto do_hilo2; 2215 case INDEX_op_mulu2_i32: 2216 i1 = OPC_MULTU; 2217 goto do_hilo2; 2218 case INDEX_op_muls2_i64: 2219 i1 = OPC_DMULT; 2220 goto do_hilo2; 2221 case INDEX_op_mulu2_i64: 2222 i1 = OPC_DMULTU; 2223 do_hilo2: 2224 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 2225 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 2226 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 2227 break; 2228 2229 case INDEX_op_not_i32: 2230 case INDEX_op_not_i64: 2231 i1 = OPC_NOR; 2232 goto do_unary; 2233 case INDEX_op_ext8s_i32: 2234 case INDEX_op_ext8s_i64: 2235 i1 = OPC_SEB; 2236 goto do_unary; 2237 case INDEX_op_ext16s_i32: 2238 case INDEX_op_ext16s_i64: 2239 i1 = OPC_SEH; 2240 do_unary: 2241 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 2242 break; 2243 2244 case INDEX_op_bswap16_i32: 2245 case INDEX_op_bswap16_i64: 2246 tcg_out_bswap16(s, a0, a1, a2); 2247 break; 2248 case INDEX_op_bswap32_i32: 2249 tcg_out_bswap32(s, a0, a1, 0); 2250 break; 2251 case INDEX_op_bswap32_i64: 2252 tcg_out_bswap32(s, a0, a1, a2); 2253 break; 2254 case INDEX_op_bswap64_i64: 2255 tcg_out_bswap64(s, a0, a1); 2256 break; 2257 case INDEX_op_extrh_i64_i32: 2258 tcg_out_dsra(s, a0, a1, 32); 2259 break; 2260 case INDEX_op_ext32s_i64: 2261 case INDEX_op_ext_i32_i64: 2262 case INDEX_op_extrl_i64_i32: 2263 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 2264 break; 2265 case INDEX_op_ext32u_i64: 2266 case INDEX_op_extu_i32_i64: 2267 tcg_out_ext32u(s, a0, a1); 2268 break; 2269 2270 case INDEX_op_sar_i32: 2271 i1 = OPC_SRAV, i2 = OPC_SRA; 2272 goto do_shift; 2273 case INDEX_op_shl_i32: 2274 i1 = OPC_SLLV, i2 = OPC_SLL; 2275 goto do_shift; 2276 case INDEX_op_shr_i32: 2277 i1 = OPC_SRLV, i2 = OPC_SRL; 2278 goto do_shift; 2279 case INDEX_op_rotr_i32: 2280 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2281 do_shift: 2282 if (c2) { 2283 tcg_out_opc_sa(s, i2, a0, a1, a2); 2284 break; 2285 } 2286 do_shiftv: 2287 tcg_out_opc_reg(s, i1, a0, a2, a1); 2288 break; 2289 case INDEX_op_rotl_i32: 2290 if (c2) { 2291 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2292 } else { 2293 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2294 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2295 } 2296 break; 2297 case INDEX_op_sar_i64: 2298 if (c2) { 2299 tcg_out_dsra(s, a0, a1, a2); 2300 break; 2301 } 2302 i1 = OPC_DSRAV; 2303 goto do_shiftv; 2304 case INDEX_op_shl_i64: 2305 if (c2) { 2306 tcg_out_dsll(s, a0, a1, a2); 2307 break; 2308 } 2309 i1 = OPC_DSLLV; 2310 goto do_shiftv; 2311 case INDEX_op_shr_i64: 2312 if (c2) { 2313 tcg_out_dsrl(s, a0, a1, a2); 2314 break; 2315 } 2316 i1 = OPC_DSRLV; 2317 goto do_shiftv; 2318 case INDEX_op_rotr_i64: 2319 if (c2) { 2320 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2321 break; 2322 } 2323 i1 = OPC_DROTRV; 2324 goto do_shiftv; 2325 case INDEX_op_rotl_i64: 2326 if (c2) { 2327 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2328 } else { 2329 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2330 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2331 } 2332 break; 2333 2334 case INDEX_op_clz_i32: 2335 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2336 break; 2337 case INDEX_op_clz_i64: 2338 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2339 break; 2340 2341 case INDEX_op_deposit_i32: 2342 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2343 break; 2344 case INDEX_op_deposit_i64: 2345 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2346 args[3] + args[4] - 1, args[3]); 2347 break; 2348 case INDEX_op_extract_i32: 2349 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2350 break; 2351 case INDEX_op_extract_i64: 2352 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2353 args[3] - 1, a2); 2354 break; 2355 2356 case INDEX_op_brcond_i32: 2357 case INDEX_op_brcond_i64: 2358 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2359 break; 2360 case INDEX_op_brcond2_i32: 2361 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2362 break; 2363 2364 case INDEX_op_movcond_i32: 2365 case INDEX_op_movcond_i64: 2366 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2367 break; 2368 2369 case INDEX_op_setcond_i32: 2370 case INDEX_op_setcond_i64: 2371 tcg_out_setcond(s, args[3], a0, a1, a2); 2372 break; 2373 case INDEX_op_setcond2_i32: 2374 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2375 break; 2376 2377 case INDEX_op_qemu_ld_i32: 2378 tcg_out_qemu_ld(s, args, false); 2379 break; 2380 case INDEX_op_qemu_ld_i64: 2381 tcg_out_qemu_ld(s, args, true); 2382 break; 2383 case INDEX_op_qemu_st_i32: 2384 tcg_out_qemu_st(s, args, false); 2385 break; 2386 case INDEX_op_qemu_st_i64: 2387 tcg_out_qemu_st(s, args, true); 2388 break; 2389 2390 case INDEX_op_add2_i32: 2391 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2392 const_args[4], const_args[5], false); 2393 break; 2394 case INDEX_op_sub2_i32: 2395 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2396 const_args[4], const_args[5], true); 2397 break; 2398 2399 case INDEX_op_mb: 2400 tcg_out_mb(s, a0); 2401 break; 2402 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2403 case INDEX_op_mov_i64: 2404 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2405 default: 2406 tcg_abort(); 2407 } 2408 } 2409 2410 static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2411 { 2412 switch (op) { 2413 case INDEX_op_goto_ptr: 2414 return C_O0_I1(r); 2415 2416 case INDEX_op_ld8u_i32: 2417 case INDEX_op_ld8s_i32: 2418 case INDEX_op_ld16u_i32: 2419 case INDEX_op_ld16s_i32: 2420 case INDEX_op_ld_i32: 2421 case INDEX_op_not_i32: 2422 case INDEX_op_bswap16_i32: 2423 case INDEX_op_bswap32_i32: 2424 case INDEX_op_ext8s_i32: 2425 case INDEX_op_ext16s_i32: 2426 case INDEX_op_extract_i32: 2427 case INDEX_op_ld8u_i64: 2428 case INDEX_op_ld8s_i64: 2429 case INDEX_op_ld16u_i64: 2430 case INDEX_op_ld16s_i64: 2431 case INDEX_op_ld32s_i64: 2432 case INDEX_op_ld32u_i64: 2433 case INDEX_op_ld_i64: 2434 case INDEX_op_not_i64: 2435 case INDEX_op_bswap16_i64: 2436 case INDEX_op_bswap32_i64: 2437 case INDEX_op_bswap64_i64: 2438 case INDEX_op_ext8s_i64: 2439 case INDEX_op_ext16s_i64: 2440 case INDEX_op_ext32s_i64: 2441 case INDEX_op_ext32u_i64: 2442 case INDEX_op_ext_i32_i64: 2443 case INDEX_op_extu_i32_i64: 2444 case INDEX_op_extrl_i64_i32: 2445 case INDEX_op_extrh_i64_i32: 2446 case INDEX_op_extract_i64: 2447 return C_O1_I1(r, r); 2448 2449 case INDEX_op_st8_i32: 2450 case INDEX_op_st16_i32: 2451 case INDEX_op_st_i32: 2452 case INDEX_op_st8_i64: 2453 case INDEX_op_st16_i64: 2454 case INDEX_op_st32_i64: 2455 case INDEX_op_st_i64: 2456 return C_O0_I2(rZ, r); 2457 2458 case INDEX_op_add_i32: 2459 case INDEX_op_add_i64: 2460 return C_O1_I2(r, r, rJ); 2461 case INDEX_op_sub_i32: 2462 case INDEX_op_sub_i64: 2463 return C_O1_I2(r, rZ, rN); 2464 case INDEX_op_mul_i32: 2465 case INDEX_op_mulsh_i32: 2466 case INDEX_op_muluh_i32: 2467 case INDEX_op_div_i32: 2468 case INDEX_op_divu_i32: 2469 case INDEX_op_rem_i32: 2470 case INDEX_op_remu_i32: 2471 case INDEX_op_nor_i32: 2472 case INDEX_op_setcond_i32: 2473 case INDEX_op_mul_i64: 2474 case INDEX_op_mulsh_i64: 2475 case INDEX_op_muluh_i64: 2476 case INDEX_op_div_i64: 2477 case INDEX_op_divu_i64: 2478 case INDEX_op_rem_i64: 2479 case INDEX_op_remu_i64: 2480 case INDEX_op_nor_i64: 2481 case INDEX_op_setcond_i64: 2482 return C_O1_I2(r, rZ, rZ); 2483 case INDEX_op_muls2_i32: 2484 case INDEX_op_mulu2_i32: 2485 case INDEX_op_muls2_i64: 2486 case INDEX_op_mulu2_i64: 2487 return C_O2_I2(r, r, r, r); 2488 case INDEX_op_and_i32: 2489 case INDEX_op_and_i64: 2490 return C_O1_I2(r, r, rIK); 2491 case INDEX_op_or_i32: 2492 case INDEX_op_xor_i32: 2493 case INDEX_op_or_i64: 2494 case INDEX_op_xor_i64: 2495 return C_O1_I2(r, r, rI); 2496 case INDEX_op_shl_i32: 2497 case INDEX_op_shr_i32: 2498 case INDEX_op_sar_i32: 2499 case INDEX_op_rotr_i32: 2500 case INDEX_op_rotl_i32: 2501 case INDEX_op_shl_i64: 2502 case INDEX_op_shr_i64: 2503 case INDEX_op_sar_i64: 2504 case INDEX_op_rotr_i64: 2505 case INDEX_op_rotl_i64: 2506 return C_O1_I2(r, r, ri); 2507 case INDEX_op_clz_i32: 2508 case INDEX_op_clz_i64: 2509 return C_O1_I2(r, r, rWZ); 2510 2511 case INDEX_op_deposit_i32: 2512 case INDEX_op_deposit_i64: 2513 return C_O1_I2(r, 0, rZ); 2514 case INDEX_op_brcond_i32: 2515 case INDEX_op_brcond_i64: 2516 return C_O0_I2(rZ, rZ); 2517 case INDEX_op_movcond_i32: 2518 case INDEX_op_movcond_i64: 2519 return (use_mips32r6_instructions 2520 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2521 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2522 case INDEX_op_add2_i32: 2523 case INDEX_op_sub2_i32: 2524 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2525 case INDEX_op_setcond2_i32: 2526 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2527 case INDEX_op_brcond2_i32: 2528 return C_O0_I4(rZ, rZ, rZ, rZ); 2529 2530 case INDEX_op_qemu_ld_i32: 2531 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2532 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 2533 case INDEX_op_qemu_st_i32: 2534 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2535 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); 2536 case INDEX_op_qemu_ld_i64: 2537 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 2538 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) 2539 : C_O2_I2(r, r, L, L)); 2540 case INDEX_op_qemu_st_i64: 2541 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) 2542 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) 2543 : C_O0_I4(SZ, SZ, S, S)); 2544 2545 default: 2546 g_assert_not_reached(); 2547 } 2548 } 2549 2550 static const int tcg_target_callee_save_regs[] = { 2551 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2552 TCG_REG_S1, 2553 TCG_REG_S2, 2554 TCG_REG_S3, 2555 TCG_REG_S4, 2556 TCG_REG_S5, 2557 TCG_REG_S6, 2558 TCG_REG_S7, 2559 TCG_REG_S8, 2560 TCG_REG_RA, /* should be last for ABI compliance */ 2561 }; 2562 2563 /* The Linux kernel doesn't provide any information about the available 2564 instruction set. Probe it using a signal handler. */ 2565 2566 2567 #ifndef use_movnz_instructions 2568 bool use_movnz_instructions = false; 2569 #endif 2570 2571 #ifndef use_mips32_instructions 2572 bool use_mips32_instructions = false; 2573 #endif 2574 2575 #ifndef use_mips32r2_instructions 2576 bool use_mips32r2_instructions = false; 2577 #endif 2578 2579 static volatile sig_atomic_t got_sigill; 2580 2581 static void sigill_handler(int signo, siginfo_t *si, void *data) 2582 { 2583 /* Skip the faulty instruction */ 2584 ucontext_t *uc = (ucontext_t *)data; 2585 uc->uc_mcontext.pc += 4; 2586 2587 got_sigill = 1; 2588 } 2589 2590 static void tcg_target_detect_isa(void) 2591 { 2592 struct sigaction sa_old, sa_new; 2593 2594 memset(&sa_new, 0, sizeof(sa_new)); 2595 sa_new.sa_flags = SA_SIGINFO; 2596 sa_new.sa_sigaction = sigill_handler; 2597 sigaction(SIGILL, &sa_new, &sa_old); 2598 2599 /* Probe for movn/movz, necessary to implement movcond. */ 2600 #ifndef use_movnz_instructions 2601 got_sigill = 0; 2602 asm volatile(".set push\n" 2603 ".set mips32\n" 2604 "movn $zero, $zero, $zero\n" 2605 "movz $zero, $zero, $zero\n" 2606 ".set pop\n" 2607 : : : ); 2608 use_movnz_instructions = !got_sigill; 2609 #endif 2610 2611 /* Probe for MIPS32 instructions. As no subsetting is allowed 2612 by the specification, it is only necessary to probe for one 2613 of the instructions. */ 2614 #ifndef use_mips32_instructions 2615 got_sigill = 0; 2616 asm volatile(".set push\n" 2617 ".set mips32\n" 2618 "mul $zero, $zero\n" 2619 ".set pop\n" 2620 : : : ); 2621 use_mips32_instructions = !got_sigill; 2622 #endif 2623 2624 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2625 available. As no subsetting is allowed by the specification, 2626 it is only necessary to probe for one of the instructions. */ 2627 #ifndef use_mips32r2_instructions 2628 if (use_mips32_instructions) { 2629 got_sigill = 0; 2630 asm volatile(".set push\n" 2631 ".set mips32r2\n" 2632 "seb $zero, $zero\n" 2633 ".set pop\n" 2634 : : : ); 2635 use_mips32r2_instructions = !got_sigill; 2636 } 2637 #endif 2638 2639 sigaction(SIGILL, &sa_old, NULL); 2640 } 2641 2642 static tcg_insn_unit *align_code_ptr(TCGContext *s) 2643 { 2644 uintptr_t p = (uintptr_t)s->code_ptr; 2645 if (p & 15) { 2646 p = (p + 15) & -16; 2647 s->code_ptr = (void *)p; 2648 } 2649 return s->code_ptr; 2650 } 2651 2652 /* Stack frame parameters. */ 2653 #define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2654 #define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2655 #define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2656 2657 #define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2658 + TCG_TARGET_STACK_ALIGN - 1) \ 2659 & -TCG_TARGET_STACK_ALIGN) 2660 #define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2661 2662 /* We're expecting to be able to use an immediate for frame allocation. */ 2663 QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2664 2665 /* Generate global QEMU prologue and epilogue code */ 2666 static void tcg_target_qemu_prologue(TCGContext *s) 2667 { 2668 int i; 2669 2670 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2671 2672 /* TB prologue */ 2673 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2674 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2675 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2676 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2677 } 2678 2679 #ifndef CONFIG_SOFTMMU 2680 if (guest_base) { 2681 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2682 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2683 } 2684 #endif 2685 2686 /* Call generated code */ 2687 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2688 /* delay slot */ 2689 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2690 2691 /* 2692 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2693 * and fall through to the rest of the epilogue. 2694 */ 2695 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2696 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2697 2698 /* TB epilogue */ 2699 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2700 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2701 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2702 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2703 } 2704 2705 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2706 /* delay slot */ 2707 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2708 2709 if (use_mips32r2_instructions) { 2710 return; 2711 } 2712 2713 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2714 clobbers TCG_TMP1, TCG_TMP2. */ 2715 2716 /* 2717 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2718 */ 2719 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2720 /* t3 = (ssss)d000 */ 2721 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2722 /* t1 = 000a */ 2723 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2724 /* t2 = 00c0 */ 2725 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2726 /* t3 = d00a */ 2727 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2728 /* t1 = 0abc */ 2729 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2730 /* t2 = 0c00 */ 2731 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2732 /* t1 = 00b0 */ 2733 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2734 /* t3 = dc0a */ 2735 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2736 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2737 /* t3 = dcba -- delay slot */ 2738 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2739 2740 if (TCG_TARGET_REG_BITS == 32) { 2741 return; 2742 } 2743 2744 /* 2745 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2746 */ 2747 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2748 /* t1 = (0000)000d */ 2749 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2750 /* t3 = 000a */ 2751 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2752 /* t1 = (0000)d000 */ 2753 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2754 /* t2 = 00c0 */ 2755 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2756 /* t3 = d00a */ 2757 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2758 /* t1 = 0abc */ 2759 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2760 /* t2 = 0c00 */ 2761 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2762 /* t1 = 00b0 */ 2763 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2764 /* t3 = dc0a */ 2765 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2766 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2767 /* t3 = dcba -- delay slot */ 2768 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2769 2770 /* 2771 * bswap64 -- 64-bit swap. a0 = abcdefgh 2772 */ 2773 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2774 /* t3 = h0000000 */ 2775 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2776 /* t1 = 0000000a */ 2777 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2778 2779 /* t2 = 000000g0 */ 2780 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2781 /* t3 = h000000a */ 2782 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2783 /* t1 = 00000abc */ 2784 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2785 /* t2 = 0g000000 */ 2786 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2787 /* t1 = 000000b0 */ 2788 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2789 2790 /* t3 = hg00000a */ 2791 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2792 /* t2 = 0000abcd */ 2793 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2794 /* t3 = hg0000ba */ 2795 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2796 2797 /* t1 = 000000c0 */ 2798 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2799 /* t2 = 0000000d */ 2800 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2801 /* t1 = 00000c00 */ 2802 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2803 /* t2 = 0000d000 */ 2804 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2805 2806 /* t3 = hg000cba */ 2807 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2808 /* t1 = 00abcdef */ 2809 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2810 /* t3 = hg00dcba */ 2811 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2812 2813 /* t2 = 0000000f */ 2814 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2815 /* t1 = 000000e0 */ 2816 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2817 /* t2 = 00f00000 */ 2818 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2819 /* t1 = 000e0000 */ 2820 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2821 2822 /* t3 = hgf0dcba */ 2823 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2824 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2825 /* t3 = hgfedcba -- delay slot */ 2826 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2827 } 2828 2829 static void tcg_target_init(TCGContext *s) 2830 { 2831 tcg_target_detect_isa(); 2832 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2833 if (TCG_TARGET_REG_BITS == 64) { 2834 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2835 } 2836 2837 tcg_target_call_clobber_regs = 0; 2838 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2839 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2840 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2841 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2842 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2843 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2844 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2845 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2846 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2847 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2848 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2849 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2850 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2851 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2852 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2853 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2854 2855 s->reserved_regs = 0; 2856 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2857 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2858 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2859 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2860 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2861 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2862 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2863 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2864 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2865 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2866 } 2867 2868 typedef struct { 2869 DebugFrameHeader h; 2870 uint8_t fde_def_cfa[4]; 2871 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2872 } DebugFrame; 2873 2874 #define ELF_HOST_MACHINE EM_MIPS 2875 /* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2876 which is good because they're really quite complicated for MIPS. */ 2877 2878 static const DebugFrame debug_frame = { 2879 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2880 .h.cie.id = -1, 2881 .h.cie.version = 1, 2882 .h.cie.code_align = 1, 2883 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2884 .h.cie.return_column = TCG_REG_RA, 2885 2886 /* Total FDE size does not include the "len" member. */ 2887 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2888 2889 .fde_def_cfa = { 2890 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2891 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2892 (FRAME_SIZE >> 7) 2893 }, 2894 .fde_reg_ofs = { 2895 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2896 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2897 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2898 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2899 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2900 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2901 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2902 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2903 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2904 } 2905 }; 2906 2907 void tcg_register_jit(const void *buf, size_t buf_size) 2908 { 2909 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2910 }