tcg-target.h (6008B)
1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.h 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #ifndef LOONGARCH_TCG_TARGET_H 30 #define LOONGARCH_TCG_TARGET_H 31 32 /* 33 * Loongson removed the (incomplete) 32-bit support from kernel and toolchain 34 * for the initial upstreaming of this architecture, so don't bother and just 35 * support the LP64* ABI for now. 36 */ 37 #if defined(__loongarch64) 38 # define TCG_TARGET_REG_BITS 64 39 #else 40 # error unsupported LoongArch register size 41 #endif 42 43 #define TCG_TARGET_INSN_UNIT_SIZE 4 44 #define TCG_TARGET_NB_REGS 32 45 /* 46 * PCADDU18I + JIRL sequence can give 20 + 16 + 2 = 38 bits 47 * signed offset, which is +/- 128 GiB. 48 */ 49 #define MAX_CODE_GEN_BUFFER_SIZE (128 * GiB) 50 51 typedef enum { 52 TCG_REG_ZERO, 53 TCG_REG_RA, 54 TCG_REG_TP, 55 TCG_REG_SP, 56 TCG_REG_A0, 57 TCG_REG_A1, 58 TCG_REG_A2, 59 TCG_REG_A3, 60 TCG_REG_A4, 61 TCG_REG_A5, 62 TCG_REG_A6, 63 TCG_REG_A7, 64 TCG_REG_T0, 65 TCG_REG_T1, 66 TCG_REG_T2, 67 TCG_REG_T3, 68 TCG_REG_T4, 69 TCG_REG_T5, 70 TCG_REG_T6, 71 TCG_REG_T7, 72 TCG_REG_T8, 73 TCG_REG_RESERVED, 74 TCG_REG_S9, 75 TCG_REG_S0, 76 TCG_REG_S1, 77 TCG_REG_S2, 78 TCG_REG_S3, 79 TCG_REG_S4, 80 TCG_REG_S5, 81 TCG_REG_S6, 82 TCG_REG_S7, 83 TCG_REG_S8, 84 85 /* aliases */ 86 TCG_AREG0 = TCG_REG_S0, 87 TCG_REG_TMP0 = TCG_REG_T8, 88 TCG_REG_TMP1 = TCG_REG_T7, 89 TCG_REG_TMP2 = TCG_REG_T6, 90 } TCGReg; 91 92 /* used for function call generation */ 93 #define TCG_REG_CALL_STACK TCG_REG_SP 94 #define TCG_TARGET_STACK_ALIGN 16 95 #define TCG_TARGET_CALL_ALIGN_ARGS 1 96 #define TCG_TARGET_CALL_STACK_OFFSET 0 97 98 /* optional instructions */ 99 #define TCG_TARGET_HAS_movcond_i32 0 100 #define TCG_TARGET_HAS_div_i32 1 101 #define TCG_TARGET_HAS_rem_i32 1 102 #define TCG_TARGET_HAS_div2_i32 0 103 #define TCG_TARGET_HAS_rot_i32 1 104 #define TCG_TARGET_HAS_deposit_i32 1 105 #define TCG_TARGET_HAS_extract_i32 1 106 #define TCG_TARGET_HAS_sextract_i32 0 107 #define TCG_TARGET_HAS_extract2_i32 0 108 #define TCG_TARGET_HAS_add2_i32 0 109 #define TCG_TARGET_HAS_sub2_i32 0 110 #define TCG_TARGET_HAS_mulu2_i32 0 111 #define TCG_TARGET_HAS_muls2_i32 0 112 #define TCG_TARGET_HAS_muluh_i32 1 113 #define TCG_TARGET_HAS_mulsh_i32 1 114 #define TCG_TARGET_HAS_ext8s_i32 1 115 #define TCG_TARGET_HAS_ext16s_i32 1 116 #define TCG_TARGET_HAS_ext8u_i32 1 117 #define TCG_TARGET_HAS_ext16u_i32 1 118 #define TCG_TARGET_HAS_bswap16_i32 1 119 #define TCG_TARGET_HAS_bswap32_i32 1 120 #define TCG_TARGET_HAS_not_i32 1 121 #define TCG_TARGET_HAS_neg_i32 0 122 #define TCG_TARGET_HAS_andc_i32 1 123 #define TCG_TARGET_HAS_orc_i32 1 124 #define TCG_TARGET_HAS_eqv_i32 0 125 #define TCG_TARGET_HAS_nand_i32 0 126 #define TCG_TARGET_HAS_nor_i32 1 127 #define TCG_TARGET_HAS_clz_i32 1 128 #define TCG_TARGET_HAS_ctz_i32 1 129 #define TCG_TARGET_HAS_ctpop_i32 0 130 #define TCG_TARGET_HAS_direct_jump 1 131 #define TCG_TARGET_HAS_brcond2 0 132 #define TCG_TARGET_HAS_setcond2 0 133 #define TCG_TARGET_HAS_qemu_st8_i32 0 134 135 /* 64-bit operations */ 136 #define TCG_TARGET_HAS_movcond_i64 0 137 #define TCG_TARGET_HAS_div_i64 1 138 #define TCG_TARGET_HAS_rem_i64 1 139 #define TCG_TARGET_HAS_div2_i64 0 140 #define TCG_TARGET_HAS_rot_i64 1 141 #define TCG_TARGET_HAS_deposit_i64 1 142 #define TCG_TARGET_HAS_extract_i64 1 143 #define TCG_TARGET_HAS_sextract_i64 0 144 #define TCG_TARGET_HAS_extract2_i64 0 145 #define TCG_TARGET_HAS_extrl_i64_i32 1 146 #define TCG_TARGET_HAS_extrh_i64_i32 1 147 #define TCG_TARGET_HAS_ext8s_i64 1 148 #define TCG_TARGET_HAS_ext16s_i64 1 149 #define TCG_TARGET_HAS_ext32s_i64 1 150 #define TCG_TARGET_HAS_ext8u_i64 1 151 #define TCG_TARGET_HAS_ext16u_i64 1 152 #define TCG_TARGET_HAS_ext32u_i64 1 153 #define TCG_TARGET_HAS_bswap16_i64 1 154 #define TCG_TARGET_HAS_bswap32_i64 1 155 #define TCG_TARGET_HAS_bswap64_i64 1 156 #define TCG_TARGET_HAS_not_i64 1 157 #define TCG_TARGET_HAS_neg_i64 0 158 #define TCG_TARGET_HAS_andc_i64 1 159 #define TCG_TARGET_HAS_orc_i64 1 160 #define TCG_TARGET_HAS_eqv_i64 0 161 #define TCG_TARGET_HAS_nand_i64 0 162 #define TCG_TARGET_HAS_nor_i64 1 163 #define TCG_TARGET_HAS_clz_i64 1 164 #define TCG_TARGET_HAS_ctz_i64 1 165 #define TCG_TARGET_HAS_ctpop_i64 0 166 #define TCG_TARGET_HAS_add2_i64 0 167 #define TCG_TARGET_HAS_sub2_i64 0 168 #define TCG_TARGET_HAS_mulu2_i64 0 169 #define TCG_TARGET_HAS_muls2_i64 0 170 #define TCG_TARGET_HAS_muluh_i64 1 171 #define TCG_TARGET_HAS_mulsh_i64 1 172 173 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t); 174 175 #define TCG_TARGET_DEFAULT_MO (0) 176 177 #define TCG_TARGET_NEED_LDST_LABELS 178 179 #define TCG_TARGET_HAS_MEMORY_BSWAP 0 180 181 #endif /* LOONGARCH_TCG_TARGET_H */