xtensa-modules.c.inc (1183764B)
1 /* Xtensa configuration-specific ISA information. 2 3 Copyright (c) 2003-2015 Tensilica Inc. 4 5 Permission is hereby granted, free of charge, to any person obtaining 6 a copy of this software and associated documentation files (the 7 "Software"), to deal in the Software without restriction, including 8 without limitation the rights to use, copy, modify, merge, publish, 9 distribute, sublicense, and/or sell copies of the Software, and to 10 permit persons to whom the Software is furnished to do so, subject to 11 the following conditions: 12 13 The above copyright notice and this permission notice shall be included 14 in all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24 #include "xtensa-isa.h" 25 #include "xtensa-isa-internal.h" 26 27 28 /* Sysregs. */ 29 30 static xtensa_sysreg_internal sysregs[] = { 31 { "LBEG", 0, 0 }, 32 { "LEND", 1, 0 }, 33 { "LCOUNT", 2, 0 }, 34 { "BR", 4, 0 }, 35 { "ACCLO", 16, 0 }, 36 { "ACCHI", 17, 0 }, 37 { "M0", 32, 0 }, 38 { "M1", 33, 0 }, 39 { "M2", 34, 0 }, 40 { "M3", 35, 0 }, 41 { "PTEVADDR", 83, 0 }, 42 { "MMID", 89, 0 }, 43 { "DDR", 104, 0 }, 44 { "CONFIGID0", 176, 0 }, 45 { "CONFIGID1", 208, 0 }, 46 { "INTERRUPT", 226, 0 }, 47 { "INTCLEAR", 227, 0 }, 48 { "CCOUNT", 234, 0 }, 49 { "PRID", 235, 0 }, 50 { "ICOUNT", 236, 0 }, 51 { "CCOMPARE0", 240, 0 }, 52 { "CCOMPARE1", 241, 0 }, 53 { "CCOMPARE2", 242, 0 }, 54 { "VECBASE", 231, 0 }, 55 { "EPC1", 177, 0 }, 56 { "EPC2", 178, 0 }, 57 { "EPC3", 179, 0 }, 58 { "EPC4", 180, 0 }, 59 { "EPC5", 181, 0 }, 60 { "EPC6", 182, 0 }, 61 { "EPC7", 183, 0 }, 62 { "EXCSAVE1", 209, 0 }, 63 { "EXCSAVE2", 210, 0 }, 64 { "EXCSAVE3", 211, 0 }, 65 { "EXCSAVE4", 212, 0 }, 66 { "EXCSAVE5", 213, 0 }, 67 { "EXCSAVE6", 214, 0 }, 68 { "EXCSAVE7", 215, 0 }, 69 { "EPS2", 194, 0 }, 70 { "EPS3", 195, 0 }, 71 { "EPS4", 196, 0 }, 72 { "EPS5", 197, 0 }, 73 { "EPS6", 198, 0 }, 74 { "EPS7", 199, 0 }, 75 { "EXCCAUSE", 232, 0 }, 76 { "DEPC", 192, 0 }, 77 { "EXCVADDR", 238, 0 }, 78 { "WINDOWBASE", 72, 0 }, 79 { "WINDOWSTART", 73, 0 }, 80 { "SAR", 3, 0 }, 81 { "PS", 230, 0 }, 82 { "MISC0", 244, 0 }, 83 { "MISC1", 245, 0 }, 84 { "INTENABLE", 228, 0 }, 85 { "DBREAKA0", 144, 0 }, 86 { "DBREAKC0", 160, 0 }, 87 { "DBREAKA1", 145, 0 }, 88 { "DBREAKC1", 161, 0 }, 89 { "IBREAKA0", 128, 0 }, 90 { "IBREAKA1", 129, 0 }, 91 { "IBREAKENABLE", 96, 0 }, 92 { "ICOUNTLEVEL", 237, 0 }, 93 { "DEBUGCAUSE", 233, 0 }, 94 { "PREFCTL", 40, 0 }, 95 { "RASID", 90, 0 }, 96 { "ITLBCFG", 91, 0 }, 97 { "DTLBCFG", 92, 0 }, 98 { "CPENABLE", 224, 0 }, 99 { "SCOMPARE1", 12, 0 }, 100 { "ATOMCTL", 99, 0 }, 101 { "THREADPTR", 231, 1 }, 102 { "AE_OVF_SAR", 240, 1 }, 103 { "AE_BITHEAD", 241, 1 }, 104 { "AE_TS_FTS_BU_BP", 242, 1 }, 105 { "AE_SD_NO", 243, 1 }, 106 { "AE_CBEGIN0", 246, 1 }, 107 { "AE_CEND0", 247, 1 }, 108 { "EXPSTATE", 230, 1 } 109 }; 110 111 #define NUM_SYSREGS 78 112 #define MAX_SPECIAL_REG 245 113 #define MAX_USER_REG 247 114 115 116 /* Processor states. */ 117 118 static xtensa_state_internal states[] = { 119 { "LCOUNT", 32, 0 }, 120 { "PC", 32, 0 }, 121 { "ICOUNT", 32, 0 }, 122 { "DDR", 32, 0 }, 123 { "INTERRUPT", 22, 0 }, 124 { "CCOUNT", 32, 0 }, 125 { "XTSYNC", 1, 0 }, 126 { "VECBASE", 22, 0 }, 127 { "EPC1", 32, 0 }, 128 { "EPC2", 32, 0 }, 129 { "EPC3", 32, 0 }, 130 { "EPC4", 32, 0 }, 131 { "EPC5", 32, 0 }, 132 { "EPC6", 32, 0 }, 133 { "EPC7", 32, 0 }, 134 { "EXCSAVE1", 32, 0 }, 135 { "EXCSAVE2", 32, 0 }, 136 { "EXCSAVE3", 32, 0 }, 137 { "EXCSAVE4", 32, 0 }, 138 { "EXCSAVE5", 32, 0 }, 139 { "EXCSAVE6", 32, 0 }, 140 { "EXCSAVE7", 32, 0 }, 141 { "EPS2", 15, 0 }, 142 { "EPS3", 15, 0 }, 143 { "EPS4", 15, 0 }, 144 { "EPS5", 15, 0 }, 145 { "EPS6", 15, 0 }, 146 { "EPS7", 15, 0 }, 147 { "EXCCAUSE", 6, 0 }, 148 { "PSINTLEVEL", 4, 0 }, 149 { "PSUM", 1, 0 }, 150 { "PSWOE", 1, 0 }, 151 { "PSRING", 2, 0 }, 152 { "PSEXCM", 1, 0 }, 153 { "DEPC", 32, 0 }, 154 { "EXCVADDR", 32, 0 }, 155 { "WindowBase", 3, 0 }, 156 { "WindowStart", 8, 0 }, 157 { "PSCALLINC", 2, 0 }, 158 { "PSOWB", 4, 0 }, 159 { "LBEG", 32, 0 }, 160 { "LEND", 32, 0 }, 161 { "SAR", 6, 0 }, 162 { "THREADPTR", 32, 0 }, 163 { "MISC0", 32, 0 }, 164 { "MISC1", 32, 0 }, 165 { "ACC", 40, 0 }, 166 { "InOCDMode", 1, 0 }, 167 { "INTENABLE", 22, 0 }, 168 { "DBREAKA0", 32, 0 }, 169 { "DBREAKC0", 8, 0 }, 170 { "DBREAKA1", 32, 0 }, 171 { "DBREAKC1", 8, 0 }, 172 { "IBREAKA0", 32, 0 }, 173 { "IBREAKA1", 32, 0 }, 174 { "IBREAKENABLE", 2, 0 }, 175 { "ICOUNTLEVEL", 4, 0 }, 176 { "DEBUGCAUSE", 6, 0 }, 177 { "DBNUM", 4, 0 }, 178 { "CCOMPARE0", 32, 0 }, 179 { "CCOMPARE1", 32, 0 }, 180 { "CCOMPARE2", 32, 0 }, 181 { "PREFCTL", 9, 0 }, 182 { "ASID3", 8, 0 }, 183 { "ASID2", 8, 0 }, 184 { "ASID1", 8, 0 }, 185 { "INSTPGSZID6", 1, 0 }, 186 { "INSTPGSZID5", 1, 0 }, 187 { "INSTPGSZID4", 2, 0 }, 188 { "DATAPGSZID6", 1, 0 }, 189 { "DATAPGSZID5", 1, 0 }, 190 { "DATAPGSZID4", 2, 0 }, 191 { "PTBASE", 10, 0 }, 192 { "CPENABLE", 8, 0 }, 193 { "SCOMPARE1", 32, 0 }, 194 { "ATOMCTL", 6, 0 }, 195 { "ERI_RAW_INTERLOCK", 1, 0 }, 196 { "AE_OVERFLOW", 1, XTENSA_STATE_IS_SHARED_OR }, 197 { "AE_SAR", 6, 0 }, 198 { "AE_BITHEAD", 32, 0 }, 199 { "AE_BITPTR", 4, 0 }, 200 { "AE_BITSUSED", 4, 0 }, 201 { "AE_TABLESIZE", 4, 0 }, 202 { "AE_FIRST_TS", 4, 0 }, 203 { "AE_NEXTOFFSET", 27, 0 }, 204 { "AE_SEARCHDONE", 1, 0 }, 205 { "AE_CBEGIN0", 32, 0 }, 206 { "AE_CEND0", 32, 0 }, 207 { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED } 208 }; 209 210 #define NUM_STATES 89 211 212 enum xtensa_state_id { 213 STATE_LCOUNT, 214 STATE_PC, 215 STATE_ICOUNT, 216 STATE_DDR, 217 STATE_INTERRUPT, 218 STATE_CCOUNT, 219 STATE_XTSYNC, 220 STATE_VECBASE, 221 STATE_EPC1, 222 STATE_EPC2, 223 STATE_EPC3, 224 STATE_EPC4, 225 STATE_EPC5, 226 STATE_EPC6, 227 STATE_EPC7, 228 STATE_EXCSAVE1, 229 STATE_EXCSAVE2, 230 STATE_EXCSAVE3, 231 STATE_EXCSAVE4, 232 STATE_EXCSAVE5, 233 STATE_EXCSAVE6, 234 STATE_EXCSAVE7, 235 STATE_EPS2, 236 STATE_EPS3, 237 STATE_EPS4, 238 STATE_EPS5, 239 STATE_EPS6, 240 STATE_EPS7, 241 STATE_EXCCAUSE, 242 STATE_PSINTLEVEL, 243 STATE_PSUM, 244 STATE_PSWOE, 245 STATE_PSRING, 246 STATE_PSEXCM, 247 STATE_DEPC, 248 STATE_EXCVADDR, 249 STATE_WindowBase, 250 STATE_WindowStart, 251 STATE_PSCALLINC, 252 STATE_PSOWB, 253 STATE_LBEG, 254 STATE_LEND, 255 STATE_SAR, 256 STATE_THREADPTR, 257 STATE_MISC0, 258 STATE_MISC1, 259 STATE_ACC, 260 STATE_InOCDMode, 261 STATE_INTENABLE, 262 STATE_DBREAKA0, 263 STATE_DBREAKC0, 264 STATE_DBREAKA1, 265 STATE_DBREAKC1, 266 STATE_IBREAKA0, 267 STATE_IBREAKA1, 268 STATE_IBREAKENABLE, 269 STATE_ICOUNTLEVEL, 270 STATE_DEBUGCAUSE, 271 STATE_DBNUM, 272 STATE_CCOMPARE0, 273 STATE_CCOMPARE1, 274 STATE_CCOMPARE2, 275 STATE_PREFCTL, 276 STATE_ASID3, 277 STATE_ASID2, 278 STATE_ASID1, 279 STATE_INSTPGSZID6, 280 STATE_INSTPGSZID5, 281 STATE_INSTPGSZID4, 282 STATE_DATAPGSZID6, 283 STATE_DATAPGSZID5, 284 STATE_DATAPGSZID4, 285 STATE_PTBASE, 286 STATE_CPENABLE, 287 STATE_SCOMPARE1, 288 STATE_ATOMCTL, 289 STATE_ERI_RAW_INTERLOCK, 290 STATE_AE_OVERFLOW, 291 STATE_AE_SAR, 292 STATE_AE_BITHEAD, 293 STATE_AE_BITPTR, 294 STATE_AE_BITSUSED, 295 STATE_AE_TABLESIZE, 296 STATE_AE_FIRST_TS, 297 STATE_AE_NEXTOFFSET, 298 STATE_AE_SEARCHDONE, 299 STATE_AE_CBEGIN0, 300 STATE_AE_CEND0, 301 STATE_EXPSTATE 302 }; 303 304 305 /* Field definitions. */ 306 307 static unsigned 308 Field_t_Slot_inst_get (const xtensa_insnbuf insn) 309 { 310 unsigned tie_t = 0; 311 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 312 return tie_t; 313 } 314 315 static void 316 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 317 { 318 uint32 tie_t; 319 tie_t = (val << 28) >> 28; 320 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 321 } 322 323 static unsigned 324 Field_s_Slot_inst_get (const xtensa_insnbuf insn) 325 { 326 unsigned tie_t = 0; 327 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 328 return tie_t; 329 } 330 331 static void 332 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 333 { 334 uint32 tie_t; 335 tie_t = (val << 28) >> 28; 336 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 337 } 338 339 static unsigned 340 Field_r_Slot_inst_get (const xtensa_insnbuf insn) 341 { 342 unsigned tie_t = 0; 343 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 344 return tie_t; 345 } 346 347 static void 348 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 349 { 350 uint32 tie_t; 351 tie_t = (val << 28) >> 28; 352 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 353 } 354 355 static unsigned 356 Field_op2_Slot_inst_get (const xtensa_insnbuf insn) 357 { 358 unsigned tie_t = 0; 359 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 360 return tie_t; 361 } 362 363 static void 364 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 365 { 366 uint32 tie_t; 367 tie_t = (val << 28) >> 28; 368 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 369 } 370 371 static unsigned 372 Field_op1_Slot_inst_get (const xtensa_insnbuf insn) 373 { 374 unsigned tie_t = 0; 375 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 376 return tie_t; 377 } 378 379 static void 380 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 381 { 382 uint32 tie_t; 383 tie_t = (val << 28) >> 28; 384 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 385 } 386 387 static unsigned 388 Field_op0_Slot_inst_get (const xtensa_insnbuf insn) 389 { 390 unsigned tie_t = 0; 391 tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28); 392 return tie_t; 393 } 394 395 static void 396 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 397 { 398 uint32 tie_t; 399 tie_t = (val << 28) >> 28; 400 insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20); 401 } 402 403 static unsigned 404 Field_n_Slot_inst_get (const xtensa_insnbuf insn) 405 { 406 unsigned tie_t = 0; 407 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 408 return tie_t; 409 } 410 411 static void 412 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 413 { 414 uint32 tie_t; 415 tie_t = (val << 30) >> 30; 416 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 417 } 418 419 static unsigned 420 Field_m_Slot_inst_get (const xtensa_insnbuf insn) 421 { 422 unsigned tie_t = 0; 423 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 424 return tie_t; 425 } 426 427 static void 428 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 429 { 430 uint32 tie_t; 431 tie_t = (val << 30) >> 30; 432 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 433 } 434 435 static unsigned 436 Field_sr_Slot_inst_get (const xtensa_insnbuf insn) 437 { 438 unsigned tie_t = 0; 439 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 440 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 441 return tie_t; 442 } 443 444 static void 445 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 446 { 447 uint32 tie_t; 448 tie_t = (val << 28) >> 28; 449 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 450 tie_t = (val << 24) >> 28; 451 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 452 } 453 454 static unsigned 455 Field_st_Slot_inst_get (const xtensa_insnbuf insn) 456 { 457 unsigned tie_t = 0; 458 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 459 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 460 return tie_t; 461 } 462 463 static void 464 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 465 { 466 uint32 tie_t; 467 tie_t = (val << 28) >> 28; 468 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 469 tie_t = (val << 24) >> 28; 470 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 471 } 472 473 static unsigned 474 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn) 475 { 476 unsigned tie_t = 0; 477 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 478 return tie_t; 479 } 480 481 static void 482 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 483 { 484 uint32 tie_t; 485 tie_t = (val << 29) >> 29; 486 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 487 } 488 489 static unsigned 490 Field_t3_Slot_inst_get (const xtensa_insnbuf insn) 491 { 492 unsigned tie_t = 0; 493 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 494 return tie_t; 495 } 496 497 static void 498 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 499 { 500 uint32 tie_t; 501 tie_t = (val << 31) >> 31; 502 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 503 } 504 505 static unsigned 506 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn) 507 { 508 unsigned tie_t = 0; 509 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 510 return tie_t; 511 } 512 513 static void 514 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 515 { 516 uint32 tie_t; 517 tie_t = (val << 30) >> 30; 518 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 519 } 520 521 static unsigned 522 Field_w_Slot_inst_get (const xtensa_insnbuf insn) 523 { 524 unsigned tie_t = 0; 525 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 526 return tie_t; 527 } 528 529 static void 530 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 531 { 532 uint32 tie_t; 533 tie_t = (val << 30) >> 30; 534 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 535 } 536 537 static unsigned 538 Field_r3_Slot_inst_get (const xtensa_insnbuf insn) 539 { 540 unsigned tie_t = 0; 541 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 542 return tie_t; 543 } 544 545 static void 546 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 547 { 548 uint32 tie_t; 549 tie_t = (val << 31) >> 31; 550 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 551 } 552 553 static unsigned 554 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn) 555 { 556 unsigned tie_t = 0; 557 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); 558 return tie_t; 559 } 560 561 static void 562 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 563 { 564 uint32 tie_t; 565 tie_t = (val << 30) >> 30; 566 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); 567 } 568 569 static unsigned 570 Field_ae_r3_Slot_inst_get (const xtensa_insnbuf insn) 571 { 572 unsigned tie_t = 0; 573 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 574 return tie_t; 575 } 576 577 static void 578 Field_ae_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 579 { 580 uint32 tie_t; 581 tie_t = (val << 31) >> 31; 582 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 583 } 584 585 static unsigned 586 Field_ae_r10_Slot_inst_get (const xtensa_insnbuf insn) 587 { 588 unsigned tie_t = 0; 589 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 590 return tie_t; 591 } 592 593 static void 594 Field_ae_r10_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 595 { 596 uint32 tie_t; 597 tie_t = (val << 30) >> 30; 598 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 599 } 600 601 static unsigned 602 Field_ae_r32_Slot_inst_get (const xtensa_insnbuf insn) 603 { 604 unsigned tie_t = 0; 605 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); 606 return tie_t; 607 } 608 609 static void 610 Field_ae_r32_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 611 { 612 uint32 tie_t; 613 tie_t = (val << 30) >> 30; 614 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); 615 } 616 617 static unsigned 618 Field_ae_s3_Slot_inst_get (const xtensa_insnbuf insn) 619 { 620 unsigned tie_t = 0; 621 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 622 return tie_t; 623 } 624 625 static void 626 Field_ae_s3_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 627 { 628 uint32 tie_t; 629 tie_t = (val << 31) >> 31; 630 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 631 } 632 633 static unsigned 634 Field_ae_s_non_samt_Slot_inst_get (const xtensa_insnbuf insn) 635 { 636 unsigned tie_t = 0; 637 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 638 return tie_t; 639 } 640 641 static void 642 Field_ae_s_non_samt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 643 { 644 uint32 tie_t; 645 tie_t = (val << 30) >> 30; 646 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 647 } 648 649 static unsigned 650 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn) 651 { 652 unsigned tie_t = 0; 653 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); 654 return tie_t; 655 } 656 657 static void 658 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 659 { 660 uint32 tie_t; 661 tie_t = (val << 29) >> 29; 662 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); 663 } 664 665 static unsigned 666 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn) 667 { 668 unsigned tie_t = 0; 669 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 670 return tie_t; 671 } 672 673 static void 674 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 675 { 676 uint32 tie_t; 677 tie_t = (val << 28) >> 28; 678 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 679 } 680 681 static unsigned 682 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) 683 { 684 unsigned tie_t = 0; 685 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 686 return tie_t; 687 } 688 689 static void 690 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 691 { 692 uint32 tie_t; 693 tie_t = (val << 28) >> 28; 694 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 695 } 696 697 static unsigned 698 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn) 699 { 700 unsigned tie_t = 0; 701 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 702 return tie_t; 703 } 704 705 static void 706 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 707 { 708 uint32 tie_t; 709 tie_t = (val << 28) >> 28; 710 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 711 } 712 713 static unsigned 714 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn) 715 { 716 unsigned tie_t = 0; 717 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 718 return tie_t; 719 } 720 721 static void 722 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 723 { 724 uint32 tie_t; 725 tie_t = (val << 28) >> 28; 726 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 727 } 728 729 static unsigned 730 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn) 731 { 732 unsigned tie_t = 0; 733 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 734 return tie_t; 735 } 736 737 static void 738 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 739 { 740 uint32 tie_t; 741 tie_t = (val << 31) >> 31; 742 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 743 } 744 745 static unsigned 746 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn) 747 { 748 unsigned tie_t = 0; 749 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 750 return tie_t; 751 } 752 753 static void 754 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 755 { 756 uint32 tie_t; 757 tie_t = (val << 31) >> 31; 758 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 759 } 760 761 static unsigned 762 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn) 763 { 764 unsigned tie_t = 0; 765 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 766 return tie_t; 767 } 768 769 static void 770 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 771 { 772 uint32 tie_t; 773 tie_t = (val << 28) >> 28; 774 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 775 } 776 777 static unsigned 778 Field_ftsf42ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 779 { 780 unsigned tie_t = 0; 781 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); 782 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 783 return tie_t; 784 } 785 786 static void 787 Field_ftsf42ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 788 { 789 uint32 tie_t; 790 tie_t = (val << 30) >> 30; 791 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 792 tie_t = (val << 22) >> 24; 793 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); 794 } 795 796 static unsigned 797 Field_op0_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) 798 { 799 unsigned tie_t = 0; 800 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); 801 return tie_t; 802 } 803 804 static void 805 Field_op0_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 806 { 807 uint32 tie_t; 808 tie_t = (val << 25) >> 25; 809 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); 810 } 811 812 static unsigned 813 Field_ftsf333ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 814 { 815 unsigned tie_t = 0; 816 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 817 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 818 return tie_t; 819 } 820 821 static void 822 Field_ftsf333ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 823 { 824 uint32 tie_t; 825 tie_t = (val << 29) >> 29; 826 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 827 tie_t = (val << 26) >> 29; 828 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 829 } 830 831 static unsigned 832 Field_ftsf43ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 833 { 834 unsigned tie_t = 0; 835 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 836 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 837 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 838 return tie_t; 839 } 840 841 static void 842 Field_ftsf43ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 843 { 844 uint32 tie_t; 845 tie_t = (val << 30) >> 30; 846 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 847 tie_t = (val << 26) >> 28; 848 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 849 tie_t = (val << 24) >> 30; 850 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 851 } 852 853 static unsigned 854 Field_ftsf359ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 855 { 856 unsigned tie_t = 0; 857 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 858 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 859 return tie_t; 860 } 861 862 static void 863 Field_ftsf359ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 864 { 865 uint32 tie_t; 866 tie_t = (val << 29) >> 29; 867 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 868 tie_t = (val << 27) >> 30; 869 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 870 } 871 872 static unsigned 873 Field_ftsf45ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 874 { 875 unsigned tie_t = 0; 876 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 877 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 878 return tie_t; 879 } 880 881 static void 882 Field_ftsf45ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 883 { 884 uint32 tie_t; 885 tie_t = (val << 23) >> 23; 886 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 887 tie_t = (val << 22) >> 31; 888 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 889 } 890 891 static unsigned 892 Field_ftsf32ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 893 { 894 unsigned tie_t = 0; 895 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 896 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 897 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 898 return tie_t; 899 } 900 901 static void 902 Field_ftsf32ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 903 { 904 uint32 tie_t; 905 tie_t = (val << 30) >> 30; 906 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 907 tie_t = (val << 26) >> 28; 908 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 909 tie_t = (val << 25) >> 31; 910 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 911 } 912 913 static unsigned 914 Field_ftsf33ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 915 { 916 unsigned tie_t = 0; 917 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 918 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 919 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 920 return tie_t; 921 } 922 923 static void 924 Field_ftsf33ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 925 { 926 uint32 tie_t; 927 tie_t = (val << 30) >> 30; 928 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 929 tie_t = (val << 26) >> 28; 930 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 931 tie_t = (val << 25) >> 31; 932 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 933 } 934 935 static unsigned 936 Field_ftsf31ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 937 { 938 unsigned tie_t = 0; 939 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 940 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 941 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 942 return tie_t; 943 } 944 945 static void 946 Field_ftsf31ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 947 { 948 uint32 tie_t; 949 tie_t = (val << 30) >> 30; 950 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 951 tie_t = (val << 26) >> 28; 952 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 953 tie_t = (val << 25) >> 31; 954 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 955 } 956 957 static unsigned 958 Field_ftsf30ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 959 { 960 unsigned tie_t = 0; 961 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 962 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 963 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 964 return tie_t; 965 } 966 967 static void 968 Field_ftsf30ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 969 { 970 uint32 tie_t; 971 tie_t = (val << 30) >> 30; 972 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 973 tie_t = (val << 26) >> 28; 974 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 975 tie_t = (val << 25) >> 31; 976 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 977 } 978 979 static unsigned 980 Field_ftsf60ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 981 { 982 unsigned tie_t = 0; 983 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 984 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 985 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 986 return tie_t; 987 } 988 989 static void 990 Field_ftsf60ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 991 { 992 uint32 tie_t; 993 tie_t = (val << 30) >> 30; 994 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 995 tie_t = (val << 28) >> 30; 996 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 997 tie_t = (val << 27) >> 31; 998 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 999 } 1000 1001 static unsigned 1002 Field_ftsf355ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1003 { 1004 unsigned tie_t = 0; 1005 tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); 1006 return tie_t; 1007 } 1008 1009 static void 1010 Field_ftsf355ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1011 { 1012 uint32 tie_t; 1013 tie_t = (val << 30) >> 30; 1014 insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); 1015 } 1016 1017 static unsigned 1018 Field_ftsf58ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1019 { 1020 unsigned tie_t = 0; 1021 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 1022 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1023 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1024 return tie_t; 1025 } 1026 1027 static void 1028 Field_ftsf58ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1029 { 1030 uint32 tie_t; 1031 tie_t = (val << 30) >> 30; 1032 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1033 tie_t = (val << 28) >> 30; 1034 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1035 tie_t = (val << 26) >> 30; 1036 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 1037 } 1038 1039 static unsigned 1040 Field_ftsf354ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1041 { 1042 unsigned tie_t = 0; 1043 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 1044 return tie_t; 1045 } 1046 1047 static void 1048 Field_ftsf354ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1049 { 1050 uint32 tie_t; 1051 tie_t = (val << 31) >> 31; 1052 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 1053 } 1054 1055 static unsigned 1056 Field_ftsf37ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1057 { 1058 unsigned tie_t = 0; 1059 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1060 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1061 return tie_t; 1062 } 1063 1064 static void 1065 Field_ftsf37ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1066 { 1067 uint32 tie_t; 1068 tie_t = (val << 30) >> 30; 1069 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1070 tie_t = (val << 26) >> 28; 1071 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1072 } 1073 1074 static unsigned 1075 Field_ftsf22ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1076 { 1077 unsigned tie_t = 0; 1078 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1079 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1080 return tie_t; 1081 } 1082 1083 static void 1084 Field_ftsf22ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1085 { 1086 uint32 tie_t; 1087 tie_t = (val << 30) >> 30; 1088 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1089 tie_t = (val << 26) >> 28; 1090 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1091 } 1092 1093 static unsigned 1094 Field_ftsf126ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1095 { 1096 unsigned tie_t = 0; 1097 tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); 1098 return tie_t; 1099 } 1100 1101 static void 1102 Field_ftsf126ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1103 { 1104 uint32 tie_t; 1105 tie_t = (val << 30) >> 30; 1106 insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); 1107 } 1108 1109 static unsigned 1110 Field_ftsf357ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1111 { 1112 unsigned tie_t = 0; 1113 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1114 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 1115 tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); 1116 return tie_t; 1117 } 1118 1119 static void 1120 Field_ftsf357ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1121 { 1122 uint32 tie_t; 1123 tie_t = (val << 27) >> 27; 1124 insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); 1125 tie_t = (val << 26) >> 31; 1126 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 1127 tie_t = (val << 25) >> 31; 1128 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1129 } 1130 1131 static unsigned 1132 Field_ftsf53ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1133 { 1134 unsigned tie_t = 0; 1135 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1136 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 1137 return tie_t; 1138 } 1139 1140 static void 1141 Field_ftsf53ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1142 { 1143 uint32 tie_t; 1144 tie_t = (val << 23) >> 23; 1145 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 1146 tie_t = (val << 22) >> 31; 1147 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1148 } 1149 1150 static unsigned 1151 Field_ftsf66ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1152 { 1153 unsigned tie_t = 0; 1154 tie_t = (tie_t << 3) | ((insn[0] << 18) >> 29); 1155 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1156 return tie_t; 1157 } 1158 1159 static void 1160 Field_ftsf66ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1161 { 1162 uint32 tie_t; 1163 tie_t = (val << 30) >> 30; 1164 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1165 tie_t = (val << 27) >> 29; 1166 insn[0] = (insn[0] & ~0x3800) | (tie_t << 11); 1167 } 1168 1169 static unsigned 1170 Field_ftsf347ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1171 { 1172 unsigned tie_t = 0; 1173 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 1174 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); 1175 return tie_t; 1176 } 1177 1178 static void 1179 Field_ftsf347ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1180 { 1181 uint32 tie_t; 1182 tie_t = (val << 30) >> 30; 1183 insn[0] = (insn[0] & ~0x600) | (tie_t << 9); 1184 tie_t = (val << 26) >> 28; 1185 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 1186 } 1187 1188 static unsigned 1189 Field_ftsf64ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1190 { 1191 unsigned tie_t = 0; 1192 tie_t = (tie_t << 4) | ((insn[0] << 18) >> 28); 1193 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1194 return tie_t; 1195 } 1196 1197 static void 1198 Field_ftsf64ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1199 { 1200 uint32 tie_t; 1201 tie_t = (val << 30) >> 30; 1202 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1203 tie_t = (val << 26) >> 28; 1204 insn[0] = (insn[0] & ~0x3c00) | (tie_t << 10); 1205 } 1206 1207 static unsigned 1208 Field_ftsf345ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1209 { 1210 unsigned tie_t = 0; 1211 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 1212 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); 1213 return tie_t; 1214 } 1215 1216 static void 1217 Field_ftsf345ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1218 { 1219 uint32 tie_t; 1220 tie_t = (val << 31) >> 31; 1221 insn[0] = (insn[0] & ~0x200) | (tie_t << 9); 1222 tie_t = (val << 27) >> 28; 1223 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 1224 } 1225 1226 static unsigned 1227 Field_ftsf63ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1228 { 1229 unsigned tie_t = 0; 1230 tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); 1231 return tie_t; 1232 } 1233 1234 static void 1235 Field_ftsf63ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1236 { 1237 uint32 tie_t; 1238 tie_t = (val << 25) >> 25; 1239 insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); 1240 } 1241 1242 static unsigned 1243 Field_ftsf344ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1244 { 1245 unsigned tie_t = 0; 1246 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 1247 return tie_t; 1248 } 1249 1250 static void 1251 Field_ftsf344ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1252 { 1253 uint32 tie_t; 1254 tie_t = (val << 28) >> 28; 1255 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 1256 } 1257 1258 static unsigned 1259 Field_ftsf48ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1260 { 1261 unsigned tie_t = 0; 1262 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1263 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 1264 return tie_t; 1265 } 1266 1267 static void 1268 Field_ftsf48ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1269 { 1270 uint32 tie_t; 1271 tie_t = (val << 23) >> 23; 1272 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 1273 tie_t = (val << 22) >> 31; 1274 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1275 } 1276 1277 static unsigned 1278 Field_ftsf47ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1279 { 1280 unsigned tie_t = 0; 1281 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1282 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 1283 return tie_t; 1284 } 1285 1286 static void 1287 Field_ftsf47ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1288 { 1289 uint32 tie_t; 1290 tie_t = (val << 23) >> 23; 1291 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 1292 tie_t = (val << 22) >> 31; 1293 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1294 } 1295 1296 static unsigned 1297 Field_ftsf92ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1298 { 1299 unsigned tie_t = 0; 1300 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 1301 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1302 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1303 return tie_t; 1304 } 1305 1306 static void 1307 Field_ftsf92ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1308 { 1309 uint32 tie_t; 1310 tie_t = (val << 27) >> 27; 1311 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1312 tie_t = (val << 26) >> 31; 1313 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1314 tie_t = (val << 22) >> 28; 1315 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 1316 } 1317 1318 static unsigned 1319 Field_ftsf358ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1320 { 1321 unsigned tie_t = 0; 1322 tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); 1323 return tie_t; 1324 } 1325 1326 static void 1327 Field_ftsf358ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1328 { 1329 uint32 tie_t; 1330 tie_t = (val << 28) >> 28; 1331 insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); 1332 } 1333 1334 static unsigned 1335 Field_ftsf94ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1336 { 1337 unsigned tie_t = 0; 1338 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 1339 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1340 return tie_t; 1341 } 1342 1343 static void 1344 Field_ftsf94ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1345 { 1346 uint32 tie_t; 1347 tie_t = (val << 27) >> 27; 1348 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1349 tie_t = (val << 20) >> 25; 1350 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 1351 } 1352 1353 static unsigned 1354 Field_ftsf93ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1355 { 1356 unsigned tie_t = 0; 1357 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 1358 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1359 return tie_t; 1360 } 1361 1362 static void 1363 Field_ftsf93ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1364 { 1365 uint32 tie_t; 1366 tie_t = (val << 27) >> 27; 1367 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1368 tie_t = (val << 23) >> 28; 1369 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 1370 } 1371 1372 static unsigned 1373 Field_ae_r10_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1374 { 1375 unsigned tie_t = 0; 1376 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 1377 return tie_t; 1378 } 1379 1380 static void 1381 Field_ae_r10_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1382 { 1383 uint32 tie_t; 1384 tie_t = (val << 30) >> 30; 1385 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 1386 } 1387 1388 static unsigned 1389 Field_ftsf90ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1390 { 1391 unsigned tie_t = 0; 1392 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 1393 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1394 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1395 return tie_t; 1396 } 1397 1398 static void 1399 Field_ftsf90ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1400 { 1401 uint32 tie_t; 1402 tie_t = (val << 27) >> 27; 1403 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1404 tie_t = (val << 26) >> 31; 1405 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1406 tie_t = (val << 22) >> 28; 1407 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 1408 } 1409 1410 static unsigned 1411 Field_ftsf55_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1412 { 1413 unsigned tie_t = 0; 1414 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 1415 return tie_t; 1416 } 1417 1418 static void 1419 Field_ftsf55_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1420 { 1421 uint32 tie_t; 1422 tie_t = (val << 31) >> 31; 1423 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 1424 } 1425 1426 static unsigned 1427 Field_ftsf121ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1428 { 1429 unsigned tie_t = 0; 1430 tie_t = (tie_t << 8) | ((insn[0] << 9) >> 24); 1431 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 1432 return tie_t; 1433 } 1434 1435 static void 1436 Field_ftsf121ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1437 { 1438 uint32 tie_t; 1439 tie_t = (val << 29) >> 29; 1440 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 1441 tie_t = (val << 21) >> 24; 1442 insn[0] = (insn[0] & ~0x7f8000) | (tie_t << 15); 1443 } 1444 1445 static unsigned 1446 Field_ftsf91_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1447 { 1448 unsigned tie_t = 0; 1449 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1450 return tie_t; 1451 } 1452 1453 static void 1454 Field_ftsf91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1455 { 1456 uint32 tie_t; 1457 tie_t = (val << 31) >> 31; 1458 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1459 } 1460 1461 static unsigned 1462 Field_ftsf99ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1463 { 1464 unsigned tie_t = 0; 1465 tie_t = (tie_t << 5) | ((insn[0] << 9) >> 27); 1466 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1467 return tie_t; 1468 } 1469 1470 static void 1471 Field_ftsf99ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1472 { 1473 uint32 tie_t; 1474 tie_t = (val << 27) >> 27; 1475 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1476 tie_t = (val << 22) >> 27; 1477 insn[0] = (insn[0] & ~0x7c0000) | (tie_t << 18); 1478 } 1479 1480 static unsigned 1481 Field_ftsf351_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1482 { 1483 unsigned tie_t = 0; 1484 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 1485 return tie_t; 1486 } 1487 1488 static void 1489 Field_ftsf351_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1490 { 1491 uint32 tie_t; 1492 tie_t = (val << 30) >> 30; 1493 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 1494 } 1495 1496 static unsigned 1497 Field_ftsf97ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1498 { 1499 unsigned tie_t = 0; 1500 tie_t = (tie_t << 6) | ((insn[0] << 9) >> 26); 1501 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1502 return tie_t; 1503 } 1504 1505 static void 1506 Field_ftsf97ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1507 { 1508 uint32 tie_t; 1509 tie_t = (val << 27) >> 27; 1510 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1511 tie_t = (val << 21) >> 26; 1512 insn[0] = (insn[0] & ~0x7e0000) | (tie_t << 17); 1513 } 1514 1515 static unsigned 1516 Field_ftsf348ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1517 { 1518 unsigned tie_t = 0; 1519 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 1520 return tie_t; 1521 } 1522 1523 static void 1524 Field_ftsf348ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1525 { 1526 uint32 tie_t; 1527 tie_t = (val << 31) >> 31; 1528 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 1529 } 1530 1531 static unsigned 1532 Field_ftsf96ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1533 { 1534 unsigned tie_t = 0; 1535 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 1536 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 1537 return tie_t; 1538 } 1539 1540 static void 1541 Field_ftsf96ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1542 { 1543 uint32 tie_t; 1544 tie_t = (val << 27) >> 27; 1545 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 1546 tie_t = (val << 20) >> 25; 1547 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 1548 } 1549 1550 static unsigned 1551 Field_ftsf23ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1552 { 1553 unsigned tie_t = 0; 1554 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1555 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1556 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1557 return tie_t; 1558 } 1559 1560 static void 1561 Field_ftsf23ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1562 { 1563 uint32 tie_t; 1564 tie_t = (val << 30) >> 30; 1565 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1566 tie_t = (val << 26) >> 28; 1567 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1568 tie_t = (val << 25) >> 31; 1569 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1570 } 1571 1572 static unsigned 1573 Field_ftsf34ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1574 { 1575 unsigned tie_t = 0; 1576 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1577 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1578 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1579 return tie_t; 1580 } 1581 1582 static void 1583 Field_ftsf34ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1584 { 1585 uint32 tie_t; 1586 tie_t = (val << 30) >> 30; 1587 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1588 tie_t = (val << 26) >> 28; 1589 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1590 tie_t = (val << 25) >> 31; 1591 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1592 } 1593 1594 static unsigned 1595 Field_ftsf40ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1596 { 1597 unsigned tie_t = 0; 1598 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); 1599 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1600 return tie_t; 1601 } 1602 1603 static void 1604 Field_ftsf40ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1605 { 1606 uint32 tie_t; 1607 tie_t = (val << 30) >> 30; 1608 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1609 tie_t = (val << 22) >> 24; 1610 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); 1611 } 1612 1613 static unsigned 1614 Field_ftsf38ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1615 { 1616 unsigned tie_t = 0; 1617 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); 1618 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1619 return tie_t; 1620 } 1621 1622 static void 1623 Field_ftsf38ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1624 { 1625 uint32 tie_t; 1626 tie_t = (val << 30) >> 30; 1627 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1628 tie_t = (val << 22) >> 24; 1629 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); 1630 } 1631 1632 static unsigned 1633 Field_ftsf24ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1634 { 1635 unsigned tie_t = 0; 1636 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1637 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1638 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1639 return tie_t; 1640 } 1641 1642 static void 1643 Field_ftsf24ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1644 { 1645 uint32 tie_t; 1646 tie_t = (val << 30) >> 30; 1647 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1648 tie_t = (val << 26) >> 28; 1649 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1650 tie_t = (val << 25) >> 31; 1651 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1652 } 1653 1654 static unsigned 1655 Field_ftsf26ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1656 { 1657 unsigned tie_t = 0; 1658 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1659 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1660 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1661 return tie_t; 1662 } 1663 1664 static void 1665 Field_ftsf26ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1666 { 1667 uint32 tie_t; 1668 tie_t = (val << 30) >> 30; 1669 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1670 tie_t = (val << 26) >> 28; 1671 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1672 tie_t = (val << 25) >> 31; 1673 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1674 } 1675 1676 static unsigned 1677 Field_ftsf20ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1678 { 1679 unsigned tie_t = 0; 1680 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1681 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1682 return tie_t; 1683 } 1684 1685 static void 1686 Field_ftsf20ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1687 { 1688 uint32 tie_t; 1689 tie_t = (val << 30) >> 30; 1690 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1691 tie_t = (val << 28) >> 30; 1692 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1693 } 1694 1695 static unsigned 1696 Field_ftsf21ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1697 { 1698 unsigned tie_t = 0; 1699 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1700 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1701 return tie_t; 1702 } 1703 1704 static void 1705 Field_ftsf21ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1706 { 1707 uint32 tie_t; 1708 tie_t = (val << 30) >> 30; 1709 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1710 tie_t = (val << 28) >> 30; 1711 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1712 } 1713 1714 static unsigned 1715 Field_ftsf25ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1716 { 1717 unsigned tie_t = 0; 1718 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1719 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1720 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1721 return tie_t; 1722 } 1723 1724 static void 1725 Field_ftsf25ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1726 { 1727 uint32 tie_t; 1728 tie_t = (val << 30) >> 30; 1729 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1730 tie_t = (val << 26) >> 28; 1731 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1732 tie_t = (val << 25) >> 31; 1733 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1734 } 1735 1736 static unsigned 1737 Field_ftsf35ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1738 { 1739 unsigned tie_t = 0; 1740 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1741 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1742 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1743 return tie_t; 1744 } 1745 1746 static void 1747 Field_ftsf35ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1748 { 1749 uint32 tie_t; 1750 tie_t = (val << 30) >> 30; 1751 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1752 tie_t = (val << 26) >> 28; 1753 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1754 tie_t = (val << 25) >> 31; 1755 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1756 } 1757 1758 static unsigned 1759 Field_ftsf41ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1760 { 1761 unsigned tie_t = 0; 1762 tie_t = (tie_t << 8) | ((insn[0] << 12) >> 24); 1763 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1764 return tie_t; 1765 } 1766 1767 static void 1768 Field_ftsf41ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1769 { 1770 uint32 tie_t; 1771 tie_t = (val << 30) >> 30; 1772 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1773 tie_t = (val << 22) >> 24; 1774 insn[0] = (insn[0] & ~0xff000) | (tie_t << 12); 1775 } 1776 1777 static unsigned 1778 Field_ftsf54ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1779 { 1780 unsigned tie_t = 0; 1781 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 1782 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1783 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1784 return tie_t; 1785 } 1786 1787 static void 1788 Field_ftsf54ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1789 { 1790 uint32 tie_t; 1791 tie_t = (val << 30) >> 30; 1792 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1793 tie_t = (val << 28) >> 30; 1794 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1795 tie_t = (val << 27) >> 31; 1796 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 1797 } 1798 1799 static unsigned 1800 Field_ftsf356ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1801 { 1802 unsigned tie_t = 0; 1803 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 1804 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 1805 return tie_t; 1806 } 1807 1808 static void 1809 Field_ftsf356ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1810 { 1811 uint32 tie_t; 1812 tie_t = (val << 31) >> 31; 1813 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 1814 tie_t = (val << 27) >> 28; 1815 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 1816 } 1817 1818 static unsigned 1819 Field_ftsf29ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1820 { 1821 unsigned tie_t = 0; 1822 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1823 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1824 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1825 return tie_t; 1826 } 1827 1828 static void 1829 Field_ftsf29ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1830 { 1831 uint32 tie_t; 1832 tie_t = (val << 30) >> 30; 1833 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1834 tie_t = (val << 26) >> 28; 1835 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1836 tie_t = (val << 25) >> 31; 1837 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1838 } 1839 1840 static unsigned 1841 Field_ftsf27ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1842 { 1843 unsigned tie_t = 0; 1844 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1845 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1846 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1847 return tie_t; 1848 } 1849 1850 static void 1851 Field_ftsf27ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1852 { 1853 uint32 tie_t; 1854 tie_t = (val << 30) >> 30; 1855 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1856 tie_t = (val << 26) >> 28; 1857 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1858 tie_t = (val << 25) >> 31; 1859 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1860 } 1861 1862 static unsigned 1863 Field_ftsf28ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1864 { 1865 unsigned tie_t = 0; 1866 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1867 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1868 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1869 return tie_t; 1870 } 1871 1872 static void 1873 Field_ftsf28ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1874 { 1875 uint32 tie_t; 1876 tie_t = (val << 30) >> 30; 1877 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1878 tie_t = (val << 26) >> 28; 1879 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1880 tie_t = (val << 25) >> 31; 1881 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1882 } 1883 1884 static unsigned 1885 Field_ftsf36ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1886 { 1887 unsigned tie_t = 0; 1888 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 1889 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 1890 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1891 return tie_t; 1892 } 1893 1894 static void 1895 Field_ftsf36ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1896 { 1897 uint32 tie_t; 1898 tie_t = (val << 30) >> 30; 1899 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1900 tie_t = (val << 26) >> 28; 1901 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 1902 tie_t = (val << 25) >> 31; 1903 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 1904 } 1905 1906 static unsigned 1907 Field_ftsf57ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1908 { 1909 unsigned tie_t = 0; 1910 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 1911 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1912 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1913 return tie_t; 1914 } 1915 1916 static void 1917 Field_ftsf57ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1918 { 1919 uint32 tie_t; 1920 tie_t = (val << 30) >> 30; 1921 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1922 tie_t = (val << 28) >> 30; 1923 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1924 tie_t = (val << 25) >> 29; 1925 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 1926 } 1927 1928 static unsigned 1929 Field_ftsf62ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1930 { 1931 unsigned tie_t = 0; 1932 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1933 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1934 return tie_t; 1935 } 1936 1937 static void 1938 Field_ftsf62ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1939 { 1940 uint32 tie_t; 1941 tie_t = (val << 30) >> 30; 1942 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1943 tie_t = (val << 28) >> 30; 1944 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1945 } 1946 1947 static unsigned 1948 Field_ae_s20_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1949 { 1950 unsigned tie_t = 0; 1951 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 1952 return tie_t; 1953 } 1954 1955 static void 1956 Field_ae_s20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1957 { 1958 uint32 tie_t; 1959 tie_t = (val << 29) >> 29; 1960 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 1961 } 1962 1963 static unsigned 1964 Field_ftsf56ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1965 { 1966 unsigned tie_t = 0; 1967 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 1968 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 1969 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 1970 return tie_t; 1971 } 1972 1973 static void 1974 Field_ftsf56ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1975 { 1976 uint32 tie_t; 1977 tie_t = (val << 30) >> 30; 1978 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 1979 tie_t = (val << 28) >> 30; 1980 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 1981 tie_t = (val << 25) >> 29; 1982 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 1983 } 1984 1985 static unsigned 1986 Field_ftsf127ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 1987 { 1988 unsigned tie_t = 0; 1989 tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); 1990 return tie_t; 1991 } 1992 1993 static void 1994 Field_ftsf127ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 1995 { 1996 uint32 tie_t; 1997 tie_t = (val << 31) >> 31; 1998 insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); 1999 } 2000 2001 static unsigned 2002 Field_ftsf350ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2003 { 2004 unsigned tie_t = 0; 2005 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2006 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 2007 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2008 return tie_t; 2009 } 2010 2011 static void 2012 Field_ftsf350ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2013 { 2014 uint32 tie_t; 2015 tie_t = (val << 29) >> 29; 2016 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2017 tie_t = (val << 27) >> 30; 2018 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 2019 tie_t = (val << 23) >> 28; 2020 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2021 } 2022 2023 static unsigned 2024 Field_ftsf114ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2025 { 2026 unsigned tie_t = 0; 2027 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2028 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2029 return tie_t; 2030 } 2031 2032 static void 2033 Field_ftsf114ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2034 { 2035 uint32 tie_t; 2036 tie_t = (val << 29) >> 29; 2037 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2038 tie_t = (val << 22) >> 25; 2039 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2040 } 2041 2042 static unsigned 2043 Field_ftsf124ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2044 { 2045 unsigned tie_t = 0; 2046 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 2047 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2048 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2049 return tie_t; 2050 } 2051 2052 static void 2053 Field_ftsf124ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2054 { 2055 uint32 tie_t; 2056 tie_t = (val << 29) >> 29; 2057 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2058 tie_t = (val << 26) >> 29; 2059 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2060 tie_t = (val << 24) >> 30; 2061 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 2062 } 2063 2064 static unsigned 2065 Field_ftsf352ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2066 { 2067 unsigned tie_t = 0; 2068 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 2069 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2070 return tie_t; 2071 } 2072 2073 static void 2074 Field_ftsf352ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2075 { 2076 uint32 tie_t; 2077 tie_t = (val << 30) >> 30; 2078 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2079 tie_t = (val << 28) >> 30; 2080 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 2081 } 2082 2083 static unsigned 2084 Field_ftsf118ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2085 { 2086 unsigned tie_t = 0; 2087 tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); 2088 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2089 return tie_t; 2090 } 2091 2092 static void 2093 Field_ftsf118ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2094 { 2095 uint32 tie_t; 2096 tie_t = (val << 29) >> 29; 2097 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2098 tie_t = (val << 20) >> 23; 2099 insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); 2100 } 2101 2102 static unsigned 2103 Field_ftsf111ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2104 { 2105 unsigned tie_t = 0; 2106 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2107 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2108 return tie_t; 2109 } 2110 2111 static void 2112 Field_ftsf111ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2113 { 2114 uint32 tie_t; 2115 tie_t = (val << 29) >> 29; 2116 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2117 tie_t = (val << 22) >> 25; 2118 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2119 } 2120 2121 static unsigned 2122 Field_ftsf113ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2123 { 2124 unsigned tie_t = 0; 2125 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2126 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2127 return tie_t; 2128 } 2129 2130 static void 2131 Field_ftsf113ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2132 { 2133 uint32 tie_t; 2134 tie_t = (val << 29) >> 29; 2135 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2136 tie_t = (val << 22) >> 25; 2137 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2138 } 2139 2140 static unsigned 2141 Field_ftsf106ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2142 { 2143 unsigned tie_t = 0; 2144 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2145 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2146 return tie_t; 2147 } 2148 2149 static void 2150 Field_ftsf106ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2151 { 2152 uint32 tie_t; 2153 tie_t = (val << 29) >> 29; 2154 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2155 tie_t = (val << 26) >> 29; 2156 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2157 } 2158 2159 static unsigned 2160 Field_ftsf107ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2161 { 2162 unsigned tie_t = 0; 2163 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2164 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2165 return tie_t; 2166 } 2167 2168 static void 2169 Field_ftsf107ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2170 { 2171 uint32 tie_t; 2172 tie_t = (val << 29) >> 29; 2173 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2174 tie_t = (val << 26) >> 29; 2175 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2176 } 2177 2178 static unsigned 2179 Field_ftsf109ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2180 { 2181 unsigned tie_t = 0; 2182 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2183 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2184 return tie_t; 2185 } 2186 2187 static void 2188 Field_ftsf109ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2189 { 2190 uint32 tie_t; 2191 tie_t = (val << 29) >> 29; 2192 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2193 tie_t = (val << 22) >> 25; 2194 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2195 } 2196 2197 static unsigned 2198 Field_ftsf115ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2199 { 2200 unsigned tie_t = 0; 2201 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2202 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2203 return tie_t; 2204 } 2205 2206 static void 2207 Field_ftsf115ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2208 { 2209 uint32 tie_t; 2210 tie_t = (val << 29) >> 29; 2211 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2212 tie_t = (val << 22) >> 25; 2213 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2214 } 2215 2216 static unsigned 2217 Field_ftsf120ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2218 { 2219 unsigned tie_t = 0; 2220 tie_t = (tie_t << 9) | ((insn[0] << 9) >> 23); 2221 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2222 return tie_t; 2223 } 2224 2225 static void 2226 Field_ftsf120ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2227 { 2228 uint32 tie_t; 2229 tie_t = (val << 29) >> 29; 2230 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2231 tie_t = (val << 20) >> 23; 2232 insn[0] = (insn[0] & ~0x7fc000) | (tie_t << 14); 2233 } 2234 2235 static unsigned 2236 Field_ftsf123ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2237 { 2238 unsigned tie_t = 0; 2239 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 2240 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2241 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2242 return tie_t; 2243 } 2244 2245 static void 2246 Field_ftsf123ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2247 { 2248 uint32 tie_t; 2249 tie_t = (val << 29) >> 29; 2250 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2251 tie_t = (val << 26) >> 29; 2252 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2253 tie_t = (val << 23) >> 29; 2254 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 2255 } 2256 2257 static unsigned 2258 Field_ftsf349ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2259 { 2260 unsigned tie_t = 0; 2261 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 2262 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2263 return tie_t; 2264 } 2265 2266 static void 2267 Field_ftsf349ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2268 { 2269 uint32 tie_t; 2270 tie_t = (val << 30) >> 30; 2271 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2272 tie_t = (val << 29) >> 31; 2273 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 2274 } 2275 2276 static unsigned 2277 Field_ftsf110ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2278 { 2279 unsigned tie_t = 0; 2280 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2281 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2282 return tie_t; 2283 } 2284 2285 static void 2286 Field_ftsf110ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2287 { 2288 uint32 tie_t; 2289 tie_t = (val << 29) >> 29; 2290 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2291 tie_t = (val << 22) >> 25; 2292 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2293 } 2294 2295 static unsigned 2296 Field_ftsf117ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2297 { 2298 unsigned tie_t = 0; 2299 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2300 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2301 return tie_t; 2302 } 2303 2304 static void 2305 Field_ftsf117ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2306 { 2307 uint32 tie_t; 2308 tie_t = (val << 29) >> 29; 2309 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2310 tie_t = (val << 22) >> 25; 2311 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2312 } 2313 2314 static unsigned 2315 Field_ftsf112ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2316 { 2317 unsigned tie_t = 0; 2318 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2319 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2320 return tie_t; 2321 } 2322 2323 static void 2324 Field_ftsf112ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2325 { 2326 uint32 tie_t; 2327 tie_t = (val << 29) >> 29; 2328 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2329 tie_t = (val << 22) >> 25; 2330 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2331 } 2332 2333 static unsigned 2334 Field_ftsf116ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2335 { 2336 unsigned tie_t = 0; 2337 tie_t = (tie_t << 7) | ((insn[0] << 9) >> 25); 2338 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2339 return tie_t; 2340 } 2341 2342 static void 2343 Field_ftsf116ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2344 { 2345 uint32 tie_t; 2346 tie_t = (val << 29) >> 29; 2347 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2348 tie_t = (val << 22) >> 25; 2349 insn[0] = (insn[0] & ~0x7f0000) | (tie_t << 16); 2350 } 2351 2352 static unsigned 2353 Field_ftsf68ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2354 { 2355 unsigned tie_t = 0; 2356 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 2357 return tie_t; 2358 } 2359 2360 static void 2361 Field_ftsf68ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2362 { 2363 uint32 tie_t; 2364 tie_t = (val << 27) >> 27; 2365 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 2366 } 2367 2368 static unsigned 2369 Field_ftsf50ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2370 { 2371 unsigned tie_t = 0; 2372 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 2373 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 2374 return tie_t; 2375 } 2376 2377 static void 2378 Field_ftsf50ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2379 { 2380 uint32 tie_t; 2381 tie_t = (val << 23) >> 23; 2382 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 2383 tie_t = (val << 22) >> 31; 2384 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 2385 } 2386 2387 static unsigned 2388 Field_ftsf52ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2389 { 2390 unsigned tie_t = 0; 2391 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 2392 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 2393 return tie_t; 2394 } 2395 2396 static void 2397 Field_ftsf52ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2398 { 2399 uint32 tie_t; 2400 tie_t = (val << 23) >> 23; 2401 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 2402 tie_t = (val << 22) >> 31; 2403 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 2404 } 2405 2406 static unsigned 2407 Field_ftsf51ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2408 { 2409 unsigned tie_t = 0; 2410 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 2411 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 2412 return tie_t; 2413 } 2414 2415 static void 2416 Field_ftsf51ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2417 { 2418 uint32 tie_t; 2419 tie_t = (val << 23) >> 23; 2420 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 2421 tie_t = (val << 22) >> 31; 2422 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 2423 } 2424 2425 static unsigned 2426 Field_ftsf49ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2427 { 2428 unsigned tie_t = 0; 2429 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 2430 tie_t = (tie_t << 9) | ((insn[0] << 16) >> 23); 2431 return tie_t; 2432 } 2433 2434 static void 2435 Field_ftsf49ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2436 { 2437 uint32 tie_t; 2438 tie_t = (val << 23) >> 23; 2439 insn[0] = (insn[0] & ~0xff80) | (tie_t << 7); 2440 tie_t = (val << 22) >> 31; 2441 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 2442 } 2443 2444 static unsigned 2445 Field_ae_r20_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2446 { 2447 unsigned tie_t = 0; 2448 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2449 return tie_t; 2450 } 2451 2452 static void 2453 Field_ae_r20_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2454 { 2455 uint32 tie_t; 2456 tie_t = (val << 29) >> 29; 2457 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2458 } 2459 2460 static unsigned 2461 Field_ftsf343ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2462 { 2463 unsigned tie_t = 0; 2464 tie_t = (tie_t << 5) | ((insn[0] << 18) >> 27); 2465 return tie_t; 2466 } 2467 2468 static void 2469 Field_ftsf343ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2470 { 2471 uint32 tie_t; 2472 tie_t = (val << 27) >> 27; 2473 insn[0] = (insn[0] & ~0x3e00) | (tie_t << 9); 2474 } 2475 2476 static unsigned 2477 Field_ftsf125ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2478 { 2479 unsigned tie_t = 0; 2480 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2481 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 2482 return tie_t; 2483 } 2484 2485 static void 2486 Field_ftsf125ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2487 { 2488 uint32 tie_t; 2489 tie_t = (val << 31) >> 31; 2490 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 2491 tie_t = (val << 28) >> 29; 2492 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2493 } 2494 2495 static unsigned 2496 Field_ftsf342ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2497 { 2498 unsigned tie_t = 0; 2499 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 2500 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); 2501 return tie_t; 2502 } 2503 2504 static void 2505 Field_ftsf342ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2506 { 2507 uint32 tie_t; 2508 tie_t = (val << 30) >> 30; 2509 insn[0] = (insn[0] & ~0x600) | (tie_t << 9); 2510 tie_t = (val << 28) >> 30; 2511 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 2512 } 2513 2514 static unsigned 2515 Field_ftsf108ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2516 { 2517 unsigned tie_t = 0; 2518 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 2519 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 2520 return tie_t; 2521 } 2522 2523 static void 2524 Field_ftsf108ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2525 { 2526 uint32 tie_t; 2527 tie_t = (val << 29) >> 29; 2528 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 2529 tie_t = (val << 26) >> 29; 2530 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 2531 } 2532 2533 static unsigned 2534 Field_ae_r32_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2535 { 2536 unsigned tie_t = 0; 2537 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 2538 return tie_t; 2539 } 2540 2541 static void 2542 Field_ae_r32_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2543 { 2544 uint32 tie_t; 2545 tie_t = (val << 30) >> 30; 2546 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 2547 } 2548 2549 static unsigned 2550 Field_ae_mul32x24fld_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2551 { 2552 unsigned tie_t = 0; 2553 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2554 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 2555 return tie_t; 2556 } 2557 2558 static void 2559 Field_ae_mul32x24fld_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2560 { 2561 uint32 tie_t; 2562 tie_t = (val << 27) >> 27; 2563 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 2564 tie_t = (val << 23) >> 28; 2565 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2566 } 2567 2568 static unsigned 2569 Field_ftsf161ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2570 { 2571 unsigned tie_t = 0; 2572 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2573 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2574 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2575 return tie_t; 2576 } 2577 2578 static void 2579 Field_ftsf161ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2580 { 2581 uint32 tie_t; 2582 tie_t = (val << 30) >> 30; 2583 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2584 tie_t = (val << 28) >> 30; 2585 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2586 tie_t = (val << 24) >> 28; 2587 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2588 } 2589 2590 static unsigned 2591 Field_ftsf155ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2592 { 2593 unsigned tie_t = 0; 2594 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2595 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2596 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2597 return tie_t; 2598 } 2599 2600 static void 2601 Field_ftsf155ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2602 { 2603 uint32 tie_t; 2604 tie_t = (val << 30) >> 30; 2605 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2606 tie_t = (val << 28) >> 30; 2607 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2608 tie_t = (val << 24) >> 28; 2609 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2610 } 2611 2612 static unsigned 2613 Field_ftsf176ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2614 { 2615 unsigned tie_t = 0; 2616 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2617 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2618 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2619 return tie_t; 2620 } 2621 2622 static void 2623 Field_ftsf176ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2624 { 2625 uint32 tie_t; 2626 tie_t = (val << 30) >> 30; 2627 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2628 tie_t = (val << 28) >> 30; 2629 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2630 tie_t = (val << 24) >> 28; 2631 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2632 } 2633 2634 static unsigned 2635 Field_ftsf159ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2636 { 2637 unsigned tie_t = 0; 2638 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2639 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2640 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2641 return tie_t; 2642 } 2643 2644 static void 2645 Field_ftsf159ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2646 { 2647 uint32 tie_t; 2648 tie_t = (val << 30) >> 30; 2649 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2650 tie_t = (val << 28) >> 30; 2651 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2652 tie_t = (val << 24) >> 28; 2653 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2654 } 2655 2656 static unsigned 2657 Field_ftsf156ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2658 { 2659 unsigned tie_t = 0; 2660 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2661 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2662 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2663 return tie_t; 2664 } 2665 2666 static void 2667 Field_ftsf156ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2668 { 2669 uint32 tie_t; 2670 tie_t = (val << 30) >> 30; 2671 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2672 tie_t = (val << 28) >> 30; 2673 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2674 tie_t = (val << 24) >> 28; 2675 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2676 } 2677 2678 static unsigned 2679 Field_ftsf168ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2680 { 2681 unsigned tie_t = 0; 2682 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2683 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2684 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2685 return tie_t; 2686 } 2687 2688 static void 2689 Field_ftsf168ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2690 { 2691 uint32 tie_t; 2692 tie_t = (val << 30) >> 30; 2693 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2694 tie_t = (val << 28) >> 30; 2695 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2696 tie_t = (val << 24) >> 28; 2697 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2698 } 2699 2700 static unsigned 2701 Field_ftsf158ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2702 { 2703 unsigned tie_t = 0; 2704 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2705 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2706 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2707 return tie_t; 2708 } 2709 2710 static void 2711 Field_ftsf158ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2712 { 2713 uint32 tie_t; 2714 tie_t = (val << 30) >> 30; 2715 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2716 tie_t = (val << 28) >> 30; 2717 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2718 tie_t = (val << 24) >> 28; 2719 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2720 } 2721 2722 static unsigned 2723 Field_ftsf154ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2724 { 2725 unsigned tie_t = 0; 2726 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2727 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2728 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2729 return tie_t; 2730 } 2731 2732 static void 2733 Field_ftsf154ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2734 { 2735 uint32 tie_t; 2736 tie_t = (val << 30) >> 30; 2737 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2738 tie_t = (val << 28) >> 30; 2739 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2740 tie_t = (val << 24) >> 28; 2741 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2742 } 2743 2744 static unsigned 2745 Field_ftsf164ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2746 { 2747 unsigned tie_t = 0; 2748 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2749 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2750 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2751 return tie_t; 2752 } 2753 2754 static void 2755 Field_ftsf164ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2756 { 2757 uint32 tie_t; 2758 tie_t = (val << 30) >> 30; 2759 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2760 tie_t = (val << 28) >> 30; 2761 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2762 tie_t = (val << 24) >> 28; 2763 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2764 } 2765 2766 static unsigned 2767 Field_ftsf157ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2768 { 2769 unsigned tie_t = 0; 2770 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2771 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2772 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2773 return tie_t; 2774 } 2775 2776 static void 2777 Field_ftsf157ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2778 { 2779 uint32 tie_t; 2780 tie_t = (val << 30) >> 30; 2781 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2782 tie_t = (val << 28) >> 30; 2783 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2784 tie_t = (val << 24) >> 28; 2785 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2786 } 2787 2788 static unsigned 2789 Field_ftsf153ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2790 { 2791 unsigned tie_t = 0; 2792 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2793 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2794 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2795 return tie_t; 2796 } 2797 2798 static void 2799 Field_ftsf153ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2800 { 2801 uint32 tie_t; 2802 tie_t = (val << 30) >> 30; 2803 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2804 tie_t = (val << 28) >> 30; 2805 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2806 tie_t = (val << 24) >> 28; 2807 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2808 } 2809 2810 static unsigned 2811 Field_ftsf162ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2812 { 2813 unsigned tie_t = 0; 2814 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2815 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2816 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2817 return tie_t; 2818 } 2819 2820 static void 2821 Field_ftsf162ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2822 { 2823 uint32 tie_t; 2824 tie_t = (val << 30) >> 30; 2825 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2826 tie_t = (val << 28) >> 30; 2827 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2828 tie_t = (val << 24) >> 28; 2829 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2830 } 2831 2832 static unsigned 2833 Field_ftsf134ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2834 { 2835 unsigned tie_t = 0; 2836 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2837 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2838 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2839 return tie_t; 2840 } 2841 2842 static void 2843 Field_ftsf134ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2844 { 2845 uint32 tie_t; 2846 tie_t = (val << 30) >> 30; 2847 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2848 tie_t = (val << 28) >> 30; 2849 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2850 tie_t = (val << 24) >> 28; 2851 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2852 } 2853 2854 static unsigned 2855 Field_ftsf192ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2856 { 2857 unsigned tie_t = 0; 2858 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2859 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2860 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2861 return tie_t; 2862 } 2863 2864 static void 2865 Field_ftsf192ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2866 { 2867 uint32 tie_t; 2868 tie_t = (val << 30) >> 30; 2869 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2870 tie_t = (val << 28) >> 30; 2871 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2872 tie_t = (val << 24) >> 28; 2873 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2874 } 2875 2876 static unsigned 2877 Field_ftsf143ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2878 { 2879 unsigned tie_t = 0; 2880 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2881 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2882 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2883 return tie_t; 2884 } 2885 2886 static void 2887 Field_ftsf143ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2888 { 2889 uint32 tie_t; 2890 tie_t = (val << 30) >> 30; 2891 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2892 tie_t = (val << 28) >> 30; 2893 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2894 tie_t = (val << 24) >> 28; 2895 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2896 } 2897 2898 static unsigned 2899 Field_ftsf133ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2900 { 2901 unsigned tie_t = 0; 2902 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2903 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2904 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2905 return tie_t; 2906 } 2907 2908 static void 2909 Field_ftsf133ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2910 { 2911 uint32 tie_t; 2912 tie_t = (val << 30) >> 30; 2913 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2914 tie_t = (val << 28) >> 30; 2915 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2916 tie_t = (val << 24) >> 28; 2917 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2918 } 2919 2920 static unsigned 2921 Field_ftsf160ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2922 { 2923 unsigned tie_t = 0; 2924 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2925 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2926 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2927 return tie_t; 2928 } 2929 2930 static void 2931 Field_ftsf160ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2932 { 2933 uint32 tie_t; 2934 tie_t = (val << 30) >> 30; 2935 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2936 tie_t = (val << 28) >> 30; 2937 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2938 tie_t = (val << 24) >> 28; 2939 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2940 } 2941 2942 static unsigned 2943 Field_ftsf142ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2944 { 2945 unsigned tie_t = 0; 2946 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2947 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2948 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2949 return tie_t; 2950 } 2951 2952 static void 2953 Field_ftsf142ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2954 { 2955 uint32 tie_t; 2956 tie_t = (val << 30) >> 30; 2957 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2958 tie_t = (val << 28) >> 30; 2959 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2960 tie_t = (val << 24) >> 28; 2961 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2962 } 2963 2964 static unsigned 2965 Field_ftsf131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2966 { 2967 unsigned tie_t = 0; 2968 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2969 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2970 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2971 return tie_t; 2972 } 2973 2974 static void 2975 Field_ftsf131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2976 { 2977 uint32 tie_t; 2978 tie_t = (val << 30) >> 30; 2979 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 2980 tie_t = (val << 28) >> 30; 2981 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 2982 tie_t = (val << 24) >> 28; 2983 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 2984 } 2985 2986 static unsigned 2987 Field_ftsf144ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 2988 { 2989 unsigned tie_t = 0; 2990 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 2991 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 2992 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 2993 return tie_t; 2994 } 2995 2996 static void 2997 Field_ftsf144ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 2998 { 2999 uint32 tie_t; 3000 tie_t = (val << 30) >> 30; 3001 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3002 tie_t = (val << 28) >> 30; 3003 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3004 tie_t = (val << 24) >> 28; 3005 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3006 } 3007 3008 static unsigned 3009 Field_ftsf141ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3010 { 3011 unsigned tie_t = 0; 3012 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3013 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3014 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3015 return tie_t; 3016 } 3017 3018 static void 3019 Field_ftsf141ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3020 { 3021 uint32 tie_t; 3022 tie_t = (val << 30) >> 30; 3023 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3024 tie_t = (val << 28) >> 30; 3025 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3026 tie_t = (val << 24) >> 28; 3027 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3028 } 3029 3030 static unsigned 3031 Field_ftsf61_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3032 { 3033 unsigned tie_t = 0; 3034 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 3035 return tie_t; 3036 } 3037 3038 static void 3039 Field_ftsf61_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3040 { 3041 uint32 tie_t; 3042 tie_t = (val << 31) >> 31; 3043 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 3044 } 3045 3046 static unsigned 3047 Field_ftsf334ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3048 { 3049 unsigned tie_t = 0; 3050 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 3051 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3052 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3053 return tie_t; 3054 } 3055 3056 static void 3057 Field_ftsf334ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3058 { 3059 uint32 tie_t; 3060 tie_t = (val << 30) >> 30; 3061 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3062 tie_t = (val << 28) >> 30; 3063 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3064 tie_t = (val << 25) >> 29; 3065 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 3066 } 3067 3068 static unsigned 3069 Field_ftsf136ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3070 { 3071 unsigned tie_t = 0; 3072 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3073 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3074 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3075 return tie_t; 3076 } 3077 3078 static void 3079 Field_ftsf136ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3080 { 3081 uint32 tie_t; 3082 tie_t = (val << 30) >> 30; 3083 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3084 tie_t = (val << 28) >> 30; 3085 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3086 tie_t = (val << 24) >> 28; 3087 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3088 } 3089 3090 static unsigned 3091 Field_ftsf139ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3092 { 3093 unsigned tie_t = 0; 3094 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3095 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3096 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3097 return tie_t; 3098 } 3099 3100 static void 3101 Field_ftsf139ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3102 { 3103 uint32 tie_t; 3104 tie_t = (val << 30) >> 30; 3105 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3106 tie_t = (val << 28) >> 30; 3107 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3108 tie_t = (val << 24) >> 28; 3109 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3110 } 3111 3112 static unsigned 3113 Field_ftsf177ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3114 { 3115 unsigned tie_t = 0; 3116 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3117 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3118 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3119 return tie_t; 3120 } 3121 3122 static void 3123 Field_ftsf177ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3124 { 3125 uint32 tie_t; 3126 tie_t = (val << 30) >> 30; 3127 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3128 tie_t = (val << 28) >> 30; 3129 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3130 tie_t = (val << 24) >> 28; 3131 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3132 } 3133 3134 static unsigned 3135 Field_ftsf171ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3136 { 3137 unsigned tie_t = 0; 3138 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3139 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3140 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3141 return tie_t; 3142 } 3143 3144 static void 3145 Field_ftsf171ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3146 { 3147 uint32 tie_t; 3148 tie_t = (val << 30) >> 30; 3149 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3150 tie_t = (val << 28) >> 30; 3151 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3152 tie_t = (val << 24) >> 28; 3153 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3154 } 3155 3156 static unsigned 3157 Field_ftsf185ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3158 { 3159 unsigned tie_t = 0; 3160 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3161 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3162 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3163 return tie_t; 3164 } 3165 3166 static void 3167 Field_ftsf185ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3168 { 3169 uint32 tie_t; 3170 tie_t = (val << 30) >> 30; 3171 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3172 tie_t = (val << 28) >> 30; 3173 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3174 tie_t = (val << 24) >> 28; 3175 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3176 } 3177 3178 static unsigned 3179 Field_ftsf175ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3180 { 3181 unsigned tie_t = 0; 3182 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3183 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3184 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3185 return tie_t; 3186 } 3187 3188 static void 3189 Field_ftsf175ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3190 { 3191 uint32 tie_t; 3192 tie_t = (val << 30) >> 30; 3193 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3194 tie_t = (val << 28) >> 30; 3195 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3196 tie_t = (val << 24) >> 28; 3197 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3198 } 3199 3200 static unsigned 3201 Field_ftsf172ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3202 { 3203 unsigned tie_t = 0; 3204 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3205 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3206 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3207 return tie_t; 3208 } 3209 3210 static void 3211 Field_ftsf172ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3212 { 3213 uint32 tie_t; 3214 tie_t = (val << 30) >> 30; 3215 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3216 tie_t = (val << 28) >> 30; 3217 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3218 tie_t = (val << 24) >> 28; 3219 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3220 } 3221 3222 static unsigned 3223 Field_ftsf183ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3224 { 3225 unsigned tie_t = 0; 3226 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3227 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3228 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3229 return tie_t; 3230 } 3231 3232 static void 3233 Field_ftsf183ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3234 { 3235 uint32 tie_t; 3236 tie_t = (val << 30) >> 30; 3237 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3238 tie_t = (val << 28) >> 30; 3239 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3240 tie_t = (val << 24) >> 28; 3241 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3242 } 3243 3244 static unsigned 3245 Field_ftsf174ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3246 { 3247 unsigned tie_t = 0; 3248 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3249 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3250 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3251 return tie_t; 3252 } 3253 3254 static void 3255 Field_ftsf174ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3256 { 3257 uint32 tie_t; 3258 tie_t = (val << 30) >> 30; 3259 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3260 tie_t = (val << 28) >> 30; 3261 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3262 tie_t = (val << 24) >> 28; 3263 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3264 } 3265 3266 static unsigned 3267 Field_ftsf170ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3268 { 3269 unsigned tie_t = 0; 3270 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3271 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3272 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3273 return tie_t; 3274 } 3275 3276 static void 3277 Field_ftsf170ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3278 { 3279 uint32 tie_t; 3280 tie_t = (val << 30) >> 30; 3281 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3282 tie_t = (val << 28) >> 30; 3283 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3284 tie_t = (val << 24) >> 28; 3285 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3286 } 3287 3288 static unsigned 3289 Field_ftsf182ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3290 { 3291 unsigned tie_t = 0; 3292 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3293 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3294 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3295 return tie_t; 3296 } 3297 3298 static void 3299 Field_ftsf182ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3300 { 3301 uint32 tie_t; 3302 tie_t = (val << 30) >> 30; 3303 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3304 tie_t = (val << 28) >> 30; 3305 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3306 tie_t = (val << 24) >> 28; 3307 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3308 } 3309 3310 static unsigned 3311 Field_ftsf173ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3312 { 3313 unsigned tie_t = 0; 3314 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3315 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3316 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3317 return tie_t; 3318 } 3319 3320 static void 3321 Field_ftsf173ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3322 { 3323 uint32 tie_t; 3324 tie_t = (val << 30) >> 30; 3325 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3326 tie_t = (val << 28) >> 30; 3327 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3328 tie_t = (val << 24) >> 28; 3329 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3330 } 3331 3332 static unsigned 3333 Field_ftsf169ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3334 { 3335 unsigned tie_t = 0; 3336 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3337 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3338 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3339 return tie_t; 3340 } 3341 3342 static void 3343 Field_ftsf169ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3344 { 3345 uint32 tie_t; 3346 tie_t = (val << 30) >> 30; 3347 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3348 tie_t = (val << 28) >> 30; 3349 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3350 tie_t = (val << 24) >> 28; 3351 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3352 } 3353 3354 static unsigned 3355 Field_ftsf181ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3356 { 3357 unsigned tie_t = 0; 3358 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3359 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3360 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3361 return tie_t; 3362 } 3363 3364 static void 3365 Field_ftsf181ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3366 { 3367 uint32 tie_t; 3368 tie_t = (val << 30) >> 30; 3369 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3370 tie_t = (val << 28) >> 30; 3371 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3372 tie_t = (val << 24) >> 28; 3373 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3374 } 3375 3376 static unsigned 3377 Field_ftsf140ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3378 { 3379 unsigned tie_t = 0; 3380 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3381 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3382 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3383 return tie_t; 3384 } 3385 3386 static void 3387 Field_ftsf140ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3388 { 3389 uint32 tie_t; 3390 tie_t = (val << 30) >> 30; 3391 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3392 tie_t = (val << 28) >> 30; 3393 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3394 tie_t = (val << 24) >> 28; 3395 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3396 } 3397 3398 static unsigned 3399 Field_ftsf152ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3400 { 3401 unsigned tie_t = 0; 3402 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3403 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3404 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3405 return tie_t; 3406 } 3407 3408 static void 3409 Field_ftsf152ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3410 { 3411 uint32 tie_t; 3412 tie_t = (val << 30) >> 30; 3413 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3414 tie_t = (val << 28) >> 30; 3415 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3416 tie_t = (val << 24) >> 28; 3417 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3418 } 3419 3420 static unsigned 3421 Field_ftsf138ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3422 { 3423 unsigned tie_t = 0; 3424 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3425 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3426 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3427 return tie_t; 3428 } 3429 3430 static void 3431 Field_ftsf138ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3432 { 3433 uint32 tie_t; 3434 tie_t = (val << 30) >> 30; 3435 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3436 tie_t = (val << 28) >> 30; 3437 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3438 tie_t = (val << 24) >> 28; 3439 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3440 } 3441 3442 static unsigned 3443 Field_ftsf148ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3444 { 3445 unsigned tie_t = 0; 3446 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3447 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3448 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3449 return tie_t; 3450 } 3451 3452 static void 3453 Field_ftsf148ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3454 { 3455 uint32 tie_t; 3456 tie_t = (val << 30) >> 30; 3457 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3458 tie_t = (val << 28) >> 30; 3459 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3460 tie_t = (val << 24) >> 28; 3461 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3462 } 3463 3464 static unsigned 3465 Field_ftsf137ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3466 { 3467 unsigned tie_t = 0; 3468 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3469 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3470 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3471 return tie_t; 3472 } 3473 3474 static void 3475 Field_ftsf137ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3476 { 3477 uint32 tie_t; 3478 tie_t = (val << 30) >> 30; 3479 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3480 tie_t = (val << 28) >> 30; 3481 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3482 tie_t = (val << 24) >> 28; 3483 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3484 } 3485 3486 static unsigned 3487 Field_ftsf146ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3488 { 3489 unsigned tie_t = 0; 3490 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3491 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3492 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3493 return tie_t; 3494 } 3495 3496 static void 3497 Field_ftsf146ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3498 { 3499 uint32 tie_t; 3500 tie_t = (val << 30) >> 30; 3501 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3502 tie_t = (val << 28) >> 30; 3503 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3504 tie_t = (val << 24) >> 28; 3505 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3506 } 3507 3508 static unsigned 3509 Field_ftsf135ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3510 { 3511 unsigned tie_t = 0; 3512 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3513 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3514 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3515 return tie_t; 3516 } 3517 3518 static void 3519 Field_ftsf135ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3520 { 3521 uint32 tie_t; 3522 tie_t = (val << 30) >> 30; 3523 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3524 tie_t = (val << 28) >> 30; 3525 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3526 tie_t = (val << 24) >> 28; 3527 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3528 } 3529 3530 static unsigned 3531 Field_ftsf145ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3532 { 3533 unsigned tie_t = 0; 3534 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3535 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3536 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3537 return tie_t; 3538 } 3539 3540 static void 3541 Field_ftsf145ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3542 { 3543 uint32 tie_t; 3544 tie_t = (val << 30) >> 30; 3545 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3546 tie_t = (val << 28) >> 30; 3547 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3548 tie_t = (val << 24) >> 28; 3549 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3550 } 3551 3552 static unsigned 3553 Field_ftsf179ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3554 { 3555 unsigned tie_t = 0; 3556 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3557 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3558 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3559 return tie_t; 3560 } 3561 3562 static void 3563 Field_ftsf179ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3564 { 3565 uint32 tie_t; 3566 tie_t = (val << 30) >> 30; 3567 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3568 tie_t = (val << 28) >> 30; 3569 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3570 tie_t = (val << 24) >> 28; 3571 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3572 } 3573 3574 static unsigned 3575 Field_ftsf189ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3576 { 3577 unsigned tie_t = 0; 3578 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3579 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3580 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3581 return tie_t; 3582 } 3583 3584 static void 3585 Field_ftsf189ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3586 { 3587 uint32 tie_t; 3588 tie_t = (val << 30) >> 30; 3589 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3590 tie_t = (val << 28) >> 30; 3591 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3592 tie_t = (val << 24) >> 28; 3593 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3594 } 3595 3596 static unsigned 3597 Field_ftsf184ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3598 { 3599 unsigned tie_t = 0; 3600 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3601 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3602 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3603 return tie_t; 3604 } 3605 3606 static void 3607 Field_ftsf184ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3608 { 3609 uint32 tie_t; 3610 tie_t = (val << 30) >> 30; 3611 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3612 tie_t = (val << 28) >> 30; 3613 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3614 tie_t = (val << 24) >> 28; 3615 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3616 } 3617 3618 static unsigned 3619 Field_ftsf187ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3620 { 3621 unsigned tie_t = 0; 3622 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3623 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3624 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3625 return tie_t; 3626 } 3627 3628 static void 3629 Field_ftsf187ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3630 { 3631 uint32 tie_t; 3632 tie_t = (val << 30) >> 30; 3633 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3634 tie_t = (val << 28) >> 30; 3635 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3636 tie_t = (val << 24) >> 28; 3637 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3638 } 3639 3640 static unsigned 3641 Field_ftsf180ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3642 { 3643 unsigned tie_t = 0; 3644 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3645 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3646 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3647 return tie_t; 3648 } 3649 3650 static void 3651 Field_ftsf180ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3652 { 3653 uint32 tie_t; 3654 tie_t = (val << 30) >> 30; 3655 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3656 tie_t = (val << 28) >> 30; 3657 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3658 tie_t = (val << 24) >> 28; 3659 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3660 } 3661 3662 static unsigned 3663 Field_ftsf188ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3664 { 3665 unsigned tie_t = 0; 3666 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3667 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3668 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3669 return tie_t; 3670 } 3671 3672 static void 3673 Field_ftsf188ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3674 { 3675 uint32 tie_t; 3676 tie_t = (val << 30) >> 30; 3677 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3678 tie_t = (val << 28) >> 30; 3679 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3680 tie_t = (val << 24) >> 28; 3681 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3682 } 3683 3684 static unsigned 3685 Field_ftsf178ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3686 { 3687 unsigned tie_t = 0; 3688 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3689 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3690 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3691 return tie_t; 3692 } 3693 3694 static void 3695 Field_ftsf178ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3696 { 3697 uint32 tie_t; 3698 tie_t = (val << 30) >> 30; 3699 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3700 tie_t = (val << 28) >> 30; 3701 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3702 tie_t = (val << 24) >> 28; 3703 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3704 } 3705 3706 static unsigned 3707 Field_ftsf186ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3708 { 3709 unsigned tie_t = 0; 3710 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3711 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 3712 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 3713 return tie_t; 3714 } 3715 3716 static void 3717 Field_ftsf186ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3718 { 3719 uint32 tie_t; 3720 tie_t = (val << 30) >> 30; 3721 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 3722 tie_t = (val << 28) >> 30; 3723 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 3724 tie_t = (val << 24) >> 28; 3725 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3726 } 3727 3728 static unsigned 3729 Field_ftsf76ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3730 { 3731 unsigned tie_t = 0; 3732 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3733 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3734 return tie_t; 3735 } 3736 3737 static void 3738 Field_ftsf76ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3739 { 3740 uint32 tie_t; 3741 tie_t = (val << 27) >> 27; 3742 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3743 tie_t = (val << 23) >> 28; 3744 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3745 } 3746 3747 static unsigned 3748 Field_ftsf75ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3749 { 3750 unsigned tie_t = 0; 3751 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3752 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3753 return tie_t; 3754 } 3755 3756 static void 3757 Field_ftsf75ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3758 { 3759 uint32 tie_t; 3760 tie_t = (val << 27) >> 27; 3761 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3762 tie_t = (val << 23) >> 28; 3763 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3764 } 3765 3766 static unsigned 3767 Field_ftsf79ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3768 { 3769 unsigned tie_t = 0; 3770 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3771 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3772 return tie_t; 3773 } 3774 3775 static void 3776 Field_ftsf79ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3777 { 3778 uint32 tie_t; 3779 tie_t = (val << 27) >> 27; 3780 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3781 tie_t = (val << 23) >> 28; 3782 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3783 } 3784 3785 static unsigned 3786 Field_ftsf78ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3787 { 3788 unsigned tie_t = 0; 3789 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3790 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3791 return tie_t; 3792 } 3793 3794 static void 3795 Field_ftsf78ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3796 { 3797 uint32 tie_t; 3798 tie_t = (val << 27) >> 27; 3799 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3800 tie_t = (val << 23) >> 28; 3801 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3802 } 3803 3804 static unsigned 3805 Field_ftsf80ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3806 { 3807 unsigned tie_t = 0; 3808 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3809 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3810 return tie_t; 3811 } 3812 3813 static void 3814 Field_ftsf80ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3815 { 3816 uint32 tie_t; 3817 tie_t = (val << 27) >> 27; 3818 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3819 tie_t = (val << 23) >> 28; 3820 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3821 } 3822 3823 static unsigned 3824 Field_ftsf81ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3825 { 3826 unsigned tie_t = 0; 3827 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3828 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3829 return tie_t; 3830 } 3831 3832 static void 3833 Field_ftsf81ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3834 { 3835 uint32 tie_t; 3836 tie_t = (val << 27) >> 27; 3837 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3838 tie_t = (val << 23) >> 28; 3839 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3840 } 3841 3842 static unsigned 3843 Field_ftsf83ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3844 { 3845 unsigned tie_t = 0; 3846 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3847 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3848 return tie_t; 3849 } 3850 3851 static void 3852 Field_ftsf83ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3853 { 3854 uint32 tie_t; 3855 tie_t = (val << 27) >> 27; 3856 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3857 tie_t = (val << 23) >> 28; 3858 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3859 } 3860 3861 static unsigned 3862 Field_ftsf82ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3863 { 3864 unsigned tie_t = 0; 3865 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3866 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3867 return tie_t; 3868 } 3869 3870 static void 3871 Field_ftsf82ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3872 { 3873 uint32 tie_t; 3874 tie_t = (val << 27) >> 27; 3875 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3876 tie_t = (val << 23) >> 28; 3877 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3878 } 3879 3880 static unsigned 3881 Field_ftsf69ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3882 { 3883 unsigned tie_t = 0; 3884 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3885 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3886 return tie_t; 3887 } 3888 3889 static void 3890 Field_ftsf69ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3891 { 3892 uint32 tie_t; 3893 tie_t = (val << 27) >> 27; 3894 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3895 tie_t = (val << 23) >> 28; 3896 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3897 } 3898 3899 static unsigned 3900 Field_ftsf103ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3901 { 3902 unsigned tie_t = 0; 3903 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 3904 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 3905 return tie_t; 3906 } 3907 3908 static void 3909 Field_ftsf103ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3910 { 3911 uint32 tie_t; 3912 tie_t = (val << 31) >> 31; 3913 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 3914 tie_t = (val << 30) >> 31; 3915 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 3916 } 3917 3918 static unsigned 3919 Field_ftsf337ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3920 { 3921 unsigned tie_t = 0; 3922 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3923 tie_t = (tie_t << 2) | ((insn[0] << 21) >> 30); 3924 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 3925 return tie_t; 3926 } 3927 3928 static void 3929 Field_ftsf337ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3930 { 3931 uint32 tie_t; 3932 tie_t = (val << 31) >> 31; 3933 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 3934 tie_t = (val << 29) >> 30; 3935 insn[0] = (insn[0] & ~0x600) | (tie_t << 9); 3936 tie_t = (val << 25) >> 28; 3937 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3938 } 3939 3940 static unsigned 3941 Field_ftsf71ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3942 { 3943 unsigned tie_t = 0; 3944 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3945 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3946 return tie_t; 3947 } 3948 3949 static void 3950 Field_ftsf71ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3951 { 3952 uint32 tie_t; 3953 tie_t = (val << 27) >> 27; 3954 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3955 tie_t = (val << 23) >> 28; 3956 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3957 } 3958 3959 static unsigned 3960 Field_ftsf70ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3961 { 3962 unsigned tie_t = 0; 3963 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3964 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3965 return tie_t; 3966 } 3967 3968 static void 3969 Field_ftsf70ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3970 { 3971 uint32 tie_t; 3972 tie_t = (val << 27) >> 27; 3973 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3974 tie_t = (val << 23) >> 28; 3975 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3976 } 3977 3978 static unsigned 3979 Field_ftsf77ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3980 { 3981 unsigned tie_t = 0; 3982 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 3983 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 3984 return tie_t; 3985 } 3986 3987 static void 3988 Field_ftsf77ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 3989 { 3990 uint32 tie_t; 3991 tie_t = (val << 27) >> 27; 3992 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 3993 tie_t = (val << 23) >> 28; 3994 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 3995 } 3996 3997 static unsigned 3998 Field_ftsf73ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 3999 { 4000 unsigned tie_t = 0; 4001 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4002 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4003 return tie_t; 4004 } 4005 4006 static void 4007 Field_ftsf73ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4008 { 4009 uint32 tie_t; 4010 tie_t = (val << 27) >> 27; 4011 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4012 tie_t = (val << 23) >> 28; 4013 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4014 } 4015 4016 static unsigned 4017 Field_ftsf74ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4018 { 4019 unsigned tie_t = 0; 4020 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4021 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4022 return tie_t; 4023 } 4024 4025 static void 4026 Field_ftsf74ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4027 { 4028 uint32 tie_t; 4029 tie_t = (val << 27) >> 27; 4030 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4031 tie_t = (val << 23) >> 28; 4032 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4033 } 4034 4035 static unsigned 4036 Field_ftsf72ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4037 { 4038 unsigned tie_t = 0; 4039 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4040 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4041 return tie_t; 4042 } 4043 4044 static void 4045 Field_ftsf72ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4046 { 4047 uint32 tie_t; 4048 tie_t = (val << 27) >> 27; 4049 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4050 tie_t = (val << 23) >> 28; 4051 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4052 } 4053 4054 static unsigned 4055 Field_ftsf85ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4056 { 4057 unsigned tie_t = 0; 4058 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4059 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4060 return tie_t; 4061 } 4062 4063 static void 4064 Field_ftsf85ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4065 { 4066 uint32 tie_t; 4067 tie_t = (val << 27) >> 27; 4068 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4069 tie_t = (val << 23) >> 28; 4070 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4071 } 4072 4073 static unsigned 4074 Field_ftsf84ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4075 { 4076 unsigned tie_t = 0; 4077 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4078 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4079 return tie_t; 4080 } 4081 4082 static void 4083 Field_ftsf84ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4084 { 4085 uint32 tie_t; 4086 tie_t = (val << 27) >> 27; 4087 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4088 tie_t = (val << 23) >> 28; 4089 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4090 } 4091 4092 static unsigned 4093 Field_ftsf86ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4094 { 4095 unsigned tie_t = 0; 4096 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4097 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4098 return tie_t; 4099 } 4100 4101 static void 4102 Field_ftsf86ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4103 { 4104 uint32 tie_t; 4105 tie_t = (val << 27) >> 27; 4106 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4107 tie_t = (val << 23) >> 28; 4108 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4109 } 4110 4111 static unsigned 4112 Field_ftsf102ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4113 { 4114 unsigned tie_t = 0; 4115 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 4116 return tie_t; 4117 } 4118 4119 static void 4120 Field_ftsf102ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4121 { 4122 uint32 tie_t; 4123 tie_t = (val << 28) >> 28; 4124 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 4125 } 4126 4127 static unsigned 4128 Field_ftsf336ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4129 { 4130 unsigned tie_t = 0; 4131 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4132 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 4133 return tie_t; 4134 } 4135 4136 static void 4137 Field_ftsf336ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4138 { 4139 uint32 tie_t; 4140 tie_t = (val << 31) >> 31; 4141 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 4142 tie_t = (val << 27) >> 28; 4143 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4144 } 4145 4146 static unsigned 4147 Field_ftsf89ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4148 { 4149 unsigned tie_t = 0; 4150 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4151 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4152 return tie_t; 4153 } 4154 4155 static void 4156 Field_ftsf89ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4157 { 4158 uint32 tie_t; 4159 tie_t = (val << 27) >> 27; 4160 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4161 tie_t = (val << 23) >> 28; 4162 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4163 } 4164 4165 static unsigned 4166 Field_ftsf87ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4167 { 4168 unsigned tie_t = 0; 4169 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4170 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4171 return tie_t; 4172 } 4173 4174 static void 4175 Field_ftsf87ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4176 { 4177 uint32 tie_t; 4178 tie_t = (val << 27) >> 27; 4179 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4180 tie_t = (val << 23) >> 28; 4181 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4182 } 4183 4184 static unsigned 4185 Field_ftsf88ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4186 { 4187 unsigned tie_t = 0; 4188 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4189 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4190 return tie_t; 4191 } 4192 4193 static void 4194 Field_ftsf88ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4195 { 4196 uint32 tie_t; 4197 tie_t = (val << 27) >> 27; 4198 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4199 tie_t = (val << 23) >> 28; 4200 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4201 } 4202 4203 static unsigned 4204 Field_ftsf101ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4205 { 4206 unsigned tie_t = 0; 4207 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 4208 tie_t = (tie_t << 5) | ((insn[0] << 20) >> 27); 4209 return tie_t; 4210 } 4211 4212 static void 4213 Field_ftsf101ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4214 { 4215 uint32 tie_t; 4216 tie_t = (val << 27) >> 27; 4217 insn[0] = (insn[0] & ~0xf80) | (tie_t << 7); 4218 tie_t = (val << 26) >> 31; 4219 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 4220 } 4221 4222 static unsigned 4223 Field_ftsf335_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4224 { 4225 unsigned tie_t = 0; 4226 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 4227 return tie_t; 4228 } 4229 4230 static void 4231 Field_ftsf335_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4232 { 4233 uint32 tie_t; 4234 tie_t = (val << 29) >> 29; 4235 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 4236 } 4237 4238 static unsigned 4239 Field_t_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4240 { 4241 unsigned tie_t = 0; 4242 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4243 return tie_t; 4244 } 4245 4246 static void 4247 Field_t_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4248 { 4249 uint32 tie_t; 4250 tie_t = (val << 28) >> 28; 4251 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4252 } 4253 4254 static unsigned 4255 Field_ftsf196ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4256 { 4257 unsigned tie_t = 0; 4258 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4259 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4260 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4261 return tie_t; 4262 } 4263 4264 static void 4265 Field_ftsf196ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4266 { 4267 uint32 tie_t; 4268 tie_t = (val << 30) >> 30; 4269 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4270 tie_t = (val << 28) >> 30; 4271 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4272 tie_t = (val << 24) >> 28; 4273 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4274 } 4275 4276 static unsigned 4277 Field_ftsf208ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4278 { 4279 unsigned tie_t = 0; 4280 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4281 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 4282 return tie_t; 4283 } 4284 4285 static void 4286 Field_ftsf208ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4287 { 4288 uint32 tie_t; 4289 tie_t = (val << 31) >> 31; 4290 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 4291 tie_t = (val << 27) >> 28; 4292 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4293 } 4294 4295 static unsigned 4296 Field_ftsf341ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4297 { 4298 unsigned tie_t = 0; 4299 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4300 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 4301 return tie_t; 4302 } 4303 4304 static void 4305 Field_ftsf341ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4306 { 4307 uint32 tie_t; 4308 tie_t = (val << 31) >> 31; 4309 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 4310 tie_t = (val << 29) >> 30; 4311 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4312 } 4313 4314 static unsigned 4315 Field_ftsf200ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4316 { 4317 unsigned tie_t = 0; 4318 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4319 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4320 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4321 return tie_t; 4322 } 4323 4324 static void 4325 Field_ftsf200ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4326 { 4327 uint32 tie_t; 4328 tie_t = (val << 30) >> 30; 4329 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4330 tie_t = (val << 28) >> 30; 4331 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4332 tie_t = (val << 24) >> 28; 4333 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4334 } 4335 4336 static unsigned 4337 Field_ftsf340ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4338 { 4339 unsigned tie_t = 0; 4340 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 4341 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4342 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4343 return tie_t; 4344 } 4345 4346 static void 4347 Field_ftsf340ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4348 { 4349 uint32 tie_t; 4350 tie_t = (val << 30) >> 30; 4351 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4352 tie_t = (val << 28) >> 30; 4353 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4354 tie_t = (val << 27) >> 31; 4355 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 4356 } 4357 4358 static unsigned 4359 Field_ftsf195ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4360 { 4361 unsigned tie_t = 0; 4362 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4363 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4364 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4365 return tie_t; 4366 } 4367 4368 static void 4369 Field_ftsf195ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4370 { 4371 uint32 tie_t; 4372 tie_t = (val << 30) >> 30; 4373 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4374 tie_t = (val << 28) >> 30; 4375 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4376 tie_t = (val << 24) >> 28; 4377 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4378 } 4379 4380 static unsigned 4381 Field_ftsf198ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4382 { 4383 unsigned tie_t = 0; 4384 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4385 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4386 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4387 return tie_t; 4388 } 4389 4390 static void 4391 Field_ftsf198ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4392 { 4393 uint32 tie_t; 4394 tie_t = (val << 30) >> 30; 4395 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4396 tie_t = (val << 28) >> 30; 4397 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4398 tie_t = (val << 24) >> 28; 4399 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4400 } 4401 4402 static unsigned 4403 Field_ftsf197ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4404 { 4405 unsigned tie_t = 0; 4406 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4407 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4408 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4409 return tie_t; 4410 } 4411 4412 static void 4413 Field_ftsf197ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4414 { 4415 uint32 tie_t; 4416 tie_t = (val << 30) >> 30; 4417 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4418 tie_t = (val << 28) >> 30; 4419 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4420 tie_t = (val << 24) >> 28; 4421 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4422 } 4423 4424 static unsigned 4425 Field_ftsf199ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4426 { 4427 unsigned tie_t = 0; 4428 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4429 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4430 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4431 return tie_t; 4432 } 4433 4434 static void 4435 Field_ftsf199ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4436 { 4437 uint32 tie_t; 4438 tie_t = (val << 30) >> 30; 4439 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4440 tie_t = (val << 28) >> 30; 4441 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4442 tie_t = (val << 24) >> 28; 4443 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4444 } 4445 4446 static unsigned 4447 Field_ftsf201ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4448 { 4449 unsigned tie_t = 0; 4450 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4451 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4452 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4453 return tie_t; 4454 } 4455 4456 static void 4457 Field_ftsf201ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4458 { 4459 uint32 tie_t; 4460 tie_t = (val << 30) >> 30; 4461 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4462 tie_t = (val << 28) >> 30; 4463 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4464 tie_t = (val << 24) >> 28; 4465 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4466 } 4467 4468 static unsigned 4469 Field_ftsf204ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4470 { 4471 unsigned tie_t = 0; 4472 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4473 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4474 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4475 return tie_t; 4476 } 4477 4478 static void 4479 Field_ftsf204ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4480 { 4481 uint32 tie_t; 4482 tie_t = (val << 30) >> 30; 4483 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4484 tie_t = (val << 28) >> 30; 4485 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4486 tie_t = (val << 24) >> 28; 4487 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4488 } 4489 4490 static unsigned 4491 Field_ftsf202ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4492 { 4493 unsigned tie_t = 0; 4494 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4495 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4496 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4497 return tie_t; 4498 } 4499 4500 static void 4501 Field_ftsf202ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4502 { 4503 uint32 tie_t; 4504 tie_t = (val << 30) >> 30; 4505 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4506 tie_t = (val << 28) >> 30; 4507 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4508 tie_t = (val << 24) >> 28; 4509 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4510 } 4511 4512 static unsigned 4513 Field_ftsf203ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4514 { 4515 unsigned tie_t = 0; 4516 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4517 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4518 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4519 return tie_t; 4520 } 4521 4522 static void 4523 Field_ftsf203ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4524 { 4525 uint32 tie_t; 4526 tie_t = (val << 30) >> 30; 4527 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4528 tie_t = (val << 28) >> 30; 4529 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4530 tie_t = (val << 24) >> 28; 4531 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4532 } 4533 4534 static unsigned 4535 Field_ftsf205ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4536 { 4537 unsigned tie_t = 0; 4538 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4539 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4540 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4541 return tie_t; 4542 } 4543 4544 static void 4545 Field_ftsf205ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4546 { 4547 uint32 tie_t; 4548 tie_t = (val << 30) >> 30; 4549 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4550 tie_t = (val << 28) >> 30; 4551 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4552 tie_t = (val << 24) >> 28; 4553 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4554 } 4555 4556 static unsigned 4557 Field_ftsf207ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4558 { 4559 unsigned tie_t = 0; 4560 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4561 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4562 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4563 return tie_t; 4564 } 4565 4566 static void 4567 Field_ftsf207ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4568 { 4569 uint32 tie_t; 4570 tie_t = (val << 30) >> 30; 4571 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4572 tie_t = (val << 28) >> 30; 4573 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4574 tie_t = (val << 24) >> 28; 4575 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4576 } 4577 4578 static unsigned 4579 Field_ftsf206ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4580 { 4581 unsigned tie_t = 0; 4582 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4583 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4584 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4585 return tie_t; 4586 } 4587 4588 static void 4589 Field_ftsf206ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4590 { 4591 uint32 tie_t; 4592 tie_t = (val << 30) >> 30; 4593 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4594 tie_t = (val << 28) >> 30; 4595 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4596 tie_t = (val << 24) >> 28; 4597 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4598 } 4599 4600 static unsigned 4601 Field_ftsf210ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4602 { 4603 unsigned tie_t = 0; 4604 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4605 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 4606 return tie_t; 4607 } 4608 4609 static void 4610 Field_ftsf210ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4611 { 4612 uint32 tie_t; 4613 tie_t = (val << 31) >> 31; 4614 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 4615 tie_t = (val << 27) >> 28; 4616 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4617 } 4618 4619 static unsigned 4620 Field_ftsf339ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4621 { 4622 unsigned tie_t = 0; 4623 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4624 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 4625 return tie_t; 4626 } 4627 4628 static void 4629 Field_ftsf339ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4630 { 4631 uint32 tie_t; 4632 tie_t = (val << 31) >> 31; 4633 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 4634 tie_t = (val << 29) >> 30; 4635 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4636 } 4637 4638 static unsigned 4639 Field_ftsf128ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4640 { 4641 unsigned tie_t = 0; 4642 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4643 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4644 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4645 return tie_t; 4646 } 4647 4648 static void 4649 Field_ftsf128ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4650 { 4651 uint32 tie_t; 4652 tie_t = (val << 30) >> 30; 4653 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4654 tie_t = (val << 28) >> 30; 4655 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4656 tie_t = (val << 24) >> 28; 4657 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4658 } 4659 4660 static unsigned 4661 Field_ftsf130ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4662 { 4663 unsigned tie_t = 0; 4664 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4665 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4666 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4667 return tie_t; 4668 } 4669 4670 static void 4671 Field_ftsf130ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4672 { 4673 uint32 tie_t; 4674 tie_t = (val << 30) >> 30; 4675 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4676 tie_t = (val << 28) >> 30; 4677 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4678 tie_t = (val << 24) >> 28; 4679 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4680 } 4681 4682 static unsigned 4683 Field_ftsf129ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4684 { 4685 unsigned tie_t = 0; 4686 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4687 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4688 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4689 return tie_t; 4690 } 4691 4692 static void 4693 Field_ftsf129ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4694 { 4695 uint32 tie_t; 4696 tie_t = (val << 30) >> 30; 4697 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4698 tie_t = (val << 28) >> 30; 4699 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4700 tie_t = (val << 24) >> 28; 4701 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4702 } 4703 4704 static unsigned 4705 Field_ftsf132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4706 { 4707 unsigned tie_t = 0; 4708 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4709 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4710 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4711 return tie_t; 4712 } 4713 4714 static void 4715 Field_ftsf132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4716 { 4717 uint32 tie_t; 4718 tie_t = (val << 30) >> 30; 4719 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4720 tie_t = (val << 28) >> 30; 4721 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4722 tie_t = (val << 24) >> 28; 4723 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4724 } 4725 4726 static unsigned 4727 Field_ftsf147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4728 { 4729 unsigned tie_t = 0; 4730 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4731 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4732 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4733 return tie_t; 4734 } 4735 4736 static void 4737 Field_ftsf147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4738 { 4739 uint32 tie_t; 4740 tie_t = (val << 30) >> 30; 4741 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4742 tie_t = (val << 28) >> 30; 4743 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4744 tie_t = (val << 24) >> 28; 4745 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4746 } 4747 4748 static unsigned 4749 Field_ftsf150ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4750 { 4751 unsigned tie_t = 0; 4752 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4753 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4754 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4755 return tie_t; 4756 } 4757 4758 static void 4759 Field_ftsf150ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4760 { 4761 uint32 tie_t; 4762 tie_t = (val << 30) >> 30; 4763 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4764 tie_t = (val << 28) >> 30; 4765 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4766 tie_t = (val << 24) >> 28; 4767 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4768 } 4769 4770 static unsigned 4771 Field_ftsf149ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4772 { 4773 unsigned tie_t = 0; 4774 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4775 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4776 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4777 return tie_t; 4778 } 4779 4780 static void 4781 Field_ftsf149ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4782 { 4783 uint32 tie_t; 4784 tie_t = (val << 30) >> 30; 4785 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4786 tie_t = (val << 28) >> 30; 4787 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4788 tie_t = (val << 24) >> 28; 4789 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4790 } 4791 4792 static unsigned 4793 Field_ftsf151ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4794 { 4795 unsigned tie_t = 0; 4796 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4797 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4798 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4799 return tie_t; 4800 } 4801 4802 static void 4803 Field_ftsf151ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4804 { 4805 uint32 tie_t; 4806 tie_t = (val << 30) >> 30; 4807 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4808 tie_t = (val << 28) >> 30; 4809 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4810 tie_t = (val << 24) >> 28; 4811 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4812 } 4813 4814 static unsigned 4815 Field_ftsf163ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4816 { 4817 unsigned tie_t = 0; 4818 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4819 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4820 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4821 return tie_t; 4822 } 4823 4824 static void 4825 Field_ftsf163ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4826 { 4827 uint32 tie_t; 4828 tie_t = (val << 30) >> 30; 4829 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4830 tie_t = (val << 28) >> 30; 4831 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4832 tie_t = (val << 24) >> 28; 4833 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4834 } 4835 4836 static unsigned 4837 Field_ftsf166ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4838 { 4839 unsigned tie_t = 0; 4840 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4841 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4842 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4843 return tie_t; 4844 } 4845 4846 static void 4847 Field_ftsf166ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4848 { 4849 uint32 tie_t; 4850 tie_t = (val << 30) >> 30; 4851 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4852 tie_t = (val << 28) >> 30; 4853 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4854 tie_t = (val << 24) >> 28; 4855 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4856 } 4857 4858 static unsigned 4859 Field_ftsf165ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4860 { 4861 unsigned tie_t = 0; 4862 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4863 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4864 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4865 return tie_t; 4866 } 4867 4868 static void 4869 Field_ftsf165ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4870 { 4871 uint32 tie_t; 4872 tie_t = (val << 30) >> 30; 4873 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4874 tie_t = (val << 28) >> 30; 4875 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4876 tie_t = (val << 24) >> 28; 4877 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4878 } 4879 4880 static unsigned 4881 Field_ftsf167ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4882 { 4883 unsigned tie_t = 0; 4884 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4885 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4886 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4887 return tie_t; 4888 } 4889 4890 static void 4891 Field_ftsf167ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4892 { 4893 uint32 tie_t; 4894 tie_t = (val << 30) >> 30; 4895 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4896 tie_t = (val << 28) >> 30; 4897 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4898 tie_t = (val << 24) >> 28; 4899 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4900 } 4901 4902 static unsigned 4903 Field_ftsf190ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4904 { 4905 unsigned tie_t = 0; 4906 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4907 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4908 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4909 return tie_t; 4910 } 4911 4912 static void 4913 Field_ftsf190ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4914 { 4915 uint32 tie_t; 4916 tie_t = (val << 30) >> 30; 4917 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4918 tie_t = (val << 28) >> 30; 4919 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4920 tie_t = (val << 24) >> 28; 4921 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4922 } 4923 4924 static unsigned 4925 Field_ftsf193ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4926 { 4927 unsigned tie_t = 0; 4928 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4929 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4930 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4931 return tie_t; 4932 } 4933 4934 static void 4935 Field_ftsf193ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4936 { 4937 uint32 tie_t; 4938 tie_t = (val << 30) >> 30; 4939 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4940 tie_t = (val << 28) >> 30; 4941 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4942 tie_t = (val << 24) >> 28; 4943 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4944 } 4945 4946 static unsigned 4947 Field_ftsf191ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4948 { 4949 unsigned tie_t = 0; 4950 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4951 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4952 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4953 return tie_t; 4954 } 4955 4956 static void 4957 Field_ftsf191ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4958 { 4959 uint32 tie_t; 4960 tie_t = (val << 30) >> 30; 4961 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4962 tie_t = (val << 28) >> 30; 4963 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4964 tie_t = (val << 24) >> 28; 4965 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4966 } 4967 4968 static unsigned 4969 Field_ftsf194ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4970 { 4971 unsigned tie_t = 0; 4972 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 4973 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 4974 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 4975 return tie_t; 4976 } 4977 4978 static void 4979 Field_ftsf194ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 4980 { 4981 uint32 tie_t; 4982 tie_t = (val << 30) >> 30; 4983 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 4984 tie_t = (val << 28) >> 30; 4985 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 4986 tie_t = (val << 24) >> 28; 4987 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 4988 } 4989 4990 static unsigned 4991 Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 4992 { 4993 unsigned tie_t = 0; 4994 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 4995 return tie_t; 4996 } 4997 4998 static void 4999 Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5000 { 5001 uint32 tie_t; 5002 tie_t = (val << 31) >> 31; 5003 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5004 } 5005 5006 static unsigned 5007 Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5008 { 5009 unsigned tie_t = 0; 5010 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 5011 return tie_t; 5012 } 5013 5014 static void 5015 Field_combined2c0b5f72_fld69_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5016 { 5017 uint32 tie_t; 5018 tie_t = (val << 31) >> 31; 5019 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 5020 } 5021 5022 static unsigned 5023 Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5024 { 5025 unsigned tie_t = 0; 5026 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 5027 return tie_t; 5028 } 5029 5030 static void 5031 Field_combined2c0b5f72_fld68_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5032 { 5033 uint32 tie_t; 5034 tie_t = (val << 30) >> 30; 5035 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 5036 } 5037 5038 static unsigned 5039 Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5040 { 5041 unsigned tie_t = 0; 5042 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 5043 return tie_t; 5044 } 5045 5046 static void 5047 Field_combined2c0b5f72_fld19_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5048 { 5049 uint32 tie_t; 5050 tie_t = (val << 31) >> 31; 5051 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 5052 } 5053 5054 static unsigned 5055 Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5056 { 5057 unsigned tie_t = 0; 5058 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 5059 return tie_t; 5060 } 5061 5062 static void 5063 Field_combined2c0b5f72_fld22_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5064 { 5065 uint32 tie_t; 5066 tie_t = (val << 31) >> 31; 5067 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 5068 } 5069 5070 static unsigned 5071 Field_op0_s3_s3_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5072 { 5073 unsigned tie_t = 0; 5074 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); 5075 return tie_t; 5076 } 5077 5078 static void 5079 Field_op0_s3_s3_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5080 { 5081 uint32 tie_t; 5082 tie_t = (val << 25) >> 25; 5083 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); 5084 } 5085 5086 static unsigned 5087 Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5088 { 5089 unsigned tie_t = 0; 5090 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5091 return tie_t; 5092 } 5093 5094 static void 5095 Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5096 { 5097 uint32 tie_t; 5098 tie_t = (val << 31) >> 31; 5099 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5100 } 5101 5102 static unsigned 5103 Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5104 { 5105 unsigned tie_t = 0; 5106 tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); 5107 return tie_t; 5108 } 5109 5110 static void 5111 Field_combined2c0b5f72_fld74_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5112 { 5113 uint32 tie_t; 5114 tie_t = (val << 31) >> 31; 5115 insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); 5116 } 5117 5118 static unsigned 5119 Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5120 { 5121 unsigned tie_t = 0; 5122 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5123 return tie_t; 5124 } 5125 5126 static void 5127 Field_combined2c0b5f72_fld66_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5128 { 5129 uint32 tie_t; 5130 tie_t = (val << 31) >> 31; 5131 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5132 } 5133 5134 static unsigned 5135 Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5136 { 5137 unsigned tie_t = 0; 5138 tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); 5139 return tie_t; 5140 } 5141 5142 static void 5143 Field_combined2c0b5f72_fld91_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5144 { 5145 uint32 tie_t; 5146 tie_t = (val << 31) >> 31; 5147 insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); 5148 } 5149 5150 static unsigned 5151 Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5152 { 5153 unsigned tie_t = 0; 5154 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 5155 return tie_t; 5156 } 5157 5158 static void 5159 Field_combined2c0b5f72_fld90_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5160 { 5161 uint32 tie_t; 5162 tie_t = (val << 31) >> 31; 5163 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 5164 } 5165 5166 static unsigned 5167 Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5168 { 5169 unsigned tie_t = 0; 5170 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 5171 return tie_t; 5172 } 5173 5174 static void 5175 Field_combined2c0b5f72_fld88_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5176 { 5177 uint32 tie_t; 5178 tie_t = (val << 31) >> 31; 5179 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 5180 } 5181 5182 static unsigned 5183 Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5184 { 5185 unsigned tie_t = 0; 5186 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 5187 return tie_t; 5188 } 5189 5190 static void 5191 Field_combined2c0b5f72_fld65_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5192 { 5193 uint32 tie_t; 5194 tie_t = (val << 31) >> 31; 5195 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 5196 } 5197 5198 static unsigned 5199 Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5200 { 5201 unsigned tie_t = 0; 5202 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); 5203 return tie_t; 5204 } 5205 5206 static void 5207 Field_combined2c0b5f72_fld24_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5208 { 5209 uint32 tie_t; 5210 tie_t = (val << 31) >> 31; 5211 insn[0] = (insn[0] & ~0x200) | (tie_t << 9); 5212 } 5213 5214 static unsigned 5215 Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5216 { 5217 unsigned tie_t = 0; 5218 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 5219 return tie_t; 5220 } 5221 5222 static void 5223 Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5224 { 5225 uint32 tie_t; 5226 tie_t = (val << 31) >> 31; 5227 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 5228 } 5229 5230 static unsigned 5231 Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (const xtensa_insnbuf insn) 5232 { 5233 unsigned tie_t = 0; 5234 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 5235 return tie_t; 5236 } 5237 5238 static void 5239 Field_combined2c0b5f72_fld79_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 5240 { 5241 uint32 tie_t; 5242 tie_t = (val << 31) >> 31; 5243 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 5244 } 5245 5246 static unsigned 5247 Field_r_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5248 { 5249 unsigned tie_t = 0; 5250 tie_t = (tie_t << 4) | ((insn[0] << 9) >> 28); 5251 return tie_t; 5252 } 5253 5254 static void 5255 Field_r_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5256 { 5257 uint32 tie_t; 5258 tie_t = (val << 28) >> 28; 5259 insn[0] = (insn[0] & ~0x780000) | (tie_t << 19); 5260 } 5261 5262 static unsigned 5263 Field_op0_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5264 { 5265 unsigned tie_t = 0; 5266 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); 5267 return tie_t; 5268 } 5269 5270 static void 5271 Field_op0_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5272 { 5273 uint32 tie_t; 5274 tie_t = (val << 25) >> 25; 5275 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); 5276 } 5277 5278 static unsigned 5279 Field_imm8_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5280 { 5281 unsigned tie_t = 0; 5282 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5283 return tie_t; 5284 } 5285 5286 static void 5287 Field_imm8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5288 { 5289 uint32 tie_t; 5290 tie_t = (val << 24) >> 24; 5291 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5292 } 5293 5294 static unsigned 5295 Field_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5296 { 5297 unsigned tie_t = 0; 5298 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 5299 return tie_t; 5300 } 5301 5302 static void 5303 Field_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5304 { 5305 uint32 tie_t; 5306 tie_t = (val << 28) >> 28; 5307 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 5308 } 5309 5310 static unsigned 5311 Field_ftsf280_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5312 { 5313 unsigned tie_t = 0; 5314 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 5315 return tie_t; 5316 } 5317 5318 static void 5319 Field_ftsf280_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5320 { 5321 uint32 tie_t; 5322 tie_t = (val << 29) >> 29; 5323 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 5324 } 5325 5326 static unsigned 5327 Field_ftsf288_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5328 { 5329 unsigned tie_t = 0; 5330 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); 5331 return tie_t; 5332 } 5333 5334 static void 5335 Field_ftsf288_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5336 { 5337 uint32 tie_t; 5338 tie_t = (val << 31) >> 31; 5339 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); 5340 } 5341 5342 static unsigned 5343 Field_ftsf360ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5344 { 5345 unsigned tie_t = 0; 5346 tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); 5347 return tie_t; 5348 } 5349 5350 static void 5351 Field_ftsf360ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5352 { 5353 uint32 tie_t; 5354 tie_t = (val << 29) >> 29; 5355 insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); 5356 } 5357 5358 static unsigned 5359 Field_ftsf213ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5360 { 5361 unsigned tie_t = 0; 5362 tie_t = (tie_t << 4) | ((insn[0] << 21) >> 28); 5363 return tie_t; 5364 } 5365 5366 static void 5367 Field_ftsf213ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5368 { 5369 uint32 tie_t; 5370 tie_t = (val << 28) >> 28; 5371 insn[0] = (insn[0] & ~0x780) | (tie_t << 7); 5372 } 5373 5374 static unsigned 5375 Field_ftsf212ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5376 { 5377 unsigned tie_t = 0; 5378 tie_t = (tie_t << 3) | ((insn[0] << 22) >> 29); 5379 return tie_t; 5380 } 5381 5382 static void 5383 Field_ftsf212ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5384 { 5385 uint32 tie_t; 5386 tie_t = (val << 29) >> 29; 5387 insn[0] = (insn[0] & ~0x380) | (tie_t << 7); 5388 } 5389 5390 static unsigned 5391 Field_ftsf211ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5392 { 5393 unsigned tie_t = 0; 5394 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 5395 return tie_t; 5396 } 5397 5398 static void 5399 Field_ftsf211ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5400 { 5401 uint32 tie_t; 5402 tie_t = (val << 30) >> 30; 5403 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 5404 } 5405 5406 static unsigned 5407 Field_ftsf279ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5408 { 5409 unsigned tie_t = 0; 5410 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 5411 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 5412 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5413 return tie_t; 5414 } 5415 5416 static void 5417 Field_ftsf279ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5418 { 5419 uint32 tie_t; 5420 tie_t = (val << 24) >> 24; 5421 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5422 tie_t = (val << 21) >> 29; 5423 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 5424 tie_t = (val << 17) >> 28; 5425 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 5426 } 5427 5428 static unsigned 5429 Field_s8_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5430 { 5431 unsigned tie_t = 0; 5432 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 5433 return tie_t; 5434 } 5435 5436 static void 5437 Field_s8_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5438 { 5439 uint32 tie_t; 5440 tie_t = (val << 31) >> 31; 5441 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 5442 } 5443 5444 static unsigned 5445 Field_ftsf313ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5446 { 5447 unsigned tie_t = 0; 5448 tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); 5449 return tie_t; 5450 } 5451 5452 static void 5453 Field_ftsf313ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5454 { 5455 uint32 tie_t; 5456 tie_t = (val << 20) >> 20; 5457 insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); 5458 } 5459 5460 static unsigned 5461 Field_ftsf282ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5462 { 5463 unsigned tie_t = 0; 5464 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 5465 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 5466 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 5467 return tie_t; 5468 } 5469 5470 static void 5471 Field_ftsf282ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5472 { 5473 uint32 tie_t; 5474 tie_t = (val << 25) >> 25; 5475 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 5476 tie_t = (val << 22) >> 29; 5477 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 5478 tie_t = (val << 18) >> 28; 5479 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 5480 } 5481 5482 static unsigned 5483 Field_ftsf361ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5484 { 5485 unsigned tie_t = 0; 5486 tie_t = (tie_t << 1) | ((insn[0] << 9) >> 31); 5487 tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); 5488 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 5489 return tie_t; 5490 } 5491 5492 static void 5493 Field_ftsf361ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5494 { 5495 uint32 tie_t; 5496 tie_t = (val << 31) >> 31; 5497 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 5498 tie_t = (val << 27) >> 28; 5499 insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); 5500 tie_t = (val << 26) >> 31; 5501 insn[0] = (insn[0] & ~0x400000) | (tie_t << 22); 5502 } 5503 5504 static unsigned 5505 Field_ftsf281ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5506 { 5507 unsigned tie_t = 0; 5508 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 5509 tie_t = (tie_t << 3) | ((insn[0] << 10) >> 29); 5510 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5511 return tie_t; 5512 } 5513 5514 static void 5515 Field_ftsf281ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5516 { 5517 uint32 tie_t; 5518 tie_t = (val << 24) >> 24; 5519 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5520 tie_t = (val << 21) >> 29; 5521 insn[0] = (insn[0] & ~0x380000) | (tie_t << 19); 5522 tie_t = (val << 17) >> 28; 5523 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 5524 } 5525 5526 static unsigned 5527 Field_ftsf287ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5528 { 5529 unsigned tie_t = 0; 5530 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); 5531 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 5532 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 5533 return tie_t; 5534 } 5535 5536 static void 5537 Field_ftsf287ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5538 { 5539 uint32 tie_t; 5540 tie_t = (val << 25) >> 25; 5541 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 5542 tie_t = (val << 23) >> 30; 5543 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 5544 tie_t = (val << 22) >> 31; 5545 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); 5546 } 5547 5548 static unsigned 5549 Field_ftsf368ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5550 { 5551 unsigned tie_t = 0; 5552 tie_t = (tie_t << 5) | ((insn[0] << 6) >> 27); 5553 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 5554 return tie_t; 5555 } 5556 5557 static void 5558 Field_ftsf368ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5559 { 5560 uint32 tie_t; 5561 tie_t = (val << 31) >> 31; 5562 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 5563 tie_t = (val << 26) >> 27; 5564 insn[0] = (insn[0] & ~0x3e00000) | (tie_t << 21); 5565 } 5566 5567 static unsigned 5568 Field_ftsf285ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5569 { 5570 unsigned tie_t = 0; 5571 tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); 5572 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 5573 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 5574 return tie_t; 5575 } 5576 5577 static void 5578 Field_ftsf285ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5579 { 5580 uint32 tie_t; 5581 tie_t = (val << 25) >> 25; 5582 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 5583 tie_t = (val << 23) >> 30; 5584 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 5585 tie_t = (val << 21) >> 30; 5586 insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); 5587 } 5588 5589 static unsigned 5590 Field_ftsf366ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5591 { 5592 unsigned tie_t = 0; 5593 tie_t = (tie_t << 4) | ((insn[0] << 7) >> 28); 5594 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 5595 return tie_t; 5596 } 5597 5598 static void 5599 Field_ftsf366ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5600 { 5601 uint32 tie_t; 5602 tie_t = (val << 31) >> 31; 5603 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 5604 tie_t = (val << 27) >> 28; 5605 insn[0] = (insn[0] & ~0x1e00000) | (tie_t << 21); 5606 } 5607 5608 static unsigned 5609 Field_ftsf284ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5610 { 5611 unsigned tie_t = 0; 5612 tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); 5613 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 5614 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 5615 return tie_t; 5616 } 5617 5618 static void 5619 Field_ftsf284ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5620 { 5621 uint32 tie_t; 5622 tie_t = (val << 25) >> 25; 5623 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 5624 tie_t = (val << 23) >> 30; 5625 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 5626 tie_t = (val << 20) >> 29; 5627 insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); 5628 } 5629 5630 static unsigned 5631 Field_ftsf364ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5632 { 5633 unsigned tie_t = 0; 5634 tie_t = (tie_t << 3) | ((insn[0] << 8) >> 29); 5635 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 5636 return tie_t; 5637 } 5638 5639 static void 5640 Field_ftsf364ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5641 { 5642 uint32 tie_t; 5643 tie_t = (val << 31) >> 31; 5644 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 5645 tie_t = (val << 28) >> 29; 5646 insn[0] = (insn[0] & ~0xe00000) | (tie_t << 21); 5647 } 5648 5649 static unsigned 5650 Field_ftsf297ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5651 { 5652 unsigned tie_t = 0; 5653 tie_t = (tie_t << 14) | ((insn[0] << 11) >> 18); 5654 return tie_t; 5655 } 5656 5657 static void 5658 Field_ftsf297ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5659 { 5660 uint32 tie_t; 5661 tie_t = (val << 18) >> 18; 5662 insn[0] = (insn[0] & ~0x1fff80) | (tie_t << 7); 5663 } 5664 5665 static unsigned 5666 Field_ftsf309_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5667 { 5668 unsigned tie_t = 0; 5669 tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); 5670 return tie_t; 5671 } 5672 5673 static void 5674 Field_ftsf309_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5675 { 5676 uint32 tie_t; 5677 tie_t = (val << 31) >> 31; 5678 insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); 5679 } 5680 5681 static unsigned 5682 Field_ftsf327ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5683 { 5684 unsigned tie_t = 0; 5685 tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); 5686 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 5687 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5688 return tie_t; 5689 } 5690 5691 static void 5692 Field_ftsf327ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5693 { 5694 uint32 tie_t; 5695 tie_t = (val << 24) >> 24; 5696 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5697 tie_t = (val << 23) >> 31; 5698 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 5699 tie_t = (val << 21) >> 30; 5700 insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); 5701 } 5702 5703 static unsigned 5704 Field_ftsf363ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5705 { 5706 unsigned tie_t = 0; 5707 tie_t = (tie_t << 1) | ((insn[0] << 7) >> 31); 5708 return tie_t; 5709 } 5710 5711 static void 5712 Field_ftsf363ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5713 { 5714 uint32 tie_t; 5715 tie_t = (val << 31) >> 31; 5716 insn[0] = (insn[0] & ~0x1000000) | (tie_t << 24); 5717 } 5718 5719 static unsigned 5720 Field_ftsf214ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5721 { 5722 unsigned tie_t = 0; 5723 tie_t = (tie_t << 7) | ((insn[0] << 18) >> 25); 5724 return tie_t; 5725 } 5726 5727 static void 5728 Field_ftsf214ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5729 { 5730 uint32 tie_t; 5731 tie_t = (val << 25) >> 25; 5732 insn[0] = (insn[0] & ~0x3f80) | (tie_t << 7); 5733 } 5734 5735 static unsigned 5736 Field_ftsf298ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5737 { 5738 unsigned tie_t = 0; 5739 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 5740 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5741 return tie_t; 5742 } 5743 5744 static void 5745 Field_ftsf298ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5746 { 5747 uint32 tie_t; 5748 tie_t = (val << 24) >> 24; 5749 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5750 tie_t = (val << 20) >> 28; 5751 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 5752 } 5753 5754 static unsigned 5755 Field_ftsf373ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5756 { 5757 unsigned tie_t = 0; 5758 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 5759 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 5760 return tie_t; 5761 } 5762 5763 static void 5764 Field_ftsf373ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5765 { 5766 uint32 tie_t; 5767 tie_t = (val << 31) >> 31; 5768 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 5769 tie_t = (val << 30) >> 31; 5770 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 5771 } 5772 5773 static unsigned 5774 Field_ftsf302ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5775 { 5776 unsigned tie_t = 0; 5777 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 5778 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5779 return tie_t; 5780 } 5781 5782 static void 5783 Field_ftsf302ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5784 { 5785 uint32 tie_t; 5786 tie_t = (val << 24) >> 24; 5787 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5788 tie_t = (val << 22) >> 30; 5789 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 5790 } 5791 5792 static unsigned 5793 Field_ftsf376ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5794 { 5795 unsigned tie_t = 0; 5796 tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); 5797 tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); 5798 return tie_t; 5799 } 5800 5801 static void 5802 Field_ftsf376ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5803 { 5804 uint32 tie_t; 5805 tie_t = (val << 29) >> 29; 5806 insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); 5807 tie_t = (val << 27) >> 30; 5808 insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); 5809 } 5810 5811 static unsigned 5812 Field_ftsf300ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5813 { 5814 unsigned tie_t = 0; 5815 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 5816 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5817 return tie_t; 5818 } 5819 5820 static void 5821 Field_ftsf300ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5822 { 5823 uint32 tie_t; 5824 tie_t = (val << 24) >> 24; 5825 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5826 tie_t = (val << 21) >> 29; 5827 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 5828 } 5829 5830 static unsigned 5831 Field_ftsf370ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5832 { 5833 unsigned tie_t = 0; 5834 tie_t = (tie_t << 2) | ((insn[0] << 10) >> 30); 5835 tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); 5836 return tie_t; 5837 } 5838 5839 static void 5840 Field_ftsf370ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5841 { 5842 uint32 tie_t; 5843 tie_t = (val << 30) >> 30; 5844 insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); 5845 tie_t = (val << 28) >> 30; 5846 insn[0] = (insn[0] & ~0x300000) | (tie_t << 20); 5847 } 5848 5849 static unsigned 5850 Field_ae_s20_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5851 { 5852 unsigned tie_t = 0; 5853 tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); 5854 return tie_t; 5855 } 5856 5857 static void 5858 Field_ae_s20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5859 { 5860 uint32 tie_t; 5861 tie_t = (val << 29) >> 29; 5862 insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); 5863 } 5864 5865 static unsigned 5866 Field_ftsf378ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5867 { 5868 unsigned tie_t = 0; 5869 tie_t = (tie_t << 5) | ((insn[0] << 8) >> 27); 5870 return tie_t; 5871 } 5872 5873 static void 5874 Field_ftsf378ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5875 { 5876 uint32 tie_t; 5877 tie_t = (val << 27) >> 27; 5878 insn[0] = (insn[0] & ~0xf80000) | (tie_t << 19); 5879 } 5880 5881 static unsigned 5882 Field_ftsf217ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5883 { 5884 unsigned tie_t = 0; 5885 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5886 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5887 return tie_t; 5888 } 5889 5890 static void 5891 Field_ftsf217ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5892 { 5893 uint32 tie_t; 5894 tie_t = (val << 24) >> 24; 5895 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5896 tie_t = (val << 23) >> 31; 5897 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5898 } 5899 5900 static unsigned 5901 Field_ftsf219ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5902 { 5903 unsigned tie_t = 0; 5904 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5905 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5906 return tie_t; 5907 } 5908 5909 static void 5910 Field_ftsf219ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5911 { 5912 uint32 tie_t; 5913 tie_t = (val << 24) >> 24; 5914 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5915 tie_t = (val << 23) >> 31; 5916 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5917 } 5918 5919 static unsigned 5920 Field_ftsf220ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5921 { 5922 unsigned tie_t = 0; 5923 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5924 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5925 return tie_t; 5926 } 5927 5928 static void 5929 Field_ftsf220ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5930 { 5931 uint32 tie_t; 5932 tie_t = (val << 24) >> 24; 5933 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5934 tie_t = (val << 23) >> 31; 5935 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5936 } 5937 5938 static unsigned 5939 Field_ftsf221ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5940 { 5941 unsigned tie_t = 0; 5942 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5943 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5944 return tie_t; 5945 } 5946 5947 static void 5948 Field_ftsf221ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5949 { 5950 uint32 tie_t; 5951 tie_t = (val << 24) >> 24; 5952 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5953 tie_t = (val << 23) >> 31; 5954 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5955 } 5956 5957 static unsigned 5958 Field_ftsf227ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5959 { 5960 unsigned tie_t = 0; 5961 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5962 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5963 return tie_t; 5964 } 5965 5966 static void 5967 Field_ftsf227ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5968 { 5969 uint32 tie_t; 5970 tie_t = (val << 24) >> 24; 5971 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5972 tie_t = (val << 23) >> 31; 5973 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5974 } 5975 5976 static unsigned 5977 Field_ftsf228ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5978 { 5979 unsigned tie_t = 0; 5980 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 5981 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 5982 return tie_t; 5983 } 5984 5985 static void 5986 Field_ftsf228ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 5987 { 5988 uint32 tie_t; 5989 tie_t = (val << 24) >> 24; 5990 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 5991 tie_t = (val << 23) >> 31; 5992 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 5993 } 5994 5995 static unsigned 5996 Field_ftsf229ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 5997 { 5998 unsigned tie_t = 0; 5999 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6000 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6001 return tie_t; 6002 } 6003 6004 static void 6005 Field_ftsf229ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6006 { 6007 uint32 tie_t; 6008 tie_t = (val << 24) >> 24; 6009 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6010 tie_t = (val << 23) >> 31; 6011 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6012 } 6013 6014 static unsigned 6015 Field_ftsf231ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6016 { 6017 unsigned tie_t = 0; 6018 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6019 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6020 return tie_t; 6021 } 6022 6023 static void 6024 Field_ftsf231ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6025 { 6026 uint32 tie_t; 6027 tie_t = (val << 24) >> 24; 6028 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6029 tie_t = (val << 23) >> 31; 6030 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6031 } 6032 6033 static unsigned 6034 Field_ftsf232ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6035 { 6036 unsigned tie_t = 0; 6037 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6038 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6039 return tie_t; 6040 } 6041 6042 static void 6043 Field_ftsf232ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6044 { 6045 uint32 tie_t; 6046 tie_t = (val << 24) >> 24; 6047 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6048 tie_t = (val << 23) >> 31; 6049 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6050 } 6051 6052 static unsigned 6053 Field_ftsf234ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6054 { 6055 unsigned tie_t = 0; 6056 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6057 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6058 return tie_t; 6059 } 6060 6061 static void 6062 Field_ftsf234ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6063 { 6064 uint32 tie_t; 6065 tie_t = (val << 24) >> 24; 6066 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6067 tie_t = (val << 23) >> 31; 6068 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6069 } 6070 6071 static unsigned 6072 Field_ftsf238ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6073 { 6074 unsigned tie_t = 0; 6075 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6076 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6077 return tie_t; 6078 } 6079 6080 static void 6081 Field_ftsf238ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6082 { 6083 uint32 tie_t; 6084 tie_t = (val << 24) >> 24; 6085 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6086 tie_t = (val << 23) >> 31; 6087 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6088 } 6089 6090 static unsigned 6091 Field_ftsf233ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6092 { 6093 unsigned tie_t = 0; 6094 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6095 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6096 return tie_t; 6097 } 6098 6099 static void 6100 Field_ftsf233ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6101 { 6102 uint32 tie_t; 6103 tie_t = (val << 24) >> 24; 6104 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6105 tie_t = (val << 23) >> 31; 6106 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6107 } 6108 6109 static unsigned 6110 Field_ftsf223ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6111 { 6112 unsigned tie_t = 0; 6113 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6114 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6115 return tie_t; 6116 } 6117 6118 static void 6119 Field_ftsf223ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6120 { 6121 uint32 tie_t; 6122 tie_t = (val << 24) >> 24; 6123 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6124 tie_t = (val << 23) >> 31; 6125 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6126 } 6127 6128 static unsigned 6129 Field_ftsf224ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6130 { 6131 unsigned tie_t = 0; 6132 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6133 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6134 return tie_t; 6135 } 6136 6137 static void 6138 Field_ftsf224ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6139 { 6140 uint32 tie_t; 6141 tie_t = (val << 24) >> 24; 6142 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6143 tie_t = (val << 23) >> 31; 6144 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6145 } 6146 6147 static unsigned 6148 Field_ftsf226ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6149 { 6150 unsigned tie_t = 0; 6151 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6152 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6153 return tie_t; 6154 } 6155 6156 static void 6157 Field_ftsf226ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6158 { 6159 uint32 tie_t; 6160 tie_t = (val << 24) >> 24; 6161 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6162 tie_t = (val << 23) >> 31; 6163 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6164 } 6165 6166 static unsigned 6167 Field_ftsf225ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6168 { 6169 unsigned tie_t = 0; 6170 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6171 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6172 return tie_t; 6173 } 6174 6175 static void 6176 Field_ftsf225ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6177 { 6178 uint32 tie_t; 6179 tie_t = (val << 24) >> 24; 6180 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6181 tie_t = (val << 23) >> 31; 6182 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6183 } 6184 6185 static unsigned 6186 Field_ftsf240ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6187 { 6188 unsigned tie_t = 0; 6189 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6190 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6191 return tie_t; 6192 } 6193 6194 static void 6195 Field_ftsf240ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6196 { 6197 uint32 tie_t; 6198 tie_t = (val << 24) >> 24; 6199 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6200 tie_t = (val << 23) >> 31; 6201 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6202 } 6203 6204 static unsigned 6205 Field_ftsf242ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6206 { 6207 unsigned tie_t = 0; 6208 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6209 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6210 return tie_t; 6211 } 6212 6213 static void 6214 Field_ftsf242ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6215 { 6216 uint32 tie_t; 6217 tie_t = (val << 24) >> 24; 6218 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6219 tie_t = (val << 23) >> 31; 6220 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6221 } 6222 6223 static unsigned 6224 Field_ftsf241ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6225 { 6226 unsigned tie_t = 0; 6227 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6228 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6229 return tie_t; 6230 } 6231 6232 static void 6233 Field_ftsf241ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6234 { 6235 uint32 tie_t; 6236 tie_t = (val << 24) >> 24; 6237 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6238 tie_t = (val << 23) >> 31; 6239 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6240 } 6241 6242 static unsigned 6243 Field_ftsf243ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6244 { 6245 unsigned tie_t = 0; 6246 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6247 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6248 return tie_t; 6249 } 6250 6251 static void 6252 Field_ftsf243ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6253 { 6254 uint32 tie_t; 6255 tie_t = (val << 24) >> 24; 6256 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6257 tie_t = (val << 23) >> 31; 6258 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6259 } 6260 6261 static unsigned 6262 Field_ftsf235ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6263 { 6264 unsigned tie_t = 0; 6265 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6266 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6267 return tie_t; 6268 } 6269 6270 static void 6271 Field_ftsf235ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6272 { 6273 uint32 tie_t; 6274 tie_t = (val << 24) >> 24; 6275 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6276 tie_t = (val << 23) >> 31; 6277 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6278 } 6279 6280 static unsigned 6281 Field_ftsf236ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6282 { 6283 unsigned tie_t = 0; 6284 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6285 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6286 return tie_t; 6287 } 6288 6289 static void 6290 Field_ftsf236ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6291 { 6292 uint32 tie_t; 6293 tie_t = (val << 24) >> 24; 6294 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6295 tie_t = (val << 23) >> 31; 6296 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6297 } 6298 6299 static unsigned 6300 Field_ftsf237ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6301 { 6302 unsigned tie_t = 0; 6303 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6304 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6305 return tie_t; 6306 } 6307 6308 static void 6309 Field_ftsf237ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6310 { 6311 uint32 tie_t; 6312 tie_t = (val << 24) >> 24; 6313 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6314 tie_t = (val << 23) >> 31; 6315 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6316 } 6317 6318 static unsigned 6319 Field_ftsf239ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6320 { 6321 unsigned tie_t = 0; 6322 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6323 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6324 return tie_t; 6325 } 6326 6327 static void 6328 Field_ftsf239ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6329 { 6330 uint32 tie_t; 6331 tie_t = (val << 24) >> 24; 6332 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6333 tie_t = (val << 23) >> 31; 6334 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6335 } 6336 6337 static unsigned 6338 Field_ftsf260ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6339 { 6340 unsigned tie_t = 0; 6341 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6342 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6343 return tie_t; 6344 } 6345 6346 static void 6347 Field_ftsf260ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6348 { 6349 uint32 tie_t; 6350 tie_t = (val << 24) >> 24; 6351 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6352 tie_t = (val << 23) >> 31; 6353 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6354 } 6355 6356 static unsigned 6357 Field_ftsf295ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6358 { 6359 unsigned tie_t = 0; 6360 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6361 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6362 return tie_t; 6363 } 6364 6365 static void 6366 Field_ftsf295ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6367 { 6368 uint32 tie_t; 6369 tie_t = (val << 24) >> 24; 6370 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6371 tie_t = (val << 23) >> 31; 6372 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6373 } 6374 6375 static unsigned 6376 Field_ftsf247ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6377 { 6378 unsigned tie_t = 0; 6379 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6380 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6381 return tie_t; 6382 } 6383 6384 static void 6385 Field_ftsf247ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6386 { 6387 uint32 tie_t; 6388 tie_t = (val << 24) >> 24; 6389 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6390 tie_t = (val << 23) >> 31; 6391 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6392 } 6393 6394 static unsigned 6395 Field_ftsf249ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6396 { 6397 unsigned tie_t = 0; 6398 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6399 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6400 return tie_t; 6401 } 6402 6403 static void 6404 Field_ftsf249ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6405 { 6406 uint32 tie_t; 6407 tie_t = (val << 24) >> 24; 6408 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6409 tie_t = (val << 23) >> 31; 6410 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6411 } 6412 6413 static unsigned 6414 Field_ftsf268ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6415 { 6416 unsigned tie_t = 0; 6417 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6418 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6419 return tie_t; 6420 } 6421 6422 static void 6423 Field_ftsf268ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6424 { 6425 uint32 tie_t; 6426 tie_t = (val << 24) >> 24; 6427 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6428 tie_t = (val << 23) >> 31; 6429 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6430 } 6431 6432 static unsigned 6433 Field_ftsf263ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6434 { 6435 unsigned tie_t = 0; 6436 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6437 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6438 return tie_t; 6439 } 6440 6441 static void 6442 Field_ftsf263ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6443 { 6444 uint32 tie_t; 6445 tie_t = (val << 24) >> 24; 6446 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6447 tie_t = (val << 23) >> 31; 6448 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6449 } 6450 6451 static unsigned 6452 Field_ftsf265ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6453 { 6454 unsigned tie_t = 0; 6455 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6456 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6457 return tie_t; 6458 } 6459 6460 static void 6461 Field_ftsf265ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6462 { 6463 uint32 tie_t; 6464 tie_t = (val << 24) >> 24; 6465 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6466 tie_t = (val << 23) >> 31; 6467 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6468 } 6469 6470 static unsigned 6471 Field_ftsf266ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6472 { 6473 unsigned tie_t = 0; 6474 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6475 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6476 return tie_t; 6477 } 6478 6479 static void 6480 Field_ftsf266ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6481 { 6482 uint32 tie_t; 6483 tie_t = (val << 24) >> 24; 6484 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6485 tie_t = (val << 23) >> 31; 6486 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6487 } 6488 6489 static unsigned 6490 Field_ftsf259ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6491 { 6492 unsigned tie_t = 0; 6493 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6494 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6495 return tie_t; 6496 } 6497 6498 static void 6499 Field_ftsf259ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6500 { 6501 uint32 tie_t; 6502 tie_t = (val << 24) >> 24; 6503 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6504 tie_t = (val << 23) >> 31; 6505 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6506 } 6507 6508 static unsigned 6509 Field_ftsf261ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6510 { 6511 unsigned tie_t = 0; 6512 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6513 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6514 return tie_t; 6515 } 6516 6517 static void 6518 Field_ftsf261ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6519 { 6520 uint32 tie_t; 6521 tie_t = (val << 24) >> 24; 6522 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6523 tie_t = (val << 23) >> 31; 6524 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6525 } 6526 6527 static unsigned 6528 Field_ftsf262ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6529 { 6530 unsigned tie_t = 0; 6531 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6532 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6533 return tie_t; 6534 } 6535 6536 static void 6537 Field_ftsf262ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6538 { 6539 uint32 tie_t; 6540 tie_t = (val << 24) >> 24; 6541 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6542 tie_t = (val << 23) >> 31; 6543 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6544 } 6545 6546 static unsigned 6547 Field_ftsf264ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6548 { 6549 unsigned tie_t = 0; 6550 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6551 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6552 return tie_t; 6553 } 6554 6555 static void 6556 Field_ftsf264ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6557 { 6558 uint32 tie_t; 6559 tie_t = (val << 24) >> 24; 6560 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6561 tie_t = (val << 23) >> 31; 6562 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6563 } 6564 6565 static unsigned 6566 Field_ftsf245ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6567 { 6568 unsigned tie_t = 0; 6569 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6570 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6571 return tie_t; 6572 } 6573 6574 static void 6575 Field_ftsf245ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6576 { 6577 uint32 tie_t; 6578 tie_t = (val << 24) >> 24; 6579 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6580 tie_t = (val << 23) >> 31; 6581 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6582 } 6583 6584 static unsigned 6585 Field_ftsf246ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6586 { 6587 unsigned tie_t = 0; 6588 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6589 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6590 return tie_t; 6591 } 6592 6593 static void 6594 Field_ftsf246ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6595 { 6596 uint32 tie_t; 6597 tie_t = (val << 24) >> 24; 6598 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6599 tie_t = (val << 23) >> 31; 6600 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6601 } 6602 6603 static unsigned 6604 Field_ftsf248ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6605 { 6606 unsigned tie_t = 0; 6607 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6608 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6609 return tie_t; 6610 } 6611 6612 static void 6613 Field_ftsf248ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6614 { 6615 uint32 tie_t; 6616 tie_t = (val << 24) >> 24; 6617 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6618 tie_t = (val << 23) >> 31; 6619 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6620 } 6621 6622 static unsigned 6623 Field_ftsf252ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6624 { 6625 unsigned tie_t = 0; 6626 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6627 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6628 return tie_t; 6629 } 6630 6631 static void 6632 Field_ftsf252ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6633 { 6634 uint32 tie_t; 6635 tie_t = (val << 24) >> 24; 6636 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6637 tie_t = (val << 23) >> 31; 6638 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6639 } 6640 6641 static unsigned 6642 Field_ftsf256ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6643 { 6644 unsigned tie_t = 0; 6645 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6646 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6647 return tie_t; 6648 } 6649 6650 static void 6651 Field_ftsf256ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6652 { 6653 uint32 tie_t; 6654 tie_t = (val << 24) >> 24; 6655 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6656 tie_t = (val << 23) >> 31; 6657 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6658 } 6659 6660 static unsigned 6661 Field_ftsf255ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6662 { 6663 unsigned tie_t = 0; 6664 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6665 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6666 return tie_t; 6667 } 6668 6669 static void 6670 Field_ftsf255ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6671 { 6672 uint32 tie_t; 6673 tie_t = (val << 24) >> 24; 6674 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6675 tie_t = (val << 23) >> 31; 6676 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6677 } 6678 6679 static unsigned 6680 Field_ftsf257ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6681 { 6682 unsigned tie_t = 0; 6683 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6684 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6685 return tie_t; 6686 } 6687 6688 static void 6689 Field_ftsf257ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6690 { 6691 uint32 tie_t; 6692 tie_t = (val << 24) >> 24; 6693 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6694 tie_t = (val << 23) >> 31; 6695 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6696 } 6697 6698 static unsigned 6699 Field_ftsf258ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6700 { 6701 unsigned tie_t = 0; 6702 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6703 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6704 return tie_t; 6705 } 6706 6707 static void 6708 Field_ftsf258ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6709 { 6710 uint32 tie_t; 6711 tie_t = (val << 24) >> 24; 6712 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6713 tie_t = (val << 23) >> 31; 6714 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6715 } 6716 6717 static unsigned 6718 Field_ftsf250ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6719 { 6720 unsigned tie_t = 0; 6721 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6722 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6723 return tie_t; 6724 } 6725 6726 static void 6727 Field_ftsf250ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6728 { 6729 uint32 tie_t; 6730 tie_t = (val << 24) >> 24; 6731 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6732 tie_t = (val << 23) >> 31; 6733 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6734 } 6735 6736 static unsigned 6737 Field_ftsf251ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6738 { 6739 unsigned tie_t = 0; 6740 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6741 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6742 return tie_t; 6743 } 6744 6745 static void 6746 Field_ftsf251ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6747 { 6748 uint32 tie_t; 6749 tie_t = (val << 24) >> 24; 6750 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6751 tie_t = (val << 23) >> 31; 6752 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6753 } 6754 6755 static unsigned 6756 Field_ftsf253ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6757 { 6758 unsigned tie_t = 0; 6759 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6760 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6761 return tie_t; 6762 } 6763 6764 static void 6765 Field_ftsf253ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6766 { 6767 uint32 tie_t; 6768 tie_t = (val << 24) >> 24; 6769 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6770 tie_t = (val << 23) >> 31; 6771 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6772 } 6773 6774 static unsigned 6775 Field_ftsf254ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6776 { 6777 unsigned tie_t = 0; 6778 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 6779 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6780 return tie_t; 6781 } 6782 6783 static void 6784 Field_ftsf254ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6785 { 6786 uint32 tie_t; 6787 tie_t = (val << 24) >> 24; 6788 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6789 tie_t = (val << 23) >> 31; 6790 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 6791 } 6792 6793 static unsigned 6794 Field_ftsf305ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6795 { 6796 unsigned tie_t = 0; 6797 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6798 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6799 return tie_t; 6800 } 6801 6802 static void 6803 Field_ftsf305ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6804 { 6805 uint32 tie_t; 6806 tie_t = (val << 24) >> 24; 6807 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6808 tie_t = (val << 22) >> 30; 6809 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6810 } 6811 6812 static unsigned 6813 Field_ftsf306ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6814 { 6815 unsigned tie_t = 0; 6816 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6817 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6818 return tie_t; 6819 } 6820 6821 static void 6822 Field_ftsf306ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6823 { 6824 uint32 tie_t; 6825 tie_t = (val << 24) >> 24; 6826 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6827 tie_t = (val << 22) >> 30; 6828 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6829 } 6830 6831 static unsigned 6832 Field_ftsf307ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6833 { 6834 unsigned tie_t = 0; 6835 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6836 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6837 return tie_t; 6838 } 6839 6840 static void 6841 Field_ftsf307ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6842 { 6843 uint32 tie_t; 6844 tie_t = (val << 24) >> 24; 6845 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6846 tie_t = (val << 22) >> 30; 6847 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6848 } 6849 6850 static unsigned 6851 Field_ftsf310ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6852 { 6853 unsigned tie_t = 0; 6854 tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); 6855 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6856 return tie_t; 6857 } 6858 6859 static void 6860 Field_ftsf310ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6861 { 6862 uint32 tie_t; 6863 tie_t = (val << 24) >> 24; 6864 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6865 tie_t = (val << 23) >> 31; 6866 insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); 6867 } 6868 6869 static unsigned 6870 Field_ftsf304ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6871 { 6872 unsigned tie_t = 0; 6873 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6874 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6875 return tie_t; 6876 } 6877 6878 static void 6879 Field_ftsf304ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6880 { 6881 uint32 tie_t; 6882 tie_t = (val << 24) >> 24; 6883 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6884 tie_t = (val << 22) >> 30; 6885 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6886 } 6887 6888 static unsigned 6889 Field_ftsf308ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6890 { 6891 unsigned tie_t = 0; 6892 tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); 6893 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6894 return tie_t; 6895 } 6896 6897 static void 6898 Field_ftsf308ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6899 { 6900 uint32 tie_t; 6901 tie_t = (val << 24) >> 24; 6902 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6903 tie_t = (val << 23) >> 31; 6904 insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); 6905 } 6906 6907 static unsigned 6908 Field_ae_r10_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6909 { 6910 unsigned tie_t = 0; 6911 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6912 return tie_t; 6913 } 6914 6915 static void 6916 Field_ae_r10_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6917 { 6918 uint32 tie_t; 6919 tie_t = (val << 30) >> 30; 6920 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6921 } 6922 6923 static unsigned 6924 Field_ftsf329ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6925 { 6926 unsigned tie_t = 0; 6927 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); 6928 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 6929 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 6930 return tie_t; 6931 } 6932 6933 static void 6934 Field_ftsf329ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6935 { 6936 uint32 tie_t; 6937 tie_t = (val << 31) >> 31; 6938 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 6939 tie_t = (val << 30) >> 31; 6940 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 6941 tie_t = (val << 27) >> 29; 6942 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); 6943 } 6944 6945 static unsigned 6946 Field_ftsf379ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6947 { 6948 unsigned tie_t = 0; 6949 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 6950 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 6951 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); 6952 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 6953 return tie_t; 6954 } 6955 6956 static void 6957 Field_ftsf379ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6958 { 6959 uint32 tie_t; 6960 tie_t = (val << 31) >> 31; 6961 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 6962 tie_t = (val << 30) >> 31; 6963 insn[0] = (insn[0] & ~0x200) | (tie_t << 9); 6964 tie_t = (val << 29) >> 31; 6965 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 6966 tie_t = (val << 27) >> 30; 6967 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 6968 } 6969 6970 static unsigned 6971 Field_ftsf272ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6972 { 6973 unsigned tie_t = 0; 6974 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 6975 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6976 return tie_t; 6977 } 6978 6979 static void 6980 Field_ftsf272ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 6981 { 6982 uint32 tie_t; 6983 tie_t = (val << 24) >> 24; 6984 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 6985 tie_t = (val << 22) >> 30; 6986 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 6987 } 6988 6989 static unsigned 6990 Field_ftsf273ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 6991 { 6992 unsigned tie_t = 0; 6993 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 6994 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 6995 return tie_t; 6996 } 6997 6998 static void 6999 Field_ftsf273ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7000 { 7001 uint32 tie_t; 7002 tie_t = (val << 24) >> 24; 7003 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7004 tie_t = (val << 22) >> 30; 7005 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7006 } 7007 7008 static unsigned 7009 Field_ftsf274ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7010 { 7011 unsigned tie_t = 0; 7012 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7013 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7014 return tie_t; 7015 } 7016 7017 static void 7018 Field_ftsf274ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7019 { 7020 uint32 tie_t; 7021 tie_t = (val << 24) >> 24; 7022 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7023 tie_t = (val << 22) >> 30; 7024 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7025 } 7026 7027 static unsigned 7028 Field_ftsf276ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7029 { 7030 unsigned tie_t = 0; 7031 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7032 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7033 return tie_t; 7034 } 7035 7036 static void 7037 Field_ftsf276ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7038 { 7039 uint32 tie_t; 7040 tie_t = (val << 24) >> 24; 7041 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7042 tie_t = (val << 22) >> 30; 7043 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7044 } 7045 7046 static unsigned 7047 Field_ftsf269ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7048 { 7049 unsigned tie_t = 0; 7050 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7051 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7052 return tie_t; 7053 } 7054 7055 static void 7056 Field_ftsf269ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7057 { 7058 uint32 tie_t; 7059 tie_t = (val << 24) >> 24; 7060 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7061 tie_t = (val << 22) >> 30; 7062 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7063 } 7064 7065 static unsigned 7066 Field_ftsf271ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7067 { 7068 unsigned tie_t = 0; 7069 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7070 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7071 return tie_t; 7072 } 7073 7074 static void 7075 Field_ftsf271ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7076 { 7077 uint32 tie_t; 7078 tie_t = (val << 24) >> 24; 7079 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7080 tie_t = (val << 22) >> 30; 7081 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7082 } 7083 7084 static unsigned 7085 Field_ftsf275ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7086 { 7087 unsigned tie_t = 0; 7088 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7089 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7090 return tie_t; 7091 } 7092 7093 static void 7094 Field_ftsf275ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7095 { 7096 uint32 tie_t; 7097 tie_t = (val << 24) >> 24; 7098 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7099 tie_t = (val << 22) >> 30; 7100 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7101 } 7102 7103 static unsigned 7104 Field_ftsf270ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7105 { 7106 unsigned tie_t = 0; 7107 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7108 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7109 return tie_t; 7110 } 7111 7112 static void 7113 Field_ftsf270ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7114 { 7115 uint32 tie_t; 7116 tie_t = (val << 24) >> 24; 7117 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7118 tie_t = (val << 22) >> 30; 7119 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7120 } 7121 7122 static unsigned 7123 Field_ftsf296ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7124 { 7125 unsigned tie_t = 0; 7126 tie_t = (tie_t << 13) | ((insn[0] << 12) >> 19); 7127 return tie_t; 7128 } 7129 7130 static void 7131 Field_ftsf296ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7132 { 7133 uint32 tie_t; 7134 tie_t = (val << 19) >> 19; 7135 insn[0] = (insn[0] & ~0xfff80) | (tie_t << 7); 7136 } 7137 7138 static unsigned 7139 Field_ftsf315_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7140 { 7141 unsigned tie_t = 0; 7142 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7143 return tie_t; 7144 } 7145 7146 static void 7147 Field_ftsf315_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7148 { 7149 uint32 tie_t; 7150 tie_t = (val << 31) >> 31; 7151 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 7152 } 7153 7154 static unsigned 7155 Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7156 { 7157 unsigned tie_t = 0; 7158 tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); 7159 return tie_t; 7160 } 7161 7162 static void 7163 Field_combined2c0b5f72_fld52_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7164 { 7165 uint32 tie_t; 7166 tie_t = (val << 31) >> 31; 7167 insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); 7168 } 7169 7170 static unsigned 7171 Field_combined1e9fefee_fld96_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7172 { 7173 unsigned tie_t = 0; 7174 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 7175 return tie_t; 7176 } 7177 7178 static void 7179 Field_combined1e9fefee_fld96_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7180 { 7181 uint32 tie_t; 7182 tie_t = (val << 31) >> 31; 7183 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 7184 } 7185 7186 static unsigned 7187 Field_combined1e9fefee_fld98_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7188 { 7189 unsigned tie_t = 0; 7190 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 7191 return tie_t; 7192 } 7193 7194 static void 7195 Field_combined1e9fefee_fld98_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7196 { 7197 uint32 tie_t; 7198 tie_t = (val << 30) >> 30; 7199 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 7200 } 7201 7202 static unsigned 7203 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7204 { 7205 unsigned tie_t = 0; 7206 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 7207 return tie_t; 7208 } 7209 7210 static void 7211 Field_combined2c0b5f72_fld49_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7212 { 7213 uint32 tie_t; 7214 tie_t = (val << 31) >> 31; 7215 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 7216 } 7217 7218 static unsigned 7219 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7220 { 7221 unsigned tie_t = 0; 7222 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 7223 return tie_t; 7224 } 7225 7226 static void 7227 Field_combined2c0b5f72_fld39_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7228 { 7229 uint32 tie_t; 7230 tie_t = (val << 31) >> 31; 7231 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 7232 } 7233 7234 static unsigned 7235 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7236 { 7237 unsigned tie_t = 0; 7238 tie_t = (tie_t << 1) | ((insn[0] << 22) >> 31); 7239 return tie_t; 7240 } 7241 7242 static void 7243 Field_combined2c0b5f72_fld50_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7244 { 7245 uint32 tie_t; 7246 tie_t = (val << 31) >> 31; 7247 insn[0] = (insn[0] & ~0x200) | (tie_t << 9); 7248 } 7249 7250 static unsigned 7251 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7252 { 7253 unsigned tie_t = 0; 7254 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 7255 return tie_t; 7256 } 7257 7258 static void 7259 Field_combined2c0b5f72_fld40_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7260 { 7261 uint32 tie_t; 7262 tie_t = (val << 31) >> 31; 7263 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 7264 } 7265 7266 static unsigned 7267 Field_ftsf362_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7268 { 7269 unsigned tie_t = 0; 7270 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 7271 return tie_t; 7272 } 7273 7274 static void 7275 Field_ftsf362_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7276 { 7277 uint32 tie_t; 7278 tie_t = (val << 31) >> 31; 7279 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 7280 } 7281 7282 static unsigned 7283 Field_op0_s4_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7284 { 7285 unsigned tie_t = 0; 7286 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); 7287 return tie_t; 7288 } 7289 7290 static void 7291 Field_op0_s4_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7292 { 7293 uint32 tie_t; 7294 tie_t = (val << 25) >> 25; 7295 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); 7296 } 7297 7298 static unsigned 7299 Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7300 { 7301 unsigned tie_t = 0; 7302 tie_t = (tie_t << 2) | ((insn[0] << 15) >> 30); 7303 return tie_t; 7304 } 7305 7306 static void 7307 Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7308 { 7309 uint32 tie_t; 7310 tie_t = (val << 30) >> 30; 7311 insn[0] = (insn[0] & ~0x18000) | (tie_t << 15); 7312 } 7313 7314 static unsigned 7315 Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7316 { 7317 unsigned tie_t = 0; 7318 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 7319 return tie_t; 7320 } 7321 7322 static void 7323 Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7324 { 7325 uint32 tie_t; 7326 tie_t = (val << 30) >> 30; 7327 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 7328 } 7329 7330 static unsigned 7331 Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7332 { 7333 unsigned tie_t = 0; 7334 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 7335 return tie_t; 7336 } 7337 7338 static void 7339 Field_combined2c0b5f72_fld47_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7340 { 7341 uint32 tie_t; 7342 tie_t = (val << 31) >> 31; 7343 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 7344 } 7345 7346 static unsigned 7347 Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7348 { 7349 unsigned tie_t = 0; 7350 tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); 7351 return tie_t; 7352 } 7353 7354 static void 7355 Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7356 { 7357 uint32 tie_t; 7358 tie_t = (val << 29) >> 29; 7359 insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); 7360 } 7361 7362 static unsigned 7363 Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7364 { 7365 unsigned tie_t = 0; 7366 tie_t = (tie_t << 3) | ((insn[0] << 14) >> 29); 7367 return tie_t; 7368 } 7369 7370 static void 7371 Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7372 { 7373 uint32 tie_t; 7374 tie_t = (val << 29) >> 29; 7375 insn[0] = (insn[0] & ~0x38000) | (tie_t << 15); 7376 } 7377 7378 static unsigned 7379 Field_ftsf244ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7380 { 7381 unsigned tie_t = 0; 7382 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7383 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7384 return tie_t; 7385 } 7386 7387 static void 7388 Field_ftsf244ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7389 { 7390 uint32 tie_t; 7391 tie_t = (val << 24) >> 24; 7392 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7393 tie_t = (val << 23) >> 31; 7394 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7395 } 7396 7397 static unsigned 7398 Field_ftsf267ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7399 { 7400 unsigned tie_t = 0; 7401 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7402 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7403 return tie_t; 7404 } 7405 7406 static void 7407 Field_ftsf267ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7408 { 7409 uint32 tie_t; 7410 tie_t = (val << 24) >> 24; 7411 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7412 tie_t = (val << 23) >> 31; 7413 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7414 } 7415 7416 static unsigned 7417 Field_ftsf290ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7418 { 7419 unsigned tie_t = 0; 7420 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7421 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7422 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7423 return tie_t; 7424 } 7425 7426 static void 7427 Field_ftsf290ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7428 { 7429 uint32 tie_t; 7430 tie_t = (val << 24) >> 24; 7431 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7432 tie_t = (val << 23) >> 31; 7433 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7434 tie_t = (val << 19) >> 28; 7435 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7436 } 7437 7438 static unsigned 7439 Field_ftsf289ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7440 { 7441 unsigned tie_t = 0; 7442 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7443 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7444 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7445 return tie_t; 7446 } 7447 7448 static void 7449 Field_ftsf289ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7450 { 7451 uint32 tie_t; 7452 tie_t = (val << 24) >> 24; 7453 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7454 tie_t = (val << 23) >> 31; 7455 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7456 tie_t = (val << 19) >> 28; 7457 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7458 } 7459 7460 static unsigned 7461 Field_ftsf230ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7462 { 7463 unsigned tie_t = 0; 7464 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7465 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7466 return tie_t; 7467 } 7468 7469 static void 7470 Field_ftsf230ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7471 { 7472 uint32 tie_t; 7473 tie_t = (val << 24) >> 24; 7474 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7475 tie_t = (val << 23) >> 31; 7476 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7477 } 7478 7479 static unsigned 7480 Field_ftsf222ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7481 { 7482 unsigned tie_t = 0; 7483 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7484 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7485 return tie_t; 7486 } 7487 7488 static void 7489 Field_ftsf222ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7490 { 7491 uint32 tie_t; 7492 tie_t = (val << 24) >> 24; 7493 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7494 tie_t = (val << 23) >> 31; 7495 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7496 } 7497 7498 static unsigned 7499 Field_ftsf218ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7500 { 7501 unsigned tie_t = 0; 7502 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7503 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7504 return tie_t; 7505 } 7506 7507 static void 7508 Field_ftsf218ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7509 { 7510 uint32 tie_t; 7511 tie_t = (val << 24) >> 24; 7512 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7513 tie_t = (val << 23) >> 31; 7514 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7515 } 7516 7517 static unsigned 7518 Field_ftsf215ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7519 { 7520 unsigned tie_t = 0; 7521 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7522 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7523 return tie_t; 7524 } 7525 7526 static void 7527 Field_ftsf215ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7528 { 7529 uint32 tie_t; 7530 tie_t = (val << 24) >> 24; 7531 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7532 tie_t = (val << 23) >> 31; 7533 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7534 } 7535 7536 static unsigned 7537 Field_ftsf314ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7538 { 7539 unsigned tie_t = 0; 7540 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7541 tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); 7542 return tie_t; 7543 } 7544 7545 static void 7546 Field_ftsf314ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7547 { 7548 uint32 tie_t; 7549 tie_t = (val << 20) >> 20; 7550 insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); 7551 tie_t = (val << 19) >> 31; 7552 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 7553 } 7554 7555 static unsigned 7556 Field_ftsf323ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7557 { 7558 unsigned tie_t = 0; 7559 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7560 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7561 return tie_t; 7562 } 7563 7564 static void 7565 Field_ftsf323ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7566 { 7567 uint32 tie_t; 7568 tie_t = (val << 24) >> 24; 7569 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7570 tie_t = (val << 20) >> 28; 7571 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7572 } 7573 7574 static unsigned 7575 Field_ftsf322ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7576 { 7577 unsigned tie_t = 0; 7578 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7579 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7580 return tie_t; 7581 } 7582 7583 static void 7584 Field_ftsf322ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7585 { 7586 uint32 tie_t; 7587 tie_t = (val << 24) >> 24; 7588 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7589 tie_t = (val << 20) >> 28; 7590 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7591 } 7592 7593 static unsigned 7594 Field_ftsf311ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7595 { 7596 unsigned tie_t = 0; 7597 tie_t = (tie_t << 1) | ((insn[0] << 10) >> 31); 7598 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 7599 return tie_t; 7600 } 7601 7602 static void 7603 Field_ftsf311ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7604 { 7605 uint32 tie_t; 7606 tie_t = (val << 25) >> 25; 7607 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 7608 tie_t = (val << 24) >> 31; 7609 insn[0] = (insn[0] & ~0x200000) | (tie_t << 21); 7610 } 7611 7612 static unsigned 7613 Field_ftsf386ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7614 { 7615 unsigned tie_t = 0; 7616 tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); 7617 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 7618 return tie_t; 7619 } 7620 7621 static void 7622 Field_ftsf386ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7623 { 7624 uint32 tie_t; 7625 tie_t = (val << 31) >> 31; 7626 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 7627 tie_t = (val << 26) >> 27; 7628 insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); 7629 } 7630 7631 static unsigned 7632 Field_ftsf278ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7633 { 7634 unsigned tie_t = 0; 7635 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7636 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 7637 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7638 return tie_t; 7639 } 7640 7641 static void 7642 Field_ftsf278ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7643 { 7644 uint32 tie_t; 7645 tie_t = (val << 24) >> 24; 7646 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7647 tie_t = (val << 22) >> 30; 7648 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 7649 tie_t = (val << 18) >> 28; 7650 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7651 } 7652 7653 static unsigned 7654 Field_ftsf292ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7655 { 7656 unsigned tie_t = 0; 7657 tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); 7658 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7659 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 7660 return tie_t; 7661 } 7662 7663 static void 7664 Field_ftsf292ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7665 { 7666 uint32 tie_t; 7667 tie_t = (val << 25) >> 25; 7668 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 7669 tie_t = (val << 24) >> 31; 7670 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7671 tie_t = (val << 21) >> 29; 7672 insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); 7673 } 7674 7675 static unsigned 7676 Field_ftsf382ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7677 { 7678 unsigned tie_t = 0; 7679 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7680 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 7681 return tie_t; 7682 } 7683 7684 static void 7685 Field_ftsf382ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7686 { 7687 uint32 tie_t; 7688 tie_t = (val << 31) >> 31; 7689 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 7690 tie_t = (val << 30) >> 31; 7691 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 7692 } 7693 7694 static unsigned 7695 Field_ftsf291ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7696 { 7697 unsigned tie_t = 0; 7698 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7699 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7700 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 7701 return tie_t; 7702 } 7703 7704 static void 7705 Field_ftsf291ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7706 { 7707 uint32 tie_t; 7708 tie_t = (val << 25) >> 25; 7709 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 7710 tie_t = (val << 24) >> 31; 7711 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7712 tie_t = (val << 20) >> 28; 7713 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7714 } 7715 7716 static unsigned 7717 Field_ftsf294ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7718 { 7719 unsigned tie_t = 0; 7720 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); 7721 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7722 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 7723 return tie_t; 7724 } 7725 7726 static void 7727 Field_ftsf294ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7728 { 7729 uint32 tie_t; 7730 tie_t = (val << 25) >> 25; 7731 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 7732 tie_t = (val << 24) >> 31; 7733 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7734 tie_t = (val << 23) >> 31; 7735 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); 7736 } 7737 7738 static unsigned 7739 Field_ftsf383ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7740 { 7741 unsigned tie_t = 0; 7742 tie_t = (tie_t << 3) | ((insn[0] << 6) >> 29); 7743 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 7744 return tie_t; 7745 } 7746 7747 static void 7748 Field_ftsf383ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7749 { 7750 uint32 tie_t; 7751 tie_t = (val << 31) >> 31; 7752 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 7753 tie_t = (val << 28) >> 29; 7754 insn[0] = (insn[0] & ~0x3800000) | (tie_t << 23); 7755 } 7756 7757 static unsigned 7758 Field_ftsf293ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7759 { 7760 unsigned tie_t = 0; 7761 tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); 7762 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 7763 tie_t = (tie_t << 7) | ((insn[0] << 17) >> 25); 7764 return tie_t; 7765 } 7766 7767 static void 7768 Field_ftsf293ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7769 { 7770 uint32 tie_t; 7771 tie_t = (val << 25) >> 25; 7772 insn[0] = (insn[0] & ~0x7f00) | (tie_t << 8); 7773 tie_t = (val << 24) >> 31; 7774 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 7775 tie_t = (val << 22) >> 30; 7776 insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); 7777 } 7778 7779 static unsigned 7780 Field_ftsf384ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7781 { 7782 unsigned tie_t = 0; 7783 tie_t = (tie_t << 2) | ((insn[0] << 7) >> 30); 7784 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 7785 return tie_t; 7786 } 7787 7788 static void 7789 Field_ftsf384ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7790 { 7791 uint32 tie_t; 7792 tie_t = (val << 31) >> 31; 7793 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 7794 tie_t = (val << 29) >> 30; 7795 insn[0] = (insn[0] & ~0x1800000) | (tie_t << 23); 7796 } 7797 7798 static unsigned 7799 Field_ftsf312ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7800 { 7801 unsigned tie_t = 0; 7802 tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); 7803 return tie_t; 7804 } 7805 7806 static void 7807 Field_ftsf312ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7808 { 7809 uint32 tie_t; 7810 tie_t = (val << 22) >> 22; 7811 insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); 7812 } 7813 7814 static unsigned 7815 Field_ftsf320ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7816 { 7817 unsigned tie_t = 0; 7818 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 7819 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7820 return tie_t; 7821 } 7822 7823 static void 7824 Field_ftsf320ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7825 { 7826 uint32 tie_t; 7827 tie_t = (val << 24) >> 24; 7828 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7829 tie_t = (val << 23) >> 31; 7830 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 7831 } 7832 7833 static unsigned 7834 Field_ftsf387ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7835 { 7836 unsigned tie_t = 0; 7837 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7838 tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); 7839 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 7840 return tie_t; 7841 } 7842 7843 static void 7844 Field_ftsf387ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7845 { 7846 uint32 tie_t; 7847 tie_t = (val << 31) >> 31; 7848 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 7849 tie_t = (val << 29) >> 30; 7850 insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); 7851 tie_t = (val << 25) >> 28; 7852 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7853 } 7854 7855 static unsigned 7856 Field_ftsf319ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7857 { 7858 unsigned tie_t = 0; 7859 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7860 tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); 7861 return tie_t; 7862 } 7863 7864 static void 7865 Field_ftsf319ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7866 { 7867 uint32 tie_t; 7868 tie_t = (val << 22) >> 22; 7869 insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); 7870 tie_t = (val << 21) >> 31; 7871 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 7872 } 7873 7874 static unsigned 7875 Field_ftsf388ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7876 { 7877 unsigned tie_t = 0; 7878 tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); 7879 tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); 7880 return tie_t; 7881 } 7882 7883 static void 7884 Field_ftsf388ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7885 { 7886 uint32 tie_t; 7887 tie_t = (val << 30) >> 30; 7888 insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); 7889 tie_t = (val << 27) >> 29; 7890 insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); 7891 } 7892 7893 static unsigned 7894 Field_ftsf317ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7895 { 7896 unsigned tie_t = 0; 7897 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7898 tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); 7899 tie_t = (tie_t << 10) | ((insn[0] << 15) >> 22); 7900 return tie_t; 7901 } 7902 7903 static void 7904 Field_ftsf317ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7905 { 7906 uint32 tie_t; 7907 tie_t = (val << 22) >> 22; 7908 insn[0] = (insn[0] & ~0x1ff80) | (tie_t << 7); 7909 tie_t = (val << 21) >> 31; 7910 insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); 7911 tie_t = (val << 20) >> 31; 7912 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 7913 } 7914 7915 static unsigned 7916 Field_ftsf389ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7917 { 7918 unsigned tie_t = 0; 7919 tie_t = (tie_t << 3) | ((insn[0] << 5) >> 29); 7920 tie_t = (tie_t << 1) | ((insn[0] << 14) >> 31); 7921 return tie_t; 7922 } 7923 7924 static void 7925 Field_ftsf389ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7926 { 7927 uint32 tie_t; 7928 tie_t = (val << 31) >> 31; 7929 insn[0] = (insn[0] & ~0x20000) | (tie_t << 17); 7930 tie_t = (val << 28) >> 29; 7931 insn[0] = (insn[0] & ~0x7000000) | (tie_t << 24); 7932 } 7933 7934 static unsigned 7935 Field_ftsf324ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7936 { 7937 unsigned tie_t = 0; 7938 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7939 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7940 return tie_t; 7941 } 7942 7943 static void 7944 Field_ftsf324ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7945 { 7946 uint32 tie_t; 7947 tie_t = (val << 24) >> 24; 7948 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7949 tie_t = (val << 20) >> 28; 7950 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7951 } 7952 7953 static unsigned 7954 Field_ftsf325ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7955 { 7956 unsigned tie_t = 0; 7957 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 7958 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7959 return tie_t; 7960 } 7961 7962 static void 7963 Field_ftsf325ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7964 { 7965 uint32 tie_t; 7966 tie_t = (val << 24) >> 24; 7967 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7968 tie_t = (val << 20) >> 28; 7969 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 7970 } 7971 7972 static unsigned 7973 Field_ftsf328ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7974 { 7975 unsigned tie_t = 0; 7976 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); 7977 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 7978 return tie_t; 7979 } 7980 7981 static void 7982 Field_ftsf328ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 7983 { 7984 uint32 tie_t; 7985 tie_t = (val << 24) >> 24; 7986 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 7987 tie_t = (val << 23) >> 31; 7988 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); 7989 } 7990 7991 static unsigned 7992 Field_ftsf316ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 7993 { 7994 unsigned tie_t = 0; 7995 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 7996 tie_t = (tie_t << 12) | ((insn[0] << 13) >> 20); 7997 return tie_t; 7998 } 7999 8000 static void 8001 Field_ftsf316ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8002 { 8003 uint32 tie_t; 8004 tie_t = (val << 20) >> 20; 8005 insn[0] = (insn[0] & ~0x7ff80) | (tie_t << 7); 8006 tie_t = (val << 19) >> 31; 8007 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 8008 } 8009 8010 static unsigned 8011 Field_ftsf326ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8012 { 8013 unsigned tie_t = 0; 8014 tie_t = (tie_t << 2) | ((insn[0] << 5) >> 30); 8015 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 8016 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 8017 return tie_t; 8018 } 8019 8020 static void 8021 Field_ftsf326ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8022 { 8023 uint32 tie_t; 8024 tie_t = (val << 24) >> 24; 8025 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 8026 tie_t = (val << 23) >> 31; 8027 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 8028 tie_t = (val << 21) >> 30; 8029 insn[0] = (insn[0] & ~0x6000000) | (tie_t << 25); 8030 } 8031 8032 static unsigned 8033 Field_ftsf277ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8034 { 8035 unsigned tie_t = 0; 8036 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 8037 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 8038 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 8039 return tie_t; 8040 } 8041 8042 static void 8043 Field_ftsf277ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8044 { 8045 uint32 tie_t; 8046 tie_t = (val << 24) >> 24; 8047 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 8048 tie_t = (val << 22) >> 30; 8049 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 8050 tie_t = (val << 18) >> 28; 8051 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 8052 } 8053 8054 static unsigned 8055 Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8056 { 8057 unsigned tie_t = 0; 8058 tie_t = (tie_t << 1) | ((insn[0] << 6) >> 31); 8059 return tie_t; 8060 } 8061 8062 static void 8063 Field_combined2c0b5f72_fld123_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8064 { 8065 uint32 tie_t; 8066 tie_t = (val << 31) >> 31; 8067 insn[0] = (insn[0] & ~0x2000000) | (tie_t << 25); 8068 } 8069 8070 static unsigned 8071 Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8072 { 8073 unsigned tie_t = 0; 8074 tie_t = (tie_t << 1) | ((insn[0] << 5) >> 31); 8075 return tie_t; 8076 } 8077 8078 static void 8079 Field_combined2c0b5f72_fld121_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8080 { 8081 uint32 tie_t; 8082 tie_t = (val << 31) >> 31; 8083 insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26); 8084 } 8085 8086 static unsigned 8087 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8088 { 8089 unsigned tie_t = 0; 8090 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 8091 return tie_t; 8092 } 8093 8094 static void 8095 Field_combined2c0b5f72_fld28_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8096 { 8097 uint32 tie_t; 8098 tie_t = (val << 31) >> 31; 8099 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 8100 } 8101 8102 static unsigned 8103 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8104 { 8105 unsigned tie_t = 0; 8106 tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30); 8107 return tie_t; 8108 } 8109 8110 static void 8111 Field_combined2c0b5f72_fld127_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8112 { 8113 uint32 tie_t; 8114 tie_t = (val << 30) >> 30; 8115 insn[0] = (insn[0] & ~0x3000) | (tie_t << 12); 8116 } 8117 8118 static unsigned 8119 Field_op0_s4_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8120 { 8121 unsigned tie_t = 0; 8122 tie_t = (tie_t << 7) | ((insn[0] << 25) >> 25); 8123 return tie_t; 8124 } 8125 8126 static void 8127 Field_op0_s4_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8128 { 8129 uint32 tie_t; 8130 tie_t = (val << 25) >> 25; 8131 insn[0] = (insn[0] & ~0x7f) | (tie_t << 0); 8132 } 8133 8134 static unsigned 8135 Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8136 { 8137 unsigned tie_t = 0; 8138 tie_t = (tie_t << 8) | ((insn[0] << 17) >> 24); 8139 return tie_t; 8140 } 8141 8142 static void 8143 Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8144 { 8145 uint32 tie_t; 8146 tie_t = (val << 24) >> 24; 8147 insn[0] = (insn[0] & ~0x7f80) | (tie_t << 7); 8148 } 8149 8150 static unsigned 8151 Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8152 { 8153 unsigned tie_t = 0; 8154 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8155 return tie_t; 8156 } 8157 8158 static void 8159 Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8160 { 8161 uint32 tie_t; 8162 tie_t = (val << 31) >> 31; 8163 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8164 } 8165 8166 static unsigned 8167 Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8168 { 8169 unsigned tie_t = 0; 8170 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8171 return tie_t; 8172 } 8173 8174 static void 8175 Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8176 { 8177 uint32 tie_t; 8178 tie_t = (val << 31) >> 31; 8179 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8180 } 8181 8182 static unsigned 8183 Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8184 { 8185 unsigned tie_t = 0; 8186 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8187 return tie_t; 8188 } 8189 8190 static void 8191 Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8192 { 8193 uint32 tie_t; 8194 tie_t = (val << 31) >> 31; 8195 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8196 } 8197 8198 static unsigned 8199 Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8200 { 8201 unsigned tie_t = 0; 8202 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8203 return tie_t; 8204 } 8205 8206 static void 8207 Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8208 { 8209 uint32 tie_t; 8210 tie_t = (val << 31) >> 31; 8211 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8212 } 8213 8214 static unsigned 8215 Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8216 { 8217 unsigned tie_t = 0; 8218 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8219 return tie_t; 8220 } 8221 8222 static void 8223 Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8224 { 8225 uint32 tie_t; 8226 tie_t = (val << 31) >> 31; 8227 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8228 } 8229 8230 static unsigned 8231 Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8232 { 8233 unsigned tie_t = 0; 8234 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8235 return tie_t; 8236 } 8237 8238 static void 8239 Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8240 { 8241 uint32 tie_t; 8242 tie_t = (val << 31) >> 31; 8243 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8244 } 8245 8246 static unsigned 8247 Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8248 { 8249 unsigned tie_t = 0; 8250 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8251 return tie_t; 8252 } 8253 8254 static void 8255 Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8256 { 8257 uint32 tie_t; 8258 tie_t = (val << 31) >> 31; 8259 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8260 } 8261 8262 static unsigned 8263 Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8264 { 8265 unsigned tie_t = 0; 8266 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8267 return tie_t; 8268 } 8269 8270 static void 8271 Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8272 { 8273 uint32 tie_t; 8274 tie_t = (val << 31) >> 31; 8275 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8276 } 8277 8278 static unsigned 8279 Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8280 { 8281 unsigned tie_t = 0; 8282 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8283 return tie_t; 8284 } 8285 8286 static void 8287 Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8288 { 8289 uint32 tie_t; 8290 tie_t = (val << 31) >> 31; 8291 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8292 } 8293 8294 static unsigned 8295 Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8296 { 8297 unsigned tie_t = 0; 8298 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8299 return tie_t; 8300 } 8301 8302 static void 8303 Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8304 { 8305 uint32 tie_t; 8306 tie_t = (val << 31) >> 31; 8307 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8308 } 8309 8310 static unsigned 8311 Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8312 { 8313 unsigned tie_t = 0; 8314 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8315 return tie_t; 8316 } 8317 8318 static void 8319 Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8320 { 8321 uint32 tie_t; 8322 tie_t = (val << 31) >> 31; 8323 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8324 } 8325 8326 static unsigned 8327 Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8328 { 8329 unsigned tie_t = 0; 8330 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8331 return tie_t; 8332 } 8333 8334 static void 8335 Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8336 { 8337 uint32 tie_t; 8338 tie_t = (val << 31) >> 31; 8339 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8340 } 8341 8342 static unsigned 8343 Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8344 { 8345 unsigned tie_t = 0; 8346 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8347 return tie_t; 8348 } 8349 8350 static void 8351 Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8352 { 8353 uint32 tie_t; 8354 tie_t = (val << 31) >> 31; 8355 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8356 } 8357 8358 static unsigned 8359 Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8360 { 8361 unsigned tie_t = 0; 8362 tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31); 8363 return tie_t; 8364 } 8365 8366 static void 8367 Field_combined2c0b5f72_fld46_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8368 { 8369 uint32 tie_t; 8370 tie_t = (val << 31) >> 31; 8371 insn[0] = (insn[0] & ~0x100000) | (tie_t << 20); 8372 } 8373 8374 static unsigned 8375 Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8376 { 8377 unsigned tie_t = 0; 8378 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 8379 return tie_t; 8380 } 8381 8382 static void 8383 Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8384 { 8385 uint32 tie_t; 8386 tie_t = (val << 31) >> 31; 8387 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 8388 } 8389 8390 static unsigned 8391 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) 8392 { 8393 unsigned tie_t = 0; 8394 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 8395 return tie_t; 8396 } 8397 8398 static void 8399 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8400 { 8401 uint32 tie_t; 8402 tie_t = (val << 28) >> 28; 8403 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 8404 } 8405 8406 static unsigned 8407 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn) 8408 { 8409 unsigned tie_t = 0; 8410 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 8411 return tie_t; 8412 } 8413 8414 static void 8415 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8416 { 8417 uint32 tie_t; 8418 tie_t = (val << 31) >> 31; 8419 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 8420 } 8421 8422 static unsigned 8423 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn) 8424 { 8425 unsigned tie_t = 0; 8426 tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31); 8427 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 8428 return tie_t; 8429 } 8430 8431 static void 8432 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8433 { 8434 uint32 tie_t; 8435 tie_t = (val << 28) >> 28; 8436 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 8437 tie_t = (val << 27) >> 31; 8438 insn[0] = (insn[0] & ~0x100) | (tie_t << 8); 8439 } 8440 8441 static unsigned 8442 Field_bbi_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8443 { 8444 unsigned tie_t = 0; 8445 tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); 8446 return tie_t; 8447 } 8448 8449 static void 8450 Field_bbi_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8451 { 8452 uint32 tie_t; 8453 tie_t = (val << 27) >> 27; 8454 insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); 8455 } 8456 8457 static unsigned 8458 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn) 8459 { 8460 unsigned tie_t = 0; 8461 tie_t = (tie_t << 12) | ((insn[0] << 20) >> 20); 8462 return tie_t; 8463 } 8464 8465 static void 8466 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8467 { 8468 uint32 tie_t; 8469 tie_t = (val << 20) >> 20; 8470 insn[0] = (insn[0] & ~0xfff) | (tie_t << 0); 8471 } 8472 8473 static unsigned 8474 Field_imm12_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8475 { 8476 unsigned tie_t = 0; 8477 tie_t = (tie_t << 8) | ((insn[0] << 5) >> 24); 8478 tie_t = (tie_t << 4) | ((insn[0] << 17) >> 28); 8479 return tie_t; 8480 } 8481 8482 static void 8483 Field_imm12_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8484 { 8485 uint32 tie_t; 8486 tie_t = (val << 28) >> 28; 8487 insn[0] = (insn[0] & ~0x7800) | (tie_t << 11); 8488 tie_t = (val << 20) >> 24; 8489 insn[0] = (insn[0] & ~0x7f80000) | (tie_t << 19); 8490 } 8491 8492 static unsigned 8493 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn) 8494 { 8495 unsigned tie_t = 0; 8496 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 8497 return tie_t; 8498 } 8499 8500 static void 8501 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8502 { 8503 uint32 tie_t; 8504 tie_t = (val << 24) >> 24; 8505 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 8506 } 8507 8508 static unsigned 8509 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn) 8510 { 8511 unsigned tie_t = 0; 8512 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 8513 return tie_t; 8514 } 8515 8516 static void 8517 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8518 { 8519 uint32 tie_t; 8520 tie_t = (val << 28) >> 28; 8521 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 8522 } 8523 8524 static unsigned 8525 Field_s_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8526 { 8527 unsigned tie_t = 0; 8528 tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); 8529 return tie_t; 8530 } 8531 8532 static void 8533 Field_s_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8534 { 8535 uint32 tie_t; 8536 tie_t = (val << 28) >> 28; 8537 insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); 8538 } 8539 8540 static unsigned 8541 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn) 8542 { 8543 unsigned tie_t = 0; 8544 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 8545 tie_t = (tie_t << 8) | ((insn[0] << 24) >> 24); 8546 return tie_t; 8547 } 8548 8549 static void 8550 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8551 { 8552 uint32 tie_t; 8553 tie_t = (val << 24) >> 24; 8554 insn[0] = (insn[0] & ~0xff) | (tie_t << 0); 8555 tie_t = (val << 20) >> 28; 8556 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 8557 } 8558 8559 static unsigned 8560 Field_imm12b_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8561 { 8562 unsigned tie_t = 0; 8563 tie_t = (tie_t << 12) | ((insn[0] << 9) >> 20); 8564 return tie_t; 8565 } 8566 8567 static void 8568 Field_imm12b_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8569 { 8570 uint32 tie_t; 8571 tie_t = (val << 20) >> 20; 8572 insn[0] = (insn[0] & ~0x7ff800) | (tie_t << 11); 8573 } 8574 8575 static unsigned 8576 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn) 8577 { 8578 unsigned tie_t = 0; 8579 tie_t = (tie_t << 16) | ((insn[0] << 16) >> 16); 8580 return tie_t; 8581 } 8582 8583 static void 8584 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8585 { 8586 uint32 tie_t; 8587 tie_t = (val << 16) >> 16; 8588 insn[0] = (insn[0] & ~0xffff) | (tie_t << 0); 8589 } 8590 8591 static unsigned 8592 Field_imm16_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8593 { 8594 unsigned tie_t = 0; 8595 tie_t = (tie_t << 16) | ((insn[0] << 9) >> 16); 8596 return tie_t; 8597 } 8598 8599 static void 8600 Field_imm16_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8601 { 8602 uint32 tie_t; 8603 tie_t = (val << 16) >> 16; 8604 insn[0] = (insn[0] & ~0x7fff80) | (tie_t << 7); 8605 } 8606 8607 static unsigned 8608 Field_offset_Slot_inst_get (const xtensa_insnbuf insn) 8609 { 8610 unsigned tie_t = 0; 8611 tie_t = (tie_t << 18) | ((insn[0] << 14) >> 14); 8612 return tie_t; 8613 } 8614 8615 static void 8616 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8617 { 8618 uint32 tie_t; 8619 tie_t = (val << 14) >> 14; 8620 insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0); 8621 } 8622 8623 static unsigned 8624 Field_offset_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8625 { 8626 unsigned tie_t = 0; 8627 tie_t = (tie_t << 18) | ((insn[0] << 5) >> 14); 8628 return tie_t; 8629 } 8630 8631 static void 8632 Field_offset_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8633 { 8634 uint32 tie_t; 8635 tie_t = (val << 14) >> 14; 8636 insn[0] = (insn[0] & ~0x7fffe00) | (tie_t << 9); 8637 } 8638 8639 static unsigned 8640 Field_op2_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8641 { 8642 unsigned tie_t = 0; 8643 tie_t = (tie_t << 4) | ((insn[0] << 13) >> 28); 8644 return tie_t; 8645 } 8646 8647 static void 8648 Field_op2_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8649 { 8650 uint32 tie_t; 8651 tie_t = (val << 28) >> 28; 8652 insn[0] = (insn[0] & ~0x78000) | (tie_t << 15); 8653 } 8654 8655 static unsigned 8656 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn) 8657 { 8658 unsigned tie_t = 0; 8659 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 8660 return tie_t; 8661 } 8662 8663 static void 8664 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8665 { 8666 uint32 tie_t; 8667 tie_t = (val << 28) >> 28; 8668 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 8669 } 8670 8671 static unsigned 8672 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn) 8673 { 8674 unsigned tie_t = 0; 8675 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 8676 return tie_t; 8677 } 8678 8679 static void 8680 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8681 { 8682 uint32 tie_t; 8683 tie_t = (val << 31) >> 31; 8684 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 8685 } 8686 8687 static unsigned 8688 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn) 8689 { 8690 unsigned tie_t = 0; 8691 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 8692 return tie_t; 8693 } 8694 8695 static void 8696 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8697 { 8698 uint32 tie_t; 8699 tie_t = (val << 31) >> 31; 8700 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 8701 } 8702 8703 static unsigned 8704 Field_sae_Slot_inst_get (const xtensa_insnbuf insn) 8705 { 8706 unsigned tie_t = 0; 8707 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 8708 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 8709 return tie_t; 8710 } 8711 8712 static void 8713 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8714 { 8715 uint32 tie_t; 8716 tie_t = (val << 28) >> 28; 8717 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 8718 tie_t = (val << 27) >> 31; 8719 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 8720 } 8721 8722 static unsigned 8723 Field_sae_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8724 { 8725 unsigned tie_t = 0; 8726 tie_t = (tie_t << 5) | ((insn[0] << 17) >> 27); 8727 return tie_t; 8728 } 8729 8730 static void 8731 Field_sae_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8732 { 8733 uint32 tie_t; 8734 tie_t = (val << 27) >> 27; 8735 insn[0] = (insn[0] & ~0x7c00) | (tie_t << 10); 8736 } 8737 8738 static unsigned 8739 Field_sal_Slot_inst_get (const xtensa_insnbuf insn) 8740 { 8741 unsigned tie_t = 0; 8742 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 8743 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 8744 return tie_t; 8745 } 8746 8747 static void 8748 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8749 { 8750 uint32 tie_t; 8751 tie_t = (val << 28) >> 28; 8752 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 8753 tie_t = (val << 27) >> 31; 8754 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 8755 } 8756 8757 static unsigned 8758 Field_sal_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8759 { 8760 unsigned tie_t = 0; 8761 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 8762 tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31); 8763 return tie_t; 8764 } 8765 8766 static void 8767 Field_sal_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8768 { 8769 uint32 tie_t; 8770 tie_t = (val << 31) >> 31; 8771 insn[0] = (insn[0] & ~0x4000) | (tie_t << 14); 8772 tie_t = (val << 27) >> 28; 8773 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 8774 } 8775 8776 static unsigned 8777 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn) 8778 { 8779 unsigned tie_t = 0; 8780 tie_t = (tie_t << 1) | ((insn[0] << 31) >> 31); 8781 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 8782 return tie_t; 8783 } 8784 8785 static void 8786 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8787 { 8788 uint32 tie_t; 8789 tie_t = (val << 28) >> 28; 8790 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 8791 tie_t = (val << 27) >> 31; 8792 insn[0] = (insn[0] & ~0x1) | (tie_t << 0); 8793 } 8794 8795 static unsigned 8796 Field_sargt_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8797 { 8798 unsigned tie_t = 0; 8799 tie_t = (tie_t << 5) | ((insn[0] << 13) >> 27); 8800 return tie_t; 8801 } 8802 8803 static void 8804 Field_sargt_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8805 { 8806 uint32 tie_t; 8807 tie_t = (val << 27) >> 27; 8808 insn[0] = (insn[0] & ~0x7c000) | (tie_t << 14); 8809 } 8810 8811 static unsigned 8812 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn) 8813 { 8814 unsigned tie_t = 0; 8815 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 8816 return tie_t; 8817 } 8818 8819 static void 8820 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8821 { 8822 uint32 tie_t; 8823 tie_t = (val << 31) >> 31; 8824 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 8825 } 8826 8827 static unsigned 8828 Field_sas_Slot_inst_get (const xtensa_insnbuf insn) 8829 { 8830 unsigned tie_t = 0; 8831 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 8832 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 8833 return tie_t; 8834 } 8835 8836 static void 8837 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8838 { 8839 uint32 tie_t; 8840 tie_t = (val << 28) >> 28; 8841 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 8842 tie_t = (val << 27) >> 31; 8843 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 8844 } 8845 8846 static unsigned 8847 Field_sas_Slot_ae_slot0_get (const xtensa_insnbuf insn) 8848 { 8849 unsigned tie_t = 0; 8850 tie_t = (tie_t << 5) | ((insn[0] << 5) >> 27); 8851 return tie_t; 8852 } 8853 8854 static void 8855 Field_sas_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 8856 { 8857 uint32 tie_t; 8858 tie_t = (val << 27) >> 27; 8859 insn[0] = (insn[0] & ~0x7c00000) | (tie_t << 22); 8860 } 8861 8862 static unsigned 8863 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn) 8864 { 8865 unsigned tie_t = 0; 8866 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 8867 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 8868 return tie_t; 8869 } 8870 8871 static void 8872 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8873 { 8874 uint32 tie_t; 8875 tie_t = (val << 28) >> 28; 8876 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 8877 tie_t = (val << 24) >> 28; 8878 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 8879 } 8880 8881 static unsigned 8882 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn) 8883 { 8884 unsigned tie_t = 0; 8885 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 8886 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 8887 return tie_t; 8888 } 8889 8890 static void 8891 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 8892 { 8893 uint32 tie_t; 8894 tie_t = (val << 28) >> 28; 8895 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 8896 tie_t = (val << 24) >> 28; 8897 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 8898 } 8899 8900 static unsigned 8901 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn) 8902 { 8903 unsigned tie_t = 0; 8904 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 8905 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 8906 return tie_t; 8907 } 8908 8909 static void 8910 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8911 { 8912 uint32 tie_t; 8913 tie_t = (val << 28) >> 28; 8914 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 8915 tie_t = (val << 24) >> 28; 8916 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 8917 } 8918 8919 static unsigned 8920 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn) 8921 { 8922 unsigned tie_t = 0; 8923 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 8924 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 8925 return tie_t; 8926 } 8927 8928 static void 8929 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 8930 { 8931 uint32 tie_t; 8932 tie_t = (val << 28) >> 28; 8933 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 8934 tie_t = (val << 24) >> 28; 8935 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 8936 } 8937 8938 static unsigned 8939 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn) 8940 { 8941 unsigned tie_t = 0; 8942 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 8943 return tie_t; 8944 } 8945 8946 static void 8947 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8948 { 8949 uint32 tie_t; 8950 tie_t = (val << 28) >> 28; 8951 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 8952 } 8953 8954 static unsigned 8955 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn) 8956 { 8957 unsigned tie_t = 0; 8958 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 8959 return tie_t; 8960 } 8961 8962 static void 8963 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 8964 { 8965 uint32 tie_t; 8966 tie_t = (val << 28) >> 28; 8967 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 8968 } 8969 8970 static unsigned 8971 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn) 8972 { 8973 unsigned tie_t = 0; 8974 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 8975 return tie_t; 8976 } 8977 8978 static void 8979 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 8980 { 8981 uint32 tie_t; 8982 tie_t = (val << 28) >> 28; 8983 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 8984 } 8985 8986 static unsigned 8987 Field_mn_Slot_inst_get (const xtensa_insnbuf insn) 8988 { 8989 unsigned tie_t = 0; 8990 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 8991 tie_t = (tie_t << 2) | ((insn[0] << 14) >> 30); 8992 return tie_t; 8993 } 8994 8995 static void 8996 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 8997 { 8998 uint32 tie_t; 8999 tie_t = (val << 30) >> 30; 9000 insn[0] = (insn[0] & ~0x30000) | (tie_t << 16); 9001 tie_t = (val << 28) >> 30; 9002 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 9003 } 9004 9005 static unsigned 9006 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn) 9007 { 9008 unsigned tie_t = 0; 9009 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 9010 return tie_t; 9011 } 9012 9013 static void 9014 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9015 { 9016 uint32 tie_t; 9017 tie_t = (val << 31) >> 31; 9018 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 9019 } 9020 9021 static unsigned 9022 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn) 9023 { 9024 unsigned tie_t = 0; 9025 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9026 return tie_t; 9027 } 9028 9029 static void 9030 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9031 { 9032 uint32 tie_t; 9033 tie_t = (val << 28) >> 28; 9034 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9035 } 9036 9037 static unsigned 9038 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn) 9039 { 9040 unsigned tie_t = 0; 9041 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9042 return tie_t; 9043 } 9044 9045 static void 9046 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9047 { 9048 uint32 tie_t; 9049 tie_t = (val << 28) >> 28; 9050 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9051 } 9052 9053 static unsigned 9054 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn) 9055 { 9056 unsigned tie_t = 0; 9057 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 9058 return tie_t; 9059 } 9060 9061 static void 9062 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9063 { 9064 uint32 tie_t; 9065 tie_t = (val << 30) >> 30; 9066 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 9067 } 9068 9069 static unsigned 9070 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn) 9071 { 9072 unsigned tie_t = 0; 9073 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 9074 return tie_t; 9075 } 9076 9077 static void 9078 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9079 { 9080 uint32 tie_t; 9081 tie_t = (val << 30) >> 30; 9082 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 9083 } 9084 9085 static unsigned 9086 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn) 9087 { 9088 unsigned tie_t = 0; 9089 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9090 return tie_t; 9091 } 9092 9093 static void 9094 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9095 { 9096 uint32 tie_t; 9097 tie_t = (val << 28) >> 28; 9098 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9099 } 9100 9101 static unsigned 9102 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn) 9103 { 9104 unsigned tie_t = 0; 9105 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9106 return tie_t; 9107 } 9108 9109 static void 9110 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9111 { 9112 uint32 tie_t; 9113 tie_t = (val << 28) >> 28; 9114 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9115 } 9116 9117 static unsigned 9118 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn) 9119 { 9120 unsigned tie_t = 0; 9121 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 9122 return tie_t; 9123 } 9124 9125 static void 9126 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9127 { 9128 uint32 tie_t; 9129 tie_t = (val << 29) >> 29; 9130 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 9131 } 9132 9133 static unsigned 9134 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn) 9135 { 9136 unsigned tie_t = 0; 9137 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 9138 return tie_t; 9139 } 9140 9141 static void 9142 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9143 { 9144 uint32 tie_t; 9145 tie_t = (val << 29) >> 29; 9146 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 9147 } 9148 9149 static unsigned 9150 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn) 9151 { 9152 unsigned tie_t = 0; 9153 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 9154 return tie_t; 9155 } 9156 9157 static void 9158 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9159 { 9160 uint32 tie_t; 9161 tie_t = (val << 31) >> 31; 9162 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 9163 } 9164 9165 static unsigned 9166 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn) 9167 { 9168 unsigned tie_t = 0; 9169 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 9170 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9171 return tie_t; 9172 } 9173 9174 static void 9175 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9176 { 9177 uint32 tie_t; 9178 tie_t = (val << 28) >> 28; 9179 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9180 tie_t = (val << 26) >> 30; 9181 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 9182 } 9183 9184 static unsigned 9185 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn) 9186 { 9187 unsigned tie_t = 0; 9188 tie_t = (tie_t << 2) | ((insn[0] << 22) >> 30); 9189 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9190 return tie_t; 9191 } 9192 9193 static void 9194 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9195 { 9196 uint32 tie_t; 9197 tie_t = (val << 28) >> 28; 9198 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9199 tie_t = (val << 26) >> 30; 9200 insn[0] = (insn[0] & ~0x300) | (tie_t << 8); 9201 } 9202 9203 static unsigned 9204 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn) 9205 { 9206 unsigned tie_t = 0; 9207 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 9208 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9209 return tie_t; 9210 } 9211 9212 static void 9213 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9214 { 9215 uint32 tie_t; 9216 tie_t = (val << 28) >> 28; 9217 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9218 tie_t = (val << 25) >> 29; 9219 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 9220 } 9221 9222 static unsigned 9223 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn) 9224 { 9225 unsigned tie_t = 0; 9226 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 9227 tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28); 9228 return tie_t; 9229 } 9230 9231 static void 9232 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9233 { 9234 uint32 tie_t; 9235 tie_t = (val << 28) >> 28; 9236 insn[0] = (insn[0] & ~0xf) | (tie_t << 0); 9237 tie_t = (val << 25) >> 29; 9238 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 9239 } 9240 9241 static unsigned 9242 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn) 9243 { 9244 unsigned tie_t = 0; 9245 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 9246 return tie_t; 9247 } 9248 9249 static void 9250 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9251 { 9252 uint32 tie_t; 9253 tie_t = (val << 31) >> 31; 9254 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 9255 } 9256 9257 static unsigned 9258 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn) 9259 { 9260 unsigned tie_t = 0; 9261 tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); 9262 return tie_t; 9263 } 9264 9265 static void 9266 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9267 { 9268 uint32 tie_t; 9269 tie_t = (val << 31) >> 31; 9270 insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); 9271 } 9272 9273 static unsigned 9274 Field_y_Slot_inst_get (const xtensa_insnbuf insn) 9275 { 9276 unsigned tie_t = 0; 9277 tie_t = (tie_t << 1) | ((insn[0] << 13) >> 31); 9278 return tie_t; 9279 } 9280 9281 static void 9282 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9283 { 9284 uint32 tie_t; 9285 tie_t = (val << 31) >> 31; 9286 insn[0] = (insn[0] & ~0x40000) | (tie_t << 18); 9287 } 9288 9289 static unsigned 9290 Field_x_Slot_inst_get (const xtensa_insnbuf insn) 9291 { 9292 unsigned tie_t = 0; 9293 tie_t = (tie_t << 1) | ((insn[0] << 21) >> 31); 9294 return tie_t; 9295 } 9296 9297 static void 9298 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9299 { 9300 uint32 tie_t; 9301 tie_t = (val << 31) >> 31; 9302 insn[0] = (insn[0] & ~0x400) | (tie_t << 10); 9303 } 9304 9305 static unsigned 9306 Field_t2_Slot_inst_get (const xtensa_insnbuf insn) 9307 { 9308 unsigned tie_t = 0; 9309 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 9310 return tie_t; 9311 } 9312 9313 static void 9314 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9315 { 9316 uint32 tie_t; 9317 tie_t = (val << 29) >> 29; 9318 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 9319 } 9320 9321 static unsigned 9322 Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn) 9323 { 9324 unsigned tie_t = 0; 9325 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 9326 return tie_t; 9327 } 9328 9329 static void 9330 Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9331 { 9332 uint32 tie_t; 9333 tie_t = (val << 29) >> 29; 9334 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 9335 } 9336 9337 static unsigned 9338 Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn) 9339 { 9340 unsigned tie_t = 0; 9341 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 9342 return tie_t; 9343 } 9344 9345 static void 9346 Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9347 { 9348 uint32 tie_t; 9349 tie_t = (val << 29) >> 29; 9350 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 9351 } 9352 9353 static unsigned 9354 Field_t2_Slot_ae_slot1_get (const xtensa_insnbuf insn) 9355 { 9356 unsigned tie_t = 0; 9357 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 9358 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 9359 return tie_t; 9360 } 9361 9362 static void 9363 Field_t2_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 9364 { 9365 uint32 tie_t; 9366 tie_t = (val << 30) >> 30; 9367 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 9368 tie_t = (val << 29) >> 31; 9369 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 9370 } 9371 9372 static unsigned 9373 Field_s2_Slot_inst_get (const xtensa_insnbuf insn) 9374 { 9375 unsigned tie_t = 0; 9376 tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29); 9377 return tie_t; 9378 } 9379 9380 static void 9381 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9382 { 9383 uint32 tie_t; 9384 tie_t = (val << 29) >> 29; 9385 insn[0] = (insn[0] & ~0xe000) | (tie_t << 13); 9386 } 9387 9388 static unsigned 9389 Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn) 9390 { 9391 unsigned tie_t = 0; 9392 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 9393 return tie_t; 9394 } 9395 9396 static void 9397 Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9398 { 9399 uint32 tie_t; 9400 tie_t = (val << 29) >> 29; 9401 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 9402 } 9403 9404 static unsigned 9405 Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn) 9406 { 9407 unsigned tie_t = 0; 9408 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 9409 return tie_t; 9410 } 9411 9412 static void 9413 Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9414 { 9415 uint32 tie_t; 9416 tie_t = (val << 29) >> 29; 9417 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 9418 } 9419 9420 static unsigned 9421 Field_r2_Slot_inst_get (const xtensa_insnbuf insn) 9422 { 9423 unsigned tie_t = 0; 9424 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 9425 return tie_t; 9426 } 9427 9428 static void 9429 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9430 { 9431 uint32 tie_t; 9432 tie_t = (val << 29) >> 29; 9433 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 9434 } 9435 9436 static unsigned 9437 Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn) 9438 { 9439 unsigned tie_t = 0; 9440 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); 9441 return tie_t; 9442 } 9443 9444 static void 9445 Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9446 { 9447 uint32 tie_t; 9448 tie_t = (val << 29) >> 29; 9449 insn[0] = (insn[0] & ~0xe) | (tie_t << 1); 9450 } 9451 9452 static unsigned 9453 Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn) 9454 { 9455 unsigned tie_t = 0; 9456 tie_t = (tie_t << 3) | ((insn[0] << 28) >> 29); 9457 return tie_t; 9458 } 9459 9460 static void 9461 Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9462 { 9463 uint32 tie_t; 9464 tie_t = (val << 29) >> 29; 9465 insn[0] = (insn[0] & ~0xe) | (tie_t << 1); 9466 } 9467 9468 static unsigned 9469 Field_t4_Slot_inst_get (const xtensa_insnbuf insn) 9470 { 9471 unsigned tie_t = 0; 9472 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 9473 return tie_t; 9474 } 9475 9476 static void 9477 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9478 { 9479 uint32 tie_t; 9480 tie_t = (val << 30) >> 30; 9481 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 9482 } 9483 9484 static unsigned 9485 Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn) 9486 { 9487 unsigned tie_t = 0; 9488 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); 9489 return tie_t; 9490 } 9491 9492 static void 9493 Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9494 { 9495 uint32 tie_t; 9496 tie_t = (val << 30) >> 30; 9497 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); 9498 } 9499 9500 static unsigned 9501 Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn) 9502 { 9503 unsigned tie_t = 0; 9504 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); 9505 return tie_t; 9506 } 9507 9508 static void 9509 Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9510 { 9511 uint32 tie_t; 9512 tie_t = (val << 30) >> 30; 9513 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); 9514 } 9515 9516 static unsigned 9517 Field_s4_Slot_inst_get (const xtensa_insnbuf insn) 9518 { 9519 unsigned tie_t = 0; 9520 tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30); 9521 return tie_t; 9522 } 9523 9524 static void 9525 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9526 { 9527 uint32 tie_t; 9528 tie_t = (val << 30) >> 30; 9529 insn[0] = (insn[0] & ~0xc000) | (tie_t << 14); 9530 } 9531 9532 static unsigned 9533 Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn) 9534 { 9535 unsigned tie_t = 0; 9536 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 9537 return tie_t; 9538 } 9539 9540 static void 9541 Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9542 { 9543 uint32 tie_t; 9544 tie_t = (val << 30) >> 30; 9545 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 9546 } 9547 9548 static unsigned 9549 Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn) 9550 { 9551 unsigned tie_t = 0; 9552 tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30); 9553 return tie_t; 9554 } 9555 9556 static void 9557 Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9558 { 9559 uint32 tie_t; 9560 tie_t = (val << 30) >> 30; 9561 insn[0] = (insn[0] & ~0xc0) | (tie_t << 6); 9562 } 9563 9564 static unsigned 9565 Field_s4_Slot_ae_slot0_get (const xtensa_insnbuf insn) 9566 { 9567 unsigned tie_t = 0; 9568 tie_t = (tie_t << 2) | ((insn[0] << 9) >> 30); 9569 return tie_t; 9570 } 9571 9572 static void 9573 Field_s4_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 9574 { 9575 uint32 tie_t; 9576 tie_t = (val << 30) >> 30; 9577 insn[0] = (insn[0] & ~0x600000) | (tie_t << 21); 9578 } 9579 9580 static unsigned 9581 Field_r4_Slot_inst_get (const xtensa_insnbuf insn) 9582 { 9583 unsigned tie_t = 0; 9584 tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30); 9585 return tie_t; 9586 } 9587 9588 static void 9589 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9590 { 9591 uint32 tie_t; 9592 tie_t = (val << 30) >> 30; 9593 insn[0] = (insn[0] & ~0xc00) | (tie_t << 10); 9594 } 9595 9596 static unsigned 9597 Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn) 9598 { 9599 unsigned tie_t = 0; 9600 tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); 9601 return tie_t; 9602 } 9603 9604 static void 9605 Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9606 { 9607 uint32 tie_t; 9608 tie_t = (val << 30) >> 30; 9609 insn[0] = (insn[0] & ~0xc) | (tie_t << 2); 9610 } 9611 9612 static unsigned 9613 Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn) 9614 { 9615 unsigned tie_t = 0; 9616 tie_t = (tie_t << 2) | ((insn[0] << 28) >> 30); 9617 return tie_t; 9618 } 9619 9620 static void 9621 Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9622 { 9623 uint32 tie_t; 9624 tie_t = (val << 30) >> 30; 9625 insn[0] = (insn[0] & ~0xc) | (tie_t << 2); 9626 } 9627 9628 static unsigned 9629 Field_t8_Slot_inst_get (const xtensa_insnbuf insn) 9630 { 9631 unsigned tie_t = 0; 9632 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 9633 return tie_t; 9634 } 9635 9636 static void 9637 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9638 { 9639 uint32 tie_t; 9640 tie_t = (val << 31) >> 31; 9641 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 9642 } 9643 9644 static unsigned 9645 Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn) 9646 { 9647 unsigned tie_t = 0; 9648 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 9649 return tie_t; 9650 } 9651 9652 static void 9653 Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9654 { 9655 uint32 tie_t; 9656 tie_t = (val << 31) >> 31; 9657 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 9658 } 9659 9660 static unsigned 9661 Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn) 9662 { 9663 unsigned tie_t = 0; 9664 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 9665 return tie_t; 9666 } 9667 9668 static void 9669 Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9670 { 9671 uint32 tie_t; 9672 tie_t = (val << 31) >> 31; 9673 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 9674 } 9675 9676 static unsigned 9677 Field_s8_Slot_inst_get (const xtensa_insnbuf insn) 9678 { 9679 unsigned tie_t = 0; 9680 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 9681 return tie_t; 9682 } 9683 9684 static void 9685 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9686 { 9687 uint32 tie_t; 9688 tie_t = (val << 31) >> 31; 9689 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 9690 } 9691 9692 static unsigned 9693 Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn) 9694 { 9695 unsigned tie_t = 0; 9696 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 9697 return tie_t; 9698 } 9699 9700 static void 9701 Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9702 { 9703 uint32 tie_t; 9704 tie_t = (val << 31) >> 31; 9705 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 9706 } 9707 9708 static unsigned 9709 Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn) 9710 { 9711 unsigned tie_t = 0; 9712 tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31); 9713 return tie_t; 9714 } 9715 9716 static void 9717 Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9718 { 9719 uint32 tie_t; 9720 tie_t = (val << 31) >> 31; 9721 insn[0] = (insn[0] & ~0x80) | (tie_t << 7); 9722 } 9723 9724 static unsigned 9725 Field_r8_Slot_inst_get (const xtensa_insnbuf insn) 9726 { 9727 unsigned tie_t = 0; 9728 tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31); 9729 return tie_t; 9730 } 9731 9732 static void 9733 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9734 { 9735 uint32 tie_t; 9736 tie_t = (val << 31) >> 31; 9737 insn[0] = (insn[0] & ~0x800) | (tie_t << 11); 9738 } 9739 9740 static unsigned 9741 Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn) 9742 { 9743 unsigned tie_t = 0; 9744 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); 9745 return tie_t; 9746 } 9747 9748 static void 9749 Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 9750 { 9751 uint32 tie_t; 9752 tie_t = (val << 31) >> 31; 9753 insn[0] = (insn[0] & ~0x8) | (tie_t << 3); 9754 } 9755 9756 static unsigned 9757 Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn) 9758 { 9759 unsigned tie_t = 0; 9760 tie_t = (tie_t << 1) | ((insn[0] << 28) >> 31); 9761 return tie_t; 9762 } 9763 9764 static void 9765 Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 9766 { 9767 uint32 tie_t; 9768 tie_t = (val << 31) >> 31; 9769 insn[0] = (insn[0] & ~0x8) | (tie_t << 3); 9770 } 9771 9772 static unsigned 9773 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn) 9774 { 9775 unsigned tie_t = 0; 9776 tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17); 9777 return tie_t; 9778 } 9779 9780 static void 9781 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9782 { 9783 uint32 tie_t; 9784 tie_t = (val << 17) >> 17; 9785 insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9); 9786 } 9787 9788 static unsigned 9789 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn) 9790 { 9791 unsigned tie_t = 0; 9792 tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14); 9793 return tie_t; 9794 } 9795 9796 static void 9797 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9798 { 9799 uint32 tie_t; 9800 tie_t = (val << 14) >> 14; 9801 insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6); 9802 } 9803 9804 static unsigned 9805 Field_ae_r32_Slot_ae_slot0_get (const xtensa_insnbuf insn) 9806 { 9807 unsigned tie_t = 0; 9808 tie_t = (tie_t << 2) | ((insn[0] << 11) >> 30); 9809 return tie_t; 9810 } 9811 9812 static void 9813 Field_ae_r32_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 9814 { 9815 uint32 tie_t; 9816 tie_t = (val << 30) >> 30; 9817 insn[0] = (insn[0] & ~0x180000) | (tie_t << 19); 9818 } 9819 9820 static unsigned 9821 Field_ae_samt_s_t_Slot_inst_get (const xtensa_insnbuf insn) 9822 { 9823 unsigned tie_t = 0; 9824 tie_t = (tie_t << 6) | ((insn[0] << 12) >> 26); 9825 return tie_t; 9826 } 9827 9828 static void 9829 Field_ae_samt_s_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9830 { 9831 uint32 tie_t; 9832 tie_t = (val << 26) >> 26; 9833 insn[0] = (insn[0] & ~0xfc000) | (tie_t << 14); 9834 } 9835 9836 static unsigned 9837 Field_ae_samt_s_t_Slot_ae_slot0_get (const xtensa_insnbuf insn) 9838 { 9839 unsigned tie_t = 0; 9840 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 9841 tie_t = (tie_t << 2) | ((insn[0] << 13) >> 30); 9842 return tie_t; 9843 } 9844 9845 static void 9846 Field_ae_samt_s_t_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 9847 { 9848 uint32 tie_t; 9849 tie_t = (val << 30) >> 30; 9850 insn[0] = (insn[0] & ~0x60000) | (tie_t << 17); 9851 tie_t = (val << 26) >> 28; 9852 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 9853 } 9854 9855 static unsigned 9856 Field_ae_r20_Slot_inst_get (const xtensa_insnbuf insn) 9857 { 9858 unsigned tie_t = 0; 9859 tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29); 9860 return tie_t; 9861 } 9862 9863 static void 9864 Field_ae_r20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9865 { 9866 uint32 tie_t; 9867 tie_t = (val << 29) >> 29; 9868 insn[0] = (insn[0] & ~0x700) | (tie_t << 8); 9869 } 9870 9871 static unsigned 9872 Field_ae_r20_Slot_ae_slot0_get (const xtensa_insnbuf insn) 9873 { 9874 unsigned tie_t = 0; 9875 tie_t = (tie_t << 3) | ((insn[0] << 9) >> 29); 9876 return tie_t; 9877 } 9878 9879 static void 9880 Field_ae_r20_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 9881 { 9882 uint32 tie_t; 9883 tie_t = (val << 29) >> 29; 9884 insn[0] = (insn[0] & ~0x700000) | (tie_t << 20); 9885 } 9886 9887 static unsigned 9888 Field_ae_s20_Slot_inst_get (const xtensa_insnbuf insn) 9889 { 9890 unsigned tie_t = 0; 9891 tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29); 9892 return tie_t; 9893 } 9894 9895 static void 9896 Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9897 { 9898 uint32 tie_t; 9899 tie_t = (val << 29) >> 29; 9900 insn[0] = (insn[0] & ~0x7000) | (tie_t << 12); 9901 } 9902 9903 static unsigned 9904 Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn) 9905 { 9906 unsigned tie_t = 0; 9907 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 9908 return tie_t; 9909 } 9910 9911 static void 9912 Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9913 { 9914 uint32 tie_t; 9915 tie_t = (val << 28) >> 28; 9916 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 9917 } 9918 9919 static unsigned 9920 Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn) 9921 { 9922 unsigned tie_t = 0; 9923 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); 9924 return tie_t; 9925 } 9926 9927 static void 9928 Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9929 { 9930 uint32 tie_t; 9931 tie_t = (val << 28) >> 28; 9932 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); 9933 } 9934 9935 static unsigned 9936 Field_ftsf11_Slot_inst_get (const xtensa_insnbuf insn) 9937 { 9938 unsigned tie_t = 0; 9939 tie_t = (tie_t << 3) | ((insn[0] << 12) >> 29); 9940 return tie_t; 9941 } 9942 9943 static void 9944 Field_ftsf11_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9945 { 9946 uint32 tie_t; 9947 tie_t = (val << 29) >> 29; 9948 insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17); 9949 } 9950 9951 static unsigned 9952 Field_ftsf11_Slot_ae_slot1_get (const xtensa_insnbuf insn) 9953 { 9954 unsigned tie_t = 0; 9955 tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29); 9956 return tie_t; 9957 } 9958 9959 static void 9960 Field_ftsf11_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 9961 { 9962 uint32 tie_t; 9963 tie_t = (val << 29) >> 29; 9964 insn[0] = (insn[0] & ~0xe00) | (tie_t << 9); 9965 } 9966 9967 static unsigned 9968 Field_ftsf11_Slot_ae_slot0_get (const xtensa_insnbuf insn) 9969 { 9970 unsigned tie_t = 0; 9971 tie_t = (tie_t << 1) | ((insn[0] << 8) >> 31); 9972 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 9973 return tie_t; 9974 } 9975 9976 static void 9977 Field_ftsf11_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 9978 { 9979 uint32 tie_t; 9980 tie_t = (val << 30) >> 30; 9981 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 9982 tie_t = (val << 29) >> 31; 9983 insn[0] = (insn[0] & ~0x800000) | (tie_t << 23); 9984 } 9985 9986 static unsigned 9987 Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn) 9988 { 9989 unsigned tie_t = 0; 9990 tie_t = (tie_t << 2) | ((insn[0] << 12) >> 30); 9991 return tie_t; 9992 } 9993 9994 static void 9995 Field_ftsf12_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 9996 { 9997 uint32 tie_t; 9998 tie_t = (val << 30) >> 30; 9999 insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18); 10000 } 10001 10002 static unsigned 10003 Field_ftsf12_Slot_ae_slot1_get (const xtensa_insnbuf insn) 10004 { 10005 unsigned tie_t = 0; 10006 tie_t = (tie_t << 2) | ((insn[0] << 23) >> 30); 10007 return tie_t; 10008 } 10009 10010 static void 10011 Field_ftsf12_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 10012 { 10013 uint32 tie_t; 10014 tie_t = (val << 30) >> 30; 10015 insn[0] = (insn[0] & ~0x180) | (tie_t << 7); 10016 } 10017 10018 static unsigned 10019 Field_ftsf13_Slot_ae_slot1_get (const xtensa_insnbuf insn) 10020 { 10021 unsigned tie_t = 0; 10022 tie_t = (tie_t << 1) | ((insn[0] << 12) >> 31); 10023 tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28); 10024 return tie_t; 10025 } 10026 10027 static void 10028 Field_ftsf13_Slot_ae_slot1_set (xtensa_insnbuf insn, uint32 val) 10029 { 10030 uint32 tie_t; 10031 tie_t = (val << 28) >> 28; 10032 insn[0] = (insn[0] & ~0xf000) | (tie_t << 12); 10033 tie_t = (val << 27) >> 31; 10034 insn[0] = (insn[0] & ~0x80000) | (tie_t << 19); 10035 } 10036 10037 static unsigned 10038 Field_combined2c0b5f72_fld37_Slot_ae_slot0_get (const xtensa_insnbuf insn) 10039 { 10040 unsigned tie_t = 0; 10041 tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31); 10042 return tie_t; 10043 } 10044 10045 static void 10046 Field_combined2c0b5f72_fld37_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 10047 { 10048 uint32 tie_t; 10049 tie_t = (val << 31) >> 31; 10050 insn[0] = (insn[0] & ~0x10000) | (tie_t << 16); 10051 } 10052 10053 static unsigned 10054 Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get (const xtensa_insnbuf insn) 10055 { 10056 unsigned tie_t = 0; 10057 tie_t = (tie_t << 11) | ((insn[0] << 14) >> 21); 10058 return tie_t; 10059 } 10060 10061 static void 10062 Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 10063 { 10064 uint32 tie_t; 10065 tie_t = (val << 21) >> 21; 10066 insn[0] = (insn[0] & ~0x3ff80) | (tie_t << 7); 10067 } 10068 10069 static unsigned 10070 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn) 10071 { 10072 unsigned tie_t = 0; 10073 tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31); 10074 tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28); 10075 return tie_t; 10076 } 10077 10078 static void 10079 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val) 10080 { 10081 uint32 tie_t; 10082 tie_t = (val << 28) >> 28; 10083 insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16); 10084 tie_t = (val << 27) >> 31; 10085 insn[0] = (insn[0] & ~0x1000) | (tie_t << 12); 10086 } 10087 10088 static unsigned 10089 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn) 10090 { 10091 unsigned tie_t = 0; 10092 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 10093 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 10094 return tie_t; 10095 } 10096 10097 static void 10098 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 10099 { 10100 uint32 tie_t; 10101 tie_t = (val << 28) >> 28; 10102 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 10103 tie_t = (val << 27) >> 31; 10104 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 10105 } 10106 10107 static unsigned 10108 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn) 10109 { 10110 unsigned tie_t = 0; 10111 tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31); 10112 tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28); 10113 return tie_t; 10114 } 10115 10116 static void 10117 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 10118 { 10119 uint32 tie_t; 10120 tie_t = (val << 28) >> 28; 10121 insn[0] = (insn[0] & ~0xf00) | (tie_t << 8); 10122 tie_t = (val << 27) >> 31; 10123 insn[0] = (insn[0] & ~0x10) | (tie_t << 4); 10124 } 10125 10126 static unsigned 10127 Field_bitindex_Slot_ae_slot0_get (const xtensa_insnbuf insn) 10128 { 10129 unsigned tie_t = 0; 10130 tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31); 10131 tie_t = (tie_t << 4) | ((insn[0] << 5) >> 28); 10132 return tie_t; 10133 } 10134 10135 static void 10136 Field_bitindex_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 10137 { 10138 uint32 tie_t; 10139 tie_t = (val << 28) >> 28; 10140 insn[0] = (insn[0] & ~0x7800000) | (tie_t << 23); 10141 tie_t = (val << 27) >> 31; 10142 insn[0] = (insn[0] & ~0x8000) | (tie_t << 15); 10143 } 10144 10145 static unsigned 10146 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn) 10147 { 10148 unsigned tie_t = 0; 10149 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 10150 return tie_t; 10151 } 10152 10153 static void 10154 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) 10155 { 10156 uint32 tie_t; 10157 tie_t = (val << 29) >> 29; 10158 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 10159 } 10160 10161 static unsigned 10162 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn) 10163 { 10164 unsigned tie_t = 0; 10165 tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29); 10166 return tie_t; 10167 } 10168 10169 static void 10170 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val) 10171 { 10172 uint32 tie_t; 10173 tie_t = (val << 29) >> 29; 10174 insn[0] = (insn[0] & ~0xe0) | (tie_t << 5); 10175 } 10176 10177 static unsigned 10178 Field_s3to1_Slot_ae_slot0_get (const xtensa_insnbuf insn) 10179 { 10180 unsigned tie_t = 0; 10181 tie_t = (tie_t << 3) | ((insn[0] << 13) >> 29); 10182 return tie_t; 10183 } 10184 10185 static void 10186 Field_s3to1_Slot_ae_slot0_set (xtensa_insnbuf insn, uint32 val) 10187 { 10188 uint32 tie_t; 10189 tie_t = (val << 29) >> 29; 10190 insn[0] = (insn[0] & ~0x70000) | (tie_t << 16); 10191 } 10192 10193 static void 10194 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED, 10195 uint32 val ATTRIBUTE_UNUSED) 10196 { 10197 /* Do nothing. */ 10198 } 10199 10200 static unsigned 10201 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10202 { 10203 return 0; 10204 } 10205 10206 static unsigned 10207 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10208 { 10209 return 4; 10210 } 10211 10212 static unsigned 10213 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10214 { 10215 return 8; 10216 } 10217 10218 static unsigned 10219 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10220 { 10221 return 12; 10222 } 10223 10224 static unsigned 10225 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10226 { 10227 return 0; 10228 } 10229 10230 static unsigned 10231 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10232 { 10233 return 1; 10234 } 10235 10236 static unsigned 10237 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10238 { 10239 return 2; 10240 } 10241 10242 static unsigned 10243 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10244 { 10245 return 3; 10246 } 10247 10248 static unsigned 10249 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10250 { 10251 return 0; 10252 } 10253 10254 static unsigned 10255 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10256 { 10257 return 0; 10258 } 10259 10260 static unsigned 10261 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10262 { 10263 return 0; 10264 } 10265 10266 static unsigned 10267 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED) 10268 { 10269 return 0; 10270 } 10271 10272 enum xtensa_field_id { 10273 FIELD_t, 10274 FIELD_bbi4, 10275 FIELD_bbi, 10276 FIELD_imm12, 10277 FIELD_imm8, 10278 FIELD_s, 10279 FIELD_imm12b, 10280 FIELD_imm16, 10281 FIELD_m, 10282 FIELD_n, 10283 FIELD_offset, 10284 FIELD_op0, 10285 FIELD_op1, 10286 FIELD_op2, 10287 FIELD_r, 10288 FIELD_sa4, 10289 FIELD_sae4, 10290 FIELD_sae, 10291 FIELD_sal, 10292 FIELD_sargt, 10293 FIELD_sas4, 10294 FIELD_sas, 10295 FIELD_sr, 10296 FIELD_st, 10297 FIELD_thi3, 10298 FIELD_imm4, 10299 FIELD_mn, 10300 FIELD_i, 10301 FIELD_imm6lo, 10302 FIELD_imm6hi, 10303 FIELD_imm7lo, 10304 FIELD_imm7hi, 10305 FIELD_z, 10306 FIELD_imm6, 10307 FIELD_imm7, 10308 FIELD_r3, 10309 FIELD_rbit2, 10310 FIELD_rhi, 10311 FIELD_t3, 10312 FIELD_tbit2, 10313 FIELD_tlo, 10314 FIELD_w, 10315 FIELD_y, 10316 FIELD_x, 10317 FIELD_t2, 10318 FIELD_s2, 10319 FIELD_r2, 10320 FIELD_t4, 10321 FIELD_s4, 10322 FIELD_r4, 10323 FIELD_t8, 10324 FIELD_s8, 10325 FIELD_r8, 10326 FIELD_xt_wbr15_imm, 10327 FIELD_xt_wbr18_imm, 10328 FIELD_ae_r3, 10329 FIELD_ae_s_non_samt, 10330 FIELD_ae_s3, 10331 FIELD_ae_r32, 10332 FIELD_ae_samt_s_t, 10333 FIELD_ae_r20, 10334 FIELD_ae_r10, 10335 FIELD_ae_s20, 10336 FIELD_ae_fld_ohba, 10337 FIELD_ae_fld_ohba2, 10338 FIELD_op0_s3, 10339 FIELD_ftsf11, 10340 FIELD_ftsf12, 10341 FIELD_ftsf13, 10342 FIELD_ftsf20ae_slot1, 10343 FIELD_ftsf21ae_slot1, 10344 FIELD_ftsf22ae_slot1, 10345 FIELD_ftsf23ae_slot1, 10346 FIELD_ftsf24ae_slot1, 10347 FIELD_ftsf25ae_slot1, 10348 FIELD_ftsf26ae_slot1, 10349 FIELD_ftsf27ae_slot1, 10350 FIELD_ftsf28ae_slot1, 10351 FIELD_ftsf29ae_slot1, 10352 FIELD_ftsf30ae_slot1, 10353 FIELD_ftsf31ae_slot1, 10354 FIELD_ftsf32ae_slot1, 10355 FIELD_ftsf33ae_slot1, 10356 FIELD_ftsf34ae_slot1, 10357 FIELD_ftsf35ae_slot1, 10358 FIELD_ftsf36ae_slot1, 10359 FIELD_ftsf37ae_slot1, 10360 FIELD_ftsf38ae_slot1, 10361 FIELD_ftsf40ae_slot1, 10362 FIELD_ftsf41ae_slot1, 10363 FIELD_ftsf42ae_slot1, 10364 FIELD_ftsf43ae_slot1, 10365 FIELD_ftsf45ae_slot1, 10366 FIELD_ftsf47ae_slot1, 10367 FIELD_ftsf48ae_slot1, 10368 FIELD_ftsf49ae_slot1, 10369 FIELD_ftsf50ae_slot1, 10370 FIELD_ftsf51ae_slot1, 10371 FIELD_ftsf52ae_slot1, 10372 FIELD_ftsf53ae_slot1, 10373 FIELD_ftsf54ae_slot1, 10374 FIELD_ftsf55, 10375 FIELD_ftsf56ae_slot1, 10376 FIELD_ftsf57ae_slot1, 10377 FIELD_ftsf58ae_slot1, 10378 FIELD_ftsf60ae_slot1, 10379 FIELD_ftsf61, 10380 FIELD_ftsf62ae_slot1, 10381 FIELD_ftsf63ae_slot1, 10382 FIELD_ftsf64ae_slot1, 10383 FIELD_ftsf66ae_slot1, 10384 FIELD_ftsf68ae_slot1, 10385 FIELD_ftsf69ae_slot1, 10386 FIELD_ftsf70ae_slot1, 10387 FIELD_ftsf71ae_slot1, 10388 FIELD_ftsf72ae_slot1, 10389 FIELD_ftsf73ae_slot1, 10390 FIELD_ftsf74ae_slot1, 10391 FIELD_ftsf75ae_slot1, 10392 FIELD_ftsf76ae_slot1, 10393 FIELD_ftsf77ae_slot1, 10394 FIELD_ftsf78ae_slot1, 10395 FIELD_ftsf79ae_slot1, 10396 FIELD_ftsf80ae_slot1, 10397 FIELD_ftsf81ae_slot1, 10398 FIELD_ftsf82ae_slot1, 10399 FIELD_ftsf83ae_slot1, 10400 FIELD_ftsf84ae_slot1, 10401 FIELD_ftsf85ae_slot1, 10402 FIELD_ftsf86ae_slot1, 10403 FIELD_ftsf87ae_slot1, 10404 FIELD_ftsf88ae_slot1, 10405 FIELD_ftsf89ae_slot1, 10406 FIELD_ftsf90ae_slot1, 10407 FIELD_ftsf91, 10408 FIELD_ftsf92ae_slot1, 10409 FIELD_ftsf93ae_slot1, 10410 FIELD_ftsf94ae_slot1, 10411 FIELD_ftsf96ae_slot1, 10412 FIELD_ftsf97ae_slot1, 10413 FIELD_ftsf99ae_slot1, 10414 FIELD_ftsf101ae_slot1, 10415 FIELD_ftsf102ae_slot1, 10416 FIELD_ftsf103ae_slot1, 10417 FIELD_ftsf106ae_slot1, 10418 FIELD_ftsf107ae_slot1, 10419 FIELD_ftsf108ae_slot1, 10420 FIELD_ftsf109ae_slot1, 10421 FIELD_ftsf110ae_slot1, 10422 FIELD_ftsf111ae_slot1, 10423 FIELD_ftsf112ae_slot1, 10424 FIELD_ftsf113ae_slot1, 10425 FIELD_ftsf114ae_slot1, 10426 FIELD_ftsf115ae_slot1, 10427 FIELD_ftsf116ae_slot1, 10428 FIELD_ftsf117ae_slot1, 10429 FIELD_ftsf118ae_slot1, 10430 FIELD_ftsf120ae_slot1, 10431 FIELD_ftsf121ae_slot1, 10432 FIELD_ftsf123ae_slot1, 10433 FIELD_ftsf124ae_slot1, 10434 FIELD_ftsf125ae_slot1, 10435 FIELD_ftsf126ae_slot1, 10436 FIELD_ftsf127ae_slot1, 10437 FIELD_ftsf128ae_slot1, 10438 FIELD_ftsf129ae_slot1, 10439 FIELD_ftsf130ae_slot1, 10440 FIELD_ftsf131ae_slot1, 10441 FIELD_ftsf132ae_slot1, 10442 FIELD_ftsf133ae_slot1, 10443 FIELD_ftsf134ae_slot1, 10444 FIELD_ftsf135ae_slot1, 10445 FIELD_ftsf136ae_slot1, 10446 FIELD_ftsf137ae_slot1, 10447 FIELD_ftsf138ae_slot1, 10448 FIELD_ftsf139ae_slot1, 10449 FIELD_ftsf140ae_slot1, 10450 FIELD_ftsf141ae_slot1, 10451 FIELD_ftsf142ae_slot1, 10452 FIELD_ftsf143ae_slot1, 10453 FIELD_ftsf144ae_slot1, 10454 FIELD_ftsf145ae_slot1, 10455 FIELD_ftsf146ae_slot1, 10456 FIELD_ftsf147ae_slot1, 10457 FIELD_ftsf148ae_slot1, 10458 FIELD_ftsf149ae_slot1, 10459 FIELD_ftsf150ae_slot1, 10460 FIELD_ftsf151ae_slot1, 10461 FIELD_ftsf152ae_slot1, 10462 FIELD_ftsf153ae_slot1, 10463 FIELD_ftsf154ae_slot1, 10464 FIELD_ftsf155ae_slot1, 10465 FIELD_ftsf156ae_slot1, 10466 FIELD_ftsf157ae_slot1, 10467 FIELD_ftsf158ae_slot1, 10468 FIELD_ftsf159ae_slot1, 10469 FIELD_ftsf160ae_slot1, 10470 FIELD_ftsf161ae_slot1, 10471 FIELD_ftsf162ae_slot1, 10472 FIELD_ftsf163ae_slot1, 10473 FIELD_ftsf164ae_slot1, 10474 FIELD_ftsf165ae_slot1, 10475 FIELD_ftsf166ae_slot1, 10476 FIELD_ftsf167ae_slot1, 10477 FIELD_ftsf168ae_slot1, 10478 FIELD_ftsf169ae_slot1, 10479 FIELD_ftsf170ae_slot1, 10480 FIELD_ftsf171ae_slot1, 10481 FIELD_ftsf172ae_slot1, 10482 FIELD_ftsf173ae_slot1, 10483 FIELD_ftsf174ae_slot1, 10484 FIELD_ftsf175ae_slot1, 10485 FIELD_ftsf176ae_slot1, 10486 FIELD_ftsf177ae_slot1, 10487 FIELD_ftsf178ae_slot1, 10488 FIELD_ftsf179ae_slot1, 10489 FIELD_ftsf180ae_slot1, 10490 FIELD_ftsf181ae_slot1, 10491 FIELD_ftsf182ae_slot1, 10492 FIELD_ftsf183ae_slot1, 10493 FIELD_ftsf184ae_slot1, 10494 FIELD_ftsf185ae_slot1, 10495 FIELD_ftsf186ae_slot1, 10496 FIELD_ftsf187ae_slot1, 10497 FIELD_ftsf188ae_slot1, 10498 FIELD_ftsf189ae_slot1, 10499 FIELD_ftsf190ae_slot1, 10500 FIELD_ftsf191ae_slot1, 10501 FIELD_ftsf192ae_slot1, 10502 FIELD_ftsf193ae_slot1, 10503 FIELD_ftsf194ae_slot1, 10504 FIELD_ftsf195ae_slot1, 10505 FIELD_ftsf196ae_slot1, 10506 FIELD_ftsf197ae_slot1, 10507 FIELD_ftsf198ae_slot1, 10508 FIELD_ftsf199ae_slot1, 10509 FIELD_ftsf200ae_slot1, 10510 FIELD_ftsf201ae_slot1, 10511 FIELD_ftsf202ae_slot1, 10512 FIELD_ftsf203ae_slot1, 10513 FIELD_ftsf204ae_slot1, 10514 FIELD_ftsf205ae_slot1, 10515 FIELD_ftsf206ae_slot1, 10516 FIELD_ftsf207ae_slot1, 10517 FIELD_ftsf208ae_slot1, 10518 FIELD_ftsf210ae_slot1, 10519 FIELD_ftsf333ae_slot1, 10520 FIELD_ftsf334ae_slot1, 10521 FIELD_ftsf335, 10522 FIELD_ftsf336ae_slot1, 10523 FIELD_ftsf337ae_slot1, 10524 FIELD_ftsf339ae_slot1, 10525 FIELD_ftsf340ae_slot1, 10526 FIELD_ftsf341ae_slot1, 10527 FIELD_ftsf342ae_slot1, 10528 FIELD_ftsf343ae_slot1, 10529 FIELD_ftsf344ae_slot1, 10530 FIELD_ftsf345ae_slot1, 10531 FIELD_ftsf347ae_slot1, 10532 FIELD_ftsf348ae_slot1, 10533 FIELD_ftsf349ae_slot1, 10534 FIELD_ftsf350ae_slot1, 10535 FIELD_ftsf351, 10536 FIELD_ftsf352ae_slot1, 10537 FIELD_ftsf354ae_slot1, 10538 FIELD_ftsf355ae_slot1, 10539 FIELD_ftsf356ae_slot1, 10540 FIELD_ftsf357ae_slot1, 10541 FIELD_ftsf358ae_slot1, 10542 FIELD_ftsf359ae_slot1, 10543 FIELD_op0_s4, 10544 FIELD_ftsf211ae_slot0, 10545 FIELD_ftsf212ae_slot0, 10546 FIELD_ftsf213ae_slot0, 10547 FIELD_ftsf214ae_slot0, 10548 FIELD_ftsf215ae_slot0, 10549 FIELD_ftsf217ae_slot0, 10550 FIELD_ftsf218ae_slot0, 10551 FIELD_ftsf219ae_slot0, 10552 FIELD_ftsf220ae_slot0, 10553 FIELD_ftsf221ae_slot0, 10554 FIELD_ftsf222ae_slot0, 10555 FIELD_ftsf223ae_slot0, 10556 FIELD_ftsf224ae_slot0, 10557 FIELD_ftsf225ae_slot0, 10558 FIELD_ftsf226ae_slot0, 10559 FIELD_ftsf227ae_slot0, 10560 FIELD_ftsf228ae_slot0, 10561 FIELD_ftsf229ae_slot0, 10562 FIELD_ftsf230ae_slot0, 10563 FIELD_ftsf231ae_slot0, 10564 FIELD_ftsf232ae_slot0, 10565 FIELD_ftsf233ae_slot0, 10566 FIELD_ftsf234ae_slot0, 10567 FIELD_ftsf235ae_slot0, 10568 FIELD_ftsf236ae_slot0, 10569 FIELD_ftsf237ae_slot0, 10570 FIELD_ftsf238ae_slot0, 10571 FIELD_ftsf239ae_slot0, 10572 FIELD_ftsf240ae_slot0, 10573 FIELD_ftsf241ae_slot0, 10574 FIELD_ftsf242ae_slot0, 10575 FIELD_ftsf243ae_slot0, 10576 FIELD_ftsf244ae_slot0, 10577 FIELD_ftsf245ae_slot0, 10578 FIELD_ftsf246ae_slot0, 10579 FIELD_ftsf247ae_slot0, 10580 FIELD_ftsf248ae_slot0, 10581 FIELD_ftsf249ae_slot0, 10582 FIELD_ftsf250ae_slot0, 10583 FIELD_ftsf251ae_slot0, 10584 FIELD_ftsf252ae_slot0, 10585 FIELD_ftsf253ae_slot0, 10586 FIELD_ftsf254ae_slot0, 10587 FIELD_ftsf255ae_slot0, 10588 FIELD_ftsf256ae_slot0, 10589 FIELD_ftsf257ae_slot0, 10590 FIELD_ftsf258ae_slot0, 10591 FIELD_ftsf259ae_slot0, 10592 FIELD_ftsf260ae_slot0, 10593 FIELD_ftsf261ae_slot0, 10594 FIELD_ftsf262ae_slot0, 10595 FIELD_ftsf263ae_slot0, 10596 FIELD_ftsf264ae_slot0, 10597 FIELD_ftsf265ae_slot0, 10598 FIELD_ftsf266ae_slot0, 10599 FIELD_ftsf267ae_slot0, 10600 FIELD_ftsf268ae_slot0, 10601 FIELD_ftsf269ae_slot0, 10602 FIELD_ftsf270ae_slot0, 10603 FIELD_ftsf271ae_slot0, 10604 FIELD_ftsf272ae_slot0, 10605 FIELD_ftsf273ae_slot0, 10606 FIELD_ftsf274ae_slot0, 10607 FIELD_ftsf275ae_slot0, 10608 FIELD_ftsf276ae_slot0, 10609 FIELD_ftsf277ae_slot0, 10610 FIELD_ftsf278ae_slot0, 10611 FIELD_ftsf279ae_slot0, 10612 FIELD_ftsf280, 10613 FIELD_ftsf281ae_slot0, 10614 FIELD_ftsf282ae_slot0, 10615 FIELD_ftsf284ae_slot0, 10616 FIELD_ftsf285ae_slot0, 10617 FIELD_ftsf287ae_slot0, 10618 FIELD_ftsf288, 10619 FIELD_ftsf289ae_slot0, 10620 FIELD_ftsf290ae_slot0, 10621 FIELD_ftsf291ae_slot0, 10622 FIELD_ftsf292ae_slot0, 10623 FIELD_ftsf293ae_slot0, 10624 FIELD_ftsf294ae_slot0, 10625 FIELD_ftsf295ae_slot0, 10626 FIELD_ftsf296ae_slot0, 10627 FIELD_ftsf297ae_slot0, 10628 FIELD_ftsf298ae_slot0, 10629 FIELD_ftsf300ae_slot0, 10630 FIELD_ftsf302ae_slot0, 10631 FIELD_ftsf304ae_slot0, 10632 FIELD_ftsf305ae_slot0, 10633 FIELD_ftsf306ae_slot0, 10634 FIELD_ftsf307ae_slot0, 10635 FIELD_ftsf308ae_slot0, 10636 FIELD_ftsf309, 10637 FIELD_ftsf310ae_slot0, 10638 FIELD_ftsf311ae_slot0, 10639 FIELD_ftsf312ae_slot0, 10640 FIELD_ftsf313ae_slot0, 10641 FIELD_ftsf314ae_slot0, 10642 FIELD_ftsf315, 10643 FIELD_ftsf316ae_slot0, 10644 FIELD_ftsf317ae_slot0, 10645 FIELD_ftsf319ae_slot0, 10646 FIELD_ftsf320ae_slot0, 10647 FIELD_ftsf322ae_slot0, 10648 FIELD_ftsf323ae_slot0, 10649 FIELD_ftsf324ae_slot0, 10650 FIELD_ftsf325ae_slot0, 10651 FIELD_ftsf326ae_slot0, 10652 FIELD_ftsf327ae_slot0, 10653 FIELD_ftsf328ae_slot0, 10654 FIELD_ftsf329ae_slot0, 10655 FIELD_ftsf360ae_slot0, 10656 FIELD_ftsf361ae_slot0, 10657 FIELD_ftsf362, 10658 FIELD_ftsf363ae_slot0, 10659 FIELD_ftsf364ae_slot0, 10660 FIELD_ftsf366ae_slot0, 10661 FIELD_ftsf368ae_slot0, 10662 FIELD_ftsf370ae_slot0, 10663 FIELD_ftsf373ae_slot0, 10664 FIELD_ftsf376ae_slot0, 10665 FIELD_ftsf378ae_slot0, 10666 FIELD_ftsf379ae_slot0, 10667 FIELD_ftsf382ae_slot0, 10668 FIELD_ftsf383ae_slot0, 10669 FIELD_ftsf384ae_slot0, 10670 FIELD_ftsf386ae_slot0, 10671 FIELD_ftsf387ae_slot0, 10672 FIELD_ftsf388ae_slot0, 10673 FIELD_ftsf389ae_slot0, 10674 FIELD_ae_mul32x24fld, 10675 FIELD_op0_s4_s4, 10676 FIELD_combined2c0b5f72_fld28, 10677 FIELD_combined2c0b5f72_fld37, 10678 FIELD_combined2c0b5f72_fld39, 10679 FIELD_combined2c0b5f72_fld40, 10680 FIELD_combined2c0b5f72_fld46, 10681 FIELD_combined2c0b5f72_fld47, 10682 FIELD_combined2c0b5f72_fld49, 10683 FIELD_combined2c0b5f72_fld50, 10684 FIELD_combined2c0b5f72_fld52, 10685 FIELD_combined2c0b5f72_fld121, 10686 FIELD_combined2c0b5f72_fld123, 10687 FIELD_combined2c0b5f72_fld127, 10688 FIELD_combined2c0b5f72_fld133ae_slot0, 10689 FIELD_combined2c0b5f72_fld134ae_slot0, 10690 FIELD_combined2c0b5f72_fld135ae_slot0, 10691 FIELD_combined2c0b5f72_fld136ae_slot0, 10692 FIELD_combined2c0b5f72_fld137ae_slot0, 10693 FIELD_combined2c0b5f72_fld138ae_slot0, 10694 FIELD_combined2c0b5f72_fld139ae_slot0, 10695 FIELD_combined2c0b5f72_fld140ae_slot0, 10696 FIELD_combined2c0b5f72_fld141ae_slot0, 10697 FIELD_combined2c0b5f72_fld142ae_slot0, 10698 FIELD_combined2c0b5f72_fld143ae_slot0, 10699 FIELD_combined2c0b5f72_fld144ae_slot0, 10700 FIELD_combined2c0b5f72_fld145ae_slot0, 10701 FIELD_combined2c0b5f72_fld146ae_slot0, 10702 FIELD_combined2c0b5f72_fld148ae_slot0, 10703 FIELD_combined2c0b5f72_fld149ae_slot0, 10704 FIELD_op0_s4_s4_s4, 10705 FIELD_combined1e9fefee_fld96, 10706 FIELD_combined1e9fefee_fld98, 10707 FIELD_combined1e9fefee_fld106ae_slot0, 10708 FIELD_combined1e9fefee_fld107ae_slot0, 10709 FIELD_combined1e9fefee_fld108ae_slot0, 10710 FIELD_combined1e9fefee_fld109ae_slot0, 10711 FIELD_op0_s3_s3, 10712 FIELD_combined2c0b5f72_fld19, 10713 FIELD_combined2c0b5f72_fld22, 10714 FIELD_combined2c0b5f72_fld24, 10715 FIELD_combined2c0b5f72_fld65, 10716 FIELD_combined2c0b5f72_fld66, 10717 FIELD_combined2c0b5f72_fld68, 10718 FIELD_combined2c0b5f72_fld69, 10719 FIELD_combined2c0b5f72_fld74, 10720 FIELD_combined2c0b5f72_fld79, 10721 FIELD_combined2c0b5f72_fld88, 10722 FIELD_combined2c0b5f72_fld90, 10723 FIELD_combined2c0b5f72_fld91, 10724 FIELD_combined2c0b5f72_fld131ae_slot1, 10725 FIELD_combined2c0b5f72_fld132ae_slot1, 10726 FIELD_combined2c0b5f72_fld147ae_slot1, 10727 FIELD_bitindex, 10728 FIELD_s3to1, 10729 FIELD__ar0, 10730 FIELD__ar4, 10731 FIELD__ar8, 10732 FIELD__ar12, 10733 FIELD__mr0, 10734 FIELD__mr1, 10735 FIELD__mr2, 10736 FIELD__mr3, 10737 FIELD__bt16, 10738 FIELD__bs16, 10739 FIELD__br16, 10740 FIELD__brall 10741 }; 10742 10743 10744 /* Functional units. */ 10745 10746 static xtensa_funcUnit_internal funcUnits[] = { 10747 { "ae_add32", 1 }, 10748 { "ae_shift32x4", 1 }, 10749 { "ae_shift32x5", 1 }, 10750 { "ae_subshift", 1 } 10751 }; 10752 10753 enum xtensa_funcUnit_id { 10754 FUNCUNIT_ae_add32, 10755 FUNCUNIT_ae_shift32x4, 10756 FUNCUNIT_ae_shift32x5, 10757 FUNCUNIT_ae_subshift 10758 }; 10759 10760 10761 /* Register files. */ 10762 10763 enum xtensa_regfile_id { 10764 REGFILE_AR, 10765 REGFILE_MR, 10766 REGFILE_BR, 10767 REGFILE_AE_PR, 10768 REGFILE_AE_QR, 10769 REGFILE_BR2, 10770 REGFILE_BR4, 10771 REGFILE_BR8, 10772 REGFILE_BR16 10773 }; 10774 10775 static xtensa_regfile_internal regfiles[] = { 10776 { "AR", "a", REGFILE_AR, 32, 32 }, 10777 { "MR", "m", REGFILE_MR, 32, 4 }, 10778 { "BR", "b", REGFILE_BR, 1, 16 }, 10779 { "AE_PR", "aep", REGFILE_AE_PR, 48, 8 }, 10780 { "AE_QR", "aeq", REGFILE_AE_QR, 56, 4 }, 10781 { "BR2", "b", REGFILE_BR, 2, 8 }, 10782 { "BR4", "b", REGFILE_BR, 4, 4 }, 10783 { "BR8", "b", REGFILE_BR, 8, 2 }, 10784 { "BR16", "b", REGFILE_BR, 16, 1 } 10785 }; 10786 10787 10788 /* Interfaces. */ 10789 10790 static xtensa_interface_internal interfaces[] = { 10791 { "ERI_RD_Out", 14, 0, 0, 'o' }, 10792 { "ERI_RD_In", 32, 0, 1, 'i' }, 10793 { "ERI_RD_Rdy", 1, 0, 0, 'i' }, 10794 { "ERI_WR_Out", 46, 0, 2, 'o' }, 10795 { "ERI_WR_In", 1, 0, 3, 'i' }, 10796 { "IMPWIRE", 32, 0, 4, 'i' } 10797 }; 10798 10799 enum xtensa_interface_id { 10800 INTERFACE_ERI_RD_Out, 10801 INTERFACE_ERI_RD_In, 10802 INTERFACE_ERI_RD_Rdy, 10803 INTERFACE_ERI_WR_Out, 10804 INTERFACE_ERI_WR_In, 10805 INTERFACE_IMPWIRE 10806 }; 10807 10808 10809 /* Constant tables. */ 10810 10811 /* constant table ai4c */ 10812 static const unsigned CONST_TBL_ai4c_0[] = { 10813 0xffffffff, 10814 0x1, 10815 0x2, 10816 0x3, 10817 0x4, 10818 0x5, 10819 0x6, 10820 0x7, 10821 0x8, 10822 0x9, 10823 0xa, 10824 0xb, 10825 0xc, 10826 0xd, 10827 0xe, 10828 0xf, 10829 0 10830 }; 10831 10832 /* constant table b4c */ 10833 static const unsigned CONST_TBL_b4c_0[] = { 10834 0xffffffff, 10835 0x1, 10836 0x2, 10837 0x3, 10838 0x4, 10839 0x5, 10840 0x6, 10841 0x7, 10842 0x8, 10843 0xa, 10844 0xc, 10845 0x10, 10846 0x20, 10847 0x40, 10848 0x80, 10849 0x100, 10850 0 10851 }; 10852 10853 /* constant table b4cu */ 10854 static const unsigned CONST_TBL_b4cu_0[] = { 10855 0x8000, 10856 0x10000, 10857 0x2, 10858 0x3, 10859 0x4, 10860 0x5, 10861 0x6, 10862 0x7, 10863 0x8, 10864 0xa, 10865 0xc, 10866 0x10, 10867 0x20, 10868 0x40, 10869 0x80, 10870 0x100, 10871 0 10872 }; 10873 10874 10875 /* Instruction operands. */ 10876 10877 static int 10878 OperandSem_opnd_sem_MR_0_decode (uint32 *valp) 10879 { 10880 *valp += 2; 10881 return 0; 10882 } 10883 10884 static int 10885 OperandSem_opnd_sem_MR_0_encode (uint32 *valp) 10886 { 10887 int error; 10888 error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0); 10889 *valp = *valp & 1; 10890 return error; 10891 } 10892 10893 static int 10894 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp) 10895 { 10896 unsigned soffsetx4_out_0; 10897 unsigned soffsetx4_in_0; 10898 soffsetx4_in_0 = *valp & 0x3ffff; 10899 soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2); 10900 *valp = soffsetx4_out_0; 10901 return 0; 10902 } 10903 10904 static int 10905 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp) 10906 { 10907 unsigned soffsetx4_in_0; 10908 unsigned soffsetx4_out_0; 10909 soffsetx4_out_0 = *valp; 10910 soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff; 10911 *valp = soffsetx4_in_0; 10912 return 0; 10913 } 10914 10915 static int 10916 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp) 10917 { 10918 unsigned uimm12x8_out_0; 10919 unsigned uimm12x8_in_0; 10920 uimm12x8_in_0 = *valp & 0xfff; 10921 uimm12x8_out_0 = uimm12x8_in_0 << 3; 10922 *valp = uimm12x8_out_0; 10923 return 0; 10924 } 10925 10926 static int 10927 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp) 10928 { 10929 unsigned uimm12x8_in_0; 10930 unsigned uimm12x8_out_0; 10931 uimm12x8_out_0 = *valp; 10932 uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff); 10933 *valp = uimm12x8_in_0; 10934 return 0; 10935 } 10936 10937 static int 10938 OperandSem_opnd_sem_simm4_decode (uint32 *valp) 10939 { 10940 unsigned simm4_out_0; 10941 unsigned simm4_in_0; 10942 simm4_in_0 = *valp & 0xf; 10943 simm4_out_0 = ((int) simm4_in_0 << 28) >> 28; 10944 *valp = simm4_out_0; 10945 return 0; 10946 } 10947 10948 static int 10949 OperandSem_opnd_sem_simm4_encode (uint32 *valp) 10950 { 10951 unsigned simm4_in_0; 10952 unsigned simm4_out_0; 10953 simm4_out_0 = *valp; 10954 simm4_in_0 = (simm4_out_0 & 0xf); 10955 *valp = simm4_in_0; 10956 return 0; 10957 } 10958 10959 static int 10960 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED) 10961 { 10962 return 0; 10963 } 10964 10965 static int 10966 OperandSem_opnd_sem_AR_encode (uint32 *valp) 10967 { 10968 int error; 10969 error = (*valp >= 32); 10970 return error; 10971 } 10972 10973 static int 10974 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED) 10975 { 10976 return 0; 10977 } 10978 10979 static int 10980 OperandSem_opnd_sem_AR_0_encode (uint32 *valp) 10981 { 10982 int error; 10983 error = (*valp >= 32); 10984 return error; 10985 } 10986 10987 static int 10988 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) 10989 { 10990 return 0; 10991 } 10992 10993 static int 10994 OperandSem_opnd_sem_AR_1_encode (uint32 *valp) 10995 { 10996 int error; 10997 error = (*valp >= 32); 10998 return error; 10999 } 11000 11001 static int 11002 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) 11003 { 11004 return 0; 11005 } 11006 11007 static int 11008 OperandSem_opnd_sem_AR_2_encode (uint32 *valp) 11009 { 11010 int error; 11011 error = (*valp >= 32); 11012 return error; 11013 } 11014 11015 static int 11016 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) 11017 { 11018 return 0; 11019 } 11020 11021 static int 11022 OperandSem_opnd_sem_AR_3_encode (uint32 *valp) 11023 { 11024 int error; 11025 error = (*valp >= 32); 11026 return error; 11027 } 11028 11029 static int 11030 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) 11031 { 11032 return 0; 11033 } 11034 11035 static int 11036 OperandSem_opnd_sem_AR_4_encode (uint32 *valp) 11037 { 11038 int error; 11039 error = (*valp >= 32); 11040 return error; 11041 } 11042 11043 static int 11044 OperandSem_opnd_sem_immrx4_decode (uint32 *valp) 11045 { 11046 unsigned immrx4_out_0; 11047 unsigned immrx4_in_0; 11048 immrx4_in_0 = *valp & 0xf; 11049 immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2; 11050 *valp = immrx4_out_0; 11051 return 0; 11052 } 11053 11054 static int 11055 OperandSem_opnd_sem_immrx4_encode (uint32 *valp) 11056 { 11057 unsigned immrx4_in_0; 11058 unsigned immrx4_out_0; 11059 immrx4_out_0 = *valp; 11060 immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf); 11061 *valp = immrx4_in_0; 11062 return 0; 11063 } 11064 11065 static int 11066 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp) 11067 { 11068 unsigned lsi4x4_out_0; 11069 unsigned lsi4x4_in_0; 11070 lsi4x4_in_0 = *valp & 0xf; 11071 lsi4x4_out_0 = lsi4x4_in_0 << 2; 11072 *valp = lsi4x4_out_0; 11073 return 0; 11074 } 11075 11076 static int 11077 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp) 11078 { 11079 unsigned lsi4x4_in_0; 11080 unsigned lsi4x4_out_0; 11081 lsi4x4_out_0 = *valp; 11082 lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf); 11083 *valp = lsi4x4_in_0; 11084 return 0; 11085 } 11086 11087 static int 11088 OperandSem_opnd_sem_simm7_decode (uint32 *valp) 11089 { 11090 unsigned simm7_out_0; 11091 unsigned simm7_in_0; 11092 simm7_in_0 = *valp & 0x7f; 11093 simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0; 11094 *valp = simm7_out_0; 11095 return 0; 11096 } 11097 11098 static int 11099 OperandSem_opnd_sem_simm7_encode (uint32 *valp) 11100 { 11101 unsigned simm7_in_0; 11102 unsigned simm7_out_0; 11103 simm7_out_0 = *valp; 11104 simm7_in_0 = (simm7_out_0 & 0x7f); 11105 *valp = simm7_in_0; 11106 return 0; 11107 } 11108 11109 static int 11110 OperandSem_opnd_sem_uimm6_decode (uint32 *valp) 11111 { 11112 unsigned uimm6_out_0; 11113 unsigned uimm6_in_0; 11114 uimm6_in_0 = *valp & 0x3f; 11115 uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0); 11116 *valp = uimm6_out_0; 11117 return 0; 11118 } 11119 11120 static int 11121 OperandSem_opnd_sem_uimm6_encode (uint32 *valp) 11122 { 11123 unsigned uimm6_in_0; 11124 unsigned uimm6_out_0; 11125 uimm6_out_0 = *valp; 11126 uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f; 11127 *valp = uimm6_in_0; 11128 return 0; 11129 } 11130 11131 static int 11132 OperandSem_opnd_sem_ai4const_decode (uint32 *valp) 11133 { 11134 unsigned ai4const_out_0; 11135 unsigned ai4const_in_0; 11136 ai4const_in_0 = *valp & 0xf; 11137 ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf]; 11138 *valp = ai4const_out_0; 11139 return 0; 11140 } 11141 11142 static int 11143 OperandSem_opnd_sem_ai4const_encode (uint32 *valp) 11144 { 11145 unsigned ai4const_in_0; 11146 unsigned ai4const_out_0; 11147 ai4const_out_0 = *valp; 11148 switch (ai4const_out_0) 11149 { 11150 case 0xffffffff: ai4const_in_0 = 0; break; 11151 case 0x1: ai4const_in_0 = 0x1; break; 11152 case 0x2: ai4const_in_0 = 0x2; break; 11153 case 0x3: ai4const_in_0 = 0x3; break; 11154 case 0x4: ai4const_in_0 = 0x4; break; 11155 case 0x5: ai4const_in_0 = 0x5; break; 11156 case 0x6: ai4const_in_0 = 0x6; break; 11157 case 0x7: ai4const_in_0 = 0x7; break; 11158 case 0x8: ai4const_in_0 = 0x8; break; 11159 case 0x9: ai4const_in_0 = 0x9; break; 11160 case 0xa: ai4const_in_0 = 0xa; break; 11161 case 0xb: ai4const_in_0 = 0xb; break; 11162 case 0xc: ai4const_in_0 = 0xc; break; 11163 case 0xd: ai4const_in_0 = 0xd; break; 11164 case 0xe: ai4const_in_0 = 0xe; break; 11165 default: ai4const_in_0 = 0xf; break; 11166 } 11167 *valp = ai4const_in_0; 11168 return 0; 11169 } 11170 11171 static int 11172 OperandSem_opnd_sem_b4const_decode (uint32 *valp) 11173 { 11174 unsigned b4const_out_0; 11175 unsigned b4const_in_0; 11176 b4const_in_0 = *valp & 0xf; 11177 b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf]; 11178 *valp = b4const_out_0; 11179 return 0; 11180 } 11181 11182 static int 11183 OperandSem_opnd_sem_b4const_encode (uint32 *valp) 11184 { 11185 unsigned b4const_in_0; 11186 unsigned b4const_out_0; 11187 b4const_out_0 = *valp; 11188 switch (b4const_out_0) 11189 { 11190 case 0xffffffff: b4const_in_0 = 0; break; 11191 case 0x1: b4const_in_0 = 0x1; break; 11192 case 0x2: b4const_in_0 = 0x2; break; 11193 case 0x3: b4const_in_0 = 0x3; break; 11194 case 0x4: b4const_in_0 = 0x4; break; 11195 case 0x5: b4const_in_0 = 0x5; break; 11196 case 0x6: b4const_in_0 = 0x6; break; 11197 case 0x7: b4const_in_0 = 0x7; break; 11198 case 0x8: b4const_in_0 = 0x8; break; 11199 case 0xa: b4const_in_0 = 0x9; break; 11200 case 0xc: b4const_in_0 = 0xa; break; 11201 case 0x10: b4const_in_0 = 0xb; break; 11202 case 0x20: b4const_in_0 = 0xc; break; 11203 case 0x40: b4const_in_0 = 0xd; break; 11204 case 0x80: b4const_in_0 = 0xe; break; 11205 default: b4const_in_0 = 0xf; break; 11206 } 11207 *valp = b4const_in_0; 11208 return 0; 11209 } 11210 11211 static int 11212 OperandSem_opnd_sem_b4constu_decode (uint32 *valp) 11213 { 11214 unsigned b4constu_out_0; 11215 unsigned b4constu_in_0; 11216 b4constu_in_0 = *valp & 0xf; 11217 b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf]; 11218 *valp = b4constu_out_0; 11219 return 0; 11220 } 11221 11222 static int 11223 OperandSem_opnd_sem_b4constu_encode (uint32 *valp) 11224 { 11225 unsigned b4constu_in_0; 11226 unsigned b4constu_out_0; 11227 b4constu_out_0 = *valp; 11228 switch (b4constu_out_0) 11229 { 11230 case 0x8000: b4constu_in_0 = 0; break; 11231 case 0x10000: b4constu_in_0 = 0x1; break; 11232 case 0x2: b4constu_in_0 = 0x2; break; 11233 case 0x3: b4constu_in_0 = 0x3; break; 11234 case 0x4: b4constu_in_0 = 0x4; break; 11235 case 0x5: b4constu_in_0 = 0x5; break; 11236 case 0x6: b4constu_in_0 = 0x6; break; 11237 case 0x7: b4constu_in_0 = 0x7; break; 11238 case 0x8: b4constu_in_0 = 0x8; break; 11239 case 0xa: b4constu_in_0 = 0x9; break; 11240 case 0xc: b4constu_in_0 = 0xa; break; 11241 case 0x10: b4constu_in_0 = 0xb; break; 11242 case 0x20: b4constu_in_0 = 0xc; break; 11243 case 0x40: b4constu_in_0 = 0xd; break; 11244 case 0x80: b4constu_in_0 = 0xe; break; 11245 default: b4constu_in_0 = 0xf; break; 11246 } 11247 *valp = b4constu_in_0; 11248 return 0; 11249 } 11250 11251 static int 11252 OperandSem_opnd_sem_uimm8_decode (uint32 *valp) 11253 { 11254 unsigned uimm8_out_0; 11255 unsigned uimm8_in_0; 11256 uimm8_in_0 = *valp & 0xff; 11257 uimm8_out_0 = uimm8_in_0; 11258 *valp = uimm8_out_0; 11259 return 0; 11260 } 11261 11262 static int 11263 OperandSem_opnd_sem_uimm8_encode (uint32 *valp) 11264 { 11265 unsigned uimm8_in_0; 11266 unsigned uimm8_out_0; 11267 uimm8_out_0 = *valp; 11268 uimm8_in_0 = (uimm8_out_0 & 0xff); 11269 *valp = uimm8_in_0; 11270 return 0; 11271 } 11272 11273 static int 11274 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp) 11275 { 11276 unsigned uimm8x2_out_0; 11277 unsigned uimm8x2_in_0; 11278 uimm8x2_in_0 = *valp & 0xff; 11279 uimm8x2_out_0 = uimm8x2_in_0 << 1; 11280 *valp = uimm8x2_out_0; 11281 return 0; 11282 } 11283 11284 static int 11285 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp) 11286 { 11287 unsigned uimm8x2_in_0; 11288 unsigned uimm8x2_out_0; 11289 uimm8x2_out_0 = *valp; 11290 uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff); 11291 *valp = uimm8x2_in_0; 11292 return 0; 11293 } 11294 11295 static int 11296 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp) 11297 { 11298 unsigned uimm8x4_out_0; 11299 unsigned uimm8x4_in_0; 11300 uimm8x4_in_0 = *valp & 0xff; 11301 uimm8x4_out_0 = uimm8x4_in_0 << 2; 11302 *valp = uimm8x4_out_0; 11303 return 0; 11304 } 11305 11306 static int 11307 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp) 11308 { 11309 unsigned uimm8x4_in_0; 11310 unsigned uimm8x4_out_0; 11311 uimm8x4_out_0 = *valp; 11312 uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff); 11313 *valp = uimm8x4_in_0; 11314 return 0; 11315 } 11316 11317 static int 11318 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp) 11319 { 11320 unsigned uimm4x16_out_0; 11321 unsigned uimm4x16_in_0; 11322 uimm4x16_in_0 = *valp & 0xf; 11323 uimm4x16_out_0 = uimm4x16_in_0 << 4; 11324 *valp = uimm4x16_out_0; 11325 return 0; 11326 } 11327 11328 static int 11329 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp) 11330 { 11331 unsigned uimm4x16_in_0; 11332 unsigned uimm4x16_out_0; 11333 uimm4x16_out_0 = *valp; 11334 uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf); 11335 *valp = uimm4x16_in_0; 11336 return 0; 11337 } 11338 11339 static int 11340 OperandSem_opnd_sem_simm8_decode (uint32 *valp) 11341 { 11342 unsigned simm8_out_0; 11343 unsigned simm8_in_0; 11344 simm8_in_0 = *valp & 0xff; 11345 simm8_out_0 = ((int) simm8_in_0 << 24) >> 24; 11346 *valp = simm8_out_0; 11347 return 0; 11348 } 11349 11350 static int 11351 OperandSem_opnd_sem_simm8_encode (uint32 *valp) 11352 { 11353 unsigned simm8_in_0; 11354 unsigned simm8_out_0; 11355 simm8_out_0 = *valp; 11356 simm8_in_0 = (simm8_out_0 & 0xff); 11357 *valp = simm8_in_0; 11358 return 0; 11359 } 11360 11361 static int 11362 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp) 11363 { 11364 unsigned simm8x256_out_0; 11365 unsigned simm8x256_in_0; 11366 simm8x256_in_0 = *valp & 0xff; 11367 simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8; 11368 *valp = simm8x256_out_0; 11369 return 0; 11370 } 11371 11372 static int 11373 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp) 11374 { 11375 unsigned simm8x256_in_0; 11376 unsigned simm8x256_out_0; 11377 simm8x256_out_0 = *valp; 11378 simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff); 11379 *valp = simm8x256_in_0; 11380 return 0; 11381 } 11382 11383 static int 11384 OperandSem_opnd_sem_simm12b_decode (uint32 *valp) 11385 { 11386 unsigned simm12b_out_0; 11387 unsigned simm12b_in_0; 11388 simm12b_in_0 = *valp & 0xfff; 11389 simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20; 11390 *valp = simm12b_out_0; 11391 return 0; 11392 } 11393 11394 static int 11395 OperandSem_opnd_sem_simm12b_encode (uint32 *valp) 11396 { 11397 unsigned simm12b_in_0; 11398 unsigned simm12b_out_0; 11399 simm12b_out_0 = *valp; 11400 simm12b_in_0 = (simm12b_out_0 & 0xfff); 11401 *valp = simm12b_in_0; 11402 return 0; 11403 } 11404 11405 static int 11406 OperandSem_opnd_sem_msalp32_decode (uint32 *valp) 11407 { 11408 unsigned msalp32_out_0; 11409 unsigned msalp32_in_0; 11410 msalp32_in_0 = *valp & 0x1f; 11411 msalp32_out_0 = 0x20 - msalp32_in_0; 11412 *valp = msalp32_out_0; 11413 return 0; 11414 } 11415 11416 static int 11417 OperandSem_opnd_sem_msalp32_encode (uint32 *valp) 11418 { 11419 unsigned msalp32_in_0; 11420 unsigned msalp32_out_0; 11421 msalp32_out_0 = *valp; 11422 msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f; 11423 *valp = msalp32_in_0; 11424 return 0; 11425 } 11426 11427 static int 11428 OperandSem_opnd_sem_op2p1_decode (uint32 *valp) 11429 { 11430 unsigned op2p1_out_0; 11431 unsigned op2p1_in_0; 11432 op2p1_in_0 = *valp & 0xf; 11433 op2p1_out_0 = op2p1_in_0 + 0x1; 11434 *valp = op2p1_out_0; 11435 return 0; 11436 } 11437 11438 static int 11439 OperandSem_opnd_sem_op2p1_encode (uint32 *valp) 11440 { 11441 unsigned op2p1_in_0; 11442 unsigned op2p1_out_0; 11443 op2p1_out_0 = *valp; 11444 op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf; 11445 *valp = op2p1_in_0; 11446 return 0; 11447 } 11448 11449 static int 11450 OperandSem_opnd_sem_label8_decode (uint32 *valp) 11451 { 11452 unsigned label8_out_0; 11453 unsigned label8_in_0; 11454 label8_in_0 = *valp & 0xff; 11455 label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24); 11456 *valp = label8_out_0; 11457 return 0; 11458 } 11459 11460 static int 11461 OperandSem_opnd_sem_label8_encode (uint32 *valp) 11462 { 11463 unsigned label8_in_0; 11464 unsigned label8_out_0; 11465 label8_out_0 = *valp; 11466 label8_in_0 = (label8_out_0 - 0x4) & 0xff; 11467 *valp = label8_in_0; 11468 return 0; 11469 } 11470 11471 static int 11472 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp) 11473 { 11474 unsigned ulabel8_out_0; 11475 unsigned ulabel8_in_0; 11476 ulabel8_in_0 = *valp & 0xff; 11477 ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0); 11478 *valp = ulabel8_out_0; 11479 return 0; 11480 } 11481 11482 static int 11483 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp) 11484 { 11485 unsigned ulabel8_in_0; 11486 unsigned ulabel8_out_0; 11487 ulabel8_out_0 = *valp; 11488 ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff; 11489 *valp = ulabel8_in_0; 11490 return 0; 11491 } 11492 11493 static int 11494 OperandSem_opnd_sem_label12_decode (uint32 *valp) 11495 { 11496 unsigned label12_out_0; 11497 unsigned label12_in_0; 11498 label12_in_0 = *valp & 0xfff; 11499 label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20); 11500 *valp = label12_out_0; 11501 return 0; 11502 } 11503 11504 static int 11505 OperandSem_opnd_sem_label12_encode (uint32 *valp) 11506 { 11507 unsigned label12_in_0; 11508 unsigned label12_out_0; 11509 label12_out_0 = *valp; 11510 label12_in_0 = (label12_out_0 - 0x4) & 0xfff; 11511 *valp = label12_in_0; 11512 return 0; 11513 } 11514 11515 static int 11516 OperandSem_opnd_sem_soffset_decode (uint32 *valp) 11517 { 11518 unsigned soffset_out_0; 11519 unsigned soffset_in_0; 11520 soffset_in_0 = *valp & 0x3ffff; 11521 soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14); 11522 *valp = soffset_out_0; 11523 return 0; 11524 } 11525 11526 static int 11527 OperandSem_opnd_sem_soffset_encode (uint32 *valp) 11528 { 11529 unsigned soffset_in_0; 11530 unsigned soffset_out_0; 11531 soffset_out_0 = *valp; 11532 soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff; 11533 *valp = soffset_in_0; 11534 return 0; 11535 } 11536 11537 static int 11538 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp) 11539 { 11540 unsigned uimm16x4_out_0; 11541 unsigned uimm16x4_in_0; 11542 uimm16x4_in_0 = *valp & 0xffff; 11543 uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2; 11544 *valp = uimm16x4_out_0; 11545 return 0; 11546 } 11547 11548 static int 11549 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp) 11550 { 11551 unsigned uimm16x4_in_0; 11552 unsigned uimm16x4_out_0; 11553 uimm16x4_out_0 = *valp; 11554 uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff; 11555 *valp = uimm16x4_in_0; 11556 return 0; 11557 } 11558 11559 static int 11560 OperandSem_opnd_sem_bbi_decode (uint32 *valp) 11561 { 11562 unsigned bbi_out_0; 11563 unsigned bbi_in_0; 11564 bbi_in_0 = *valp & 0x1f; 11565 bbi_out_0 = (0 << 5) | bbi_in_0; 11566 *valp = bbi_out_0; 11567 return 0; 11568 } 11569 11570 static int 11571 OperandSem_opnd_sem_bbi_encode (uint32 *valp) 11572 { 11573 unsigned bbi_in_0; 11574 unsigned bbi_out_0; 11575 bbi_out_0 = *valp; 11576 bbi_in_0 = (bbi_out_0 & 0x1f); 11577 *valp = bbi_in_0; 11578 return 0; 11579 } 11580 11581 static int 11582 OperandSem_opnd_sem_s_decode (uint32 *valp) 11583 { 11584 unsigned s_out_0; 11585 unsigned s_in_0; 11586 s_in_0 = *valp & 0xf; 11587 s_out_0 = (0 << 4) | s_in_0; 11588 *valp = s_out_0; 11589 return 0; 11590 } 11591 11592 static int 11593 OperandSem_opnd_sem_s_encode (uint32 *valp) 11594 { 11595 unsigned s_in_0; 11596 unsigned s_out_0; 11597 s_out_0 = *valp; 11598 s_in_0 = (s_out_0 & 0xf); 11599 *valp = s_in_0; 11600 return 0; 11601 } 11602 11603 static int 11604 OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED) 11605 { 11606 return 0; 11607 } 11608 11609 static int 11610 OperandSem_opnd_sem_MR_encode (uint32 *valp) 11611 { 11612 int error; 11613 error = (*valp >= 4); 11614 return error; 11615 } 11616 11617 static int 11618 OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED) 11619 { 11620 return 0; 11621 } 11622 11623 static int 11624 OperandSem_opnd_sem_MR_1_encode (uint32 *valp) 11625 { 11626 int error; 11627 error = (*valp >= 4); 11628 return error; 11629 } 11630 11631 static int 11632 OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED) 11633 { 11634 return 0; 11635 } 11636 11637 static int 11638 OperandSem_opnd_sem_MR_2_encode (uint32 *valp) 11639 { 11640 int error; 11641 error = (*valp >= 4); 11642 return error; 11643 } 11644 11645 static int 11646 OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED) 11647 { 11648 return 0; 11649 } 11650 11651 static int 11652 OperandSem_opnd_sem_MR_3_encode (uint32 *valp) 11653 { 11654 int error; 11655 error = (*valp >= 4); 11656 return error; 11657 } 11658 11659 static int 11660 OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED) 11661 { 11662 return 0; 11663 } 11664 11665 static int 11666 OperandSem_opnd_sem_MR_4_encode (uint32 *valp) 11667 { 11668 int error; 11669 error = (*valp >= 4); 11670 return error; 11671 } 11672 11673 static int 11674 OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED) 11675 { 11676 return 0; 11677 } 11678 11679 static int 11680 OperandSem_opnd_sem_MR_5_encode (uint32 *valp) 11681 { 11682 int error; 11683 error = (*valp >= 4); 11684 return error; 11685 } 11686 11687 static int 11688 OperandSem_opnd_sem_immt_decode (uint32 *valp) 11689 { 11690 unsigned immt_out_0; 11691 unsigned immt_in_0; 11692 immt_in_0 = *valp & 0xf; 11693 immt_out_0 = immt_in_0; 11694 *valp = immt_out_0; 11695 return 0; 11696 } 11697 11698 static int 11699 OperandSem_opnd_sem_immt_encode (uint32 *valp) 11700 { 11701 unsigned immt_in_0; 11702 unsigned immt_out_0; 11703 immt_out_0 = *valp; 11704 immt_in_0 = immt_out_0 & 0xf; 11705 *valp = immt_in_0; 11706 return 0; 11707 } 11708 11709 static int 11710 OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED) 11711 { 11712 return 0; 11713 } 11714 11715 static int 11716 OperandSem_opnd_sem_BR_encode (uint32 *valp) 11717 { 11718 int error; 11719 error = (*valp >= 16); 11720 return error; 11721 } 11722 11723 static int 11724 OperandSem_opnd_sem_BR2_decode (uint32 *valp) 11725 { 11726 *valp = *valp << 1; 11727 return 0; 11728 } 11729 11730 static int 11731 OperandSem_opnd_sem_BR2_encode (uint32 *valp) 11732 { 11733 int error; 11734 error = (*valp >= 16) || ((*valp & 1) != 0); 11735 *valp = *valp >> 1; 11736 return error; 11737 } 11738 11739 static int 11740 OperandSem_opnd_sem_BR4_decode (uint32 *valp) 11741 { 11742 *valp = *valp << 2; 11743 return 0; 11744 } 11745 11746 static int 11747 OperandSem_opnd_sem_BR4_encode (uint32 *valp) 11748 { 11749 int error; 11750 error = (*valp >= 16) || ((*valp & 3) != 0); 11751 *valp = *valp >> 2; 11752 return error; 11753 } 11754 11755 static int 11756 OperandSem_opnd_sem_BR8_decode (uint32 *valp) 11757 { 11758 *valp = *valp << 3; 11759 return 0; 11760 } 11761 11762 static int 11763 OperandSem_opnd_sem_BR8_encode (uint32 *valp) 11764 { 11765 int error; 11766 error = (*valp >= 16) || ((*valp & 7) != 0); 11767 *valp = *valp >> 3; 11768 return error; 11769 } 11770 11771 static int 11772 OperandSem_opnd_sem_BR16_decode (uint32 *valp) 11773 { 11774 *valp = *valp << 4; 11775 return 0; 11776 } 11777 11778 static int 11779 OperandSem_opnd_sem_BR16_encode (uint32 *valp) 11780 { 11781 int error; 11782 error = (*valp >= 16) || ((*valp & 15) != 0); 11783 *valp = *valp >> 4; 11784 return error; 11785 } 11786 11787 static int 11788 OperandSem_opnd_sem_tp7_decode (uint32 *valp) 11789 { 11790 unsigned tp7_out_0; 11791 unsigned tp7_in_0; 11792 tp7_in_0 = *valp & 0xf; 11793 tp7_out_0 = tp7_in_0 + 0x7; 11794 *valp = tp7_out_0; 11795 return 0; 11796 } 11797 11798 static int 11799 OperandSem_opnd_sem_tp7_encode (uint32 *valp) 11800 { 11801 unsigned tp7_in_0; 11802 unsigned tp7_out_0; 11803 tp7_out_0 = *valp; 11804 tp7_in_0 = (tp7_out_0 - 0x7) & 0xf; 11805 *valp = tp7_in_0; 11806 return 0; 11807 } 11808 11809 static int 11810 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp) 11811 { 11812 unsigned xt_wbr15_label_out_0; 11813 unsigned xt_wbr15_label_in_0; 11814 xt_wbr15_label_in_0 = *valp & 0x7fff; 11815 xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17); 11816 *valp = xt_wbr15_label_out_0; 11817 return 0; 11818 } 11819 11820 static int 11821 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp) 11822 { 11823 unsigned xt_wbr15_label_in_0; 11824 unsigned xt_wbr15_label_out_0; 11825 xt_wbr15_label_out_0 = *valp; 11826 xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff; 11827 *valp = xt_wbr15_label_in_0; 11828 return 0; 11829 } 11830 11831 static int 11832 OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp) 11833 { 11834 unsigned ae_samt32_out_0; 11835 unsigned ae_samt32_in_0; 11836 ae_samt32_in_0 = *valp & 0x1f; 11837 ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0; 11838 *valp = ae_samt32_out_0; 11839 return 0; 11840 } 11841 11842 static int 11843 OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp) 11844 { 11845 unsigned ae_samt32_in_0; 11846 unsigned ae_samt32_out_0; 11847 ae_samt32_out_0 = *valp; 11848 ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f); 11849 *valp = ae_samt32_in_0; 11850 return 0; 11851 } 11852 11853 static int 11854 OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED) 11855 { 11856 return 0; 11857 } 11858 11859 static int 11860 OperandSem_opnd_sem_AE_PR_encode (uint32 *valp) 11861 { 11862 int error; 11863 error = (*valp >= 8); 11864 return error; 11865 } 11866 11867 static int 11868 OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED) 11869 { 11870 return 0; 11871 } 11872 11873 static int 11874 OperandSem_opnd_sem_AE_QR_encode (uint32 *valp) 11875 { 11876 int error; 11877 error = (*valp >= 4); 11878 return error; 11879 } 11880 11881 static int 11882 OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp) 11883 { 11884 unsigned ae_lsimm16_out_0; 11885 unsigned ae_lsimm16_in_0; 11886 ae_lsimm16_in_0 = *valp & 0xf; 11887 ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1; 11888 *valp = ae_lsimm16_out_0; 11889 return 0; 11890 } 11891 11892 static int 11893 OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp) 11894 { 11895 unsigned ae_lsimm16_in_0; 11896 unsigned ae_lsimm16_out_0; 11897 ae_lsimm16_out_0 = *valp; 11898 ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf); 11899 *valp = ae_lsimm16_in_0; 11900 return 0; 11901 } 11902 11903 static int 11904 OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp) 11905 { 11906 unsigned ae_lsimm32_out_0; 11907 unsigned ae_lsimm32_in_0; 11908 ae_lsimm32_in_0 = *valp & 0xf; 11909 ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2; 11910 *valp = ae_lsimm32_out_0; 11911 return 0; 11912 } 11913 11914 static int 11915 OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp) 11916 { 11917 unsigned ae_lsimm32_in_0; 11918 unsigned ae_lsimm32_out_0; 11919 ae_lsimm32_out_0 = *valp; 11920 ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf); 11921 *valp = ae_lsimm32_in_0; 11922 return 0; 11923 } 11924 11925 static int 11926 OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp) 11927 { 11928 unsigned ae_lsimm64_out_0; 11929 unsigned ae_lsimm64_in_0; 11930 ae_lsimm64_in_0 = *valp & 0xf; 11931 ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3; 11932 *valp = ae_lsimm64_out_0; 11933 return 0; 11934 } 11935 11936 static int 11937 OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp) 11938 { 11939 unsigned ae_lsimm64_in_0; 11940 unsigned ae_lsimm64_out_0; 11941 ae_lsimm64_out_0 = *valp; 11942 ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf); 11943 *valp = ae_lsimm64_in_0; 11944 return 0; 11945 } 11946 11947 static int 11948 OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp) 11949 { 11950 unsigned ae_samt64_out_0; 11951 unsigned ae_samt64_in_0; 11952 ae_samt64_in_0 = *valp & 0x3f; 11953 ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0; 11954 *valp = ae_samt64_out_0; 11955 return 0; 11956 } 11957 11958 static int 11959 OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp) 11960 { 11961 unsigned ae_samt64_in_0; 11962 unsigned ae_samt64_out_0; 11963 ae_samt64_out_0 = *valp; 11964 ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f); 11965 *valp = ae_samt64_in_0; 11966 return 0; 11967 } 11968 11969 static int 11970 OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp) 11971 { 11972 unsigned ae_ohba_out_0; 11973 unsigned ae_ohba_in_0; 11974 ae_ohba_in_0 = *valp & 0xf; 11975 ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf)); 11976 *valp = ae_ohba_out_0; 11977 return 0; 11978 } 11979 11980 static int 11981 OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp) 11982 { 11983 unsigned ae_ohba_in_0; 11984 unsigned ae_ohba_out_0; 11985 ae_ohba_out_0 = *valp; 11986 ae_ohba_in_0 = (ae_ohba_out_0 & 0xf); 11987 *valp = ae_ohba_in_0; 11988 return 0; 11989 } 11990 11991 static int 11992 Operand_soffsetx4_ator (uint32 *valp, uint32 pc) 11993 { 11994 *valp -= (pc & ~0x3); 11995 return 0; 11996 } 11997 11998 static int 11999 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc) 12000 { 12001 *valp += (pc & ~0x3); 12002 return 0; 12003 } 12004 12005 static int 12006 Operand_uimm6_ator (uint32 *valp, uint32 pc) 12007 { 12008 *valp -= pc; 12009 return 0; 12010 } 12011 12012 static int 12013 Operand_uimm6_rtoa (uint32 *valp, uint32 pc) 12014 { 12015 *valp += pc; 12016 return 0; 12017 } 12018 12019 static int 12020 Operand_label8_ator (uint32 *valp, uint32 pc) 12021 { 12022 *valp -= pc; 12023 return 0; 12024 } 12025 12026 static int 12027 Operand_label8_rtoa (uint32 *valp, uint32 pc) 12028 { 12029 *valp += pc; 12030 return 0; 12031 } 12032 12033 static int 12034 Operand_ulabel8_ator (uint32 *valp, uint32 pc) 12035 { 12036 *valp -= pc; 12037 return 0; 12038 } 12039 12040 static int 12041 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc) 12042 { 12043 *valp += pc; 12044 return 0; 12045 } 12046 12047 static int 12048 Operand_label12_ator (uint32 *valp, uint32 pc) 12049 { 12050 *valp -= pc; 12051 return 0; 12052 } 12053 12054 static int 12055 Operand_label12_rtoa (uint32 *valp, uint32 pc) 12056 { 12057 *valp += pc; 12058 return 0; 12059 } 12060 12061 static int 12062 Operand_soffset_ator (uint32 *valp, uint32 pc) 12063 { 12064 *valp -= pc; 12065 return 0; 12066 } 12067 12068 static int 12069 Operand_soffset_rtoa (uint32 *valp, uint32 pc) 12070 { 12071 *valp += pc; 12072 return 0; 12073 } 12074 12075 static int 12076 Operand_uimm16x4_ator (uint32 *valp, uint32 pc) 12077 { 12078 *valp -= ((pc + 3) & ~0x3); 12079 return 0; 12080 } 12081 12082 static int 12083 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc) 12084 { 12085 *valp += ((pc + 3) & ~0x3); 12086 return 0; 12087 } 12088 12089 static int 12090 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc) 12091 { 12092 *valp -= pc; 12093 return 0; 12094 } 12095 12096 static int 12097 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc) 12098 { 12099 *valp += pc; 12100 return 0; 12101 } 12102 12103 static int 12104 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc) 12105 { 12106 *valp -= pc; 12107 return 0; 12108 } 12109 12110 static int 12111 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc) 12112 { 12113 *valp += pc; 12114 return 0; 12115 } 12116 12117 static xtensa_operand_internal operands[] = { 12118 { "soffsetx4", FIELD_offset, -1, 0, 12119 XTENSA_OPERAND_IS_PCRELATIVE, 12120 OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode, 12121 Operand_soffsetx4_ator, Operand_soffsetx4_rtoa }, 12122 { "uimm12x8", FIELD_imm12, -1, 0, 12123 0, 12124 OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode, 12125 0, 0 }, 12126 { "simm4", FIELD_mn, -1, 0, 12127 0, 12128 OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode, 12129 0, 0 }, 12130 { "arr", FIELD_r, REGFILE_AR, 1, 12131 XTENSA_OPERAND_IS_REGISTER, 12132 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 12133 0, 0 }, 12134 { "ars", FIELD_s, REGFILE_AR, 1, 12135 XTENSA_OPERAND_IS_REGISTER, 12136 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 12137 0, 0 }, 12138 { "*ars_invisible", FIELD_s, REGFILE_AR, 1, 12139 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12140 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 12141 0, 0 }, 12142 { "art", FIELD_t, REGFILE_AR, 1, 12143 XTENSA_OPERAND_IS_REGISTER, 12144 OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode, 12145 0, 0 }, 12146 { "ar0", FIELD__ar0, REGFILE_AR, 1, 12147 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12148 OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode, 12149 0, 0 }, 12150 { "ar4", FIELD__ar4, REGFILE_AR, 1, 12151 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12152 OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode, 12153 0, 0 }, 12154 { "ar8", FIELD__ar8, REGFILE_AR, 1, 12155 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12156 OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode, 12157 0, 0 }, 12158 { "ar12", FIELD__ar12, REGFILE_AR, 1, 12159 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12160 OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode, 12161 0, 0 }, 12162 { "ars_entry", FIELD_s, REGFILE_AR, 1, 12163 XTENSA_OPERAND_IS_REGISTER, 12164 OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode, 12165 0, 0 }, 12166 { "immrx4", FIELD_r, -1, 0, 12167 0, 12168 OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode, 12169 0, 0 }, 12170 { "lsi4x4", FIELD_r, -1, 0, 12171 0, 12172 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, 12173 0, 0 }, 12174 { "simm7", FIELD_imm7, -1, 0, 12175 0, 12176 OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode, 12177 0, 0 }, 12178 { "uimm6", FIELD_imm6, -1, 0, 12179 XTENSA_OPERAND_IS_PCRELATIVE, 12180 OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode, 12181 Operand_uimm6_ator, Operand_uimm6_rtoa }, 12182 { "ai4const", FIELD_t, -1, 0, 12183 0, 12184 OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode, 12185 0, 0 }, 12186 { "b4const", FIELD_r, -1, 0, 12187 0, 12188 OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode, 12189 0, 0 }, 12190 { "b4constu", FIELD_r, -1, 0, 12191 0, 12192 OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode, 12193 0, 0 }, 12194 { "uimm8", FIELD_imm8, -1, 0, 12195 0, 12196 OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode, 12197 0, 0 }, 12198 { "uimm8x2", FIELD_imm8, -1, 0, 12199 0, 12200 OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode, 12201 0, 0 }, 12202 { "uimm8x4", FIELD_imm8, -1, 0, 12203 0, 12204 OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode, 12205 0, 0 }, 12206 { "uimm4x16", FIELD_op2, -1, 0, 12207 0, 12208 OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode, 12209 0, 0 }, 12210 { "uimmrx4", FIELD_r, -1, 0, 12211 0, 12212 OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode, 12213 0, 0 }, 12214 { "simm8", FIELD_imm8, -1, 0, 12215 0, 12216 OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode, 12217 0, 0 }, 12218 { "simm8x256", FIELD_imm8, -1, 0, 12219 0, 12220 OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode, 12221 0, 0 }, 12222 { "simm12b", FIELD_imm12b, -1, 0, 12223 0, 12224 OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode, 12225 0, 0 }, 12226 { "msalp32", FIELD_sal, -1, 0, 12227 0, 12228 OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode, 12229 0, 0 }, 12230 { "op2p1", FIELD_op2, -1, 0, 12231 0, 12232 OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode, 12233 0, 0 }, 12234 { "label8", FIELD_imm8, -1, 0, 12235 XTENSA_OPERAND_IS_PCRELATIVE, 12236 OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode, 12237 Operand_label8_ator, Operand_label8_rtoa }, 12238 { "ulabel8", FIELD_imm8, -1, 0, 12239 XTENSA_OPERAND_IS_PCRELATIVE, 12240 OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode, 12241 Operand_ulabel8_ator, Operand_ulabel8_rtoa }, 12242 { "label12", FIELD_imm12, -1, 0, 12243 XTENSA_OPERAND_IS_PCRELATIVE, 12244 OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode, 12245 Operand_label12_ator, Operand_label12_rtoa }, 12246 { "soffset", FIELD_offset, -1, 0, 12247 XTENSA_OPERAND_IS_PCRELATIVE, 12248 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, 12249 Operand_soffset_ator, Operand_soffset_rtoa }, 12250 { "uimm16x4", FIELD_imm16, -1, 0, 12251 XTENSA_OPERAND_IS_PCRELATIVE, 12252 OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode, 12253 Operand_uimm16x4_ator, Operand_uimm16x4_rtoa }, 12254 { "bbi", FIELD_bbi, -1, 0, 12255 0, 12256 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 12257 0, 0 }, 12258 { "sae", FIELD_sae, -1, 0, 12259 0, 12260 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 12261 0, 0 }, 12262 { "sas", FIELD_sas, -1, 0, 12263 0, 12264 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 12265 0, 0 }, 12266 { "sargt", FIELD_sargt, -1, 0, 12267 0, 12268 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 12269 0, 0 }, 12270 { "s", FIELD_s, -1, 0, 12271 0, 12272 OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode, 12273 0, 0 }, 12274 { "mx", FIELD_x, REGFILE_MR, 1, 12275 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 12276 OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode, 12277 0, 0 }, 12278 { "my", FIELD_y, REGFILE_MR, 1, 12279 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN, 12280 OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode, 12281 0, 0 }, 12282 { "mw", FIELD_w, REGFILE_MR, 1, 12283 XTENSA_OPERAND_IS_REGISTER, 12284 OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode, 12285 0, 0 }, 12286 { "mr0", FIELD__mr0, REGFILE_MR, 1, 12287 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12288 OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode, 12289 0, 0 }, 12290 { "mr1", FIELD__mr1, REGFILE_MR, 1, 12291 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12292 OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode, 12293 0, 0 }, 12294 { "mr2", FIELD__mr2, REGFILE_MR, 1, 12295 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12296 OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode, 12297 0, 0 }, 12298 { "mr3", FIELD__mr3, REGFILE_MR, 1, 12299 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12300 OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode, 12301 0, 0 }, 12302 { "immt", FIELD_t, -1, 0, 12303 0, 12304 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 12305 0, 0 }, 12306 { "imms", FIELD_s, -1, 0, 12307 0, 12308 OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode, 12309 0, 0 }, 12310 { "bt", FIELD_t, REGFILE_BR, 1, 12311 XTENSA_OPERAND_IS_REGISTER, 12312 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 12313 0, 0 }, 12314 { "bs", FIELD_s, REGFILE_BR, 1, 12315 XTENSA_OPERAND_IS_REGISTER, 12316 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 12317 0, 0 }, 12318 { "br", FIELD_r, REGFILE_BR, 1, 12319 XTENSA_OPERAND_IS_REGISTER, 12320 OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode, 12321 0, 0 }, 12322 { "bt2", FIELD_t2, REGFILE_BR, 2, 12323 XTENSA_OPERAND_IS_REGISTER, 12324 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 12325 0, 0 }, 12326 { "bs2", FIELD_s2, REGFILE_BR, 2, 12327 XTENSA_OPERAND_IS_REGISTER, 12328 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 12329 0, 0 }, 12330 { "br2", FIELD_r2, REGFILE_BR, 2, 12331 XTENSA_OPERAND_IS_REGISTER, 12332 OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode, 12333 0, 0 }, 12334 { "bt4", FIELD_t4, REGFILE_BR, 4, 12335 XTENSA_OPERAND_IS_REGISTER, 12336 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 12337 0, 0 }, 12338 { "bs4", FIELD_s4, REGFILE_BR, 4, 12339 XTENSA_OPERAND_IS_REGISTER, 12340 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 12341 0, 0 }, 12342 { "br4", FIELD_r4, REGFILE_BR, 4, 12343 XTENSA_OPERAND_IS_REGISTER, 12344 OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode, 12345 0, 0 }, 12346 { "bt8", FIELD_t8, REGFILE_BR, 8, 12347 XTENSA_OPERAND_IS_REGISTER, 12348 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 12349 0, 0 }, 12350 { "bs8", FIELD_s8, REGFILE_BR, 8, 12351 XTENSA_OPERAND_IS_REGISTER, 12352 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 12353 0, 0 }, 12354 { "br8", FIELD_r8, REGFILE_BR, 8, 12355 XTENSA_OPERAND_IS_REGISTER, 12356 OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode, 12357 0, 0 }, 12358 { "bt16", FIELD__bt16, REGFILE_BR, 16, 12359 XTENSA_OPERAND_IS_REGISTER, 12360 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 12361 0, 0 }, 12362 { "bs16", FIELD__bs16, REGFILE_BR, 16, 12363 XTENSA_OPERAND_IS_REGISTER, 12364 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 12365 0, 0 }, 12366 { "br16", FIELD__br16, REGFILE_BR, 16, 12367 XTENSA_OPERAND_IS_REGISTER, 12368 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 12369 0, 0 }, 12370 { "brall", FIELD__brall, REGFILE_BR, 16, 12371 XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE, 12372 OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode, 12373 0, 0 }, 12374 { "tp7", FIELD_t, -1, 0, 12375 0, 12376 OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode, 12377 0, 0 }, 12378 { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0, 12379 XTENSA_OPERAND_IS_PCRELATIVE, 12380 OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode, 12381 Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa }, 12382 { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0, 12383 XTENSA_OPERAND_IS_PCRELATIVE, 12384 OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode, 12385 Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa }, 12386 { "ae_samt32", FIELD_ftsf13, -1, 0, 12387 0, 12388 OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode, 12389 0, 0 }, 12390 { "pr0", FIELD_ftsf11, REGFILE_AE_PR, 1, 12391 XTENSA_OPERAND_IS_REGISTER, 12392 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 12393 0, 0 }, 12394 { "qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, 12395 XTENSA_OPERAND_IS_REGISTER, 12396 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12397 0, 0 }, 12398 { "mac_qr0", FIELD_ftsf12, REGFILE_AE_QR, 1, 12399 XTENSA_OPERAND_IS_REGISTER, 12400 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12401 0, 0 }, 12402 { "ae_lsimm16", FIELD_t, -1, 0, 12403 0, 12404 OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode, 12405 0, 0 }, 12406 { "ae_lsimm32", FIELD_t, -1, 0, 12407 0, 12408 OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode, 12409 0, 0 }, 12410 { "ae_lsimm64", FIELD_t, -1, 0, 12411 0, 12412 OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode, 12413 0, 0 }, 12414 { "ae_samt64", FIELD_ae_samt_s_t, -1, 0, 12415 0, 12416 OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode, 12417 0, 0 }, 12418 { "ae_ohba", FIELD_ae_fld_ohba, -1, 0, 12419 0, 12420 OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, 12421 0, 0 }, 12422 { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0, 12423 0, 12424 OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode, 12425 0, 0 }, 12426 { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1, 12427 XTENSA_OPERAND_IS_REGISTER, 12428 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 12429 0, 0 }, 12430 { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1, 12431 XTENSA_OPERAND_IS_REGISTER, 12432 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 12433 0, 0 }, 12434 { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, 12435 XTENSA_OPERAND_IS_REGISTER, 12436 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12437 0, 0 }, 12438 { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1, 12439 XTENSA_OPERAND_IS_REGISTER, 12440 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12441 0, 0 }, 12442 { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, 12443 XTENSA_OPERAND_IS_REGISTER, 12444 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12445 0, 0 }, 12446 { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1, 12447 XTENSA_OPERAND_IS_REGISTER, 12448 OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode, 12449 0, 0 }, 12450 { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1, 12451 XTENSA_OPERAND_IS_REGISTER, 12452 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 12453 0, 0 }, 12454 { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1, 12455 XTENSA_OPERAND_IS_REGISTER, 12456 OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode, 12457 0, 0 }, 12458 { "bitindex", FIELD_bitindex, -1, 0, 12459 0, 12460 OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode, 12461 0, 0 }, 12462 { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 }, 12463 { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 }, 12464 { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 }, 12465 { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 }, 12466 { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 }, 12467 { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 }, 12468 { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 }, 12469 { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 }, 12470 { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 }, 12471 { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 }, 12472 { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 }, 12473 { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 }, 12474 { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 }, 12475 { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 }, 12476 { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 }, 12477 { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 }, 12478 { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 }, 12479 { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 }, 12480 { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 }, 12481 { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 }, 12482 { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 }, 12483 { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 }, 12484 { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 }, 12485 { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 }, 12486 { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 }, 12487 { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 }, 12488 { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 }, 12489 { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 }, 12490 { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 }, 12491 { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 }, 12492 { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 }, 12493 { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 }, 12494 { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 }, 12495 { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 }, 12496 { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 }, 12497 { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 }, 12498 { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 }, 12499 { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 }, 12500 { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 }, 12501 { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 }, 12502 { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 }, 12503 { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 }, 12504 { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 }, 12505 { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 }, 12506 { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 }, 12507 { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 }, 12508 { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 }, 12509 { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 }, 12510 { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 }, 12511 { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 }, 12512 { "ae_r3", FIELD_ae_r3, -1, 0, 0, 0, 0, 0, 0 }, 12513 { "ae_s_non_samt", FIELD_ae_s_non_samt, -1, 0, 0, 0, 0, 0, 0 }, 12514 { "ae_s3", FIELD_ae_s3, -1, 0, 0, 0, 0, 0, 0 }, 12515 { "ae_r32", FIELD_ae_r32, -1, 0, 0, 0, 0, 0, 0 }, 12516 { "ae_samt_s_t", FIELD_ae_samt_s_t, -1, 0, 0, 0, 0, 0, 0 }, 12517 { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 }, 12518 { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 }, 12519 { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 }, 12520 { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 }, 12521 { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 }, 12522 { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 }, 12523 { "ftsf11", FIELD_ftsf11, -1, 0, 0, 0, 0, 0, 0 }, 12524 { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 }, 12525 { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 }, 12526 { "ftsf20ae_slot1", FIELD_ftsf20ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12527 { "ftsf21ae_slot1", FIELD_ftsf21ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12528 { "ftsf22ae_slot1", FIELD_ftsf22ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12529 { "ftsf23ae_slot1", FIELD_ftsf23ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12530 { "ftsf24ae_slot1", FIELD_ftsf24ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12531 { "ftsf25ae_slot1", FIELD_ftsf25ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12532 { "ftsf26ae_slot1", FIELD_ftsf26ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12533 { "ftsf27ae_slot1", FIELD_ftsf27ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12534 { "ftsf28ae_slot1", FIELD_ftsf28ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12535 { "ftsf29ae_slot1", FIELD_ftsf29ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12536 { "ftsf30ae_slot1", FIELD_ftsf30ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12537 { "ftsf31ae_slot1", FIELD_ftsf31ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12538 { "ftsf32ae_slot1", FIELD_ftsf32ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12539 { "ftsf33ae_slot1", FIELD_ftsf33ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12540 { "ftsf34ae_slot1", FIELD_ftsf34ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12541 { "ftsf35ae_slot1", FIELD_ftsf35ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12542 { "ftsf36ae_slot1", FIELD_ftsf36ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12543 { "ftsf37ae_slot1", FIELD_ftsf37ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12544 { "ftsf38ae_slot1", FIELD_ftsf38ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12545 { "ftsf40ae_slot1", FIELD_ftsf40ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12546 { "ftsf41ae_slot1", FIELD_ftsf41ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12547 { "ftsf42ae_slot1", FIELD_ftsf42ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12548 { "ftsf43ae_slot1", FIELD_ftsf43ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12549 { "ftsf45ae_slot1", FIELD_ftsf45ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12550 { "ftsf47ae_slot1", FIELD_ftsf47ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12551 { "ftsf48ae_slot1", FIELD_ftsf48ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12552 { "ftsf49ae_slot1", FIELD_ftsf49ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12553 { "ftsf50ae_slot1", FIELD_ftsf50ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12554 { "ftsf51ae_slot1", FIELD_ftsf51ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12555 { "ftsf52ae_slot1", FIELD_ftsf52ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12556 { "ftsf53ae_slot1", FIELD_ftsf53ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12557 { "ftsf54ae_slot1", FIELD_ftsf54ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12558 { "ftsf55", FIELD_ftsf55, -1, 0, 0, 0, 0, 0, 0 }, 12559 { "ftsf56ae_slot1", FIELD_ftsf56ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12560 { "ftsf57ae_slot1", FIELD_ftsf57ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12561 { "ftsf58ae_slot1", FIELD_ftsf58ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12562 { "ftsf60ae_slot1", FIELD_ftsf60ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12563 { "ftsf61", FIELD_ftsf61, -1, 0, 0, 0, 0, 0, 0 }, 12564 { "ftsf62ae_slot1", FIELD_ftsf62ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12565 { "ftsf63ae_slot1", FIELD_ftsf63ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12566 { "ftsf64ae_slot1", FIELD_ftsf64ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12567 { "ftsf66ae_slot1", FIELD_ftsf66ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12568 { "ftsf68ae_slot1", FIELD_ftsf68ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12569 { "ftsf69ae_slot1", FIELD_ftsf69ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12570 { "ftsf70ae_slot1", FIELD_ftsf70ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12571 { "ftsf71ae_slot1", FIELD_ftsf71ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12572 { "ftsf72ae_slot1", FIELD_ftsf72ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12573 { "ftsf73ae_slot1", FIELD_ftsf73ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12574 { "ftsf74ae_slot1", FIELD_ftsf74ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12575 { "ftsf75ae_slot1", FIELD_ftsf75ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12576 { "ftsf76ae_slot1", FIELD_ftsf76ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12577 { "ftsf77ae_slot1", FIELD_ftsf77ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12578 { "ftsf78ae_slot1", FIELD_ftsf78ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12579 { "ftsf79ae_slot1", FIELD_ftsf79ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12580 { "ftsf80ae_slot1", FIELD_ftsf80ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12581 { "ftsf81ae_slot1", FIELD_ftsf81ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12582 { "ftsf82ae_slot1", FIELD_ftsf82ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12583 { "ftsf83ae_slot1", FIELD_ftsf83ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12584 { "ftsf84ae_slot1", FIELD_ftsf84ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12585 { "ftsf85ae_slot1", FIELD_ftsf85ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12586 { "ftsf86ae_slot1", FIELD_ftsf86ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12587 { "ftsf87ae_slot1", FIELD_ftsf87ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12588 { "ftsf88ae_slot1", FIELD_ftsf88ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12589 { "ftsf89ae_slot1", FIELD_ftsf89ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12590 { "ftsf90ae_slot1", FIELD_ftsf90ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12591 { "ftsf91", FIELD_ftsf91, -1, 0, 0, 0, 0, 0, 0 }, 12592 { "ftsf92ae_slot1", FIELD_ftsf92ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12593 { "ftsf93ae_slot1", FIELD_ftsf93ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12594 { "ftsf94ae_slot1", FIELD_ftsf94ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12595 { "ftsf96ae_slot1", FIELD_ftsf96ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12596 { "ftsf97ae_slot1", FIELD_ftsf97ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12597 { "ftsf99ae_slot1", FIELD_ftsf99ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12598 { "ftsf101ae_slot1", FIELD_ftsf101ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12599 { "ftsf102ae_slot1", FIELD_ftsf102ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12600 { "ftsf103ae_slot1", FIELD_ftsf103ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12601 { "ftsf106ae_slot1", FIELD_ftsf106ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12602 { "ftsf107ae_slot1", FIELD_ftsf107ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12603 { "ftsf108ae_slot1", FIELD_ftsf108ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12604 { "ftsf109ae_slot1", FIELD_ftsf109ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12605 { "ftsf110ae_slot1", FIELD_ftsf110ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12606 { "ftsf111ae_slot1", FIELD_ftsf111ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12607 { "ftsf112ae_slot1", FIELD_ftsf112ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12608 { "ftsf113ae_slot1", FIELD_ftsf113ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12609 { "ftsf114ae_slot1", FIELD_ftsf114ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12610 { "ftsf115ae_slot1", FIELD_ftsf115ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12611 { "ftsf116ae_slot1", FIELD_ftsf116ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12612 { "ftsf117ae_slot1", FIELD_ftsf117ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12613 { "ftsf118ae_slot1", FIELD_ftsf118ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12614 { "ftsf120ae_slot1", FIELD_ftsf120ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12615 { "ftsf121ae_slot1", FIELD_ftsf121ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12616 { "ftsf123ae_slot1", FIELD_ftsf123ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12617 { "ftsf124ae_slot1", FIELD_ftsf124ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12618 { "ftsf125ae_slot1", FIELD_ftsf125ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12619 { "ftsf126ae_slot1", FIELD_ftsf126ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12620 { "ftsf127ae_slot1", FIELD_ftsf127ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12621 { "ftsf128ae_slot1", FIELD_ftsf128ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12622 { "ftsf129ae_slot1", FIELD_ftsf129ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12623 { "ftsf130ae_slot1", FIELD_ftsf130ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12624 { "ftsf131ae_slot1", FIELD_ftsf131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12625 { "ftsf132ae_slot1", FIELD_ftsf132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12626 { "ftsf133ae_slot1", FIELD_ftsf133ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12627 { "ftsf134ae_slot1", FIELD_ftsf134ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12628 { "ftsf135ae_slot1", FIELD_ftsf135ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12629 { "ftsf136ae_slot1", FIELD_ftsf136ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12630 { "ftsf137ae_slot1", FIELD_ftsf137ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12631 { "ftsf138ae_slot1", FIELD_ftsf138ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12632 { "ftsf139ae_slot1", FIELD_ftsf139ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12633 { "ftsf140ae_slot1", FIELD_ftsf140ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12634 { "ftsf141ae_slot1", FIELD_ftsf141ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12635 { "ftsf142ae_slot1", FIELD_ftsf142ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12636 { "ftsf143ae_slot1", FIELD_ftsf143ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12637 { "ftsf144ae_slot1", FIELD_ftsf144ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12638 { "ftsf145ae_slot1", FIELD_ftsf145ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12639 { "ftsf146ae_slot1", FIELD_ftsf146ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12640 { "ftsf147ae_slot1", FIELD_ftsf147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12641 { "ftsf148ae_slot1", FIELD_ftsf148ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12642 { "ftsf149ae_slot1", FIELD_ftsf149ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12643 { "ftsf150ae_slot1", FIELD_ftsf150ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12644 { "ftsf151ae_slot1", FIELD_ftsf151ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12645 { "ftsf152ae_slot1", FIELD_ftsf152ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12646 { "ftsf153ae_slot1", FIELD_ftsf153ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12647 { "ftsf154ae_slot1", FIELD_ftsf154ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12648 { "ftsf155ae_slot1", FIELD_ftsf155ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12649 { "ftsf156ae_slot1", FIELD_ftsf156ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12650 { "ftsf157ae_slot1", FIELD_ftsf157ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12651 { "ftsf158ae_slot1", FIELD_ftsf158ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12652 { "ftsf159ae_slot1", FIELD_ftsf159ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12653 { "ftsf160ae_slot1", FIELD_ftsf160ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12654 { "ftsf161ae_slot1", FIELD_ftsf161ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12655 { "ftsf162ae_slot1", FIELD_ftsf162ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12656 { "ftsf163ae_slot1", FIELD_ftsf163ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12657 { "ftsf164ae_slot1", FIELD_ftsf164ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12658 { "ftsf165ae_slot1", FIELD_ftsf165ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12659 { "ftsf166ae_slot1", FIELD_ftsf166ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12660 { "ftsf167ae_slot1", FIELD_ftsf167ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12661 { "ftsf168ae_slot1", FIELD_ftsf168ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12662 { "ftsf169ae_slot1", FIELD_ftsf169ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12663 { "ftsf170ae_slot1", FIELD_ftsf170ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12664 { "ftsf171ae_slot1", FIELD_ftsf171ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12665 { "ftsf172ae_slot1", FIELD_ftsf172ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12666 { "ftsf173ae_slot1", FIELD_ftsf173ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12667 { "ftsf174ae_slot1", FIELD_ftsf174ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12668 { "ftsf175ae_slot1", FIELD_ftsf175ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12669 { "ftsf176ae_slot1", FIELD_ftsf176ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12670 { "ftsf177ae_slot1", FIELD_ftsf177ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12671 { "ftsf178ae_slot1", FIELD_ftsf178ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12672 { "ftsf179ae_slot1", FIELD_ftsf179ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12673 { "ftsf180ae_slot1", FIELD_ftsf180ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12674 { "ftsf181ae_slot1", FIELD_ftsf181ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12675 { "ftsf182ae_slot1", FIELD_ftsf182ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12676 { "ftsf183ae_slot1", FIELD_ftsf183ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12677 { "ftsf184ae_slot1", FIELD_ftsf184ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12678 { "ftsf185ae_slot1", FIELD_ftsf185ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12679 { "ftsf186ae_slot1", FIELD_ftsf186ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12680 { "ftsf187ae_slot1", FIELD_ftsf187ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12681 { "ftsf188ae_slot1", FIELD_ftsf188ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12682 { "ftsf189ae_slot1", FIELD_ftsf189ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12683 { "ftsf190ae_slot1", FIELD_ftsf190ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12684 { "ftsf191ae_slot1", FIELD_ftsf191ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12685 { "ftsf192ae_slot1", FIELD_ftsf192ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12686 { "ftsf193ae_slot1", FIELD_ftsf193ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12687 { "ftsf194ae_slot1", FIELD_ftsf194ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12688 { "ftsf195ae_slot1", FIELD_ftsf195ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12689 { "ftsf196ae_slot1", FIELD_ftsf196ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12690 { "ftsf197ae_slot1", FIELD_ftsf197ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12691 { "ftsf198ae_slot1", FIELD_ftsf198ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12692 { "ftsf199ae_slot1", FIELD_ftsf199ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12693 { "ftsf200ae_slot1", FIELD_ftsf200ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12694 { "ftsf201ae_slot1", FIELD_ftsf201ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12695 { "ftsf202ae_slot1", FIELD_ftsf202ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12696 { "ftsf203ae_slot1", FIELD_ftsf203ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12697 { "ftsf204ae_slot1", FIELD_ftsf204ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12698 { "ftsf205ae_slot1", FIELD_ftsf205ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12699 { "ftsf206ae_slot1", FIELD_ftsf206ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12700 { "ftsf207ae_slot1", FIELD_ftsf207ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12701 { "ftsf208ae_slot1", FIELD_ftsf208ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12702 { "ftsf210ae_slot1", FIELD_ftsf210ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12703 { "ftsf333ae_slot1", FIELD_ftsf333ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12704 { "ftsf334ae_slot1", FIELD_ftsf334ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12705 { "ftsf335", FIELD_ftsf335, -1, 0, 0, 0, 0, 0, 0 }, 12706 { "ftsf336ae_slot1", FIELD_ftsf336ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12707 { "ftsf337ae_slot1", FIELD_ftsf337ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12708 { "ftsf339ae_slot1", FIELD_ftsf339ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12709 { "ftsf340ae_slot1", FIELD_ftsf340ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12710 { "ftsf341ae_slot1", FIELD_ftsf341ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12711 { "ftsf342ae_slot1", FIELD_ftsf342ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12712 { "ftsf343ae_slot1", FIELD_ftsf343ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12713 { "ftsf344ae_slot1", FIELD_ftsf344ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12714 { "ftsf345ae_slot1", FIELD_ftsf345ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12715 { "ftsf347ae_slot1", FIELD_ftsf347ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12716 { "ftsf348ae_slot1", FIELD_ftsf348ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12717 { "ftsf349ae_slot1", FIELD_ftsf349ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12718 { "ftsf350ae_slot1", FIELD_ftsf350ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12719 { "ftsf351", FIELD_ftsf351, -1, 0, 0, 0, 0, 0, 0 }, 12720 { "ftsf352ae_slot1", FIELD_ftsf352ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12721 { "ftsf354ae_slot1", FIELD_ftsf354ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12722 { "ftsf355ae_slot1", FIELD_ftsf355ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12723 { "ftsf356ae_slot1", FIELD_ftsf356ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12724 { "ftsf357ae_slot1", FIELD_ftsf357ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12725 { "ftsf358ae_slot1", FIELD_ftsf358ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12726 { "ftsf359ae_slot1", FIELD_ftsf359ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12727 { "op0_s4", FIELD_op0_s4, -1, 0, 0, 0, 0, 0, 0 }, 12728 { "ftsf211ae_slot0", FIELD_ftsf211ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12729 { "ftsf212ae_slot0", FIELD_ftsf212ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12730 { "ftsf213ae_slot0", FIELD_ftsf213ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12731 { "ftsf214ae_slot0", FIELD_ftsf214ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12732 { "ftsf215ae_slot0", FIELD_ftsf215ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12733 { "ftsf217ae_slot0", FIELD_ftsf217ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12734 { "ftsf218ae_slot0", FIELD_ftsf218ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12735 { "ftsf219ae_slot0", FIELD_ftsf219ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12736 { "ftsf220ae_slot0", FIELD_ftsf220ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12737 { "ftsf221ae_slot0", FIELD_ftsf221ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12738 { "ftsf222ae_slot0", FIELD_ftsf222ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12739 { "ftsf223ae_slot0", FIELD_ftsf223ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12740 { "ftsf224ae_slot0", FIELD_ftsf224ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12741 { "ftsf225ae_slot0", FIELD_ftsf225ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12742 { "ftsf226ae_slot0", FIELD_ftsf226ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12743 { "ftsf227ae_slot0", FIELD_ftsf227ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12744 { "ftsf228ae_slot0", FIELD_ftsf228ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12745 { "ftsf229ae_slot0", FIELD_ftsf229ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12746 { "ftsf230ae_slot0", FIELD_ftsf230ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12747 { "ftsf231ae_slot0", FIELD_ftsf231ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12748 { "ftsf232ae_slot0", FIELD_ftsf232ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12749 { "ftsf233ae_slot0", FIELD_ftsf233ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12750 { "ftsf234ae_slot0", FIELD_ftsf234ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12751 { "ftsf235ae_slot0", FIELD_ftsf235ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12752 { "ftsf236ae_slot0", FIELD_ftsf236ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12753 { "ftsf237ae_slot0", FIELD_ftsf237ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12754 { "ftsf238ae_slot0", FIELD_ftsf238ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12755 { "ftsf239ae_slot0", FIELD_ftsf239ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12756 { "ftsf240ae_slot0", FIELD_ftsf240ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12757 { "ftsf241ae_slot0", FIELD_ftsf241ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12758 { "ftsf242ae_slot0", FIELD_ftsf242ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12759 { "ftsf243ae_slot0", FIELD_ftsf243ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12760 { "ftsf244ae_slot0", FIELD_ftsf244ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12761 { "ftsf245ae_slot0", FIELD_ftsf245ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12762 { "ftsf246ae_slot0", FIELD_ftsf246ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12763 { "ftsf247ae_slot0", FIELD_ftsf247ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12764 { "ftsf248ae_slot0", FIELD_ftsf248ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12765 { "ftsf249ae_slot0", FIELD_ftsf249ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12766 { "ftsf250ae_slot0", FIELD_ftsf250ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12767 { "ftsf251ae_slot0", FIELD_ftsf251ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12768 { "ftsf252ae_slot0", FIELD_ftsf252ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12769 { "ftsf253ae_slot0", FIELD_ftsf253ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12770 { "ftsf254ae_slot0", FIELD_ftsf254ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12771 { "ftsf255ae_slot0", FIELD_ftsf255ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12772 { "ftsf256ae_slot0", FIELD_ftsf256ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12773 { "ftsf257ae_slot0", FIELD_ftsf257ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12774 { "ftsf258ae_slot0", FIELD_ftsf258ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12775 { "ftsf259ae_slot0", FIELD_ftsf259ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12776 { "ftsf260ae_slot0", FIELD_ftsf260ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12777 { "ftsf261ae_slot0", FIELD_ftsf261ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12778 { "ftsf262ae_slot0", FIELD_ftsf262ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12779 { "ftsf263ae_slot0", FIELD_ftsf263ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12780 { "ftsf264ae_slot0", FIELD_ftsf264ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12781 { "ftsf265ae_slot0", FIELD_ftsf265ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12782 { "ftsf266ae_slot0", FIELD_ftsf266ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12783 { "ftsf267ae_slot0", FIELD_ftsf267ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12784 { "ftsf268ae_slot0", FIELD_ftsf268ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12785 { "ftsf269ae_slot0", FIELD_ftsf269ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12786 { "ftsf270ae_slot0", FIELD_ftsf270ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12787 { "ftsf271ae_slot0", FIELD_ftsf271ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12788 { "ftsf272ae_slot0", FIELD_ftsf272ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12789 { "ftsf273ae_slot0", FIELD_ftsf273ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12790 { "ftsf274ae_slot0", FIELD_ftsf274ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12791 { "ftsf275ae_slot0", FIELD_ftsf275ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12792 { "ftsf276ae_slot0", FIELD_ftsf276ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12793 { "ftsf277ae_slot0", FIELD_ftsf277ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12794 { "ftsf278ae_slot0", FIELD_ftsf278ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12795 { "ftsf279ae_slot0", FIELD_ftsf279ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12796 { "ftsf280", FIELD_ftsf280, -1, 0, 0, 0, 0, 0, 0 }, 12797 { "ftsf281ae_slot0", FIELD_ftsf281ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12798 { "ftsf282ae_slot0", FIELD_ftsf282ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12799 { "ftsf284ae_slot0", FIELD_ftsf284ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12800 { "ftsf285ae_slot0", FIELD_ftsf285ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12801 { "ftsf287ae_slot0", FIELD_ftsf287ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12802 { "ftsf288", FIELD_ftsf288, -1, 0, 0, 0, 0, 0, 0 }, 12803 { "ftsf289ae_slot0", FIELD_ftsf289ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12804 { "ftsf290ae_slot0", FIELD_ftsf290ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12805 { "ftsf291ae_slot0", FIELD_ftsf291ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12806 { "ftsf292ae_slot0", FIELD_ftsf292ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12807 { "ftsf293ae_slot0", FIELD_ftsf293ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12808 { "ftsf294ae_slot0", FIELD_ftsf294ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12809 { "ftsf295ae_slot0", FIELD_ftsf295ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12810 { "ftsf296ae_slot0", FIELD_ftsf296ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12811 { "ftsf297ae_slot0", FIELD_ftsf297ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12812 { "ftsf298ae_slot0", FIELD_ftsf298ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12813 { "ftsf300ae_slot0", FIELD_ftsf300ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12814 { "ftsf302ae_slot0", FIELD_ftsf302ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12815 { "ftsf304ae_slot0", FIELD_ftsf304ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12816 { "ftsf305ae_slot0", FIELD_ftsf305ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12817 { "ftsf306ae_slot0", FIELD_ftsf306ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12818 { "ftsf307ae_slot0", FIELD_ftsf307ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12819 { "ftsf308ae_slot0", FIELD_ftsf308ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12820 { "ftsf309", FIELD_ftsf309, -1, 0, 0, 0, 0, 0, 0 }, 12821 { "ftsf310ae_slot0", FIELD_ftsf310ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12822 { "ftsf311ae_slot0", FIELD_ftsf311ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12823 { "ftsf312ae_slot0", FIELD_ftsf312ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12824 { "ftsf313ae_slot0", FIELD_ftsf313ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12825 { "ftsf314ae_slot0", FIELD_ftsf314ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12826 { "ftsf315", FIELD_ftsf315, -1, 0, 0, 0, 0, 0, 0 }, 12827 { "ftsf316ae_slot0", FIELD_ftsf316ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12828 { "ftsf317ae_slot0", FIELD_ftsf317ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12829 { "ftsf319ae_slot0", FIELD_ftsf319ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12830 { "ftsf320ae_slot0", FIELD_ftsf320ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12831 { "ftsf322ae_slot0", FIELD_ftsf322ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12832 { "ftsf323ae_slot0", FIELD_ftsf323ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12833 { "ftsf324ae_slot0", FIELD_ftsf324ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12834 { "ftsf325ae_slot0", FIELD_ftsf325ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12835 { "ftsf326ae_slot0", FIELD_ftsf326ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12836 { "ftsf327ae_slot0", FIELD_ftsf327ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12837 { "ftsf328ae_slot0", FIELD_ftsf328ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12838 { "ftsf329ae_slot0", FIELD_ftsf329ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12839 { "ftsf360ae_slot0", FIELD_ftsf360ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12840 { "ftsf361ae_slot0", FIELD_ftsf361ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12841 { "ftsf362", FIELD_ftsf362, -1, 0, 0, 0, 0, 0, 0 }, 12842 { "ftsf363ae_slot0", FIELD_ftsf363ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12843 { "ftsf364ae_slot0", FIELD_ftsf364ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12844 { "ftsf366ae_slot0", FIELD_ftsf366ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12845 { "ftsf368ae_slot0", FIELD_ftsf368ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12846 { "ftsf370ae_slot0", FIELD_ftsf370ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12847 { "ftsf373ae_slot0", FIELD_ftsf373ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12848 { "ftsf376ae_slot0", FIELD_ftsf376ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12849 { "ftsf378ae_slot0", FIELD_ftsf378ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12850 { "ftsf379ae_slot0", FIELD_ftsf379ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12851 { "ftsf382ae_slot0", FIELD_ftsf382ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12852 { "ftsf383ae_slot0", FIELD_ftsf383ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12853 { "ftsf384ae_slot0", FIELD_ftsf384ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12854 { "ftsf386ae_slot0", FIELD_ftsf386ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12855 { "ftsf387ae_slot0", FIELD_ftsf387ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12856 { "ftsf388ae_slot0", FIELD_ftsf388ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12857 { "ftsf389ae_slot0", FIELD_ftsf389ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12858 { "ae_mul32x24fld", FIELD_ae_mul32x24fld, -1, 0, 0, 0, 0, 0, 0 }, 12859 { "op0_s4_s4", FIELD_op0_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, 12860 { "combined2c0b5f72_fld28", FIELD_combined2c0b5f72_fld28, -1, 0, 0, 0, 0, 0, 0 }, 12861 { "combined2c0b5f72_fld37", FIELD_combined2c0b5f72_fld37, -1, 0, 0, 0, 0, 0, 0 }, 12862 { "combined2c0b5f72_fld39", FIELD_combined2c0b5f72_fld39, -1, 0, 0, 0, 0, 0, 0 }, 12863 { "combined2c0b5f72_fld40", FIELD_combined2c0b5f72_fld40, -1, 0, 0, 0, 0, 0, 0 }, 12864 { "combined2c0b5f72_fld46", FIELD_combined2c0b5f72_fld46, -1, 0, 0, 0, 0, 0, 0 }, 12865 { "combined2c0b5f72_fld47", FIELD_combined2c0b5f72_fld47, -1, 0, 0, 0, 0, 0, 0 }, 12866 { "combined2c0b5f72_fld49", FIELD_combined2c0b5f72_fld49, -1, 0, 0, 0, 0, 0, 0 }, 12867 { "combined2c0b5f72_fld50", FIELD_combined2c0b5f72_fld50, -1, 0, 0, 0, 0, 0, 0 }, 12868 { "combined2c0b5f72_fld52", FIELD_combined2c0b5f72_fld52, -1, 0, 0, 0, 0, 0, 0 }, 12869 { "combined2c0b5f72_fld121", FIELD_combined2c0b5f72_fld121, -1, 0, 0, 0, 0, 0, 0 }, 12870 { "combined2c0b5f72_fld123", FIELD_combined2c0b5f72_fld123, -1, 0, 0, 0, 0, 0, 0 }, 12871 { "combined2c0b5f72_fld127", FIELD_combined2c0b5f72_fld127, -1, 0, 0, 0, 0, 0, 0 }, 12872 { "combined2c0b5f72_fld133ae_slot0", FIELD_combined2c0b5f72_fld133ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12873 { "combined2c0b5f72_fld134ae_slot0", FIELD_combined2c0b5f72_fld134ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12874 { "combined2c0b5f72_fld135ae_slot0", FIELD_combined2c0b5f72_fld135ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12875 { "combined2c0b5f72_fld136ae_slot0", FIELD_combined2c0b5f72_fld136ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12876 { "combined2c0b5f72_fld137ae_slot0", FIELD_combined2c0b5f72_fld137ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12877 { "combined2c0b5f72_fld138ae_slot0", FIELD_combined2c0b5f72_fld138ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12878 { "combined2c0b5f72_fld139ae_slot0", FIELD_combined2c0b5f72_fld139ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12879 { "combined2c0b5f72_fld140ae_slot0", FIELD_combined2c0b5f72_fld140ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12880 { "combined2c0b5f72_fld141ae_slot0", FIELD_combined2c0b5f72_fld141ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12881 { "combined2c0b5f72_fld142ae_slot0", FIELD_combined2c0b5f72_fld142ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12882 { "combined2c0b5f72_fld143ae_slot0", FIELD_combined2c0b5f72_fld143ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12883 { "combined2c0b5f72_fld144ae_slot0", FIELD_combined2c0b5f72_fld144ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12884 { "combined2c0b5f72_fld145ae_slot0", FIELD_combined2c0b5f72_fld145ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12885 { "combined2c0b5f72_fld146ae_slot0", FIELD_combined2c0b5f72_fld146ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12886 { "combined2c0b5f72_fld148ae_slot0", FIELD_combined2c0b5f72_fld148ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12887 { "combined2c0b5f72_fld149ae_slot0", FIELD_combined2c0b5f72_fld149ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12888 { "op0_s4_s4_s4", FIELD_op0_s4_s4_s4, -1, 0, 0, 0, 0, 0, 0 }, 12889 { "combined1e9fefee_fld96", FIELD_combined1e9fefee_fld96, -1, 0, 0, 0, 0, 0, 0 }, 12890 { "combined1e9fefee_fld98", FIELD_combined1e9fefee_fld98, -1, 0, 0, 0, 0, 0, 0 }, 12891 { "combined1e9fefee_fld106ae_slot0", FIELD_combined1e9fefee_fld106ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12892 { "combined1e9fefee_fld107ae_slot0", FIELD_combined1e9fefee_fld107ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12893 { "combined1e9fefee_fld108ae_slot0", FIELD_combined1e9fefee_fld108ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12894 { "combined1e9fefee_fld109ae_slot0", FIELD_combined1e9fefee_fld109ae_slot0, -1, 0, 0, 0, 0, 0, 0 }, 12895 { "op0_s3_s3", FIELD_op0_s3_s3, -1, 0, 0, 0, 0, 0, 0 }, 12896 { "combined2c0b5f72_fld19", FIELD_combined2c0b5f72_fld19, -1, 0, 0, 0, 0, 0, 0 }, 12897 { "combined2c0b5f72_fld22", FIELD_combined2c0b5f72_fld22, -1, 0, 0, 0, 0, 0, 0 }, 12898 { "combined2c0b5f72_fld24", FIELD_combined2c0b5f72_fld24, -1, 0, 0, 0, 0, 0, 0 }, 12899 { "combined2c0b5f72_fld65", FIELD_combined2c0b5f72_fld65, -1, 0, 0, 0, 0, 0, 0 }, 12900 { "combined2c0b5f72_fld66", FIELD_combined2c0b5f72_fld66, -1, 0, 0, 0, 0, 0, 0 }, 12901 { "combined2c0b5f72_fld68", FIELD_combined2c0b5f72_fld68, -1, 0, 0, 0, 0, 0, 0 }, 12902 { "combined2c0b5f72_fld69", FIELD_combined2c0b5f72_fld69, -1, 0, 0, 0, 0, 0, 0 }, 12903 { "combined2c0b5f72_fld74", FIELD_combined2c0b5f72_fld74, -1, 0, 0, 0, 0, 0, 0 }, 12904 { "combined2c0b5f72_fld79", FIELD_combined2c0b5f72_fld79, -1, 0, 0, 0, 0, 0, 0 }, 12905 { "combined2c0b5f72_fld88", FIELD_combined2c0b5f72_fld88, -1, 0, 0, 0, 0, 0, 0 }, 12906 { "combined2c0b5f72_fld90", FIELD_combined2c0b5f72_fld90, -1, 0, 0, 0, 0, 0, 0 }, 12907 { "combined2c0b5f72_fld91", FIELD_combined2c0b5f72_fld91, -1, 0, 0, 0, 0, 0, 0 }, 12908 { "combined2c0b5f72_fld131ae_slot1", FIELD_combined2c0b5f72_fld131ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12909 { "combined2c0b5f72_fld132ae_slot1", FIELD_combined2c0b5f72_fld132ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12910 { "combined2c0b5f72_fld147ae_slot1", FIELD_combined2c0b5f72_fld147ae_slot1, -1, 0, 0, 0, 0, 0, 0 }, 12911 { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 } 12912 }; 12913 12914 enum xtensa_operand_id { 12915 OPERAND_soffsetx4, 12916 OPERAND_uimm12x8, 12917 OPERAND_simm4, 12918 OPERAND_arr, 12919 OPERAND_ars, 12920 OPERAND__ars_invisible, 12921 OPERAND_art, 12922 OPERAND_ar0, 12923 OPERAND_ar4, 12924 OPERAND_ar8, 12925 OPERAND_ar12, 12926 OPERAND_ars_entry, 12927 OPERAND_immrx4, 12928 OPERAND_lsi4x4, 12929 OPERAND_simm7, 12930 OPERAND_uimm6, 12931 OPERAND_ai4const, 12932 OPERAND_b4const, 12933 OPERAND_b4constu, 12934 OPERAND_uimm8, 12935 OPERAND_uimm8x2, 12936 OPERAND_uimm8x4, 12937 OPERAND_uimm4x16, 12938 OPERAND_uimmrx4, 12939 OPERAND_simm8, 12940 OPERAND_simm8x256, 12941 OPERAND_simm12b, 12942 OPERAND_msalp32, 12943 OPERAND_op2p1, 12944 OPERAND_label8, 12945 OPERAND_ulabel8, 12946 OPERAND_label12, 12947 OPERAND_soffset, 12948 OPERAND_uimm16x4, 12949 OPERAND_bbi, 12950 OPERAND_sae, 12951 OPERAND_sas, 12952 OPERAND_sargt, 12953 OPERAND_s, 12954 OPERAND_mx, 12955 OPERAND_my, 12956 OPERAND_mw, 12957 OPERAND_mr0, 12958 OPERAND_mr1, 12959 OPERAND_mr2, 12960 OPERAND_mr3, 12961 OPERAND_immt, 12962 OPERAND_imms, 12963 OPERAND_bt, 12964 OPERAND_bs, 12965 OPERAND_br, 12966 OPERAND_bt2, 12967 OPERAND_bs2, 12968 OPERAND_br2, 12969 OPERAND_bt4, 12970 OPERAND_bs4, 12971 OPERAND_br4, 12972 OPERAND_bt8, 12973 OPERAND_bs8, 12974 OPERAND_br8, 12975 OPERAND_bt16, 12976 OPERAND_bs16, 12977 OPERAND_br16, 12978 OPERAND_brall, 12979 OPERAND_tp7, 12980 OPERAND_xt_wbr15_label, 12981 OPERAND_xt_wbr18_label, 12982 OPERAND_ae_samt32, 12983 OPERAND_pr0, 12984 OPERAND_qr0, 12985 OPERAND_mac_qr0, 12986 OPERAND_ae_lsimm16, 12987 OPERAND_ae_lsimm32, 12988 OPERAND_ae_lsimm64, 12989 OPERAND_ae_samt64, 12990 OPERAND_ae_ohba, 12991 OPERAND_ae_ohba2, 12992 OPERAND_pr, 12993 OPERAND_cvt_pr, 12994 OPERAND_qr0_rw, 12995 OPERAND_mac_qr0_rw, 12996 OPERAND_qr1_w, 12997 OPERAND_mac_qr1_w, 12998 OPERAND_ps, 12999 OPERAND_alupppb_ps, 13000 OPERAND_bitindex, 13001 OPERAND_t, 13002 OPERAND_bbi4, 13003 OPERAND_imm12, 13004 OPERAND_imm8, 13005 OPERAND_imm12b, 13006 OPERAND_imm16, 13007 OPERAND_m, 13008 OPERAND_n, 13009 OPERAND_offset, 13010 OPERAND_op0, 13011 OPERAND_op1, 13012 OPERAND_op2, 13013 OPERAND_r, 13014 OPERAND_sa4, 13015 OPERAND_sae4, 13016 OPERAND_sal, 13017 OPERAND_sas4, 13018 OPERAND_sr, 13019 OPERAND_st, 13020 OPERAND_thi3, 13021 OPERAND_imm4, 13022 OPERAND_mn, 13023 OPERAND_i, 13024 OPERAND_imm6lo, 13025 OPERAND_imm6hi, 13026 OPERAND_imm7lo, 13027 OPERAND_imm7hi, 13028 OPERAND_z, 13029 OPERAND_imm6, 13030 OPERAND_imm7, 13031 OPERAND_r3, 13032 OPERAND_rbit2, 13033 OPERAND_rhi, 13034 OPERAND_t3, 13035 OPERAND_tbit2, 13036 OPERAND_tlo, 13037 OPERAND_w, 13038 OPERAND_y, 13039 OPERAND_x, 13040 OPERAND_t2, 13041 OPERAND_s2, 13042 OPERAND_r2, 13043 OPERAND_t4, 13044 OPERAND_s4, 13045 OPERAND_r4, 13046 OPERAND_t8, 13047 OPERAND_s8, 13048 OPERAND_r8, 13049 OPERAND_xt_wbr15_imm, 13050 OPERAND_xt_wbr18_imm, 13051 OPERAND_ae_r3, 13052 OPERAND_ae_s_non_samt, 13053 OPERAND_ae_s3, 13054 OPERAND_ae_r32, 13055 OPERAND_ae_samt_s_t, 13056 OPERAND_ae_r20, 13057 OPERAND_ae_r10, 13058 OPERAND_ae_s20, 13059 OPERAND_ae_fld_ohba, 13060 OPERAND_ae_fld_ohba2, 13061 OPERAND_op0_s3, 13062 OPERAND_ftsf11, 13063 OPERAND_ftsf12, 13064 OPERAND_ftsf13, 13065 OPERAND_ftsf20ae_slot1, 13066 OPERAND_ftsf21ae_slot1, 13067 OPERAND_ftsf22ae_slot1, 13068 OPERAND_ftsf23ae_slot1, 13069 OPERAND_ftsf24ae_slot1, 13070 OPERAND_ftsf25ae_slot1, 13071 OPERAND_ftsf26ae_slot1, 13072 OPERAND_ftsf27ae_slot1, 13073 OPERAND_ftsf28ae_slot1, 13074 OPERAND_ftsf29ae_slot1, 13075 OPERAND_ftsf30ae_slot1, 13076 OPERAND_ftsf31ae_slot1, 13077 OPERAND_ftsf32ae_slot1, 13078 OPERAND_ftsf33ae_slot1, 13079 OPERAND_ftsf34ae_slot1, 13080 OPERAND_ftsf35ae_slot1, 13081 OPERAND_ftsf36ae_slot1, 13082 OPERAND_ftsf37ae_slot1, 13083 OPERAND_ftsf38ae_slot1, 13084 OPERAND_ftsf40ae_slot1, 13085 OPERAND_ftsf41ae_slot1, 13086 OPERAND_ftsf42ae_slot1, 13087 OPERAND_ftsf43ae_slot1, 13088 OPERAND_ftsf45ae_slot1, 13089 OPERAND_ftsf47ae_slot1, 13090 OPERAND_ftsf48ae_slot1, 13091 OPERAND_ftsf49ae_slot1, 13092 OPERAND_ftsf50ae_slot1, 13093 OPERAND_ftsf51ae_slot1, 13094 OPERAND_ftsf52ae_slot1, 13095 OPERAND_ftsf53ae_slot1, 13096 OPERAND_ftsf54ae_slot1, 13097 OPERAND_ftsf55, 13098 OPERAND_ftsf56ae_slot1, 13099 OPERAND_ftsf57ae_slot1, 13100 OPERAND_ftsf58ae_slot1, 13101 OPERAND_ftsf60ae_slot1, 13102 OPERAND_ftsf61, 13103 OPERAND_ftsf62ae_slot1, 13104 OPERAND_ftsf63ae_slot1, 13105 OPERAND_ftsf64ae_slot1, 13106 OPERAND_ftsf66ae_slot1, 13107 OPERAND_ftsf68ae_slot1, 13108 OPERAND_ftsf69ae_slot1, 13109 OPERAND_ftsf70ae_slot1, 13110 OPERAND_ftsf71ae_slot1, 13111 OPERAND_ftsf72ae_slot1, 13112 OPERAND_ftsf73ae_slot1, 13113 OPERAND_ftsf74ae_slot1, 13114 OPERAND_ftsf75ae_slot1, 13115 OPERAND_ftsf76ae_slot1, 13116 OPERAND_ftsf77ae_slot1, 13117 OPERAND_ftsf78ae_slot1, 13118 OPERAND_ftsf79ae_slot1, 13119 OPERAND_ftsf80ae_slot1, 13120 OPERAND_ftsf81ae_slot1, 13121 OPERAND_ftsf82ae_slot1, 13122 OPERAND_ftsf83ae_slot1, 13123 OPERAND_ftsf84ae_slot1, 13124 OPERAND_ftsf85ae_slot1, 13125 OPERAND_ftsf86ae_slot1, 13126 OPERAND_ftsf87ae_slot1, 13127 OPERAND_ftsf88ae_slot1, 13128 OPERAND_ftsf89ae_slot1, 13129 OPERAND_ftsf90ae_slot1, 13130 OPERAND_ftsf91, 13131 OPERAND_ftsf92ae_slot1, 13132 OPERAND_ftsf93ae_slot1, 13133 OPERAND_ftsf94ae_slot1, 13134 OPERAND_ftsf96ae_slot1, 13135 OPERAND_ftsf97ae_slot1, 13136 OPERAND_ftsf99ae_slot1, 13137 OPERAND_ftsf101ae_slot1, 13138 OPERAND_ftsf102ae_slot1, 13139 OPERAND_ftsf103ae_slot1, 13140 OPERAND_ftsf106ae_slot1, 13141 OPERAND_ftsf107ae_slot1, 13142 OPERAND_ftsf108ae_slot1, 13143 OPERAND_ftsf109ae_slot1, 13144 OPERAND_ftsf110ae_slot1, 13145 OPERAND_ftsf111ae_slot1, 13146 OPERAND_ftsf112ae_slot1, 13147 OPERAND_ftsf113ae_slot1, 13148 OPERAND_ftsf114ae_slot1, 13149 OPERAND_ftsf115ae_slot1, 13150 OPERAND_ftsf116ae_slot1, 13151 OPERAND_ftsf117ae_slot1, 13152 OPERAND_ftsf118ae_slot1, 13153 OPERAND_ftsf120ae_slot1, 13154 OPERAND_ftsf121ae_slot1, 13155 OPERAND_ftsf123ae_slot1, 13156 OPERAND_ftsf124ae_slot1, 13157 OPERAND_ftsf125ae_slot1, 13158 OPERAND_ftsf126ae_slot1, 13159 OPERAND_ftsf127ae_slot1, 13160 OPERAND_ftsf128ae_slot1, 13161 OPERAND_ftsf129ae_slot1, 13162 OPERAND_ftsf130ae_slot1, 13163 OPERAND_ftsf131ae_slot1, 13164 OPERAND_ftsf132ae_slot1, 13165 OPERAND_ftsf133ae_slot1, 13166 OPERAND_ftsf134ae_slot1, 13167 OPERAND_ftsf135ae_slot1, 13168 OPERAND_ftsf136ae_slot1, 13169 OPERAND_ftsf137ae_slot1, 13170 OPERAND_ftsf138ae_slot1, 13171 OPERAND_ftsf139ae_slot1, 13172 OPERAND_ftsf140ae_slot1, 13173 OPERAND_ftsf141ae_slot1, 13174 OPERAND_ftsf142ae_slot1, 13175 OPERAND_ftsf143ae_slot1, 13176 OPERAND_ftsf144ae_slot1, 13177 OPERAND_ftsf145ae_slot1, 13178 OPERAND_ftsf146ae_slot1, 13179 OPERAND_ftsf147ae_slot1, 13180 OPERAND_ftsf148ae_slot1, 13181 OPERAND_ftsf149ae_slot1, 13182 OPERAND_ftsf150ae_slot1, 13183 OPERAND_ftsf151ae_slot1, 13184 OPERAND_ftsf152ae_slot1, 13185 OPERAND_ftsf153ae_slot1, 13186 OPERAND_ftsf154ae_slot1, 13187 OPERAND_ftsf155ae_slot1, 13188 OPERAND_ftsf156ae_slot1, 13189 OPERAND_ftsf157ae_slot1, 13190 OPERAND_ftsf158ae_slot1, 13191 OPERAND_ftsf159ae_slot1, 13192 OPERAND_ftsf160ae_slot1, 13193 OPERAND_ftsf161ae_slot1, 13194 OPERAND_ftsf162ae_slot1, 13195 OPERAND_ftsf163ae_slot1, 13196 OPERAND_ftsf164ae_slot1, 13197 OPERAND_ftsf165ae_slot1, 13198 OPERAND_ftsf166ae_slot1, 13199 OPERAND_ftsf167ae_slot1, 13200 OPERAND_ftsf168ae_slot1, 13201 OPERAND_ftsf169ae_slot1, 13202 OPERAND_ftsf170ae_slot1, 13203 OPERAND_ftsf171ae_slot1, 13204 OPERAND_ftsf172ae_slot1, 13205 OPERAND_ftsf173ae_slot1, 13206 OPERAND_ftsf174ae_slot1, 13207 OPERAND_ftsf175ae_slot1, 13208 OPERAND_ftsf176ae_slot1, 13209 OPERAND_ftsf177ae_slot1, 13210 OPERAND_ftsf178ae_slot1, 13211 OPERAND_ftsf179ae_slot1, 13212 OPERAND_ftsf180ae_slot1, 13213 OPERAND_ftsf181ae_slot1, 13214 OPERAND_ftsf182ae_slot1, 13215 OPERAND_ftsf183ae_slot1, 13216 OPERAND_ftsf184ae_slot1, 13217 OPERAND_ftsf185ae_slot1, 13218 OPERAND_ftsf186ae_slot1, 13219 OPERAND_ftsf187ae_slot1, 13220 OPERAND_ftsf188ae_slot1, 13221 OPERAND_ftsf189ae_slot1, 13222 OPERAND_ftsf190ae_slot1, 13223 OPERAND_ftsf191ae_slot1, 13224 OPERAND_ftsf192ae_slot1, 13225 OPERAND_ftsf193ae_slot1, 13226 OPERAND_ftsf194ae_slot1, 13227 OPERAND_ftsf195ae_slot1, 13228 OPERAND_ftsf196ae_slot1, 13229 OPERAND_ftsf197ae_slot1, 13230 OPERAND_ftsf198ae_slot1, 13231 OPERAND_ftsf199ae_slot1, 13232 OPERAND_ftsf200ae_slot1, 13233 OPERAND_ftsf201ae_slot1, 13234 OPERAND_ftsf202ae_slot1, 13235 OPERAND_ftsf203ae_slot1, 13236 OPERAND_ftsf204ae_slot1, 13237 OPERAND_ftsf205ae_slot1, 13238 OPERAND_ftsf206ae_slot1, 13239 OPERAND_ftsf207ae_slot1, 13240 OPERAND_ftsf208ae_slot1, 13241 OPERAND_ftsf210ae_slot1, 13242 OPERAND_ftsf333ae_slot1, 13243 OPERAND_ftsf334ae_slot1, 13244 OPERAND_ftsf335, 13245 OPERAND_ftsf336ae_slot1, 13246 OPERAND_ftsf337ae_slot1, 13247 OPERAND_ftsf339ae_slot1, 13248 OPERAND_ftsf340ae_slot1, 13249 OPERAND_ftsf341ae_slot1, 13250 OPERAND_ftsf342ae_slot1, 13251 OPERAND_ftsf343ae_slot1, 13252 OPERAND_ftsf344ae_slot1, 13253 OPERAND_ftsf345ae_slot1, 13254 OPERAND_ftsf347ae_slot1, 13255 OPERAND_ftsf348ae_slot1, 13256 OPERAND_ftsf349ae_slot1, 13257 OPERAND_ftsf350ae_slot1, 13258 OPERAND_ftsf351, 13259 OPERAND_ftsf352ae_slot1, 13260 OPERAND_ftsf354ae_slot1, 13261 OPERAND_ftsf355ae_slot1, 13262 OPERAND_ftsf356ae_slot1, 13263 OPERAND_ftsf357ae_slot1, 13264 OPERAND_ftsf358ae_slot1, 13265 OPERAND_ftsf359ae_slot1, 13266 OPERAND_op0_s4, 13267 OPERAND_ftsf211ae_slot0, 13268 OPERAND_ftsf212ae_slot0, 13269 OPERAND_ftsf213ae_slot0, 13270 OPERAND_ftsf214ae_slot0, 13271 OPERAND_ftsf215ae_slot0, 13272 OPERAND_ftsf217ae_slot0, 13273 OPERAND_ftsf218ae_slot0, 13274 OPERAND_ftsf219ae_slot0, 13275 OPERAND_ftsf220ae_slot0, 13276 OPERAND_ftsf221ae_slot0, 13277 OPERAND_ftsf222ae_slot0, 13278 OPERAND_ftsf223ae_slot0, 13279 OPERAND_ftsf224ae_slot0, 13280 OPERAND_ftsf225ae_slot0, 13281 OPERAND_ftsf226ae_slot0, 13282 OPERAND_ftsf227ae_slot0, 13283 OPERAND_ftsf228ae_slot0, 13284 OPERAND_ftsf229ae_slot0, 13285 OPERAND_ftsf230ae_slot0, 13286 OPERAND_ftsf231ae_slot0, 13287 OPERAND_ftsf232ae_slot0, 13288 OPERAND_ftsf233ae_slot0, 13289 OPERAND_ftsf234ae_slot0, 13290 OPERAND_ftsf235ae_slot0, 13291 OPERAND_ftsf236ae_slot0, 13292 OPERAND_ftsf237ae_slot0, 13293 OPERAND_ftsf238ae_slot0, 13294 OPERAND_ftsf239ae_slot0, 13295 OPERAND_ftsf240ae_slot0, 13296 OPERAND_ftsf241ae_slot0, 13297 OPERAND_ftsf242ae_slot0, 13298 OPERAND_ftsf243ae_slot0, 13299 OPERAND_ftsf244ae_slot0, 13300 OPERAND_ftsf245ae_slot0, 13301 OPERAND_ftsf246ae_slot0, 13302 OPERAND_ftsf247ae_slot0, 13303 OPERAND_ftsf248ae_slot0, 13304 OPERAND_ftsf249ae_slot0, 13305 OPERAND_ftsf250ae_slot0, 13306 OPERAND_ftsf251ae_slot0, 13307 OPERAND_ftsf252ae_slot0, 13308 OPERAND_ftsf253ae_slot0, 13309 OPERAND_ftsf254ae_slot0, 13310 OPERAND_ftsf255ae_slot0, 13311 OPERAND_ftsf256ae_slot0, 13312 OPERAND_ftsf257ae_slot0, 13313 OPERAND_ftsf258ae_slot0, 13314 OPERAND_ftsf259ae_slot0, 13315 OPERAND_ftsf260ae_slot0, 13316 OPERAND_ftsf261ae_slot0, 13317 OPERAND_ftsf262ae_slot0, 13318 OPERAND_ftsf263ae_slot0, 13319 OPERAND_ftsf264ae_slot0, 13320 OPERAND_ftsf265ae_slot0, 13321 OPERAND_ftsf266ae_slot0, 13322 OPERAND_ftsf267ae_slot0, 13323 OPERAND_ftsf268ae_slot0, 13324 OPERAND_ftsf269ae_slot0, 13325 OPERAND_ftsf270ae_slot0, 13326 OPERAND_ftsf271ae_slot0, 13327 OPERAND_ftsf272ae_slot0, 13328 OPERAND_ftsf273ae_slot0, 13329 OPERAND_ftsf274ae_slot0, 13330 OPERAND_ftsf275ae_slot0, 13331 OPERAND_ftsf276ae_slot0, 13332 OPERAND_ftsf277ae_slot0, 13333 OPERAND_ftsf278ae_slot0, 13334 OPERAND_ftsf279ae_slot0, 13335 OPERAND_ftsf280, 13336 OPERAND_ftsf281ae_slot0, 13337 OPERAND_ftsf282ae_slot0, 13338 OPERAND_ftsf284ae_slot0, 13339 OPERAND_ftsf285ae_slot0, 13340 OPERAND_ftsf287ae_slot0, 13341 OPERAND_ftsf288, 13342 OPERAND_ftsf289ae_slot0, 13343 OPERAND_ftsf290ae_slot0, 13344 OPERAND_ftsf291ae_slot0, 13345 OPERAND_ftsf292ae_slot0, 13346 OPERAND_ftsf293ae_slot0, 13347 OPERAND_ftsf294ae_slot0, 13348 OPERAND_ftsf295ae_slot0, 13349 OPERAND_ftsf296ae_slot0, 13350 OPERAND_ftsf297ae_slot0, 13351 OPERAND_ftsf298ae_slot0, 13352 OPERAND_ftsf300ae_slot0, 13353 OPERAND_ftsf302ae_slot0, 13354 OPERAND_ftsf304ae_slot0, 13355 OPERAND_ftsf305ae_slot0, 13356 OPERAND_ftsf306ae_slot0, 13357 OPERAND_ftsf307ae_slot0, 13358 OPERAND_ftsf308ae_slot0, 13359 OPERAND_ftsf309, 13360 OPERAND_ftsf310ae_slot0, 13361 OPERAND_ftsf311ae_slot0, 13362 OPERAND_ftsf312ae_slot0, 13363 OPERAND_ftsf313ae_slot0, 13364 OPERAND_ftsf314ae_slot0, 13365 OPERAND_ftsf315, 13366 OPERAND_ftsf316ae_slot0, 13367 OPERAND_ftsf317ae_slot0, 13368 OPERAND_ftsf319ae_slot0, 13369 OPERAND_ftsf320ae_slot0, 13370 OPERAND_ftsf322ae_slot0, 13371 OPERAND_ftsf323ae_slot0, 13372 OPERAND_ftsf324ae_slot0, 13373 OPERAND_ftsf325ae_slot0, 13374 OPERAND_ftsf326ae_slot0, 13375 OPERAND_ftsf327ae_slot0, 13376 OPERAND_ftsf328ae_slot0, 13377 OPERAND_ftsf329ae_slot0, 13378 OPERAND_ftsf360ae_slot0, 13379 OPERAND_ftsf361ae_slot0, 13380 OPERAND_ftsf362, 13381 OPERAND_ftsf363ae_slot0, 13382 OPERAND_ftsf364ae_slot0, 13383 OPERAND_ftsf366ae_slot0, 13384 OPERAND_ftsf368ae_slot0, 13385 OPERAND_ftsf370ae_slot0, 13386 OPERAND_ftsf373ae_slot0, 13387 OPERAND_ftsf376ae_slot0, 13388 OPERAND_ftsf378ae_slot0, 13389 OPERAND_ftsf379ae_slot0, 13390 OPERAND_ftsf382ae_slot0, 13391 OPERAND_ftsf383ae_slot0, 13392 OPERAND_ftsf384ae_slot0, 13393 OPERAND_ftsf386ae_slot0, 13394 OPERAND_ftsf387ae_slot0, 13395 OPERAND_ftsf388ae_slot0, 13396 OPERAND_ftsf389ae_slot0, 13397 OPERAND_ae_mul32x24fld, 13398 OPERAND_op0_s4_s4, 13399 OPERAND_combined2c0b5f72_fld28, 13400 OPERAND_combined2c0b5f72_fld37, 13401 OPERAND_combined2c0b5f72_fld39, 13402 OPERAND_combined2c0b5f72_fld40, 13403 OPERAND_combined2c0b5f72_fld46, 13404 OPERAND_combined2c0b5f72_fld47, 13405 OPERAND_combined2c0b5f72_fld49, 13406 OPERAND_combined2c0b5f72_fld50, 13407 OPERAND_combined2c0b5f72_fld52, 13408 OPERAND_combined2c0b5f72_fld121, 13409 OPERAND_combined2c0b5f72_fld123, 13410 OPERAND_combined2c0b5f72_fld127, 13411 OPERAND_combined2c0b5f72_fld133ae_slot0, 13412 OPERAND_combined2c0b5f72_fld134ae_slot0, 13413 OPERAND_combined2c0b5f72_fld135ae_slot0, 13414 OPERAND_combined2c0b5f72_fld136ae_slot0, 13415 OPERAND_combined2c0b5f72_fld137ae_slot0, 13416 OPERAND_combined2c0b5f72_fld138ae_slot0, 13417 OPERAND_combined2c0b5f72_fld139ae_slot0, 13418 OPERAND_combined2c0b5f72_fld140ae_slot0, 13419 OPERAND_combined2c0b5f72_fld141ae_slot0, 13420 OPERAND_combined2c0b5f72_fld142ae_slot0, 13421 OPERAND_combined2c0b5f72_fld143ae_slot0, 13422 OPERAND_combined2c0b5f72_fld144ae_slot0, 13423 OPERAND_combined2c0b5f72_fld145ae_slot0, 13424 OPERAND_combined2c0b5f72_fld146ae_slot0, 13425 OPERAND_combined2c0b5f72_fld148ae_slot0, 13426 OPERAND_combined2c0b5f72_fld149ae_slot0, 13427 OPERAND_op0_s4_s4_s4, 13428 OPERAND_combined1e9fefee_fld96, 13429 OPERAND_combined1e9fefee_fld98, 13430 OPERAND_combined1e9fefee_fld106ae_slot0, 13431 OPERAND_combined1e9fefee_fld107ae_slot0, 13432 OPERAND_combined1e9fefee_fld108ae_slot0, 13433 OPERAND_combined1e9fefee_fld109ae_slot0, 13434 OPERAND_op0_s3_s3, 13435 OPERAND_combined2c0b5f72_fld19, 13436 OPERAND_combined2c0b5f72_fld22, 13437 OPERAND_combined2c0b5f72_fld24, 13438 OPERAND_combined2c0b5f72_fld65, 13439 OPERAND_combined2c0b5f72_fld66, 13440 OPERAND_combined2c0b5f72_fld68, 13441 OPERAND_combined2c0b5f72_fld69, 13442 OPERAND_combined2c0b5f72_fld74, 13443 OPERAND_combined2c0b5f72_fld79, 13444 OPERAND_combined2c0b5f72_fld88, 13445 OPERAND_combined2c0b5f72_fld90, 13446 OPERAND_combined2c0b5f72_fld91, 13447 OPERAND_combined2c0b5f72_fld131ae_slot1, 13448 OPERAND_combined2c0b5f72_fld132ae_slot1, 13449 OPERAND_combined2c0b5f72_fld147ae_slot1, 13450 OPERAND_s3to1 13451 }; 13452 13453 13454 /* Iclass table. */ 13455 13456 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = { 13457 { { STATE_PSRING }, 'i' }, 13458 { { STATE_PSEXCM }, 'm' }, 13459 { { STATE_EPC1 }, 'i' } 13460 }; 13461 13462 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = { 13463 { { STATE_PSEXCM }, 'i' }, 13464 { { STATE_PSRING }, 'i' }, 13465 { { STATE_DEPC }, 'i' } 13466 }; 13467 13468 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = { 13469 { { OPERAND_soffsetx4 }, 'i' }, 13470 { { OPERAND_ar12 }, 'o' } 13471 }; 13472 13473 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = { 13474 { { STATE_PSCALLINC }, 'o' } 13475 }; 13476 13477 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = { 13478 { { OPERAND_soffsetx4 }, 'i' }, 13479 { { OPERAND_ar8 }, 'o' } 13480 }; 13481 13482 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = { 13483 { { STATE_PSCALLINC }, 'o' } 13484 }; 13485 13486 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = { 13487 { { OPERAND_soffsetx4 }, 'i' }, 13488 { { OPERAND_ar4 }, 'o' } 13489 }; 13490 13491 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = { 13492 { { STATE_PSCALLINC }, 'o' } 13493 }; 13494 13495 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = { 13496 { { OPERAND_ars }, 'i' }, 13497 { { OPERAND_ar12 }, 'o' } 13498 }; 13499 13500 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = { 13501 { { STATE_PSCALLINC }, 'o' } 13502 }; 13503 13504 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = { 13505 { { OPERAND_ars }, 'i' }, 13506 { { OPERAND_ar8 }, 'o' } 13507 }; 13508 13509 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = { 13510 { { STATE_PSCALLINC }, 'o' } 13511 }; 13512 13513 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = { 13514 { { OPERAND_ars }, 'i' }, 13515 { { OPERAND_ar4 }, 'o' } 13516 }; 13517 13518 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = { 13519 { { STATE_PSCALLINC }, 'o' } 13520 }; 13521 13522 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = { 13523 { { OPERAND_ars_entry }, 's' }, 13524 { { OPERAND_ars }, 'i' }, 13525 { { OPERAND_uimm12x8 }, 'i' } 13526 }; 13527 13528 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = { 13529 { { STATE_PSCALLINC }, 'i' }, 13530 { { STATE_PSEXCM }, 'i' }, 13531 { { STATE_PSWOE }, 'i' }, 13532 { { STATE_WindowBase }, 'm' }, 13533 { { STATE_WindowStart }, 'm' } 13534 }; 13535 13536 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = { 13537 { { OPERAND_art }, 'o' }, 13538 { { OPERAND_ars }, 'i' } 13539 }; 13540 13541 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = { 13542 { { STATE_WindowBase }, 'i' }, 13543 { { STATE_WindowStart }, 'i' } 13544 }; 13545 13546 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = { 13547 { { OPERAND_simm4 }, 'i' } 13548 }; 13549 13550 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = { 13551 { { STATE_PSEXCM }, 'i' }, 13552 { { STATE_PSRING }, 'i' }, 13553 { { STATE_WindowBase }, 'm' } 13554 }; 13555 13556 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = { 13557 { { OPERAND__ars_invisible }, 'i' } 13558 }; 13559 13560 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = { 13561 { { STATE_WindowBase }, 'm' }, 13562 { { STATE_WindowStart }, 'm' }, 13563 { { STATE_PSCALLINC }, 'o' }, 13564 { { STATE_PSEXCM }, 'i' }, 13565 { { STATE_PSWOE }, 'i' } 13566 }; 13567 13568 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = { 13569 { { STATE_EPC1 }, 'i' }, 13570 { { STATE_PSEXCM }, 'm' }, 13571 { { STATE_PSRING }, 'i' }, 13572 { { STATE_WindowBase }, 'm' }, 13573 { { STATE_WindowStart }, 'm' }, 13574 { { STATE_PSOWB }, 'i' } 13575 }; 13576 13577 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = { 13578 { { OPERAND_art }, 'o' }, 13579 { { OPERAND_ars }, 'i' }, 13580 { { OPERAND_immrx4 }, 'i' } 13581 }; 13582 13583 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = { 13584 { { STATE_PSEXCM }, 'i' }, 13585 { { STATE_PSRING }, 'i' } 13586 }; 13587 13588 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = { 13589 { { OPERAND_art }, 'i' }, 13590 { { OPERAND_ars }, 'i' }, 13591 { { OPERAND_immrx4 }, 'i' } 13592 }; 13593 13594 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = { 13595 { { STATE_PSEXCM }, 'i' }, 13596 { { STATE_PSRING }, 'i' } 13597 }; 13598 13599 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = { 13600 { { OPERAND_art }, 'o' } 13601 }; 13602 13603 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = { 13604 { { STATE_PSEXCM }, 'i' }, 13605 { { STATE_PSRING }, 'i' }, 13606 { { STATE_WindowBase }, 'i' } 13607 }; 13608 13609 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = { 13610 { { OPERAND_art }, 'i' } 13611 }; 13612 13613 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = { 13614 { { STATE_PSEXCM }, 'i' }, 13615 { { STATE_PSRING }, 'i' }, 13616 { { STATE_WindowBase }, 'o' } 13617 }; 13618 13619 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = { 13620 { { OPERAND_art }, 'm' } 13621 }; 13622 13623 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = { 13624 { { STATE_PSEXCM }, 'i' }, 13625 { { STATE_PSRING }, 'i' }, 13626 { { STATE_WindowBase }, 'm' } 13627 }; 13628 13629 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = { 13630 { { OPERAND_art }, 'o' } 13631 }; 13632 13633 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = { 13634 { { STATE_PSEXCM }, 'i' }, 13635 { { STATE_PSRING }, 'i' }, 13636 { { STATE_WindowStart }, 'i' } 13637 }; 13638 13639 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = { 13640 { { OPERAND_art }, 'i' } 13641 }; 13642 13643 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = { 13644 { { STATE_PSEXCM }, 'i' }, 13645 { { STATE_PSRING }, 'i' }, 13646 { { STATE_WindowStart }, 'o' } 13647 }; 13648 13649 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = { 13650 { { OPERAND_art }, 'm' } 13651 }; 13652 13653 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = { 13654 { { STATE_PSEXCM }, 'i' }, 13655 { { STATE_PSRING }, 'i' }, 13656 { { STATE_WindowStart }, 'm' } 13657 }; 13658 13659 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = { 13660 { { OPERAND_arr }, 'o' }, 13661 { { OPERAND_ars }, 'i' }, 13662 { { OPERAND_art }, 'i' } 13663 }; 13664 13665 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = { 13666 { { OPERAND_arr }, 'o' }, 13667 { { OPERAND_ars }, 'i' }, 13668 { { OPERAND_ai4const }, 'i' } 13669 }; 13670 13671 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = { 13672 { { OPERAND_ars }, 'i' }, 13673 { { OPERAND_uimm6 }, 'i' } 13674 }; 13675 13676 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = { 13677 { { OPERAND_art }, 'o' }, 13678 { { OPERAND_ars }, 'i' }, 13679 { { OPERAND_lsi4x4 }, 'i' } 13680 }; 13681 13682 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = { 13683 { { OPERAND_art }, 'o' }, 13684 { { OPERAND_ars }, 'i' } 13685 }; 13686 13687 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = { 13688 { { OPERAND_ars }, 'o' }, 13689 { { OPERAND_simm7 }, 'i' } 13690 }; 13691 13692 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = { 13693 { { OPERAND__ars_invisible }, 'i' } 13694 }; 13695 13696 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = { 13697 { { OPERAND_art }, 'i' }, 13698 { { OPERAND_ars }, 'i' }, 13699 { { OPERAND_lsi4x4 }, 'i' } 13700 }; 13701 13702 static xtensa_arg_internal Iclass_rur_threadptr_args[] = { 13703 { { OPERAND_arr }, 'o' } 13704 }; 13705 13706 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = { 13707 { { STATE_THREADPTR }, 'i' } 13708 }; 13709 13710 static xtensa_arg_internal Iclass_wur_threadptr_args[] = { 13711 { { OPERAND_art }, 'i' } 13712 }; 13713 13714 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = { 13715 { { STATE_THREADPTR }, 'o' } 13716 }; 13717 13718 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = { 13719 { { OPERAND_art }, 'o' }, 13720 { { OPERAND_ars }, 'i' }, 13721 { { OPERAND_simm8 }, 'i' } 13722 }; 13723 13724 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = { 13725 { { OPERAND_art }, 'o' }, 13726 { { OPERAND_ars }, 'i' }, 13727 { { OPERAND_simm8x256 }, 'i' } 13728 }; 13729 13730 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = { 13731 { { OPERAND_arr }, 'o' }, 13732 { { OPERAND_ars }, 'i' }, 13733 { { OPERAND_art }, 'i' } 13734 }; 13735 13736 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = { 13737 { { OPERAND_arr }, 'o' }, 13738 { { OPERAND_ars }, 'i' }, 13739 { { OPERAND_art }, 'i' } 13740 }; 13741 13742 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = { 13743 { { OPERAND_ars }, 'i' }, 13744 { { OPERAND_b4const }, 'i' }, 13745 { { OPERAND_label8 }, 'i' } 13746 }; 13747 13748 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = { 13749 { { OPERAND_ars }, 'i' }, 13750 { { OPERAND_bbi }, 'i' }, 13751 { { OPERAND_label8 }, 'i' } 13752 }; 13753 13754 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = { 13755 { { OPERAND_ars }, 'i' }, 13756 { { OPERAND_b4constu }, 'i' }, 13757 { { OPERAND_label8 }, 'i' } 13758 }; 13759 13760 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = { 13761 { { OPERAND_ars }, 'i' }, 13762 { { OPERAND_art }, 'i' }, 13763 { { OPERAND_label8 }, 'i' } 13764 }; 13765 13766 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = { 13767 { { OPERAND_ars }, 'i' }, 13768 { { OPERAND_label12 }, 'i' } 13769 }; 13770 13771 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = { 13772 { { OPERAND_soffsetx4 }, 'i' }, 13773 { { OPERAND_ar0 }, 'o' } 13774 }; 13775 13776 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = { 13777 { { OPERAND_ars }, 'i' }, 13778 { { OPERAND_ar0 }, 'o' } 13779 }; 13780 13781 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = { 13782 { { OPERAND_arr }, 'o' }, 13783 { { OPERAND_art }, 'i' }, 13784 { { OPERAND_sae }, 'i' }, 13785 { { OPERAND_op2p1 }, 'i' } 13786 }; 13787 13788 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = { 13789 { { OPERAND_soffset }, 'i' } 13790 }; 13791 13792 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = { 13793 { { OPERAND_ars }, 'i' } 13794 }; 13795 13796 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = { 13797 { { OPERAND_art }, 'o' }, 13798 { { OPERAND_ars }, 'i' }, 13799 { { OPERAND_uimm8x2 }, 'i' } 13800 }; 13801 13802 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = { 13803 { { OPERAND_art }, 'o' }, 13804 { { OPERAND_ars }, 'i' }, 13805 { { OPERAND_uimm8x2 }, 'i' } 13806 }; 13807 13808 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = { 13809 { { OPERAND_art }, 'o' }, 13810 { { OPERAND_ars }, 'i' }, 13811 { { OPERAND_uimm8x4 }, 'i' } 13812 }; 13813 13814 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = { 13815 { { OPERAND_art }, 'o' }, 13816 { { OPERAND_uimm16x4 }, 'i' } 13817 }; 13818 13819 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = { 13820 { { OPERAND_art }, 'o' }, 13821 { { OPERAND_ars }, 'i' }, 13822 { { OPERAND_uimm8 }, 'i' } 13823 }; 13824 13825 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = { 13826 { { OPERAND_ars }, 'i' }, 13827 { { OPERAND_ulabel8 }, 'i' } 13828 }; 13829 13830 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = { 13831 { { STATE_LBEG }, 'o' }, 13832 { { STATE_LEND }, 'o' }, 13833 { { STATE_LCOUNT }, 'o' } 13834 }; 13835 13836 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = { 13837 { { OPERAND_ars }, 'i' }, 13838 { { OPERAND_ulabel8 }, 'i' } 13839 }; 13840 13841 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = { 13842 { { STATE_LBEG }, 'o' }, 13843 { { STATE_LEND }, 'o' }, 13844 { { STATE_LCOUNT }, 'o' } 13845 }; 13846 13847 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = { 13848 { { OPERAND_art }, 'o' }, 13849 { { OPERAND_simm12b }, 'i' } 13850 }; 13851 13852 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = { 13853 { { OPERAND_arr }, 'm' }, 13854 { { OPERAND_ars }, 'i' }, 13855 { { OPERAND_art }, 'i' } 13856 }; 13857 13858 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = { 13859 { { OPERAND_arr }, 'o' }, 13860 { { OPERAND_art }, 'i' } 13861 }; 13862 13863 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = { 13864 { { OPERAND__ars_invisible }, 'i' } 13865 }; 13866 13867 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = { 13868 { { OPERAND_art }, 'i' }, 13869 { { OPERAND_ars }, 'i' }, 13870 { { OPERAND_uimm8x2 }, 'i' } 13871 }; 13872 13873 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = { 13874 { { OPERAND_art }, 'i' }, 13875 { { OPERAND_ars }, 'i' }, 13876 { { OPERAND_uimm8x4 }, 'i' } 13877 }; 13878 13879 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = { 13880 { { OPERAND_art }, 'i' }, 13881 { { OPERAND_ars }, 'i' }, 13882 { { OPERAND_uimmrx4 }, 'i' } 13883 }; 13884 13885 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = { 13886 { { OPERAND_art }, 'i' }, 13887 { { OPERAND_ars }, 'i' }, 13888 { { OPERAND_uimm8 }, 'i' } 13889 }; 13890 13891 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = { 13892 { { OPERAND_ars }, 'i' } 13893 }; 13894 13895 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = { 13896 { { STATE_SAR }, 'o' } 13897 }; 13898 13899 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = { 13900 { { OPERAND_sas }, 'i' } 13901 }; 13902 13903 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = { 13904 { { STATE_SAR }, 'o' } 13905 }; 13906 13907 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = { 13908 { { OPERAND_arr }, 'o' }, 13909 { { OPERAND_ars }, 'i' } 13910 }; 13911 13912 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = { 13913 { { STATE_SAR }, 'i' } 13914 }; 13915 13916 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = { 13917 { { OPERAND_arr }, 'o' }, 13918 { { OPERAND_ars }, 'i' }, 13919 { { OPERAND_art }, 'i' } 13920 }; 13921 13922 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = { 13923 { { STATE_SAR }, 'i' } 13924 }; 13925 13926 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = { 13927 { { OPERAND_arr }, 'o' }, 13928 { { OPERAND_art }, 'i' } 13929 }; 13930 13931 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = { 13932 { { STATE_SAR }, 'i' } 13933 }; 13934 13935 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = { 13936 { { OPERAND_arr }, 'o' }, 13937 { { OPERAND_ars }, 'i' }, 13938 { { OPERAND_msalp32 }, 'i' } 13939 }; 13940 13941 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = { 13942 { { OPERAND_arr }, 'o' }, 13943 { { OPERAND_art }, 'i' }, 13944 { { OPERAND_sargt }, 'i' } 13945 }; 13946 13947 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = { 13948 { { OPERAND_arr }, 'o' }, 13949 { { OPERAND_art }, 'i' }, 13950 { { OPERAND_s }, 'i' } 13951 }; 13952 13953 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = { 13954 { { STATE_XTSYNC }, 'i' } 13955 }; 13956 13957 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = { 13958 { { OPERAND_art }, 'o' }, 13959 { { OPERAND_s }, 'i' } 13960 }; 13961 13962 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = { 13963 { { STATE_PSWOE }, 'i' }, 13964 { { STATE_PSCALLINC }, 'i' }, 13965 { { STATE_PSOWB }, 'i' }, 13966 { { STATE_PSRING }, 'i' }, 13967 { { STATE_PSUM }, 'i' }, 13968 { { STATE_PSEXCM }, 'i' }, 13969 { { STATE_PSINTLEVEL }, 'm' } 13970 }; 13971 13972 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = { 13973 { { OPERAND_art }, 'o' } 13974 }; 13975 13976 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = { 13977 { { STATE_LEND }, 'i' } 13978 }; 13979 13980 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = { 13981 { { OPERAND_art }, 'i' } 13982 }; 13983 13984 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = { 13985 { { STATE_LEND }, 'o' } 13986 }; 13987 13988 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = { 13989 { { OPERAND_art }, 'm' } 13990 }; 13991 13992 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = { 13993 { { STATE_LEND }, 'm' } 13994 }; 13995 13996 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = { 13997 { { OPERAND_art }, 'o' } 13998 }; 13999 14000 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = { 14001 { { STATE_LCOUNT }, 'i' } 14002 }; 14003 14004 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = { 14005 { { OPERAND_art }, 'i' } 14006 }; 14007 14008 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = { 14009 { { STATE_XTSYNC }, 'o' }, 14010 { { STATE_LCOUNT }, 'o' } 14011 }; 14012 14013 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = { 14014 { { OPERAND_art }, 'm' } 14015 }; 14016 14017 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = { 14018 { { STATE_XTSYNC }, 'o' }, 14019 { { STATE_LCOUNT }, 'm' } 14020 }; 14021 14022 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = { 14023 { { OPERAND_art }, 'o' } 14024 }; 14025 14026 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = { 14027 { { STATE_LBEG }, 'i' } 14028 }; 14029 14030 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = { 14031 { { OPERAND_art }, 'i' } 14032 }; 14033 14034 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = { 14035 { { STATE_LBEG }, 'o' } 14036 }; 14037 14038 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = { 14039 { { OPERAND_art }, 'm' } 14040 }; 14041 14042 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = { 14043 { { STATE_LBEG }, 'm' } 14044 }; 14045 14046 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = { 14047 { { OPERAND_art }, 'o' } 14048 }; 14049 14050 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = { 14051 { { STATE_SAR }, 'i' } 14052 }; 14053 14054 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = { 14055 { { OPERAND_art }, 'i' } 14056 }; 14057 14058 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = { 14059 { { STATE_SAR }, 'o' }, 14060 { { STATE_XTSYNC }, 'o' } 14061 }; 14062 14063 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = { 14064 { { OPERAND_art }, 'm' } 14065 }; 14066 14067 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = { 14068 { { STATE_SAR }, 'm' } 14069 }; 14070 14071 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = { 14072 { { OPERAND_art }, 'o' } 14073 }; 14074 14075 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = { 14076 { { OPERAND_art }, 'i' } 14077 }; 14078 14079 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = { 14080 { { OPERAND_art }, 'm' } 14081 }; 14082 14083 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = { 14084 { { OPERAND_art }, 'o' } 14085 }; 14086 14087 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = { 14088 { { OPERAND_art }, 'i' } 14089 }; 14090 14091 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = { 14092 { { OPERAND_art }, 'm' } 14093 }; 14094 14095 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = { 14096 { { OPERAND_art }, 'o' } 14097 }; 14098 14099 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = { 14100 { { STATE_PSEXCM }, 'i' }, 14101 { { STATE_PSRING }, 'i' } 14102 }; 14103 14104 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = { 14105 { { OPERAND_art }, 'i' } 14106 }; 14107 14108 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = { 14109 { { STATE_PSEXCM }, 'i' }, 14110 { { STATE_PSRING }, 'i' } 14111 }; 14112 14113 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = { 14114 { { OPERAND_art }, 'o' } 14115 }; 14116 14117 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = { 14118 { { STATE_PSEXCM }, 'i' }, 14119 { { STATE_PSRING }, 'i' } 14120 }; 14121 14122 static xtensa_arg_internal Iclass_xt_iclass_rsr_243_args[] = { 14123 { { OPERAND_art }, 'o' } 14124 }; 14125 14126 static xtensa_arg_internal Iclass_xt_iclass_rsr_243_stateArgs[] = { 14127 { { STATE_PSEXCM }, 'i' }, 14128 { { STATE_PSRING }, 'i' } 14129 }; 14130 14131 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = { 14132 { { OPERAND_art }, 'o' } 14133 }; 14134 14135 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = { 14136 { { STATE_PSWOE }, 'i' }, 14137 { { STATE_PSCALLINC }, 'i' }, 14138 { { STATE_PSOWB }, 'i' }, 14139 { { STATE_PSRING }, 'i' }, 14140 { { STATE_PSUM }, 'i' }, 14141 { { STATE_PSEXCM }, 'i' }, 14142 { { STATE_PSINTLEVEL }, 'i' } 14143 }; 14144 14145 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = { 14146 { { OPERAND_art }, 'i' } 14147 }; 14148 14149 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = { 14150 { { STATE_PSWOE }, 'o' }, 14151 { { STATE_PSCALLINC }, 'o' }, 14152 { { STATE_PSOWB }, 'o' }, 14153 { { STATE_PSRING }, 'm' }, 14154 { { STATE_PSUM }, 'o' }, 14155 { { STATE_PSEXCM }, 'm' }, 14156 { { STATE_PSINTLEVEL }, 'o' } 14157 }; 14158 14159 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = { 14160 { { OPERAND_art }, 'm' } 14161 }; 14162 14163 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = { 14164 { { STATE_PSWOE }, 'm' }, 14165 { { STATE_PSCALLINC }, 'm' }, 14166 { { STATE_PSOWB }, 'm' }, 14167 { { STATE_PSRING }, 'm' }, 14168 { { STATE_PSUM }, 'm' }, 14169 { { STATE_PSEXCM }, 'm' }, 14170 { { STATE_PSINTLEVEL }, 'm' } 14171 }; 14172 14173 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = { 14174 { { OPERAND_art }, 'o' } 14175 }; 14176 14177 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = { 14178 { { STATE_PSEXCM }, 'i' }, 14179 { { STATE_PSRING }, 'i' }, 14180 { { STATE_EPC1 }, 'i' } 14181 }; 14182 14183 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = { 14184 { { OPERAND_art }, 'i' } 14185 }; 14186 14187 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = { 14188 { { STATE_PSEXCM }, 'i' }, 14189 { { STATE_PSRING }, 'i' }, 14190 { { STATE_EPC1 }, 'o' } 14191 }; 14192 14193 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = { 14194 { { OPERAND_art }, 'm' } 14195 }; 14196 14197 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = { 14198 { { STATE_PSEXCM }, 'i' }, 14199 { { STATE_PSRING }, 'i' }, 14200 { { STATE_EPC1 }, 'm' } 14201 }; 14202 14203 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = { 14204 { { OPERAND_art }, 'o' } 14205 }; 14206 14207 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = { 14208 { { STATE_PSEXCM }, 'i' }, 14209 { { STATE_PSRING }, 'i' }, 14210 { { STATE_EXCSAVE1 }, 'i' } 14211 }; 14212 14213 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = { 14214 { { OPERAND_art }, 'i' } 14215 }; 14216 14217 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = { 14218 { { STATE_PSEXCM }, 'i' }, 14219 { { STATE_PSRING }, 'i' }, 14220 { { STATE_EXCSAVE1 }, 'o' } 14221 }; 14222 14223 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = { 14224 { { OPERAND_art }, 'm' } 14225 }; 14226 14227 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = { 14228 { { STATE_PSEXCM }, 'i' }, 14229 { { STATE_PSRING }, 'i' }, 14230 { { STATE_EXCSAVE1 }, 'm' } 14231 }; 14232 14233 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = { 14234 { { OPERAND_art }, 'o' } 14235 }; 14236 14237 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = { 14238 { { STATE_PSEXCM }, 'i' }, 14239 { { STATE_PSRING }, 'i' }, 14240 { { STATE_EPC2 }, 'i' } 14241 }; 14242 14243 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = { 14244 { { OPERAND_art }, 'i' } 14245 }; 14246 14247 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = { 14248 { { STATE_PSEXCM }, 'i' }, 14249 { { STATE_PSRING }, 'i' }, 14250 { { STATE_EPC2 }, 'o' } 14251 }; 14252 14253 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = { 14254 { { OPERAND_art }, 'm' } 14255 }; 14256 14257 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = { 14258 { { STATE_PSEXCM }, 'i' }, 14259 { { STATE_PSRING }, 'i' }, 14260 { { STATE_EPC2 }, 'm' } 14261 }; 14262 14263 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = { 14264 { { OPERAND_art }, 'o' } 14265 }; 14266 14267 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = { 14268 { { STATE_PSEXCM }, 'i' }, 14269 { { STATE_PSRING }, 'i' }, 14270 { { STATE_EXCSAVE2 }, 'i' } 14271 }; 14272 14273 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = { 14274 { { OPERAND_art }, 'i' } 14275 }; 14276 14277 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = { 14278 { { STATE_PSEXCM }, 'i' }, 14279 { { STATE_PSRING }, 'i' }, 14280 { { STATE_EXCSAVE2 }, 'o' } 14281 }; 14282 14283 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = { 14284 { { OPERAND_art }, 'm' } 14285 }; 14286 14287 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = { 14288 { { STATE_PSEXCM }, 'i' }, 14289 { { STATE_PSRING }, 'i' }, 14290 { { STATE_EXCSAVE2 }, 'm' } 14291 }; 14292 14293 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = { 14294 { { OPERAND_art }, 'o' } 14295 }; 14296 14297 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = { 14298 { { STATE_PSEXCM }, 'i' }, 14299 { { STATE_PSRING }, 'i' }, 14300 { { STATE_EPC3 }, 'i' } 14301 }; 14302 14303 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = { 14304 { { OPERAND_art }, 'i' } 14305 }; 14306 14307 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = { 14308 { { STATE_PSEXCM }, 'i' }, 14309 { { STATE_PSRING }, 'i' }, 14310 { { STATE_EPC3 }, 'o' } 14311 }; 14312 14313 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = { 14314 { { OPERAND_art }, 'm' } 14315 }; 14316 14317 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = { 14318 { { STATE_PSEXCM }, 'i' }, 14319 { { STATE_PSRING }, 'i' }, 14320 { { STATE_EPC3 }, 'm' } 14321 }; 14322 14323 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = { 14324 { { OPERAND_art }, 'o' } 14325 }; 14326 14327 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = { 14328 { { STATE_PSEXCM }, 'i' }, 14329 { { STATE_PSRING }, 'i' }, 14330 { { STATE_EXCSAVE3 }, 'i' } 14331 }; 14332 14333 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = { 14334 { { OPERAND_art }, 'i' } 14335 }; 14336 14337 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = { 14338 { { STATE_PSEXCM }, 'i' }, 14339 { { STATE_PSRING }, 'i' }, 14340 { { STATE_EXCSAVE3 }, 'o' } 14341 }; 14342 14343 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = { 14344 { { OPERAND_art }, 'm' } 14345 }; 14346 14347 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = { 14348 { { STATE_PSEXCM }, 'i' }, 14349 { { STATE_PSRING }, 'i' }, 14350 { { STATE_EXCSAVE3 }, 'm' } 14351 }; 14352 14353 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = { 14354 { { OPERAND_art }, 'o' } 14355 }; 14356 14357 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = { 14358 { { STATE_PSEXCM }, 'i' }, 14359 { { STATE_PSRING }, 'i' }, 14360 { { STATE_EPC4 }, 'i' } 14361 }; 14362 14363 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = { 14364 { { OPERAND_art }, 'i' } 14365 }; 14366 14367 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = { 14368 { { STATE_PSEXCM }, 'i' }, 14369 { { STATE_PSRING }, 'i' }, 14370 { { STATE_EPC4 }, 'o' } 14371 }; 14372 14373 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = { 14374 { { OPERAND_art }, 'm' } 14375 }; 14376 14377 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = { 14378 { { STATE_PSEXCM }, 'i' }, 14379 { { STATE_PSRING }, 'i' }, 14380 { { STATE_EPC4 }, 'm' } 14381 }; 14382 14383 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = { 14384 { { OPERAND_art }, 'o' } 14385 }; 14386 14387 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = { 14388 { { STATE_PSEXCM }, 'i' }, 14389 { { STATE_PSRING }, 'i' }, 14390 { { STATE_EXCSAVE4 }, 'i' } 14391 }; 14392 14393 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = { 14394 { { OPERAND_art }, 'i' } 14395 }; 14396 14397 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = { 14398 { { STATE_PSEXCM }, 'i' }, 14399 { { STATE_PSRING }, 'i' }, 14400 { { STATE_EXCSAVE4 }, 'o' } 14401 }; 14402 14403 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = { 14404 { { OPERAND_art }, 'm' } 14405 }; 14406 14407 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = { 14408 { { STATE_PSEXCM }, 'i' }, 14409 { { STATE_PSRING }, 'i' }, 14410 { { STATE_EXCSAVE4 }, 'm' } 14411 }; 14412 14413 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = { 14414 { { OPERAND_art }, 'o' } 14415 }; 14416 14417 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = { 14418 { { STATE_PSEXCM }, 'i' }, 14419 { { STATE_PSRING }, 'i' }, 14420 { { STATE_EPC5 }, 'i' } 14421 }; 14422 14423 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = { 14424 { { OPERAND_art }, 'i' } 14425 }; 14426 14427 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = { 14428 { { STATE_PSEXCM }, 'i' }, 14429 { { STATE_PSRING }, 'i' }, 14430 { { STATE_EPC5 }, 'o' } 14431 }; 14432 14433 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = { 14434 { { OPERAND_art }, 'm' } 14435 }; 14436 14437 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = { 14438 { { STATE_PSEXCM }, 'i' }, 14439 { { STATE_PSRING }, 'i' }, 14440 { { STATE_EPC5 }, 'm' } 14441 }; 14442 14443 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = { 14444 { { OPERAND_art }, 'o' } 14445 }; 14446 14447 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = { 14448 { { STATE_PSEXCM }, 'i' }, 14449 { { STATE_PSRING }, 'i' }, 14450 { { STATE_EXCSAVE5 }, 'i' } 14451 }; 14452 14453 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = { 14454 { { OPERAND_art }, 'i' } 14455 }; 14456 14457 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = { 14458 { { STATE_PSEXCM }, 'i' }, 14459 { { STATE_PSRING }, 'i' }, 14460 { { STATE_EXCSAVE5 }, 'o' } 14461 }; 14462 14463 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = { 14464 { { OPERAND_art }, 'm' } 14465 }; 14466 14467 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = { 14468 { { STATE_PSEXCM }, 'i' }, 14469 { { STATE_PSRING }, 'i' }, 14470 { { STATE_EXCSAVE5 }, 'm' } 14471 }; 14472 14473 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = { 14474 { { OPERAND_art }, 'o' } 14475 }; 14476 14477 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = { 14478 { { STATE_PSEXCM }, 'i' }, 14479 { { STATE_PSRING }, 'i' }, 14480 { { STATE_EPC6 }, 'i' } 14481 }; 14482 14483 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = { 14484 { { OPERAND_art }, 'i' } 14485 }; 14486 14487 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = { 14488 { { STATE_PSEXCM }, 'i' }, 14489 { { STATE_PSRING }, 'i' }, 14490 { { STATE_EPC6 }, 'o' } 14491 }; 14492 14493 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = { 14494 { { OPERAND_art }, 'm' } 14495 }; 14496 14497 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = { 14498 { { STATE_PSEXCM }, 'i' }, 14499 { { STATE_PSRING }, 'i' }, 14500 { { STATE_EPC6 }, 'm' } 14501 }; 14502 14503 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = { 14504 { { OPERAND_art }, 'o' } 14505 }; 14506 14507 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = { 14508 { { STATE_PSEXCM }, 'i' }, 14509 { { STATE_PSRING }, 'i' }, 14510 { { STATE_EXCSAVE6 }, 'i' } 14511 }; 14512 14513 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = { 14514 { { OPERAND_art }, 'i' } 14515 }; 14516 14517 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = { 14518 { { STATE_PSEXCM }, 'i' }, 14519 { { STATE_PSRING }, 'i' }, 14520 { { STATE_EXCSAVE6 }, 'o' } 14521 }; 14522 14523 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = { 14524 { { OPERAND_art }, 'm' } 14525 }; 14526 14527 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = { 14528 { { STATE_PSEXCM }, 'i' }, 14529 { { STATE_PSRING }, 'i' }, 14530 { { STATE_EXCSAVE6 }, 'm' } 14531 }; 14532 14533 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = { 14534 { { OPERAND_art }, 'o' } 14535 }; 14536 14537 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = { 14538 { { STATE_PSEXCM }, 'i' }, 14539 { { STATE_PSRING }, 'i' }, 14540 { { STATE_EPC7 }, 'i' } 14541 }; 14542 14543 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = { 14544 { { OPERAND_art }, 'i' } 14545 }; 14546 14547 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = { 14548 { { STATE_PSEXCM }, 'i' }, 14549 { { STATE_PSRING }, 'i' }, 14550 { { STATE_EPC7 }, 'o' } 14551 }; 14552 14553 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = { 14554 { { OPERAND_art }, 'm' } 14555 }; 14556 14557 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = { 14558 { { STATE_PSEXCM }, 'i' }, 14559 { { STATE_PSRING }, 'i' }, 14560 { { STATE_EPC7 }, 'm' } 14561 }; 14562 14563 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = { 14564 { { OPERAND_art }, 'o' } 14565 }; 14566 14567 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = { 14568 { { STATE_PSEXCM }, 'i' }, 14569 { { STATE_PSRING }, 'i' }, 14570 { { STATE_EXCSAVE7 }, 'i' } 14571 }; 14572 14573 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = { 14574 { { OPERAND_art }, 'i' } 14575 }; 14576 14577 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = { 14578 { { STATE_PSEXCM }, 'i' }, 14579 { { STATE_PSRING }, 'i' }, 14580 { { STATE_EXCSAVE7 }, 'o' } 14581 }; 14582 14583 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = { 14584 { { OPERAND_art }, 'm' } 14585 }; 14586 14587 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = { 14588 { { STATE_PSEXCM }, 'i' }, 14589 { { STATE_PSRING }, 'i' }, 14590 { { STATE_EXCSAVE7 }, 'm' } 14591 }; 14592 14593 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = { 14594 { { OPERAND_art }, 'o' } 14595 }; 14596 14597 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = { 14598 { { STATE_PSEXCM }, 'i' }, 14599 { { STATE_PSRING }, 'i' }, 14600 { { STATE_EPS2 }, 'i' } 14601 }; 14602 14603 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = { 14604 { { OPERAND_art }, 'i' } 14605 }; 14606 14607 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = { 14608 { { STATE_PSEXCM }, 'i' }, 14609 { { STATE_PSRING }, 'i' }, 14610 { { STATE_EPS2 }, 'o' } 14611 }; 14612 14613 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = { 14614 { { OPERAND_art }, 'm' } 14615 }; 14616 14617 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = { 14618 { { STATE_PSEXCM }, 'i' }, 14619 { { STATE_PSRING }, 'i' }, 14620 { { STATE_EPS2 }, 'm' } 14621 }; 14622 14623 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = { 14624 { { OPERAND_art }, 'o' } 14625 }; 14626 14627 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = { 14628 { { STATE_PSEXCM }, 'i' }, 14629 { { STATE_PSRING }, 'i' }, 14630 { { STATE_EPS3 }, 'i' } 14631 }; 14632 14633 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = { 14634 { { OPERAND_art }, 'i' } 14635 }; 14636 14637 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = { 14638 { { STATE_PSEXCM }, 'i' }, 14639 { { STATE_PSRING }, 'i' }, 14640 { { STATE_EPS3 }, 'o' } 14641 }; 14642 14643 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = { 14644 { { OPERAND_art }, 'm' } 14645 }; 14646 14647 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = { 14648 { { STATE_PSEXCM }, 'i' }, 14649 { { STATE_PSRING }, 'i' }, 14650 { { STATE_EPS3 }, 'm' } 14651 }; 14652 14653 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = { 14654 { { OPERAND_art }, 'o' } 14655 }; 14656 14657 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = { 14658 { { STATE_PSEXCM }, 'i' }, 14659 { { STATE_PSRING }, 'i' }, 14660 { { STATE_EPS4 }, 'i' } 14661 }; 14662 14663 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = { 14664 { { OPERAND_art }, 'i' } 14665 }; 14666 14667 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = { 14668 { { STATE_PSEXCM }, 'i' }, 14669 { { STATE_PSRING }, 'i' }, 14670 { { STATE_EPS4 }, 'o' } 14671 }; 14672 14673 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = { 14674 { { OPERAND_art }, 'm' } 14675 }; 14676 14677 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = { 14678 { { STATE_PSEXCM }, 'i' }, 14679 { { STATE_PSRING }, 'i' }, 14680 { { STATE_EPS4 }, 'm' } 14681 }; 14682 14683 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = { 14684 { { OPERAND_art }, 'o' } 14685 }; 14686 14687 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = { 14688 { { STATE_PSEXCM }, 'i' }, 14689 { { STATE_PSRING }, 'i' }, 14690 { { STATE_EPS5 }, 'i' } 14691 }; 14692 14693 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = { 14694 { { OPERAND_art }, 'i' } 14695 }; 14696 14697 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = { 14698 { { STATE_PSEXCM }, 'i' }, 14699 { { STATE_PSRING }, 'i' }, 14700 { { STATE_EPS5 }, 'o' } 14701 }; 14702 14703 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = { 14704 { { OPERAND_art }, 'm' } 14705 }; 14706 14707 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = { 14708 { { STATE_PSEXCM }, 'i' }, 14709 { { STATE_PSRING }, 'i' }, 14710 { { STATE_EPS5 }, 'm' } 14711 }; 14712 14713 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = { 14714 { { OPERAND_art }, 'o' } 14715 }; 14716 14717 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = { 14718 { { STATE_PSEXCM }, 'i' }, 14719 { { STATE_PSRING }, 'i' }, 14720 { { STATE_EPS6 }, 'i' } 14721 }; 14722 14723 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = { 14724 { { OPERAND_art }, 'i' } 14725 }; 14726 14727 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = { 14728 { { STATE_PSEXCM }, 'i' }, 14729 { { STATE_PSRING }, 'i' }, 14730 { { STATE_EPS6 }, 'o' } 14731 }; 14732 14733 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = { 14734 { { OPERAND_art }, 'm' } 14735 }; 14736 14737 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = { 14738 { { STATE_PSEXCM }, 'i' }, 14739 { { STATE_PSRING }, 'i' }, 14740 { { STATE_EPS6 }, 'm' } 14741 }; 14742 14743 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = { 14744 { { OPERAND_art }, 'o' } 14745 }; 14746 14747 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = { 14748 { { STATE_PSEXCM }, 'i' }, 14749 { { STATE_PSRING }, 'i' }, 14750 { { STATE_EPS7 }, 'i' } 14751 }; 14752 14753 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = { 14754 { { OPERAND_art }, 'i' } 14755 }; 14756 14757 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = { 14758 { { STATE_PSEXCM }, 'i' }, 14759 { { STATE_PSRING }, 'i' }, 14760 { { STATE_EPS7 }, 'o' } 14761 }; 14762 14763 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = { 14764 { { OPERAND_art }, 'm' } 14765 }; 14766 14767 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = { 14768 { { STATE_PSEXCM }, 'i' }, 14769 { { STATE_PSRING }, 'i' }, 14770 { { STATE_EPS7 }, 'm' } 14771 }; 14772 14773 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = { 14774 { { OPERAND_art }, 'o' } 14775 }; 14776 14777 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = { 14778 { { STATE_PSEXCM }, 'i' }, 14779 { { STATE_PSRING }, 'i' }, 14780 { { STATE_EXCVADDR }, 'i' } 14781 }; 14782 14783 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = { 14784 { { OPERAND_art }, 'i' } 14785 }; 14786 14787 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = { 14788 { { STATE_PSEXCM }, 'i' }, 14789 { { STATE_PSRING }, 'i' }, 14790 { { STATE_EXCVADDR }, 'o' } 14791 }; 14792 14793 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = { 14794 { { OPERAND_art }, 'm' } 14795 }; 14796 14797 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = { 14798 { { STATE_PSEXCM }, 'i' }, 14799 { { STATE_PSRING }, 'i' }, 14800 { { STATE_EXCVADDR }, 'm' } 14801 }; 14802 14803 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = { 14804 { { OPERAND_art }, 'o' } 14805 }; 14806 14807 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = { 14808 { { STATE_PSEXCM }, 'i' }, 14809 { { STATE_PSRING }, 'i' }, 14810 { { STATE_DEPC }, 'i' } 14811 }; 14812 14813 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = { 14814 { { OPERAND_art }, 'i' } 14815 }; 14816 14817 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = { 14818 { { STATE_PSEXCM }, 'i' }, 14819 { { STATE_PSRING }, 'i' }, 14820 { { STATE_DEPC }, 'o' } 14821 }; 14822 14823 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = { 14824 { { OPERAND_art }, 'm' } 14825 }; 14826 14827 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = { 14828 { { STATE_PSEXCM }, 'i' }, 14829 { { STATE_PSRING }, 'i' }, 14830 { { STATE_DEPC }, 'm' } 14831 }; 14832 14833 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = { 14834 { { OPERAND_art }, 'o' } 14835 }; 14836 14837 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = { 14838 { { STATE_PSEXCM }, 'i' }, 14839 { { STATE_PSRING }, 'i' }, 14840 { { STATE_EXCCAUSE }, 'i' }, 14841 { { STATE_XTSYNC }, 'i' } 14842 }; 14843 14844 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = { 14845 { { OPERAND_art }, 'i' } 14846 }; 14847 14848 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = { 14849 { { STATE_PSEXCM }, 'i' }, 14850 { { STATE_PSRING }, 'i' }, 14851 { { STATE_EXCCAUSE }, 'o' } 14852 }; 14853 14854 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = { 14855 { { OPERAND_art }, 'm' } 14856 }; 14857 14858 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = { 14859 { { STATE_PSEXCM }, 'i' }, 14860 { { STATE_PSRING }, 'i' }, 14861 { { STATE_EXCCAUSE }, 'm' } 14862 }; 14863 14864 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = { 14865 { { OPERAND_art }, 'o' } 14866 }; 14867 14868 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = { 14869 { { STATE_PSEXCM }, 'i' }, 14870 { { STATE_PSRING }, 'i' }, 14871 { { STATE_MISC0 }, 'i' } 14872 }; 14873 14874 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = { 14875 { { OPERAND_art }, 'i' } 14876 }; 14877 14878 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = { 14879 { { STATE_PSEXCM }, 'i' }, 14880 { { STATE_PSRING }, 'i' }, 14881 { { STATE_MISC0 }, 'o' } 14882 }; 14883 14884 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = { 14885 { { OPERAND_art }, 'm' } 14886 }; 14887 14888 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = { 14889 { { STATE_PSEXCM }, 'i' }, 14890 { { STATE_PSRING }, 'i' }, 14891 { { STATE_MISC0 }, 'm' } 14892 }; 14893 14894 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = { 14895 { { OPERAND_art }, 'o' } 14896 }; 14897 14898 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = { 14899 { { STATE_PSEXCM }, 'i' }, 14900 { { STATE_PSRING }, 'i' }, 14901 { { STATE_MISC1 }, 'i' } 14902 }; 14903 14904 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = { 14905 { { OPERAND_art }, 'i' } 14906 }; 14907 14908 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = { 14909 { { STATE_PSEXCM }, 'i' }, 14910 { { STATE_PSRING }, 'i' }, 14911 { { STATE_MISC1 }, 'o' } 14912 }; 14913 14914 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = { 14915 { { OPERAND_art }, 'm' } 14916 }; 14917 14918 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = { 14919 { { STATE_PSEXCM }, 'i' }, 14920 { { STATE_PSRING }, 'i' }, 14921 { { STATE_MISC1 }, 'm' } 14922 }; 14923 14924 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = { 14925 { { OPERAND_art }, 'o' } 14926 }; 14927 14928 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = { 14929 { { STATE_PSEXCM }, 'i' }, 14930 { { STATE_PSRING }, 'i' } 14931 }; 14932 14933 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = { 14934 { { OPERAND_art }, 'o' } 14935 }; 14936 14937 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = { 14938 { { STATE_PSEXCM }, 'i' }, 14939 { { STATE_PSRING }, 'i' }, 14940 { { STATE_VECBASE }, 'i' } 14941 }; 14942 14943 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = { 14944 { { OPERAND_art }, 'i' } 14945 }; 14946 14947 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = { 14948 { { STATE_PSEXCM }, 'i' }, 14949 { { STATE_PSRING }, 'i' }, 14950 { { STATE_VECBASE }, 'o' } 14951 }; 14952 14953 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = { 14954 { { OPERAND_art }, 'm' } 14955 }; 14956 14957 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = { 14958 { { STATE_PSEXCM }, 'i' }, 14959 { { STATE_PSRING }, 'i' }, 14960 { { STATE_VECBASE }, 'm' } 14961 }; 14962 14963 static xtensa_arg_internal Iclass_xt_mul16_args[] = { 14964 { { OPERAND_arr }, 'o' }, 14965 { { OPERAND_ars }, 'i' }, 14966 { { OPERAND_art }, 'i' } 14967 }; 14968 14969 static xtensa_arg_internal Iclass_xt_mul32_args[] = { 14970 { { OPERAND_arr }, 'o' }, 14971 { { OPERAND_ars }, 'i' }, 14972 { { OPERAND_art }, 'i' } 14973 }; 14974 14975 static xtensa_arg_internal Iclass_xt_mul32h_args[] = { 14976 { { OPERAND_arr }, 'o' }, 14977 { { OPERAND_ars }, 'i' }, 14978 { { OPERAND_art }, 'i' } 14979 }; 14980 14981 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = { 14982 { { OPERAND_ars }, 'i' }, 14983 { { OPERAND_art }, 'i' } 14984 }; 14985 14986 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = { 14987 { { STATE_ACC }, 'o' } 14988 }; 14989 14990 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = { 14991 { { OPERAND_ars }, 'i' }, 14992 { { OPERAND_my }, 'i' } 14993 }; 14994 14995 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = { 14996 { { STATE_ACC }, 'o' } 14997 }; 14998 14999 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = { 15000 { { OPERAND_mx }, 'i' }, 15001 { { OPERAND_art }, 'i' } 15002 }; 15003 15004 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = { 15005 { { STATE_ACC }, 'o' } 15006 }; 15007 15008 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = { 15009 { { OPERAND_mx }, 'i' }, 15010 { { OPERAND_my }, 'i' } 15011 }; 15012 15013 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = { 15014 { { STATE_ACC }, 'o' } 15015 }; 15016 15017 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = { 15018 { { OPERAND_ars }, 'i' }, 15019 { { OPERAND_art }, 'i' } 15020 }; 15021 15022 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = { 15023 { { STATE_ACC }, 'm' } 15024 }; 15025 15026 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = { 15027 { { OPERAND_ars }, 'i' }, 15028 { { OPERAND_my }, 'i' } 15029 }; 15030 15031 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = { 15032 { { STATE_ACC }, 'm' } 15033 }; 15034 15035 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = { 15036 { { OPERAND_mx }, 'i' }, 15037 { { OPERAND_art }, 'i' } 15038 }; 15039 15040 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = { 15041 { { STATE_ACC }, 'm' } 15042 }; 15043 15044 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = { 15045 { { OPERAND_mx }, 'i' }, 15046 { { OPERAND_my }, 'i' } 15047 }; 15048 15049 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = { 15050 { { STATE_ACC }, 'm' } 15051 }; 15052 15053 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = { 15054 { { OPERAND_mw }, 'o' }, 15055 { { OPERAND_ars }, 'm' }, 15056 { { OPERAND_mx }, 'i' }, 15057 { { OPERAND_art }, 'i' } 15058 }; 15059 15060 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = { 15061 { { STATE_ACC }, 'm' } 15062 }; 15063 15064 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = { 15065 { { OPERAND_mw }, 'o' }, 15066 { { OPERAND_ars }, 'm' }, 15067 { { OPERAND_mx }, 'i' }, 15068 { { OPERAND_my }, 'i' } 15069 }; 15070 15071 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = { 15072 { { STATE_ACC }, 'm' } 15073 }; 15074 15075 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = { 15076 { { OPERAND_mw }, 'o' }, 15077 { { OPERAND_ars }, 'm' } 15078 }; 15079 15080 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = { 15081 { { OPERAND_art }, 'o' }, 15082 { { OPERAND_mr0 }, 'i' } 15083 }; 15084 15085 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = { 15086 { { OPERAND_art }, 'i' }, 15087 { { OPERAND_mr0 }, 'o' } 15088 }; 15089 15090 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = { 15091 { { OPERAND_art }, 'm' }, 15092 { { OPERAND_mr0 }, 'm' } 15093 }; 15094 15095 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = { 15096 { { OPERAND_art }, 'o' }, 15097 { { OPERAND_mr1 }, 'i' } 15098 }; 15099 15100 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = { 15101 { { OPERAND_art }, 'i' }, 15102 { { OPERAND_mr1 }, 'o' } 15103 }; 15104 15105 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = { 15106 { { OPERAND_art }, 'm' }, 15107 { { OPERAND_mr1 }, 'm' } 15108 }; 15109 15110 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = { 15111 { { OPERAND_art }, 'o' }, 15112 { { OPERAND_mr2 }, 'i' } 15113 }; 15114 15115 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = { 15116 { { OPERAND_art }, 'i' }, 15117 { { OPERAND_mr2 }, 'o' } 15118 }; 15119 15120 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = { 15121 { { OPERAND_art }, 'm' }, 15122 { { OPERAND_mr2 }, 'm' } 15123 }; 15124 15125 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = { 15126 { { OPERAND_art }, 'o' }, 15127 { { OPERAND_mr3 }, 'i' } 15128 }; 15129 15130 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = { 15131 { { OPERAND_art }, 'i' }, 15132 { { OPERAND_mr3 }, 'o' } 15133 }; 15134 15135 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = { 15136 { { OPERAND_art }, 'm' }, 15137 { { OPERAND_mr3 }, 'm' } 15138 }; 15139 15140 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = { 15141 { { OPERAND_art }, 'o' } 15142 }; 15143 15144 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = { 15145 { { STATE_ACC }, 'i' } 15146 }; 15147 15148 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = { 15149 { { OPERAND_art }, 'i' } 15150 }; 15151 15152 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = { 15153 { { STATE_ACC }, 'm' } 15154 }; 15155 15156 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = { 15157 { { OPERAND_art }, 'm' } 15158 }; 15159 15160 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = { 15161 { { STATE_ACC }, 'm' } 15162 }; 15163 15164 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = { 15165 { { OPERAND_art }, 'o' } 15166 }; 15167 15168 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = { 15169 { { STATE_ACC }, 'i' } 15170 }; 15171 15172 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = { 15173 { { OPERAND_art }, 'i' } 15174 }; 15175 15176 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = { 15177 { { STATE_ACC }, 'm' } 15178 }; 15179 15180 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = { 15181 { { OPERAND_art }, 'm' } 15182 }; 15183 15184 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = { 15185 { { STATE_ACC }, 'm' } 15186 }; 15187 15188 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = { 15189 { { OPERAND_s }, 'i' } 15190 }; 15191 15192 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = { 15193 { { STATE_PSWOE }, 'o' }, 15194 { { STATE_PSCALLINC }, 'o' }, 15195 { { STATE_PSOWB }, 'o' }, 15196 { { STATE_PSRING }, 'm' }, 15197 { { STATE_PSUM }, 'o' }, 15198 { { STATE_PSEXCM }, 'm' }, 15199 { { STATE_PSINTLEVEL }, 'o' }, 15200 { { STATE_EPC1 }, 'i' }, 15201 { { STATE_EPC2 }, 'i' }, 15202 { { STATE_EPC3 }, 'i' }, 15203 { { STATE_EPC4 }, 'i' }, 15204 { { STATE_EPC5 }, 'i' }, 15205 { { STATE_EPC6 }, 'i' }, 15206 { { STATE_EPC7 }, 'i' }, 15207 { { STATE_EPS2 }, 'i' }, 15208 { { STATE_EPS3 }, 'i' }, 15209 { { STATE_EPS4 }, 'i' }, 15210 { { STATE_EPS5 }, 'i' }, 15211 { { STATE_EPS6 }, 'i' }, 15212 { { STATE_EPS7 }, 'i' }, 15213 { { STATE_InOCDMode }, 'm' } 15214 }; 15215 15216 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = { 15217 { { OPERAND_s }, 'i' } 15218 }; 15219 15220 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = { 15221 { { STATE_PSEXCM }, 'i' }, 15222 { { STATE_PSRING }, 'i' }, 15223 { { STATE_PSINTLEVEL }, 'o' } 15224 }; 15225 15226 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = { 15227 { { OPERAND_art }, 'o' } 15228 }; 15229 15230 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = { 15231 { { STATE_PSEXCM }, 'i' }, 15232 { { STATE_PSRING }, 'i' }, 15233 { { STATE_INTERRUPT }, 'i' } 15234 }; 15235 15236 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = { 15237 { { OPERAND_art }, 'i' } 15238 }; 15239 15240 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = { 15241 { { STATE_PSEXCM }, 'i' }, 15242 { { STATE_PSRING }, 'i' }, 15243 { { STATE_XTSYNC }, 'o' }, 15244 { { STATE_INTERRUPT }, 'm' } 15245 }; 15246 15247 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = { 15248 { { OPERAND_art }, 'i' } 15249 }; 15250 15251 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = { 15252 { { STATE_PSEXCM }, 'i' }, 15253 { { STATE_PSRING }, 'i' }, 15254 { { STATE_XTSYNC }, 'o' }, 15255 { { STATE_INTERRUPT }, 'm' } 15256 }; 15257 15258 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = { 15259 { { OPERAND_art }, 'o' } 15260 }; 15261 15262 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = { 15263 { { STATE_PSEXCM }, 'i' }, 15264 { { STATE_PSRING }, 'i' }, 15265 { { STATE_INTENABLE }, 'i' } 15266 }; 15267 15268 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = { 15269 { { OPERAND_art }, 'i' } 15270 }; 15271 15272 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = { 15273 { { STATE_PSEXCM }, 'i' }, 15274 { { STATE_PSRING }, 'i' }, 15275 { { STATE_INTENABLE }, 'o' } 15276 }; 15277 15278 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = { 15279 { { OPERAND_art }, 'm' } 15280 }; 15281 15282 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = { 15283 { { STATE_PSEXCM }, 'i' }, 15284 { { STATE_PSRING }, 'i' }, 15285 { { STATE_INTENABLE }, 'm' } 15286 }; 15287 15288 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = { 15289 { { OPERAND_imms }, 'i' }, 15290 { { OPERAND_immt }, 'i' } 15291 }; 15292 15293 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = { 15294 { { STATE_PSEXCM }, 'i' }, 15295 { { STATE_PSINTLEVEL }, 'i' } 15296 }; 15297 15298 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = { 15299 { { OPERAND_imms }, 'i' } 15300 }; 15301 15302 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = { 15303 { { STATE_PSEXCM }, 'i' }, 15304 { { STATE_PSINTLEVEL }, 'i' } 15305 }; 15306 15307 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = { 15308 { { OPERAND_art }, 'o' } 15309 }; 15310 15311 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = { 15312 { { STATE_PSEXCM }, 'i' }, 15313 { { STATE_PSRING }, 'i' }, 15314 { { STATE_DBREAKA0 }, 'i' } 15315 }; 15316 15317 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = { 15318 { { OPERAND_art }, 'i' } 15319 }; 15320 15321 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = { 15322 { { STATE_PSEXCM }, 'i' }, 15323 { { STATE_PSRING }, 'i' }, 15324 { { STATE_DBREAKA0 }, 'o' }, 15325 { { STATE_XTSYNC }, 'o' } 15326 }; 15327 15328 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = { 15329 { { OPERAND_art }, 'm' } 15330 }; 15331 15332 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = { 15333 { { STATE_PSEXCM }, 'i' }, 15334 { { STATE_PSRING }, 'i' }, 15335 { { STATE_DBREAKA0 }, 'm' }, 15336 { { STATE_XTSYNC }, 'o' } 15337 }; 15338 15339 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = { 15340 { { OPERAND_art }, 'o' } 15341 }; 15342 15343 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = { 15344 { { STATE_PSEXCM }, 'i' }, 15345 { { STATE_PSRING }, 'i' }, 15346 { { STATE_DBREAKC0 }, 'i' } 15347 }; 15348 15349 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = { 15350 { { OPERAND_art }, 'i' } 15351 }; 15352 15353 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = { 15354 { { STATE_PSEXCM }, 'i' }, 15355 { { STATE_PSRING }, 'i' }, 15356 { { STATE_DBREAKC0 }, 'o' }, 15357 { { STATE_XTSYNC }, 'o' } 15358 }; 15359 15360 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = { 15361 { { OPERAND_art }, 'm' } 15362 }; 15363 15364 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = { 15365 { { STATE_PSEXCM }, 'i' }, 15366 { { STATE_PSRING }, 'i' }, 15367 { { STATE_DBREAKC0 }, 'm' }, 15368 { { STATE_XTSYNC }, 'o' } 15369 }; 15370 15371 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = { 15372 { { OPERAND_art }, 'o' } 15373 }; 15374 15375 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = { 15376 { { STATE_PSEXCM }, 'i' }, 15377 { { STATE_PSRING }, 'i' }, 15378 { { STATE_DBREAKA1 }, 'i' } 15379 }; 15380 15381 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = { 15382 { { OPERAND_art }, 'i' } 15383 }; 15384 15385 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = { 15386 { { STATE_PSEXCM }, 'i' }, 15387 { { STATE_PSRING }, 'i' }, 15388 { { STATE_DBREAKA1 }, 'o' }, 15389 { { STATE_XTSYNC }, 'o' } 15390 }; 15391 15392 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = { 15393 { { OPERAND_art }, 'm' } 15394 }; 15395 15396 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = { 15397 { { STATE_PSEXCM }, 'i' }, 15398 { { STATE_PSRING }, 'i' }, 15399 { { STATE_DBREAKA1 }, 'm' }, 15400 { { STATE_XTSYNC }, 'o' } 15401 }; 15402 15403 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = { 15404 { { OPERAND_art }, 'o' } 15405 }; 15406 15407 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = { 15408 { { STATE_PSEXCM }, 'i' }, 15409 { { STATE_PSRING }, 'i' }, 15410 { { STATE_DBREAKC1 }, 'i' } 15411 }; 15412 15413 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = { 15414 { { OPERAND_art }, 'i' } 15415 }; 15416 15417 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = { 15418 { { STATE_PSEXCM }, 'i' }, 15419 { { STATE_PSRING }, 'i' }, 15420 { { STATE_DBREAKC1 }, 'o' }, 15421 { { STATE_XTSYNC }, 'o' } 15422 }; 15423 15424 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = { 15425 { { OPERAND_art }, 'm' } 15426 }; 15427 15428 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = { 15429 { { STATE_PSEXCM }, 'i' }, 15430 { { STATE_PSRING }, 'i' }, 15431 { { STATE_DBREAKC1 }, 'm' }, 15432 { { STATE_XTSYNC }, 'o' } 15433 }; 15434 15435 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = { 15436 { { OPERAND_art }, 'o' } 15437 }; 15438 15439 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = { 15440 { { STATE_PSEXCM }, 'i' }, 15441 { { STATE_PSRING }, 'i' }, 15442 { { STATE_IBREAKA0 }, 'i' } 15443 }; 15444 15445 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = { 15446 { { OPERAND_art }, 'i' } 15447 }; 15448 15449 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = { 15450 { { STATE_PSEXCM }, 'i' }, 15451 { { STATE_PSRING }, 'i' }, 15452 { { STATE_IBREAKA0 }, 'o' } 15453 }; 15454 15455 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = { 15456 { { OPERAND_art }, 'm' } 15457 }; 15458 15459 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = { 15460 { { STATE_PSEXCM }, 'i' }, 15461 { { STATE_PSRING }, 'i' }, 15462 { { STATE_IBREAKA0 }, 'm' } 15463 }; 15464 15465 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = { 15466 { { OPERAND_art }, 'o' } 15467 }; 15468 15469 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = { 15470 { { STATE_PSEXCM }, 'i' }, 15471 { { STATE_PSRING }, 'i' }, 15472 { { STATE_IBREAKA1 }, 'i' } 15473 }; 15474 15475 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = { 15476 { { OPERAND_art }, 'i' } 15477 }; 15478 15479 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = { 15480 { { STATE_PSEXCM }, 'i' }, 15481 { { STATE_PSRING }, 'i' }, 15482 { { STATE_IBREAKA1 }, 'o' } 15483 }; 15484 15485 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = { 15486 { { OPERAND_art }, 'm' } 15487 }; 15488 15489 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = { 15490 { { STATE_PSEXCM }, 'i' }, 15491 { { STATE_PSRING }, 'i' }, 15492 { { STATE_IBREAKA1 }, 'm' } 15493 }; 15494 15495 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = { 15496 { { OPERAND_art }, 'o' } 15497 }; 15498 15499 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = { 15500 { { STATE_PSEXCM }, 'i' }, 15501 { { STATE_PSRING }, 'i' }, 15502 { { STATE_IBREAKENABLE }, 'i' } 15503 }; 15504 15505 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = { 15506 { { OPERAND_art }, 'i' } 15507 }; 15508 15509 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = { 15510 { { STATE_PSEXCM }, 'i' }, 15511 { { STATE_PSRING }, 'i' }, 15512 { { STATE_IBREAKENABLE }, 'o' } 15513 }; 15514 15515 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = { 15516 { { OPERAND_art }, 'm' } 15517 }; 15518 15519 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = { 15520 { { STATE_PSEXCM }, 'i' }, 15521 { { STATE_PSRING }, 'i' }, 15522 { { STATE_IBREAKENABLE }, 'm' } 15523 }; 15524 15525 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = { 15526 { { OPERAND_art }, 'o' } 15527 }; 15528 15529 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = { 15530 { { STATE_PSEXCM }, 'i' }, 15531 { { STATE_PSRING }, 'i' }, 15532 { { STATE_DEBUGCAUSE }, 'i' }, 15533 { { STATE_DBNUM }, 'i' } 15534 }; 15535 15536 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = { 15537 { { OPERAND_art }, 'i' } 15538 }; 15539 15540 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = { 15541 { { STATE_PSEXCM }, 'i' }, 15542 { { STATE_PSRING }, 'i' }, 15543 { { STATE_DEBUGCAUSE }, 'o' }, 15544 { { STATE_DBNUM }, 'o' } 15545 }; 15546 15547 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = { 15548 { { OPERAND_art }, 'm' } 15549 }; 15550 15551 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = { 15552 { { STATE_PSEXCM }, 'i' }, 15553 { { STATE_PSRING }, 'i' }, 15554 { { STATE_DEBUGCAUSE }, 'm' }, 15555 { { STATE_DBNUM }, 'm' } 15556 }; 15557 15558 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = { 15559 { { OPERAND_art }, 'o' } 15560 }; 15561 15562 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = { 15563 { { STATE_PSEXCM }, 'i' }, 15564 { { STATE_PSRING }, 'i' }, 15565 { { STATE_ICOUNT }, 'i' } 15566 }; 15567 15568 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = { 15569 { { OPERAND_art }, 'i' } 15570 }; 15571 15572 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = { 15573 { { STATE_PSEXCM }, 'i' }, 15574 { { STATE_PSRING }, 'i' }, 15575 { { STATE_XTSYNC }, 'o' }, 15576 { { STATE_ICOUNT }, 'o' } 15577 }; 15578 15579 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = { 15580 { { OPERAND_art }, 'm' } 15581 }; 15582 15583 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = { 15584 { { STATE_PSEXCM }, 'i' }, 15585 { { STATE_PSRING }, 'i' }, 15586 { { STATE_XTSYNC }, 'o' }, 15587 { { STATE_ICOUNT }, 'm' } 15588 }; 15589 15590 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = { 15591 { { OPERAND_art }, 'o' } 15592 }; 15593 15594 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = { 15595 { { STATE_PSEXCM }, 'i' }, 15596 { { STATE_PSRING }, 'i' }, 15597 { { STATE_ICOUNTLEVEL }, 'i' } 15598 }; 15599 15600 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = { 15601 { { OPERAND_art }, 'i' } 15602 }; 15603 15604 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = { 15605 { { STATE_PSEXCM }, 'i' }, 15606 { { STATE_PSRING }, 'i' }, 15607 { { STATE_ICOUNTLEVEL }, 'o' } 15608 }; 15609 15610 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = { 15611 { { OPERAND_art }, 'm' } 15612 }; 15613 15614 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = { 15615 { { STATE_PSEXCM }, 'i' }, 15616 { { STATE_PSRING }, 'i' }, 15617 { { STATE_ICOUNTLEVEL }, 'm' } 15618 }; 15619 15620 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = { 15621 { { OPERAND_art }, 'o' } 15622 }; 15623 15624 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = { 15625 { { STATE_PSEXCM }, 'i' }, 15626 { { STATE_PSRING }, 'i' }, 15627 { { STATE_DDR }, 'i' } 15628 }; 15629 15630 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = { 15631 { { OPERAND_art }, 'i' } 15632 }; 15633 15634 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = { 15635 { { STATE_PSEXCM }, 'i' }, 15636 { { STATE_PSRING }, 'i' }, 15637 { { STATE_XTSYNC }, 'o' }, 15638 { { STATE_DDR }, 'o' } 15639 }; 15640 15641 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = { 15642 { { OPERAND_art }, 'm' } 15643 }; 15644 15645 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = { 15646 { { STATE_PSEXCM }, 'i' }, 15647 { { STATE_PSRING }, 'i' }, 15648 { { STATE_XTSYNC }, 'o' }, 15649 { { STATE_DDR }, 'm' } 15650 }; 15651 15652 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = { 15653 { { OPERAND_ars }, 'm' } 15654 }; 15655 15656 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = { 15657 { { STATE_PSEXCM }, 'i' }, 15658 { { STATE_PSRING }, 'i' }, 15659 { { STATE_XTSYNC }, 'o' }, 15660 { { STATE_InOCDMode }, 'i' }, 15661 { { STATE_DDR }, 'o' } 15662 }; 15663 15664 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = { 15665 { { OPERAND_ars }, 'm' } 15666 }; 15667 15668 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = { 15669 { { STATE_PSEXCM }, 'i' }, 15670 { { STATE_PSRING }, 'i' }, 15671 { { STATE_InOCDMode }, 'i' }, 15672 { { STATE_DDR }, 'i' } 15673 }; 15674 15675 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = { 15676 { { OPERAND_imms }, 'i' } 15677 }; 15678 15679 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = { 15680 { { STATE_InOCDMode }, 'm' }, 15681 { { STATE_EPC6 }, 'i' }, 15682 { { STATE_PSWOE }, 'o' }, 15683 { { STATE_PSCALLINC }, 'o' }, 15684 { { STATE_PSOWB }, 'o' }, 15685 { { STATE_PSRING }, 'o' }, 15686 { { STATE_PSUM }, 'o' }, 15687 { { STATE_PSEXCM }, 'o' }, 15688 { { STATE_PSINTLEVEL }, 'o' }, 15689 { { STATE_EPS6 }, 'i' } 15690 }; 15691 15692 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = { 15693 { { STATE_InOCDMode }, 'm' } 15694 }; 15695 15696 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = { 15697 { { OPERAND_art }, 'i' } 15698 }; 15699 15700 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = { 15701 { { STATE_PSEXCM }, 'i' }, 15702 { { STATE_PSRING }, 'i' }, 15703 { { STATE_XTSYNC }, 'o' } 15704 }; 15705 15706 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = { 15707 { { OPERAND_br }, 'o' }, 15708 { { OPERAND_bs }, 'i' }, 15709 { { OPERAND_bt }, 'i' } 15710 }; 15711 15712 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = { 15713 { { OPERAND_bt }, 'o' }, 15714 { { OPERAND_bs4 }, 'i' } 15715 }; 15716 15717 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = { 15718 { { OPERAND_bt }, 'o' }, 15719 { { OPERAND_bs8 }, 'i' } 15720 }; 15721 15722 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = { 15723 { { OPERAND_bs }, 'i' }, 15724 { { OPERAND_label8 }, 'i' } 15725 }; 15726 15727 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = { 15728 { { OPERAND_arr }, 'm' }, 15729 { { OPERAND_ars }, 'i' }, 15730 { { OPERAND_bt }, 'i' } 15731 }; 15732 15733 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = { 15734 { { OPERAND_art }, 'o' }, 15735 { { OPERAND_brall }, 'i' } 15736 }; 15737 15738 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = { 15739 { { OPERAND_art }, 'i' }, 15740 { { OPERAND_brall }, 'o' } 15741 }; 15742 15743 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = { 15744 { { OPERAND_art }, 'm' }, 15745 { { OPERAND_brall }, 'm' } 15746 }; 15747 15748 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = { 15749 { { OPERAND_art }, 'o' } 15750 }; 15751 15752 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = { 15753 { { STATE_PSEXCM }, 'i' }, 15754 { { STATE_PSRING }, 'i' }, 15755 { { STATE_CCOUNT }, 'i' } 15756 }; 15757 15758 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = { 15759 { { OPERAND_art }, 'i' } 15760 }; 15761 15762 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = { 15763 { { STATE_PSEXCM }, 'i' }, 15764 { { STATE_PSRING }, 'i' }, 15765 { { STATE_XTSYNC }, 'o' }, 15766 { { STATE_CCOUNT }, 'o' } 15767 }; 15768 15769 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = { 15770 { { OPERAND_art }, 'm' } 15771 }; 15772 15773 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = { 15774 { { STATE_PSEXCM }, 'i' }, 15775 { { STATE_PSRING }, 'i' }, 15776 { { STATE_XTSYNC }, 'o' }, 15777 { { STATE_CCOUNT }, 'm' } 15778 }; 15779 15780 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = { 15781 { { OPERAND_art }, 'o' } 15782 }; 15783 15784 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = { 15785 { { STATE_PSEXCM }, 'i' }, 15786 { { STATE_PSRING }, 'i' }, 15787 { { STATE_CCOMPARE0 }, 'i' } 15788 }; 15789 15790 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = { 15791 { { OPERAND_art }, 'i' } 15792 }; 15793 15794 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = { 15795 { { STATE_PSEXCM }, 'i' }, 15796 { { STATE_PSRING }, 'i' }, 15797 { { STATE_CCOMPARE0 }, 'o' }, 15798 { { STATE_INTERRUPT }, 'm' } 15799 }; 15800 15801 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = { 15802 { { OPERAND_art }, 'm' } 15803 }; 15804 15805 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = { 15806 { { STATE_PSEXCM }, 'i' }, 15807 { { STATE_PSRING }, 'i' }, 15808 { { STATE_CCOMPARE0 }, 'm' }, 15809 { { STATE_INTERRUPT }, 'm' } 15810 }; 15811 15812 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = { 15813 { { OPERAND_art }, 'o' } 15814 }; 15815 15816 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = { 15817 { { STATE_PSEXCM }, 'i' }, 15818 { { STATE_PSRING }, 'i' }, 15819 { { STATE_CCOMPARE1 }, 'i' } 15820 }; 15821 15822 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = { 15823 { { OPERAND_art }, 'i' } 15824 }; 15825 15826 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = { 15827 { { STATE_PSEXCM }, 'i' }, 15828 { { STATE_PSRING }, 'i' }, 15829 { { STATE_CCOMPARE1 }, 'o' }, 15830 { { STATE_INTERRUPT }, 'm' } 15831 }; 15832 15833 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = { 15834 { { OPERAND_art }, 'm' } 15835 }; 15836 15837 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = { 15838 { { STATE_PSEXCM }, 'i' }, 15839 { { STATE_PSRING }, 'i' }, 15840 { { STATE_CCOMPARE1 }, 'm' }, 15841 { { STATE_INTERRUPT }, 'm' } 15842 }; 15843 15844 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = { 15845 { { OPERAND_art }, 'o' } 15846 }; 15847 15848 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = { 15849 { { STATE_PSEXCM }, 'i' }, 15850 { { STATE_PSRING }, 'i' }, 15851 { { STATE_CCOMPARE2 }, 'i' } 15852 }; 15853 15854 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = { 15855 { { OPERAND_art }, 'i' } 15856 }; 15857 15858 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = { 15859 { { STATE_PSEXCM }, 'i' }, 15860 { { STATE_PSRING }, 'i' }, 15861 { { STATE_CCOMPARE2 }, 'o' }, 15862 { { STATE_INTERRUPT }, 'm' } 15863 }; 15864 15865 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = { 15866 { { OPERAND_art }, 'm' } 15867 }; 15868 15869 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = { 15870 { { STATE_PSEXCM }, 'i' }, 15871 { { STATE_PSRING }, 'i' }, 15872 { { STATE_CCOMPARE2 }, 'm' }, 15873 { { STATE_INTERRUPT }, 'm' } 15874 }; 15875 15876 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = { 15877 { { OPERAND_ars }, 'i' }, 15878 { { OPERAND_uimm8x4 }, 'i' } 15879 }; 15880 15881 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = { 15882 { { OPERAND_ars }, 'i' }, 15883 { { OPERAND_uimm4x16 }, 'i' } 15884 }; 15885 15886 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = { 15887 { { STATE_PSEXCM }, 'i' }, 15888 { { STATE_PSRING }, 'i' } 15889 }; 15890 15891 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = { 15892 { { OPERAND_ars }, 'i' }, 15893 { { OPERAND_uimm8x4 }, 'i' } 15894 }; 15895 15896 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = { 15897 { { STATE_PSEXCM }, 'i' }, 15898 { { STATE_PSRING }, 'i' } 15899 }; 15900 15901 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = { 15902 { { OPERAND_art }, 'o' }, 15903 { { OPERAND_ars }, 'i' } 15904 }; 15905 15906 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = { 15907 { { STATE_PSEXCM }, 'i' }, 15908 { { STATE_PSRING }, 'i' } 15909 }; 15910 15911 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = { 15912 { { OPERAND_art }, 'i' }, 15913 { { OPERAND_ars }, 'i' } 15914 }; 15915 15916 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = { 15917 { { STATE_PSEXCM }, 'i' }, 15918 { { STATE_PSRING }, 'i' } 15919 }; 15920 15921 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = { 15922 { { OPERAND_ars }, 'i' }, 15923 { { OPERAND_uimm8x4 }, 'i' } 15924 }; 15925 15926 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = { 15927 { { OPERAND_ars }, 'm' } 15928 }; 15929 15930 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = { 15931 { { STATE_PSEXCM }, 'i' }, 15932 { { STATE_PSRING }, 'i' } 15933 }; 15934 15935 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = { 15936 { { OPERAND_ars }, 'i' }, 15937 { { OPERAND_uimm4x16 }, 'i' } 15938 }; 15939 15940 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = { 15941 { { STATE_PSEXCM }, 'i' }, 15942 { { STATE_PSRING }, 'i' } 15943 }; 15944 15945 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = { 15946 { { OPERAND_ars }, 'i' }, 15947 { { OPERAND_uimm8x4 }, 'i' } 15948 }; 15949 15950 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = { 15951 { { STATE_PSEXCM }, 'i' }, 15952 { { STATE_PSRING }, 'i' } 15953 }; 15954 15955 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = { 15956 { { OPERAND_ars }, 'i' }, 15957 { { OPERAND_uimm8x4 }, 'i' } 15958 }; 15959 15960 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = { 15961 { { OPERAND_ars }, 'i' }, 15962 { { OPERAND_uimm4x16 }, 'i' } 15963 }; 15964 15965 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = { 15966 { { STATE_PSEXCM }, 'i' }, 15967 { { STATE_PSRING }, 'i' } 15968 }; 15969 15970 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = { 15971 { { OPERAND_art }, 'i' }, 15972 { { OPERAND_ars }, 'i' } 15973 }; 15974 15975 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = { 15976 { { STATE_PSEXCM }, 'i' }, 15977 { { STATE_PSRING }, 'i' } 15978 }; 15979 15980 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = { 15981 { { OPERAND_art }, 'o' }, 15982 { { OPERAND_ars }, 'i' } 15983 }; 15984 15985 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = { 15986 { { STATE_PSEXCM }, 'i' }, 15987 { { STATE_PSRING }, 'i' } 15988 }; 15989 15990 static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_args[] = { 15991 { { OPERAND_art }, 'o' } 15992 }; 15993 15994 static xtensa_arg_internal Iclass_xt_iclass_rsr_prefctl_stateArgs[] = { 15995 { { STATE_PREFCTL }, 'i' } 15996 }; 15997 15998 static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_args[] = { 15999 { { OPERAND_art }, 'i' } 16000 }; 16001 16002 static xtensa_arg_internal Iclass_xt_iclass_wsr_prefctl_stateArgs[] = { 16003 { { STATE_PREFCTL }, 'o' } 16004 }; 16005 16006 static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_args[] = { 16007 { { OPERAND_art }, 'm' } 16008 }; 16009 16010 static xtensa_arg_internal Iclass_xt_iclass_xsr_prefctl_stateArgs[] = { 16011 { { STATE_PREFCTL }, 'm' } 16012 }; 16013 16014 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = { 16015 { { OPERAND_art }, 'i' } 16016 }; 16017 16018 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = { 16019 { { STATE_PSEXCM }, 'i' }, 16020 { { STATE_PSRING }, 'i' }, 16021 { { STATE_PTBASE }, 'o' }, 16022 { { STATE_XTSYNC }, 'o' } 16023 }; 16024 16025 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = { 16026 { { OPERAND_art }, 'o' } 16027 }; 16028 16029 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = { 16030 { { STATE_PSEXCM }, 'i' }, 16031 { { STATE_PSRING }, 'i' }, 16032 { { STATE_PTBASE }, 'i' }, 16033 { { STATE_EXCVADDR }, 'i' } 16034 }; 16035 16036 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = { 16037 { { OPERAND_art }, 'm' } 16038 }; 16039 16040 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = { 16041 { { STATE_PSEXCM }, 'i' }, 16042 { { STATE_PSRING }, 'i' }, 16043 { { STATE_PTBASE }, 'm' }, 16044 { { STATE_EXCVADDR }, 'i' }, 16045 { { STATE_XTSYNC }, 'o' } 16046 }; 16047 16048 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = { 16049 { { OPERAND_art }, 'o' } 16050 }; 16051 16052 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = { 16053 { { STATE_PSEXCM }, 'i' }, 16054 { { STATE_PSRING }, 'i' }, 16055 { { STATE_ASID3 }, 'i' }, 16056 { { STATE_ASID2 }, 'i' }, 16057 { { STATE_ASID1 }, 'i' } 16058 }; 16059 16060 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = { 16061 { { OPERAND_art }, 'i' } 16062 }; 16063 16064 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = { 16065 { { STATE_XTSYNC }, 'o' }, 16066 { { STATE_PSEXCM }, 'i' }, 16067 { { STATE_PSRING }, 'i' }, 16068 { { STATE_ASID3 }, 'o' }, 16069 { { STATE_ASID2 }, 'o' }, 16070 { { STATE_ASID1 }, 'o' } 16071 }; 16072 16073 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = { 16074 { { OPERAND_art }, 'm' } 16075 }; 16076 16077 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = { 16078 { { STATE_XTSYNC }, 'o' }, 16079 { { STATE_PSEXCM }, 'i' }, 16080 { { STATE_PSRING }, 'i' }, 16081 { { STATE_ASID3 }, 'm' }, 16082 { { STATE_ASID2 }, 'm' }, 16083 { { STATE_ASID1 }, 'm' } 16084 }; 16085 16086 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = { 16087 { { OPERAND_art }, 'o' } 16088 }; 16089 16090 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = { 16091 { { STATE_PSEXCM }, 'i' }, 16092 { { STATE_PSRING }, 'i' }, 16093 { { STATE_INSTPGSZID6 }, 'i' }, 16094 { { STATE_INSTPGSZID5 }, 'i' }, 16095 { { STATE_INSTPGSZID4 }, 'i' } 16096 }; 16097 16098 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = { 16099 { { OPERAND_art }, 'i' } 16100 }; 16101 16102 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = { 16103 { { STATE_XTSYNC }, 'o' }, 16104 { { STATE_PSEXCM }, 'i' }, 16105 { { STATE_PSRING }, 'i' }, 16106 { { STATE_INSTPGSZID6 }, 'o' }, 16107 { { STATE_INSTPGSZID5 }, 'o' }, 16108 { { STATE_INSTPGSZID4 }, 'o' } 16109 }; 16110 16111 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = { 16112 { { OPERAND_art }, 'm' } 16113 }; 16114 16115 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = { 16116 { { STATE_XTSYNC }, 'o' }, 16117 { { STATE_PSEXCM }, 'i' }, 16118 { { STATE_PSRING }, 'i' }, 16119 { { STATE_INSTPGSZID6 }, 'm' }, 16120 { { STATE_INSTPGSZID5 }, 'm' }, 16121 { { STATE_INSTPGSZID4 }, 'm' } 16122 }; 16123 16124 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = { 16125 { { OPERAND_art }, 'o' } 16126 }; 16127 16128 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = { 16129 { { STATE_PSEXCM }, 'i' }, 16130 { { STATE_PSRING }, 'i' }, 16131 { { STATE_DATAPGSZID6 }, 'i' }, 16132 { { STATE_DATAPGSZID5 }, 'i' }, 16133 { { STATE_DATAPGSZID4 }, 'i' } 16134 }; 16135 16136 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = { 16137 { { OPERAND_art }, 'i' } 16138 }; 16139 16140 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = { 16141 { { STATE_XTSYNC }, 'o' }, 16142 { { STATE_PSEXCM }, 'i' }, 16143 { { STATE_PSRING }, 'i' }, 16144 { { STATE_DATAPGSZID6 }, 'o' }, 16145 { { STATE_DATAPGSZID5 }, 'o' }, 16146 { { STATE_DATAPGSZID4 }, 'o' } 16147 }; 16148 16149 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = { 16150 { { OPERAND_art }, 'm' } 16151 }; 16152 16153 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = { 16154 { { STATE_XTSYNC }, 'o' }, 16155 { { STATE_PSEXCM }, 'i' }, 16156 { { STATE_PSRING }, 'i' }, 16157 { { STATE_DATAPGSZID6 }, 'm' }, 16158 { { STATE_DATAPGSZID5 }, 'm' }, 16159 { { STATE_DATAPGSZID4 }, 'm' } 16160 }; 16161 16162 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = { 16163 { { OPERAND_ars }, 'i' } 16164 }; 16165 16166 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = { 16167 { { STATE_PSEXCM }, 'i' }, 16168 { { STATE_PSRING }, 'i' }, 16169 { { STATE_XTSYNC }, 'o' } 16170 }; 16171 16172 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = { 16173 { { OPERAND_art }, 'o' }, 16174 { { OPERAND_ars }, 'i' } 16175 }; 16176 16177 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = { 16178 { { STATE_PSEXCM }, 'i' }, 16179 { { STATE_PSRING }, 'i' } 16180 }; 16181 16182 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = { 16183 { { OPERAND_art }, 'i' }, 16184 { { OPERAND_ars }, 'i' } 16185 }; 16186 16187 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = { 16188 { { STATE_PSEXCM }, 'i' }, 16189 { { STATE_PSRING }, 'i' }, 16190 { { STATE_XTSYNC }, 'o' } 16191 }; 16192 16193 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = { 16194 { { OPERAND_ars }, 'i' } 16195 }; 16196 16197 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = { 16198 { { STATE_PSEXCM }, 'i' }, 16199 { { STATE_PSRING }, 'i' } 16200 }; 16201 16202 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = { 16203 { { OPERAND_art }, 'o' }, 16204 { { OPERAND_ars }, 'i' } 16205 }; 16206 16207 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = { 16208 { { STATE_PSEXCM }, 'i' }, 16209 { { STATE_PSRING }, 'i' } 16210 }; 16211 16212 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = { 16213 { { OPERAND_art }, 'i' }, 16214 { { OPERAND_ars }, 'i' } 16215 }; 16216 16217 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = { 16218 { { STATE_PSEXCM }, 'i' }, 16219 { { STATE_PSRING }, 'i' } 16220 }; 16221 16222 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = { 16223 { { STATE_PTBASE }, 'i' }, 16224 { { STATE_EXCVADDR }, 'i' } 16225 }; 16226 16227 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = { 16228 { { STATE_EXCVADDR }, 'i' } 16229 }; 16230 16231 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = { 16232 { { STATE_EXCVADDR }, 'i' } 16233 }; 16234 16235 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = { 16236 { { OPERAND_art }, 'o' } 16237 }; 16238 16239 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = { 16240 { { STATE_PSEXCM }, 'i' }, 16241 { { STATE_PSRING }, 'i' }, 16242 { { STATE_CPENABLE }, 'i' } 16243 }; 16244 16245 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = { 16246 { { OPERAND_art }, 'i' } 16247 }; 16248 16249 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = { 16250 { { STATE_PSEXCM }, 'i' }, 16251 { { STATE_PSRING }, 'i' }, 16252 { { STATE_CPENABLE }, 'o' } 16253 }; 16254 16255 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = { 16256 { { OPERAND_art }, 'm' } 16257 }; 16258 16259 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = { 16260 { { STATE_PSEXCM }, 'i' }, 16261 { { STATE_PSRING }, 'i' }, 16262 { { STATE_CPENABLE }, 'm' } 16263 }; 16264 16265 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = { 16266 { { OPERAND_arr }, 'o' }, 16267 { { OPERAND_ars }, 'i' }, 16268 { { OPERAND_tp7 }, 'i' } 16269 }; 16270 16271 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = { 16272 { { OPERAND_arr }, 'o' }, 16273 { { OPERAND_ars }, 'i' }, 16274 { { OPERAND_art }, 'i' } 16275 }; 16276 16277 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = { 16278 { { OPERAND_art }, 'o' }, 16279 { { OPERAND_ars }, 'i' } 16280 }; 16281 16282 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = { 16283 { { OPERAND_arr }, 'o' }, 16284 { { OPERAND_ars }, 'i' }, 16285 { { OPERAND_tp7 }, 'i' } 16286 }; 16287 16288 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = { 16289 { { OPERAND_art }, 'o' }, 16290 { { OPERAND_ars }, 'i' }, 16291 { { OPERAND_uimm8x4 }, 'i' } 16292 }; 16293 16294 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = { 16295 { { OPERAND_art }, 'i' }, 16296 { { OPERAND_ars }, 'i' }, 16297 { { OPERAND_uimm8x4 }, 'i' } 16298 }; 16299 16300 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = { 16301 { { OPERAND_art }, 'm' }, 16302 { { OPERAND_ars }, 'i' }, 16303 { { OPERAND_uimm8x4 }, 'i' } 16304 }; 16305 16306 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = { 16307 { { STATE_SCOMPARE1 }, 'i' }, 16308 { { STATE_XTSYNC }, 'i' }, 16309 { { STATE_SCOMPARE1 }, 'i' } 16310 }; 16311 16312 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = { 16313 { { OPERAND_art }, 'o' } 16314 }; 16315 16316 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = { 16317 { { STATE_SCOMPARE1 }, 'i' } 16318 }; 16319 16320 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = { 16321 { { OPERAND_art }, 'i' } 16322 }; 16323 16324 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = { 16325 { { STATE_SCOMPARE1 }, 'o' } 16326 }; 16327 16328 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = { 16329 { { OPERAND_art }, 'm' } 16330 }; 16331 16332 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = { 16333 { { STATE_SCOMPARE1 }, 'm' } 16334 }; 16335 16336 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = { 16337 { { OPERAND_art }, 'o' } 16338 }; 16339 16340 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = { 16341 { { STATE_PSEXCM }, 'i' }, 16342 { { STATE_PSRING }, 'i' }, 16343 { { STATE_ATOMCTL }, 'i' } 16344 }; 16345 16346 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = { 16347 { { OPERAND_art }, 'i' } 16348 }; 16349 16350 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = { 16351 { { STATE_PSEXCM }, 'i' }, 16352 { { STATE_PSRING }, 'i' }, 16353 { { STATE_ATOMCTL }, 'o' }, 16354 { { STATE_XTSYNC }, 'o' } 16355 }; 16356 16357 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = { 16358 { { OPERAND_art }, 'm' } 16359 }; 16360 16361 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = { 16362 { { STATE_PSEXCM }, 'i' }, 16363 { { STATE_PSRING }, 'i' }, 16364 { { STATE_ATOMCTL }, 'm' }, 16365 { { STATE_XTSYNC }, 'o' } 16366 }; 16367 16368 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = { 16369 { { OPERAND_arr }, 'o' }, 16370 { { OPERAND_ars }, 'i' }, 16371 { { OPERAND_art }, 'i' } 16372 }; 16373 16374 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = { 16375 { { OPERAND_art }, 'o' }, 16376 { { OPERAND_ars }, 'i' } 16377 }; 16378 16379 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = { 16380 { { STATE_PSEXCM }, 'i' }, 16381 { { STATE_ERI_RAW_INTERLOCK }, 'i' }, 16382 { { STATE_PSRING }, 'i' } 16383 }; 16384 16385 static xtensa_interface Iclass_xt_iclass_rer_intfArgs[] = { 16386 INTERFACE_ERI_RD_In, 16387 INTERFACE_ERI_RD_Out 16388 }; 16389 16390 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = { 16391 { { OPERAND_art }, 'i' }, 16392 { { OPERAND_ars }, 'i' } 16393 }; 16394 16395 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = { 16396 { { STATE_PSEXCM }, 'i' }, 16397 { { STATE_ERI_RAW_INTERLOCK }, 'o' }, 16398 { { STATE_PSRING }, 'i' } 16399 }; 16400 16401 static xtensa_interface Iclass_xt_iclass_wer_intfArgs[] = { 16402 INTERFACE_ERI_WR_In, 16403 INTERFACE_ERI_WR_Out 16404 }; 16405 16406 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_args[] = { 16407 { { OPERAND_arr }, 'o' } 16408 }; 16409 16410 static xtensa_arg_internal Iclass_rur_ae_ovf_sar_stateArgs[] = { 16411 { { STATE_AE_OVERFLOW }, 'i' }, 16412 { { STATE_AE_SAR }, 'i' }, 16413 { { STATE_CPENABLE }, 'i' } 16414 }; 16415 16416 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_args[] = { 16417 { { OPERAND_art }, 'i' } 16418 }; 16419 16420 static xtensa_arg_internal Iclass_wur_ae_ovf_sar_stateArgs[] = { 16421 { { STATE_AE_OVERFLOW }, 'o' }, 16422 { { STATE_AE_SAR }, 'o' }, 16423 { { STATE_CPENABLE }, 'i' } 16424 }; 16425 16426 static xtensa_arg_internal Iclass_rur_ae_bithead_args[] = { 16427 { { OPERAND_arr }, 'o' } 16428 }; 16429 16430 static xtensa_arg_internal Iclass_rur_ae_bithead_stateArgs[] = { 16431 { { STATE_AE_BITHEAD }, 'i' }, 16432 { { STATE_CPENABLE }, 'i' } 16433 }; 16434 16435 static xtensa_arg_internal Iclass_wur_ae_bithead_args[] = { 16436 { { OPERAND_art }, 'i' } 16437 }; 16438 16439 static xtensa_arg_internal Iclass_wur_ae_bithead_stateArgs[] = { 16440 { { STATE_AE_BITHEAD }, 'o' }, 16441 { { STATE_CPENABLE }, 'i' } 16442 }; 16443 16444 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_args[] = { 16445 { { OPERAND_arr }, 'o' } 16446 }; 16447 16448 static xtensa_arg_internal Iclass_rur_ae_ts_fts_bu_bp_stateArgs[] = { 16449 { { STATE_AE_BITPTR }, 'i' }, 16450 { { STATE_AE_BITSUSED }, 'i' }, 16451 { { STATE_AE_TABLESIZE }, 'i' }, 16452 { { STATE_AE_FIRST_TS }, 'i' }, 16453 { { STATE_CPENABLE }, 'i' } 16454 }; 16455 16456 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_args[] = { 16457 { { OPERAND_art }, 'i' } 16458 }; 16459 16460 static xtensa_arg_internal Iclass_wur_ae_ts_fts_bu_bp_stateArgs[] = { 16461 { { STATE_AE_BITPTR }, 'o' }, 16462 { { STATE_AE_BITSUSED }, 'o' }, 16463 { { STATE_AE_TABLESIZE }, 'o' }, 16464 { { STATE_AE_FIRST_TS }, 'o' }, 16465 { { STATE_CPENABLE }, 'i' } 16466 }; 16467 16468 static xtensa_arg_internal Iclass_rur_ae_sd_no_args[] = { 16469 { { OPERAND_arr }, 'o' } 16470 }; 16471 16472 static xtensa_arg_internal Iclass_rur_ae_sd_no_stateArgs[] = { 16473 { { STATE_AE_NEXTOFFSET }, 'i' }, 16474 { { STATE_AE_SEARCHDONE }, 'i' }, 16475 { { STATE_CPENABLE }, 'i' } 16476 }; 16477 16478 static xtensa_arg_internal Iclass_wur_ae_sd_no_args[] = { 16479 { { OPERAND_art }, 'i' } 16480 }; 16481 16482 static xtensa_arg_internal Iclass_wur_ae_sd_no_stateArgs[] = { 16483 { { STATE_AE_NEXTOFFSET }, 'o' }, 16484 { { STATE_AE_SEARCHDONE }, 'o' }, 16485 { { STATE_CPENABLE }, 'i' } 16486 }; 16487 16488 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_args[] = { 16489 { { OPERAND_arr }, 'o' } 16490 }; 16491 16492 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_overflow_stateArgs[] = { 16493 { { STATE_AE_OVERFLOW }, 'i' }, 16494 { { STATE_CPENABLE }, 'i' } 16495 }; 16496 16497 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_args[] = { 16498 { { OPERAND_art }, 'i' } 16499 }; 16500 16501 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_overflow_stateArgs[] = { 16502 { { STATE_AE_OVERFLOW }, 'o' }, 16503 { { STATE_CPENABLE }, 'i' } 16504 }; 16505 16506 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_args[] = { 16507 { { OPERAND_arr }, 'o' } 16508 }; 16509 16510 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_sar_stateArgs[] = { 16511 { { STATE_AE_SAR }, 'i' }, 16512 { { STATE_CPENABLE }, 'i' } 16513 }; 16514 16515 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_args[] = { 16516 { { OPERAND_art }, 'i' } 16517 }; 16518 16519 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_sar_stateArgs[] = { 16520 { { STATE_AE_SAR }, 'o' }, 16521 { { STATE_CPENABLE }, 'i' } 16522 }; 16523 16524 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_args[] = { 16525 { { OPERAND_arr }, 'o' } 16526 }; 16527 16528 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitptr_stateArgs[] = { 16529 { { STATE_AE_BITPTR }, 'i' }, 16530 { { STATE_CPENABLE }, 'i' } 16531 }; 16532 16533 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_args[] = { 16534 { { OPERAND_art }, 'i' } 16535 }; 16536 16537 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitptr_stateArgs[] = { 16538 { { STATE_AE_BITPTR }, 'o' }, 16539 { { STATE_CPENABLE }, 'i' } 16540 }; 16541 16542 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_args[] = { 16543 { { OPERAND_arr }, 'o' } 16544 }; 16545 16546 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_bitsused_stateArgs[] = { 16547 { { STATE_AE_BITSUSED }, 'i' }, 16548 { { STATE_CPENABLE }, 'i' } 16549 }; 16550 16551 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_args[] = { 16552 { { OPERAND_art }, 'i' } 16553 }; 16554 16555 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_bitsused_stateArgs[] = { 16556 { { STATE_AE_BITSUSED }, 'o' }, 16557 { { STATE_CPENABLE }, 'i' } 16558 }; 16559 16560 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_args[] = { 16561 { { OPERAND_arr }, 'o' } 16562 }; 16563 16564 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_tablesize_stateArgs[] = { 16565 { { STATE_AE_TABLESIZE }, 'i' }, 16566 { { STATE_CPENABLE }, 'i' } 16567 }; 16568 16569 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_args[] = { 16570 { { OPERAND_art }, 'i' } 16571 }; 16572 16573 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_tablesize_stateArgs[] = { 16574 { { STATE_AE_TABLESIZE }, 'o' }, 16575 { { STATE_CPENABLE }, 'i' } 16576 }; 16577 16578 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_args[] = { 16579 { { OPERAND_arr }, 'o' } 16580 }; 16581 16582 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_first_ts_stateArgs[] = { 16583 { { STATE_AE_FIRST_TS }, 'i' }, 16584 { { STATE_CPENABLE }, 'i' } 16585 }; 16586 16587 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_args[] = { 16588 { { OPERAND_art }, 'i' } 16589 }; 16590 16591 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_first_ts_stateArgs[] = { 16592 { { STATE_AE_FIRST_TS }, 'o' }, 16593 { { STATE_CPENABLE }, 'i' } 16594 }; 16595 16596 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_args[] = { 16597 { { OPERAND_arr }, 'o' } 16598 }; 16599 16600 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_nextoffset_stateArgs[] = { 16601 { { STATE_AE_NEXTOFFSET }, 'i' }, 16602 { { STATE_CPENABLE }, 'i' } 16603 }; 16604 16605 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_args[] = { 16606 { { OPERAND_art }, 'i' } 16607 }; 16608 16609 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_nextoffset_stateArgs[] = { 16610 { { STATE_AE_NEXTOFFSET }, 'o' }, 16611 { { STATE_CPENABLE }, 'i' } 16612 }; 16613 16614 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_args[] = { 16615 { { OPERAND_arr }, 'o' } 16616 }; 16617 16618 static xtensa_arg_internal Iclass_ae_iclass_rur_ae_searchdone_stateArgs[] = { 16619 { { STATE_AE_SEARCHDONE }, 'i' }, 16620 { { STATE_CPENABLE }, 'i' } 16621 }; 16622 16623 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_args[] = { 16624 { { OPERAND_art }, 'i' } 16625 }; 16626 16627 static xtensa_arg_internal Iclass_ae_iclass_wur_ae_searchdone_stateArgs[] = { 16628 { { STATE_AE_SEARCHDONE }, 'o' }, 16629 { { STATE_CPENABLE }, 'i' } 16630 }; 16631 16632 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_args[] = { 16633 { { OPERAND_pr }, 'o' }, 16634 { { OPERAND_ars }, 'i' }, 16635 { { OPERAND_ae_lsimm16 }, 'i' } 16636 }; 16637 16638 static xtensa_arg_internal Iclass_ae_iclass_lp16f_i_stateArgs[] = { 16639 { { STATE_CPENABLE }, 'i' } 16640 }; 16641 16642 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_args[] = { 16643 { { OPERAND_pr }, 'o' }, 16644 { { OPERAND_ars }, 'm' }, 16645 { { OPERAND_ae_lsimm16 }, 'i' } 16646 }; 16647 16648 static xtensa_arg_internal Iclass_ae_iclass_lp16f_iu_stateArgs[] = { 16649 { { STATE_CPENABLE }, 'i' } 16650 }; 16651 16652 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_args[] = { 16653 { { OPERAND_pr }, 'o' }, 16654 { { OPERAND_ars }, 'i' }, 16655 { { OPERAND_art }, 'i' } 16656 }; 16657 16658 static xtensa_arg_internal Iclass_ae_iclass_lp16f_x_stateArgs[] = { 16659 { { STATE_CPENABLE }, 'i' } 16660 }; 16661 16662 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_args[] = { 16663 { { OPERAND_pr }, 'o' }, 16664 { { OPERAND_ars }, 'm' }, 16665 { { OPERAND_art }, 'i' } 16666 }; 16667 16668 static xtensa_arg_internal Iclass_ae_iclass_lp16f_xu_stateArgs[] = { 16669 { { STATE_CPENABLE }, 'i' } 16670 }; 16671 16672 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_args[] = { 16673 { { OPERAND_pr }, 'o' }, 16674 { { OPERAND_ars }, 'i' }, 16675 { { OPERAND_ae_lsimm32 }, 'i' } 16676 }; 16677 16678 static xtensa_arg_internal Iclass_ae_iclass_lp24_i_stateArgs[] = { 16679 { { STATE_CPENABLE }, 'i' } 16680 }; 16681 16682 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_args[] = { 16683 { { OPERAND_pr }, 'o' }, 16684 { { OPERAND_ars }, 'm' }, 16685 { { OPERAND_ae_lsimm32 }, 'i' } 16686 }; 16687 16688 static xtensa_arg_internal Iclass_ae_iclass_lp24_iu_stateArgs[] = { 16689 { { STATE_CPENABLE }, 'i' } 16690 }; 16691 16692 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_args[] = { 16693 { { OPERAND_pr }, 'o' }, 16694 { { OPERAND_ars }, 'i' }, 16695 { { OPERAND_art }, 'i' } 16696 }; 16697 16698 static xtensa_arg_internal Iclass_ae_iclass_lp24_x_stateArgs[] = { 16699 { { STATE_CPENABLE }, 'i' } 16700 }; 16701 16702 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_args[] = { 16703 { { OPERAND_pr }, 'o' }, 16704 { { OPERAND_ars }, 'm' }, 16705 { { OPERAND_art }, 'i' } 16706 }; 16707 16708 static xtensa_arg_internal Iclass_ae_iclass_lp24_xu_stateArgs[] = { 16709 { { STATE_CPENABLE }, 'i' } 16710 }; 16711 16712 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_args[] = { 16713 { { OPERAND_pr }, 'o' }, 16714 { { OPERAND_ars }, 'i' }, 16715 { { OPERAND_ae_lsimm32 }, 'i' } 16716 }; 16717 16718 static xtensa_arg_internal Iclass_ae_iclass_lp24f_i_stateArgs[] = { 16719 { { STATE_CPENABLE }, 'i' } 16720 }; 16721 16722 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_args[] = { 16723 { { OPERAND_pr }, 'o' }, 16724 { { OPERAND_ars }, 'm' }, 16725 { { OPERAND_ae_lsimm32 }, 'i' } 16726 }; 16727 16728 static xtensa_arg_internal Iclass_ae_iclass_lp24f_iu_stateArgs[] = { 16729 { { STATE_CPENABLE }, 'i' } 16730 }; 16731 16732 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_args[] = { 16733 { { OPERAND_pr }, 'o' }, 16734 { { OPERAND_ars }, 'i' }, 16735 { { OPERAND_art }, 'i' } 16736 }; 16737 16738 static xtensa_arg_internal Iclass_ae_iclass_lp24f_x_stateArgs[] = { 16739 { { STATE_CPENABLE }, 'i' } 16740 }; 16741 16742 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_args[] = { 16743 { { OPERAND_pr }, 'o' }, 16744 { { OPERAND_ars }, 'm' }, 16745 { { OPERAND_art }, 'i' } 16746 }; 16747 16748 static xtensa_arg_internal Iclass_ae_iclass_lp24f_xu_stateArgs[] = { 16749 { { STATE_CPENABLE }, 'i' } 16750 }; 16751 16752 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_args[] = { 16753 { { OPERAND_pr }, 'o' }, 16754 { { OPERAND_ars }, 'i' }, 16755 { { OPERAND_ae_lsimm32 }, 'i' } 16756 }; 16757 16758 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_i_stateArgs[] = { 16759 { { STATE_CPENABLE }, 'i' } 16760 }; 16761 16762 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_args[] = { 16763 { { OPERAND_pr }, 'o' }, 16764 { { OPERAND_ars }, 'm' }, 16765 { { OPERAND_ae_lsimm32 }, 'i' } 16766 }; 16767 16768 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_iu_stateArgs[] = { 16769 { { STATE_CPENABLE }, 'i' } 16770 }; 16771 16772 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_args[] = { 16773 { { OPERAND_pr }, 'o' }, 16774 { { OPERAND_ars }, 'i' }, 16775 { { OPERAND_art }, 'i' } 16776 }; 16777 16778 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_x_stateArgs[] = { 16779 { { STATE_CPENABLE }, 'i' } 16780 }; 16781 16782 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_args[] = { 16783 { { OPERAND_pr }, 'o' }, 16784 { { OPERAND_ars }, 'm' }, 16785 { { OPERAND_art }, 'i' } 16786 }; 16787 16788 static xtensa_arg_internal Iclass_ae_iclass_lp16x2f_xu_stateArgs[] = { 16789 { { STATE_CPENABLE }, 'i' } 16790 }; 16791 16792 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_args[] = { 16793 { { OPERAND_pr }, 'o' }, 16794 { { OPERAND_ars }, 'i' }, 16795 { { OPERAND_ae_lsimm64 }, 'i' } 16796 }; 16797 16798 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_i_stateArgs[] = { 16799 { { STATE_CPENABLE }, 'i' } 16800 }; 16801 16802 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_args[] = { 16803 { { OPERAND_pr }, 'o' }, 16804 { { OPERAND_ars }, 'm' }, 16805 { { OPERAND_ae_lsimm64 }, 'i' } 16806 }; 16807 16808 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_iu_stateArgs[] = { 16809 { { STATE_CPENABLE }, 'i' } 16810 }; 16811 16812 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_args[] = { 16813 { { OPERAND_pr }, 'o' }, 16814 { { OPERAND_ars }, 'i' }, 16815 { { OPERAND_art }, 'i' } 16816 }; 16817 16818 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_x_stateArgs[] = { 16819 { { STATE_CPENABLE }, 'i' } 16820 }; 16821 16822 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_args[] = { 16823 { { OPERAND_pr }, 'o' }, 16824 { { OPERAND_ars }, 'm' }, 16825 { { OPERAND_art }, 'i' } 16826 }; 16827 16828 static xtensa_arg_internal Iclass_ae_iclass_lp24x2f_xu_stateArgs[] = { 16829 { { STATE_CPENABLE }, 'i' } 16830 }; 16831 16832 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_args[] = { 16833 { { OPERAND_pr }, 'o' }, 16834 { { OPERAND_ars }, 'i' }, 16835 { { OPERAND_ae_lsimm64 }, 'i' } 16836 }; 16837 16838 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_i_stateArgs[] = { 16839 { { STATE_CPENABLE }, 'i' } 16840 }; 16841 16842 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_args[] = { 16843 { { OPERAND_pr }, 'o' }, 16844 { { OPERAND_ars }, 'm' }, 16845 { { OPERAND_ae_lsimm64 }, 'i' } 16846 }; 16847 16848 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_iu_stateArgs[] = { 16849 { { STATE_CPENABLE }, 'i' } 16850 }; 16851 16852 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_args[] = { 16853 { { OPERAND_pr }, 'o' }, 16854 { { OPERAND_ars }, 'i' }, 16855 { { OPERAND_art }, 'i' } 16856 }; 16857 16858 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_x_stateArgs[] = { 16859 { { STATE_CPENABLE }, 'i' } 16860 }; 16861 16862 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_args[] = { 16863 { { OPERAND_pr }, 'o' }, 16864 { { OPERAND_ars }, 'm' }, 16865 { { OPERAND_art }, 'i' } 16866 }; 16867 16868 static xtensa_arg_internal Iclass_ae_iclass_lp24x2_xu_stateArgs[] = { 16869 { { STATE_CPENABLE }, 'i' } 16870 }; 16871 16872 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_args[] = { 16873 { { OPERAND_pr }, 'i' }, 16874 { { OPERAND_ars }, 'i' }, 16875 { { OPERAND_ae_lsimm32 }, 'i' } 16876 }; 16877 16878 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_i_stateArgs[] = { 16879 { { STATE_CPENABLE }, 'i' } 16880 }; 16881 16882 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_args[] = { 16883 { { OPERAND_pr }, 'i' }, 16884 { { OPERAND_ars }, 'm' }, 16885 { { OPERAND_ae_lsimm32 }, 'i' } 16886 }; 16887 16888 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_iu_stateArgs[] = { 16889 { { STATE_CPENABLE }, 'i' } 16890 }; 16891 16892 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_args[] = { 16893 { { OPERAND_pr }, 'i' }, 16894 { { OPERAND_ars }, 'i' }, 16895 { { OPERAND_art }, 'i' } 16896 }; 16897 16898 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_x_stateArgs[] = { 16899 { { STATE_CPENABLE }, 'i' } 16900 }; 16901 16902 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_args[] = { 16903 { { OPERAND_pr }, 'i' }, 16904 { { OPERAND_ars }, 'm' }, 16905 { { OPERAND_art }, 'i' } 16906 }; 16907 16908 static xtensa_arg_internal Iclass_ae_iclass_sp16x2f_xu_stateArgs[] = { 16909 { { STATE_CPENABLE }, 'i' } 16910 }; 16911 16912 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_args[] = { 16913 { { OPERAND_pr }, 'i' }, 16914 { { OPERAND_ars }, 'i' }, 16915 { { OPERAND_ae_lsimm64 }, 'i' } 16916 }; 16917 16918 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_i_stateArgs[] = { 16919 { { STATE_CPENABLE }, 'i' } 16920 }; 16921 16922 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_args[] = { 16923 { { OPERAND_pr }, 'i' }, 16924 { { OPERAND_ars }, 'm' }, 16925 { { OPERAND_ae_lsimm64 }, 'i' } 16926 }; 16927 16928 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_iu_stateArgs[] = { 16929 { { STATE_CPENABLE }, 'i' } 16930 }; 16931 16932 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_args[] = { 16933 { { OPERAND_pr }, 'i' }, 16934 { { OPERAND_ars }, 'i' }, 16935 { { OPERAND_art }, 'i' } 16936 }; 16937 16938 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_x_stateArgs[] = { 16939 { { STATE_CPENABLE }, 'i' } 16940 }; 16941 16942 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_args[] = { 16943 { { OPERAND_pr }, 'i' }, 16944 { { OPERAND_ars }, 'm' }, 16945 { { OPERAND_art }, 'i' } 16946 }; 16947 16948 static xtensa_arg_internal Iclass_ae_iclass_sp24x2s_xu_stateArgs[] = { 16949 { { STATE_CPENABLE }, 'i' } 16950 }; 16951 16952 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_args[] = { 16953 { { OPERAND_pr }, 'i' }, 16954 { { OPERAND_ars }, 'i' }, 16955 { { OPERAND_ae_lsimm64 }, 'i' } 16956 }; 16957 16958 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_i_stateArgs[] = { 16959 { { STATE_CPENABLE }, 'i' } 16960 }; 16961 16962 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_args[] = { 16963 { { OPERAND_pr }, 'i' }, 16964 { { OPERAND_ars }, 'm' }, 16965 { { OPERAND_ae_lsimm64 }, 'i' } 16966 }; 16967 16968 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_iu_stateArgs[] = { 16969 { { STATE_CPENABLE }, 'i' } 16970 }; 16971 16972 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_args[] = { 16973 { { OPERAND_pr }, 'i' }, 16974 { { OPERAND_ars }, 'i' }, 16975 { { OPERAND_art }, 'i' } 16976 }; 16977 16978 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_x_stateArgs[] = { 16979 { { STATE_CPENABLE }, 'i' } 16980 }; 16981 16982 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_args[] = { 16983 { { OPERAND_pr }, 'i' }, 16984 { { OPERAND_ars }, 'm' }, 16985 { { OPERAND_art }, 'i' } 16986 }; 16987 16988 static xtensa_arg_internal Iclass_ae_iclass_sp24x2f_xu_stateArgs[] = { 16989 { { STATE_CPENABLE }, 'i' } 16990 }; 16991 16992 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_args[] = { 16993 { { OPERAND_pr }, 'i' }, 16994 { { OPERAND_ars }, 'i' }, 16995 { { OPERAND_ae_lsimm16 }, 'i' } 16996 }; 16997 16998 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_i_stateArgs[] = { 16999 { { STATE_CPENABLE }, 'i' } 17000 }; 17001 17002 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_args[] = { 17003 { { OPERAND_pr }, 'i' }, 17004 { { OPERAND_ars }, 'm' }, 17005 { { OPERAND_ae_lsimm16 }, 'i' } 17006 }; 17007 17008 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_iu_stateArgs[] = { 17009 { { STATE_CPENABLE }, 'i' } 17010 }; 17011 17012 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_args[] = { 17013 { { OPERAND_pr }, 'i' }, 17014 { { OPERAND_ars }, 'i' }, 17015 { { OPERAND_art }, 'i' } 17016 }; 17017 17018 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_x_stateArgs[] = { 17019 { { STATE_CPENABLE }, 'i' } 17020 }; 17021 17022 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_args[] = { 17023 { { OPERAND_pr }, 'i' }, 17024 { { OPERAND_ars }, 'm' }, 17025 { { OPERAND_art }, 'i' } 17026 }; 17027 17028 static xtensa_arg_internal Iclass_ae_iclass_sp16f_l_xu_stateArgs[] = { 17029 { { STATE_CPENABLE }, 'i' } 17030 }; 17031 17032 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_args[] = { 17033 { { OPERAND_pr }, 'i' }, 17034 { { OPERAND_ars }, 'i' }, 17035 { { OPERAND_ae_lsimm32 }, 'i' } 17036 }; 17037 17038 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_i_stateArgs[] = { 17039 { { STATE_CPENABLE }, 'i' } 17040 }; 17041 17042 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_args[] = { 17043 { { OPERAND_pr }, 'i' }, 17044 { { OPERAND_ars }, 'm' }, 17045 { { OPERAND_ae_lsimm32 }, 'i' } 17046 }; 17047 17048 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_iu_stateArgs[] = { 17049 { { STATE_CPENABLE }, 'i' } 17050 }; 17051 17052 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_args[] = { 17053 { { OPERAND_pr }, 'i' }, 17054 { { OPERAND_ars }, 'i' }, 17055 { { OPERAND_art }, 'i' } 17056 }; 17057 17058 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_x_stateArgs[] = { 17059 { { STATE_CPENABLE }, 'i' } 17060 }; 17061 17062 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_args[] = { 17063 { { OPERAND_pr }, 'i' }, 17064 { { OPERAND_ars }, 'm' }, 17065 { { OPERAND_art }, 'i' } 17066 }; 17067 17068 static xtensa_arg_internal Iclass_ae_iclass_sp24s_l_xu_stateArgs[] = { 17069 { { STATE_CPENABLE }, 'i' } 17070 }; 17071 17072 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_args[] = { 17073 { { OPERAND_pr }, 'i' }, 17074 { { OPERAND_ars }, 'i' }, 17075 { { OPERAND_ae_lsimm32 }, 'i' } 17076 }; 17077 17078 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_i_stateArgs[] = { 17079 { { STATE_CPENABLE }, 'i' } 17080 }; 17081 17082 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_args[] = { 17083 { { OPERAND_pr }, 'i' }, 17084 { { OPERAND_ars }, 'm' }, 17085 { { OPERAND_ae_lsimm32 }, 'i' } 17086 }; 17087 17088 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_iu_stateArgs[] = { 17089 { { STATE_CPENABLE }, 'i' } 17090 }; 17091 17092 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_args[] = { 17093 { { OPERAND_pr }, 'i' }, 17094 { { OPERAND_ars }, 'i' }, 17095 { { OPERAND_art }, 'i' } 17096 }; 17097 17098 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_x_stateArgs[] = { 17099 { { STATE_CPENABLE }, 'i' } 17100 }; 17101 17102 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_args[] = { 17103 { { OPERAND_pr }, 'i' }, 17104 { { OPERAND_ars }, 'm' }, 17105 { { OPERAND_art }, 'i' } 17106 }; 17107 17108 static xtensa_arg_internal Iclass_ae_iclass_sp24f_l_xu_stateArgs[] = { 17109 { { STATE_CPENABLE }, 'i' } 17110 }; 17111 17112 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_args[] = { 17113 { { OPERAND_qr1_w }, 'o' }, 17114 { { OPERAND_ars }, 'i' }, 17115 { { OPERAND_ae_lsimm64 }, 'i' } 17116 }; 17117 17118 static xtensa_arg_internal Iclass_ae_iclass_lq56_i_stateArgs[] = { 17119 { { STATE_CPENABLE }, 'i' } 17120 }; 17121 17122 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_args[] = { 17123 { { OPERAND_qr1_w }, 'o' }, 17124 { { OPERAND_ars }, 'm' }, 17125 { { OPERAND_ae_lsimm64 }, 'i' } 17126 }; 17127 17128 static xtensa_arg_internal Iclass_ae_iclass_lq56_iu_stateArgs[] = { 17129 { { STATE_CPENABLE }, 'i' } 17130 }; 17131 17132 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_args[] = { 17133 { { OPERAND_qr1_w }, 'o' }, 17134 { { OPERAND_ars }, 'i' }, 17135 { { OPERAND_art }, 'i' } 17136 }; 17137 17138 static xtensa_arg_internal Iclass_ae_iclass_lq56_x_stateArgs[] = { 17139 { { STATE_CPENABLE }, 'i' } 17140 }; 17141 17142 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_args[] = { 17143 { { OPERAND_qr1_w }, 'o' }, 17144 { { OPERAND_ars }, 'm' }, 17145 { { OPERAND_art }, 'i' } 17146 }; 17147 17148 static xtensa_arg_internal Iclass_ae_iclass_lq56_xu_stateArgs[] = { 17149 { { STATE_CPENABLE }, 'i' } 17150 }; 17151 17152 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_args[] = { 17153 { { OPERAND_qr1_w }, 'o' }, 17154 { { OPERAND_ars }, 'i' }, 17155 { { OPERAND_ae_lsimm32 }, 'i' } 17156 }; 17157 17158 static xtensa_arg_internal Iclass_ae_iclass_lq32f_i_stateArgs[] = { 17159 { { STATE_CPENABLE }, 'i' } 17160 }; 17161 17162 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_args[] = { 17163 { { OPERAND_qr1_w }, 'o' }, 17164 { { OPERAND_ars }, 'm' }, 17165 { { OPERAND_ae_lsimm32 }, 'i' } 17166 }; 17167 17168 static xtensa_arg_internal Iclass_ae_iclass_lq32f_iu_stateArgs[] = { 17169 { { STATE_CPENABLE }, 'i' } 17170 }; 17171 17172 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_args[] = { 17173 { { OPERAND_qr1_w }, 'o' }, 17174 { { OPERAND_ars }, 'i' }, 17175 { { OPERAND_art }, 'i' } 17176 }; 17177 17178 static xtensa_arg_internal Iclass_ae_iclass_lq32f_x_stateArgs[] = { 17179 { { STATE_CPENABLE }, 'i' } 17180 }; 17181 17182 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_args[] = { 17183 { { OPERAND_qr1_w }, 'o' }, 17184 { { OPERAND_ars }, 'm' }, 17185 { { OPERAND_art }, 'i' } 17186 }; 17187 17188 static xtensa_arg_internal Iclass_ae_iclass_lq32f_xu_stateArgs[] = { 17189 { { STATE_CPENABLE }, 'i' } 17190 }; 17191 17192 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_args[] = { 17193 { { OPERAND_qr0_rw }, 'i' }, 17194 { { OPERAND_ars }, 'i' }, 17195 { { OPERAND_ae_lsimm64 }, 'i' } 17196 }; 17197 17198 static xtensa_arg_internal Iclass_ae_iclass_sq56s_i_stateArgs[] = { 17199 { { STATE_CPENABLE }, 'i' } 17200 }; 17201 17202 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_args[] = { 17203 { { OPERAND_qr0_rw }, 'i' }, 17204 { { OPERAND_ars }, 'm' }, 17205 { { OPERAND_ae_lsimm64 }, 'i' } 17206 }; 17207 17208 static xtensa_arg_internal Iclass_ae_iclass_sq56s_iu_stateArgs[] = { 17209 { { STATE_CPENABLE }, 'i' } 17210 }; 17211 17212 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_args[] = { 17213 { { OPERAND_qr0_rw }, 'i' }, 17214 { { OPERAND_ars }, 'i' }, 17215 { { OPERAND_art }, 'i' } 17216 }; 17217 17218 static xtensa_arg_internal Iclass_ae_iclass_sq56s_x_stateArgs[] = { 17219 { { STATE_CPENABLE }, 'i' } 17220 }; 17221 17222 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_args[] = { 17223 { { OPERAND_qr0_rw }, 'i' }, 17224 { { OPERAND_ars }, 'm' }, 17225 { { OPERAND_art }, 'i' } 17226 }; 17227 17228 static xtensa_arg_internal Iclass_ae_iclass_sq56s_xu_stateArgs[] = { 17229 { { STATE_CPENABLE }, 'i' } 17230 }; 17231 17232 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_args[] = { 17233 { { OPERAND_qr0_rw }, 'i' }, 17234 { { OPERAND_ars }, 'i' }, 17235 { { OPERAND_ae_lsimm32 }, 'i' } 17236 }; 17237 17238 static xtensa_arg_internal Iclass_ae_iclass_sq32f_i_stateArgs[] = { 17239 { { STATE_CPENABLE }, 'i' } 17240 }; 17241 17242 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_args[] = { 17243 { { OPERAND_qr0_rw }, 'i' }, 17244 { { OPERAND_ars }, 'm' }, 17245 { { OPERAND_ae_lsimm32 }, 'i' } 17246 }; 17247 17248 static xtensa_arg_internal Iclass_ae_iclass_sq32f_iu_stateArgs[] = { 17249 { { STATE_CPENABLE }, 'i' } 17250 }; 17251 17252 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_args[] = { 17253 { { OPERAND_qr0_rw }, 'i' }, 17254 { { OPERAND_ars }, 'i' }, 17255 { { OPERAND_art }, 'i' } 17256 }; 17257 17258 static xtensa_arg_internal Iclass_ae_iclass_sq32f_x_stateArgs[] = { 17259 { { STATE_CPENABLE }, 'i' } 17260 }; 17261 17262 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_args[] = { 17263 { { OPERAND_qr0_rw }, 'i' }, 17264 { { OPERAND_ars }, 'm' }, 17265 { { OPERAND_art }, 'i' } 17266 }; 17267 17268 static xtensa_arg_internal Iclass_ae_iclass_sq32f_xu_stateArgs[] = { 17269 { { STATE_CPENABLE }, 'i' } 17270 }; 17271 17272 static xtensa_arg_internal Iclass_ae_iclass_zerop48_args[] = { 17273 { { OPERAND_ps }, 'o' } 17274 }; 17275 17276 static xtensa_arg_internal Iclass_ae_iclass_zerop48_stateArgs[] = { 17277 { { STATE_CPENABLE }, 'i' } 17278 }; 17279 17280 static xtensa_arg_internal Iclass_ae_iclass_movp48_args[] = { 17281 { { OPERAND_ps }, 'o' }, 17282 { { OPERAND_pr }, 'i' } 17283 }; 17284 17285 static xtensa_arg_internal Iclass_ae_iclass_movp48_stateArgs[] = { 17286 { { STATE_CPENABLE }, 'i' } 17287 }; 17288 17289 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_args[] = { 17290 { { OPERAND_ps }, 'o' }, 17291 { { OPERAND_pr }, 'i' }, 17292 { { OPERAND_pr0 }, 'i' } 17293 }; 17294 17295 static xtensa_arg_internal Iclass_ae_iclass_selp24_ll_stateArgs[] = { 17296 { { STATE_CPENABLE }, 'i' } 17297 }; 17298 17299 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_args[] = { 17300 { { OPERAND_ps }, 'o' }, 17301 { { OPERAND_pr }, 'i' }, 17302 { { OPERAND_pr0 }, 'i' } 17303 }; 17304 17305 static xtensa_arg_internal Iclass_ae_iclass_selp24_lh_stateArgs[] = { 17306 { { STATE_CPENABLE }, 'i' } 17307 }; 17308 17309 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_args[] = { 17310 { { OPERAND_ps }, 'o' }, 17311 { { OPERAND_pr }, 'i' }, 17312 { { OPERAND_pr0 }, 'i' } 17313 }; 17314 17315 static xtensa_arg_internal Iclass_ae_iclass_selp24_hl_stateArgs[] = { 17316 { { STATE_CPENABLE }, 'i' } 17317 }; 17318 17319 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_args[] = { 17320 { { OPERAND_ps }, 'o' }, 17321 { { OPERAND_pr }, 'i' }, 17322 { { OPERAND_pr0 }, 'i' } 17323 }; 17324 17325 static xtensa_arg_internal Iclass_ae_iclass_selp24_hh_stateArgs[] = { 17326 { { STATE_CPENABLE }, 'i' } 17327 }; 17328 17329 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_args[] = { 17330 { { OPERAND_pr }, 'm' }, 17331 { { OPERAND_pr0 }, 'i' }, 17332 { { OPERAND_bt2 }, 'i' } 17333 }; 17334 17335 static xtensa_arg_internal Iclass_ae_iclass_movtp24x2_stateArgs[] = { 17336 { { STATE_CPENABLE }, 'i' } 17337 }; 17338 17339 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_args[] = { 17340 { { OPERAND_pr }, 'm' }, 17341 { { OPERAND_pr0 }, 'i' }, 17342 { { OPERAND_bt2 }, 'i' } 17343 }; 17344 17345 static xtensa_arg_internal Iclass_ae_iclass_movfp24x2_stateArgs[] = { 17346 { { STATE_CPENABLE }, 'i' } 17347 }; 17348 17349 static xtensa_arg_internal Iclass_ae_iclass_movtp48_args[] = { 17350 { { OPERAND_pr }, 'm' }, 17351 { { OPERAND_pr0 }, 'i' }, 17352 { { OPERAND_bt }, 'i' } 17353 }; 17354 17355 static xtensa_arg_internal Iclass_ae_iclass_movtp48_stateArgs[] = { 17356 { { STATE_CPENABLE }, 'i' } 17357 }; 17358 17359 static xtensa_arg_internal Iclass_ae_iclass_movfp48_args[] = { 17360 { { OPERAND_pr }, 'm' }, 17361 { { OPERAND_pr0 }, 'i' }, 17362 { { OPERAND_bt }, 'i' } 17363 }; 17364 17365 static xtensa_arg_internal Iclass_ae_iclass_movfp48_stateArgs[] = { 17366 { { STATE_CPENABLE }, 'i' } 17367 }; 17368 17369 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_args[] = { 17370 { { OPERAND_pr }, 'o' }, 17371 { { OPERAND_ars }, 'i' }, 17372 { { OPERAND_art }, 'i' } 17373 }; 17374 17375 static xtensa_arg_internal Iclass_ae_iclass_movpa24x2_stateArgs[] = { 17376 { { STATE_CPENABLE }, 'i' } 17377 }; 17378 17379 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_args[] = { 17380 { { OPERAND_pr }, 'o' }, 17381 { { OPERAND_ars }, 'i' }, 17382 { { OPERAND_art }, 'i' } 17383 }; 17384 17385 static xtensa_arg_internal Iclass_ae_iclass_truncp24a32x2_stateArgs[] = { 17386 { { STATE_CPENABLE }, 'i' } 17387 }; 17388 17389 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_args[] = { 17390 { { OPERAND_ars }, 'o' }, 17391 { { OPERAND_pr }, 'i' } 17392 }; 17393 17394 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_l_stateArgs[] = { 17395 { { STATE_CPENABLE }, 'i' } 17396 }; 17397 17398 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_args[] = { 17399 { { OPERAND_ars }, 'o' }, 17400 { { OPERAND_pr }, 'i' } 17401 }; 17402 17403 static xtensa_arg_internal Iclass_ae_iclass_cvta32p24_h_stateArgs[] = { 17404 { { STATE_CPENABLE }, 'i' } 17405 }; 17406 17407 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_args[] = { 17408 { { OPERAND_pr }, 'o' }, 17409 { { OPERAND_ars }, 'i' }, 17410 { { OPERAND_art }, 'i' } 17411 }; 17412 17413 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_ll_stateArgs[] = { 17414 { { STATE_CPENABLE }, 'i' } 17415 }; 17416 17417 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_args[] = { 17418 { { OPERAND_pr }, 'o' }, 17419 { { OPERAND_ars }, 'i' }, 17420 { { OPERAND_art }, 'i' } 17421 }; 17422 17423 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_lh_stateArgs[] = { 17424 { { STATE_CPENABLE }, 'i' } 17425 }; 17426 17427 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_args[] = { 17428 { { OPERAND_pr }, 'o' }, 17429 { { OPERAND_ars }, 'i' }, 17430 { { OPERAND_art }, 'i' } 17431 }; 17432 17433 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hl_stateArgs[] = { 17434 { { STATE_CPENABLE }, 'i' } 17435 }; 17436 17437 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_args[] = { 17438 { { OPERAND_pr }, 'o' }, 17439 { { OPERAND_ars }, 'i' }, 17440 { { OPERAND_art }, 'i' } 17441 }; 17442 17443 static xtensa_arg_internal Iclass_ae_iclass_cvtp24a16x2_hh_stateArgs[] = { 17444 { { STATE_CPENABLE }, 'i' } 17445 }; 17446 17447 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_args[] = { 17448 { { OPERAND_ps }, 'o' }, 17449 { { OPERAND_qr0_rw }, 'i' }, 17450 { { OPERAND_qr0 }, 'i' } 17451 }; 17452 17453 static xtensa_arg_internal Iclass_ae_iclass_truncp24q48x2_stateArgs[] = { 17454 { { STATE_CPENABLE }, 'i' } 17455 }; 17456 17457 static xtensa_arg_internal Iclass_ae_iclass_truncp16_args[] = { 17458 { { OPERAND_ps }, 'o' }, 17459 { { OPERAND_pr }, 'i' } 17460 }; 17461 17462 static xtensa_arg_internal Iclass_ae_iclass_truncp16_stateArgs[] = { 17463 { { STATE_CPENABLE }, 'i' } 17464 }; 17465 17466 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_args[] = { 17467 { { OPERAND_ps }, 'o' }, 17468 { { OPERAND_qr0_rw }, 'i' } 17469 }; 17470 17471 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48sym_stateArgs[] = { 17472 { { STATE_AE_OVERFLOW }, 'm' }, 17473 { { STATE_CPENABLE }, 'i' } 17474 }; 17475 17476 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_args[] = { 17477 { { OPERAND_ps }, 'o' }, 17478 { { OPERAND_qr0_rw }, 'i' } 17479 }; 17480 17481 static xtensa_arg_internal Iclass_ae_iclass_roundsp24q48asym_stateArgs[] = { 17482 { { STATE_AE_OVERFLOW }, 'm' }, 17483 { { STATE_CPENABLE }, 'i' } 17484 }; 17485 17486 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_args[] = { 17487 { { OPERAND_ps }, 'o' }, 17488 { { OPERAND_qr0_rw }, 'i' } 17489 }; 17490 17491 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48sym_stateArgs[] = { 17492 { { STATE_AE_OVERFLOW }, 'm' }, 17493 { { STATE_CPENABLE }, 'i' } 17494 }; 17495 17496 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_args[] = { 17497 { { OPERAND_ps }, 'o' }, 17498 { { OPERAND_qr0_rw }, 'i' } 17499 }; 17500 17501 static xtensa_arg_internal Iclass_ae_iclass_roundsp16q48asym_stateArgs[] = { 17502 { { STATE_AE_OVERFLOW }, 'm' }, 17503 { { STATE_CPENABLE }, 'i' } 17504 }; 17505 17506 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_args[] = { 17507 { { OPERAND_ps }, 'o' }, 17508 { { OPERAND_pr }, 'i' } 17509 }; 17510 17511 static xtensa_arg_internal Iclass_ae_iclass_roundsp16sym_stateArgs[] = { 17512 { { STATE_AE_OVERFLOW }, 'm' }, 17513 { { STATE_CPENABLE }, 'i' } 17514 }; 17515 17516 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_args[] = { 17517 { { OPERAND_ps }, 'o' }, 17518 { { OPERAND_pr }, 'i' } 17519 }; 17520 17521 static xtensa_arg_internal Iclass_ae_iclass_roundsp16asym_stateArgs[] = { 17522 { { STATE_AE_OVERFLOW }, 'm' }, 17523 { { STATE_CPENABLE }, 'i' } 17524 }; 17525 17526 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_args[] = { 17527 { { OPERAND_qr1_w }, 'o' } 17528 }; 17529 17530 static xtensa_arg_internal Iclass_ae_iclass_zeroq56_stateArgs[] = { 17531 { { STATE_CPENABLE }, 'i' } 17532 }; 17533 17534 static xtensa_arg_internal Iclass_ae_iclass_movq56_args[] = { 17535 { { OPERAND_qr1_w }, 'o' }, 17536 { { OPERAND_qr0_rw }, 'i' } 17537 }; 17538 17539 static xtensa_arg_internal Iclass_ae_iclass_movq56_stateArgs[] = { 17540 { { STATE_CPENABLE }, 'i' } 17541 }; 17542 17543 static xtensa_arg_internal Iclass_ae_iclass_movtq56_args[] = { 17544 { { OPERAND_qr1_w }, 'm' }, 17545 { { OPERAND_qr0_rw }, 'i' }, 17546 { { OPERAND_bs }, 'i' } 17547 }; 17548 17549 static xtensa_arg_internal Iclass_ae_iclass_movtq56_stateArgs[] = { 17550 { { STATE_CPENABLE }, 'i' } 17551 }; 17552 17553 static xtensa_arg_internal Iclass_ae_iclass_movfq56_args[] = { 17554 { { OPERAND_qr1_w }, 'm' }, 17555 { { OPERAND_qr0_rw }, 'i' }, 17556 { { OPERAND_bs }, 'i' } 17557 }; 17558 17559 static xtensa_arg_internal Iclass_ae_iclass_movfq56_stateArgs[] = { 17560 { { STATE_CPENABLE }, 'i' } 17561 }; 17562 17563 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_args[] = { 17564 { { OPERAND_qr1_w }, 'o' }, 17565 { { OPERAND_ars }, 'i' } 17566 }; 17567 17568 static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = { 17569 { { STATE_CPENABLE }, 'i' } 17570 }; 17571 17572 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = { 17573 { { OPERAND_qr1_w }, 'o' }, 17574 { { OPERAND_cvt_pr }, 'i' } 17575 }; 17576 17577 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = { 17578 { { STATE_CPENABLE }, 'i' } 17579 }; 17580 17581 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = { 17582 { { OPERAND_qr1_w }, 'o' }, 17583 { { OPERAND_cvt_pr }, 'i' } 17584 }; 17585 17586 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = { 17587 { { STATE_CPENABLE }, 'i' } 17588 }; 17589 17590 static xtensa_arg_internal Iclass_ae_iclass_satq48s_args[] = { 17591 { { OPERAND_qr1_w }, 'o' }, 17592 { { OPERAND_qr0 }, 'i' } 17593 }; 17594 17595 static xtensa_arg_internal Iclass_ae_iclass_satq48s_stateArgs[] = { 17596 { { STATE_AE_OVERFLOW }, 'm' }, 17597 { { STATE_CPENABLE }, 'i' } 17598 }; 17599 17600 static xtensa_arg_internal Iclass_ae_iclass_truncq32_args[] = { 17601 { { OPERAND_qr1_w }, 'o' }, 17602 { { OPERAND_qr0_rw }, 'i' } 17603 }; 17604 17605 static xtensa_arg_internal Iclass_ae_iclass_truncq32_stateArgs[] = { 17606 { { STATE_CPENABLE }, 'i' } 17607 }; 17608 17609 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_args[] = { 17610 { { OPERAND_qr1_w }, 'o' }, 17611 { { OPERAND_qr0_rw }, 'i' } 17612 }; 17613 17614 static xtensa_arg_internal Iclass_ae_iclass_roundsq32sym_stateArgs[] = { 17615 { { STATE_AE_OVERFLOW }, 'm' }, 17616 { { STATE_CPENABLE }, 'i' } 17617 }; 17618 17619 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_args[] = { 17620 { { OPERAND_qr1_w }, 'o' }, 17621 { { OPERAND_qr0_rw }, 'i' } 17622 }; 17623 17624 static xtensa_arg_internal Iclass_ae_iclass_roundsq32asym_stateArgs[] = { 17625 { { STATE_AE_OVERFLOW }, 'm' }, 17626 { { STATE_CPENABLE }, 'i' } 17627 }; 17628 17629 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_args[] = { 17630 { { OPERAND_ars }, 'o' }, 17631 { { OPERAND_qr0_rw }, 'i' } 17632 }; 17633 17634 static xtensa_arg_internal Iclass_ae_iclass_trunca32q48_stateArgs[] = { 17635 { { STATE_CPENABLE }, 'i' } 17636 }; 17637 17638 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_args[] = { 17639 { { OPERAND_ars }, 'o' }, 17640 { { OPERAND_pr }, 'i' } 17641 }; 17642 17643 static xtensa_arg_internal Iclass_ae_iclass_movap24s_l_stateArgs[] = { 17644 { { STATE_CPENABLE }, 'i' } 17645 }; 17646 17647 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_args[] = { 17648 { { OPERAND_ars }, 'o' }, 17649 { { OPERAND_pr }, 'i' } 17650 }; 17651 17652 static xtensa_arg_internal Iclass_ae_iclass_movap24s_h_stateArgs[] = { 17653 { { STATE_CPENABLE }, 'i' } 17654 }; 17655 17656 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_args[] = { 17657 { { OPERAND_ars }, 'o' }, 17658 { { OPERAND_pr }, 'i' } 17659 }; 17660 17661 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_l_stateArgs[] = { 17662 { { STATE_CPENABLE }, 'i' } 17663 }; 17664 17665 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_args[] = { 17666 { { OPERAND_ars }, 'o' }, 17667 { { OPERAND_pr }, 'i' } 17668 }; 17669 17670 static xtensa_arg_internal Iclass_ae_iclass_trunca16p24s_h_stateArgs[] = { 17671 { { STATE_CPENABLE }, 'i' } 17672 }; 17673 17674 static xtensa_arg_internal Iclass_ae_iclass_addp24_args[] = { 17675 { { OPERAND_ps }, 'o' }, 17676 { { OPERAND_pr }, 'i' }, 17677 { { OPERAND_pr0 }, 'i' } 17678 }; 17679 17680 static xtensa_arg_internal Iclass_ae_iclass_addp24_stateArgs[] = { 17681 { { STATE_CPENABLE }, 'i' } 17682 }; 17683 17684 static xtensa_arg_internal Iclass_ae_iclass_subp24_args[] = { 17685 { { OPERAND_ps }, 'o' }, 17686 { { OPERAND_pr }, 'i' }, 17687 { { OPERAND_pr0 }, 'i' } 17688 }; 17689 17690 static xtensa_arg_internal Iclass_ae_iclass_subp24_stateArgs[] = { 17691 { { STATE_CPENABLE }, 'i' } 17692 }; 17693 17694 static xtensa_arg_internal Iclass_ae_iclass_negp24_args[] = { 17695 { { OPERAND_ps }, 'o' }, 17696 { { OPERAND_pr0 }, 'i' } 17697 }; 17698 17699 static xtensa_arg_internal Iclass_ae_iclass_negp24_stateArgs[] = { 17700 { { STATE_CPENABLE }, 'i' } 17701 }; 17702 17703 static xtensa_arg_internal Iclass_ae_iclass_absp24_args[] = { 17704 { { OPERAND_ps }, 'o' }, 17705 { { OPERAND_pr0 }, 'i' } 17706 }; 17707 17708 static xtensa_arg_internal Iclass_ae_iclass_absp24_stateArgs[] = { 17709 { { STATE_CPENABLE }, 'i' } 17710 }; 17711 17712 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_args[] = { 17713 { { OPERAND_ps }, 'o' }, 17714 { { OPERAND_pr }, 'i' }, 17715 { { OPERAND_pr0 }, 'i' } 17716 }; 17717 17718 static xtensa_arg_internal Iclass_ae_iclass_maxp24s_stateArgs[] = { 17719 { { STATE_CPENABLE }, 'i' } 17720 }; 17721 17722 static xtensa_arg_internal Iclass_ae_iclass_minp24s_args[] = { 17723 { { OPERAND_ps }, 'o' }, 17724 { { OPERAND_pr }, 'i' }, 17725 { { OPERAND_pr0 }, 'i' } 17726 }; 17727 17728 static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = { 17729 { { STATE_CPENABLE }, 'i' } 17730 }; 17731 17732 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = { 17733 { { OPERAND_alupppb_ps }, 'o' }, 17734 { { OPERAND_pr }, 'i' }, 17735 { { OPERAND_pr0 }, 'i' }, 17736 { { OPERAND_bt2 }, 'o' } 17737 }; 17738 17739 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = { 17740 { { STATE_CPENABLE }, 'i' } 17741 }; 17742 17743 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = { 17744 { { OPERAND_alupppb_ps }, 'o' }, 17745 { { OPERAND_pr }, 'i' }, 17746 { { OPERAND_pr0 }, 'i' }, 17747 { { OPERAND_bt2 }, 'o' } 17748 }; 17749 17750 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_stateArgs[] = { 17751 { { STATE_CPENABLE }, 'i' } 17752 }; 17753 17754 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_args[] = { 17755 { { OPERAND_ps }, 'o' }, 17756 { { OPERAND_pr }, 'i' }, 17757 { { OPERAND_pr0 }, 'i' } 17758 }; 17759 17760 static xtensa_arg_internal Iclass_ae_iclass_addsp24s_stateArgs[] = { 17761 { { STATE_AE_OVERFLOW }, 'm' }, 17762 { { STATE_CPENABLE }, 'i' } 17763 }; 17764 17765 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_args[] = { 17766 { { OPERAND_ps }, 'o' }, 17767 { { OPERAND_pr }, 'i' }, 17768 { { OPERAND_pr0 }, 'i' } 17769 }; 17770 17771 static xtensa_arg_internal Iclass_ae_iclass_subsp24s_stateArgs[] = { 17772 { { STATE_AE_OVERFLOW }, 'm' }, 17773 { { STATE_CPENABLE }, 'i' } 17774 }; 17775 17776 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_args[] = { 17777 { { OPERAND_ps }, 'o' }, 17778 { { OPERAND_pr0 }, 'i' } 17779 }; 17780 17781 static xtensa_arg_internal Iclass_ae_iclass_negsp24s_stateArgs[] = { 17782 { { STATE_AE_OVERFLOW }, 'm' }, 17783 { { STATE_CPENABLE }, 'i' } 17784 }; 17785 17786 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_args[] = { 17787 { { OPERAND_ps }, 'o' }, 17788 { { OPERAND_pr0 }, 'i' } 17789 }; 17790 17791 static xtensa_arg_internal Iclass_ae_iclass_abssp24s_stateArgs[] = { 17792 { { STATE_AE_OVERFLOW }, 'm' }, 17793 { { STATE_CPENABLE }, 'i' } 17794 }; 17795 17796 static xtensa_arg_internal Iclass_ae_iclass_andp48_args[] = { 17797 { { OPERAND_ps }, 'o' }, 17798 { { OPERAND_pr }, 'i' }, 17799 { { OPERAND_pr0 }, 'i' } 17800 }; 17801 17802 static xtensa_arg_internal Iclass_ae_iclass_andp48_stateArgs[] = { 17803 { { STATE_CPENABLE }, 'i' } 17804 }; 17805 17806 static xtensa_arg_internal Iclass_ae_iclass_nandp48_args[] = { 17807 { { OPERAND_ps }, 'o' }, 17808 { { OPERAND_pr }, 'i' }, 17809 { { OPERAND_pr0 }, 'i' } 17810 }; 17811 17812 static xtensa_arg_internal Iclass_ae_iclass_nandp48_stateArgs[] = { 17813 { { STATE_CPENABLE }, 'i' } 17814 }; 17815 17816 static xtensa_arg_internal Iclass_ae_iclass_orp48_args[] = { 17817 { { OPERAND_ps }, 'o' }, 17818 { { OPERAND_pr }, 'i' }, 17819 { { OPERAND_pr0 }, 'i' } 17820 }; 17821 17822 static xtensa_arg_internal Iclass_ae_iclass_orp48_stateArgs[] = { 17823 { { STATE_CPENABLE }, 'i' } 17824 }; 17825 17826 static xtensa_arg_internal Iclass_ae_iclass_xorp48_args[] = { 17827 { { OPERAND_ps }, 'o' }, 17828 { { OPERAND_pr }, 'i' }, 17829 { { OPERAND_pr0 }, 'i' } 17830 }; 17831 17832 static xtensa_arg_internal Iclass_ae_iclass_xorp48_stateArgs[] = { 17833 { { STATE_CPENABLE }, 'i' } 17834 }; 17835 17836 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_args[] = { 17837 { { OPERAND_bt2 }, 'o' }, 17838 { { OPERAND_pr }, 'i' }, 17839 { { OPERAND_pr0 }, 'i' } 17840 }; 17841 17842 static xtensa_arg_internal Iclass_ae_iclass_ltp24s_stateArgs[] = { 17843 { { STATE_CPENABLE }, 'i' } 17844 }; 17845 17846 static xtensa_arg_internal Iclass_ae_iclass_lep24s_args[] = { 17847 { { OPERAND_bt2 }, 'o' }, 17848 { { OPERAND_pr }, 'i' }, 17849 { { OPERAND_pr0 }, 'i' } 17850 }; 17851 17852 static xtensa_arg_internal Iclass_ae_iclass_lep24s_stateArgs[] = { 17853 { { STATE_CPENABLE }, 'i' } 17854 }; 17855 17856 static xtensa_arg_internal Iclass_ae_iclass_eqp24_args[] = { 17857 { { OPERAND_bt2 }, 'o' }, 17858 { { OPERAND_pr }, 'i' }, 17859 { { OPERAND_pr0 }, 'i' } 17860 }; 17861 17862 static xtensa_arg_internal Iclass_ae_iclass_eqp24_stateArgs[] = { 17863 { { STATE_CPENABLE }, 'i' } 17864 }; 17865 17866 static xtensa_arg_internal Iclass_ae_iclass_addq56_args[] = { 17867 { { OPERAND_qr1_w }, 'o' }, 17868 { { OPERAND_qr0_rw }, 'i' }, 17869 { { OPERAND_qr0 }, 'i' } 17870 }; 17871 17872 static xtensa_arg_internal Iclass_ae_iclass_addq56_stateArgs[] = { 17873 { { STATE_CPENABLE }, 'i' } 17874 }; 17875 17876 static xtensa_arg_internal Iclass_ae_iclass_subq56_args[] = { 17877 { { OPERAND_qr1_w }, 'o' }, 17878 { { OPERAND_qr0_rw }, 'i' }, 17879 { { OPERAND_qr0 }, 'i' } 17880 }; 17881 17882 static xtensa_arg_internal Iclass_ae_iclass_subq56_stateArgs[] = { 17883 { { STATE_CPENABLE }, 'i' } 17884 }; 17885 17886 static xtensa_arg_internal Iclass_ae_iclass_negq56_args[] = { 17887 { { OPERAND_qr1_w }, 'o' }, 17888 { { OPERAND_qr0 }, 'i' } 17889 }; 17890 17891 static xtensa_arg_internal Iclass_ae_iclass_negq56_stateArgs[] = { 17892 { { STATE_CPENABLE }, 'i' } 17893 }; 17894 17895 static xtensa_arg_internal Iclass_ae_iclass_absq56_args[] = { 17896 { { OPERAND_qr1_w }, 'o' }, 17897 { { OPERAND_qr0 }, 'i' } 17898 }; 17899 17900 static xtensa_arg_internal Iclass_ae_iclass_absq56_stateArgs[] = { 17901 { { STATE_CPENABLE }, 'i' } 17902 }; 17903 17904 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_args[] = { 17905 { { OPERAND_qr1_w }, 'o' }, 17906 { { OPERAND_qr0 }, 'i' }, 17907 { { OPERAND_qr0_rw }, 'i' } 17908 }; 17909 17910 static xtensa_arg_internal Iclass_ae_iclass_maxq56s_stateArgs[] = { 17911 { { STATE_CPENABLE }, 'i' } 17912 }; 17913 17914 static xtensa_arg_internal Iclass_ae_iclass_minq56s_args[] = { 17915 { { OPERAND_qr1_w }, 'o' }, 17916 { { OPERAND_qr0 }, 'i' }, 17917 { { OPERAND_qr0_rw }, 'i' } 17918 }; 17919 17920 static xtensa_arg_internal Iclass_ae_iclass_minq56s_stateArgs[] = { 17921 { { STATE_CPENABLE }, 'i' } 17922 }; 17923 17924 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_args[] = { 17925 { { OPERAND_qr1_w }, 'o' }, 17926 { { OPERAND_qr0 }, 'i' }, 17927 { { OPERAND_qr0_rw }, 'i' }, 17928 { { OPERAND_bt }, 'o' } 17929 }; 17930 17931 static xtensa_arg_internal Iclass_ae_iclass_maxbq56s_stateArgs[] = { 17932 { { STATE_CPENABLE }, 'i' } 17933 }; 17934 17935 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_args[] = { 17936 { { OPERAND_qr1_w }, 'o' }, 17937 { { OPERAND_qr0 }, 'i' }, 17938 { { OPERAND_qr0_rw }, 'i' }, 17939 { { OPERAND_bt }, 'o' } 17940 }; 17941 17942 static xtensa_arg_internal Iclass_ae_iclass_minbq56s_stateArgs[] = { 17943 { { STATE_CPENABLE }, 'i' } 17944 }; 17945 17946 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_args[] = { 17947 { { OPERAND_qr1_w }, 'o' }, 17948 { { OPERAND_qr0_rw }, 'i' }, 17949 { { OPERAND_qr0 }, 'i' } 17950 }; 17951 17952 static xtensa_arg_internal Iclass_ae_iclass_addsq56s_stateArgs[] = { 17953 { { STATE_AE_OVERFLOW }, 'm' }, 17954 { { STATE_CPENABLE }, 'i' } 17955 }; 17956 17957 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_args[] = { 17958 { { OPERAND_qr1_w }, 'o' }, 17959 { { OPERAND_qr0_rw }, 'i' }, 17960 { { OPERAND_qr0 }, 'i' } 17961 }; 17962 17963 static xtensa_arg_internal Iclass_ae_iclass_subsq56s_stateArgs[] = { 17964 { { STATE_AE_OVERFLOW }, 'm' }, 17965 { { STATE_CPENABLE }, 'i' } 17966 }; 17967 17968 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_args[] = { 17969 { { OPERAND_qr1_w }, 'o' }, 17970 { { OPERAND_qr0 }, 'i' } 17971 }; 17972 17973 static xtensa_arg_internal Iclass_ae_iclass_negsq56s_stateArgs[] = { 17974 { { STATE_AE_OVERFLOW }, 'm' }, 17975 { { STATE_CPENABLE }, 'i' } 17976 }; 17977 17978 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_args[] = { 17979 { { OPERAND_qr1_w }, 'o' }, 17980 { { OPERAND_qr0 }, 'i' } 17981 }; 17982 17983 static xtensa_arg_internal Iclass_ae_iclass_abssq56s_stateArgs[] = { 17984 { { STATE_AE_OVERFLOW }, 'm' }, 17985 { { STATE_CPENABLE }, 'i' } 17986 }; 17987 17988 static xtensa_arg_internal Iclass_ae_iclass_andq56_args[] = { 17989 { { OPERAND_qr1_w }, 'o' }, 17990 { { OPERAND_qr0 }, 'i' }, 17991 { { OPERAND_qr0_rw }, 'i' } 17992 }; 17993 17994 static xtensa_arg_internal Iclass_ae_iclass_andq56_stateArgs[] = { 17995 { { STATE_CPENABLE }, 'i' } 17996 }; 17997 17998 static xtensa_arg_internal Iclass_ae_iclass_nandq56_args[] = { 17999 { { OPERAND_qr1_w }, 'o' }, 18000 { { OPERAND_qr0 }, 'i' }, 18001 { { OPERAND_qr0_rw }, 'i' } 18002 }; 18003 18004 static xtensa_arg_internal Iclass_ae_iclass_nandq56_stateArgs[] = { 18005 { { STATE_CPENABLE }, 'i' } 18006 }; 18007 18008 static xtensa_arg_internal Iclass_ae_iclass_orq56_args[] = { 18009 { { OPERAND_qr1_w }, 'o' }, 18010 { { OPERAND_qr0 }, 'i' }, 18011 { { OPERAND_qr0_rw }, 'i' } 18012 }; 18013 18014 static xtensa_arg_internal Iclass_ae_iclass_orq56_stateArgs[] = { 18015 { { STATE_CPENABLE }, 'i' } 18016 }; 18017 18018 static xtensa_arg_internal Iclass_ae_iclass_xorq56_args[] = { 18019 { { OPERAND_qr1_w }, 'o' }, 18020 { { OPERAND_qr0 }, 'i' }, 18021 { { OPERAND_qr0_rw }, 'i' } 18022 }; 18023 18024 static xtensa_arg_internal Iclass_ae_iclass_xorq56_stateArgs[] = { 18025 { { STATE_CPENABLE }, 'i' } 18026 }; 18027 18028 static xtensa_arg_internal Iclass_ae_iclass_sllip24_args[] = { 18029 { { OPERAND_ps }, 'o' }, 18030 { { OPERAND_pr }, 'i' }, 18031 { { OPERAND_ae_samt32 }, 'i' } 18032 }; 18033 18034 static xtensa_arg_internal Iclass_ae_iclass_sllip24_stateArgs[] = { 18035 { { STATE_CPENABLE }, 'i' } 18036 }; 18037 18038 static xtensa_arg_internal Iclass_ae_iclass_srlip24_args[] = { 18039 { { OPERAND_ps }, 'o' }, 18040 { { OPERAND_pr }, 'i' }, 18041 { { OPERAND_ae_samt32 }, 'i' } 18042 }; 18043 18044 static xtensa_arg_internal Iclass_ae_iclass_srlip24_stateArgs[] = { 18045 { { STATE_CPENABLE }, 'i' } 18046 }; 18047 18048 static xtensa_arg_internal Iclass_ae_iclass_sraip24_args[] = { 18049 { { OPERAND_ps }, 'o' }, 18050 { { OPERAND_pr }, 'i' }, 18051 { { OPERAND_ae_samt32 }, 'i' } 18052 }; 18053 18054 static xtensa_arg_internal Iclass_ae_iclass_sraip24_stateArgs[] = { 18055 { { STATE_CPENABLE }, 'i' } 18056 }; 18057 18058 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_args[] = { 18059 { { OPERAND_ps }, 'o' }, 18060 { { OPERAND_pr }, 'i' } 18061 }; 18062 18063 static xtensa_arg_internal Iclass_ae_iclass_sllsp24_stateArgs[] = { 18064 { { STATE_AE_SAR }, 'i' }, 18065 { { STATE_CPENABLE }, 'i' } 18066 }; 18067 18068 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_args[] = { 18069 { { OPERAND_ps }, 'o' }, 18070 { { OPERAND_pr }, 'i' } 18071 }; 18072 18073 static xtensa_arg_internal Iclass_ae_iclass_srlsp24_stateArgs[] = { 18074 { { STATE_AE_SAR }, 'i' }, 18075 { { STATE_CPENABLE }, 'i' } 18076 }; 18077 18078 static xtensa_arg_internal Iclass_ae_iclass_srasp24_args[] = { 18079 { { OPERAND_ps }, 'o' }, 18080 { { OPERAND_pr }, 'i' } 18081 }; 18082 18083 static xtensa_arg_internal Iclass_ae_iclass_srasp24_stateArgs[] = { 18084 { { STATE_AE_SAR }, 'i' }, 18085 { { STATE_CPENABLE }, 'i' } 18086 }; 18087 18088 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_args[] = { 18089 { { OPERAND_ps }, 'o' }, 18090 { { OPERAND_pr }, 'i' }, 18091 { { OPERAND_ae_samt32 }, 'i' } 18092 }; 18093 18094 static xtensa_arg_internal Iclass_ae_iclass_sllisp24s_stateArgs[] = { 18095 { { STATE_AE_OVERFLOW }, 'm' }, 18096 { { STATE_CPENABLE }, 'i' } 18097 }; 18098 18099 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_args[] = { 18100 { { OPERAND_ps }, 'o' }, 18101 { { OPERAND_pr }, 'i' } 18102 }; 18103 18104 static xtensa_arg_internal Iclass_ae_iclass_sllssp24s_stateArgs[] = { 18105 { { STATE_AE_OVERFLOW }, 'm' }, 18106 { { STATE_AE_SAR }, 'i' }, 18107 { { STATE_CPENABLE }, 'i' } 18108 }; 18109 18110 static xtensa_arg_internal Iclass_ae_iclass_slliq56_args[] = { 18111 { { OPERAND_qr1_w }, 'o' }, 18112 { { OPERAND_qr0_rw }, 'i' }, 18113 { { OPERAND_ae_samt64 }, 'i' } 18114 }; 18115 18116 static xtensa_arg_internal Iclass_ae_iclass_slliq56_stateArgs[] = { 18117 { { STATE_CPENABLE }, 'i' } 18118 }; 18119 18120 static xtensa_arg_internal Iclass_ae_iclass_srliq56_args[] = { 18121 { { OPERAND_qr1_w }, 'o' }, 18122 { { OPERAND_qr0_rw }, 'i' }, 18123 { { OPERAND_ae_samt64 }, 'i' } 18124 }; 18125 18126 static xtensa_arg_internal Iclass_ae_iclass_srliq56_stateArgs[] = { 18127 { { STATE_CPENABLE }, 'i' } 18128 }; 18129 18130 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_args[] = { 18131 { { OPERAND_qr1_w }, 'o' }, 18132 { { OPERAND_qr0_rw }, 'i' }, 18133 { { OPERAND_ae_samt64 }, 'i' } 18134 }; 18135 18136 static xtensa_arg_internal Iclass_ae_iclass_sraiq56_stateArgs[] = { 18137 { { STATE_CPENABLE }, 'i' } 18138 }; 18139 18140 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_args[] = { 18141 { { OPERAND_qr1_w }, 'o' }, 18142 { { OPERAND_qr0_rw }, 'i' } 18143 }; 18144 18145 static xtensa_arg_internal Iclass_ae_iclass_sllsq56_stateArgs[] = { 18146 { { STATE_AE_SAR }, 'i' }, 18147 { { STATE_CPENABLE }, 'i' } 18148 }; 18149 18150 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_args[] = { 18151 { { OPERAND_qr1_w }, 'o' }, 18152 { { OPERAND_qr0_rw }, 'i' } 18153 }; 18154 18155 static xtensa_arg_internal Iclass_ae_iclass_srlsq56_stateArgs[] = { 18156 { { STATE_AE_SAR }, 'i' }, 18157 { { STATE_CPENABLE }, 'i' } 18158 }; 18159 18160 static xtensa_arg_internal Iclass_ae_iclass_srasq56_args[] = { 18161 { { OPERAND_qr1_w }, 'o' }, 18162 { { OPERAND_qr0_rw }, 'i' } 18163 }; 18164 18165 static xtensa_arg_internal Iclass_ae_iclass_srasq56_stateArgs[] = { 18166 { { STATE_AE_SAR }, 'i' }, 18167 { { STATE_CPENABLE }, 'i' } 18168 }; 18169 18170 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_args[] = { 18171 { { OPERAND_qr1_w }, 'o' }, 18172 { { OPERAND_qr0_rw }, 'i' }, 18173 { { OPERAND_ars }, 'i' } 18174 }; 18175 18176 static xtensa_arg_internal Iclass_ae_iclass_sllaq56_stateArgs[] = { 18177 { { STATE_CPENABLE }, 'i' } 18178 }; 18179 18180 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_args[] = { 18181 { { OPERAND_qr1_w }, 'o' }, 18182 { { OPERAND_qr0_rw }, 'i' }, 18183 { { OPERAND_ars }, 'i' } 18184 }; 18185 18186 static xtensa_arg_internal Iclass_ae_iclass_srlaq56_stateArgs[] = { 18187 { { STATE_CPENABLE }, 'i' } 18188 }; 18189 18190 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_args[] = { 18191 { { OPERAND_qr1_w }, 'o' }, 18192 { { OPERAND_qr0_rw }, 'i' }, 18193 { { OPERAND_ars }, 'i' } 18194 }; 18195 18196 static xtensa_arg_internal Iclass_ae_iclass_sraaq56_stateArgs[] = { 18197 { { STATE_CPENABLE }, 'i' } 18198 }; 18199 18200 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_args[] = { 18201 { { OPERAND_qr1_w }, 'o' }, 18202 { { OPERAND_qr0_rw }, 'i' }, 18203 { { OPERAND_ae_samt64 }, 'i' } 18204 }; 18205 18206 static xtensa_arg_internal Iclass_ae_iclass_sllisq56s_stateArgs[] = { 18207 { { STATE_AE_OVERFLOW }, 'm' }, 18208 { { STATE_CPENABLE }, 'i' } 18209 }; 18210 18211 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_args[] = { 18212 { { OPERAND_qr1_w }, 'o' }, 18213 { { OPERAND_qr0_rw }, 'i' } 18214 }; 18215 18216 static xtensa_arg_internal Iclass_ae_iclass_sllssq56s_stateArgs[] = { 18217 { { STATE_AE_OVERFLOW }, 'm' }, 18218 { { STATE_AE_SAR }, 'i' }, 18219 { { STATE_CPENABLE }, 'i' } 18220 }; 18221 18222 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_args[] = { 18223 { { OPERAND_qr1_w }, 'o' }, 18224 { { OPERAND_qr0_rw }, 'i' }, 18225 { { OPERAND_ars }, 'i' } 18226 }; 18227 18228 static xtensa_arg_internal Iclass_ae_iclass_sllasq56s_stateArgs[] = { 18229 { { STATE_AE_OVERFLOW }, 'm' }, 18230 { { STATE_CPENABLE }, 'i' } 18231 }; 18232 18233 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_args[] = { 18234 { { OPERAND_bt }, 'o' }, 18235 { { OPERAND_qr0 }, 'i' }, 18236 { { OPERAND_qr0_rw }, 'i' } 18237 }; 18238 18239 static xtensa_arg_internal Iclass_ae_iclass_ltq56s_stateArgs[] = { 18240 { { STATE_CPENABLE }, 'i' } 18241 }; 18242 18243 static xtensa_arg_internal Iclass_ae_iclass_leq56s_args[] = { 18244 { { OPERAND_bt }, 'o' }, 18245 { { OPERAND_qr0 }, 'i' }, 18246 { { OPERAND_qr0_rw }, 'i' } 18247 }; 18248 18249 static xtensa_arg_internal Iclass_ae_iclass_leq56s_stateArgs[] = { 18250 { { STATE_CPENABLE }, 'i' } 18251 }; 18252 18253 static xtensa_arg_internal Iclass_ae_iclass_eqq56_args[] = { 18254 { { OPERAND_bt }, 'o' }, 18255 { { OPERAND_qr0 }, 'i' }, 18256 { { OPERAND_qr0_rw }, 'i' } 18257 }; 18258 18259 static xtensa_arg_internal Iclass_ae_iclass_eqq56_stateArgs[] = { 18260 { { STATE_CPENABLE }, 'i' } 18261 }; 18262 18263 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_args[] = { 18264 { { OPERAND_ars }, 'o' }, 18265 { { OPERAND_qr0_rw }, 'i' } 18266 }; 18267 18268 static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = { 18269 { { STATE_CPENABLE }, 'i' } 18270 }; 18271 18272 static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_args[] = { 18273 { { OPERAND_mac_qr1_w }, 'm' }, 18274 { { OPERAND_mac_qr0_rw }, 'i' }, 18275 { { OPERAND_pr }, 'i' } 18276 }; 18277 18278 static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_h_stateArgs[] = { 18279 { { STATE_CPENABLE }, 'i' } 18280 }; 18281 18282 static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_args[] = { 18283 { { OPERAND_mac_qr1_w }, 'm' }, 18284 { { OPERAND_mac_qr0_rw }, 'i' }, 18285 { { OPERAND_pr }, 'i' } 18286 }; 18287 18288 static xtensa_arg_internal Iclass_ae_iclass_mulsrfq32sp24s_l_stateArgs[] = { 18289 { { STATE_CPENABLE }, 'i' } 18290 }; 18291 18292 static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_args[] = { 18293 { { OPERAND_mac_qr1_w }, 'm' }, 18294 { { OPERAND_mac_qr0_rw }, 'i' }, 18295 { { OPERAND_pr }, 'i' } 18296 }; 18297 18298 static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_h_stateArgs[] = { 18299 { { STATE_CPENABLE }, 'i' } 18300 }; 18301 18302 static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_args[] = { 18303 { { OPERAND_mac_qr1_w }, 'm' }, 18304 { { OPERAND_mac_qr0_rw }, 'i' }, 18305 { { OPERAND_pr }, 'i' } 18306 }; 18307 18308 static xtensa_arg_internal Iclass_ae_iclass_mularfq32sp24s_l_stateArgs[] = { 18309 { { STATE_CPENABLE }, 'i' } 18310 }; 18311 18312 static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_args[] = { 18313 { { OPERAND_mac_qr1_w }, 'o' }, 18314 { { OPERAND_mac_qr0_rw }, 'i' }, 18315 { { OPERAND_pr }, 'i' } 18316 }; 18317 18318 static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_h_stateArgs[] = { 18319 { { STATE_CPENABLE }, 'i' } 18320 }; 18321 18322 static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_args[] = { 18323 { { OPERAND_mac_qr1_w }, 'o' }, 18324 { { OPERAND_mac_qr0_rw }, 'i' }, 18325 { { OPERAND_pr }, 'i' } 18326 }; 18327 18328 static xtensa_arg_internal Iclass_ae_iclass_mulrfq32sp24s_l_stateArgs[] = { 18329 { { STATE_CPENABLE }, 'i' } 18330 }; 18331 18332 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_args[] = { 18333 { { OPERAND_mac_qr1_w }, 'm' }, 18334 { { OPERAND_mac_qr0_rw }, 'i' }, 18335 { { OPERAND_pr }, 'i' } 18336 }; 18337 18338 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_h_stateArgs[] = { 18339 { { STATE_CPENABLE }, 'i' } 18340 }; 18341 18342 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_args[] = { 18343 { { OPERAND_mac_qr1_w }, 'm' }, 18344 { { OPERAND_mac_qr0_rw }, 'i' }, 18345 { { OPERAND_pr }, 'i' } 18346 }; 18347 18348 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp24s_l_stateArgs[] = { 18349 { { STATE_CPENABLE }, 'i' } 18350 }; 18351 18352 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_args[] = { 18353 { { OPERAND_mac_qr1_w }, 'm' }, 18354 { { OPERAND_mac_qr0_rw }, 'i' }, 18355 { { OPERAND_pr }, 'i' } 18356 }; 18357 18358 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_h_stateArgs[] = { 18359 { { STATE_CPENABLE }, 'i' } 18360 }; 18361 18362 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_args[] = { 18363 { { OPERAND_mac_qr1_w }, 'm' }, 18364 { { OPERAND_mac_qr0_rw }, 'i' }, 18365 { { OPERAND_pr }, 'i' } 18366 }; 18367 18368 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp24s_l_stateArgs[] = { 18369 { { STATE_CPENABLE }, 'i' } 18370 }; 18371 18372 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_args[] = { 18373 { { OPERAND_mac_qr1_w }, 'o' }, 18374 { { OPERAND_mac_qr0_rw }, 'i' }, 18375 { { OPERAND_pr }, 'i' } 18376 }; 18377 18378 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_h_stateArgs[] = { 18379 { { STATE_CPENABLE }, 'i' } 18380 }; 18381 18382 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_args[] = { 18383 { { OPERAND_mac_qr1_w }, 'o' }, 18384 { { OPERAND_mac_qr0_rw }, 'i' }, 18385 { { OPERAND_pr }, 'i' } 18386 }; 18387 18388 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp24s_l_stateArgs[] = { 18389 { { STATE_CPENABLE }, 'i' } 18390 }; 18391 18392 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = { 18393 { { OPERAND_mac_qr1_w }, 'o' }, 18394 { { OPERAND_pr }, 'i' }, 18395 { { OPERAND_pr0 }, 'i' } 18396 }; 18397 18398 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = { 18399 { { STATE_AE_OVERFLOW }, 'm' }, 18400 { { STATE_CPENABLE }, 'i' } 18401 }; 18402 18403 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = { 18404 { { OPERAND_mac_qr1_w }, 'o' }, 18405 { { OPERAND_pr }, 'i' }, 18406 { { OPERAND_pr0 }, 'i' } 18407 }; 18408 18409 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = { 18410 { { STATE_CPENABLE }, 'i' } 18411 }; 18412 18413 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = { 18414 { { OPERAND_mac_qr1_w }, 'o' }, 18415 { { OPERAND_pr }, 'i' }, 18416 { { OPERAND_pr0 }, 'i' } 18417 }; 18418 18419 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = { 18420 { { STATE_CPENABLE }, 'i' } 18421 }; 18422 18423 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = { 18424 { { OPERAND_mac_qr1_w }, 'o' }, 18425 { { OPERAND_pr }, 'i' }, 18426 { { OPERAND_pr0 }, 'i' } 18427 }; 18428 18429 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = { 18430 { { STATE_AE_OVERFLOW }, 'm' }, 18431 { { STATE_CPENABLE }, 'i' } 18432 }; 18433 18434 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = { 18435 { { OPERAND_mac_qr1_w }, 'o' }, 18436 { { OPERAND_pr }, 'i' }, 18437 { { OPERAND_pr0 }, 'i' } 18438 }; 18439 18440 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = { 18441 { { STATE_CPENABLE }, 'i' } 18442 }; 18443 18444 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = { 18445 { { OPERAND_mac_qr1_w }, 'o' }, 18446 { { OPERAND_pr }, 'i' }, 18447 { { OPERAND_pr0 }, 'i' } 18448 }; 18449 18450 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = { 18451 { { STATE_CPENABLE }, 'i' } 18452 }; 18453 18454 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = { 18455 { { OPERAND_mac_qr1_w }, 'o' }, 18456 { { OPERAND_pr }, 'i' }, 18457 { { OPERAND_pr0 }, 'i' } 18458 }; 18459 18460 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = { 18461 { { STATE_AE_OVERFLOW }, 'm' }, 18462 { { STATE_CPENABLE }, 'i' } 18463 }; 18464 18465 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = { 18466 { { OPERAND_mac_qr1_w }, 'o' }, 18467 { { OPERAND_pr }, 'i' }, 18468 { { OPERAND_pr0 }, 'i' } 18469 }; 18470 18471 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = { 18472 { { STATE_CPENABLE }, 'i' } 18473 }; 18474 18475 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = { 18476 { { OPERAND_mac_qr1_w }, 'o' }, 18477 { { OPERAND_pr }, 'i' }, 18478 { { OPERAND_pr0 }, 'i' } 18479 }; 18480 18481 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = { 18482 { { STATE_CPENABLE }, 'i' } 18483 }; 18484 18485 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = { 18486 { { OPERAND_mac_qr1_w }, 'o' }, 18487 { { OPERAND_pr }, 'i' }, 18488 { { OPERAND_pr0 }, 'i' } 18489 }; 18490 18491 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = { 18492 { { STATE_AE_OVERFLOW }, 'm' }, 18493 { { STATE_CPENABLE }, 'i' } 18494 }; 18495 18496 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = { 18497 { { OPERAND_mac_qr1_w }, 'o' }, 18498 { { OPERAND_pr }, 'i' }, 18499 { { OPERAND_pr0 }, 'i' } 18500 }; 18501 18502 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = { 18503 { { STATE_CPENABLE }, 'i' } 18504 }; 18505 18506 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = { 18507 { { OPERAND_mac_qr1_w }, 'o' }, 18508 { { OPERAND_pr }, 'i' }, 18509 { { OPERAND_pr0 }, 'i' } 18510 }; 18511 18512 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = { 18513 { { STATE_CPENABLE }, 'i' } 18514 }; 18515 18516 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = { 18517 { { OPERAND_mac_qr1_w }, 'm' }, 18518 { { OPERAND_pr }, 'i' }, 18519 { { OPERAND_pr0 }, 'i' } 18520 }; 18521 18522 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = { 18523 { { STATE_AE_OVERFLOW }, 'm' }, 18524 { { STATE_CPENABLE }, 'i' } 18525 }; 18526 18527 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = { 18528 { { OPERAND_mac_qr1_w }, 'm' }, 18529 { { OPERAND_pr }, 'i' }, 18530 { { OPERAND_pr0 }, 'i' } 18531 }; 18532 18533 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = { 18534 { { STATE_CPENABLE }, 'i' } 18535 }; 18536 18537 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = { 18538 { { OPERAND_mac_qr1_w }, 'm' }, 18539 { { OPERAND_pr }, 'i' }, 18540 { { OPERAND_pr0 }, 'i' } 18541 }; 18542 18543 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = { 18544 { { STATE_CPENABLE }, 'i' } 18545 }; 18546 18547 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = { 18548 { { OPERAND_mac_qr1_w }, 'm' }, 18549 { { OPERAND_pr }, 'i' }, 18550 { { OPERAND_pr0 }, 'i' } 18551 }; 18552 18553 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = { 18554 { { STATE_AE_OVERFLOW }, 'm' }, 18555 { { STATE_CPENABLE }, 'i' } 18556 }; 18557 18558 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = { 18559 { { OPERAND_mac_qr1_w }, 'm' }, 18560 { { OPERAND_pr }, 'i' }, 18561 { { OPERAND_pr0 }, 'i' } 18562 }; 18563 18564 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = { 18565 { { STATE_CPENABLE }, 'i' } 18566 }; 18567 18568 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = { 18569 { { OPERAND_mac_qr1_w }, 'm' }, 18570 { { OPERAND_pr }, 'i' }, 18571 { { OPERAND_pr0 }, 'i' } 18572 }; 18573 18574 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = { 18575 { { STATE_CPENABLE }, 'i' } 18576 }; 18577 18578 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = { 18579 { { OPERAND_mac_qr1_w }, 'm' }, 18580 { { OPERAND_pr }, 'i' }, 18581 { { OPERAND_pr0 }, 'i' } 18582 }; 18583 18584 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = { 18585 { { STATE_AE_OVERFLOW }, 'm' }, 18586 { { STATE_CPENABLE }, 'i' } 18587 }; 18588 18589 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = { 18590 { { OPERAND_mac_qr1_w }, 'm' }, 18591 { { OPERAND_pr }, 'i' }, 18592 { { OPERAND_pr0 }, 'i' } 18593 }; 18594 18595 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = { 18596 { { STATE_CPENABLE }, 'i' } 18597 }; 18598 18599 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = { 18600 { { OPERAND_mac_qr1_w }, 'm' }, 18601 { { OPERAND_pr }, 'i' }, 18602 { { OPERAND_pr0 }, 'i' } 18603 }; 18604 18605 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = { 18606 { { STATE_CPENABLE }, 'i' } 18607 }; 18608 18609 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = { 18610 { { OPERAND_mac_qr1_w }, 'm' }, 18611 { { OPERAND_pr }, 'i' }, 18612 { { OPERAND_pr0 }, 'i' } 18613 }; 18614 18615 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = { 18616 { { STATE_AE_OVERFLOW }, 'm' }, 18617 { { STATE_CPENABLE }, 'i' } 18618 }; 18619 18620 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = { 18621 { { OPERAND_mac_qr1_w }, 'm' }, 18622 { { OPERAND_pr }, 'i' }, 18623 { { OPERAND_pr0 }, 'i' } 18624 }; 18625 18626 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = { 18627 { { STATE_CPENABLE }, 'i' } 18628 }; 18629 18630 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = { 18631 { { OPERAND_mac_qr1_w }, 'm' }, 18632 { { OPERAND_pr }, 'i' }, 18633 { { OPERAND_pr0 }, 'i' } 18634 }; 18635 18636 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = { 18637 { { STATE_CPENABLE }, 'i' } 18638 }; 18639 18640 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = { 18641 { { OPERAND_mac_qr1_w }, 'm' }, 18642 { { OPERAND_pr }, 'i' }, 18643 { { OPERAND_pr0 }, 'i' } 18644 }; 18645 18646 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = { 18647 { { STATE_AE_OVERFLOW }, 'm' }, 18648 { { STATE_CPENABLE }, 'i' } 18649 }; 18650 18651 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = { 18652 { { OPERAND_mac_qr1_w }, 'm' }, 18653 { { OPERAND_pr }, 'i' }, 18654 { { OPERAND_pr0 }, 'i' } 18655 }; 18656 18657 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = { 18658 { { STATE_CPENABLE }, 'i' } 18659 }; 18660 18661 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = { 18662 { { OPERAND_mac_qr1_w }, 'm' }, 18663 { { OPERAND_pr }, 'i' }, 18664 { { OPERAND_pr0 }, 'i' } 18665 }; 18666 18667 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = { 18668 { { STATE_CPENABLE }, 'i' } 18669 }; 18670 18671 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = { 18672 { { OPERAND_mac_qr1_w }, 'm' }, 18673 { { OPERAND_pr }, 'i' }, 18674 { { OPERAND_pr0 }, 'i' } 18675 }; 18676 18677 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = { 18678 { { STATE_AE_OVERFLOW }, 'm' }, 18679 { { STATE_CPENABLE }, 'i' } 18680 }; 18681 18682 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = { 18683 { { OPERAND_mac_qr1_w }, 'm' }, 18684 { { OPERAND_pr }, 'i' }, 18685 { { OPERAND_pr0 }, 'i' } 18686 }; 18687 18688 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = { 18689 { { STATE_CPENABLE }, 'i' } 18690 }; 18691 18692 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = { 18693 { { OPERAND_mac_qr1_w }, 'm' }, 18694 { { OPERAND_pr }, 'i' }, 18695 { { OPERAND_pr0 }, 'i' } 18696 }; 18697 18698 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = { 18699 { { STATE_CPENABLE }, 'i' } 18700 }; 18701 18702 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = { 18703 { { OPERAND_mac_qr1_w }, 'm' }, 18704 { { OPERAND_pr }, 'i' }, 18705 { { OPERAND_pr0 }, 'i' } 18706 }; 18707 18708 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = { 18709 { { STATE_AE_OVERFLOW }, 'm' }, 18710 { { STATE_CPENABLE }, 'i' } 18711 }; 18712 18713 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = { 18714 { { OPERAND_mac_qr1_w }, 'm' }, 18715 { { OPERAND_pr }, 'i' }, 18716 { { OPERAND_pr0 }, 'i' } 18717 }; 18718 18719 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = { 18720 { { STATE_CPENABLE }, 'i' } 18721 }; 18722 18723 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = { 18724 { { OPERAND_mac_qr1_w }, 'm' }, 18725 { { OPERAND_pr }, 'i' }, 18726 { { OPERAND_pr0 }, 'i' } 18727 }; 18728 18729 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = { 18730 { { STATE_CPENABLE }, 'i' } 18731 }; 18732 18733 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = { 18734 { { OPERAND_mac_qr1_w }, 'm' }, 18735 { { OPERAND_pr }, 'i' }, 18736 { { OPERAND_pr0 }, 'i' } 18737 }; 18738 18739 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = { 18740 { { STATE_AE_OVERFLOW }, 'm' }, 18741 { { STATE_CPENABLE }, 'i' } 18742 }; 18743 18744 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = { 18745 { { OPERAND_mac_qr1_w }, 'm' }, 18746 { { OPERAND_pr }, 'i' }, 18747 { { OPERAND_pr0 }, 'i' } 18748 }; 18749 18750 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = { 18751 { { STATE_CPENABLE }, 'i' } 18752 }; 18753 18754 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = { 18755 { { OPERAND_mac_qr1_w }, 'm' }, 18756 { { OPERAND_pr }, 'i' }, 18757 { { OPERAND_pr0 }, 'i' } 18758 }; 18759 18760 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = { 18761 { { STATE_CPENABLE }, 'i' } 18762 }; 18763 18764 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = { 18765 { { OPERAND_mac_qr1_w }, 'm' }, 18766 { { OPERAND_pr }, 'i' }, 18767 { { OPERAND_pr0 }, 'i' } 18768 }; 18769 18770 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = { 18771 { { STATE_AE_OVERFLOW }, 'm' }, 18772 { { STATE_CPENABLE }, 'i' } 18773 }; 18774 18775 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = { 18776 { { OPERAND_mac_qr1_w }, 'm' }, 18777 { { OPERAND_pr }, 'i' }, 18778 { { OPERAND_pr0 }, 'i' } 18779 }; 18780 18781 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = { 18782 { { STATE_AE_OVERFLOW }, 'm' }, 18783 { { STATE_CPENABLE }, 'i' } 18784 }; 18785 18786 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = { 18787 { { OPERAND_mac_qr1_w }, 'm' }, 18788 { { OPERAND_pr }, 'i' }, 18789 { { OPERAND_pr0 }, 'i' } 18790 }; 18791 18792 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = { 18793 { { STATE_AE_OVERFLOW }, 'm' }, 18794 { { STATE_CPENABLE }, 'i' } 18795 }; 18796 18797 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = { 18798 { { OPERAND_mac_qr1_w }, 'm' }, 18799 { { OPERAND_pr }, 'i' }, 18800 { { OPERAND_pr0 }, 'i' } 18801 }; 18802 18803 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = { 18804 { { STATE_AE_OVERFLOW }, 'm' }, 18805 { { STATE_CPENABLE }, 'i' } 18806 }; 18807 18808 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = { 18809 { { OPERAND_mac_qr1_w }, 'm' }, 18810 { { OPERAND_pr }, 'i' }, 18811 { { OPERAND_pr0 }, 'i' } 18812 }; 18813 18814 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = { 18815 { { STATE_AE_OVERFLOW }, 'm' }, 18816 { { STATE_CPENABLE }, 'i' } 18817 }; 18818 18819 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = { 18820 { { OPERAND_mac_qr1_w }, 'm' }, 18821 { { OPERAND_pr }, 'i' }, 18822 { { OPERAND_pr0 }, 'i' } 18823 }; 18824 18825 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = { 18826 { { STATE_AE_OVERFLOW }, 'm' }, 18827 { { STATE_CPENABLE }, 'i' } 18828 }; 18829 18830 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = { 18831 { { OPERAND_mac_qr1_w }, 'm' }, 18832 { { OPERAND_pr }, 'i' }, 18833 { { OPERAND_pr0 }, 'i' } 18834 }; 18835 18836 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = { 18837 { { STATE_AE_OVERFLOW }, 'm' }, 18838 { { STATE_CPENABLE }, 'i' } 18839 }; 18840 18841 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = { 18842 { { OPERAND_mac_qr1_w }, 'm' }, 18843 { { OPERAND_pr }, 'i' }, 18844 { { OPERAND_pr0 }, 'i' } 18845 }; 18846 18847 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = { 18848 { { STATE_AE_OVERFLOW }, 'm' }, 18849 { { STATE_CPENABLE }, 'i' } 18850 }; 18851 18852 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = { 18853 { { OPERAND_mac_qr1_w }, 'm' }, 18854 { { OPERAND_pr }, 'i' }, 18855 { { OPERAND_pr0 }, 'i' } 18856 }; 18857 18858 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = { 18859 { { STATE_AE_OVERFLOW }, 'm' }, 18860 { { STATE_CPENABLE }, 'i' } 18861 }; 18862 18863 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = { 18864 { { OPERAND_mac_qr1_w }, 'm' }, 18865 { { OPERAND_pr }, 'i' }, 18866 { { OPERAND_pr0 }, 'i' } 18867 }; 18868 18869 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = { 18870 { { STATE_AE_OVERFLOW }, 'm' }, 18871 { { STATE_CPENABLE }, 'i' } 18872 }; 18873 18874 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = { 18875 { { OPERAND_mac_qr1_w }, 'm' }, 18876 { { OPERAND_pr }, 'i' }, 18877 { { OPERAND_pr0 }, 'i' } 18878 }; 18879 18880 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = { 18881 { { STATE_AE_OVERFLOW }, 'm' }, 18882 { { STATE_CPENABLE }, 'i' } 18883 }; 18884 18885 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = { 18886 { { OPERAND_mac_qr1_w }, 'm' }, 18887 { { OPERAND_pr }, 'i' }, 18888 { { OPERAND_pr0 }, 'i' } 18889 }; 18890 18891 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = { 18892 { { STATE_AE_OVERFLOW }, 'm' }, 18893 { { STATE_CPENABLE }, 'i' } 18894 }; 18895 18896 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = { 18897 { { OPERAND_mac_qr1_w }, 'm' }, 18898 { { OPERAND_pr }, 'i' }, 18899 { { OPERAND_pr0 }, 'i' } 18900 }; 18901 18902 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = { 18903 { { STATE_AE_OVERFLOW }, 'm' }, 18904 { { STATE_CPENABLE }, 'i' } 18905 }; 18906 18907 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = { 18908 { { OPERAND_mac_qr1_w }, 'm' }, 18909 { { OPERAND_pr }, 'i' }, 18910 { { OPERAND_pr0 }, 'i' } 18911 }; 18912 18913 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = { 18914 { { STATE_AE_OVERFLOW }, 'm' }, 18915 { { STATE_CPENABLE }, 'i' } 18916 }; 18917 18918 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = { 18919 { { OPERAND_mac_qr1_w }, 'm' }, 18920 { { OPERAND_pr }, 'i' }, 18921 { { OPERAND_pr0 }, 'i' } 18922 }; 18923 18924 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = { 18925 { { STATE_AE_OVERFLOW }, 'm' }, 18926 { { STATE_CPENABLE }, 'i' } 18927 }; 18928 18929 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = { 18930 { { OPERAND_mac_qr1_w }, 'm' }, 18931 { { OPERAND_pr }, 'i' }, 18932 { { OPERAND_pr0 }, 'i' } 18933 }; 18934 18935 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = { 18936 { { STATE_AE_OVERFLOW }, 'm' }, 18937 { { STATE_CPENABLE }, 'i' } 18938 }; 18939 18940 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = { 18941 { { OPERAND_mac_qr1_w }, 'o' }, 18942 { { OPERAND_mac_qr0_rw }, 'i' }, 18943 { { OPERAND_pr }, 'i' } 18944 }; 18945 18946 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = { 18947 { { STATE_CPENABLE }, 'i' } 18948 }; 18949 18950 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = { 18951 { { OPERAND_mac_qr1_w }, 'o' }, 18952 { { OPERAND_mac_qr0_rw }, 'i' }, 18953 { { OPERAND_pr }, 'i' } 18954 }; 18955 18956 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = { 18957 { { STATE_CPENABLE }, 'i' } 18958 }; 18959 18960 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = { 18961 { { OPERAND_mac_qr1_w }, 'o' }, 18962 { { OPERAND_mac_qr0_rw }, 'i' }, 18963 { { OPERAND_pr }, 'i' } 18964 }; 18965 18966 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = { 18967 { { STATE_CPENABLE }, 'i' } 18968 }; 18969 18970 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = { 18971 { { OPERAND_mac_qr1_w }, 'o' }, 18972 { { OPERAND_mac_qr0_rw }, 'i' }, 18973 { { OPERAND_pr }, 'i' } 18974 }; 18975 18976 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = { 18977 { { STATE_CPENABLE }, 'i' } 18978 }; 18979 18980 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = { 18981 { { OPERAND_mac_qr1_w }, 'o' }, 18982 { { OPERAND_mac_qr0_rw }, 'i' }, 18983 { { OPERAND_pr }, 'i' } 18984 }; 18985 18986 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = { 18987 { { STATE_CPENABLE }, 'i' } 18988 }; 18989 18990 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = { 18991 { { OPERAND_mac_qr1_w }, 'o' }, 18992 { { OPERAND_mac_qr0_rw }, 'i' }, 18993 { { OPERAND_pr }, 'i' } 18994 }; 18995 18996 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = { 18997 { { STATE_CPENABLE }, 'i' } 18998 }; 18999 19000 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = { 19001 { { OPERAND_mac_qr1_w }, 'o' }, 19002 { { OPERAND_mac_qr0_rw }, 'i' }, 19003 { { OPERAND_pr }, 'i' } 19004 }; 19005 19006 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = { 19007 { { STATE_CPENABLE }, 'i' } 19008 }; 19009 19010 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = { 19011 { { OPERAND_mac_qr1_w }, 'o' }, 19012 { { OPERAND_mac_qr0_rw }, 'i' }, 19013 { { OPERAND_pr }, 'i' } 19014 }; 19015 19016 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = { 19017 { { STATE_CPENABLE }, 'i' } 19018 }; 19019 19020 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = { 19021 { { OPERAND_mac_qr1_w }, 'm' }, 19022 { { OPERAND_mac_qr0_rw }, 'i' }, 19023 { { OPERAND_pr }, 'i' } 19024 }; 19025 19026 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = { 19027 { { STATE_CPENABLE }, 'i' } 19028 }; 19029 19030 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = { 19031 { { OPERAND_mac_qr1_w }, 'm' }, 19032 { { OPERAND_mac_qr0_rw }, 'i' }, 19033 { { OPERAND_pr }, 'i' } 19034 }; 19035 19036 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = { 19037 { { STATE_CPENABLE }, 'i' } 19038 }; 19039 19040 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = { 19041 { { OPERAND_mac_qr1_w }, 'm' }, 19042 { { OPERAND_mac_qr0_rw }, 'i' }, 19043 { { OPERAND_pr }, 'i' } 19044 }; 19045 19046 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = { 19047 { { STATE_CPENABLE }, 'i' } 19048 }; 19049 19050 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = { 19051 { { OPERAND_mac_qr1_w }, 'm' }, 19052 { { OPERAND_mac_qr0_rw }, 'i' }, 19053 { { OPERAND_pr }, 'i' } 19054 }; 19055 19056 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = { 19057 { { STATE_CPENABLE }, 'i' } 19058 }; 19059 19060 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = { 19061 { { OPERAND_mac_qr1_w }, 'm' }, 19062 { { OPERAND_mac_qr0_rw }, 'i' }, 19063 { { OPERAND_pr }, 'i' } 19064 }; 19065 19066 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = { 19067 { { STATE_CPENABLE }, 'i' } 19068 }; 19069 19070 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = { 19071 { { OPERAND_mac_qr1_w }, 'm' }, 19072 { { OPERAND_mac_qr0_rw }, 'i' }, 19073 { { OPERAND_pr }, 'i' } 19074 }; 19075 19076 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = { 19077 { { STATE_CPENABLE }, 'i' } 19078 }; 19079 19080 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = { 19081 { { OPERAND_mac_qr1_w }, 'm' }, 19082 { { OPERAND_mac_qr0_rw }, 'i' }, 19083 { { OPERAND_pr }, 'i' } 19084 }; 19085 19086 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = { 19087 { { STATE_CPENABLE }, 'i' } 19088 }; 19089 19090 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = { 19091 { { OPERAND_mac_qr1_w }, 'm' }, 19092 { { OPERAND_mac_qr0_rw }, 'i' }, 19093 { { OPERAND_pr }, 'i' } 19094 }; 19095 19096 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = { 19097 { { STATE_CPENABLE }, 'i' } 19098 }; 19099 19100 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = { 19101 { { OPERAND_mac_qr1_w }, 'm' }, 19102 { { OPERAND_mac_qr0_rw }, 'i' }, 19103 { { OPERAND_pr }, 'i' } 19104 }; 19105 19106 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = { 19107 { { STATE_CPENABLE }, 'i' } 19108 }; 19109 19110 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = { 19111 { { OPERAND_mac_qr1_w }, 'm' }, 19112 { { OPERAND_mac_qr0_rw }, 'i' }, 19113 { { OPERAND_pr }, 'i' } 19114 }; 19115 19116 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = { 19117 { { STATE_CPENABLE }, 'i' } 19118 }; 19119 19120 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = { 19121 { { OPERAND_mac_qr1_w }, 'm' }, 19122 { { OPERAND_mac_qr0_rw }, 'i' }, 19123 { { OPERAND_pr }, 'i' } 19124 }; 19125 19126 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = { 19127 { { STATE_CPENABLE }, 'i' } 19128 }; 19129 19130 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = { 19131 { { OPERAND_mac_qr1_w }, 'm' }, 19132 { { OPERAND_mac_qr0_rw }, 'i' }, 19133 { { OPERAND_pr }, 'i' } 19134 }; 19135 19136 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = { 19137 { { STATE_CPENABLE }, 'i' } 19138 }; 19139 19140 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = { 19141 { { OPERAND_mac_qr1_w }, 'm' }, 19142 { { OPERAND_mac_qr0_rw }, 'i' }, 19143 { { OPERAND_pr }, 'i' } 19144 }; 19145 19146 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = { 19147 { { STATE_CPENABLE }, 'i' } 19148 }; 19149 19150 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = { 19151 { { OPERAND_mac_qr1_w }, 'm' }, 19152 { { OPERAND_mac_qr0_rw }, 'i' }, 19153 { { OPERAND_pr }, 'i' } 19154 }; 19155 19156 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = { 19157 { { STATE_CPENABLE }, 'i' } 19158 }; 19159 19160 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = { 19161 { { OPERAND_mac_qr1_w }, 'm' }, 19162 { { OPERAND_mac_qr0_rw }, 'i' }, 19163 { { OPERAND_pr }, 'i' } 19164 }; 19165 19166 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = { 19167 { { STATE_CPENABLE }, 'i' } 19168 }; 19169 19170 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = { 19171 { { OPERAND_mac_qr1_w }, 'm' }, 19172 { { OPERAND_mac_qr0_rw }, 'i' }, 19173 { { OPERAND_pr }, 'i' } 19174 }; 19175 19176 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = { 19177 { { STATE_CPENABLE }, 'i' } 19178 }; 19179 19180 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = { 19181 { { OPERAND_mac_qr1_w }, 'o' }, 19182 { { OPERAND_mac_qr0_rw }, 'i' }, 19183 { { OPERAND_pr }, 'i' }, 19184 { { OPERAND_mac_qr0 }, 'i' }, 19185 { { OPERAND_pr0 }, 'i' } 19186 }; 19187 19188 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = { 19189 { { STATE_CPENABLE }, 'i' } 19190 }; 19191 19192 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = { 19193 { { OPERAND_mac_qr1_w }, 'o' }, 19194 { { OPERAND_mac_qr0_rw }, 'i' }, 19195 { { OPERAND_pr }, 'i' }, 19196 { { OPERAND_mac_qr0 }, 'i' }, 19197 { { OPERAND_pr0 }, 'i' } 19198 }; 19199 19200 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = { 19201 { { STATE_CPENABLE }, 'i' } 19202 }; 19203 19204 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = { 19205 { { OPERAND_mac_qr1_w }, 'o' }, 19206 { { OPERAND_mac_qr0_rw }, 'i' }, 19207 { { OPERAND_pr }, 'i' }, 19208 { { OPERAND_mac_qr0 }, 'i' }, 19209 { { OPERAND_pr0 }, 'i' } 19210 }; 19211 19212 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = { 19213 { { STATE_CPENABLE }, 'i' } 19214 }; 19215 19216 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = { 19217 { { OPERAND_mac_qr1_w }, 'o' }, 19218 { { OPERAND_mac_qr0_rw }, 'i' }, 19219 { { OPERAND_pr }, 'i' }, 19220 { { OPERAND_mac_qr0 }, 'i' }, 19221 { { OPERAND_pr0 }, 'i' } 19222 }; 19223 19224 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = { 19225 { { STATE_CPENABLE }, 'i' } 19226 }; 19227 19228 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = { 19229 { { OPERAND_mac_qr1_w }, 'o' }, 19230 { { OPERAND_mac_qr0_rw }, 'i' }, 19231 { { OPERAND_pr }, 'i' }, 19232 { { OPERAND_mac_qr0 }, 'i' }, 19233 { { OPERAND_pr0 }, 'i' } 19234 }; 19235 19236 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = { 19237 { { STATE_CPENABLE }, 'i' } 19238 }; 19239 19240 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = { 19241 { { OPERAND_mac_qr1_w }, 'o' }, 19242 { { OPERAND_mac_qr0_rw }, 'i' }, 19243 { { OPERAND_pr }, 'i' }, 19244 { { OPERAND_mac_qr0 }, 'i' }, 19245 { { OPERAND_pr0 }, 'i' } 19246 }; 19247 19248 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = { 19249 { { STATE_CPENABLE }, 'i' } 19250 }; 19251 19252 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = { 19253 { { OPERAND_mac_qr1_w }, 'o' }, 19254 { { OPERAND_mac_qr0_rw }, 'i' }, 19255 { { OPERAND_pr }, 'i' }, 19256 { { OPERAND_mac_qr0 }, 'i' }, 19257 { { OPERAND_pr0 }, 'i' } 19258 }; 19259 19260 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = { 19261 { { STATE_CPENABLE }, 'i' } 19262 }; 19263 19264 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = { 19265 { { OPERAND_mac_qr1_w }, 'o' }, 19266 { { OPERAND_mac_qr0_rw }, 'i' }, 19267 { { OPERAND_pr }, 'i' }, 19268 { { OPERAND_mac_qr0 }, 'i' }, 19269 { { OPERAND_pr0 }, 'i' } 19270 }; 19271 19272 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = { 19273 { { STATE_CPENABLE }, 'i' } 19274 }; 19275 19276 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = { 19277 { { OPERAND_mac_qr1_w }, 'o' }, 19278 { { OPERAND_mac_qr0_rw }, 'i' }, 19279 { { OPERAND_pr }, 'i' }, 19280 { { OPERAND_mac_qr0 }, 'i' }, 19281 { { OPERAND_pr0 }, 'i' } 19282 }; 19283 19284 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = { 19285 { { STATE_CPENABLE }, 'i' } 19286 }; 19287 19288 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = { 19289 { { OPERAND_mac_qr1_w }, 'o' }, 19290 { { OPERAND_mac_qr0_rw }, 'i' }, 19291 { { OPERAND_pr }, 'i' }, 19292 { { OPERAND_mac_qr0 }, 'i' }, 19293 { { OPERAND_pr0 }, 'i' } 19294 }; 19295 19296 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = { 19297 { { STATE_CPENABLE }, 'i' } 19298 }; 19299 19300 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = { 19301 { { OPERAND_mac_qr1_w }, 'o' }, 19302 { { OPERAND_mac_qr0_rw }, 'i' }, 19303 { { OPERAND_pr }, 'i' }, 19304 { { OPERAND_mac_qr0 }, 'i' }, 19305 { { OPERAND_pr0 }, 'i' } 19306 }; 19307 19308 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = { 19309 { { STATE_CPENABLE }, 'i' } 19310 }; 19311 19312 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = { 19313 { { OPERAND_mac_qr1_w }, 'o' }, 19314 { { OPERAND_mac_qr0_rw }, 'i' }, 19315 { { OPERAND_pr }, 'i' }, 19316 { { OPERAND_mac_qr0 }, 'i' }, 19317 { { OPERAND_pr0 }, 'i' } 19318 }; 19319 19320 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = { 19321 { { STATE_CPENABLE }, 'i' } 19322 }; 19323 19324 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = { 19325 { { OPERAND_mac_qr1_w }, 'o' }, 19326 { { OPERAND_mac_qr0_rw }, 'i' }, 19327 { { OPERAND_pr }, 'i' }, 19328 { { OPERAND_mac_qr0 }, 'i' }, 19329 { { OPERAND_pr0 }, 'i' } 19330 }; 19331 19332 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = { 19333 { { STATE_CPENABLE }, 'i' } 19334 }; 19335 19336 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = { 19337 { { OPERAND_mac_qr1_w }, 'o' }, 19338 { { OPERAND_mac_qr0_rw }, 'i' }, 19339 { { OPERAND_pr }, 'i' }, 19340 { { OPERAND_mac_qr0 }, 'i' }, 19341 { { OPERAND_pr0 }, 'i' } 19342 }; 19343 19344 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = { 19345 { { STATE_CPENABLE }, 'i' } 19346 }; 19347 19348 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = { 19349 { { OPERAND_mac_qr1_w }, 'o' }, 19350 { { OPERAND_mac_qr0_rw }, 'i' }, 19351 { { OPERAND_pr }, 'i' }, 19352 { { OPERAND_mac_qr0 }, 'i' }, 19353 { { OPERAND_pr0 }, 'i' } 19354 }; 19355 19356 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = { 19357 { { STATE_CPENABLE }, 'i' } 19358 }; 19359 19360 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = { 19361 { { OPERAND_mac_qr1_w }, 'o' }, 19362 { { OPERAND_mac_qr0_rw }, 'i' }, 19363 { { OPERAND_pr }, 'i' }, 19364 { { OPERAND_mac_qr0 }, 'i' }, 19365 { { OPERAND_pr0 }, 'i' } 19366 }; 19367 19368 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = { 19369 { { STATE_CPENABLE }, 'i' } 19370 }; 19371 19372 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = { 19373 { { OPERAND_mac_qr1_w }, 'o' }, 19374 { { OPERAND_mac_qr0_rw }, 'i' }, 19375 { { OPERAND_pr }, 'i' }, 19376 { { OPERAND_mac_qr0 }, 'i' }, 19377 { { OPERAND_pr0 }, 'i' } 19378 }; 19379 19380 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = { 19381 { { STATE_CPENABLE }, 'i' } 19382 }; 19383 19384 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = { 19385 { { OPERAND_mac_qr1_w }, 'o' }, 19386 { { OPERAND_mac_qr0_rw }, 'i' }, 19387 { { OPERAND_pr }, 'i' }, 19388 { { OPERAND_mac_qr0 }, 'i' }, 19389 { { OPERAND_pr0 }, 'i' } 19390 }; 19391 19392 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = { 19393 { { STATE_CPENABLE }, 'i' } 19394 }; 19395 19396 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = { 19397 { { OPERAND_mac_qr1_w }, 'o' }, 19398 { { OPERAND_mac_qr0_rw }, 'i' }, 19399 { { OPERAND_pr }, 'i' }, 19400 { { OPERAND_mac_qr0 }, 'i' }, 19401 { { OPERAND_pr0 }, 'i' } 19402 }; 19403 19404 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = { 19405 { { STATE_CPENABLE }, 'i' } 19406 }; 19407 19408 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = { 19409 { { OPERAND_mac_qr1_w }, 'o' }, 19410 { { OPERAND_mac_qr0_rw }, 'i' }, 19411 { { OPERAND_pr }, 'i' }, 19412 { { OPERAND_mac_qr0 }, 'i' }, 19413 { { OPERAND_pr0 }, 'i' } 19414 }; 19415 19416 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = { 19417 { { STATE_CPENABLE }, 'i' } 19418 }; 19419 19420 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = { 19421 { { OPERAND_mac_qr1_w }, 'o' }, 19422 { { OPERAND_mac_qr0_rw }, 'i' }, 19423 { { OPERAND_pr }, 'i' }, 19424 { { OPERAND_mac_qr0 }, 'i' }, 19425 { { OPERAND_pr0 }, 'i' } 19426 }; 19427 19428 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = { 19429 { { STATE_CPENABLE }, 'i' } 19430 }; 19431 19432 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = { 19433 { { OPERAND_mac_qr1_w }, 'o' }, 19434 { { OPERAND_mac_qr0_rw }, 'i' }, 19435 { { OPERAND_pr }, 'i' }, 19436 { { OPERAND_mac_qr0 }, 'i' }, 19437 { { OPERAND_pr0 }, 'i' } 19438 }; 19439 19440 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = { 19441 { { STATE_CPENABLE }, 'i' } 19442 }; 19443 19444 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = { 19445 { { OPERAND_mac_qr1_w }, 'o' }, 19446 { { OPERAND_mac_qr0_rw }, 'i' }, 19447 { { OPERAND_pr }, 'i' }, 19448 { { OPERAND_mac_qr0 }, 'i' }, 19449 { { OPERAND_pr0 }, 'i' } 19450 }; 19451 19452 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = { 19453 { { STATE_CPENABLE }, 'i' } 19454 }; 19455 19456 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = { 19457 { { OPERAND_mac_qr1_w }, 'o' }, 19458 { { OPERAND_mac_qr0_rw }, 'i' }, 19459 { { OPERAND_pr }, 'i' }, 19460 { { OPERAND_mac_qr0 }, 'i' }, 19461 { { OPERAND_pr0 }, 'i' } 19462 }; 19463 19464 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = { 19465 { { STATE_CPENABLE }, 'i' } 19466 }; 19467 19468 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = { 19469 { { OPERAND_mac_qr1_w }, 'o' }, 19470 { { OPERAND_mac_qr0_rw }, 'i' }, 19471 { { OPERAND_pr }, 'i' }, 19472 { { OPERAND_mac_qr0 }, 'i' }, 19473 { { OPERAND_pr0 }, 'i' } 19474 }; 19475 19476 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = { 19477 { { STATE_CPENABLE }, 'i' } 19478 }; 19479 19480 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = { 19481 { { OPERAND_mac_qr1_w }, 'o' }, 19482 { { OPERAND_mac_qr0_rw }, 'i' }, 19483 { { OPERAND_pr }, 'i' }, 19484 { { OPERAND_mac_qr0 }, 'i' }, 19485 { { OPERAND_pr0 }, 'i' } 19486 }; 19487 19488 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = { 19489 { { STATE_CPENABLE }, 'i' } 19490 }; 19491 19492 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = { 19493 { { OPERAND_mac_qr1_w }, 'o' }, 19494 { { OPERAND_mac_qr0_rw }, 'i' }, 19495 { { OPERAND_pr }, 'i' }, 19496 { { OPERAND_mac_qr0 }, 'i' }, 19497 { { OPERAND_pr0 }, 'i' } 19498 }; 19499 19500 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = { 19501 { { STATE_CPENABLE }, 'i' } 19502 }; 19503 19504 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = { 19505 { { OPERAND_mac_qr1_w }, 'o' }, 19506 { { OPERAND_mac_qr0_rw }, 'i' }, 19507 { { OPERAND_pr }, 'i' }, 19508 { { OPERAND_mac_qr0 }, 'i' }, 19509 { { OPERAND_pr0 }, 'i' } 19510 }; 19511 19512 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = { 19513 { { STATE_CPENABLE }, 'i' } 19514 }; 19515 19516 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = { 19517 { { OPERAND_mac_qr1_w }, 'o' }, 19518 { { OPERAND_mac_qr0_rw }, 'i' }, 19519 { { OPERAND_pr }, 'i' }, 19520 { { OPERAND_mac_qr0 }, 'i' }, 19521 { { OPERAND_pr0 }, 'i' } 19522 }; 19523 19524 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = { 19525 { { STATE_CPENABLE }, 'i' } 19526 }; 19527 19528 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = { 19529 { { OPERAND_mac_qr1_w }, 'o' }, 19530 { { OPERAND_mac_qr0_rw }, 'i' }, 19531 { { OPERAND_pr }, 'i' }, 19532 { { OPERAND_mac_qr0 }, 'i' }, 19533 { { OPERAND_pr0 }, 'i' } 19534 }; 19535 19536 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = { 19537 { { STATE_CPENABLE }, 'i' } 19538 }; 19539 19540 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = { 19541 { { OPERAND_mac_qr1_w }, 'o' }, 19542 { { OPERAND_mac_qr0_rw }, 'i' }, 19543 { { OPERAND_pr }, 'i' }, 19544 { { OPERAND_mac_qr0 }, 'i' }, 19545 { { OPERAND_pr0 }, 'i' } 19546 }; 19547 19548 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = { 19549 { { STATE_CPENABLE }, 'i' } 19550 }; 19551 19552 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = { 19553 { { OPERAND_mac_qr1_w }, 'o' }, 19554 { { OPERAND_mac_qr0_rw }, 'i' }, 19555 { { OPERAND_pr }, 'i' }, 19556 { { OPERAND_mac_qr0 }, 'i' }, 19557 { { OPERAND_pr0 }, 'i' } 19558 }; 19559 19560 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = { 19561 { { STATE_CPENABLE }, 'i' } 19562 }; 19563 19564 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = { 19565 { { OPERAND_mac_qr1_w }, 'o' }, 19566 { { OPERAND_mac_qr0_rw }, 'i' }, 19567 { { OPERAND_pr }, 'i' }, 19568 { { OPERAND_mac_qr0 }, 'i' }, 19569 { { OPERAND_pr0 }, 'i' } 19570 }; 19571 19572 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = { 19573 { { STATE_CPENABLE }, 'i' } 19574 }; 19575 19576 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = { 19577 { { OPERAND_mac_qr1_w }, 'o' }, 19578 { { OPERAND_mac_qr0_rw }, 'i' }, 19579 { { OPERAND_pr }, 'i' }, 19580 { { OPERAND_mac_qr0 }, 'i' }, 19581 { { OPERAND_pr0 }, 'i' } 19582 }; 19583 19584 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = { 19585 { { STATE_CPENABLE }, 'i' } 19586 }; 19587 19588 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = { 19589 { { OPERAND_mac_qr1_w }, 'o' }, 19590 { { OPERAND_mac_qr0_rw }, 'i' }, 19591 { { OPERAND_pr }, 'i' }, 19592 { { OPERAND_mac_qr0 }, 'i' }, 19593 { { OPERAND_pr0 }, 'i' } 19594 }; 19595 19596 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = { 19597 { { STATE_CPENABLE }, 'i' } 19598 }; 19599 19600 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = { 19601 { { OPERAND_mac_qr1_w }, 'o' }, 19602 { { OPERAND_mac_qr0_rw }, 'i' }, 19603 { { OPERAND_pr }, 'i' }, 19604 { { OPERAND_mac_qr0 }, 'i' }, 19605 { { OPERAND_pr0 }, 'i' } 19606 }; 19607 19608 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = { 19609 { { STATE_CPENABLE }, 'i' } 19610 }; 19611 19612 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = { 19613 { { OPERAND_mac_qr1_w }, 'o' }, 19614 { { OPERAND_mac_qr0_rw }, 'i' }, 19615 { { OPERAND_pr }, 'i' }, 19616 { { OPERAND_mac_qr0 }, 'i' }, 19617 { { OPERAND_pr0 }, 'i' } 19618 }; 19619 19620 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = { 19621 { { STATE_CPENABLE }, 'i' } 19622 }; 19623 19624 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = { 19625 { { OPERAND_mac_qr1_w }, 'o' }, 19626 { { OPERAND_mac_qr0_rw }, 'i' }, 19627 { { OPERAND_pr }, 'i' }, 19628 { { OPERAND_mac_qr0 }, 'i' }, 19629 { { OPERAND_pr0 }, 'i' } 19630 }; 19631 19632 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = { 19633 { { STATE_CPENABLE }, 'i' } 19634 }; 19635 19636 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = { 19637 { { OPERAND_mac_qr1_w }, 'o' }, 19638 { { OPERAND_mac_qr0_rw }, 'i' }, 19639 { { OPERAND_pr }, 'i' }, 19640 { { OPERAND_mac_qr0 }, 'i' }, 19641 { { OPERAND_pr0 }, 'i' } 19642 }; 19643 19644 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = { 19645 { { STATE_CPENABLE }, 'i' } 19646 }; 19647 19648 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = { 19649 { { OPERAND_mac_qr1_w }, 'o' }, 19650 { { OPERAND_mac_qr0_rw }, 'i' }, 19651 { { OPERAND_pr }, 'i' }, 19652 { { OPERAND_mac_qr0 }, 'i' }, 19653 { { OPERAND_pr0 }, 'i' } 19654 }; 19655 19656 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = { 19657 { { STATE_CPENABLE }, 'i' } 19658 }; 19659 19660 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = { 19661 { { OPERAND_mac_qr1_w }, 'o' }, 19662 { { OPERAND_mac_qr0_rw }, 'i' }, 19663 { { OPERAND_pr }, 'i' }, 19664 { { OPERAND_mac_qr0 }, 'i' }, 19665 { { OPERAND_pr0 }, 'i' } 19666 }; 19667 19668 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = { 19669 { { STATE_CPENABLE }, 'i' } 19670 }; 19671 19672 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = { 19673 { { OPERAND_mac_qr1_w }, 'o' }, 19674 { { OPERAND_mac_qr0_rw }, 'i' }, 19675 { { OPERAND_pr }, 'i' }, 19676 { { OPERAND_mac_qr0 }, 'i' }, 19677 { { OPERAND_pr0 }, 'i' } 19678 }; 19679 19680 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = { 19681 { { STATE_CPENABLE }, 'i' } 19682 }; 19683 19684 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = { 19685 { { OPERAND_mac_qr1_w }, 'o' }, 19686 { { OPERAND_mac_qr0_rw }, 'i' }, 19687 { { OPERAND_pr }, 'i' }, 19688 { { OPERAND_mac_qr0 }, 'i' }, 19689 { { OPERAND_pr0 }, 'i' } 19690 }; 19691 19692 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = { 19693 { { STATE_CPENABLE }, 'i' } 19694 }; 19695 19696 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = { 19697 { { OPERAND_mac_qr1_w }, 'o' }, 19698 { { OPERAND_mac_qr0_rw }, 'i' }, 19699 { { OPERAND_pr }, 'i' }, 19700 { { OPERAND_mac_qr0 }, 'i' }, 19701 { { OPERAND_pr0 }, 'i' } 19702 }; 19703 19704 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = { 19705 { { STATE_CPENABLE }, 'i' } 19706 }; 19707 19708 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = { 19709 { { OPERAND_mac_qr1_w }, 'o' }, 19710 { { OPERAND_mac_qr0_rw }, 'i' }, 19711 { { OPERAND_pr }, 'i' }, 19712 { { OPERAND_mac_qr0 }, 'i' }, 19713 { { OPERAND_pr0 }, 'i' } 19714 }; 19715 19716 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = { 19717 { { STATE_CPENABLE }, 'i' } 19718 }; 19719 19720 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = { 19721 { { OPERAND_mac_qr1_w }, 'o' }, 19722 { { OPERAND_mac_qr0_rw }, 'i' }, 19723 { { OPERAND_pr }, 'i' }, 19724 { { OPERAND_mac_qr0 }, 'i' }, 19725 { { OPERAND_pr0 }, 'i' } 19726 }; 19727 19728 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = { 19729 { { STATE_CPENABLE }, 'i' } 19730 }; 19731 19732 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = { 19733 { { OPERAND_mac_qr1_w }, 'o' }, 19734 { { OPERAND_mac_qr0_rw }, 'i' }, 19735 { { OPERAND_pr }, 'i' }, 19736 { { OPERAND_mac_qr0 }, 'i' }, 19737 { { OPERAND_pr0 }, 'i' } 19738 }; 19739 19740 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = { 19741 { { STATE_CPENABLE }, 'i' } 19742 }; 19743 19744 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = { 19745 { { OPERAND_mac_qr1_w }, 'o' }, 19746 { { OPERAND_mac_qr0_rw }, 'i' }, 19747 { { OPERAND_pr }, 'i' }, 19748 { { OPERAND_mac_qr0 }, 'i' }, 19749 { { OPERAND_pr0 }, 'i' } 19750 }; 19751 19752 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = { 19753 { { STATE_CPENABLE }, 'i' } 19754 }; 19755 19756 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = { 19757 { { OPERAND_mac_qr1_w }, 'o' }, 19758 { { OPERAND_pr }, 'i' }, 19759 { { OPERAND_pr0 }, 'i' } 19760 }; 19761 19762 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = { 19763 { { STATE_CPENABLE }, 'i' } 19764 }; 19765 19766 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = { 19767 { { OPERAND_mac_qr1_w }, 'o' }, 19768 { { OPERAND_pr }, 'i' }, 19769 { { OPERAND_pr0 }, 'i' } 19770 }; 19771 19772 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = { 19773 { { STATE_CPENABLE }, 'i' } 19774 }; 19775 19776 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = { 19777 { { OPERAND_mac_qr1_w }, 'o' }, 19778 { { OPERAND_pr }, 'i' }, 19779 { { OPERAND_pr0 }, 'i' } 19780 }; 19781 19782 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = { 19783 { { STATE_CPENABLE }, 'i' } 19784 }; 19785 19786 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = { 19787 { { OPERAND_mac_qr1_w }, 'o' }, 19788 { { OPERAND_pr }, 'i' }, 19789 { { OPERAND_pr0 }, 'i' } 19790 }; 19791 19792 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = { 19793 { { STATE_CPENABLE }, 'i' } 19794 }; 19795 19796 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = { 19797 { { OPERAND_mac_qr1_w }, 'o' }, 19798 { { OPERAND_pr }, 'i' }, 19799 { { OPERAND_pr0 }, 'i' } 19800 }; 19801 19802 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = { 19803 { { STATE_CPENABLE }, 'i' } 19804 }; 19805 19806 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = { 19807 { { OPERAND_mac_qr1_w }, 'o' }, 19808 { { OPERAND_pr }, 'i' }, 19809 { { OPERAND_pr0 }, 'i' } 19810 }; 19811 19812 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = { 19813 { { STATE_CPENABLE }, 'i' } 19814 }; 19815 19816 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = { 19817 { { OPERAND_mac_qr1_w }, 'o' }, 19818 { { OPERAND_pr }, 'i' }, 19819 { { OPERAND_pr0 }, 'i' } 19820 }; 19821 19822 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = { 19823 { { STATE_CPENABLE }, 'i' } 19824 }; 19825 19826 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = { 19827 { { OPERAND_mac_qr1_w }, 'o' }, 19828 { { OPERAND_pr }, 'i' }, 19829 { { OPERAND_pr0 }, 'i' } 19830 }; 19831 19832 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = { 19833 { { STATE_CPENABLE }, 'i' } 19834 }; 19835 19836 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = { 19837 { { OPERAND_mac_qr1_w }, 'o' }, 19838 { { OPERAND_pr }, 'i' }, 19839 { { OPERAND_pr0 }, 'i' } 19840 }; 19841 19842 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = { 19843 { { STATE_CPENABLE }, 'i' } 19844 }; 19845 19846 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = { 19847 { { OPERAND_mac_qr1_w }, 'o' }, 19848 { { OPERAND_pr }, 'i' }, 19849 { { OPERAND_pr0 }, 'i' } 19850 }; 19851 19852 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = { 19853 { { STATE_CPENABLE }, 'i' } 19854 }; 19855 19856 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = { 19857 { { OPERAND_mac_qr1_w }, 'o' }, 19858 { { OPERAND_pr }, 'i' }, 19859 { { OPERAND_pr0 }, 'i' } 19860 }; 19861 19862 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = { 19863 { { STATE_CPENABLE }, 'i' } 19864 }; 19865 19866 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = { 19867 { { OPERAND_mac_qr1_w }, 'o' }, 19868 { { OPERAND_pr }, 'i' }, 19869 { { OPERAND_pr0 }, 'i' } 19870 }; 19871 19872 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = { 19873 { { STATE_CPENABLE }, 'i' } 19874 }; 19875 19876 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = { 19877 { { OPERAND_mac_qr1_w }, 'o' }, 19878 { { OPERAND_pr }, 'i' }, 19879 { { OPERAND_pr0 }, 'i' } 19880 }; 19881 19882 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = { 19883 { { STATE_CPENABLE }, 'i' } 19884 }; 19885 19886 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = { 19887 { { OPERAND_mac_qr1_w }, 'o' }, 19888 { { OPERAND_pr }, 'i' }, 19889 { { OPERAND_pr0 }, 'i' } 19890 }; 19891 19892 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = { 19893 { { STATE_CPENABLE }, 'i' } 19894 }; 19895 19896 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = { 19897 { { OPERAND_mac_qr1_w }, 'o' }, 19898 { { OPERAND_pr }, 'i' }, 19899 { { OPERAND_pr0 }, 'i' } 19900 }; 19901 19902 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = { 19903 { { STATE_CPENABLE }, 'i' } 19904 }; 19905 19906 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = { 19907 { { OPERAND_mac_qr1_w }, 'o' }, 19908 { { OPERAND_pr }, 'i' }, 19909 { { OPERAND_pr0 }, 'i' } 19910 }; 19911 19912 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = { 19913 { { STATE_CPENABLE }, 'i' } 19914 }; 19915 19916 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = { 19917 { { OPERAND_mac_qr1_w }, 'm' }, 19918 { { OPERAND_pr }, 'i' }, 19919 { { OPERAND_pr0 }, 'i' } 19920 }; 19921 19922 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = { 19923 { { STATE_CPENABLE }, 'i' } 19924 }; 19925 19926 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = { 19927 { { OPERAND_mac_qr1_w }, 'm' }, 19928 { { OPERAND_pr }, 'i' }, 19929 { { OPERAND_pr0 }, 'i' } 19930 }; 19931 19932 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = { 19933 { { STATE_CPENABLE }, 'i' } 19934 }; 19935 19936 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = { 19937 { { OPERAND_mac_qr1_w }, 'm' }, 19938 { { OPERAND_pr }, 'i' }, 19939 { { OPERAND_pr0 }, 'i' } 19940 }; 19941 19942 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = { 19943 { { STATE_CPENABLE }, 'i' } 19944 }; 19945 19946 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = { 19947 { { OPERAND_mac_qr1_w }, 'm' }, 19948 { { OPERAND_pr }, 'i' }, 19949 { { OPERAND_pr0 }, 'i' } 19950 }; 19951 19952 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = { 19953 { { STATE_CPENABLE }, 'i' } 19954 }; 19955 19956 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = { 19957 { { OPERAND_mac_qr1_w }, 'm' }, 19958 { { OPERAND_pr }, 'i' }, 19959 { { OPERAND_pr0 }, 'i' } 19960 }; 19961 19962 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = { 19963 { { STATE_CPENABLE }, 'i' } 19964 }; 19965 19966 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = { 19967 { { OPERAND_mac_qr1_w }, 'm' }, 19968 { { OPERAND_pr }, 'i' }, 19969 { { OPERAND_pr0 }, 'i' } 19970 }; 19971 19972 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = { 19973 { { STATE_CPENABLE }, 'i' } 19974 }; 19975 19976 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = { 19977 { { OPERAND_mac_qr1_w }, 'm' }, 19978 { { OPERAND_pr }, 'i' }, 19979 { { OPERAND_pr0 }, 'i' } 19980 }; 19981 19982 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = { 19983 { { STATE_CPENABLE }, 'i' } 19984 }; 19985 19986 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = { 19987 { { OPERAND_mac_qr1_w }, 'm' }, 19988 { { OPERAND_pr }, 'i' }, 19989 { { OPERAND_pr0 }, 'i' } 19990 }; 19991 19992 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = { 19993 { { STATE_CPENABLE }, 'i' } 19994 }; 19995 19996 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = { 19997 { { OPERAND_mac_qr1_w }, 'm' }, 19998 { { OPERAND_pr }, 'i' }, 19999 { { OPERAND_pr0 }, 'i' } 20000 }; 20001 20002 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = { 20003 { { STATE_CPENABLE }, 'i' } 20004 }; 20005 20006 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = { 20007 { { OPERAND_mac_qr1_w }, 'm' }, 20008 { { OPERAND_pr }, 'i' }, 20009 { { OPERAND_pr0 }, 'i' } 20010 }; 20011 20012 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = { 20013 { { STATE_CPENABLE }, 'i' } 20014 }; 20015 20016 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = { 20017 { { OPERAND_mac_qr1_w }, 'm' }, 20018 { { OPERAND_pr }, 'i' }, 20019 { { OPERAND_pr0 }, 'i' } 20020 }; 20021 20022 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = { 20023 { { STATE_CPENABLE }, 'i' } 20024 }; 20025 20026 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = { 20027 { { OPERAND_mac_qr1_w }, 'm' }, 20028 { { OPERAND_pr }, 'i' }, 20029 { { OPERAND_pr0 }, 'i' } 20030 }; 20031 20032 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = { 20033 { { STATE_CPENABLE }, 'i' } 20034 }; 20035 20036 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = { 20037 { { OPERAND_mac_qr1_w }, 'm' }, 20038 { { OPERAND_pr }, 'i' }, 20039 { { OPERAND_pr0 }, 'i' } 20040 }; 20041 20042 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = { 20043 { { STATE_CPENABLE }, 'i' } 20044 }; 20045 20046 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = { 20047 { { OPERAND_mac_qr1_w }, 'm' }, 20048 { { OPERAND_pr }, 'i' }, 20049 { { OPERAND_pr0 }, 'i' } 20050 }; 20051 20052 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = { 20053 { { STATE_CPENABLE }, 'i' } 20054 }; 20055 20056 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = { 20057 { { OPERAND_mac_qr1_w }, 'm' }, 20058 { { OPERAND_pr }, 'i' }, 20059 { { OPERAND_pr0 }, 'i' } 20060 }; 20061 20062 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = { 20063 { { STATE_CPENABLE }, 'i' } 20064 }; 20065 20066 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = { 20067 { { OPERAND_mac_qr1_w }, 'm' }, 20068 { { OPERAND_pr }, 'i' }, 20069 { { OPERAND_pr0 }, 'i' } 20070 }; 20071 20072 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs[] = { 20073 { { STATE_CPENABLE }, 'i' } 20074 }; 20075 20076 static xtensa_arg_internal Iclass_ae_iclass_sha32_args[] = { 20077 { { OPERAND_arr }, 'o' }, 20078 { { OPERAND_ars }, 'i' } 20079 }; 20080 20081 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_args[] = { 20082 { { OPERAND_br }, 'o' }, 20083 { { OPERAND_art }, 'o' }, 20084 { { OPERAND_ars }, 'i' } 20085 }; 20086 20087 static xtensa_arg_internal Iclass_ae_iclass_vldl32t_stateArgs[] = { 20088 { { STATE_AE_TABLESIZE }, 'm' }, 20089 { { STATE_AE_BITSUSED }, 'o' }, 20090 { { STATE_AE_NEXTOFFSET }, 'm' }, 20091 { { STATE_AE_SEARCHDONE }, 'o' }, 20092 { { STATE_CPENABLE }, 'i' } 20093 }; 20094 20095 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_args[] = { 20096 { { OPERAND_br }, 'o' }, 20097 { { OPERAND_art }, 'o' }, 20098 { { OPERAND_ars }, 'i' } 20099 }; 20100 20101 static xtensa_arg_internal Iclass_ae_iclass_vldl16t_stateArgs[] = { 20102 { { STATE_AE_TABLESIZE }, 'm' }, 20103 { { STATE_AE_BITSUSED }, 'o' }, 20104 { { STATE_AE_NEXTOFFSET }, 'm' }, 20105 { { STATE_AE_SEARCHDONE }, 'o' }, 20106 { { STATE_CPENABLE }, 'i' } 20107 }; 20108 20109 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_args[] = { 20110 { { OPERAND_ars }, 'm' } 20111 }; 20112 20113 static xtensa_arg_internal Iclass_ae_iclass_vldl16c_stateArgs[] = { 20114 { { STATE_AE_NEXTOFFSET }, 'm' }, 20115 { { STATE_AE_TABLESIZE }, 'm' }, 20116 { { STATE_AE_BITPTR }, 'm' }, 20117 { { STATE_AE_BITHEAD }, 'm' }, 20118 { { STATE_AE_FIRST_TS }, 'i' }, 20119 { { STATE_AE_BITSUSED }, 'i' }, 20120 { { STATE_AE_SEARCHDONE }, 'i' }, 20121 { { STATE_CPENABLE }, 'i' } 20122 }; 20123 20124 static xtensa_arg_internal Iclass_ae_iclass_vldsht_args[] = { 20125 { { OPERAND_art }, 'i' } 20126 }; 20127 20128 static xtensa_arg_internal Iclass_ae_iclass_vldsht_stateArgs[] = { 20129 { { STATE_AE_BITPTR }, 'i' }, 20130 { { STATE_AE_BITHEAD }, 'i' }, 20131 { { STATE_AE_FIRST_TS }, 'o' }, 20132 { { STATE_AE_NEXTOFFSET }, 'o' }, 20133 { { STATE_AE_TABLESIZE }, 'o' }, 20134 { { STATE_CPENABLE }, 'i' } 20135 }; 20136 20137 static xtensa_arg_internal Iclass_ae_iclass_lb_args[] = { 20138 { { OPERAND_arr }, 'o' }, 20139 { { OPERAND_art }, 'i' } 20140 }; 20141 20142 static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = { 20143 { { STATE_AE_BITPTR }, 'i' }, 20144 { { STATE_AE_BITHEAD }, 'i' }, 20145 { { STATE_CPENABLE }, 'i' } 20146 }; 20147 20148 static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = { 20149 { { OPERAND_arr }, 'o' }, 20150 { { OPERAND_ae_ohba2 }, 'i' } 20151 }; 20152 20153 static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = { 20154 { { STATE_AE_BITPTR }, 'i' }, 20155 { { STATE_AE_BITHEAD }, 'i' }, 20156 { { STATE_CPENABLE }, 'i' } 20157 }; 20158 20159 static xtensa_arg_internal Iclass_ae_iclass_lbk_args[] = { 20160 { { OPERAND_arr }, 'o' }, 20161 { { OPERAND_ars }, 'i' }, 20162 { { OPERAND_art }, 'i' } 20163 }; 20164 20165 static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = { 20166 { { STATE_AE_BITPTR }, 'i' }, 20167 { { STATE_AE_BITHEAD }, 'i' }, 20168 { { STATE_CPENABLE }, 'i' } 20169 }; 20170 20171 static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = { 20172 { { OPERAND_arr }, 'o' }, 20173 { { OPERAND_ars }, 'i' }, 20174 { { OPERAND_ae_ohba2 }, 'i' } 20175 }; 20176 20177 static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = { 20178 { { STATE_AE_BITPTR }, 'i' }, 20179 { { STATE_AE_BITHEAD }, 'i' }, 20180 { { STATE_CPENABLE }, 'i' } 20181 }; 20182 20183 static xtensa_arg_internal Iclass_ae_iclass_db_args[] = { 20184 { { OPERAND_ars }, 'm' }, 20185 { { OPERAND_art }, 'i' } 20186 }; 20187 20188 static xtensa_arg_internal Iclass_ae_iclass_db_stateArgs[] = { 20189 { { STATE_AE_BITPTR }, 'm' }, 20190 { { STATE_AE_BITHEAD }, 'm' }, 20191 { { STATE_CPENABLE }, 'i' } 20192 }; 20193 20194 static xtensa_arg_internal Iclass_ae_iclass_dbi_args[] = { 20195 { { OPERAND_ars }, 'm' }, 20196 { { OPERAND_ae_ohba }, 'i' } 20197 }; 20198 20199 static xtensa_arg_internal Iclass_ae_iclass_dbi_stateArgs[] = { 20200 { { STATE_AE_BITPTR }, 'm' }, 20201 { { STATE_AE_BITHEAD }, 'm' }, 20202 { { STATE_CPENABLE }, 'i' } 20203 }; 20204 20205 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_args[] = { 20206 { { OPERAND_br }, 'o' }, 20207 { { OPERAND_art }, 'm' }, 20208 { { OPERAND_ars }, 'i' } 20209 }; 20210 20211 static xtensa_arg_internal Iclass_ae_iclass_vlel32t_stateArgs[] = { 20212 { { STATE_AE_BITSUSED }, 'o' }, 20213 { { STATE_AE_NEXTOFFSET }, 'o' }, 20214 { { STATE_CPENABLE }, 'i' } 20215 }; 20216 20217 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_args[] = { 20218 { { OPERAND_br }, 'o' }, 20219 { { OPERAND_art }, 'm' }, 20220 { { OPERAND_ars }, 'i' } 20221 }; 20222 20223 static xtensa_arg_internal Iclass_ae_iclass_vlel16t_stateArgs[] = { 20224 { { STATE_AE_BITSUSED }, 'o' }, 20225 { { STATE_AE_NEXTOFFSET }, 'o' }, 20226 { { STATE_CPENABLE }, 'i' } 20227 }; 20228 20229 static xtensa_arg_internal Iclass_ae_iclass_sb_args[] = { 20230 { { OPERAND_ars }, 'm' }, 20231 { { OPERAND_art }, 'i' } 20232 }; 20233 20234 static xtensa_arg_internal Iclass_ae_iclass_sb_stateArgs[] = { 20235 { { STATE_AE_BITSUSED }, 'i' }, 20236 { { STATE_AE_BITPTR }, 'm' }, 20237 { { STATE_AE_BITHEAD }, 'm' }, 20238 { { STATE_CPENABLE }, 'i' } 20239 }; 20240 20241 static xtensa_arg_internal Iclass_ae_iclass_sbi_args[] = { 20242 { { OPERAND_ars }, 'm' }, 20243 { { OPERAND_art }, 'i' }, 20244 { { OPERAND_ae_ohba }, 'i' } 20245 }; 20246 20247 static xtensa_arg_internal Iclass_ae_iclass_sbi_stateArgs[] = { 20248 { { STATE_AE_BITPTR }, 'm' }, 20249 { { STATE_AE_BITHEAD }, 'm' }, 20250 { { STATE_CPENABLE }, 'i' } 20251 }; 20252 20253 static xtensa_arg_internal Iclass_ae_iclass_vles16c_args[] = { 20254 { { OPERAND_ars }, 'm' } 20255 }; 20256 20257 static xtensa_arg_internal Iclass_ae_iclass_vles16c_stateArgs[] = { 20258 { { STATE_AE_BITPTR }, 'm' }, 20259 { { STATE_AE_BITHEAD }, 'm' }, 20260 { { STATE_AE_BITSUSED }, 'i' }, 20261 { { STATE_AE_NEXTOFFSET }, 'i' }, 20262 { { STATE_CPENABLE }, 'i' } 20263 }; 20264 20265 static xtensa_arg_internal Iclass_ae_iclass_sbf_args[] = { 20266 { { OPERAND_ars }, 'm' } 20267 }; 20268 20269 static xtensa_arg_internal Iclass_ae_iclass_sbf_stateArgs[] = { 20270 { { STATE_AE_BITPTR }, 'i' }, 20271 { { STATE_AE_BITHEAD }, 'm' }, 20272 { { STATE_CPENABLE }, 'i' } 20273 }; 20274 20275 static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_args[] = { 20276 { { OPERAND_qr1_w }, 'o' }, 20277 { { OPERAND_qr0_rw }, 'i' }, 20278 { { OPERAND_ars }, 'i' } 20279 }; 20280 20281 static xtensa_arg_internal Iclass_icls_AE_SLAASQ56S_stateArgs[] = { 20282 { { STATE_AE_OVERFLOW }, 'm' }, 20283 { { STATE_CPENABLE }, 'i' } 20284 }; 20285 20286 static xtensa_arg_internal Iclass_icls_AE_ADDBRBA32_args[] = { 20287 { { OPERAND_arr }, 'o' }, 20288 { { OPERAND_ars }, 'i' }, 20289 { { OPERAND_art }, 'i' } 20290 }; 20291 20292 static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_args[] = { 20293 { { OPERAND_ps }, 'o' }, 20294 { { OPERAND_pr }, 'i' }, 20295 { { OPERAND_pr0 }, 'i' } 20296 }; 20297 20298 static xtensa_arg_internal Iclass_icls_AE_MINABSSP24S_stateArgs[] = { 20299 { { STATE_AE_OVERFLOW }, 'm' }, 20300 { { STATE_CPENABLE }, 'i' } 20301 }; 20302 20303 static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_args[] = { 20304 { { OPERAND_ps }, 'o' }, 20305 { { OPERAND_pr }, 'i' }, 20306 { { OPERAND_pr0 }, 'i' } 20307 }; 20308 20309 static xtensa_arg_internal Iclass_icls_AE_MAXABSSP24S_stateArgs[] = { 20310 { { STATE_AE_OVERFLOW }, 'm' }, 20311 { { STATE_CPENABLE }, 'i' } 20312 }; 20313 20314 static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_args[] = { 20315 { { OPERAND_qr1_w }, 'o' }, 20316 { { OPERAND_qr0 }, 'i' }, 20317 { { OPERAND_qr0_rw }, 'i' } 20318 }; 20319 20320 static xtensa_arg_internal Iclass_icls_AE_MINABSSQ56S_stateArgs[] = { 20321 { { STATE_AE_OVERFLOW }, 'm' }, 20322 { { STATE_CPENABLE }, 'i' } 20323 }; 20324 20325 static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_args[] = { 20326 { { OPERAND_qr1_w }, 'o' }, 20327 { { OPERAND_qr0 }, 'i' }, 20328 { { OPERAND_qr0_rw }, 'i' } 20329 }; 20330 20331 static xtensa_arg_internal Iclass_icls_AE_MAXABSSQ56S_stateArgs[] = { 20332 { { STATE_AE_OVERFLOW }, 'm' }, 20333 { { STATE_CPENABLE }, 'i' } 20334 }; 20335 20336 static xtensa_arg_internal Iclass_rur_ae_cbegin0_args[] = { 20337 { { OPERAND_arr }, 'o' } 20338 }; 20339 20340 static xtensa_arg_internal Iclass_rur_ae_cbegin0_stateArgs[] = { 20341 { { STATE_AE_CBEGIN0 }, 'i' }, 20342 { { STATE_CPENABLE }, 'i' } 20343 }; 20344 20345 static xtensa_arg_internal Iclass_wur_ae_cbegin0_args[] = { 20346 { { OPERAND_art }, 'i' } 20347 }; 20348 20349 static xtensa_arg_internal Iclass_wur_ae_cbegin0_stateArgs[] = { 20350 { { STATE_AE_CBEGIN0 }, 'o' }, 20351 { { STATE_CPENABLE }, 'i' } 20352 }; 20353 20354 static xtensa_arg_internal Iclass_rur_ae_cend0_args[] = { 20355 { { OPERAND_arr }, 'o' } 20356 }; 20357 20358 static xtensa_arg_internal Iclass_rur_ae_cend0_stateArgs[] = { 20359 { { STATE_AE_CEND0 }, 'i' }, 20360 { { STATE_CPENABLE }, 'i' } 20361 }; 20362 20363 static xtensa_arg_internal Iclass_wur_ae_cend0_args[] = { 20364 { { OPERAND_art }, 'i' } 20365 }; 20366 20367 static xtensa_arg_internal Iclass_wur_ae_cend0_stateArgs[] = { 20368 { { STATE_AE_CEND0 }, 'o' }, 20369 { { STATE_CPENABLE }, 'i' } 20370 }; 20371 20372 static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_args[] = { 20373 { { OPERAND_pr }, 'o' }, 20374 { { OPERAND_ars }, 'm' }, 20375 { { OPERAND_art }, 'i' } 20376 }; 20377 20378 static xtensa_arg_internal Iclass_icls_AE_LP24X2_C_stateArgs[] = { 20379 { { STATE_AE_CBEGIN0 }, 'i' }, 20380 { { STATE_AE_CEND0 }, 'i' }, 20381 { { STATE_CPENABLE }, 'i' } 20382 }; 20383 20384 static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_args[] = { 20385 { { OPERAND_pr }, 'i' }, 20386 { { OPERAND_ars }, 'm' }, 20387 { { OPERAND_art }, 'i' } 20388 }; 20389 20390 static xtensa_arg_internal Iclass_icls_AE_SP24X2S_C_stateArgs[] = { 20391 { { STATE_AE_CBEGIN0 }, 'i' }, 20392 { { STATE_AE_CEND0 }, 'i' }, 20393 { { STATE_CPENABLE }, 'i' } 20394 }; 20395 20396 static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_args[] = { 20397 { { OPERAND_pr }, 'o' }, 20398 { { OPERAND_ars }, 'm' }, 20399 { { OPERAND_art }, 'i' } 20400 }; 20401 20402 static xtensa_arg_internal Iclass_icls_AE_LP24X2F_C_stateArgs[] = { 20403 { { STATE_AE_CBEGIN0 }, 'i' }, 20404 { { STATE_AE_CEND0 }, 'i' }, 20405 { { STATE_CPENABLE }, 'i' } 20406 }; 20407 20408 static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_args[] = { 20409 { { OPERAND_pr }, 'i' }, 20410 { { OPERAND_ars }, 'm' }, 20411 { { OPERAND_art }, 'i' } 20412 }; 20413 20414 static xtensa_arg_internal Iclass_icls_AE_SP24X2F_C_stateArgs[] = { 20415 { { STATE_AE_CBEGIN0 }, 'i' }, 20416 { { STATE_AE_CEND0 }, 'i' }, 20417 { { STATE_CPENABLE }, 'i' } 20418 }; 20419 20420 static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_args[] = { 20421 { { OPERAND_pr }, 'o' }, 20422 { { OPERAND_ars }, 'm' }, 20423 { { OPERAND_art }, 'i' } 20424 }; 20425 20426 static xtensa_arg_internal Iclass_icls_AE_LP16X2F_C_stateArgs[] = { 20427 { { STATE_AE_CBEGIN0 }, 'i' }, 20428 { { STATE_AE_CEND0 }, 'i' }, 20429 { { STATE_CPENABLE }, 'i' } 20430 }; 20431 20432 static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_args[] = { 20433 { { OPERAND_pr }, 'i' }, 20434 { { OPERAND_ars }, 'm' }, 20435 { { OPERAND_art }, 'i' } 20436 }; 20437 20438 static xtensa_arg_internal Iclass_icls_AE_SP16X2F_C_stateArgs[] = { 20439 { { STATE_AE_CBEGIN0 }, 'i' }, 20440 { { STATE_AE_CEND0 }, 'i' }, 20441 { { STATE_CPENABLE }, 'i' } 20442 }; 20443 20444 static xtensa_arg_internal Iclass_icls_AE_LP24_C_args[] = { 20445 { { OPERAND_pr }, 'o' }, 20446 { { OPERAND_ars }, 'm' }, 20447 { { OPERAND_art }, 'i' } 20448 }; 20449 20450 static xtensa_arg_internal Iclass_icls_AE_LP24_C_stateArgs[] = { 20451 { { STATE_AE_CBEGIN0 }, 'i' }, 20452 { { STATE_AE_CEND0 }, 'i' }, 20453 { { STATE_CPENABLE }, 'i' } 20454 }; 20455 20456 static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_args[] = { 20457 { { OPERAND_pr }, 'i' }, 20458 { { OPERAND_ars }, 'm' }, 20459 { { OPERAND_art }, 'i' } 20460 }; 20461 20462 static xtensa_arg_internal Iclass_icls_AE_SP24S_L_C_stateArgs[] = { 20463 { { STATE_AE_CBEGIN0 }, 'i' }, 20464 { { STATE_AE_CEND0 }, 'i' }, 20465 { { STATE_CPENABLE }, 'i' } 20466 }; 20467 20468 static xtensa_arg_internal Iclass_icls_AE_LP24F_C_args[] = { 20469 { { OPERAND_pr }, 'o' }, 20470 { { OPERAND_ars }, 'm' }, 20471 { { OPERAND_art }, 'i' } 20472 }; 20473 20474 static xtensa_arg_internal Iclass_icls_AE_LP24F_C_stateArgs[] = { 20475 { { STATE_AE_CBEGIN0 }, 'i' }, 20476 { { STATE_AE_CEND0 }, 'i' }, 20477 { { STATE_CPENABLE }, 'i' } 20478 }; 20479 20480 static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_args[] = { 20481 { { OPERAND_pr }, 'i' }, 20482 { { OPERAND_ars }, 'm' }, 20483 { { OPERAND_art }, 'i' } 20484 }; 20485 20486 static xtensa_arg_internal Iclass_icls_AE_SP24F_L_C_stateArgs[] = { 20487 { { STATE_AE_CBEGIN0 }, 'i' }, 20488 { { STATE_AE_CEND0 }, 'i' }, 20489 { { STATE_CPENABLE }, 'i' } 20490 }; 20491 20492 static xtensa_arg_internal Iclass_icls_AE_LP16F_C_args[] = { 20493 { { OPERAND_pr }, 'o' }, 20494 { { OPERAND_ars }, 'm' }, 20495 { { OPERAND_art }, 'i' } 20496 }; 20497 20498 static xtensa_arg_internal Iclass_icls_AE_LP16F_C_stateArgs[] = { 20499 { { STATE_AE_CBEGIN0 }, 'i' }, 20500 { { STATE_AE_CEND0 }, 'i' }, 20501 { { STATE_CPENABLE }, 'i' } 20502 }; 20503 20504 static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_args[] = { 20505 { { OPERAND_pr }, 'i' }, 20506 { { OPERAND_ars }, 'm' }, 20507 { { OPERAND_art }, 'i' } 20508 }; 20509 20510 static xtensa_arg_internal Iclass_icls_AE_SP16F_L_C_stateArgs[] = { 20511 { { STATE_AE_CBEGIN0 }, 'i' }, 20512 { { STATE_AE_CEND0 }, 'i' }, 20513 { { STATE_CPENABLE }, 'i' } 20514 }; 20515 20516 static xtensa_arg_internal Iclass_icls_AE_LQ56_C_args[] = { 20517 { { OPERAND_qr1_w }, 'o' }, 20518 { { OPERAND_ars }, 'm' }, 20519 { { OPERAND_art }, 'i' } 20520 }; 20521 20522 static xtensa_arg_internal Iclass_icls_AE_LQ56_C_stateArgs[] = { 20523 { { STATE_AE_CBEGIN0 }, 'i' }, 20524 { { STATE_AE_CEND0 }, 'i' }, 20525 { { STATE_CPENABLE }, 'i' } 20526 }; 20527 20528 static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_args[] = { 20529 { { OPERAND_qr0_rw }, 'i' }, 20530 { { OPERAND_ars }, 'm' }, 20531 { { OPERAND_art }, 'i' } 20532 }; 20533 20534 static xtensa_arg_internal Iclass_icls_AE_SQ56S_C_stateArgs[] = { 20535 { { STATE_AE_CBEGIN0 }, 'i' }, 20536 { { STATE_AE_CEND0 }, 'i' }, 20537 { { STATE_CPENABLE }, 'i' } 20538 }; 20539 20540 static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_args[] = { 20541 { { OPERAND_qr1_w }, 'o' }, 20542 { { OPERAND_ars }, 'm' }, 20543 { { OPERAND_art }, 'i' } 20544 }; 20545 20546 static xtensa_arg_internal Iclass_icls_AE_LQ32F_C_stateArgs[] = { 20547 { { STATE_AE_CBEGIN0 }, 'i' }, 20548 { { STATE_AE_CEND0 }, 'i' }, 20549 { { STATE_CPENABLE }, 'i' } 20550 }; 20551 20552 static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_args[] = { 20553 { { OPERAND_qr0_rw }, 'i' }, 20554 { { OPERAND_ars }, 'm' }, 20555 { { OPERAND_art }, 'i' } 20556 }; 20557 20558 static xtensa_arg_internal Iclass_icls_AE_SQ32F_C_stateArgs[] = { 20559 { { STATE_AE_CBEGIN0 }, 'i' }, 20560 { { STATE_AE_CEND0 }, 'i' }, 20561 { { STATE_CPENABLE }, 'i' } 20562 }; 20563 20564 static xtensa_arg_internal Iclass_rur_expstate_args[] = { 20565 { { OPERAND_arr }, 'o' } 20566 }; 20567 20568 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = { 20569 { { STATE_EXPSTATE }, 'i' }, 20570 { { STATE_CPENABLE }, 'i' } 20571 }; 20572 20573 static xtensa_arg_internal Iclass_wur_expstate_args[] = { 20574 { { OPERAND_art }, 'i' } 20575 }; 20576 20577 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = { 20578 { { STATE_EXPSTATE }, 'o' }, 20579 { { STATE_CPENABLE }, 'i' } 20580 }; 20581 20582 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = { 20583 { { OPERAND_art }, 'o' } 20584 }; 20585 20586 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = { 20587 { { STATE_CPENABLE }, 'i' } 20588 }; 20589 20590 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = { 20591 INTERFACE_IMPWIRE 20592 }; 20593 20594 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = { 20595 { { OPERAND_bitindex }, 'i' } 20596 }; 20597 20598 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = { 20599 { { STATE_EXPSTATE }, 'm' }, 20600 { { STATE_CPENABLE }, 'i' } 20601 }; 20602 20603 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = { 20604 { { OPERAND_bitindex }, 'i' } 20605 }; 20606 20607 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = { 20608 { { STATE_EXPSTATE }, 'm' }, 20609 { { STATE_CPENABLE }, 'i' } 20610 }; 20611 20612 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = { 20613 { { OPERAND_art }, 'i' }, 20614 { { OPERAND_ars }, 'i' } 20615 }; 20616 20617 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = { 20618 { { STATE_EXPSTATE }, 'm' }, 20619 { { STATE_CPENABLE }, 'i' } 20620 }; 20621 20622 static xtensa_iclass_internal iclasses[] = { 20623 { 0, 0 /* xt_iclass_excw */, 20624 0, 0, 0, 0 }, 20625 { 0, 0 /* xt_iclass_rfe */, 20626 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 }, 20627 { 0, 0 /* xt_iclass_rfde */, 20628 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 }, 20629 { 0, 0 /* xt_iclass_syscall */, 20630 0, 0, 0, 0 }, 20631 { 2, Iclass_xt_iclass_call12_args, 20632 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 }, 20633 { 2, Iclass_xt_iclass_call8_args, 20634 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 }, 20635 { 2, Iclass_xt_iclass_call4_args, 20636 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 }, 20637 { 2, Iclass_xt_iclass_callx12_args, 20638 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 }, 20639 { 2, Iclass_xt_iclass_callx8_args, 20640 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 }, 20641 { 2, Iclass_xt_iclass_callx4_args, 20642 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 }, 20643 { 3, Iclass_xt_iclass_entry_args, 20644 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 }, 20645 { 2, Iclass_xt_iclass_movsp_args, 20646 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 }, 20647 { 1, Iclass_xt_iclass_rotw_args, 20648 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 }, 20649 { 1, Iclass_xt_iclass_retw_args, 20650 5, Iclass_xt_iclass_retw_stateArgs, 0, 0 }, 20651 { 0, 0 /* xt_iclass_rfwou */, 20652 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 }, 20653 { 3, Iclass_xt_iclass_l32e_args, 20654 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 }, 20655 { 3, Iclass_xt_iclass_s32e_args, 20656 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 }, 20657 { 1, Iclass_xt_iclass_rsr_windowbase_args, 20658 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 }, 20659 { 1, Iclass_xt_iclass_wsr_windowbase_args, 20660 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 }, 20661 { 1, Iclass_xt_iclass_xsr_windowbase_args, 20662 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 }, 20663 { 1, Iclass_xt_iclass_rsr_windowstart_args, 20664 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 }, 20665 { 1, Iclass_xt_iclass_wsr_windowstart_args, 20666 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 }, 20667 { 1, Iclass_xt_iclass_xsr_windowstart_args, 20668 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 }, 20669 { 3, Iclass_xt_iclass_add_n_args, 20670 0, 0, 0, 0 }, 20671 { 3, Iclass_xt_iclass_addi_n_args, 20672 0, 0, 0, 0 }, 20673 { 2, Iclass_xt_iclass_bz6_args, 20674 0, 0, 0, 0 }, 20675 { 0, 0 /* xt_iclass_ill_n */, 20676 0, 0, 0, 0 }, 20677 { 3, Iclass_xt_iclass_loadi4_args, 20678 0, 0, 0, 0 }, 20679 { 2, Iclass_xt_iclass_mov_n_args, 20680 0, 0, 0, 0 }, 20681 { 2, Iclass_xt_iclass_movi_n_args, 20682 0, 0, 0, 0 }, 20683 { 0, 0 /* xt_iclass_nopn */, 20684 0, 0, 0, 0 }, 20685 { 1, Iclass_xt_iclass_retn_args, 20686 0, 0, 0, 0 }, 20687 { 3, Iclass_xt_iclass_storei4_args, 20688 0, 0, 0, 0 }, 20689 { 1, Iclass_rur_threadptr_args, 20690 1, Iclass_rur_threadptr_stateArgs, 0, 0 }, 20691 { 1, Iclass_wur_threadptr_args, 20692 1, Iclass_wur_threadptr_stateArgs, 0, 0 }, 20693 { 3, Iclass_xt_iclass_addi_args, 20694 0, 0, 0, 0 }, 20695 { 3, Iclass_xt_iclass_addmi_args, 20696 0, 0, 0, 0 }, 20697 { 3, Iclass_xt_iclass_addsub_args, 20698 0, 0, 0, 0 }, 20699 { 3, Iclass_xt_iclass_bit_args, 20700 0, 0, 0, 0 }, 20701 { 3, Iclass_xt_iclass_bsi8_args, 20702 0, 0, 0, 0 }, 20703 { 3, Iclass_xt_iclass_bsi8b_args, 20704 0, 0, 0, 0 }, 20705 { 3, Iclass_xt_iclass_bsi8u_args, 20706 0, 0, 0, 0 }, 20707 { 3, Iclass_xt_iclass_bst8_args, 20708 0, 0, 0, 0 }, 20709 { 2, Iclass_xt_iclass_bsz12_args, 20710 0, 0, 0, 0 }, 20711 { 2, Iclass_xt_iclass_call0_args, 20712 0, 0, 0, 0 }, 20713 { 2, Iclass_xt_iclass_callx0_args, 20714 0, 0, 0, 0 }, 20715 { 4, Iclass_xt_iclass_exti_args, 20716 0, 0, 0, 0 }, 20717 { 0, 0 /* xt_iclass_ill */, 20718 0, 0, 0, 0 }, 20719 { 1, Iclass_xt_iclass_jump_args, 20720 0, 0, 0, 0 }, 20721 { 1, Iclass_xt_iclass_jumpx_args, 20722 0, 0, 0, 0 }, 20723 { 3, Iclass_xt_iclass_l16ui_args, 20724 0, 0, 0, 0 }, 20725 { 3, Iclass_xt_iclass_l16si_args, 20726 0, 0, 0, 0 }, 20727 { 3, Iclass_xt_iclass_l32i_args, 20728 0, 0, 0, 0 }, 20729 { 2, Iclass_xt_iclass_l32r_args, 20730 0, 0, 0, 0 }, 20731 { 3, Iclass_xt_iclass_l8i_args, 20732 0, 0, 0, 0 }, 20733 { 2, Iclass_xt_iclass_loop_args, 20734 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 }, 20735 { 2, Iclass_xt_iclass_loopz_args, 20736 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 }, 20737 { 2, Iclass_xt_iclass_movi_args, 20738 0, 0, 0, 0 }, 20739 { 3, Iclass_xt_iclass_movz_args, 20740 0, 0, 0, 0 }, 20741 { 2, Iclass_xt_iclass_neg_args, 20742 0, 0, 0, 0 }, 20743 { 0, 0 /* xt_iclass_nop */, 20744 0, 0, 0, 0 }, 20745 { 1, Iclass_xt_iclass_return_args, 20746 0, 0, 0, 0 }, 20747 { 0, 0 /* xt_iclass_simcall */, 20748 0, 0, 0, 0 }, 20749 { 3, Iclass_xt_iclass_s16i_args, 20750 0, 0, 0, 0 }, 20751 { 3, Iclass_xt_iclass_s32i_args, 20752 0, 0, 0, 0 }, 20753 { 3, Iclass_xt_iclass_s32nb_args, 20754 0, 0, 0, 0 }, 20755 { 3, Iclass_xt_iclass_s8i_args, 20756 0, 0, 0, 0 }, 20757 { 1, Iclass_xt_iclass_sar_args, 20758 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 }, 20759 { 1, Iclass_xt_iclass_sari_args, 20760 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 }, 20761 { 2, Iclass_xt_iclass_shifts_args, 20762 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 }, 20763 { 3, Iclass_xt_iclass_shiftst_args, 20764 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 }, 20765 { 2, Iclass_xt_iclass_shiftt_args, 20766 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 }, 20767 { 3, Iclass_xt_iclass_slli_args, 20768 0, 0, 0, 0 }, 20769 { 3, Iclass_xt_iclass_srai_args, 20770 0, 0, 0, 0 }, 20771 { 3, Iclass_xt_iclass_srli_args, 20772 0, 0, 0, 0 }, 20773 { 0, 0 /* xt_iclass_memw */, 20774 0, 0, 0, 0 }, 20775 { 0, 0 /* xt_iclass_extw */, 20776 0, 0, 0, 0 }, 20777 { 0, 0 /* xt_iclass_isync */, 20778 0, 0, 0, 0 }, 20779 { 0, 0 /* xt_iclass_sync */, 20780 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 }, 20781 { 2, Iclass_xt_iclass_rsil_args, 20782 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 }, 20783 { 1, Iclass_xt_iclass_rsr_lend_args, 20784 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 }, 20785 { 1, Iclass_xt_iclass_wsr_lend_args, 20786 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 }, 20787 { 1, Iclass_xt_iclass_xsr_lend_args, 20788 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 }, 20789 { 1, Iclass_xt_iclass_rsr_lcount_args, 20790 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 }, 20791 { 1, Iclass_xt_iclass_wsr_lcount_args, 20792 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 }, 20793 { 1, Iclass_xt_iclass_xsr_lcount_args, 20794 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 }, 20795 { 1, Iclass_xt_iclass_rsr_lbeg_args, 20796 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 }, 20797 { 1, Iclass_xt_iclass_wsr_lbeg_args, 20798 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 }, 20799 { 1, Iclass_xt_iclass_xsr_lbeg_args, 20800 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 }, 20801 { 1, Iclass_xt_iclass_rsr_sar_args, 20802 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 }, 20803 { 1, Iclass_xt_iclass_wsr_sar_args, 20804 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 }, 20805 { 1, Iclass_xt_iclass_xsr_sar_args, 20806 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 }, 20807 { 1, Iclass_xt_iclass_rsr_memctl_args, 20808 0, 0, 0, 0 }, 20809 { 1, Iclass_xt_iclass_wsr_memctl_args, 20810 0, 0, 0, 0 }, 20811 { 1, Iclass_xt_iclass_xsr_memctl_args, 20812 0, 0, 0, 0 }, 20813 { 1, Iclass_xt_iclass_rsr_litbase_args, 20814 0, 0, 0, 0 }, 20815 { 1, Iclass_xt_iclass_wsr_litbase_args, 20816 0, 0, 0, 0 }, 20817 { 1, Iclass_xt_iclass_xsr_litbase_args, 20818 0, 0, 0, 0 }, 20819 { 1, Iclass_xt_iclass_rsr_configid0_args, 20820 2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 }, 20821 { 1, Iclass_xt_iclass_wsr_configid0_args, 20822 2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 }, 20823 { 1, Iclass_xt_iclass_rsr_configid1_args, 20824 2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 }, 20825 { 1, Iclass_xt_iclass_rsr_243_args, 20826 2, Iclass_xt_iclass_rsr_243_stateArgs, 0, 0 }, 20827 { 1, Iclass_xt_iclass_rsr_ps_args, 20828 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 }, 20829 { 1, Iclass_xt_iclass_wsr_ps_args, 20830 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 }, 20831 { 1, Iclass_xt_iclass_xsr_ps_args, 20832 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 }, 20833 { 1, Iclass_xt_iclass_rsr_epc1_args, 20834 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 }, 20835 { 1, Iclass_xt_iclass_wsr_epc1_args, 20836 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 }, 20837 { 1, Iclass_xt_iclass_xsr_epc1_args, 20838 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 }, 20839 { 1, Iclass_xt_iclass_rsr_excsave1_args, 20840 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 }, 20841 { 1, Iclass_xt_iclass_wsr_excsave1_args, 20842 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 }, 20843 { 1, Iclass_xt_iclass_xsr_excsave1_args, 20844 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 }, 20845 { 1, Iclass_xt_iclass_rsr_epc2_args, 20846 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 }, 20847 { 1, Iclass_xt_iclass_wsr_epc2_args, 20848 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 }, 20849 { 1, Iclass_xt_iclass_xsr_epc2_args, 20850 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 }, 20851 { 1, Iclass_xt_iclass_rsr_excsave2_args, 20852 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 }, 20853 { 1, Iclass_xt_iclass_wsr_excsave2_args, 20854 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 }, 20855 { 1, Iclass_xt_iclass_xsr_excsave2_args, 20856 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 }, 20857 { 1, Iclass_xt_iclass_rsr_epc3_args, 20858 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 }, 20859 { 1, Iclass_xt_iclass_wsr_epc3_args, 20860 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 }, 20861 { 1, Iclass_xt_iclass_xsr_epc3_args, 20862 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 }, 20863 { 1, Iclass_xt_iclass_rsr_excsave3_args, 20864 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 }, 20865 { 1, Iclass_xt_iclass_wsr_excsave3_args, 20866 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 }, 20867 { 1, Iclass_xt_iclass_xsr_excsave3_args, 20868 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 }, 20869 { 1, Iclass_xt_iclass_rsr_epc4_args, 20870 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 }, 20871 { 1, Iclass_xt_iclass_wsr_epc4_args, 20872 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 }, 20873 { 1, Iclass_xt_iclass_xsr_epc4_args, 20874 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 }, 20875 { 1, Iclass_xt_iclass_rsr_excsave4_args, 20876 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 }, 20877 { 1, Iclass_xt_iclass_wsr_excsave4_args, 20878 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 }, 20879 { 1, Iclass_xt_iclass_xsr_excsave4_args, 20880 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 }, 20881 { 1, Iclass_xt_iclass_rsr_epc5_args, 20882 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 }, 20883 { 1, Iclass_xt_iclass_wsr_epc5_args, 20884 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 }, 20885 { 1, Iclass_xt_iclass_xsr_epc5_args, 20886 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 }, 20887 { 1, Iclass_xt_iclass_rsr_excsave5_args, 20888 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 }, 20889 { 1, Iclass_xt_iclass_wsr_excsave5_args, 20890 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 }, 20891 { 1, Iclass_xt_iclass_xsr_excsave5_args, 20892 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 }, 20893 { 1, Iclass_xt_iclass_rsr_epc6_args, 20894 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 }, 20895 { 1, Iclass_xt_iclass_wsr_epc6_args, 20896 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 }, 20897 { 1, Iclass_xt_iclass_xsr_epc6_args, 20898 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 }, 20899 { 1, Iclass_xt_iclass_rsr_excsave6_args, 20900 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 }, 20901 { 1, Iclass_xt_iclass_wsr_excsave6_args, 20902 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 }, 20903 { 1, Iclass_xt_iclass_xsr_excsave6_args, 20904 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 }, 20905 { 1, Iclass_xt_iclass_rsr_epc7_args, 20906 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 }, 20907 { 1, Iclass_xt_iclass_wsr_epc7_args, 20908 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 }, 20909 { 1, Iclass_xt_iclass_xsr_epc7_args, 20910 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 }, 20911 { 1, Iclass_xt_iclass_rsr_excsave7_args, 20912 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 }, 20913 { 1, Iclass_xt_iclass_wsr_excsave7_args, 20914 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 }, 20915 { 1, Iclass_xt_iclass_xsr_excsave7_args, 20916 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 }, 20917 { 1, Iclass_xt_iclass_rsr_eps2_args, 20918 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 }, 20919 { 1, Iclass_xt_iclass_wsr_eps2_args, 20920 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 }, 20921 { 1, Iclass_xt_iclass_xsr_eps2_args, 20922 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 }, 20923 { 1, Iclass_xt_iclass_rsr_eps3_args, 20924 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 }, 20925 { 1, Iclass_xt_iclass_wsr_eps3_args, 20926 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 }, 20927 { 1, Iclass_xt_iclass_xsr_eps3_args, 20928 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 }, 20929 { 1, Iclass_xt_iclass_rsr_eps4_args, 20930 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 }, 20931 { 1, Iclass_xt_iclass_wsr_eps4_args, 20932 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 }, 20933 { 1, Iclass_xt_iclass_xsr_eps4_args, 20934 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 }, 20935 { 1, Iclass_xt_iclass_rsr_eps5_args, 20936 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 }, 20937 { 1, Iclass_xt_iclass_wsr_eps5_args, 20938 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 }, 20939 { 1, Iclass_xt_iclass_xsr_eps5_args, 20940 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 }, 20941 { 1, Iclass_xt_iclass_rsr_eps6_args, 20942 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 }, 20943 { 1, Iclass_xt_iclass_wsr_eps6_args, 20944 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 }, 20945 { 1, Iclass_xt_iclass_xsr_eps6_args, 20946 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 }, 20947 { 1, Iclass_xt_iclass_rsr_eps7_args, 20948 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 }, 20949 { 1, Iclass_xt_iclass_wsr_eps7_args, 20950 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 }, 20951 { 1, Iclass_xt_iclass_xsr_eps7_args, 20952 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 }, 20953 { 1, Iclass_xt_iclass_rsr_excvaddr_args, 20954 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 }, 20955 { 1, Iclass_xt_iclass_wsr_excvaddr_args, 20956 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 }, 20957 { 1, Iclass_xt_iclass_xsr_excvaddr_args, 20958 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 }, 20959 { 1, Iclass_xt_iclass_rsr_depc_args, 20960 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 }, 20961 { 1, Iclass_xt_iclass_wsr_depc_args, 20962 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 }, 20963 { 1, Iclass_xt_iclass_xsr_depc_args, 20964 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 }, 20965 { 1, Iclass_xt_iclass_rsr_exccause_args, 20966 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 }, 20967 { 1, Iclass_xt_iclass_wsr_exccause_args, 20968 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 }, 20969 { 1, Iclass_xt_iclass_xsr_exccause_args, 20970 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 }, 20971 { 1, Iclass_xt_iclass_rsr_misc0_args, 20972 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 }, 20973 { 1, Iclass_xt_iclass_wsr_misc0_args, 20974 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 }, 20975 { 1, Iclass_xt_iclass_xsr_misc0_args, 20976 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 }, 20977 { 1, Iclass_xt_iclass_rsr_misc1_args, 20978 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 }, 20979 { 1, Iclass_xt_iclass_wsr_misc1_args, 20980 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 }, 20981 { 1, Iclass_xt_iclass_xsr_misc1_args, 20982 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 }, 20983 { 1, Iclass_xt_iclass_rsr_prid_args, 20984 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 }, 20985 { 1, Iclass_xt_iclass_rsr_vecbase_args, 20986 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 }, 20987 { 1, Iclass_xt_iclass_wsr_vecbase_args, 20988 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 }, 20989 { 1, Iclass_xt_iclass_xsr_vecbase_args, 20990 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 }, 20991 { 3, Iclass_xt_mul16_args, 20992 0, 0, 0, 0 }, 20993 { 3, Iclass_xt_mul32_args, 20994 0, 0, 0, 0 }, 20995 { 3, Iclass_xt_mul32h_args, 20996 0, 0, 0, 0 }, 20997 { 2, Iclass_xt_iclass_mac16_aa_args, 20998 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 }, 20999 { 2, Iclass_xt_iclass_mac16_ad_args, 21000 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 }, 21001 { 2, Iclass_xt_iclass_mac16_da_args, 21002 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 }, 21003 { 2, Iclass_xt_iclass_mac16_dd_args, 21004 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 }, 21005 { 2, Iclass_xt_iclass_mac16a_aa_args, 21006 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 }, 21007 { 2, Iclass_xt_iclass_mac16a_ad_args, 21008 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 }, 21009 { 2, Iclass_xt_iclass_mac16a_da_args, 21010 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 }, 21011 { 2, Iclass_xt_iclass_mac16a_dd_args, 21012 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 }, 21013 { 4, Iclass_xt_iclass_mac16al_da_args, 21014 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 }, 21015 { 4, Iclass_xt_iclass_mac16al_dd_args, 21016 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 }, 21017 { 2, Iclass_xt_iclass_mac16_l_args, 21018 0, 0, 0, 0 }, 21019 { 2, Iclass_xt_iclass_rsr_m0_args, 21020 0, 0, 0, 0 }, 21021 { 2, Iclass_xt_iclass_wsr_m0_args, 21022 0, 0, 0, 0 }, 21023 { 2, Iclass_xt_iclass_xsr_m0_args, 21024 0, 0, 0, 0 }, 21025 { 2, Iclass_xt_iclass_rsr_m1_args, 21026 0, 0, 0, 0 }, 21027 { 2, Iclass_xt_iclass_wsr_m1_args, 21028 0, 0, 0, 0 }, 21029 { 2, Iclass_xt_iclass_xsr_m1_args, 21030 0, 0, 0, 0 }, 21031 { 2, Iclass_xt_iclass_rsr_m2_args, 21032 0, 0, 0, 0 }, 21033 { 2, Iclass_xt_iclass_wsr_m2_args, 21034 0, 0, 0, 0 }, 21035 { 2, Iclass_xt_iclass_xsr_m2_args, 21036 0, 0, 0, 0 }, 21037 { 2, Iclass_xt_iclass_rsr_m3_args, 21038 0, 0, 0, 0 }, 21039 { 2, Iclass_xt_iclass_wsr_m3_args, 21040 0, 0, 0, 0 }, 21041 { 2, Iclass_xt_iclass_xsr_m3_args, 21042 0, 0, 0, 0 }, 21043 { 1, Iclass_xt_iclass_rsr_acclo_args, 21044 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 }, 21045 { 1, Iclass_xt_iclass_wsr_acclo_args, 21046 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 }, 21047 { 1, Iclass_xt_iclass_xsr_acclo_args, 21048 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 }, 21049 { 1, Iclass_xt_iclass_rsr_acchi_args, 21050 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 }, 21051 { 1, Iclass_xt_iclass_wsr_acchi_args, 21052 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 }, 21053 { 1, Iclass_xt_iclass_xsr_acchi_args, 21054 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 }, 21055 { 1, Iclass_xt_iclass_rfi_args, 21056 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 }, 21057 { 1, Iclass_xt_iclass_wait_args, 21058 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 }, 21059 { 1, Iclass_xt_iclass_rsr_interrupt_args, 21060 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 }, 21061 { 1, Iclass_xt_iclass_wsr_intset_args, 21062 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 }, 21063 { 1, Iclass_xt_iclass_wsr_intclear_args, 21064 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 }, 21065 { 1, Iclass_xt_iclass_rsr_intenable_args, 21066 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 }, 21067 { 1, Iclass_xt_iclass_wsr_intenable_args, 21068 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 }, 21069 { 1, Iclass_xt_iclass_xsr_intenable_args, 21070 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 }, 21071 { 2, Iclass_xt_iclass_break_args, 21072 2, Iclass_xt_iclass_break_stateArgs, 0, 0 }, 21073 { 1, Iclass_xt_iclass_break_n_args, 21074 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 }, 21075 { 1, Iclass_xt_iclass_rsr_dbreaka0_args, 21076 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 }, 21077 { 1, Iclass_xt_iclass_wsr_dbreaka0_args, 21078 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 }, 21079 { 1, Iclass_xt_iclass_xsr_dbreaka0_args, 21080 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 }, 21081 { 1, Iclass_xt_iclass_rsr_dbreakc0_args, 21082 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 }, 21083 { 1, Iclass_xt_iclass_wsr_dbreakc0_args, 21084 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 }, 21085 { 1, Iclass_xt_iclass_xsr_dbreakc0_args, 21086 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 }, 21087 { 1, Iclass_xt_iclass_rsr_dbreaka1_args, 21088 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 }, 21089 { 1, Iclass_xt_iclass_wsr_dbreaka1_args, 21090 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 }, 21091 { 1, Iclass_xt_iclass_xsr_dbreaka1_args, 21092 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 }, 21093 { 1, Iclass_xt_iclass_rsr_dbreakc1_args, 21094 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 }, 21095 { 1, Iclass_xt_iclass_wsr_dbreakc1_args, 21096 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 }, 21097 { 1, Iclass_xt_iclass_xsr_dbreakc1_args, 21098 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 }, 21099 { 1, Iclass_xt_iclass_rsr_ibreaka0_args, 21100 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 }, 21101 { 1, Iclass_xt_iclass_wsr_ibreaka0_args, 21102 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 }, 21103 { 1, Iclass_xt_iclass_xsr_ibreaka0_args, 21104 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 }, 21105 { 1, Iclass_xt_iclass_rsr_ibreaka1_args, 21106 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 }, 21107 { 1, Iclass_xt_iclass_wsr_ibreaka1_args, 21108 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 }, 21109 { 1, Iclass_xt_iclass_xsr_ibreaka1_args, 21110 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 }, 21111 { 1, Iclass_xt_iclass_rsr_ibreakenable_args, 21112 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 }, 21113 { 1, Iclass_xt_iclass_wsr_ibreakenable_args, 21114 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 }, 21115 { 1, Iclass_xt_iclass_xsr_ibreakenable_args, 21116 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 }, 21117 { 1, Iclass_xt_iclass_rsr_debugcause_args, 21118 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 }, 21119 { 1, Iclass_xt_iclass_wsr_debugcause_args, 21120 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 }, 21121 { 1, Iclass_xt_iclass_xsr_debugcause_args, 21122 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 }, 21123 { 1, Iclass_xt_iclass_rsr_icount_args, 21124 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 }, 21125 { 1, Iclass_xt_iclass_wsr_icount_args, 21126 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 }, 21127 { 1, Iclass_xt_iclass_xsr_icount_args, 21128 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 }, 21129 { 1, Iclass_xt_iclass_rsr_icountlevel_args, 21130 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 }, 21131 { 1, Iclass_xt_iclass_wsr_icountlevel_args, 21132 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 }, 21133 { 1, Iclass_xt_iclass_xsr_icountlevel_args, 21134 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 }, 21135 { 1, Iclass_xt_iclass_rsr_ddr_args, 21136 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 }, 21137 { 1, Iclass_xt_iclass_wsr_ddr_args, 21138 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 }, 21139 { 1, Iclass_xt_iclass_xsr_ddr_args, 21140 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 }, 21141 { 1, Iclass_xt_iclass_lddr32_p_args, 21142 5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 }, 21143 { 1, Iclass_xt_iclass_sddr32_p_args, 21144 4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 }, 21145 { 1, Iclass_xt_iclass_rfdo_args, 21146 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 }, 21147 { 0, 0 /* xt_iclass_rfdd */, 21148 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 }, 21149 { 1, Iclass_xt_iclass_wsr_mmid_args, 21150 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 }, 21151 { 3, Iclass_xt_iclass_bbool1_args, 21152 0, 0, 0, 0 }, 21153 { 2, Iclass_xt_iclass_bbool4_args, 21154 0, 0, 0, 0 }, 21155 { 2, Iclass_xt_iclass_bbool8_args, 21156 0, 0, 0, 0 }, 21157 { 2, Iclass_xt_iclass_bbranch_args, 21158 0, 0, 0, 0 }, 21159 { 3, Iclass_xt_iclass_bmove_args, 21160 0, 0, 0, 0 }, 21161 { 2, Iclass_xt_iclass_RSR_BR_args, 21162 0, 0, 0, 0 }, 21163 { 2, Iclass_xt_iclass_WSR_BR_args, 21164 0, 0, 0, 0 }, 21165 { 2, Iclass_xt_iclass_XSR_BR_args, 21166 0, 0, 0, 0 }, 21167 { 1, Iclass_xt_iclass_rsr_ccount_args, 21168 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 }, 21169 { 1, Iclass_xt_iclass_wsr_ccount_args, 21170 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 }, 21171 { 1, Iclass_xt_iclass_xsr_ccount_args, 21172 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 }, 21173 { 1, Iclass_xt_iclass_rsr_ccompare0_args, 21174 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 }, 21175 { 1, Iclass_xt_iclass_wsr_ccompare0_args, 21176 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 }, 21177 { 1, Iclass_xt_iclass_xsr_ccompare0_args, 21178 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 }, 21179 { 1, Iclass_xt_iclass_rsr_ccompare1_args, 21180 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 }, 21181 { 1, Iclass_xt_iclass_wsr_ccompare1_args, 21182 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 }, 21183 { 1, Iclass_xt_iclass_xsr_ccompare1_args, 21184 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 }, 21185 { 1, Iclass_xt_iclass_rsr_ccompare2_args, 21186 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 }, 21187 { 1, Iclass_xt_iclass_wsr_ccompare2_args, 21188 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 }, 21189 { 1, Iclass_xt_iclass_xsr_ccompare2_args, 21190 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 }, 21191 { 2, Iclass_xt_iclass_icache_args, 21192 0, 0, 0, 0 }, 21193 { 2, Iclass_xt_iclass_icache_lock_args, 21194 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 }, 21195 { 2, Iclass_xt_iclass_icache_inv_args, 21196 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 }, 21197 { 2, Iclass_xt_iclass_licx_args, 21198 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 }, 21199 { 2, Iclass_xt_iclass_sicx_args, 21200 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 }, 21201 { 2, Iclass_xt_iclass_dcache_args, 21202 0, 0, 0, 0 }, 21203 { 1, Iclass_xt_iclass_dcache_dyn_args, 21204 2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 }, 21205 { 2, Iclass_xt_iclass_dcache_ind_args, 21206 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 }, 21207 { 2, Iclass_xt_iclass_dcache_inv_args, 21208 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 }, 21209 { 2, Iclass_xt_iclass_dpf_args, 21210 0, 0, 0, 0 }, 21211 { 2, Iclass_xt_iclass_dcache_lock_args, 21212 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 }, 21213 { 2, Iclass_xt_iclass_sdct_args, 21214 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 }, 21215 { 2, Iclass_xt_iclass_ldct_args, 21216 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 }, 21217 { 1, Iclass_xt_iclass_rsr_prefctl_args, 21218 1, Iclass_xt_iclass_rsr_prefctl_stateArgs, 0, 0 }, 21219 { 1, Iclass_xt_iclass_wsr_prefctl_args, 21220 1, Iclass_xt_iclass_wsr_prefctl_stateArgs, 0, 0 }, 21221 { 1, Iclass_xt_iclass_xsr_prefctl_args, 21222 1, Iclass_xt_iclass_xsr_prefctl_stateArgs, 0, 0 }, 21223 { 1, Iclass_xt_iclass_wsr_ptevaddr_args, 21224 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 }, 21225 { 1, Iclass_xt_iclass_rsr_ptevaddr_args, 21226 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 }, 21227 { 1, Iclass_xt_iclass_xsr_ptevaddr_args, 21228 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 }, 21229 { 1, Iclass_xt_iclass_rsr_rasid_args, 21230 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 }, 21231 { 1, Iclass_xt_iclass_wsr_rasid_args, 21232 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 }, 21233 { 1, Iclass_xt_iclass_xsr_rasid_args, 21234 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 }, 21235 { 1, Iclass_xt_iclass_rsr_itlbcfg_args, 21236 5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 }, 21237 { 1, Iclass_xt_iclass_wsr_itlbcfg_args, 21238 6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 }, 21239 { 1, Iclass_xt_iclass_xsr_itlbcfg_args, 21240 6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 }, 21241 { 1, Iclass_xt_iclass_rsr_dtlbcfg_args, 21242 5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 }, 21243 { 1, Iclass_xt_iclass_wsr_dtlbcfg_args, 21244 6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 }, 21245 { 1, Iclass_xt_iclass_xsr_dtlbcfg_args, 21246 6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 }, 21247 { 1, Iclass_xt_iclass_idtlb_args, 21248 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 }, 21249 { 2, Iclass_xt_iclass_rdtlb_args, 21250 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 }, 21251 { 2, Iclass_xt_iclass_wdtlb_args, 21252 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 }, 21253 { 1, Iclass_xt_iclass_iitlb_args, 21254 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 }, 21255 { 2, Iclass_xt_iclass_ritlb_args, 21256 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 }, 21257 { 2, Iclass_xt_iclass_witlb_args, 21258 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 }, 21259 { 0, 0 /* xt_iclass_ldpte */, 21260 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 }, 21261 { 0, 0 /* xt_iclass_hwwitlba */, 21262 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 }, 21263 { 0, 0 /* xt_iclass_hwwdtlba */, 21264 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 }, 21265 { 1, Iclass_xt_iclass_rsr_cpenable_args, 21266 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 }, 21267 { 1, Iclass_xt_iclass_wsr_cpenable_args, 21268 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 }, 21269 { 1, Iclass_xt_iclass_xsr_cpenable_args, 21270 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 }, 21271 { 3, Iclass_xt_iclass_clamp_args, 21272 0, 0, 0, 0 }, 21273 { 3, Iclass_xt_iclass_minmax_args, 21274 0, 0, 0, 0 }, 21275 { 2, Iclass_xt_iclass_nsa_args, 21276 0, 0, 0, 0 }, 21277 { 3, Iclass_xt_iclass_sx_args, 21278 0, 0, 0, 0 }, 21279 { 3, Iclass_xt_iclass_l32ai_args, 21280 0, 0, 0, 0 }, 21281 { 3, Iclass_xt_iclass_s32ri_args, 21282 0, 0, 0, 0 }, 21283 { 3, Iclass_xt_iclass_s32c1i_args, 21284 3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 }, 21285 { 1, Iclass_xt_iclass_rsr_scompare1_args, 21286 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 }, 21287 { 1, Iclass_xt_iclass_wsr_scompare1_args, 21288 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 }, 21289 { 1, Iclass_xt_iclass_xsr_scompare1_args, 21290 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 }, 21291 { 1, Iclass_xt_iclass_rsr_atomctl_args, 21292 3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 }, 21293 { 1, Iclass_xt_iclass_wsr_atomctl_args, 21294 4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 }, 21295 { 1, Iclass_xt_iclass_xsr_atomctl_args, 21296 4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 }, 21297 { 3, Iclass_xt_iclass_div_args, 21298 0, 0, 0, 0 }, 21299 { 2, Iclass_xt_iclass_rer_args, 21300 3, Iclass_xt_iclass_rer_stateArgs, 2, Iclass_xt_iclass_rer_intfArgs }, 21301 { 2, Iclass_xt_iclass_wer_args, 21302 3, Iclass_xt_iclass_wer_stateArgs, 2, Iclass_xt_iclass_wer_intfArgs }, 21303 { 1, Iclass_rur_ae_ovf_sar_args, 21304 3, Iclass_rur_ae_ovf_sar_stateArgs, 0, 0 }, 21305 { 1, Iclass_wur_ae_ovf_sar_args, 21306 3, Iclass_wur_ae_ovf_sar_stateArgs, 0, 0 }, 21307 { 1, Iclass_rur_ae_bithead_args, 21308 2, Iclass_rur_ae_bithead_stateArgs, 0, 0 }, 21309 { 1, Iclass_wur_ae_bithead_args, 21310 2, Iclass_wur_ae_bithead_stateArgs, 0, 0 }, 21311 { 1, Iclass_rur_ae_ts_fts_bu_bp_args, 21312 5, Iclass_rur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, 21313 { 1, Iclass_wur_ae_ts_fts_bu_bp_args, 21314 5, Iclass_wur_ae_ts_fts_bu_bp_stateArgs, 0, 0 }, 21315 { 1, Iclass_rur_ae_sd_no_args, 21316 3, Iclass_rur_ae_sd_no_stateArgs, 0, 0 }, 21317 { 1, Iclass_wur_ae_sd_no_args, 21318 3, Iclass_wur_ae_sd_no_stateArgs, 0, 0 }, 21319 { 1, Iclass_ae_iclass_rur_ae_overflow_args, 21320 2, Iclass_ae_iclass_rur_ae_overflow_stateArgs, 0, 0 }, 21321 { 1, Iclass_ae_iclass_wur_ae_overflow_args, 21322 2, Iclass_ae_iclass_wur_ae_overflow_stateArgs, 0, 0 }, 21323 { 1, Iclass_ae_iclass_rur_ae_sar_args, 21324 2, Iclass_ae_iclass_rur_ae_sar_stateArgs, 0, 0 }, 21325 { 1, Iclass_ae_iclass_wur_ae_sar_args, 21326 2, Iclass_ae_iclass_wur_ae_sar_stateArgs, 0, 0 }, 21327 { 1, Iclass_ae_iclass_rur_ae_bitptr_args, 21328 2, Iclass_ae_iclass_rur_ae_bitptr_stateArgs, 0, 0 }, 21329 { 1, Iclass_ae_iclass_wur_ae_bitptr_args, 21330 2, Iclass_ae_iclass_wur_ae_bitptr_stateArgs, 0, 0 }, 21331 { 1, Iclass_ae_iclass_rur_ae_bitsused_args, 21332 2, Iclass_ae_iclass_rur_ae_bitsused_stateArgs, 0, 0 }, 21333 { 1, Iclass_ae_iclass_wur_ae_bitsused_args, 21334 2, Iclass_ae_iclass_wur_ae_bitsused_stateArgs, 0, 0 }, 21335 { 1, Iclass_ae_iclass_rur_ae_tablesize_args, 21336 2, Iclass_ae_iclass_rur_ae_tablesize_stateArgs, 0, 0 }, 21337 { 1, Iclass_ae_iclass_wur_ae_tablesize_args, 21338 2, Iclass_ae_iclass_wur_ae_tablesize_stateArgs, 0, 0 }, 21339 { 1, Iclass_ae_iclass_rur_ae_first_ts_args, 21340 2, Iclass_ae_iclass_rur_ae_first_ts_stateArgs, 0, 0 }, 21341 { 1, Iclass_ae_iclass_wur_ae_first_ts_args, 21342 2, Iclass_ae_iclass_wur_ae_first_ts_stateArgs, 0, 0 }, 21343 { 1, Iclass_ae_iclass_rur_ae_nextoffset_args, 21344 2, Iclass_ae_iclass_rur_ae_nextoffset_stateArgs, 0, 0 }, 21345 { 1, Iclass_ae_iclass_wur_ae_nextoffset_args, 21346 2, Iclass_ae_iclass_wur_ae_nextoffset_stateArgs, 0, 0 }, 21347 { 1, Iclass_ae_iclass_rur_ae_searchdone_args, 21348 2, Iclass_ae_iclass_rur_ae_searchdone_stateArgs, 0, 0 }, 21349 { 1, Iclass_ae_iclass_wur_ae_searchdone_args, 21350 2, Iclass_ae_iclass_wur_ae_searchdone_stateArgs, 0, 0 }, 21351 { 3, Iclass_ae_iclass_lp16f_i_args, 21352 1, Iclass_ae_iclass_lp16f_i_stateArgs, 0, 0 }, 21353 { 3, Iclass_ae_iclass_lp16f_iu_args, 21354 1, Iclass_ae_iclass_lp16f_iu_stateArgs, 0, 0 }, 21355 { 3, Iclass_ae_iclass_lp16f_x_args, 21356 1, Iclass_ae_iclass_lp16f_x_stateArgs, 0, 0 }, 21357 { 3, Iclass_ae_iclass_lp16f_xu_args, 21358 1, Iclass_ae_iclass_lp16f_xu_stateArgs, 0, 0 }, 21359 { 3, Iclass_ae_iclass_lp24_i_args, 21360 1, Iclass_ae_iclass_lp24_i_stateArgs, 0, 0 }, 21361 { 3, Iclass_ae_iclass_lp24_iu_args, 21362 1, Iclass_ae_iclass_lp24_iu_stateArgs, 0, 0 }, 21363 { 3, Iclass_ae_iclass_lp24_x_args, 21364 1, Iclass_ae_iclass_lp24_x_stateArgs, 0, 0 }, 21365 { 3, Iclass_ae_iclass_lp24_xu_args, 21366 1, Iclass_ae_iclass_lp24_xu_stateArgs, 0, 0 }, 21367 { 3, Iclass_ae_iclass_lp24f_i_args, 21368 1, Iclass_ae_iclass_lp24f_i_stateArgs, 0, 0 }, 21369 { 3, Iclass_ae_iclass_lp24f_iu_args, 21370 1, Iclass_ae_iclass_lp24f_iu_stateArgs, 0, 0 }, 21371 { 3, Iclass_ae_iclass_lp24f_x_args, 21372 1, Iclass_ae_iclass_lp24f_x_stateArgs, 0, 0 }, 21373 { 3, Iclass_ae_iclass_lp24f_xu_args, 21374 1, Iclass_ae_iclass_lp24f_xu_stateArgs, 0, 0 }, 21375 { 3, Iclass_ae_iclass_lp16x2f_i_args, 21376 1, Iclass_ae_iclass_lp16x2f_i_stateArgs, 0, 0 }, 21377 { 3, Iclass_ae_iclass_lp16x2f_iu_args, 21378 1, Iclass_ae_iclass_lp16x2f_iu_stateArgs, 0, 0 }, 21379 { 3, Iclass_ae_iclass_lp16x2f_x_args, 21380 1, Iclass_ae_iclass_lp16x2f_x_stateArgs, 0, 0 }, 21381 { 3, Iclass_ae_iclass_lp16x2f_xu_args, 21382 1, Iclass_ae_iclass_lp16x2f_xu_stateArgs, 0, 0 }, 21383 { 3, Iclass_ae_iclass_lp24x2f_i_args, 21384 1, Iclass_ae_iclass_lp24x2f_i_stateArgs, 0, 0 }, 21385 { 3, Iclass_ae_iclass_lp24x2f_iu_args, 21386 1, Iclass_ae_iclass_lp24x2f_iu_stateArgs, 0, 0 }, 21387 { 3, Iclass_ae_iclass_lp24x2f_x_args, 21388 1, Iclass_ae_iclass_lp24x2f_x_stateArgs, 0, 0 }, 21389 { 3, Iclass_ae_iclass_lp24x2f_xu_args, 21390 1, Iclass_ae_iclass_lp24x2f_xu_stateArgs, 0, 0 }, 21391 { 3, Iclass_ae_iclass_lp24x2_i_args, 21392 1, Iclass_ae_iclass_lp24x2_i_stateArgs, 0, 0 }, 21393 { 3, Iclass_ae_iclass_lp24x2_iu_args, 21394 1, Iclass_ae_iclass_lp24x2_iu_stateArgs, 0, 0 }, 21395 { 3, Iclass_ae_iclass_lp24x2_x_args, 21396 1, Iclass_ae_iclass_lp24x2_x_stateArgs, 0, 0 }, 21397 { 3, Iclass_ae_iclass_lp24x2_xu_args, 21398 1, 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Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs, 0, 0 }, 21915 { 5, Iclass_ae_iclass_mulzsafq32sp16s_hh_args, 21916 1, Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs, 0, 0 }, 21917 { 5, Iclass_ae_iclass_mulzsaq32sp16u_hh_args, 21918 1, Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs, 0, 0 }, 21919 { 5, Iclass_ae_iclass_mulzsafq32sp16u_hh_args, 21920 1, Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs, 0, 0 }, 21921 { 5, Iclass_ae_iclass_mulzsaq32sp16s_lh_args, 21922 1, Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs, 0, 0 }, 21923 { 5, Iclass_ae_iclass_mulzsafq32sp16s_lh_args, 21924 1, Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs, 0, 0 }, 21925 { 5, Iclass_ae_iclass_mulzsaq32sp16u_lh_args, 21926 1, Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs, 0, 0 }, 21927 { 5, Iclass_ae_iclass_mulzsafq32sp16u_lh_args, 21928 1, Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs, 0, 0 }, 21929 { 5, Iclass_ae_iclass_mulzssq32sp16s_ll_args, 21930 1, Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs, 0, 0 }, 21931 { 5, Iclass_ae_iclass_mulzssfq32sp16s_ll_args, 21932 1, Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs, 0, 0 }, 21933 { 5, Iclass_ae_iclass_mulzssq32sp16u_ll_args, 21934 1, Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs, 0, 0 }, 21935 { 5, Iclass_ae_iclass_mulzssfq32sp16u_ll_args, 21936 1, Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs, 0, 0 }, 21937 { 5, Iclass_ae_iclass_mulzssq32sp16s_hh_args, 21938 1, Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs, 0, 0 }, 21939 { 5, Iclass_ae_iclass_mulzssfq32sp16s_hh_args, 21940 1, Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs, 0, 0 }, 21941 { 5, Iclass_ae_iclass_mulzssq32sp16u_hh_args, 21942 1, Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs, 0, 0 }, 21943 { 5, Iclass_ae_iclass_mulzssfq32sp16u_hh_args, 21944 1, Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs, 0, 0 }, 21945 { 5, Iclass_ae_iclass_mulzssq32sp16s_lh_args, 21946 1, Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs, 0, 0 }, 21947 { 5, Iclass_ae_iclass_mulzssfq32sp16s_lh_args, 21948 1, Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs, 0, 0 }, 21949 { 5, Iclass_ae_iclass_mulzssq32sp16u_lh_args, 21950 1, Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs, 0, 0 }, 21951 { 5, Iclass_ae_iclass_mulzssfq32sp16u_lh_args, 21952 1, Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs, 0, 0 }, 21953 { 3, Iclass_ae_iclass_mulzaafp24s_hh_ll_args, 21954 1, Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs, 0, 0 }, 21955 { 3, Iclass_ae_iclass_mulzaap24s_hh_ll_args, 21956 1, Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs, 0, 0 }, 21957 { 3, Iclass_ae_iclass_mulzaafp24s_hl_lh_args, 21958 1, Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs, 0, 0 }, 21959 { 3, Iclass_ae_iclass_mulzaap24s_hl_lh_args, 21960 1, Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs, 0, 0 }, 21961 { 3, Iclass_ae_iclass_mulzasfp24s_hh_ll_args, 21962 1, Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs, 0, 0 }, 21963 { 3, Iclass_ae_iclass_mulzasp24s_hh_ll_args, 21964 1, Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs, 0, 0 }, 21965 { 3, Iclass_ae_iclass_mulzasfp24s_hl_lh_args, 21966 1, Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs, 0, 0 }, 21967 { 3, Iclass_ae_iclass_mulzasp24s_hl_lh_args, 21968 1, Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs, 0, 0 }, 21969 { 3, Iclass_ae_iclass_mulzsafp24s_hh_ll_args, 21970 1, Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs, 0, 0 }, 21971 { 3, Iclass_ae_iclass_mulzsap24s_hh_ll_args, 21972 1, Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs, 0, 0 }, 21973 { 3, Iclass_ae_iclass_mulzsafp24s_hl_lh_args, 21974 1, Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs, 0, 0 }, 21975 { 3, Iclass_ae_iclass_mulzsap24s_hl_lh_args, 21976 1, Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs, 0, 0 }, 21977 { 3, Iclass_ae_iclass_mulzssfp24s_hh_ll_args, 21978 1, Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs, 0, 0 }, 21979 { 3, Iclass_ae_iclass_mulzssp24s_hh_ll_args, 21980 1, Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs, 0, 0 }, 21981 { 3, Iclass_ae_iclass_mulzssfp24s_hl_lh_args, 21982 1, Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs, 0, 0 }, 21983 { 3, Iclass_ae_iclass_mulzssp24s_hl_lh_args, 21984 1, Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs, 0, 0 }, 21985 { 3, Iclass_ae_iclass_mulaafp24s_hh_ll_args, 21986 1, Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs, 0, 0 }, 21987 { 3, Iclass_ae_iclass_mulaap24s_hh_ll_args, 21988 1, Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs, 0, 0 }, 21989 { 3, Iclass_ae_iclass_mulaafp24s_hl_lh_args, 21990 1, Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs, 0, 0 }, 21991 { 3, Iclass_ae_iclass_mulaap24s_hl_lh_args, 21992 1, Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs, 0, 0 }, 21993 { 3, Iclass_ae_iclass_mulasfp24s_hh_ll_args, 21994 1, Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs, 0, 0 }, 21995 { 3, Iclass_ae_iclass_mulasp24s_hh_ll_args, 21996 1, Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs, 0, 0 }, 21997 { 3, Iclass_ae_iclass_mulasfp24s_hl_lh_args, 21998 1, Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs, 0, 0 }, 21999 { 3, Iclass_ae_iclass_mulasp24s_hl_lh_args, 22000 1, Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs, 0, 0 }, 22001 { 3, Iclass_ae_iclass_mulsafp24s_hh_ll_args, 22002 1, Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs, 0, 0 }, 22003 { 3, Iclass_ae_iclass_mulsap24s_hh_ll_args, 22004 1, Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs, 0, 0 }, 22005 { 3, Iclass_ae_iclass_mulsafp24s_hl_lh_args, 22006 1, Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs, 0, 0 }, 22007 { 3, Iclass_ae_iclass_mulsap24s_hl_lh_args, 22008 1, Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs, 0, 0 }, 22009 { 3, Iclass_ae_iclass_mulssfp24s_hh_ll_args, 22010 1, Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs, 0, 0 }, 22011 { 3, Iclass_ae_iclass_mulssp24s_hh_ll_args, 22012 1, Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs, 0, 0 }, 22013 { 3, Iclass_ae_iclass_mulssfp24s_hl_lh_args, 22014 1, Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs, 0, 0 }, 22015 { 3, Iclass_ae_iclass_mulssp24s_hl_lh_args, 22016 1, Iclass_ae_iclass_mulssp24s_hl_lh_stateArgs, 0, 0 }, 22017 { 2, Iclass_ae_iclass_sha32_args, 22018 0, 0, 0, 0 }, 22019 { 3, Iclass_ae_iclass_vldl32t_args, 22020 5, Iclass_ae_iclass_vldl32t_stateArgs, 0, 0 }, 22021 { 3, Iclass_ae_iclass_vldl16t_args, 22022 5, Iclass_ae_iclass_vldl16t_stateArgs, 0, 0 }, 22023 { 1, Iclass_ae_iclass_vldl16c_args, 22024 8, Iclass_ae_iclass_vldl16c_stateArgs, 0, 0 }, 22025 { 1, Iclass_ae_iclass_vldsht_args, 22026 6, Iclass_ae_iclass_vldsht_stateArgs, 0, 0 }, 22027 { 2, Iclass_ae_iclass_lb_args, 22028 3, Iclass_ae_iclass_lb_stateArgs, 0, 0 }, 22029 { 2, Iclass_ae_iclass_lbi_args, 22030 3, Iclass_ae_iclass_lbi_stateArgs, 0, 0 }, 22031 { 3, Iclass_ae_iclass_lbk_args, 22032 3, Iclass_ae_iclass_lbk_stateArgs, 0, 0 }, 22033 { 3, Iclass_ae_iclass_lbki_args, 22034 3, Iclass_ae_iclass_lbki_stateArgs, 0, 0 }, 22035 { 2, Iclass_ae_iclass_db_args, 22036 3, Iclass_ae_iclass_db_stateArgs, 0, 0 }, 22037 { 2, Iclass_ae_iclass_dbi_args, 22038 3, Iclass_ae_iclass_dbi_stateArgs, 0, 0 }, 22039 { 3, Iclass_ae_iclass_vlel32t_args, 22040 3, Iclass_ae_iclass_vlel32t_stateArgs, 0, 0 }, 22041 { 3, Iclass_ae_iclass_vlel16t_args, 22042 3, Iclass_ae_iclass_vlel16t_stateArgs, 0, 0 }, 22043 { 2, Iclass_ae_iclass_sb_args, 22044 4, Iclass_ae_iclass_sb_stateArgs, 0, 0 }, 22045 { 3, Iclass_ae_iclass_sbi_args, 22046 3, Iclass_ae_iclass_sbi_stateArgs, 0, 0 }, 22047 { 1, Iclass_ae_iclass_vles16c_args, 22048 5, Iclass_ae_iclass_vles16c_stateArgs, 0, 0 }, 22049 { 1, Iclass_ae_iclass_sbf_args, 22050 3, Iclass_ae_iclass_sbf_stateArgs, 0, 0 }, 22051 { 3, Iclass_icls_AE_SLAASQ56S_args, 22052 2, Iclass_icls_AE_SLAASQ56S_stateArgs, 0, 0 }, 22053 { 3, Iclass_icls_AE_ADDBRBA32_args, 22054 0, 0, 0, 0 }, 22055 { 3, Iclass_icls_AE_MINABSSP24S_args, 22056 2, Iclass_icls_AE_MINABSSP24S_stateArgs, 0, 0 }, 22057 { 3, Iclass_icls_AE_MAXABSSP24S_args, 22058 2, Iclass_icls_AE_MAXABSSP24S_stateArgs, 0, 0 }, 22059 { 3, Iclass_icls_AE_MINABSSQ56S_args, 22060 2, Iclass_icls_AE_MINABSSQ56S_stateArgs, 0, 0 }, 22061 { 3, Iclass_icls_AE_MAXABSSQ56S_args, 22062 2, Iclass_icls_AE_MAXABSSQ56S_stateArgs, 0, 0 }, 22063 { 1, Iclass_rur_ae_cbegin0_args, 22064 2, Iclass_rur_ae_cbegin0_stateArgs, 0, 0 }, 22065 { 1, Iclass_wur_ae_cbegin0_args, 22066 2, Iclass_wur_ae_cbegin0_stateArgs, 0, 0 }, 22067 { 1, Iclass_rur_ae_cend0_args, 22068 2, Iclass_rur_ae_cend0_stateArgs, 0, 0 }, 22069 { 1, Iclass_wur_ae_cend0_args, 22070 2, Iclass_wur_ae_cend0_stateArgs, 0, 0 }, 22071 { 3, Iclass_icls_AE_LP24X2_C_args, 22072 3, Iclass_icls_AE_LP24X2_C_stateArgs, 0, 0 }, 22073 { 3, Iclass_icls_AE_SP24X2S_C_args, 22074 3, Iclass_icls_AE_SP24X2S_C_stateArgs, 0, 0 }, 22075 { 3, Iclass_icls_AE_LP24X2F_C_args, 22076 3, Iclass_icls_AE_LP24X2F_C_stateArgs, 0, 0 }, 22077 { 3, Iclass_icls_AE_SP24X2F_C_args, 22078 3, Iclass_icls_AE_SP24X2F_C_stateArgs, 0, 0 }, 22079 { 3, Iclass_icls_AE_LP16X2F_C_args, 22080 3, Iclass_icls_AE_LP16X2F_C_stateArgs, 0, 0 }, 22081 { 3, Iclass_icls_AE_SP16X2F_C_args, 22082 3, Iclass_icls_AE_SP16X2F_C_stateArgs, 0, 0 }, 22083 { 3, Iclass_icls_AE_LP24_C_args, 22084 3, Iclass_icls_AE_LP24_C_stateArgs, 0, 0 }, 22085 { 3, Iclass_icls_AE_SP24S_L_C_args, 22086 3, Iclass_icls_AE_SP24S_L_C_stateArgs, 0, 0 }, 22087 { 3, Iclass_icls_AE_LP24F_C_args, 22088 3, Iclass_icls_AE_LP24F_C_stateArgs, 0, 0 }, 22089 { 3, Iclass_icls_AE_SP24F_L_C_args, 22090 3, Iclass_icls_AE_SP24F_L_C_stateArgs, 0, 0 }, 22091 { 3, Iclass_icls_AE_LP16F_C_args, 22092 3, Iclass_icls_AE_LP16F_C_stateArgs, 0, 0 }, 22093 { 3, Iclass_icls_AE_SP16F_L_C_args, 22094 3, Iclass_icls_AE_SP16F_L_C_stateArgs, 0, 0 }, 22095 { 3, Iclass_icls_AE_LQ56_C_args, 22096 3, Iclass_icls_AE_LQ56_C_stateArgs, 0, 0 }, 22097 { 3, Iclass_icls_AE_SQ56S_C_args, 22098 3, Iclass_icls_AE_SQ56S_C_stateArgs, 0, 0 }, 22099 { 3, Iclass_icls_AE_LQ32F_C_args, 22100 3, Iclass_icls_AE_LQ32F_C_stateArgs, 0, 0 }, 22101 { 3, Iclass_icls_AE_SQ32F_C_args, 22102 3, Iclass_icls_AE_SQ32F_C_stateArgs, 0, 0 }, 22103 { 1, Iclass_rur_expstate_args, 22104 2, Iclass_rur_expstate_stateArgs, 0, 0 }, 22105 { 1, Iclass_wur_expstate_args, 22106 2, Iclass_wur_expstate_stateArgs, 0, 0 }, 22107 { 1, Iclass_iclass_READ_IMPWIRE_args, 22108 1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs }, 22109 { 1, Iclass_iclass_SETB_EXPSTATE_args, 22110 2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 }, 22111 { 1, Iclass_iclass_CLRB_EXPSTATE_args, 22112 2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 }, 22113 { 2, Iclass_iclass_WRMSK_EXPSTATE_args, 22114 2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 } 22115 }; 22116 22117 enum xtensa_iclass_id { 22118 ICLASS_xt_iclass_excw, 22119 ICLASS_xt_iclass_rfe, 22120 ICLASS_xt_iclass_rfde, 22121 ICLASS_xt_iclass_syscall, 22122 ICLASS_xt_iclass_call12, 22123 ICLASS_xt_iclass_call8, 22124 ICLASS_xt_iclass_call4, 22125 ICLASS_xt_iclass_callx12, 22126 ICLASS_xt_iclass_callx8, 22127 ICLASS_xt_iclass_callx4, 22128 ICLASS_xt_iclass_entry, 22129 ICLASS_xt_iclass_movsp, 22130 ICLASS_xt_iclass_rotw, 22131 ICLASS_xt_iclass_retw, 22132 ICLASS_xt_iclass_rfwou, 22133 ICLASS_xt_iclass_l32e, 22134 ICLASS_xt_iclass_s32e, 22135 ICLASS_xt_iclass_rsr_windowbase, 22136 ICLASS_xt_iclass_wsr_windowbase, 22137 ICLASS_xt_iclass_xsr_windowbase, 22138 ICLASS_xt_iclass_rsr_windowstart, 22139 ICLASS_xt_iclass_wsr_windowstart, 22140 ICLASS_xt_iclass_xsr_windowstart, 22141 ICLASS_xt_iclass_add_n, 22142 ICLASS_xt_iclass_addi_n, 22143 ICLASS_xt_iclass_bz6, 22144 ICLASS_xt_iclass_ill_n, 22145 ICLASS_xt_iclass_loadi4, 22146 ICLASS_xt_iclass_mov_n, 22147 ICLASS_xt_iclass_movi_n, 22148 ICLASS_xt_iclass_nopn, 22149 ICLASS_xt_iclass_retn, 22150 ICLASS_xt_iclass_storei4, 22151 ICLASS_rur_threadptr, 22152 ICLASS_wur_threadptr, 22153 ICLASS_xt_iclass_addi, 22154 ICLASS_xt_iclass_addmi, 22155 ICLASS_xt_iclass_addsub, 22156 ICLASS_xt_iclass_bit, 22157 ICLASS_xt_iclass_bsi8, 22158 ICLASS_xt_iclass_bsi8b, 22159 ICLASS_xt_iclass_bsi8u, 22160 ICLASS_xt_iclass_bst8, 22161 ICLASS_xt_iclass_bsz12, 22162 ICLASS_xt_iclass_call0, 22163 ICLASS_xt_iclass_callx0, 22164 ICLASS_xt_iclass_exti, 22165 ICLASS_xt_iclass_ill, 22166 ICLASS_xt_iclass_jump, 22167 ICLASS_xt_iclass_jumpx, 22168 ICLASS_xt_iclass_l16ui, 22169 ICLASS_xt_iclass_l16si, 22170 ICLASS_xt_iclass_l32i, 22171 ICLASS_xt_iclass_l32r, 22172 ICLASS_xt_iclass_l8i, 22173 ICLASS_xt_iclass_loop, 22174 ICLASS_xt_iclass_loopz, 22175 ICLASS_xt_iclass_movi, 22176 ICLASS_xt_iclass_movz, 22177 ICLASS_xt_iclass_neg, 22178 ICLASS_xt_iclass_nop, 22179 ICLASS_xt_iclass_return, 22180 ICLASS_xt_iclass_simcall, 22181 ICLASS_xt_iclass_s16i, 22182 ICLASS_xt_iclass_s32i, 22183 ICLASS_xt_iclass_s32nb, 22184 ICLASS_xt_iclass_s8i, 22185 ICLASS_xt_iclass_sar, 22186 ICLASS_xt_iclass_sari, 22187 ICLASS_xt_iclass_shifts, 22188 ICLASS_xt_iclass_shiftst, 22189 ICLASS_xt_iclass_shiftt, 22190 ICLASS_xt_iclass_slli, 22191 ICLASS_xt_iclass_srai, 22192 ICLASS_xt_iclass_srli, 22193 ICLASS_xt_iclass_memw, 22194 ICLASS_xt_iclass_extw, 22195 ICLASS_xt_iclass_isync, 22196 ICLASS_xt_iclass_sync, 22197 ICLASS_xt_iclass_rsil, 22198 ICLASS_xt_iclass_rsr_lend, 22199 ICLASS_xt_iclass_wsr_lend, 22200 ICLASS_xt_iclass_xsr_lend, 22201 ICLASS_xt_iclass_rsr_lcount, 22202 ICLASS_xt_iclass_wsr_lcount, 22203 ICLASS_xt_iclass_xsr_lcount, 22204 ICLASS_xt_iclass_rsr_lbeg, 22205 ICLASS_xt_iclass_wsr_lbeg, 22206 ICLASS_xt_iclass_xsr_lbeg, 22207 ICLASS_xt_iclass_rsr_sar, 22208 ICLASS_xt_iclass_wsr_sar, 22209 ICLASS_xt_iclass_xsr_sar, 22210 ICLASS_xt_iclass_rsr_memctl, 22211 ICLASS_xt_iclass_wsr_memctl, 22212 ICLASS_xt_iclass_xsr_memctl, 22213 ICLASS_xt_iclass_rsr_litbase, 22214 ICLASS_xt_iclass_wsr_litbase, 22215 ICLASS_xt_iclass_xsr_litbase, 22216 ICLASS_xt_iclass_rsr_configid0, 22217 ICLASS_xt_iclass_wsr_configid0, 22218 ICLASS_xt_iclass_rsr_configid1, 22219 ICLASS_xt_iclass_rsr_243, 22220 ICLASS_xt_iclass_rsr_ps, 22221 ICLASS_xt_iclass_wsr_ps, 22222 ICLASS_xt_iclass_xsr_ps, 22223 ICLASS_xt_iclass_rsr_epc1, 22224 ICLASS_xt_iclass_wsr_epc1, 22225 ICLASS_xt_iclass_xsr_epc1, 22226 ICLASS_xt_iclass_rsr_excsave1, 22227 ICLASS_xt_iclass_wsr_excsave1, 22228 ICLASS_xt_iclass_xsr_excsave1, 22229 ICLASS_xt_iclass_rsr_epc2, 22230 ICLASS_xt_iclass_wsr_epc2, 22231 ICLASS_xt_iclass_xsr_epc2, 22232 ICLASS_xt_iclass_rsr_excsave2, 22233 ICLASS_xt_iclass_wsr_excsave2, 22234 ICLASS_xt_iclass_xsr_excsave2, 22235 ICLASS_xt_iclass_rsr_epc3, 22236 ICLASS_xt_iclass_wsr_epc3, 22237 ICLASS_xt_iclass_xsr_epc3, 22238 ICLASS_xt_iclass_rsr_excsave3, 22239 ICLASS_xt_iclass_wsr_excsave3, 22240 ICLASS_xt_iclass_xsr_excsave3, 22241 ICLASS_xt_iclass_rsr_epc4, 22242 ICLASS_xt_iclass_wsr_epc4, 22243 ICLASS_xt_iclass_xsr_epc4, 22244 ICLASS_xt_iclass_rsr_excsave4, 22245 ICLASS_xt_iclass_wsr_excsave4, 22246 ICLASS_xt_iclass_xsr_excsave4, 22247 ICLASS_xt_iclass_rsr_epc5, 22248 ICLASS_xt_iclass_wsr_epc5, 22249 ICLASS_xt_iclass_xsr_epc5, 22250 ICLASS_xt_iclass_rsr_excsave5, 22251 ICLASS_xt_iclass_wsr_excsave5, 22252 ICLASS_xt_iclass_xsr_excsave5, 22253 ICLASS_xt_iclass_rsr_epc6, 22254 ICLASS_xt_iclass_wsr_epc6, 22255 ICLASS_xt_iclass_xsr_epc6, 22256 ICLASS_xt_iclass_rsr_excsave6, 22257 ICLASS_xt_iclass_wsr_excsave6, 22258 ICLASS_xt_iclass_xsr_excsave6, 22259 ICLASS_xt_iclass_rsr_epc7, 22260 ICLASS_xt_iclass_wsr_epc7, 22261 ICLASS_xt_iclass_xsr_epc7, 22262 ICLASS_xt_iclass_rsr_excsave7, 22263 ICLASS_xt_iclass_wsr_excsave7, 22264 ICLASS_xt_iclass_xsr_excsave7, 22265 ICLASS_xt_iclass_rsr_eps2, 22266 ICLASS_xt_iclass_wsr_eps2, 22267 ICLASS_xt_iclass_xsr_eps2, 22268 ICLASS_xt_iclass_rsr_eps3, 22269 ICLASS_xt_iclass_wsr_eps3, 22270 ICLASS_xt_iclass_xsr_eps3, 22271 ICLASS_xt_iclass_rsr_eps4, 22272 ICLASS_xt_iclass_wsr_eps4, 22273 ICLASS_xt_iclass_xsr_eps4, 22274 ICLASS_xt_iclass_rsr_eps5, 22275 ICLASS_xt_iclass_wsr_eps5, 22276 ICLASS_xt_iclass_xsr_eps5, 22277 ICLASS_xt_iclass_rsr_eps6, 22278 ICLASS_xt_iclass_wsr_eps6, 22279 ICLASS_xt_iclass_xsr_eps6, 22280 ICLASS_xt_iclass_rsr_eps7, 22281 ICLASS_xt_iclass_wsr_eps7, 22282 ICLASS_xt_iclass_xsr_eps7, 22283 ICLASS_xt_iclass_rsr_excvaddr, 22284 ICLASS_xt_iclass_wsr_excvaddr, 22285 ICLASS_xt_iclass_xsr_excvaddr, 22286 ICLASS_xt_iclass_rsr_depc, 22287 ICLASS_xt_iclass_wsr_depc, 22288 ICLASS_xt_iclass_xsr_depc, 22289 ICLASS_xt_iclass_rsr_exccause, 22290 ICLASS_xt_iclass_wsr_exccause, 22291 ICLASS_xt_iclass_xsr_exccause, 22292 ICLASS_xt_iclass_rsr_misc0, 22293 ICLASS_xt_iclass_wsr_misc0, 22294 ICLASS_xt_iclass_xsr_misc0, 22295 ICLASS_xt_iclass_rsr_misc1, 22296 ICLASS_xt_iclass_wsr_misc1, 22297 ICLASS_xt_iclass_xsr_misc1, 22298 ICLASS_xt_iclass_rsr_prid, 22299 ICLASS_xt_iclass_rsr_vecbase, 22300 ICLASS_xt_iclass_wsr_vecbase, 22301 ICLASS_xt_iclass_xsr_vecbase, 22302 ICLASS_xt_mul16, 22303 ICLASS_xt_mul32, 22304 ICLASS_xt_mul32h, 22305 ICLASS_xt_iclass_mac16_aa, 22306 ICLASS_xt_iclass_mac16_ad, 22307 ICLASS_xt_iclass_mac16_da, 22308 ICLASS_xt_iclass_mac16_dd, 22309 ICLASS_xt_iclass_mac16a_aa, 22310 ICLASS_xt_iclass_mac16a_ad, 22311 ICLASS_xt_iclass_mac16a_da, 22312 ICLASS_xt_iclass_mac16a_dd, 22313 ICLASS_xt_iclass_mac16al_da, 22314 ICLASS_xt_iclass_mac16al_dd, 22315 ICLASS_xt_iclass_mac16_l, 22316 ICLASS_xt_iclass_rsr_m0, 22317 ICLASS_xt_iclass_wsr_m0, 22318 ICLASS_xt_iclass_xsr_m0, 22319 ICLASS_xt_iclass_rsr_m1, 22320 ICLASS_xt_iclass_wsr_m1, 22321 ICLASS_xt_iclass_xsr_m1, 22322 ICLASS_xt_iclass_rsr_m2, 22323 ICLASS_xt_iclass_wsr_m2, 22324 ICLASS_xt_iclass_xsr_m2, 22325 ICLASS_xt_iclass_rsr_m3, 22326 ICLASS_xt_iclass_wsr_m3, 22327 ICLASS_xt_iclass_xsr_m3, 22328 ICLASS_xt_iclass_rsr_acclo, 22329 ICLASS_xt_iclass_wsr_acclo, 22330 ICLASS_xt_iclass_xsr_acclo, 22331 ICLASS_xt_iclass_rsr_acchi, 22332 ICLASS_xt_iclass_wsr_acchi, 22333 ICLASS_xt_iclass_xsr_acchi, 22334 ICLASS_xt_iclass_rfi, 22335 ICLASS_xt_iclass_wait, 22336 ICLASS_xt_iclass_rsr_interrupt, 22337 ICLASS_xt_iclass_wsr_intset, 22338 ICLASS_xt_iclass_wsr_intclear, 22339 ICLASS_xt_iclass_rsr_intenable, 22340 ICLASS_xt_iclass_wsr_intenable, 22341 ICLASS_xt_iclass_xsr_intenable, 22342 ICLASS_xt_iclass_break, 22343 ICLASS_xt_iclass_break_n, 22344 ICLASS_xt_iclass_rsr_dbreaka0, 22345 ICLASS_xt_iclass_wsr_dbreaka0, 22346 ICLASS_xt_iclass_xsr_dbreaka0, 22347 ICLASS_xt_iclass_rsr_dbreakc0, 22348 ICLASS_xt_iclass_wsr_dbreakc0, 22349 ICLASS_xt_iclass_xsr_dbreakc0, 22350 ICLASS_xt_iclass_rsr_dbreaka1, 22351 ICLASS_xt_iclass_wsr_dbreaka1, 22352 ICLASS_xt_iclass_xsr_dbreaka1, 22353 ICLASS_xt_iclass_rsr_dbreakc1, 22354 ICLASS_xt_iclass_wsr_dbreakc1, 22355 ICLASS_xt_iclass_xsr_dbreakc1, 22356 ICLASS_xt_iclass_rsr_ibreaka0, 22357 ICLASS_xt_iclass_wsr_ibreaka0, 22358 ICLASS_xt_iclass_xsr_ibreaka0, 22359 ICLASS_xt_iclass_rsr_ibreaka1, 22360 ICLASS_xt_iclass_wsr_ibreaka1, 22361 ICLASS_xt_iclass_xsr_ibreaka1, 22362 ICLASS_xt_iclass_rsr_ibreakenable, 22363 ICLASS_xt_iclass_wsr_ibreakenable, 22364 ICLASS_xt_iclass_xsr_ibreakenable, 22365 ICLASS_xt_iclass_rsr_debugcause, 22366 ICLASS_xt_iclass_wsr_debugcause, 22367 ICLASS_xt_iclass_xsr_debugcause, 22368 ICLASS_xt_iclass_rsr_icount, 22369 ICLASS_xt_iclass_wsr_icount, 22370 ICLASS_xt_iclass_xsr_icount, 22371 ICLASS_xt_iclass_rsr_icountlevel, 22372 ICLASS_xt_iclass_wsr_icountlevel, 22373 ICLASS_xt_iclass_xsr_icountlevel, 22374 ICLASS_xt_iclass_rsr_ddr, 22375 ICLASS_xt_iclass_wsr_ddr, 22376 ICLASS_xt_iclass_xsr_ddr, 22377 ICLASS_xt_iclass_lddr32_p, 22378 ICLASS_xt_iclass_sddr32_p, 22379 ICLASS_xt_iclass_rfdo, 22380 ICLASS_xt_iclass_rfdd, 22381 ICLASS_xt_iclass_wsr_mmid, 22382 ICLASS_xt_iclass_bbool1, 22383 ICLASS_xt_iclass_bbool4, 22384 ICLASS_xt_iclass_bbool8, 22385 ICLASS_xt_iclass_bbranch, 22386 ICLASS_xt_iclass_bmove, 22387 ICLASS_xt_iclass_RSR_BR, 22388 ICLASS_xt_iclass_WSR_BR, 22389 ICLASS_xt_iclass_XSR_BR, 22390 ICLASS_xt_iclass_rsr_ccount, 22391 ICLASS_xt_iclass_wsr_ccount, 22392 ICLASS_xt_iclass_xsr_ccount, 22393 ICLASS_xt_iclass_rsr_ccompare0, 22394 ICLASS_xt_iclass_wsr_ccompare0, 22395 ICLASS_xt_iclass_xsr_ccompare0, 22396 ICLASS_xt_iclass_rsr_ccompare1, 22397 ICLASS_xt_iclass_wsr_ccompare1, 22398 ICLASS_xt_iclass_xsr_ccompare1, 22399 ICLASS_xt_iclass_rsr_ccompare2, 22400 ICLASS_xt_iclass_wsr_ccompare2, 22401 ICLASS_xt_iclass_xsr_ccompare2, 22402 ICLASS_xt_iclass_icache, 22403 ICLASS_xt_iclass_icache_lock, 22404 ICLASS_xt_iclass_icache_inv, 22405 ICLASS_xt_iclass_licx, 22406 ICLASS_xt_iclass_sicx, 22407 ICLASS_xt_iclass_dcache, 22408 ICLASS_xt_iclass_dcache_dyn, 22409 ICLASS_xt_iclass_dcache_ind, 22410 ICLASS_xt_iclass_dcache_inv, 22411 ICLASS_xt_iclass_dpf, 22412 ICLASS_xt_iclass_dcache_lock, 22413 ICLASS_xt_iclass_sdct, 22414 ICLASS_xt_iclass_ldct, 22415 ICLASS_xt_iclass_rsr_prefctl, 22416 ICLASS_xt_iclass_wsr_prefctl, 22417 ICLASS_xt_iclass_xsr_prefctl, 22418 ICLASS_xt_iclass_wsr_ptevaddr, 22419 ICLASS_xt_iclass_rsr_ptevaddr, 22420 ICLASS_xt_iclass_xsr_ptevaddr, 22421 ICLASS_xt_iclass_rsr_rasid, 22422 ICLASS_xt_iclass_wsr_rasid, 22423 ICLASS_xt_iclass_xsr_rasid, 22424 ICLASS_xt_iclass_rsr_itlbcfg, 22425 ICLASS_xt_iclass_wsr_itlbcfg, 22426 ICLASS_xt_iclass_xsr_itlbcfg, 22427 ICLASS_xt_iclass_rsr_dtlbcfg, 22428 ICLASS_xt_iclass_wsr_dtlbcfg, 22429 ICLASS_xt_iclass_xsr_dtlbcfg, 22430 ICLASS_xt_iclass_idtlb, 22431 ICLASS_xt_iclass_rdtlb, 22432 ICLASS_xt_iclass_wdtlb, 22433 ICLASS_xt_iclass_iitlb, 22434 ICLASS_xt_iclass_ritlb, 22435 ICLASS_xt_iclass_witlb, 22436 ICLASS_xt_iclass_ldpte, 22437 ICLASS_xt_iclass_hwwitlba, 22438 ICLASS_xt_iclass_hwwdtlba, 22439 ICLASS_xt_iclass_rsr_cpenable, 22440 ICLASS_xt_iclass_wsr_cpenable, 22441 ICLASS_xt_iclass_xsr_cpenable, 22442 ICLASS_xt_iclass_clamp, 22443 ICLASS_xt_iclass_minmax, 22444 ICLASS_xt_iclass_nsa, 22445 ICLASS_xt_iclass_sx, 22446 ICLASS_xt_iclass_l32ai, 22447 ICLASS_xt_iclass_s32ri, 22448 ICLASS_xt_iclass_s32c1i, 22449 ICLASS_xt_iclass_rsr_scompare1, 22450 ICLASS_xt_iclass_wsr_scompare1, 22451 ICLASS_xt_iclass_xsr_scompare1, 22452 ICLASS_xt_iclass_rsr_atomctl, 22453 ICLASS_xt_iclass_wsr_atomctl, 22454 ICLASS_xt_iclass_xsr_atomctl, 22455 ICLASS_xt_iclass_div, 22456 ICLASS_xt_iclass_rer, 22457 ICLASS_xt_iclass_wer, 22458 ICLASS_rur_ae_ovf_sar, 22459 ICLASS_wur_ae_ovf_sar, 22460 ICLASS_rur_ae_bithead, 22461 ICLASS_wur_ae_bithead, 22462 ICLASS_rur_ae_ts_fts_bu_bp, 22463 ICLASS_wur_ae_ts_fts_bu_bp, 22464 ICLASS_rur_ae_sd_no, 22465 ICLASS_wur_ae_sd_no, 22466 ICLASS_ae_iclass_rur_ae_overflow, 22467 ICLASS_ae_iclass_wur_ae_overflow, 22468 ICLASS_ae_iclass_rur_ae_sar, 22469 ICLASS_ae_iclass_wur_ae_sar, 22470 ICLASS_ae_iclass_rur_ae_bitptr, 22471 ICLASS_ae_iclass_wur_ae_bitptr, 22472 ICLASS_ae_iclass_rur_ae_bitsused, 22473 ICLASS_ae_iclass_wur_ae_bitsused, 22474 ICLASS_ae_iclass_rur_ae_tablesize, 22475 ICLASS_ae_iclass_wur_ae_tablesize, 22476 ICLASS_ae_iclass_rur_ae_first_ts, 22477 ICLASS_ae_iclass_wur_ae_first_ts, 22478 ICLASS_ae_iclass_rur_ae_nextoffset, 22479 ICLASS_ae_iclass_wur_ae_nextoffset, 22480 ICLASS_ae_iclass_rur_ae_searchdone, 22481 ICLASS_ae_iclass_wur_ae_searchdone, 22482 ICLASS_ae_iclass_lp16f_i, 22483 ICLASS_ae_iclass_lp16f_iu, 22484 ICLASS_ae_iclass_lp16f_x, 22485 ICLASS_ae_iclass_lp16f_xu, 22486 ICLASS_ae_iclass_lp24_i, 22487 ICLASS_ae_iclass_lp24_iu, 22488 ICLASS_ae_iclass_lp24_x, 22489 ICLASS_ae_iclass_lp24_xu, 22490 ICLASS_ae_iclass_lp24f_i, 22491 ICLASS_ae_iclass_lp24f_iu, 22492 ICLASS_ae_iclass_lp24f_x, 22493 ICLASS_ae_iclass_lp24f_xu, 22494 ICLASS_ae_iclass_lp16x2f_i, 22495 ICLASS_ae_iclass_lp16x2f_iu, 22496 ICLASS_ae_iclass_lp16x2f_x, 22497 ICLASS_ae_iclass_lp16x2f_xu, 22498 ICLASS_ae_iclass_lp24x2f_i, 22499 ICLASS_ae_iclass_lp24x2f_iu, 22500 ICLASS_ae_iclass_lp24x2f_x, 22501 ICLASS_ae_iclass_lp24x2f_xu, 22502 ICLASS_ae_iclass_lp24x2_i, 22503 ICLASS_ae_iclass_lp24x2_iu, 22504 ICLASS_ae_iclass_lp24x2_x, 22505 ICLASS_ae_iclass_lp24x2_xu, 22506 ICLASS_ae_iclass_sp16x2f_i, 22507 ICLASS_ae_iclass_sp16x2f_iu, 22508 ICLASS_ae_iclass_sp16x2f_x, 22509 ICLASS_ae_iclass_sp16x2f_xu, 22510 ICLASS_ae_iclass_sp24x2s_i, 22511 ICLASS_ae_iclass_sp24x2s_iu, 22512 ICLASS_ae_iclass_sp24x2s_x, 22513 ICLASS_ae_iclass_sp24x2s_xu, 22514 ICLASS_ae_iclass_sp24x2f_i, 22515 ICLASS_ae_iclass_sp24x2f_iu, 22516 ICLASS_ae_iclass_sp24x2f_x, 22517 ICLASS_ae_iclass_sp24x2f_xu, 22518 ICLASS_ae_iclass_sp16f_l_i, 22519 ICLASS_ae_iclass_sp16f_l_iu, 22520 ICLASS_ae_iclass_sp16f_l_x, 22521 ICLASS_ae_iclass_sp16f_l_xu, 22522 ICLASS_ae_iclass_sp24s_l_i, 22523 ICLASS_ae_iclass_sp24s_l_iu, 22524 ICLASS_ae_iclass_sp24s_l_x, 22525 ICLASS_ae_iclass_sp24s_l_xu, 22526 ICLASS_ae_iclass_sp24f_l_i, 22527 ICLASS_ae_iclass_sp24f_l_iu, 22528 ICLASS_ae_iclass_sp24f_l_x, 22529 ICLASS_ae_iclass_sp24f_l_xu, 22530 ICLASS_ae_iclass_lq56_i, 22531 ICLASS_ae_iclass_lq56_iu, 22532 ICLASS_ae_iclass_lq56_x, 22533 ICLASS_ae_iclass_lq56_xu, 22534 ICLASS_ae_iclass_lq32f_i, 22535 ICLASS_ae_iclass_lq32f_iu, 22536 ICLASS_ae_iclass_lq32f_x, 22537 ICLASS_ae_iclass_lq32f_xu, 22538 ICLASS_ae_iclass_sq56s_i, 22539 ICLASS_ae_iclass_sq56s_iu, 22540 ICLASS_ae_iclass_sq56s_x, 22541 ICLASS_ae_iclass_sq56s_xu, 22542 ICLASS_ae_iclass_sq32f_i, 22543 ICLASS_ae_iclass_sq32f_iu, 22544 ICLASS_ae_iclass_sq32f_x, 22545 ICLASS_ae_iclass_sq32f_xu, 22546 ICLASS_ae_iclass_zerop48, 22547 ICLASS_ae_iclass_movp48, 22548 ICLASS_ae_iclass_selp24_ll, 22549 ICLASS_ae_iclass_selp24_lh, 22550 ICLASS_ae_iclass_selp24_hl, 22551 ICLASS_ae_iclass_selp24_hh, 22552 ICLASS_ae_iclass_movtp24x2, 22553 ICLASS_ae_iclass_movfp24x2, 22554 ICLASS_ae_iclass_movtp48, 22555 ICLASS_ae_iclass_movfp48, 22556 ICLASS_ae_iclass_movpa24x2, 22557 ICLASS_ae_iclass_truncp24a32x2, 22558 ICLASS_ae_iclass_cvta32p24_l, 22559 ICLASS_ae_iclass_cvta32p24_h, 22560 ICLASS_ae_iclass_cvtp24a16x2_ll, 22561 ICLASS_ae_iclass_cvtp24a16x2_lh, 22562 ICLASS_ae_iclass_cvtp24a16x2_hl, 22563 ICLASS_ae_iclass_cvtp24a16x2_hh, 22564 ICLASS_ae_iclass_truncp24q48x2, 22565 ICLASS_ae_iclass_truncp16, 22566 ICLASS_ae_iclass_roundsp24q48sym, 22567 ICLASS_ae_iclass_roundsp24q48asym, 22568 ICLASS_ae_iclass_roundsp16q48sym, 22569 ICLASS_ae_iclass_roundsp16q48asym, 22570 ICLASS_ae_iclass_roundsp16sym, 22571 ICLASS_ae_iclass_roundsp16asym, 22572 ICLASS_ae_iclass_zeroq56, 22573 ICLASS_ae_iclass_movq56, 22574 ICLASS_ae_iclass_movtq56, 22575 ICLASS_ae_iclass_movfq56, 22576 ICLASS_ae_iclass_cvtq48a32s, 22577 ICLASS_ae_iclass_cvtq48p24s_l, 22578 ICLASS_ae_iclass_cvtq48p24s_h, 22579 ICLASS_ae_iclass_satq48s, 22580 ICLASS_ae_iclass_truncq32, 22581 ICLASS_ae_iclass_roundsq32sym, 22582 ICLASS_ae_iclass_roundsq32asym, 22583 ICLASS_ae_iclass_trunca32q48, 22584 ICLASS_ae_iclass_movap24s_l, 22585 ICLASS_ae_iclass_movap24s_h, 22586 ICLASS_ae_iclass_trunca16p24s_l, 22587 ICLASS_ae_iclass_trunca16p24s_h, 22588 ICLASS_ae_iclass_addp24, 22589 ICLASS_ae_iclass_subp24, 22590 ICLASS_ae_iclass_negp24, 22591 ICLASS_ae_iclass_absp24, 22592 ICLASS_ae_iclass_maxp24s, 22593 ICLASS_ae_iclass_minp24s, 22594 ICLASS_ae_iclass_maxbp24s, 22595 ICLASS_ae_iclass_minbp24s, 22596 ICLASS_ae_iclass_addsp24s, 22597 ICLASS_ae_iclass_subsp24s, 22598 ICLASS_ae_iclass_negsp24s, 22599 ICLASS_ae_iclass_abssp24s, 22600 ICLASS_ae_iclass_andp48, 22601 ICLASS_ae_iclass_nandp48, 22602 ICLASS_ae_iclass_orp48, 22603 ICLASS_ae_iclass_xorp48, 22604 ICLASS_ae_iclass_ltp24s, 22605 ICLASS_ae_iclass_lep24s, 22606 ICLASS_ae_iclass_eqp24, 22607 ICLASS_ae_iclass_addq56, 22608 ICLASS_ae_iclass_subq56, 22609 ICLASS_ae_iclass_negq56, 22610 ICLASS_ae_iclass_absq56, 22611 ICLASS_ae_iclass_maxq56s, 22612 ICLASS_ae_iclass_minq56s, 22613 ICLASS_ae_iclass_maxbq56s, 22614 ICLASS_ae_iclass_minbq56s, 22615 ICLASS_ae_iclass_addsq56s, 22616 ICLASS_ae_iclass_subsq56s, 22617 ICLASS_ae_iclass_negsq56s, 22618 ICLASS_ae_iclass_abssq56s, 22619 ICLASS_ae_iclass_andq56, 22620 ICLASS_ae_iclass_nandq56, 22621 ICLASS_ae_iclass_orq56, 22622 ICLASS_ae_iclass_xorq56, 22623 ICLASS_ae_iclass_sllip24, 22624 ICLASS_ae_iclass_srlip24, 22625 ICLASS_ae_iclass_sraip24, 22626 ICLASS_ae_iclass_sllsp24, 22627 ICLASS_ae_iclass_srlsp24, 22628 ICLASS_ae_iclass_srasp24, 22629 ICLASS_ae_iclass_sllisp24s, 22630 ICLASS_ae_iclass_sllssp24s, 22631 ICLASS_ae_iclass_slliq56, 22632 ICLASS_ae_iclass_srliq56, 22633 ICLASS_ae_iclass_sraiq56, 22634 ICLASS_ae_iclass_sllsq56, 22635 ICLASS_ae_iclass_srlsq56, 22636 ICLASS_ae_iclass_srasq56, 22637 ICLASS_ae_iclass_sllaq56, 22638 ICLASS_ae_iclass_srlaq56, 22639 ICLASS_ae_iclass_sraaq56, 22640 ICLASS_ae_iclass_sllisq56s, 22641 ICLASS_ae_iclass_sllssq56s, 22642 ICLASS_ae_iclass_sllasq56s, 22643 ICLASS_ae_iclass_ltq56s, 22644 ICLASS_ae_iclass_leq56s, 22645 ICLASS_ae_iclass_eqq56, 22646 ICLASS_ae_iclass_nsaq56s, 22647 ICLASS_ae_iclass_mulsrfq32sp24s_h, 22648 ICLASS_ae_iclass_mulsrfq32sp24s_l, 22649 ICLASS_ae_iclass_mularfq32sp24s_h, 22650 ICLASS_ae_iclass_mularfq32sp24s_l, 22651 ICLASS_ae_iclass_mulrfq32sp24s_h, 22652 ICLASS_ae_iclass_mulrfq32sp24s_l, 22653 ICLASS_ae_iclass_mulsfq32sp24s_h, 22654 ICLASS_ae_iclass_mulsfq32sp24s_l, 22655 ICLASS_ae_iclass_mulafq32sp24s_h, 22656 ICLASS_ae_iclass_mulafq32sp24s_l, 22657 ICLASS_ae_iclass_mulfq32sp24s_h, 22658 ICLASS_ae_iclass_mulfq32sp24s_l, 22659 ICLASS_ae_iclass_mulfs32p16s_ll, 22660 ICLASS_ae_iclass_mulfp24s_ll, 22661 ICLASS_ae_iclass_mulp24s_ll, 22662 ICLASS_ae_iclass_mulfs32p16s_lh, 22663 ICLASS_ae_iclass_mulfp24s_lh, 22664 ICLASS_ae_iclass_mulp24s_lh, 22665 ICLASS_ae_iclass_mulfs32p16s_hl, 22666 ICLASS_ae_iclass_mulfp24s_hl, 22667 ICLASS_ae_iclass_mulp24s_hl, 22668 ICLASS_ae_iclass_mulfs32p16s_hh, 22669 ICLASS_ae_iclass_mulfp24s_hh, 22670 ICLASS_ae_iclass_mulp24s_hh, 22671 ICLASS_ae_iclass_mulafs32p16s_ll, 22672 ICLASS_ae_iclass_mulafp24s_ll, 22673 ICLASS_ae_iclass_mulap24s_ll, 22674 ICLASS_ae_iclass_mulafs32p16s_lh, 22675 ICLASS_ae_iclass_mulafp24s_lh, 22676 ICLASS_ae_iclass_mulap24s_lh, 22677 ICLASS_ae_iclass_mulafs32p16s_hl, 22678 ICLASS_ae_iclass_mulafp24s_hl, 22679 ICLASS_ae_iclass_mulap24s_hl, 22680 ICLASS_ae_iclass_mulafs32p16s_hh, 22681 ICLASS_ae_iclass_mulafp24s_hh, 22682 ICLASS_ae_iclass_mulap24s_hh, 22683 ICLASS_ae_iclass_mulsfs32p16s_ll, 22684 ICLASS_ae_iclass_mulsfp24s_ll, 22685 ICLASS_ae_iclass_mulsp24s_ll, 22686 ICLASS_ae_iclass_mulsfs32p16s_lh, 22687 ICLASS_ae_iclass_mulsfp24s_lh, 22688 ICLASS_ae_iclass_mulsp24s_lh, 22689 ICLASS_ae_iclass_mulsfs32p16s_hl, 22690 ICLASS_ae_iclass_mulsfp24s_hl, 22691 ICLASS_ae_iclass_mulsp24s_hl, 22692 ICLASS_ae_iclass_mulsfs32p16s_hh, 22693 ICLASS_ae_iclass_mulsfp24s_hh, 22694 ICLASS_ae_iclass_mulsp24s_hh, 22695 ICLASS_ae_iclass_mulafs56p24s_ll, 22696 ICLASS_ae_iclass_mulas56p24s_ll, 22697 ICLASS_ae_iclass_mulafs56p24s_lh, 22698 ICLASS_ae_iclass_mulas56p24s_lh, 22699 ICLASS_ae_iclass_mulafs56p24s_hl, 22700 ICLASS_ae_iclass_mulas56p24s_hl, 22701 ICLASS_ae_iclass_mulafs56p24s_hh, 22702 ICLASS_ae_iclass_mulas56p24s_hh, 22703 ICLASS_ae_iclass_mulsfs56p24s_ll, 22704 ICLASS_ae_iclass_mulss56p24s_ll, 22705 ICLASS_ae_iclass_mulsfs56p24s_lh, 22706 ICLASS_ae_iclass_mulss56p24s_lh, 22707 ICLASS_ae_iclass_mulsfs56p24s_hl, 22708 ICLASS_ae_iclass_mulss56p24s_hl, 22709 ICLASS_ae_iclass_mulsfs56p24s_hh, 22710 ICLASS_ae_iclass_mulss56p24s_hh, 22711 ICLASS_ae_iclass_mulfq32sp16s_l, 22712 ICLASS_ae_iclass_mulfq32sp16s_h, 22713 ICLASS_ae_iclass_mulfq32sp16u_l, 22714 ICLASS_ae_iclass_mulfq32sp16u_h, 22715 ICLASS_ae_iclass_mulq32sp16s_l, 22716 ICLASS_ae_iclass_mulq32sp16s_h, 22717 ICLASS_ae_iclass_mulq32sp16u_l, 22718 ICLASS_ae_iclass_mulq32sp16u_h, 22719 ICLASS_ae_iclass_mulafq32sp16s_l, 22720 ICLASS_ae_iclass_mulafq32sp16s_h, 22721 ICLASS_ae_iclass_mulafq32sp16u_l, 22722 ICLASS_ae_iclass_mulafq32sp16u_h, 22723 ICLASS_ae_iclass_mulaq32sp16s_l, 22724 ICLASS_ae_iclass_mulaq32sp16s_h, 22725 ICLASS_ae_iclass_mulaq32sp16u_l, 22726 ICLASS_ae_iclass_mulaq32sp16u_h, 22727 ICLASS_ae_iclass_mulsfq32sp16s_l, 22728 ICLASS_ae_iclass_mulsfq32sp16s_h, 22729 ICLASS_ae_iclass_mulsfq32sp16u_l, 22730 ICLASS_ae_iclass_mulsfq32sp16u_h, 22731 ICLASS_ae_iclass_mulsq32sp16s_l, 22732 ICLASS_ae_iclass_mulsq32sp16s_h, 22733 ICLASS_ae_iclass_mulsq32sp16u_l, 22734 ICLASS_ae_iclass_mulsq32sp16u_h, 22735 ICLASS_ae_iclass_mulzaaq32sp16s_ll, 22736 ICLASS_ae_iclass_mulzaafq32sp16s_ll, 22737 ICLASS_ae_iclass_mulzaaq32sp16u_ll, 22738 ICLASS_ae_iclass_mulzaafq32sp16u_ll, 22739 ICLASS_ae_iclass_mulzaaq32sp16s_hh, 22740 ICLASS_ae_iclass_mulzaafq32sp16s_hh, 22741 ICLASS_ae_iclass_mulzaaq32sp16u_hh, 22742 ICLASS_ae_iclass_mulzaafq32sp16u_hh, 22743 ICLASS_ae_iclass_mulzaaq32sp16s_lh, 22744 ICLASS_ae_iclass_mulzaafq32sp16s_lh, 22745 ICLASS_ae_iclass_mulzaaq32sp16u_lh, 22746 ICLASS_ae_iclass_mulzaafq32sp16u_lh, 22747 ICLASS_ae_iclass_mulzasq32sp16s_ll, 22748 ICLASS_ae_iclass_mulzasfq32sp16s_ll, 22749 ICLASS_ae_iclass_mulzasq32sp16u_ll, 22750 ICLASS_ae_iclass_mulzasfq32sp16u_ll, 22751 ICLASS_ae_iclass_mulzasq32sp16s_hh, 22752 ICLASS_ae_iclass_mulzasfq32sp16s_hh, 22753 ICLASS_ae_iclass_mulzasq32sp16u_hh, 22754 ICLASS_ae_iclass_mulzasfq32sp16u_hh, 22755 ICLASS_ae_iclass_mulzasq32sp16s_lh, 22756 ICLASS_ae_iclass_mulzasfq32sp16s_lh, 22757 ICLASS_ae_iclass_mulzasq32sp16u_lh, 22758 ICLASS_ae_iclass_mulzasfq32sp16u_lh, 22759 ICLASS_ae_iclass_mulzsaq32sp16s_ll, 22760 ICLASS_ae_iclass_mulzsafq32sp16s_ll, 22761 ICLASS_ae_iclass_mulzsaq32sp16u_ll, 22762 ICLASS_ae_iclass_mulzsafq32sp16u_ll, 22763 ICLASS_ae_iclass_mulzsaq32sp16s_hh, 22764 ICLASS_ae_iclass_mulzsafq32sp16s_hh, 22765 ICLASS_ae_iclass_mulzsaq32sp16u_hh, 22766 ICLASS_ae_iclass_mulzsafq32sp16u_hh, 22767 ICLASS_ae_iclass_mulzsaq32sp16s_lh, 22768 ICLASS_ae_iclass_mulzsafq32sp16s_lh, 22769 ICLASS_ae_iclass_mulzsaq32sp16u_lh, 22770 ICLASS_ae_iclass_mulzsafq32sp16u_lh, 22771 ICLASS_ae_iclass_mulzssq32sp16s_ll, 22772 ICLASS_ae_iclass_mulzssfq32sp16s_ll, 22773 ICLASS_ae_iclass_mulzssq32sp16u_ll, 22774 ICLASS_ae_iclass_mulzssfq32sp16u_ll, 22775 ICLASS_ae_iclass_mulzssq32sp16s_hh, 22776 ICLASS_ae_iclass_mulzssfq32sp16s_hh, 22777 ICLASS_ae_iclass_mulzssq32sp16u_hh, 22778 ICLASS_ae_iclass_mulzssfq32sp16u_hh, 22779 ICLASS_ae_iclass_mulzssq32sp16s_lh, 22780 ICLASS_ae_iclass_mulzssfq32sp16s_lh, 22781 ICLASS_ae_iclass_mulzssq32sp16u_lh, 22782 ICLASS_ae_iclass_mulzssfq32sp16u_lh, 22783 ICLASS_ae_iclass_mulzaafp24s_hh_ll, 22784 ICLASS_ae_iclass_mulzaap24s_hh_ll, 22785 ICLASS_ae_iclass_mulzaafp24s_hl_lh, 22786 ICLASS_ae_iclass_mulzaap24s_hl_lh, 22787 ICLASS_ae_iclass_mulzasfp24s_hh_ll, 22788 ICLASS_ae_iclass_mulzasp24s_hh_ll, 22789 ICLASS_ae_iclass_mulzasfp24s_hl_lh, 22790 ICLASS_ae_iclass_mulzasp24s_hl_lh, 22791 ICLASS_ae_iclass_mulzsafp24s_hh_ll, 22792 ICLASS_ae_iclass_mulzsap24s_hh_ll, 22793 ICLASS_ae_iclass_mulzsafp24s_hl_lh, 22794 ICLASS_ae_iclass_mulzsap24s_hl_lh, 22795 ICLASS_ae_iclass_mulzssfp24s_hh_ll, 22796 ICLASS_ae_iclass_mulzssp24s_hh_ll, 22797 ICLASS_ae_iclass_mulzssfp24s_hl_lh, 22798 ICLASS_ae_iclass_mulzssp24s_hl_lh, 22799 ICLASS_ae_iclass_mulaafp24s_hh_ll, 22800 ICLASS_ae_iclass_mulaap24s_hh_ll, 22801 ICLASS_ae_iclass_mulaafp24s_hl_lh, 22802 ICLASS_ae_iclass_mulaap24s_hl_lh, 22803 ICLASS_ae_iclass_mulasfp24s_hh_ll, 22804 ICLASS_ae_iclass_mulasp24s_hh_ll, 22805 ICLASS_ae_iclass_mulasfp24s_hl_lh, 22806 ICLASS_ae_iclass_mulasp24s_hl_lh, 22807 ICLASS_ae_iclass_mulsafp24s_hh_ll, 22808 ICLASS_ae_iclass_mulsap24s_hh_ll, 22809 ICLASS_ae_iclass_mulsafp24s_hl_lh, 22810 ICLASS_ae_iclass_mulsap24s_hl_lh, 22811 ICLASS_ae_iclass_mulssfp24s_hh_ll, 22812 ICLASS_ae_iclass_mulssp24s_hh_ll, 22813 ICLASS_ae_iclass_mulssfp24s_hl_lh, 22814 ICLASS_ae_iclass_mulssp24s_hl_lh, 22815 ICLASS_ae_iclass_sha32, 22816 ICLASS_ae_iclass_vldl32t, 22817 ICLASS_ae_iclass_vldl16t, 22818 ICLASS_ae_iclass_vldl16c, 22819 ICLASS_ae_iclass_vldsht, 22820 ICLASS_ae_iclass_lb, 22821 ICLASS_ae_iclass_lbi, 22822 ICLASS_ae_iclass_lbk, 22823 ICLASS_ae_iclass_lbki, 22824 ICLASS_ae_iclass_db, 22825 ICLASS_ae_iclass_dbi, 22826 ICLASS_ae_iclass_vlel32t, 22827 ICLASS_ae_iclass_vlel16t, 22828 ICLASS_ae_iclass_sb, 22829 ICLASS_ae_iclass_sbi, 22830 ICLASS_ae_iclass_vles16c, 22831 ICLASS_ae_iclass_sbf, 22832 ICLASS_icls_AE_SLAASQ56S, 22833 ICLASS_icls_AE_ADDBRBA32, 22834 ICLASS_icls_AE_MINABSSP24S, 22835 ICLASS_icls_AE_MAXABSSP24S, 22836 ICLASS_icls_AE_MINABSSQ56S, 22837 ICLASS_icls_AE_MAXABSSQ56S, 22838 ICLASS_rur_ae_cbegin0, 22839 ICLASS_wur_ae_cbegin0, 22840 ICLASS_rur_ae_cend0, 22841 ICLASS_wur_ae_cend0, 22842 ICLASS_icls_AE_LP24X2_C, 22843 ICLASS_icls_AE_SP24X2S_C, 22844 ICLASS_icls_AE_LP24X2F_C, 22845 ICLASS_icls_AE_SP24X2F_C, 22846 ICLASS_icls_AE_LP16X2F_C, 22847 ICLASS_icls_AE_SP16X2F_C, 22848 ICLASS_icls_AE_LP24_C, 22849 ICLASS_icls_AE_SP24S_L_C, 22850 ICLASS_icls_AE_LP24F_C, 22851 ICLASS_icls_AE_SP24F_L_C, 22852 ICLASS_icls_AE_LP16F_C, 22853 ICLASS_icls_AE_SP16F_L_C, 22854 ICLASS_icls_AE_LQ56_C, 22855 ICLASS_icls_AE_SQ56S_C, 22856 ICLASS_icls_AE_LQ32F_C, 22857 ICLASS_icls_AE_SQ32F_C, 22858 ICLASS_rur_expstate, 22859 ICLASS_wur_expstate, 22860 ICLASS_iclass_READ_IMPWIRE, 22861 ICLASS_iclass_SETB_EXPSTATE, 22862 ICLASS_iclass_CLRB_EXPSTATE, 22863 ICLASS_iclass_WRMSK_EXPSTATE 22864 }; 22865 22866 22867 /* Opcode encodings. */ 22868 22869 static void 22870 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf) 22871 { 22872 slotbuf[0] = 0x80200; 22873 } 22874 22875 static void 22876 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf) 22877 { 22878 slotbuf[0] = 0x300; 22879 } 22880 22881 static void 22882 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf) 22883 { 22884 slotbuf[0] = 0x2300; 22885 } 22886 22887 static void 22888 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf) 22889 { 22890 slotbuf[0] = 0x500; 22891 } 22892 22893 static void 22894 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf) 22895 { 22896 slotbuf[0] = 0x5c0000; 22897 } 22898 22899 static void 22900 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf) 22901 { 22902 slotbuf[0] = 0x580000; 22903 } 22904 22905 static void 22906 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf) 22907 { 22908 slotbuf[0] = 0x540000; 22909 } 22910 22911 static void 22912 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf) 22913 { 22914 slotbuf[0] = 0xf0000; 22915 } 22916 22917 static void 22918 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 22919 { 22920 slotbuf[0] = 0xb0000; 22921 } 22922 22923 static void 22924 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 22925 { 22926 slotbuf[0] = 0x70000; 22927 } 22928 22929 static void 22930 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf) 22931 { 22932 slotbuf[0] = 0x6c0000; 22933 } 22934 22935 static void 22936 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf) 22937 { 22938 slotbuf[0] = 0x100; 22939 } 22940 22941 static void 22942 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf) 22943 { 22944 slotbuf[0] = 0x804; 22945 } 22946 22947 static void 22948 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf) 22949 { 22950 slotbuf[0] = 0x60000; 22951 } 22952 22953 static void 22954 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 22955 { 22956 slotbuf[0] = 0xd10f; 22957 } 22958 22959 static void 22960 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 22961 { 22962 slotbuf[0] = 0x4300; 22963 } 22964 22965 static void 22966 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf) 22967 { 22968 slotbuf[0] = 0x5300; 22969 } 22970 22971 static void 22972 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 22973 { 22974 slotbuf[0] = 0x90; 22975 } 22976 22977 static void 22978 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf) 22979 { 22980 slotbuf[0] = 0x94; 22981 } 22982 22983 static void 22984 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 22985 { 22986 slotbuf[0] = 0x4830; 22987 } 22988 22989 static void 22990 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 22991 { 22992 slotbuf[0] = 0x4831; 22993 } 22994 22995 static void 22996 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 22997 { 22998 slotbuf[0] = 0x4816; 22999 } 23000 23001 static void 23002 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 23003 { 23004 slotbuf[0] = 0x4930; 23005 } 23006 23007 static void 23008 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 23009 { 23010 slotbuf[0] = 0x4931; 23011 } 23012 23013 static void 23014 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf) 23015 { 23016 slotbuf[0] = 0x4916; 23017 } 23018 23019 static void 23020 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 23021 { 23022 slotbuf[0] = 0xa000; 23023 } 23024 23025 static void 23026 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 23027 { 23028 slotbuf[0] = 0xb000; 23029 } 23030 23031 static void 23032 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23033 { 23034 slotbuf[0] = 0xc800; 23035 } 23036 23037 static void 23038 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23039 { 23040 slotbuf[0] = 0xcc00; 23041 } 23042 23043 static void 23044 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23045 { 23046 slotbuf[0] = 0xd60f; 23047 } 23048 23049 static void 23050 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 23051 { 23052 slotbuf[0] = 0x8000; 23053 } 23054 23055 static void 23056 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23057 { 23058 slotbuf[0] = 0xd000; 23059 } 23060 23061 static void 23062 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23063 { 23064 slotbuf[0] = 0xc000; 23065 } 23066 23067 static void 23068 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23069 { 23070 slotbuf[0] = 0xd30f; 23071 } 23072 23073 static void 23074 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 23075 { 23076 slotbuf[0] = 0xd00f; 23077 } 23078 23079 static void 23080 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf) 23081 { 23082 slotbuf[0] = 0x9000; 23083 } 23084 23085 static void 23086 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 23087 { 23088 slotbuf[0] = 0x7e03e; 23089 } 23090 23091 static void 23092 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 23093 { 23094 slotbuf[0] = 0xe73f; 23095 } 23096 23097 static void 23098 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf) 23099 { 23100 slotbuf[0] = 0x200c00; 23101 } 23102 23103 static void 23104 Opcode_addi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23105 { 23106 slotbuf[0] = 0x100002; 23107 } 23108 23109 static void 23110 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf) 23111 { 23112 slotbuf[0] = 0x200d00; 23113 } 23114 23115 static void 23116 Opcode_addmi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23117 { 23118 slotbuf[0] = 0x200002; 23119 } 23120 23121 static void 23122 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf) 23123 { 23124 slotbuf[0] = 0x8; 23125 } 23126 23127 static void 23128 Opcode_add_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23129 { 23130 slotbuf[0] = 0xb81; 23131 } 23132 23133 static void 23134 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf) 23135 { 23136 slotbuf[0] = 0xc; 23137 } 23138 23139 static void 23140 Opcode_sub_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23141 { 23142 slotbuf[0] = 0xf01; 23143 } 23144 23145 static void 23146 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 23147 { 23148 slotbuf[0] = 0x9; 23149 } 23150 23151 static void 23152 Opcode_addx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23153 { 23154 slotbuf[0] = 0x1381; 23155 } 23156 23157 static void 23158 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 23159 { 23160 slotbuf[0] = 0xa; 23161 } 23162 23163 static void 23164 Opcode_addx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23165 { 23166 slotbuf[0] = 0x2381; 23167 } 23168 23169 static void 23170 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 23171 { 23172 slotbuf[0] = 0xb; 23173 } 23174 23175 static void 23176 Opcode_addx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23177 { 23178 slotbuf[0] = 0x4b81; 23179 } 23180 23181 static void 23182 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf) 23183 { 23184 slotbuf[0] = 0xd; 23185 } 23186 23187 static void 23188 Opcode_subx2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23189 { 23190 slotbuf[0] = 0x4d01; 23191 } 23192 23193 static void 23194 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf) 23195 { 23196 slotbuf[0] = 0xe; 23197 } 23198 23199 static void 23200 Opcode_subx4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23201 { 23202 slotbuf[0] = 0xf81; 23203 } 23204 23205 static void 23206 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf) 23207 { 23208 slotbuf[0] = 0xf; 23209 } 23210 23211 static void 23212 Opcode_subx8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23213 { 23214 slotbuf[0] = 0x4d81; 23215 } 23216 23217 static void 23218 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf) 23219 { 23220 slotbuf[0] = 0x1; 23221 } 23222 23223 static void 23224 Opcode_and_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23225 { 23226 slotbuf[0] = 0x1b81; 23227 } 23228 23229 static void 23230 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf) 23231 { 23232 slotbuf[0] = 0x2; 23233 } 23234 23235 static void 23236 Opcode_or_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23237 { 23238 slotbuf[0] = 0x2501; 23239 } 23240 23241 static void 23242 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf) 23243 { 23244 slotbuf[0] = 0x3; 23245 } 23246 23247 static void 23248 Opcode_xor_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23249 { 23250 slotbuf[0] = 0x4f01; 23251 } 23252 23253 static void 23254 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf) 23255 { 23256 slotbuf[0] = 0x680000; 23257 } 23258 23259 static void 23260 Opcode_beqi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23261 { 23262 slotbuf[0] = 0x3; 23263 } 23264 23265 static void 23266 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf) 23267 { 23268 slotbuf[0] = 0x690000; 23269 } 23270 23271 static void 23272 Opcode_bnei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23273 { 23274 slotbuf[0] = 0x1800003; 23275 } 23276 23277 static void 23278 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf) 23279 { 23280 slotbuf[0] = 0x6b0000; 23281 } 23282 23283 static void 23284 Opcode_bgei_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23285 { 23286 slotbuf[0] = 0x800003; 23287 } 23288 23289 static void 23290 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf) 23291 { 23292 slotbuf[0] = 0x6a0000; 23293 } 23294 23295 static void 23296 Opcode_blti_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23297 { 23298 slotbuf[0] = 0x2000003; 23299 } 23300 23301 static void 23302 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf) 23303 { 23304 slotbuf[0] = 0x700600; 23305 } 23306 23307 static void 23308 Opcode_bbci_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23309 { 23310 slotbuf[0] = 0x2; 23311 } 23312 23313 static void 23314 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf) 23315 { 23316 slotbuf[0] = 0x700e00; 23317 } 23318 23319 static void 23320 Opcode_bbsi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23321 { 23322 slotbuf[0] = 0x80002; 23323 } 23324 23325 static void 23326 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf) 23327 { 23328 slotbuf[0] = 0x6f0000; 23329 } 23330 23331 static void 23332 Opcode_bgeui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23333 { 23334 slotbuf[0] = 0x1000003; 23335 } 23336 23337 static void 23338 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf) 23339 { 23340 slotbuf[0] = 0x6e0000; 23341 } 23342 23343 static void 23344 Opcode_bltui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23345 { 23346 slotbuf[0] = 0x4000003; 23347 } 23348 23349 static void 23350 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf) 23351 { 23352 slotbuf[0] = 0x700100; 23353 } 23354 23355 static void 23356 Opcode_beq_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23357 { 23358 slotbuf[0] = 0x300002; 23359 } 23360 23361 static void 23362 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf) 23363 { 23364 slotbuf[0] = 0x700900; 23365 } 23366 23367 static void 23368 Opcode_bne_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23369 { 23370 slotbuf[0] = 0x4; 23371 } 23372 23373 static void 23374 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf) 23375 { 23376 slotbuf[0] = 0x700a00; 23377 } 23378 23379 static void 23380 Opcode_bge_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23381 { 23382 slotbuf[0] = 0x600002; 23383 } 23384 23385 static void 23386 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf) 23387 { 23388 slotbuf[0] = 0x700200; 23389 } 23390 23391 static void 23392 Opcode_blt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23393 { 23394 slotbuf[0] = 0x680002; 23395 } 23396 23397 static void 23398 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf) 23399 { 23400 slotbuf[0] = 0x700b00; 23401 } 23402 23403 static void 23404 Opcode_bgeu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23405 { 23406 slotbuf[0] = 0x380002; 23407 } 23408 23409 static void 23410 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf) 23411 { 23412 slotbuf[0] = 0x700300; 23413 } 23414 23415 static void 23416 Opcode_bltu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23417 { 23418 slotbuf[0] = 0x700002; 23419 } 23420 23421 static void 23422 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf) 23423 { 23424 slotbuf[0] = 0x700800; 23425 } 23426 23427 static void 23428 Opcode_bany_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23429 { 23430 slotbuf[0] = 0x500002; 23431 } 23432 23433 static void 23434 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf) 23435 { 23436 slotbuf[0] = 0x700000; 23437 } 23438 23439 static void 23440 Opcode_bnone_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23441 { 23442 slotbuf[0] = 0x80004; 23443 } 23444 23445 static void 23446 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf) 23447 { 23448 slotbuf[0] = 0x700400; 23449 } 23450 23451 static void 23452 Opcode_ball_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23453 { 23454 slotbuf[0] = 0x180002; 23455 } 23456 23457 static void 23458 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf) 23459 { 23460 slotbuf[0] = 0x700c00; 23461 } 23462 23463 static void 23464 Opcode_bnall_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23465 { 23466 slotbuf[0] = 0x780002; 23467 } 23468 23469 static void 23470 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 23471 { 23472 slotbuf[0] = 0x700500; 23473 } 23474 23475 static void 23476 Opcode_bbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23477 { 23478 slotbuf[0] = 0x580002; 23479 } 23480 23481 static void 23482 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf) 23483 { 23484 slotbuf[0] = 0x700d00; 23485 } 23486 23487 static void 23488 Opcode_bbs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23489 { 23490 slotbuf[0] = 0x280002; 23491 } 23492 23493 static void 23494 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 23495 { 23496 slotbuf[0] = 0x640000; 23497 } 23498 23499 static void 23500 Opcode_beqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23501 { 23502 slotbuf[0] = 0x101; 23503 } 23504 23505 static void 23506 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 23507 { 23508 slotbuf[0] = 0x650000; 23509 } 23510 23511 static void 23512 Opcode_bnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23513 { 23514 slotbuf[0] = 0x181; 23515 } 23516 23517 static void 23518 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 23519 { 23520 slotbuf[0] = 0x670000; 23521 } 23522 23523 static void 23524 Opcode_bgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23525 { 23526 slotbuf[0] = 0x281; 23527 } 23528 23529 static void 23530 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 23531 { 23532 slotbuf[0] = 0x660000; 23533 } 23534 23535 static void 23536 Opcode_bltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23537 { 23538 slotbuf[0] = 0x681; 23539 } 23540 23541 static void 23542 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf) 23543 { 23544 slotbuf[0] = 0x500000; 23545 } 23546 23547 static void 23548 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf) 23549 { 23550 slotbuf[0] = 0x30000; 23551 } 23552 23553 static void 23554 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf) 23555 { 23556 slotbuf[0] = 0x40; 23557 } 23558 23559 static void 23560 Opcode_extui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23561 { 23562 slotbuf[0] = 0x81; 23563 } 23564 23565 static void 23566 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf) 23567 { 23568 slotbuf[0] = 0; 23569 } 23570 23571 static void 23572 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf) 23573 { 23574 slotbuf[0] = 0x600000; 23575 } 23576 23577 static void 23578 Opcode_j_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23579 { 23580 slotbuf[0] = 0x1; 23581 } 23582 23583 static void 23584 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf) 23585 { 23586 slotbuf[0] = 0xa0000; 23587 } 23588 23589 static void 23590 Opcode_jx_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23591 { 23592 slotbuf[0] = 0x983d01; 23593 } 23594 23595 static void 23596 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 23597 { 23598 slotbuf[0] = 0x200100; 23599 } 23600 23601 static void 23602 Opcode_l16ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23603 { 23604 slotbuf[0] = 0x200004; 23605 } 23606 23607 static void 23608 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf) 23609 { 23610 slotbuf[0] = 0x200900; 23611 } 23612 23613 static void 23614 Opcode_l16si_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23615 { 23616 slotbuf[0] = 0x100004; 23617 } 23618 23619 static void 23620 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 23621 { 23622 slotbuf[0] = 0x200200; 23623 } 23624 23625 static void 23626 Opcode_l32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23627 { 23628 slotbuf[0] = 0x400004; 23629 } 23630 23631 static void 23632 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf) 23633 { 23634 slotbuf[0] = 0x100000; 23635 } 23636 23637 static void 23638 Opcode_l32r_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23639 { 23640 slotbuf[0] = 0x5; 23641 } 23642 23643 static void 23644 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf) 23645 { 23646 slotbuf[0] = 0x200000; 23647 } 23648 23649 static void 23650 Opcode_l8ui_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23651 { 23652 slotbuf[0] = 0x180004; 23653 } 23654 23655 static void 23656 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf) 23657 { 23658 slotbuf[0] = 0x6d0800; 23659 } 23660 23661 static void 23662 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 23663 { 23664 slotbuf[0] = 0x6d0900; 23665 } 23666 23667 static void 23668 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf) 23669 { 23670 slotbuf[0] = 0x6d0a00; 23671 } 23672 23673 static void 23674 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf) 23675 { 23676 slotbuf[0] = 0x200a00; 23677 } 23678 23679 static void 23680 Opcode_movi_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23681 { 23682 slotbuf[0] = 0x301; 23683 } 23684 23685 static void 23686 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf) 23687 { 23688 slotbuf[0] = 0x38; 23689 } 23690 23691 static void 23692 Opcode_moveqz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23693 { 23694 slotbuf[0] = 0x7381; 23695 } 23696 23697 static void 23698 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf) 23699 { 23700 slotbuf[0] = 0x39; 23701 } 23702 23703 static void 23704 Opcode_movnez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23705 { 23706 slotbuf[0] = 0xd01; 23707 } 23708 23709 static void 23710 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf) 23711 { 23712 slotbuf[0] = 0x3a; 23713 } 23714 23715 static void 23716 Opcode_movltz_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23717 { 23718 slotbuf[0] = 0x701; 23719 } 23720 23721 static void 23722 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf) 23723 { 23724 slotbuf[0] = 0x3b; 23725 } 23726 23727 static void 23728 Opcode_movgez_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23729 { 23730 slotbuf[0] = 0x581; 23731 } 23732 23733 static void 23734 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf) 23735 { 23736 slotbuf[0] = 0x6; 23737 } 23738 23739 static void 23740 Opcode_neg_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23741 { 23742 slotbuf[0] = 0x3ed81; 23743 } 23744 23745 static void 23746 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf) 23747 { 23748 slotbuf[0] = 0x1006; 23749 } 23750 23751 static void 23752 Opcode_abs_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23753 { 23754 slotbuf[0] = 0x1ed81; 23755 } 23756 23757 static void 23758 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf) 23759 { 23760 slotbuf[0] = 0xf0200; 23761 } 23762 23763 static void 23764 Opcode_nop_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 23765 { 23766 slotbuf[0] = 0x36001; 23767 } 23768 23769 static void 23770 Opcode_nop_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23771 { 23772 slotbuf[0] = 0xb83d01; 23773 } 23774 23775 static void 23776 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf) 23777 { 23778 slotbuf[0] = 0x20000; 23779 } 23780 23781 static void 23782 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf) 23783 { 23784 slotbuf[0] = 0x1500; 23785 } 23786 23787 static void 23788 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf) 23789 { 23790 slotbuf[0] = 0x200500; 23791 } 23792 23793 static void 23794 Opcode_s16i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23795 { 23796 slotbuf[0] = 0x280004; 23797 } 23798 23799 static void 23800 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf) 23801 { 23802 slotbuf[0] = 0x200600; 23803 } 23804 23805 static void 23806 Opcode_s32i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23807 { 23808 slotbuf[0] = 0x300004; 23809 } 23810 23811 static void 23812 Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf) 23813 { 23814 slotbuf[0] = 0x95; 23815 } 23816 23817 static void 23818 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf) 23819 { 23820 slotbuf[0] = 0x200400; 23821 } 23822 23823 static void 23824 Opcode_s8i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23825 { 23826 slotbuf[0] = 0x380004; 23827 } 23828 23829 static void 23830 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf) 23831 { 23832 slotbuf[0] = 0x4; 23833 } 23834 23835 static void 23836 Opcode_ssr_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23837 { 23838 slotbuf[0] = 0x983d81; 23839 } 23840 23841 static void 23842 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf) 23843 { 23844 slotbuf[0] = 0x104; 23845 } 23846 23847 static void 23848 Opcode_ssl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23849 { 23850 slotbuf[0] = 0x4183d01; 23851 } 23852 23853 static void 23854 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf) 23855 { 23856 slotbuf[0] = 0x204; 23857 } 23858 23859 static void 23860 Opcode_ssa8l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23861 { 23862 slotbuf[0] = 0x2183d01; 23863 } 23864 23865 static void 23866 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf) 23867 { 23868 slotbuf[0] = 0x304; 23869 } 23870 23871 static void 23872 Opcode_ssa8b_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23873 { 23874 slotbuf[0] = 0x1183d01; 23875 } 23876 23877 static void 23878 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf) 23879 { 23880 slotbuf[0] = 0x404; 23881 } 23882 23883 static void 23884 Opcode_ssai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23885 { 23886 slotbuf[0] = 0x18e501; 23887 } 23888 23889 static void 23890 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf) 23891 { 23892 slotbuf[0] = 0x1a; 23893 } 23894 23895 static void 23896 Opcode_sll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23897 { 23898 slotbuf[0] = 0x2806f81; 23899 } 23900 23901 static void 23902 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf) 23903 { 23904 slotbuf[0] = 0x18; 23905 } 23906 23907 static void 23908 Opcode_src_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23909 { 23910 slotbuf[0] = 0x4781; 23911 } 23912 23913 static void 23914 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf) 23915 { 23916 slotbuf[0] = 0x19; 23917 } 23918 23919 static void 23920 Opcode_srl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23921 { 23922 slotbuf[0] = 0x7ed81; 23923 } 23924 23925 static void 23926 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf) 23927 { 23928 slotbuf[0] = 0x1b; 23929 } 23930 23931 static void 23932 Opcode_sra_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23933 { 23934 slotbuf[0] = 0x5ed81; 23935 } 23936 23937 static void 23938 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf) 23939 { 23940 slotbuf[0] = 0x10; 23941 } 23942 23943 static void 23944 Opcode_slli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23945 { 23946 slotbuf[0] = 0x501; 23947 } 23948 23949 static void 23950 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf) 23951 { 23952 slotbuf[0] = 0x12; 23953 } 23954 23955 static void 23956 Opcode_srai_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23957 { 23958 slotbuf[0] = 0x381; 23959 } 23960 23961 static void 23962 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf) 23963 { 23964 slotbuf[0] = 0x14; 23965 } 23966 23967 static void 23968 Opcode_srli_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 23969 { 23970 slotbuf[0] = 0xd81; 23971 } 23972 23973 static void 23974 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf) 23975 { 23976 slotbuf[0] = 0xc0200; 23977 } 23978 23979 static void 23980 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf) 23981 { 23982 slotbuf[0] = 0xd0200; 23983 } 23984 23985 static void 23986 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf) 23987 { 23988 slotbuf[0] = 0x200; 23989 } 23990 23991 static void 23992 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 23993 { 23994 slotbuf[0] = 0x10200; 23995 } 23996 23997 static void 23998 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf) 23999 { 24000 slotbuf[0] = 0x20200; 24001 } 24002 24003 static void 24004 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf) 24005 { 24006 slotbuf[0] = 0x30200; 24007 } 24008 24009 static void 24010 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf) 24011 { 24012 slotbuf[0] = 0x600; 24013 } 24014 24015 static void 24016 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 24017 { 24018 slotbuf[0] = 0x130; 24019 } 24020 24021 static void 24022 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 24023 { 24024 slotbuf[0] = 0x131; 24025 } 24026 24027 static void 24028 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf) 24029 { 24030 slotbuf[0] = 0x116; 24031 } 24032 24033 static void 24034 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 24035 { 24036 slotbuf[0] = 0x230; 24037 } 24038 24039 static void 24040 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 24041 { 24042 slotbuf[0] = 0x231; 24043 } 24044 24045 static void 24046 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf) 24047 { 24048 slotbuf[0] = 0x216; 24049 } 24050 24051 static void 24052 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 24053 { 24054 slotbuf[0] = 0x30; 24055 } 24056 24057 static void 24058 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 24059 { 24060 slotbuf[0] = 0x31; 24061 } 24062 24063 static void 24064 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf) 24065 { 24066 slotbuf[0] = 0x16; 24067 } 24068 24069 static void 24070 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 24071 { 24072 slotbuf[0] = 0x330; 24073 } 24074 24075 static void 24076 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 24077 { 24078 slotbuf[0] = 0x331; 24079 } 24080 24081 static void 24082 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 24083 { 24084 slotbuf[0] = 0x316; 24085 } 24086 24087 static void 24088 Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24089 { 24090 slotbuf[0] = 0x6130; 24091 } 24092 24093 static void 24094 Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24095 { 24096 slotbuf[0] = 0x6131; 24097 } 24098 24099 static void 24100 Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24101 { 24102 slotbuf[0] = 0x6116; 24103 } 24104 24105 static void 24106 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24107 { 24108 slotbuf[0] = 0x530; 24109 } 24110 24111 static void 24112 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24113 { 24114 slotbuf[0] = 0x531; 24115 } 24116 24117 static void 24118 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24119 { 24120 slotbuf[0] = 0x516; 24121 } 24122 24123 static void 24124 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) 24125 { 24126 slotbuf[0] = 0xb030; 24127 } 24128 24129 static void 24130 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf) 24131 { 24132 slotbuf[0] = 0xb031; 24133 } 24134 24135 static void 24136 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24137 { 24138 slotbuf[0] = 0xd030; 24139 } 24140 24141 static void 24142 Opcode_rsr_243_Slot_inst_encode (xtensa_insnbuf slotbuf) 24143 { 24144 slotbuf[0] = 0xf330; 24145 } 24146 24147 static void 24148 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 24149 { 24150 slotbuf[0] = 0xe630; 24151 } 24152 24153 static void 24154 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 24155 { 24156 slotbuf[0] = 0xe631; 24157 } 24158 24159 static void 24160 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf) 24161 { 24162 slotbuf[0] = 0xe616; 24163 } 24164 24165 static void 24166 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24167 { 24168 slotbuf[0] = 0xb130; 24169 } 24170 24171 static void 24172 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24173 { 24174 slotbuf[0] = 0xb131; 24175 } 24176 24177 static void 24178 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24179 { 24180 slotbuf[0] = 0xb116; 24181 } 24182 24183 static void 24184 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24185 { 24186 slotbuf[0] = 0xd130; 24187 } 24188 24189 static void 24190 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24191 { 24192 slotbuf[0] = 0xd131; 24193 } 24194 24195 static void 24196 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24197 { 24198 slotbuf[0] = 0xd116; 24199 } 24200 24201 static void 24202 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24203 { 24204 slotbuf[0] = 0xb230; 24205 } 24206 24207 static void 24208 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24209 { 24210 slotbuf[0] = 0xb231; 24211 } 24212 24213 static void 24214 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24215 { 24216 slotbuf[0] = 0xb216; 24217 } 24218 24219 static void 24220 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24221 { 24222 slotbuf[0] = 0xd230; 24223 } 24224 24225 static void 24226 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24227 { 24228 slotbuf[0] = 0xd231; 24229 } 24230 24231 static void 24232 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24233 { 24234 slotbuf[0] = 0xd216; 24235 } 24236 24237 static void 24238 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24239 { 24240 slotbuf[0] = 0xb330; 24241 } 24242 24243 static void 24244 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24245 { 24246 slotbuf[0] = 0xb331; 24247 } 24248 24249 static void 24250 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24251 { 24252 slotbuf[0] = 0xb316; 24253 } 24254 24255 static void 24256 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24257 { 24258 slotbuf[0] = 0xd330; 24259 } 24260 24261 static void 24262 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24263 { 24264 slotbuf[0] = 0xd331; 24265 } 24266 24267 static void 24268 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24269 { 24270 slotbuf[0] = 0xd316; 24271 } 24272 24273 static void 24274 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24275 { 24276 slotbuf[0] = 0xb430; 24277 } 24278 24279 static void 24280 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24281 { 24282 slotbuf[0] = 0xb431; 24283 } 24284 24285 static void 24286 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24287 { 24288 slotbuf[0] = 0xb416; 24289 } 24290 24291 static void 24292 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24293 { 24294 slotbuf[0] = 0xd430; 24295 } 24296 24297 static void 24298 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24299 { 24300 slotbuf[0] = 0xd431; 24301 } 24302 24303 static void 24304 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24305 { 24306 slotbuf[0] = 0xd416; 24307 } 24308 24309 static void 24310 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24311 { 24312 slotbuf[0] = 0xb530; 24313 } 24314 24315 static void 24316 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24317 { 24318 slotbuf[0] = 0xb531; 24319 } 24320 24321 static void 24322 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24323 { 24324 slotbuf[0] = 0xb516; 24325 } 24326 24327 static void 24328 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24329 { 24330 slotbuf[0] = 0xd530; 24331 } 24332 24333 static void 24334 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24335 { 24336 slotbuf[0] = 0xd531; 24337 } 24338 24339 static void 24340 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24341 { 24342 slotbuf[0] = 0xd516; 24343 } 24344 24345 static void 24346 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24347 { 24348 slotbuf[0] = 0xb630; 24349 } 24350 24351 static void 24352 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24353 { 24354 slotbuf[0] = 0xb631; 24355 } 24356 24357 static void 24358 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24359 { 24360 slotbuf[0] = 0xb616; 24361 } 24362 24363 static void 24364 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24365 { 24366 slotbuf[0] = 0xd630; 24367 } 24368 24369 static void 24370 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24371 { 24372 slotbuf[0] = 0xd631; 24373 } 24374 24375 static void 24376 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24377 { 24378 slotbuf[0] = 0xd616; 24379 } 24380 24381 static void 24382 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24383 { 24384 slotbuf[0] = 0xb730; 24385 } 24386 24387 static void 24388 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24389 { 24390 slotbuf[0] = 0xb731; 24391 } 24392 24393 static void 24394 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24395 { 24396 slotbuf[0] = 0xb716; 24397 } 24398 24399 static void 24400 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24401 { 24402 slotbuf[0] = 0xd730; 24403 } 24404 24405 static void 24406 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24407 { 24408 slotbuf[0] = 0xd731; 24409 } 24410 24411 static void 24412 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24413 { 24414 slotbuf[0] = 0xd716; 24415 } 24416 24417 static void 24418 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24419 { 24420 slotbuf[0] = 0xc230; 24421 } 24422 24423 static void 24424 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24425 { 24426 slotbuf[0] = 0xc231; 24427 } 24428 24429 static void 24430 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf) 24431 { 24432 slotbuf[0] = 0xc216; 24433 } 24434 24435 static void 24436 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24437 { 24438 slotbuf[0] = 0xc330; 24439 } 24440 24441 static void 24442 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24443 { 24444 slotbuf[0] = 0xc331; 24445 } 24446 24447 static void 24448 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf) 24449 { 24450 slotbuf[0] = 0xc316; 24451 } 24452 24453 static void 24454 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24455 { 24456 slotbuf[0] = 0xc430; 24457 } 24458 24459 static void 24460 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24461 { 24462 slotbuf[0] = 0xc431; 24463 } 24464 24465 static void 24466 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf) 24467 { 24468 slotbuf[0] = 0xc416; 24469 } 24470 24471 static void 24472 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24473 { 24474 slotbuf[0] = 0xc530; 24475 } 24476 24477 static void 24478 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24479 { 24480 slotbuf[0] = 0xc531; 24481 } 24482 24483 static void 24484 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf) 24485 { 24486 slotbuf[0] = 0xc516; 24487 } 24488 24489 static void 24490 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24491 { 24492 slotbuf[0] = 0xc630; 24493 } 24494 24495 static void 24496 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24497 { 24498 slotbuf[0] = 0xc631; 24499 } 24500 24501 static void 24502 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf) 24503 { 24504 slotbuf[0] = 0xc616; 24505 } 24506 24507 static void 24508 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24509 { 24510 slotbuf[0] = 0xc730; 24511 } 24512 24513 static void 24514 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24515 { 24516 slotbuf[0] = 0xc731; 24517 } 24518 24519 static void 24520 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf) 24521 { 24522 slotbuf[0] = 0xc716; 24523 } 24524 24525 static void 24526 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 24527 { 24528 slotbuf[0] = 0xee30; 24529 } 24530 24531 static void 24532 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 24533 { 24534 slotbuf[0] = 0xee31; 24535 } 24536 24537 static void 24538 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 24539 { 24540 slotbuf[0] = 0xee16; 24541 } 24542 24543 static void 24544 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 24545 { 24546 slotbuf[0] = 0xc030; 24547 } 24548 24549 static void 24550 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 24551 { 24552 slotbuf[0] = 0xc031; 24553 } 24554 24555 static void 24556 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf) 24557 { 24558 slotbuf[0] = 0xc016; 24559 } 24560 24561 static void 24562 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 24563 { 24564 slotbuf[0] = 0xe830; 24565 } 24566 24567 static void 24568 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 24569 { 24570 slotbuf[0] = 0xe831; 24571 } 24572 24573 static void 24574 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf) 24575 { 24576 slotbuf[0] = 0xe816; 24577 } 24578 24579 static void 24580 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 24581 { 24582 slotbuf[0] = 0xf430; 24583 } 24584 24585 static void 24586 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 24587 { 24588 slotbuf[0] = 0xf431; 24589 } 24590 24591 static void 24592 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 24593 { 24594 slotbuf[0] = 0xf416; 24595 } 24596 24597 static void 24598 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24599 { 24600 slotbuf[0] = 0xf530; 24601 } 24602 24603 static void 24604 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24605 { 24606 slotbuf[0] = 0xf531; 24607 } 24608 24609 static void 24610 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 24611 { 24612 slotbuf[0] = 0xf516; 24613 } 24614 24615 static void 24616 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf) 24617 { 24618 slotbuf[0] = 0xeb30; 24619 } 24620 24621 static void 24622 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24623 { 24624 slotbuf[0] = 0xe730; 24625 } 24626 24627 static void 24628 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24629 { 24630 slotbuf[0] = 0xe731; 24631 } 24632 24633 static void 24634 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf) 24635 { 24636 slotbuf[0] = 0xe716; 24637 } 24638 24639 static void 24640 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf) 24641 { 24642 slotbuf[0] = 0x1c; 24643 } 24644 24645 static void 24646 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf) 24647 { 24648 slotbuf[0] = 0x1d; 24649 } 24650 24651 static void 24652 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf) 24653 { 24654 slotbuf[0] = 0x28; 24655 } 24656 24657 static void 24658 Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24659 { 24660 slotbuf[0] = 0x2a; 24661 } 24662 24663 static void 24664 Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24665 { 24666 slotbuf[0] = 0x2b; 24667 } 24668 24669 static void 24670 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24671 { 24672 slotbuf[0] = 0x400047; 24673 } 24674 24675 static void 24676 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24677 { 24678 slotbuf[0] = 0x400057; 24679 } 24680 24681 static void 24682 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24683 { 24684 slotbuf[0] = 0x400067; 24685 } 24686 24687 static void 24688 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24689 { 24690 slotbuf[0] = 0x400077; 24691 } 24692 24693 static void 24694 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24695 { 24696 slotbuf[0] = 0x400007; 24697 } 24698 24699 static void 24700 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24701 { 24702 slotbuf[0] = 0x400017; 24703 } 24704 24705 static void 24706 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24707 { 24708 slotbuf[0] = 0x400027; 24709 } 24710 24711 static void 24712 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24713 { 24714 slotbuf[0] = 0x400037; 24715 } 24716 24717 static void 24718 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24719 { 24720 slotbuf[0] = 0x400043; 24721 } 24722 24723 static void 24724 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24725 { 24726 slotbuf[0] = 0x400053; 24727 } 24728 24729 static void 24730 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24731 { 24732 slotbuf[0] = 0x400063; 24733 } 24734 24735 static void 24736 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24737 { 24738 slotbuf[0] = 0x400073; 24739 } 24740 24741 static void 24742 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24743 { 24744 slotbuf[0] = 0x400046; 24745 } 24746 24747 static void 24748 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24749 { 24750 slotbuf[0] = 0x400056; 24751 } 24752 24753 static void 24754 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24755 { 24756 slotbuf[0] = 0x400066; 24757 } 24758 24759 static void 24760 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24761 { 24762 slotbuf[0] = 0x400076; 24763 } 24764 24765 static void 24766 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24767 { 24768 slotbuf[0] = 0x400042; 24769 } 24770 24771 static void 24772 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24773 { 24774 slotbuf[0] = 0x400052; 24775 } 24776 24777 static void 24778 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24779 { 24780 slotbuf[0] = 0x400062; 24781 } 24782 24783 static void 24784 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24785 { 24786 slotbuf[0] = 0x400072; 24787 } 24788 24789 static void 24790 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24791 { 24792 slotbuf[0] = 0x400087; 24793 } 24794 24795 static void 24796 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24797 { 24798 slotbuf[0] = 0x400097; 24799 } 24800 24801 static void 24802 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24803 { 24804 slotbuf[0] = 0x4000a7; 24805 } 24806 24807 static void 24808 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24809 { 24810 slotbuf[0] = 0x4000b7; 24811 } 24812 24813 static void 24814 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24815 { 24816 slotbuf[0] = 0x4000c7; 24817 } 24818 24819 static void 24820 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24821 { 24822 slotbuf[0] = 0x4000d7; 24823 } 24824 24825 static void 24826 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24827 { 24828 slotbuf[0] = 0x4000e7; 24829 } 24830 24831 static void 24832 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24833 { 24834 slotbuf[0] = 0x4000f7; 24835 } 24836 24837 static void 24838 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24839 { 24840 slotbuf[0] = 0x400083; 24841 } 24842 24843 static void 24844 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24845 { 24846 slotbuf[0] = 0x400093; 24847 } 24848 24849 static void 24850 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24851 { 24852 slotbuf[0] = 0x4000a3; 24853 } 24854 24855 static void 24856 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24857 { 24858 slotbuf[0] = 0x4000b3; 24859 } 24860 24861 static void 24862 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24863 { 24864 slotbuf[0] = 0x4000c3; 24865 } 24866 24867 static void 24868 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24869 { 24870 slotbuf[0] = 0x4000d3; 24871 } 24872 24873 static void 24874 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24875 { 24876 slotbuf[0] = 0x4000e3; 24877 } 24878 24879 static void 24880 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24881 { 24882 slotbuf[0] = 0x4000f3; 24883 } 24884 24885 static void 24886 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24887 { 24888 slotbuf[0] = 0x400086; 24889 } 24890 24891 static void 24892 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24893 { 24894 slotbuf[0] = 0x400096; 24895 } 24896 24897 static void 24898 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24899 { 24900 slotbuf[0] = 0x4000a6; 24901 } 24902 24903 static void 24904 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24905 { 24906 slotbuf[0] = 0x4000b6; 24907 } 24908 24909 static void 24910 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24911 { 24912 slotbuf[0] = 0x4000c6; 24913 } 24914 24915 static void 24916 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24917 { 24918 slotbuf[0] = 0x4000d6; 24919 } 24920 24921 static void 24922 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24923 { 24924 slotbuf[0] = 0x4000e6; 24925 } 24926 24927 static void 24928 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24929 { 24930 slotbuf[0] = 0x4000f6; 24931 } 24932 24933 static void 24934 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24935 { 24936 slotbuf[0] = 0x400082; 24937 } 24938 24939 static void 24940 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24941 { 24942 slotbuf[0] = 0x400092; 24943 } 24944 24945 static void 24946 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24947 { 24948 slotbuf[0] = 0x4000a2; 24949 } 24950 24951 static void 24952 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24953 { 24954 slotbuf[0] = 0x4000b2; 24955 } 24956 24957 static void 24958 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 24959 { 24960 slotbuf[0] = 0x4000c2; 24961 } 24962 24963 static void 24964 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 24965 { 24966 slotbuf[0] = 0x4000d2; 24967 } 24968 24969 static void 24970 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24971 { 24972 slotbuf[0] = 0x4000e2; 24973 } 24974 24975 static void 24976 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 24977 { 24978 slotbuf[0] = 0x4000f2; 24979 } 24980 24981 static void 24982 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 24983 { 24984 slotbuf[0] = 0x400085; 24985 } 24986 24987 static void 24988 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 24989 { 24990 slotbuf[0] = 0x400084; 24991 } 24992 24993 static void 24994 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 24995 { 24996 slotbuf[0] = 0x400095; 24997 } 24998 24999 static void 25000 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25001 { 25002 slotbuf[0] = 0x400094; 25003 } 25004 25005 static void 25006 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25007 { 25008 slotbuf[0] = 0x4000a5; 25009 } 25010 25011 static void 25012 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25013 { 25014 slotbuf[0] = 0x4000a4; 25015 } 25016 25017 static void 25018 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25019 { 25020 slotbuf[0] = 0x4000b5; 25021 } 25022 25023 static void 25024 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25025 { 25026 slotbuf[0] = 0x4000b4; 25027 } 25028 25029 static void 25030 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25031 { 25032 slotbuf[0] = 0x400081; 25033 } 25034 25035 static void 25036 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25037 { 25038 slotbuf[0] = 0x400080; 25039 } 25040 25041 static void 25042 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25043 { 25044 slotbuf[0] = 0x400091; 25045 } 25046 25047 static void 25048 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25049 { 25050 slotbuf[0] = 0x400090; 25051 } 25052 25053 static void 25054 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25055 { 25056 slotbuf[0] = 0x4000a1; 25057 } 25058 25059 static void 25060 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25061 { 25062 slotbuf[0] = 0x4000a0; 25063 } 25064 25065 static void 25066 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25067 { 25068 slotbuf[0] = 0x4000b1; 25069 } 25070 25071 static void 25072 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25073 { 25074 slotbuf[0] = 0x4000b0; 25075 } 25076 25077 static void 25078 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf) 25079 { 25080 slotbuf[0] = 0x400009; 25081 } 25082 25083 static void 25084 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25085 { 25086 slotbuf[0] = 0x400008; 25087 } 25088 25089 static void 25090 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25091 { 25092 slotbuf[0] = 0x2030; 25093 } 25094 25095 static void 25096 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25097 { 25098 slotbuf[0] = 0x2031; 25099 } 25100 25101 static void 25102 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25103 { 25104 slotbuf[0] = 0x2016; 25105 } 25106 25107 static void 25108 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25109 { 25110 slotbuf[0] = 0x2130; 25111 } 25112 25113 static void 25114 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25115 { 25116 slotbuf[0] = 0x2131; 25117 } 25118 25119 static void 25120 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25121 { 25122 slotbuf[0] = 0x2116; 25123 } 25124 25125 static void 25126 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25127 { 25128 slotbuf[0] = 0x2230; 25129 } 25130 25131 static void 25132 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25133 { 25134 slotbuf[0] = 0x2231; 25135 } 25136 25137 static void 25138 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25139 { 25140 slotbuf[0] = 0x2216; 25141 } 25142 25143 static void 25144 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 25145 { 25146 slotbuf[0] = 0x2330; 25147 } 25148 25149 static void 25150 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 25151 { 25152 slotbuf[0] = 0x2331; 25153 } 25154 25155 static void 25156 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf) 25157 { 25158 slotbuf[0] = 0x2316; 25159 } 25160 25161 static void 25162 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 25163 { 25164 slotbuf[0] = 0x1030; 25165 } 25166 25167 static void 25168 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 25169 { 25170 slotbuf[0] = 0x1031; 25171 } 25172 25173 static void 25174 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf) 25175 { 25176 slotbuf[0] = 0x1016; 25177 } 25178 25179 static void 25180 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25181 { 25182 slotbuf[0] = 0x1130; 25183 } 25184 25185 static void 25186 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25187 { 25188 slotbuf[0] = 0x1131; 25189 } 25190 25191 static void 25192 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25193 { 25194 slotbuf[0] = 0x1116; 25195 } 25196 25197 static void 25198 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25199 { 25200 slotbuf[0] = 0x10300; 25201 } 25202 25203 static void 25204 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf) 25205 { 25206 slotbuf[0] = 0x700; 25207 } 25208 25209 static void 25210 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf) 25211 { 25212 slotbuf[0] = 0xe230; 25213 } 25214 25215 static void 25216 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf) 25217 { 25218 slotbuf[0] = 0xe231; 25219 } 25220 25221 static void 25222 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf) 25223 { 25224 slotbuf[0] = 0xe331; 25225 } 25226 25227 static void 25228 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25229 { 25230 slotbuf[0] = 0xe430; 25231 } 25232 25233 static void 25234 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25235 { 25236 slotbuf[0] = 0xe431; 25237 } 25238 25239 static void 25240 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25241 { 25242 slotbuf[0] = 0xe416; 25243 } 25244 25245 static void 25246 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf) 25247 { 25248 slotbuf[0] = 0x400; 25249 } 25250 25251 static void 25252 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf) 25253 { 25254 slotbuf[0] = 0xd20f; 25255 } 25256 25257 static void 25258 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25259 { 25260 slotbuf[0] = 0x9030; 25261 } 25262 25263 static void 25264 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25265 { 25266 slotbuf[0] = 0x9031; 25267 } 25268 25269 static void 25270 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25271 { 25272 slotbuf[0] = 0x9016; 25273 } 25274 25275 static void 25276 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25277 { 25278 slotbuf[0] = 0xa030; 25279 } 25280 25281 static void 25282 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25283 { 25284 slotbuf[0] = 0xa031; 25285 } 25286 25287 static void 25288 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25289 { 25290 slotbuf[0] = 0xa016; 25291 } 25292 25293 static void 25294 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25295 { 25296 slotbuf[0] = 0x9130; 25297 } 25298 25299 static void 25300 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25301 { 25302 slotbuf[0] = 0x9131; 25303 } 25304 25305 static void 25306 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25307 { 25308 slotbuf[0] = 0x9116; 25309 } 25310 25311 static void 25312 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25313 { 25314 slotbuf[0] = 0xa130; 25315 } 25316 25317 static void 25318 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25319 { 25320 slotbuf[0] = 0xa131; 25321 } 25322 25323 static void 25324 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25325 { 25326 slotbuf[0] = 0xa116; 25327 } 25328 25329 static void 25330 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25331 { 25332 slotbuf[0] = 0x8030; 25333 } 25334 25335 static void 25336 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25337 { 25338 slotbuf[0] = 0x8031; 25339 } 25340 25341 static void 25342 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25343 { 25344 slotbuf[0] = 0x8016; 25345 } 25346 25347 static void 25348 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25349 { 25350 slotbuf[0] = 0x8130; 25351 } 25352 25353 static void 25354 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25355 { 25356 slotbuf[0] = 0x8131; 25357 } 25358 25359 static void 25360 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25361 { 25362 slotbuf[0] = 0x8116; 25363 } 25364 25365 static void 25366 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25367 { 25368 slotbuf[0] = 0x6030; 25369 } 25370 25371 static void 25372 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25373 { 25374 slotbuf[0] = 0x6031; 25375 } 25376 25377 static void 25378 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 25379 { 25380 slotbuf[0] = 0x6016; 25381 } 25382 25383 static void 25384 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 25385 { 25386 slotbuf[0] = 0xe930; 25387 } 25388 25389 static void 25390 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 25391 { 25392 slotbuf[0] = 0xe931; 25393 } 25394 25395 static void 25396 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf) 25397 { 25398 slotbuf[0] = 0xe916; 25399 } 25400 25401 static void 25402 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25403 { 25404 slotbuf[0] = 0xec30; 25405 } 25406 25407 static void 25408 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25409 { 25410 slotbuf[0] = 0xec31; 25411 } 25412 25413 static void 25414 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25415 { 25416 slotbuf[0] = 0xec16; 25417 } 25418 25419 static void 25420 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 25421 { 25422 slotbuf[0] = 0xed30; 25423 } 25424 25425 static void 25426 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 25427 { 25428 slotbuf[0] = 0xed31; 25429 } 25430 25431 static void 25432 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf) 25433 { 25434 slotbuf[0] = 0xed16; 25435 } 25436 25437 static void 25438 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25439 { 25440 slotbuf[0] = 0x6830; 25441 } 25442 25443 static void 25444 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25445 { 25446 slotbuf[0] = 0x6831; 25447 } 25448 25449 static void 25450 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25451 { 25452 slotbuf[0] = 0x6816; 25453 } 25454 25455 static void 25456 Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 25457 { 25458 slotbuf[0] = 0xe0700; 25459 } 25460 25461 static void 25462 Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 25463 { 25464 slotbuf[0] = 0xf0700; 25465 } 25466 25467 static void 25468 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf) 25469 { 25470 slotbuf[0] = 0xe1f; 25471 } 25472 25473 static void 25474 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf) 25475 { 25476 slotbuf[0] = 0x10e1f; 25477 } 25478 25479 static void 25480 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf) 25481 { 25482 slotbuf[0] = 0x5931; 25483 } 25484 25485 static void 25486 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25487 { 25488 slotbuf[0] = 0x20; 25489 } 25490 25491 static void 25492 Opcode_andb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25493 { 25494 slotbuf[0] = 0x5381; 25495 } 25496 25497 static void 25498 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25499 { 25500 slotbuf[0] = 0x21; 25501 } 25502 25503 static void 25504 Opcode_andbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25505 { 25506 slotbuf[0] = 0x5b81; 25507 } 25508 25509 static void 25510 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25511 { 25512 slotbuf[0] = 0x22; 25513 } 25514 25515 static void 25516 Opcode_orb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25517 { 25518 slotbuf[0] = 0x4581; 25519 } 25520 25521 static void 25522 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf) 25523 { 25524 slotbuf[0] = 0x23; 25525 } 25526 25527 static void 25528 Opcode_orbc_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25529 { 25530 slotbuf[0] = 0x781; 25531 } 25532 25533 static void 25534 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25535 { 25536 slotbuf[0] = 0x24; 25537 } 25538 25539 static void 25540 Opcode_xorb_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25541 { 25542 slotbuf[0] = 0x4f81; 25543 } 25544 25545 static void 25546 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf) 25547 { 25548 slotbuf[0] = 0x800; 25549 } 25550 25551 static void 25552 Opcode_any4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25553 { 25554 slotbuf[0] = 0x96501; 25555 } 25556 25557 static void 25558 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf) 25559 { 25560 slotbuf[0] = 0x900; 25561 } 25562 25563 static void 25564 Opcode_all4_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25565 { 25566 slotbuf[0] = 0x8e501; 25567 } 25568 25569 static void 25570 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf) 25571 { 25572 slotbuf[0] = 0xa00; 25573 } 25574 25575 static void 25576 Opcode_any8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25577 { 25578 slotbuf[0] = 0xc6501; 25579 } 25580 25581 static void 25582 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf) 25583 { 25584 slotbuf[0] = 0xb00; 25585 } 25586 25587 static void 25588 Opcode_all8_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25589 { 25590 slotbuf[0] = 0xa6501; 25591 } 25592 25593 static void 25594 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf) 25595 { 25596 slotbuf[0] = 0x6d0000; 25597 } 25598 25599 static void 25600 Opcode_bf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25601 { 25602 slotbuf[0] = 0x2800003; 25603 } 25604 25605 static void 25606 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf) 25607 { 25608 slotbuf[0] = 0x6d0100; 25609 } 25610 25611 static void 25612 Opcode_bt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25613 { 25614 slotbuf[0] = 0x3000003; 25615 } 25616 25617 static void 25618 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf) 25619 { 25620 slotbuf[0] = 0x3c; 25621 } 25622 25623 static void 25624 Opcode_movf_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25625 { 25626 slotbuf[0] = 0x7b81; 25627 } 25628 25629 static void 25630 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf) 25631 { 25632 slotbuf[0] = 0x3d; 25633 } 25634 25635 static void 25636 Opcode_movt_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 25637 { 25638 slotbuf[0] = 0x1501; 25639 } 25640 25641 static void 25642 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) 25643 { 25644 slotbuf[0] = 0x430; 25645 } 25646 25647 static void 25648 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) 25649 { 25650 slotbuf[0] = 0x431; 25651 } 25652 25653 static void 25654 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf) 25655 { 25656 slotbuf[0] = 0x416; 25657 } 25658 25659 static void 25660 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25661 { 25662 slotbuf[0] = 0xea30; 25663 } 25664 25665 static void 25666 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25667 { 25668 slotbuf[0] = 0xea31; 25669 } 25670 25671 static void 25672 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf) 25673 { 25674 slotbuf[0] = 0xea16; 25675 } 25676 25677 static void 25678 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25679 { 25680 slotbuf[0] = 0xf030; 25681 } 25682 25683 static void 25684 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25685 { 25686 slotbuf[0] = 0xf031; 25687 } 25688 25689 static void 25690 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25691 { 25692 slotbuf[0] = 0xf016; 25693 } 25694 25695 static void 25696 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25697 { 25698 slotbuf[0] = 0xf130; 25699 } 25700 25701 static void 25702 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25703 { 25704 slotbuf[0] = 0xf131; 25705 } 25706 25707 static void 25708 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25709 { 25710 slotbuf[0] = 0xf116; 25711 } 25712 25713 static void 25714 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25715 { 25716 slotbuf[0] = 0xf230; 25717 } 25718 25719 static void 25720 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25721 { 25722 slotbuf[0] = 0xf231; 25723 } 25724 25725 static void 25726 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf) 25727 { 25728 slotbuf[0] = 0xf216; 25729 } 25730 25731 static void 25732 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf) 25733 { 25734 slotbuf[0] = 0x2c0700; 25735 } 25736 25737 static void 25738 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25739 { 25740 slotbuf[0] = 0x2e0700; 25741 } 25742 25743 static void 25744 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 25745 { 25746 slotbuf[0] = 0x2d0700; 25747 } 25748 25749 static void 25750 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf) 25751 { 25752 slotbuf[0] = 0x2d0720; 25753 } 25754 25755 static void 25756 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf) 25757 { 25758 slotbuf[0] = 0x2d0730; 25759 } 25760 25761 static void 25762 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf) 25763 { 25764 slotbuf[0] = 0x2f0700; 25765 } 25766 25767 static void 25768 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf) 25769 { 25770 slotbuf[0] = 0x1f; 25771 } 25772 25773 static void 25774 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf) 25775 { 25776 slotbuf[0] = 0x21f; 25777 } 25778 25779 static void 25780 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf) 25781 { 25782 slotbuf[0] = 0x11f; 25783 } 25784 25785 static void 25786 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf) 25787 { 25788 slotbuf[0] = 0x31f; 25789 } 25790 25791 static void 25792 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25793 { 25794 slotbuf[0] = 0x240700; 25795 } 25796 25797 static void 25798 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25799 { 25800 slotbuf[0] = 0x250700; 25801 } 25802 25803 static void 25804 Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf) 25805 { 25806 slotbuf[0] = 0x2807f0; 25807 } 25808 25809 static void 25810 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25811 { 25812 slotbuf[0] = 0x280740; 25813 } 25814 25815 static void 25816 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25817 { 25818 slotbuf[0] = 0x280750; 25819 } 25820 25821 static void 25822 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf) 25823 { 25824 slotbuf[0] = 0x260700; 25825 } 25826 25827 static void 25828 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf) 25829 { 25830 slotbuf[0] = 0x270700; 25831 } 25832 25833 static void 25834 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25835 { 25836 slotbuf[0] = 0x200700; 25837 } 25838 25839 static void 25840 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf) 25841 { 25842 slotbuf[0] = 0x210700; 25843 } 25844 25845 static void 25846 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf) 25847 { 25848 slotbuf[0] = 0x220700; 25849 } 25850 25851 static void 25852 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf) 25853 { 25854 slotbuf[0] = 0x230700; 25855 } 25856 25857 static void 25858 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf) 25859 { 25860 slotbuf[0] = 0x280700; 25861 } 25862 25863 static void 25864 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf) 25865 { 25866 slotbuf[0] = 0x280720; 25867 } 25868 25869 static void 25870 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf) 25871 { 25872 slotbuf[0] = 0x280730; 25873 } 25874 25875 static void 25876 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf) 25877 { 25878 slotbuf[0] = 0x91f; 25879 } 25880 25881 static void 25882 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf) 25883 { 25884 slotbuf[0] = 0x81f; 25885 } 25886 25887 static void 25888 Opcode_rsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 25889 { 25890 slotbuf[0] = 0x2830; 25891 } 25892 25893 static void 25894 Opcode_wsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 25895 { 25896 slotbuf[0] = 0x2831; 25897 } 25898 25899 static void 25900 Opcode_xsr_prefctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 25901 { 25902 slotbuf[0] = 0x2816; 25903 } 25904 25905 static void 25906 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25907 { 25908 slotbuf[0] = 0x5331; 25909 } 25910 25911 static void 25912 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25913 { 25914 slotbuf[0] = 0x5330; 25915 } 25916 25917 static void 25918 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf) 25919 { 25920 slotbuf[0] = 0x5316; 25921 } 25922 25923 static void 25924 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 25925 { 25926 slotbuf[0] = 0x5a30; 25927 } 25928 25929 static void 25930 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 25931 { 25932 slotbuf[0] = 0x5a31; 25933 } 25934 25935 static void 25936 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf) 25937 { 25938 slotbuf[0] = 0x5a16; 25939 } 25940 25941 static void 25942 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25943 { 25944 slotbuf[0] = 0x5b30; 25945 } 25946 25947 static void 25948 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25949 { 25950 slotbuf[0] = 0x5b31; 25951 } 25952 25953 static void 25954 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25955 { 25956 slotbuf[0] = 0x5b16; 25957 } 25958 25959 static void 25960 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25961 { 25962 slotbuf[0] = 0x5c30; 25963 } 25964 25965 static void 25966 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25967 { 25968 slotbuf[0] = 0x5c31; 25969 } 25970 25971 static void 25972 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf) 25973 { 25974 slotbuf[0] = 0x5c16; 25975 } 25976 25977 static void 25978 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25979 { 25980 slotbuf[0] = 0xc05; 25981 } 25982 25983 static void 25984 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 25985 { 25986 slotbuf[0] = 0xd05; 25987 } 25988 25989 static void 25990 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 25991 { 25992 slotbuf[0] = 0xb05; 25993 } 25994 25995 static void 25996 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 25997 { 25998 slotbuf[0] = 0xf05; 25999 } 26000 26001 static void 26002 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 26003 { 26004 slotbuf[0] = 0xe05; 26005 } 26006 26007 static void 26008 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 26009 { 26010 slotbuf[0] = 0x405; 26011 } 26012 26013 static void 26014 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 26015 { 26016 slotbuf[0] = 0x505; 26017 } 26018 26019 static void 26020 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf) 26021 { 26022 slotbuf[0] = 0x305; 26023 } 26024 26025 static void 26026 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf) 26027 { 26028 slotbuf[0] = 0x705; 26029 } 26030 26031 static void 26032 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf) 26033 { 26034 slotbuf[0] = 0x605; 26035 } 26036 26037 static void 26038 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf) 26039 { 26040 slotbuf[0] = 0xf1f; 26041 } 26042 26043 static void 26044 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 26045 { 26046 slotbuf[0] = 0x105; 26047 } 26048 26049 static void 26050 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf) 26051 { 26052 slotbuf[0] = 0x905; 26053 } 26054 26055 static void 26056 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 26057 { 26058 slotbuf[0] = 0xe030; 26059 } 26060 26061 static void 26062 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 26063 { 26064 slotbuf[0] = 0xe031; 26065 } 26066 26067 static void 26068 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf) 26069 { 26070 slotbuf[0] = 0xe016; 26071 } 26072 26073 static void 26074 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf) 26075 { 26076 slotbuf[0] = 0x33; 26077 } 26078 26079 static void 26080 Opcode_clamps_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26081 { 26082 slotbuf[0] = 0x2b81; 26083 } 26084 26085 static void 26086 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf) 26087 { 26088 slotbuf[0] = 0x34; 26089 } 26090 26091 static void 26092 Opcode_min_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26093 { 26094 slotbuf[0] = 0x3b81; 26095 } 26096 26097 static void 26098 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf) 26099 { 26100 slotbuf[0] = 0x35; 26101 } 26102 26103 static void 26104 Opcode_max_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26105 { 26106 slotbuf[0] = 0x3381; 26107 } 26108 26109 static void 26110 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26111 { 26112 slotbuf[0] = 0x36; 26113 } 26114 26115 static void 26116 Opcode_minu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26117 { 26118 slotbuf[0] = 0x6b81; 26119 } 26120 26121 static void 26122 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26123 { 26124 slotbuf[0] = 0x37; 26125 } 26126 26127 static void 26128 Opcode_maxu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26129 { 26130 slotbuf[0] = 0x6381; 26131 } 26132 26133 static void 26134 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf) 26135 { 26136 slotbuf[0] = 0xe04; 26137 } 26138 26139 static void 26140 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf) 26141 { 26142 slotbuf[0] = 0xf04; 26143 } 26144 26145 static void 26146 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf) 26147 { 26148 slotbuf[0] = 0x32; 26149 } 26150 26151 static void 26152 Opcode_sext_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26153 { 26154 slotbuf[0] = 0x4701; 26155 } 26156 26157 static void 26158 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf) 26159 { 26160 slotbuf[0] = 0x200b00; 26161 } 26162 26163 static void 26164 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf) 26165 { 26166 slotbuf[0] = 0x200f00; 26167 } 26168 26169 static void 26170 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26171 { 26172 slotbuf[0] = 0x200e00; 26173 } 26174 26175 static void 26176 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 26177 { 26178 slotbuf[0] = 0xc30; 26179 } 26180 26181 static void 26182 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 26183 { 26184 slotbuf[0] = 0xc31; 26185 } 26186 26187 static void 26188 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf) 26189 { 26190 slotbuf[0] = 0xc16; 26191 } 26192 26193 static void 26194 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 26195 { 26196 slotbuf[0] = 0x6330; 26197 } 26198 26199 static void 26200 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 26201 { 26202 slotbuf[0] = 0x6331; 26203 } 26204 26205 static void 26206 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf) 26207 { 26208 slotbuf[0] = 0x6316; 26209 } 26210 26211 static void 26212 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf) 26213 { 26214 slotbuf[0] = 0x2c; 26215 } 26216 26217 static void 26218 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf) 26219 { 26220 slotbuf[0] = 0x2d; 26221 } 26222 26223 static void 26224 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26225 { 26226 slotbuf[0] = 0x2e; 26227 } 26228 26229 static void 26230 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf) 26231 { 26232 slotbuf[0] = 0x2f; 26233 } 26234 26235 static void 26236 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf) 26237 { 26238 slotbuf[0] = 0x604; 26239 } 26240 26241 static void 26242 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf) 26243 { 26244 slotbuf[0] = 0x704; 26245 } 26246 26247 static void 26248 Opcode_rur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 26249 { 26250 slotbuf[0] = 0xf03e; 26251 } 26252 26253 static void 26254 Opcode_wur_ae_ovf_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 26255 { 26256 slotbuf[0] = 0xf03f; 26257 } 26258 26259 static void 26260 Opcode_rur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) 26261 { 26262 slotbuf[0] = 0x1f03e; 26263 } 26264 26265 static void 26266 Opcode_wur_ae_bithead_Slot_inst_encode (xtensa_insnbuf slotbuf) 26267 { 26268 slotbuf[0] = 0xf13f; 26269 } 26270 26271 static void 26272 Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) 26273 { 26274 slotbuf[0] = 0x2f03e; 26275 } 26276 26277 static void 26278 Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode (xtensa_insnbuf slotbuf) 26279 { 26280 slotbuf[0] = 0xf23f; 26281 } 26282 26283 static void 26284 Opcode_rur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) 26285 { 26286 slotbuf[0] = 0x3f03e; 26287 } 26288 26289 static void 26290 Opcode_wur_ae_sd_no_Slot_inst_encode (xtensa_insnbuf slotbuf) 26291 { 26292 slotbuf[0] = 0xf33f; 26293 } 26294 26295 static void 26296 Opcode_rur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) 26297 { 26298 slotbuf[0] = 0x40809c; 26299 } 26300 26301 static void 26302 Opcode_wur_ae_overflow_Slot_inst_encode (xtensa_insnbuf slotbuf) 26303 { 26304 slotbuf[0] = 0x4000ac; 26305 } 26306 26307 static void 26308 Opcode_rur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 26309 { 26310 slotbuf[0] = 0x40909c; 26311 } 26312 26313 static void 26314 Opcode_wur_ae_sar_Slot_inst_encode (xtensa_insnbuf slotbuf) 26315 { 26316 slotbuf[0] = 0x4001ac; 26317 } 26318 26319 static void 26320 Opcode_rur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 26321 { 26322 slotbuf[0] = 0x40a09c; 26323 } 26324 26325 static void 26326 Opcode_wur_ae_bitptr_Slot_inst_encode (xtensa_insnbuf slotbuf) 26327 { 26328 slotbuf[0] = 0x4002ac; 26329 } 26330 26331 static void 26332 Opcode_rur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) 26333 { 26334 slotbuf[0] = 0x40b09c; 26335 } 26336 26337 static void 26338 Opcode_wur_ae_bitsused_Slot_inst_encode (xtensa_insnbuf slotbuf) 26339 { 26340 slotbuf[0] = 0x4003ac; 26341 } 26342 26343 static void 26344 Opcode_rur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) 26345 { 26346 slotbuf[0] = 0x40c09c; 26347 } 26348 26349 static void 26350 Opcode_wur_ae_tablesize_Slot_inst_encode (xtensa_insnbuf slotbuf) 26351 { 26352 slotbuf[0] = 0x4004ac; 26353 } 26354 26355 static void 26356 Opcode_rur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) 26357 { 26358 slotbuf[0] = 0x40d09c; 26359 } 26360 26361 static void 26362 Opcode_wur_ae_first_ts_Slot_inst_encode (xtensa_insnbuf slotbuf) 26363 { 26364 slotbuf[0] = 0x4005ac; 26365 } 26366 26367 static void 26368 Opcode_rur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) 26369 { 26370 slotbuf[0] = 0x40e09c; 26371 } 26372 26373 static void 26374 Opcode_wur_ae_nextoffset_Slot_inst_encode (xtensa_insnbuf slotbuf) 26375 { 26376 slotbuf[0] = 0x4006ac; 26377 } 26378 26379 static void 26380 Opcode_rur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) 26381 { 26382 slotbuf[0] = 0x40f09c; 26383 } 26384 26385 static void 26386 Opcode_wur_ae_searchdone_Slot_inst_encode (xtensa_insnbuf slotbuf) 26387 { 26388 slotbuf[0] = 0x4007ac; 26389 } 26390 26391 static void 26392 Opcode_ae_lp16f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26393 { 26394 slotbuf[0] = 0x81581; 26395 } 26396 26397 static void 26398 Opcode_ae_lp16f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26399 { 26400 slotbuf[0] = 0x40005a; 26401 } 26402 26403 static void 26404 Opcode_ae_lp16f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26405 { 26406 slotbuf[0] = 0x1781; 26407 } 26408 26409 static void 26410 Opcode_ae_lp16f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26411 { 26412 slotbuf[0] = 0x40009a; 26413 } 26414 26415 static void 26416 Opcode_ae_lp16f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26417 { 26418 slotbuf[0] = 0x81701; 26419 } 26420 26421 static void 26422 Opcode_ae_lp16f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26423 { 26424 slotbuf[0] = 0x4000ca; 26425 } 26426 26427 static void 26428 Opcode_ae_lp16f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26429 { 26430 slotbuf[0] = 0x81781; 26431 } 26432 26433 static void 26434 Opcode_ae_lp16f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26435 { 26436 slotbuf[0] = 0x4000fa; 26437 } 26438 26439 static void 26440 Opcode_ae_lp24_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26441 { 26442 slotbuf[0] = 0x81d81; 26443 } 26444 26445 static void 26446 Opcode_ae_lp24_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26447 { 26448 slotbuf[0] = 0x40085a; 26449 } 26450 26451 static void 26452 Opcode_ae_lp24_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26453 { 26454 slotbuf[0] = 0x81f01; 26455 } 26456 26457 static void 26458 Opcode_ae_lp24_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26459 { 26460 slotbuf[0] = 0x40089a; 26461 } 26462 26463 static void 26464 Opcode_ae_lp24_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26465 { 26466 slotbuf[0] = 0x81f81; 26467 } 26468 26469 static void 26470 Opcode_ae_lp24_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26471 { 26472 slotbuf[0] = 0x4008ca; 26473 } 26474 26475 static void 26476 Opcode_ae_lp24_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26477 { 26478 slotbuf[0] = 0x5581; 26479 } 26480 26481 static void 26482 Opcode_ae_lp24_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26483 { 26484 slotbuf[0] = 0x4008fa; 26485 } 26486 26487 static void 26488 Opcode_ae_lp24f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26489 { 26490 slotbuf[0] = 0x5701; 26491 } 26492 26493 static void 26494 Opcode_ae_lp24f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26495 { 26496 slotbuf[0] = 0x40006a; 26497 } 26498 26499 static void 26500 Opcode_ae_lp24f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26501 { 26502 slotbuf[0] = 0x5d01; 26503 } 26504 26505 static void 26506 Opcode_ae_lp24f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26507 { 26508 slotbuf[0] = 0x4000aa; 26509 } 26510 26511 static void 26512 Opcode_ae_lp24f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26513 { 26514 slotbuf[0] = 0x85501; 26515 } 26516 26517 static void 26518 Opcode_ae_lp24f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26519 { 26520 slotbuf[0] = 0x4000da; 26521 } 26522 26523 static void 26524 Opcode_ae_lp24f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26525 { 26526 slotbuf[0] = 0x5781; 26527 } 26528 26529 static void 26530 Opcode_ae_lp24f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26531 { 26532 slotbuf[0] = 0x40000b; 26533 } 26534 26535 static void 26536 Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26537 { 26538 slotbuf[0] = 0x1d81; 26539 } 26540 26541 static void 26542 Opcode_ae_lp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26543 { 26544 slotbuf[0] = 0x40086a; 26545 } 26546 26547 static void 26548 Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26549 { 26550 slotbuf[0] = 0x1f01; 26551 } 26552 26553 static void 26554 Opcode_ae_lp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26555 { 26556 slotbuf[0] = 0x4008aa; 26557 } 26558 26559 static void 26560 Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26561 { 26562 slotbuf[0] = 0x81d01; 26563 } 26564 26565 static void 26566 Opcode_ae_lp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26567 { 26568 slotbuf[0] = 0x4008da; 26569 } 26570 26571 static void 26572 Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26573 { 26574 slotbuf[0] = 0x1f81; 26575 } 26576 26577 static void 26578 Opcode_ae_lp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26579 { 26580 slotbuf[0] = 0x40080b; 26581 } 26582 26583 static void 26584 Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26585 { 26586 slotbuf[0] = 0x85701; 26587 } 26588 26589 static void 26590 Opcode_ae_lp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26591 { 26592 slotbuf[0] = 0x40007a; 26593 } 26594 26595 static void 26596 Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26597 { 26598 slotbuf[0] = 0x85d01; 26599 } 26600 26601 static void 26602 Opcode_ae_lp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26603 { 26604 slotbuf[0] = 0x4000ba; 26605 } 26606 26607 static void 26608 Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26609 { 26610 slotbuf[0] = 0x85781; 26611 } 26612 26613 static void 26614 Opcode_ae_lp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26615 { 26616 slotbuf[0] = 0x4000ea; 26617 } 26618 26619 static void 26620 Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26621 { 26622 slotbuf[0] = 0x85d81; 26623 } 26624 26625 static void 26626 Opcode_ae_lp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26627 { 26628 slotbuf[0] = 0x40001b; 26629 } 26630 26631 static void 26632 Opcode_ae_lp24x2_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26633 { 26634 slotbuf[0] = 0x5d81; 26635 } 26636 26637 static void 26638 Opcode_ae_lp24x2_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26639 { 26640 slotbuf[0] = 0x40087a; 26641 } 26642 26643 static void 26644 Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26645 { 26646 slotbuf[0] = 0x5f01; 26647 } 26648 26649 static void 26650 Opcode_ae_lp24x2_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26651 { 26652 slotbuf[0] = 0x4008ba; 26653 } 26654 26655 static void 26656 Opcode_ae_lp24x2_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26657 { 26658 slotbuf[0] = 0x5f81; 26659 } 26660 26661 static void 26662 Opcode_ae_lp24x2_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26663 { 26664 slotbuf[0] = 0x4008ea; 26665 } 26666 26667 static void 26668 Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26669 { 26670 slotbuf[0] = 0x85581; 26671 } 26672 26673 static void 26674 Opcode_ae_lp24x2_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26675 { 26676 slotbuf[0] = 0x40081b; 26677 } 26678 26679 static void 26680 Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26681 { 26682 slotbuf[0] = 0x3501; 26683 } 26684 26685 static void 26686 Opcode_ae_sp16x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26687 { 26688 slotbuf[0] = 0x40002b; 26689 } 26690 26691 static void 26692 Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26693 { 26694 slotbuf[0] = 0x6501; 26695 } 26696 26697 static void 26698 Opcode_ae_sp16x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26699 { 26700 slotbuf[0] = 0x40005b; 26701 } 26702 26703 static void 26704 Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26705 { 26706 slotbuf[0] = 0x82581; 26707 } 26708 26709 static void 26710 Opcode_ae_sp16x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26711 { 26712 slotbuf[0] = 0x40008b; 26713 } 26714 26715 static void 26716 Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26717 { 26718 slotbuf[0] = 0x2781; 26719 } 26720 26721 static void 26722 Opcode_ae_sp16x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26723 { 26724 slotbuf[0] = 0x4000bb; 26725 } 26726 26727 static void 26728 Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26729 { 26730 slotbuf[0] = 0x83501; 26731 } 26732 26733 static void 26734 Opcode_ae_sp24x2s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26735 { 26736 slotbuf[0] = 0x40082b; 26737 } 26738 26739 static void 26740 Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26741 { 26742 slotbuf[0] = 0x3781; 26743 } 26744 26745 static void 26746 Opcode_ae_sp24x2s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26747 { 26748 slotbuf[0] = 0x40085b; 26749 } 26750 26751 static void 26752 Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26753 { 26754 slotbuf[0] = 0x3d81; 26755 } 26756 26757 static void 26758 Opcode_ae_sp24x2s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26759 { 26760 slotbuf[0] = 0x40088b; 26761 } 26762 26763 static void 26764 Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26765 { 26766 slotbuf[0] = 0x3f01; 26767 } 26768 26769 static void 26770 Opcode_ae_sp24x2s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26771 { 26772 slotbuf[0] = 0x4008bb; 26773 } 26774 26775 static void 26776 Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26777 { 26778 slotbuf[0] = 0x82f81; 26779 } 26780 26781 static void 26782 Opcode_ae_sp24x2f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26783 { 26784 slotbuf[0] = 0x40003b; 26785 } 26786 26787 static void 26788 Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26789 { 26790 slotbuf[0] = 0x3581; 26791 } 26792 26793 static void 26794 Opcode_ae_sp24x2f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26795 { 26796 slotbuf[0] = 0x40006b; 26797 } 26798 26799 static void 26800 Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26801 { 26802 slotbuf[0] = 0x3701; 26803 } 26804 26805 static void 26806 Opcode_ae_sp24x2f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26807 { 26808 slotbuf[0] = 0x40009b; 26809 } 26810 26811 static void 26812 Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26813 { 26814 slotbuf[0] = 0x3d01; 26815 } 26816 26817 static void 26818 Opcode_ae_sp24x2f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26819 { 26820 slotbuf[0] = 0x4000cb; 26821 } 26822 26823 static void 26824 Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26825 { 26826 slotbuf[0] = 0x85f81; 26827 } 26828 26829 static void 26830 Opcode_ae_sp16f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26831 { 26832 slotbuf[0] = 0x40083b; 26833 } 26834 26835 static void 26836 Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26837 { 26838 slotbuf[0] = 0x2581; 26839 } 26840 26841 static void 26842 Opcode_ae_sp16f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26843 { 26844 slotbuf[0] = 0x40086b; 26845 } 26846 26847 static void 26848 Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26849 { 26850 slotbuf[0] = 0x2701; 26851 } 26852 26853 static void 26854 Opcode_ae_sp16f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26855 { 26856 slotbuf[0] = 0x40089b; 26857 } 26858 26859 static void 26860 Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26861 { 26862 slotbuf[0] = 0x2d01; 26863 } 26864 26865 static void 26866 Opcode_ae_sp16f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26867 { 26868 slotbuf[0] = 0x4008cb; 26869 } 26870 26871 static void 26872 Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26873 { 26874 slotbuf[0] = 0x82d01; 26875 } 26876 26877 static void 26878 Opcode_ae_sp24s_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26879 { 26880 slotbuf[0] = 0x40004b; 26881 } 26882 26883 static void 26884 Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26885 { 26886 slotbuf[0] = 0x2f81; 26887 } 26888 26889 static void 26890 Opcode_ae_sp24s_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26891 { 26892 slotbuf[0] = 0x40007b; 26893 } 26894 26895 static void 26896 Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26897 { 26898 slotbuf[0] = 0x82d81; 26899 } 26900 26901 static void 26902 Opcode_ae_sp24s_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26903 { 26904 slotbuf[0] = 0x4000ab; 26905 } 26906 26907 static void 26908 Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26909 { 26910 slotbuf[0] = 0x82f01; 26911 } 26912 26913 static void 26914 Opcode_ae_sp24s_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26915 { 26916 slotbuf[0] = 0x4000db; 26917 } 26918 26919 static void 26920 Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26921 { 26922 slotbuf[0] = 0x82701; 26923 } 26924 26925 static void 26926 Opcode_ae_sp24f_l_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26927 { 26928 slotbuf[0] = 0x40084b; 26929 } 26930 26931 static void 26932 Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26933 { 26934 slotbuf[0] = 0x82781; 26935 } 26936 26937 static void 26938 Opcode_ae_sp24f_l_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26939 { 26940 slotbuf[0] = 0x40087b; 26941 } 26942 26943 static void 26944 Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26945 { 26946 slotbuf[0] = 0x2d81; 26947 } 26948 26949 static void 26950 Opcode_ae_sp24f_l_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26951 { 26952 slotbuf[0] = 0x4008ab; 26953 } 26954 26955 static void 26956 Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26957 { 26958 slotbuf[0] = 0x2f01; 26959 } 26960 26961 static void 26962 Opcode_ae_sp24f_l_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26963 { 26964 slotbuf[0] = 0x4008db; 26965 } 26966 26967 static void 26968 Opcode_ae_lq56_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26969 { 26970 slotbuf[0] = 0x206581; 26971 } 26972 26973 static void 26974 Opcode_ae_lq56_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 26975 { 26976 slotbuf[0] = 0x40001c; 26977 } 26978 26979 static void 26980 Opcode_ae_lq56_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26981 { 26982 slotbuf[0] = 0x406581; 26983 } 26984 26985 static void 26986 Opcode_ae_lq56_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 26987 { 26988 slotbuf[0] = 0x40021c; 26989 } 26990 26991 static void 26992 Opcode_ae_lq56_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 26993 { 26994 slotbuf[0] = 0x606581; 26995 } 26996 26997 static void 26998 Opcode_ae_lq56_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 26999 { 27000 slotbuf[0] = 0x40002c; 27001 } 27002 27003 static void 27004 Opcode_ae_lq56_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27005 { 27006 slotbuf[0] = 0x6781; 27007 } 27008 27009 static void 27010 Opcode_ae_lq56_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27011 { 27012 slotbuf[0] = 0x40022c; 27013 } 27014 27015 static void 27016 Opcode_ae_lq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27017 { 27018 slotbuf[0] = 0x6581; 27019 } 27020 27021 static void 27022 Opcode_ae_lq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 27023 { 27024 slotbuf[0] = 0x40011c; 27025 } 27026 27027 static void 27028 Opcode_ae_lq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27029 { 27030 slotbuf[0] = 0x6701; 27031 } 27032 27033 static void 27034 Opcode_ae_lq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27035 { 27036 slotbuf[0] = 0x40031c; 27037 } 27038 27039 static void 27040 Opcode_ae_lq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27041 { 27042 slotbuf[0] = 0x6d01; 27043 } 27044 27045 static void 27046 Opcode_ae_lq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 27047 { 27048 slotbuf[0] = 0x40012c; 27049 } 27050 27051 static void 27052 Opcode_ae_lq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27053 { 27054 slotbuf[0] = 0x7501; 27055 } 27056 27057 static void 27058 Opcode_ae_lq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27059 { 27060 slotbuf[0] = 0x40032c; 27061 } 27062 27063 static void 27064 Opcode_ae_sq56s_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27065 { 27066 slotbuf[0] = 0x83781; 27067 } 27068 27069 static void 27070 Opcode_ae_sq56s_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 27071 { 27072 slotbuf[0] = 0x40003c; 27073 } 27074 27075 static void 27076 Opcode_ae_sq56s_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27077 { 27078 slotbuf[0] = 0x183701; 27079 } 27080 27081 static void 27082 Opcode_ae_sq56s_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27083 { 27084 slotbuf[0] = 0x40083c; 27085 } 27086 27087 static void 27088 Opcode_ae_sq56s_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27089 { 27090 slotbuf[0] = 0x183781; 27091 } 27092 27093 static void 27094 Opcode_ae_sq56s_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 27095 { 27096 slotbuf[0] = 0x40004c; 27097 } 27098 27099 static void 27100 Opcode_ae_sq56s_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27101 { 27102 slotbuf[0] = 0x83d81; 27103 } 27104 27105 static void 27106 Opcode_ae_sq56s_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27107 { 27108 slotbuf[0] = 0x40084c; 27109 } 27110 27111 static void 27112 Opcode_ae_sq32f_i_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27113 { 27114 slotbuf[0] = 0x83581; 27115 } 27116 27117 static void 27118 Opcode_ae_sq32f_i_Slot_inst_encode (xtensa_insnbuf slotbuf) 27119 { 27120 slotbuf[0] = 0x40043c; 27121 } 27122 27123 static void 27124 Opcode_ae_sq32f_iu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27125 { 27126 slotbuf[0] = 0x83701; 27127 } 27128 27129 static void 27130 Opcode_ae_sq32f_iu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27131 { 27132 slotbuf[0] = 0x400c3c; 27133 } 27134 27135 static void 27136 Opcode_ae_sq32f_x_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27137 { 27138 slotbuf[0] = 0x83d01; 27139 } 27140 27141 static void 27142 Opcode_ae_sq32f_x_Slot_inst_encode (xtensa_insnbuf slotbuf) 27143 { 27144 slotbuf[0] = 0x40044c; 27145 } 27146 27147 static void 27148 Opcode_ae_sq32f_xu_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27149 { 27150 slotbuf[0] = 0x183581; 27151 } 27152 27153 static void 27154 Opcode_ae_sq32f_xu_Slot_inst_encode (xtensa_insnbuf slotbuf) 27155 { 27156 slotbuf[0] = 0x400c4c; 27157 } 27158 27159 static void 27160 Opcode_ae_zerop48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27161 { 27162 slotbuf[0] = 0x46001; 27163 } 27164 27165 static void 27166 Opcode_ae_movp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27167 { 27168 slotbuf[0] = 0x86001; 27169 } 27170 27171 static void 27172 Opcode_ae_movp48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27173 { 27174 slotbuf[0] = 0x86501; 27175 } 27176 27177 static void 27178 Opcode_ae_movp48_Slot_inst_encode (xtensa_insnbuf slotbuf) 27179 { 27180 slotbuf[0] = 0x40009c; 27181 } 27182 27183 static void 27184 Opcode_ae_selp24_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27185 { 27186 slotbuf[0] = 0xd081; 27187 } 27188 27189 static void 27190 Opcode_ae_selp24_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27191 { 27192 slotbuf[0] = 0x24000; 27193 } 27194 27195 static void 27196 Opcode_ae_selp24_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27197 { 27198 slotbuf[0] = 0x89001; 27199 } 27200 27201 static void 27202 Opcode_ae_selp24_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27203 { 27204 slotbuf[0] = 0x14000; 27205 } 27206 27207 static void 27208 Opcode_ae_selp24_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27209 { 27210 slotbuf[0] = 0xd001; 27211 } 27212 27213 static void 27214 Opcode_ae_selp24_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27215 { 27216 slotbuf[0] = 0xc000; 27217 } 27218 27219 static void 27220 Opcode_ae_selp24_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27221 { 27222 slotbuf[0] = 0x9081; 27223 } 27224 27225 static void 27226 Opcode_ae_selp24_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27227 { 27228 slotbuf[0] = 0x4000; 27229 } 27230 27231 static void 27232 Opcode_ae_movtp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27233 { 27234 slotbuf[0] = 0x402081; 27235 } 27236 27237 static void 27238 Opcode_ae_movfp24x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27239 { 27240 slotbuf[0] = 0x202081; 27241 } 27242 27243 static void 27244 Opcode_ae_movtp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27245 { 27246 slotbuf[0] = 0x2001; 27247 } 27248 27249 static void 27250 Opcode_ae_movfp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27251 { 27252 slotbuf[0] = 0x1001; 27253 } 27254 27255 static void 27256 Opcode_ae_movpa24x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27257 { 27258 slotbuf[0] = 0x85f01; 27259 } 27260 27261 static void 27262 Opcode_ae_movpa24x2_Slot_inst_encode (xtensa_insnbuf slotbuf) 27263 { 27264 slotbuf[0] = 0x40000c; 27265 } 27266 27267 static void 27268 Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27269 { 27270 slotbuf[0] = 0x3f81; 27271 } 27272 27273 static void 27274 Opcode_ae_truncp24a32x2_Slot_inst_encode (xtensa_insnbuf slotbuf) 27275 { 27276 slotbuf[0] = 0x40080c; 27277 } 27278 27279 static void 27280 Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27281 { 27282 slotbuf[0] = 0x83f81; 27283 } 27284 27285 static void 27286 Opcode_ae_cvta32p24_l_Slot_inst_encode (xtensa_insnbuf slotbuf) 27287 { 27288 slotbuf[0] = 0x4000bc; 27289 } 27290 27291 static void 27292 Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27293 { 27294 slotbuf[0] = 0x83f01; 27295 } 27296 27297 static void 27298 Opcode_ae_cvta32p24_h_Slot_inst_encode (xtensa_insnbuf slotbuf) 27299 { 27300 slotbuf[0] = 0x4008bc; 27301 } 27302 27303 static void 27304 Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27305 { 27306 slotbuf[0] = 0x5501; 27307 } 27308 27309 static void 27310 Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode (xtensa_insnbuf slotbuf) 27311 { 27312 slotbuf[0] = 0x4000eb; 27313 } 27314 27315 static void 27316 Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27317 { 27318 slotbuf[0] = 0x1d01; 27319 } 27320 27321 static void 27322 Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode (xtensa_insnbuf slotbuf) 27323 { 27324 slotbuf[0] = 0x4008eb; 27325 } 27326 27327 static void 27328 Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27329 { 27330 slotbuf[0] = 0x1701; 27331 } 27332 27333 static void 27334 Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode (xtensa_insnbuf slotbuf) 27335 { 27336 slotbuf[0] = 0x4000fb; 27337 } 27338 27339 static void 27340 Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27341 { 27342 slotbuf[0] = 0x1581; 27343 } 27344 27345 static void 27346 Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode (xtensa_insnbuf slotbuf) 27347 { 27348 slotbuf[0] = 0x4008fb; 27349 } 27350 27351 static void 27352 Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27353 { 27354 slotbuf[0] = 0x20005; 27355 } 27356 27357 static void 27358 Opcode_ae_truncp16_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27359 { 27360 slotbuf[0] = 0x86e01; 27361 } 27362 27363 static void 27364 Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27365 { 27366 slotbuf[0] = 0x3881; 27367 } 27368 27369 static void 27370 Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27371 { 27372 slotbuf[0] = 0x3481; 27373 } 27374 27375 static void 27376 Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27377 { 27378 slotbuf[0] = 0x3281; 27379 } 27380 27381 static void 27382 Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27383 { 27384 slotbuf[0] = 0x3081; 27385 } 27386 27387 static void 27388 Opcode_ae_roundsp16sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27389 { 27390 slotbuf[0] = 0x86401; 27391 } 27392 27393 static void 27394 Opcode_ae_roundsp16asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27395 { 27396 slotbuf[0] = 0x86201; 27397 } 27398 27399 static void 27400 Opcode_ae_zeroq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27401 { 27402 slotbuf[0] = 0x284581; 27403 } 27404 27405 static void 27406 Opcode_ae_movq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27407 { 27408 slotbuf[0] = 0x380581; 27409 } 27410 27411 static void 27412 Opcode_ae_movq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27413 { 27414 slotbuf[0] = 0xef01; 27415 } 27416 27417 static void 27418 Opcode_ae_movq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27419 { 27420 slotbuf[0] = 0x41409c; 27421 } 27422 27423 static void 27424 Opcode_ae_movtq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27425 { 27426 slotbuf[0] = 0x806f81; 27427 } 27428 27429 static void 27430 Opcode_ae_movtq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27431 { 27432 slotbuf[0] = 0x41005e; 27433 } 27434 27435 static void 27436 Opcode_ae_movfq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27437 { 27438 slotbuf[0] = 0x6f81; 27439 } 27440 27441 static void 27442 Opcode_ae_movfq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27443 { 27444 slotbuf[0] = 0x41006e; 27445 } 27446 27447 static void 27448 Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27449 { 27450 slotbuf[0] = 0x206701; 27451 } 27452 27453 static void 27454 Opcode_ae_cvtq48a32s_Slot_inst_encode (xtensa_insnbuf slotbuf) 27455 { 27456 slotbuf[0] = 0x43027e; 27457 } 27458 27459 static void 27460 Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27461 { 27462 slotbuf[0] = 0x300581; 27463 } 27464 27465 static void 27466 Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27467 { 27468 slotbuf[0] = 0x280581; 27469 } 27470 27471 static void 27472 Opcode_ae_satq48s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27473 { 27474 slotbuf[0] = 0x488605; 27475 } 27476 27477 static void 27478 Opcode_ae_truncq32_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27479 { 27480 slotbuf[0] = 0x3c0581; 27481 } 27482 27483 static void 27484 Opcode_ae_roundsq32sym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27485 { 27486 slotbuf[0] = 0x3a0581; 27487 } 27488 27489 static void 27490 Opcode_ae_roundsq32asym_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27491 { 27492 slotbuf[0] = 0x390581; 27493 } 27494 27495 static void 27496 Opcode_ae_trunca32q48_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27497 { 27498 slotbuf[0] = 0x183d81; 27499 } 27500 27501 static void 27502 Opcode_ae_trunca32q48_Slot_inst_encode (xtensa_insnbuf slotbuf) 27503 { 27504 slotbuf[0] = 0x41007e; 27505 } 27506 27507 static void 27508 Opcode_ae_movap24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27509 { 27510 slotbuf[0] = 0x1083f01; 27511 } 27512 27513 static void 27514 Opcode_ae_movap24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) 27515 { 27516 slotbuf[0] = 0x40007c; 27517 } 27518 27519 static void 27520 Opcode_ae_movap24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27521 { 27522 slotbuf[0] = 0x883f01; 27523 } 27524 27525 static void 27526 Opcode_ae_movap24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) 27527 { 27528 slotbuf[0] = 0x40087c; 27529 } 27530 27531 static void 27532 Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27533 { 27534 slotbuf[0] = 0x4083f01; 27535 } 27536 27537 static void 27538 Opcode_ae_trunca16p24s_l_Slot_inst_encode (xtensa_insnbuf slotbuf) 27539 { 27540 slotbuf[0] = 0x40008c; 27541 } 27542 27543 static void 27544 Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27545 { 27546 slotbuf[0] = 0x2083f01; 27547 } 27548 27549 static void 27550 Opcode_ae_trunca16p24s_h_Slot_inst_encode (xtensa_insnbuf slotbuf) 27551 { 27552 slotbuf[0] = 0x40088c; 27553 } 27554 27555 static void 27556 Opcode_ae_addp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27557 { 27558 slotbuf[0] = 0x1081; 27559 } 27560 27561 static void 27562 Opcode_ae_subp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27563 { 27564 slotbuf[0] = 0x89081; 27565 } 27566 27567 static void 27568 Opcode_ae_negp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27569 { 27570 slotbuf[0] = 0x16001; 27571 } 27572 27573 static void 27574 Opcode_ae_absp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27575 { 27576 slotbuf[0] = 0x6001; 27577 } 27578 27579 static void 27580 Opcode_ae_maxp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27581 { 27582 slotbuf[0] = 0x81081; 27583 } 27584 27585 static void 27586 Opcode_ae_minp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27587 { 27588 slotbuf[0] = 0x5081; 27589 } 27590 27591 static void 27592 Opcode_ae_maxbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27593 { 27594 slotbuf[0] = 0x1; 27595 } 27596 27597 static void 27598 Opcode_ae_minbp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27599 { 27600 slotbuf[0] = 0x81; 27601 } 27602 27603 static void 27604 Opcode_ae_addsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27605 { 27606 slotbuf[0] = 0x5001; 27607 } 27608 27609 static void 27610 Opcode_ae_subsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27611 { 27612 slotbuf[0] = 0x8d001; 27613 } 27614 27615 static void 27616 Opcode_ae_negsp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27617 { 27618 slotbuf[0] = 0x26001; 27619 } 27620 27621 static void 27622 Opcode_ae_abssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27623 { 27624 slotbuf[0] = 0xa001; 27625 } 27626 27627 static void 27628 Opcode_ae_andp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27629 { 27630 slotbuf[0] = 0x9001; 27631 } 27632 27633 static void 27634 Opcode_ae_nandp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27635 { 27636 slotbuf[0] = 0x85001; 27637 } 27638 27639 static void 27640 Opcode_ae_orp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27641 { 27642 slotbuf[0] = 0x85081; 27643 } 27644 27645 static void 27646 Opcode_ae_xorp48_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27647 { 27648 slotbuf[0] = 0x8d081; 27649 } 27650 27651 static void 27652 Opcode_ae_ltp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27653 { 27654 slotbuf[0] = 0x102081; 27655 } 27656 27657 static void 27658 Opcode_ae_lep24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27659 { 27660 slotbuf[0] = 0x3001; 27661 } 27662 27663 static void 27664 Opcode_ae_eqp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27665 { 27666 slotbuf[0] = 0x2081; 27667 } 27668 27669 static void 27670 Opcode_ae_addq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27671 { 27672 slotbuf[0] = 0x40005; 27673 } 27674 27675 static void 27676 Opcode_ae_subq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27677 { 27678 slotbuf[0] = 0x280605; 27679 } 27680 27681 static void 27682 Opcode_ae_negq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27683 { 27684 slotbuf[0] = 0x600605; 27685 } 27686 27687 static void 27688 Opcode_ae_absq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27689 { 27690 slotbuf[0] = 0x480605; 27691 } 27692 27693 static void 27694 Opcode_ae_maxq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27695 { 27696 slotbuf[0] = 0x100605; 27697 } 27698 27699 static void 27700 Opcode_ae_minq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27701 { 27702 slotbuf[0] = 0x200605; 27703 } 27704 27705 static void 27706 Opcode_ae_maxbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27707 { 27708 slotbuf[0] = 0x5; 27709 } 27710 27711 static void 27712 Opcode_ae_minbq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27713 { 27714 slotbuf[0] = 0x205; 27715 } 27716 27717 static void 27718 Opcode_ae_addsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27719 { 27720 slotbuf[0] = 0x605; 27721 } 27722 27723 static void 27724 Opcode_ae_subsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27725 { 27726 slotbuf[0] = 0x300605; 27727 } 27728 27729 static void 27730 Opcode_ae_negsq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27731 { 27732 slotbuf[0] = 0x484605; 27733 } 27734 27735 static void 27736 Opcode_ae_abssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27737 { 27738 slotbuf[0] = 0x500605; 27739 } 27740 27741 static void 27742 Opcode_ae_andq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27743 { 27744 slotbuf[0] = 0x80605; 27745 } 27746 27747 static void 27748 Opcode_ae_nandq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27749 { 27750 slotbuf[0] = 0x400605; 27751 } 27752 27753 static void 27754 Opcode_ae_orq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27755 { 27756 slotbuf[0] = 0x180605; 27757 } 27758 27759 static void 27760 Opcode_ae_xorq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27761 { 27762 slotbuf[0] = 0x380605; 27763 } 27764 27765 static void 27766 Opcode_ae_sllip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27767 { 27768 slotbuf[0] = 0x101; 27769 } 27770 27771 static void 27772 Opcode_ae_srlip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27773 { 27774 slotbuf[0] = 0x501; 27775 } 27776 27777 static void 27778 Opcode_ae_sraip24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27779 { 27780 slotbuf[0] = 0x301; 27781 } 27782 27783 static void 27784 Opcode_ae_sllsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27785 { 27786 slotbuf[0] = 0x86801; 27787 } 27788 27789 static void 27790 Opcode_ae_srlsp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27791 { 27792 slotbuf[0] = 0x86c01; 27793 } 27794 27795 static void 27796 Opcode_ae_srasp24_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27797 { 27798 slotbuf[0] = 0x86a01; 27799 } 27800 27801 static void 27802 Opcode_ae_sllisp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27803 { 27804 slotbuf[0] = 0x181; 27805 } 27806 27807 static void 27808 Opcode_ae_sllssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27809 { 27810 slotbuf[0] = 0x86601; 27811 } 27812 27813 static void 27814 Opcode_ae_slliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27815 { 27816 slotbuf[0] = 0x6d81; 27817 } 27818 27819 static void 27820 Opcode_ae_slliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27821 { 27822 slotbuf[0] = 0x40005c; 27823 } 27824 27825 static void 27826 Opcode_ae_srliq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27827 { 27828 slotbuf[0] = 0x16d81; 27829 } 27830 27831 static void 27832 Opcode_ae_srliq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27833 { 27834 slotbuf[0] = 0x40105c; 27835 } 27836 27837 static void 27838 Opcode_ae_sraiq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27839 { 27840 slotbuf[0] = 0xed81; 27841 } 27842 27843 static void 27844 Opcode_ae_sraiq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27845 { 27846 slotbuf[0] = 0x40205c; 27847 } 27848 27849 static void 27850 Opcode_ae_sllsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27851 { 27852 slotbuf[0] = 0x16f01; 27853 } 27854 27855 static void 27856 Opcode_ae_sllsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27857 { 27858 slotbuf[0] = 0x41009c; 27859 } 27860 27861 static void 27862 Opcode_ae_srlsq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27863 { 27864 slotbuf[0] = 0x80ef01; 27865 } 27866 27867 static void 27868 Opcode_ae_srlsq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27869 { 27870 slotbuf[0] = 0x41109c; 27871 } 27872 27873 static void 27874 Opcode_ae_srasq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27875 { 27876 slotbuf[0] = 0x4ef01; 27877 } 27878 27879 static void 27880 Opcode_ae_srasq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27881 { 27882 slotbuf[0] = 0x41209c; 27883 } 27884 27885 static void 27886 Opcode_ae_sllaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27887 { 27888 slotbuf[0] = 0x1006f81; 27889 } 27890 27891 static void 27892 Opcode_ae_sllaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27893 { 27894 slotbuf[0] = 0x41001e; 27895 } 27896 27897 static void 27898 Opcode_ae_srlaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27899 { 27900 slotbuf[0] = 0x1806f81; 27901 } 27902 27903 static void 27904 Opcode_ae_srlaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27905 { 27906 slotbuf[0] = 0x41002e; 27907 } 27908 27909 static void 27910 Opcode_ae_sraaq56_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27911 { 27912 slotbuf[0] = 0x4006f81; 27913 } 27914 27915 static void 27916 Opcode_ae_sraaq56_Slot_inst_encode (xtensa_insnbuf slotbuf) 27917 { 27918 slotbuf[0] = 0x41003e; 27919 } 27920 27921 static void 27922 Opcode_ae_sllisq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27923 { 27924 slotbuf[0] = 0x6f01; 27925 } 27926 27927 static void 27928 Opcode_ae_sllisq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) 27929 { 27930 slotbuf[0] = 0x40305c; 27931 } 27932 27933 static void 27934 Opcode_ae_sllssq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27935 { 27936 slotbuf[0] = 0x2ef01; 27937 } 27938 27939 static void 27940 Opcode_ae_sllssq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) 27941 { 27942 slotbuf[0] = 0x41309c; 27943 } 27944 27945 static void 27946 Opcode_ae_sllasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27947 { 27948 slotbuf[0] = 0x2006f81; 27949 } 27950 27951 static void 27952 Opcode_ae_sllasq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) 27953 { 27954 slotbuf[0] = 0x41004e; 27955 } 27956 27957 static void 27958 Opcode_ae_ltq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27959 { 27960 slotbuf[0] = 0x10005; 27961 } 27962 27963 static void 27964 Opcode_ae_leq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27965 { 27966 slotbuf[0] = 0x805; 27967 } 27968 27969 static void 27970 Opcode_ae_eqq56_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27971 { 27972 slotbuf[0] = 0x405; 27973 } 27974 27975 static void 27976 Opcode_ae_nsaq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 27977 { 27978 slotbuf[0] = 0x183d01; 27979 } 27980 27981 static void 27982 Opcode_ae_nsaq56s_Slot_inst_encode (xtensa_insnbuf slotbuf) 27983 { 27984 slotbuf[0] = 0x41047e; 27985 } 27986 27987 static void 27988 Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27989 { 27990 slotbuf[0] = 0x500901; 27991 } 27992 27993 static void 27994 Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 27995 { 27996 slotbuf[0] = 0x300901; 27997 } 27998 27999 static void 28000 Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28001 { 28002 slotbuf[0] = 0x600901; 28003 } 28004 28005 static void 28006 Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28007 { 28008 slotbuf[0] = 0x100901; 28009 } 28010 28011 static void 28012 Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28013 { 28014 slotbuf[0] = 0x400901; 28015 } 28016 28017 static void 28018 Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28019 { 28020 slotbuf[0] = 0x200901; 28021 } 28022 28023 static void 28024 Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28025 { 28026 slotbuf[0] = 0x680901; 28027 } 28028 28029 static void 28030 Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28031 { 28032 slotbuf[0] = 0x180901; 28033 } 28034 28035 static void 28036 Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28037 { 28038 slotbuf[0] = 0x480901; 28039 } 28040 28041 static void 28042 Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28043 { 28044 slotbuf[0] = 0x280901; 28045 } 28046 28047 static void 28048 Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28049 { 28050 slotbuf[0] = 0x700901; 28051 } 28052 28053 static void 28054 Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28055 { 28056 slotbuf[0] = 0x80901; 28057 } 28058 28059 static void 28060 Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28061 { 28062 slotbuf[0] = 0x100086; 28063 } 28064 28065 static void 28066 Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28067 { 28068 slotbuf[0] = 0x88186; 28069 } 28070 28071 static void 28072 Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28073 { 28074 slotbuf[0] = 0x180006; 28075 } 28076 28077 static void 28078 Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28079 { 28080 slotbuf[0] = 0x8c186; 28081 } 28082 28083 static void 28084 Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28085 { 28086 slotbuf[0] = 0x8c006; 28087 } 28088 28089 static void 28090 Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28091 { 28092 slotbuf[0] = 0x108006; 28093 } 28094 28095 static void 28096 Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28097 { 28098 slotbuf[0] = 0x8c106; 28099 } 28100 28101 static void 28102 Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28103 { 28104 slotbuf[0] = 0x88106; 28105 } 28106 28107 static void 28108 Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28109 { 28110 slotbuf[0] = 0x104006; 28111 } 28112 28113 static void 28114 Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28115 { 28116 slotbuf[0] = 0x8c086; 28117 } 28118 28119 static void 28120 Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28121 { 28122 slotbuf[0] = 0x88086; 28123 } 28124 28125 static void 28126 Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28127 { 28128 slotbuf[0] = 0x100106; 28129 } 28130 28131 static void 28132 Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28133 { 28134 slotbuf[0] = 0x4106; 28135 } 28136 28137 static void 28138 Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28139 { 28140 slotbuf[0] = 0x200006; 28141 } 28142 28143 static void 28144 Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28145 { 28146 slotbuf[0] = 0xc186; 28147 } 28148 28149 static void 28150 Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28151 { 28152 slotbuf[0] = 0x4086; 28153 } 28154 28155 static void 28156 Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28157 { 28158 slotbuf[0] = 0x100006; 28159 } 28160 28161 static void 28162 Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28163 { 28164 slotbuf[0] = 0xc106; 28165 } 28166 28167 static void 28168 Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28169 { 28170 slotbuf[0] = 0x186; 28171 } 28172 28173 static void 28174 Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28175 { 28176 slotbuf[0] = 0x80006; 28177 } 28178 28179 static void 28180 Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28181 { 28182 slotbuf[0] = 0xc086; 28183 } 28184 28185 static void 28186 Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28187 { 28188 slotbuf[0] = 0x400006; 28189 } 28190 28191 static void 28192 Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28193 { 28194 slotbuf[0] = 0x8006; 28195 } 28196 28197 static void 28198 Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28199 { 28200 slotbuf[0] = 0x8186; 28201 } 28202 28203 static void 28204 Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28205 { 28206 slotbuf[0] = 0x180086; 28207 } 28208 28209 static void 28210 Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28211 { 28212 slotbuf[0] = 0x108186; 28213 } 28214 28215 static void 28216 Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28217 { 28218 slotbuf[0] = 0x188086; 28219 } 28220 28221 static void 28222 Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28223 { 28224 slotbuf[0] = 0x10c186; 28225 } 28226 28227 static void 28228 Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28229 { 28230 slotbuf[0] = 0x10c006; 28231 } 28232 28233 static void 28234 Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28235 { 28236 slotbuf[0] = 0x184186; 28237 } 28238 28239 static void 28240 Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28241 { 28242 slotbuf[0] = 0x10c106; 28243 } 28244 28245 static void 28246 Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28247 { 28248 slotbuf[0] = 0x108106; 28249 } 28250 28251 static void 28252 Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28253 { 28254 slotbuf[0] = 0x184106; 28255 } 28256 28257 static void 28258 Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28259 { 28260 slotbuf[0] = 0x10c086; 28261 } 28262 28263 static void 28264 Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28265 { 28266 slotbuf[0] = 0x108086; 28267 } 28268 28269 static void 28270 Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28271 { 28272 slotbuf[0] = 0x184086; 28273 } 28274 28275 static void 28276 Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28277 { 28278 slotbuf[0] = 0xc006; 28279 } 28280 28281 static void 28282 Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28283 { 28284 slotbuf[0] = 0x88006; 28285 } 28286 28287 static void 28288 Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28289 { 28290 slotbuf[0] = 0x8106; 28291 } 28292 28293 static void 28294 Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28295 { 28296 slotbuf[0] = 0x84006; 28297 } 28298 28299 static void 28300 Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28301 { 28302 slotbuf[0] = 0x8086; 28303 } 28304 28305 static void 28306 Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28307 { 28308 slotbuf[0] = 0x80106; 28309 } 28310 28311 static void 28312 Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28313 { 28314 slotbuf[0] = 0x4186; 28315 } 28316 28317 static void 28318 Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28319 { 28320 slotbuf[0] = 0x80086; 28321 } 28322 28323 static void 28324 Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28325 { 28326 slotbuf[0] = 0x180186; 28327 } 28328 28329 static void 28330 Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28331 { 28332 slotbuf[0] = 0x18c086; 28333 } 28334 28335 static void 28336 Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28337 { 28338 slotbuf[0] = 0x188006; 28339 } 28340 28341 static void 28342 Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28343 { 28344 slotbuf[0] = 0x188186; 28345 } 28346 28347 static void 28348 Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28349 { 28350 slotbuf[0] = 0x184006; 28351 } 28352 28353 static void 28354 Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28355 { 28356 slotbuf[0] = 0x18c006; 28357 } 28358 28359 static void 28360 Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28361 { 28362 slotbuf[0] = 0x180106; 28363 } 28364 28365 static void 28366 Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28367 { 28368 slotbuf[0] = 0x188106; 28369 } 28370 28371 static void 28372 Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28373 { 28374 slotbuf[0] = 0x380381; 28375 } 28376 28377 static void 28378 Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28379 { 28380 slotbuf[0] = 0x300381; 28381 } 28382 28383 static void 28384 Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28385 { 28386 slotbuf[0] = 0x500381; 28387 } 28388 28389 static void 28390 Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28391 { 28392 slotbuf[0] = 0x480381; 28393 } 28394 28395 static void 28396 Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28397 { 28398 slotbuf[0] = 0x580381; 28399 } 28400 28401 static void 28402 Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28403 { 28404 slotbuf[0] = 0x600381; 28405 } 28406 28407 static void 28408 Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28409 { 28410 slotbuf[0] = 0x700381; 28411 } 28412 28413 static void 28414 Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28415 { 28416 slotbuf[0] = 0x680381; 28417 } 28418 28419 static void 28420 Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28421 { 28422 slotbuf[0] = 0x381; 28423 } 28424 28425 static void 28426 Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28427 { 28428 slotbuf[0] = 0x901; 28429 } 28430 28431 static void 28432 Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28433 { 28434 slotbuf[0] = 0x100381; 28435 } 28436 28437 static void 28438 Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28439 { 28440 slotbuf[0] = 0x80381; 28441 } 28442 28443 static void 28444 Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28445 { 28446 slotbuf[0] = 0x400381; 28447 } 28448 28449 static void 28450 Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28451 { 28452 slotbuf[0] = 0x200381; 28453 } 28454 28455 static void 28456 Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28457 { 28458 slotbuf[0] = 0x280381; 28459 } 28460 28461 static void 28462 Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28463 { 28464 slotbuf[0] = 0x180381; 28465 } 28466 28467 static void 28468 Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28469 { 28470 slotbuf[0] = 0x581; 28471 } 28472 28473 static void 28474 Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28475 { 28476 slotbuf[0] = 0x780381; 28477 } 28478 28479 static void 28480 Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28481 { 28482 slotbuf[0] = 0x80581; 28483 } 28484 28485 static void 28486 Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28487 { 28488 slotbuf[0] = 0x701; 28489 } 28490 28491 static void 28492 Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28493 { 28494 slotbuf[0] = 0x200581; 28495 } 28496 28497 static void 28498 Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28499 { 28500 slotbuf[0] = 0x100581; 28501 } 28502 28503 static void 28504 Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28505 { 28506 slotbuf[0] = 0x180581; 28507 } 28508 28509 static void 28510 Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28511 { 28512 slotbuf[0] = 0x400581; 28513 } 28514 28515 static void 28516 Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28517 { 28518 slotbuf[0] = 0x380002; 28519 } 28520 28521 static void 28522 Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28523 { 28524 slotbuf[0] = 0x100002; 28525 } 28526 28527 static void 28528 Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28529 { 28530 slotbuf[0] = 0x600002; 28531 } 28532 28533 static void 28534 Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28535 { 28536 slotbuf[0] = 0x180002; 28537 } 28538 28539 static void 28540 Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28541 { 28542 slotbuf[0] = 0x280002; 28543 } 28544 28545 static void 28546 Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28547 { 28548 slotbuf[0] = 0x2; 28549 } 28550 28551 static void 28552 Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28553 { 28554 slotbuf[0] = 0x480002; 28555 } 28556 28557 static void 28558 Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28559 { 28560 slotbuf[0] = 0x200002; 28561 } 28562 28563 static void 28564 Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28565 { 28566 slotbuf[0] = 0x300002; 28567 } 28568 28569 static void 28570 Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28571 { 28572 slotbuf[0] = 0x80002; 28573 } 28574 28575 static void 28576 Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28577 { 28578 slotbuf[0] = 0x500002; 28579 } 28580 28581 static void 28582 Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28583 { 28584 slotbuf[0] = 0x400002; 28585 } 28586 28587 static void 28588 Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28589 { 28590 slotbuf[0] = 0x400003; 28591 } 28592 28593 static void 28594 Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28595 { 28596 slotbuf[0] = 0x700002; 28597 } 28598 28599 static void 28600 Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28601 { 28602 slotbuf[0] = 0x300003; 28603 } 28604 28605 static void 28606 Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28607 { 28608 slotbuf[0] = 0x80003; 28609 } 28610 28611 static void 28612 Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28613 { 28614 slotbuf[0] = 0x100003; 28615 } 28616 28617 static void 28618 Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28619 { 28620 slotbuf[0] = 0x580002; 28621 } 28622 28623 static void 28624 Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28625 { 28626 slotbuf[0] = 0x180003; 28627 } 28628 28629 static void 28630 Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28631 { 28632 slotbuf[0] = 0x780002; 28633 } 28634 28635 static void 28636 Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28637 { 28638 slotbuf[0] = 0x200003; 28639 } 28640 28641 static void 28642 Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28643 { 28644 slotbuf[0] = 0x680002; 28645 } 28646 28647 static void 28648 Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28649 { 28650 slotbuf[0] = 0x280003; 28651 } 28652 28653 static void 28654 Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28655 { 28656 slotbuf[0] = 0x3; 28657 } 28658 28659 static void 28660 Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28661 { 28662 slotbuf[0] = 0x4; 28663 } 28664 28665 static void 28666 Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28667 { 28668 slotbuf[0] = 0x500003; 28669 } 28670 28671 static void 28672 Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28673 { 28674 slotbuf[0] = 0x200004; 28675 } 28676 28677 static void 28678 Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28679 { 28680 slotbuf[0] = 0x680003; 28681 } 28682 28683 static void 28684 Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28685 { 28686 slotbuf[0] = 0x700003; 28687 } 28688 28689 static void 28690 Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28691 { 28692 slotbuf[0] = 0x380003; 28693 } 28694 28695 static void 28696 Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28697 { 28698 slotbuf[0] = 0x80004; 28699 } 28700 28701 static void 28702 Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28703 { 28704 slotbuf[0] = 0x600003; 28705 } 28706 28707 static void 28708 Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28709 { 28710 slotbuf[0] = 0x780003; 28711 } 28712 28713 static void 28714 Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28715 { 28716 slotbuf[0] = 0x480003; 28717 } 28718 28719 static void 28720 Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28721 { 28722 slotbuf[0] = 0x100004; 28723 } 28724 28725 static void 28726 Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28727 { 28728 slotbuf[0] = 0x580003; 28729 } 28730 28731 static void 28732 Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28733 { 28734 slotbuf[0] = 0x580004; 28735 } 28736 28737 static void 28738 Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28739 { 28740 slotbuf[0] = 0x280004; 28741 } 28742 28743 static void 28744 Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28745 { 28746 slotbuf[0] = 0x780004; 28747 } 28748 28749 static void 28750 Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28751 { 28752 slotbuf[0] = 0x480004; 28753 } 28754 28755 static void 28756 Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28757 { 28758 slotbuf[0] = 0x500004; 28759 } 28760 28761 static void 28762 Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28763 { 28764 slotbuf[0] = 0x400004; 28765 } 28766 28767 static void 28768 Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28769 { 28770 slotbuf[0] = 0x680004; 28771 } 28772 28773 static void 28774 Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28775 { 28776 slotbuf[0] = 0x300004; 28777 } 28778 28779 static void 28780 Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28781 { 28782 slotbuf[0] = 0x600004; 28783 } 28784 28785 static void 28786 Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28787 { 28788 slotbuf[0] = 0x180004; 28789 } 28790 28791 static void 28792 Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28793 { 28794 slotbuf[0] = 0x700004; 28795 } 28796 28797 static void 28798 Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28799 { 28800 slotbuf[0] = 0x380004; 28801 } 28802 28803 static void 28804 Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28805 { 28806 slotbuf[0] = 0x204006; 28807 } 28808 28809 static void 28810 Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28811 { 28812 slotbuf[0] = 0x280006; 28813 } 28814 28815 static void 28816 Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28817 { 28818 slotbuf[0] = 0x208006; 28819 } 28820 28821 static void 28822 Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28823 { 28824 slotbuf[0] = 0x300006; 28825 } 28826 28827 static void 28828 Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28829 { 28830 slotbuf[0] = 0x200186; 28831 } 28832 28833 static void 28834 Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28835 { 28836 slotbuf[0] = 0x204106; 28837 } 28838 28839 static void 28840 Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28841 { 28842 slotbuf[0] = 0x204086; 28843 } 28844 28845 static void 28846 Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28847 { 28848 slotbuf[0] = 0x204186; 28849 } 28850 28851 static void 28852 Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28853 { 28854 slotbuf[0] = 0x208086; 28855 } 28856 28857 static void 28858 Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28859 { 28860 slotbuf[0] = 0x20c006; 28861 } 28862 28863 static void 28864 Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28865 { 28866 slotbuf[0] = 0x208106; 28867 } 28868 28869 static void 28870 Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28871 { 28872 slotbuf[0] = 0x208186; 28873 } 28874 28875 static void 28876 Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28877 { 28878 slotbuf[0] = 0x20c086; 28879 } 28880 28881 static void 28882 Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28883 { 28884 slotbuf[0] = 0x20c186; 28885 } 28886 28887 static void 28888 Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28889 { 28890 slotbuf[0] = 0x20c106; 28891 } 28892 28893 static void 28894 Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28895 { 28896 slotbuf[0] = 0x280086; 28897 } 28898 28899 static void 28900 Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28901 { 28902 slotbuf[0] = 0x6; 28903 } 28904 28905 static void 28906 Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28907 { 28908 slotbuf[0] = 0x106; 28909 } 28910 28911 static void 28912 Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28913 { 28914 slotbuf[0] = 0x86; 28915 } 28916 28917 static void 28918 Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28919 { 28920 slotbuf[0] = 0x4006; 28921 } 28922 28923 static void 28924 Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28925 { 28926 slotbuf[0] = 0x80186; 28927 } 28928 28929 static void 28930 Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28931 { 28932 slotbuf[0] = 0x84106; 28933 } 28934 28935 static void 28936 Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28937 { 28938 slotbuf[0] = 0x84086; 28939 } 28940 28941 static void 28942 Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28943 { 28944 slotbuf[0] = 0x84186; 28945 } 28946 28947 static void 28948 Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28949 { 28950 slotbuf[0] = 0x100186; 28951 } 28952 28953 static void 28954 Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28955 { 28956 slotbuf[0] = 0x104106; 28957 } 28958 28959 static void 28960 Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28961 { 28962 slotbuf[0] = 0x104086; 28963 } 28964 28965 static void 28966 Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28967 { 28968 slotbuf[0] = 0x104186; 28969 } 28970 28971 static void 28972 Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28973 { 28974 slotbuf[0] = 0x18c106; 28975 } 28976 28977 static void 28978 Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28979 { 28980 slotbuf[0] = 0x200086; 28981 } 28982 28983 static void 28984 Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28985 { 28986 slotbuf[0] = 0x18c186; 28987 } 28988 28989 static void 28990 Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 28991 { 28992 slotbuf[0] = 0x200106; 28993 } 28994 28995 static void 28996 Opcode_ae_sha32_Slot_inst_encode (xtensa_insnbuf slotbuf) 28997 { 28998 slotbuf[0] = 0x41000e; 28999 } 29000 29001 static void 29002 Opcode_ae_vldl32t_Slot_inst_encode (xtensa_insnbuf slotbuf) 29003 { 29004 slotbuf[0] = 0x40000a; 29005 } 29006 29007 static void 29008 Opcode_ae_vldl16t_Slot_inst_encode (xtensa_insnbuf slotbuf) 29009 { 29010 slotbuf[0] = 0x40001a; 29011 } 29012 29013 static void 29014 Opcode_ae_vldl16c_Slot_inst_encode (xtensa_insnbuf slotbuf) 29015 { 29016 slotbuf[0] = 0x410e7e; 29017 } 29018 29019 static void 29020 Opcode_ae_vldsht_Slot_inst_encode (xtensa_insnbuf slotbuf) 29021 { 29022 slotbuf[0] = 0x4008ac; 29023 } 29024 29025 static void 29026 Opcode_ae_lb_Slot_inst_encode (xtensa_insnbuf slotbuf) 29027 { 29028 slotbuf[0] = 0x40006c; 29029 } 29030 29031 static void 29032 Opcode_ae_lbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 29033 { 29034 slotbuf[0] = 0x42000e; 29035 } 29036 29037 static void 29038 Opcode_ae_lbk_Slot_inst_encode (xtensa_insnbuf slotbuf) 29039 { 29040 slotbuf[0] = 0x40002a; 29041 } 29042 29043 static void 29044 Opcode_ae_lbki_Slot_inst_encode (xtensa_insnbuf slotbuf) 29045 { 29046 slotbuf[0] = 0x40000e; 29047 } 29048 29049 static void 29050 Opcode_ae_db_Slot_inst_encode (xtensa_insnbuf slotbuf) 29051 { 29052 slotbuf[0] = 0x40010f; 29053 } 29054 29055 static void 29056 Opcode_ae_dbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 29057 { 29058 slotbuf[0] = 0x40020f; 29059 } 29060 29061 static void 29062 Opcode_ae_vlel32t_Slot_inst_encode (xtensa_insnbuf slotbuf) 29063 { 29064 slotbuf[0] = 0x40003a; 29065 } 29066 29067 static void 29068 Opcode_ae_vlel16t_Slot_inst_encode (xtensa_insnbuf slotbuf) 29069 { 29070 slotbuf[0] = 0x40004a; 29071 } 29072 29073 static void 29074 Opcode_ae_sb_Slot_inst_encode (xtensa_insnbuf slotbuf) 29075 { 29076 slotbuf[0] = 0x40011f; 29077 } 29078 29079 static void 29080 Opcode_ae_sbi_Slot_inst_encode (xtensa_insnbuf slotbuf) 29081 { 29082 slotbuf[0] = 0x40000f; 29083 } 29084 29085 static void 29086 Opcode_ae_vles16c_Slot_inst_encode (xtensa_insnbuf slotbuf) 29087 { 29088 slotbuf[0] = 0x410c7e; 29089 } 29090 29091 static void 29092 Opcode_ae_sbf_Slot_inst_encode (xtensa_insnbuf slotbuf) 29093 { 29094 slotbuf[0] = 0x410d7e; 29095 } 29096 29097 static void 29098 Opcode_ae_slaasq56s_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29099 { 29100 slotbuf[0] = 0x6006f81; 29101 } 29102 29103 static void 29104 Opcode_ae_addbrba32_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29105 { 29106 slotbuf[0] = 0; 29107 } 29108 29109 static void 29110 Opcode_ae_minabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 29111 { 29112 slotbuf[0] = 0x8e001; 29113 } 29114 29115 static void 29116 Opcode_ae_maxabssp24s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 29117 { 29118 slotbuf[0] = 0xe001; 29119 } 29120 29121 static void 29122 Opcode_ae_minabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 29123 { 29124 slotbuf[0] = 0x240005; 29125 } 29126 29127 static void 29128 Opcode_ae_maxabssq56s_Slot_ae_slot1_encode (xtensa_insnbuf slotbuf) 29129 { 29130 slotbuf[0] = 0x440005; 29131 } 29132 29133 static void 29134 Opcode_rur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) 29135 { 29136 slotbuf[0] = 0x6f03e; 29137 } 29138 29139 static void 29140 Opcode_wur_ae_cbegin0_Slot_inst_encode (xtensa_insnbuf slotbuf) 29141 { 29142 slotbuf[0] = 0xf63f; 29143 } 29144 29145 static void 29146 Opcode_rur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) 29147 { 29148 slotbuf[0] = 0x7f03e; 29149 } 29150 29151 static void 29152 Opcode_wur_ae_cend0_Slot_inst_encode (xtensa_insnbuf slotbuf) 29153 { 29154 slotbuf[0] = 0xf73f; 29155 } 29156 29157 static void 29158 Opcode_ae_lp24x2_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29159 { 29160 slotbuf[0] = 0x7f01; 29161 } 29162 29163 static void 29164 Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29165 { 29166 slotbuf[0] = 0x87781; 29167 } 29168 29169 static void 29170 Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29171 { 29172 slotbuf[0] = 0x87f01; 29173 } 29174 29175 static void 29176 Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29177 { 29178 slotbuf[0] = 0x7781; 29179 } 29180 29181 static void 29182 Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29183 { 29184 slotbuf[0] = 0x87d01; 29185 } 29186 29187 static void 29188 Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29189 { 29190 slotbuf[0] = 0x87581; 29191 } 29192 29193 static void 29194 Opcode_ae_lp24_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29195 { 29196 slotbuf[0] = 0x7701; 29197 } 29198 29199 static void 29200 Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29201 { 29202 slotbuf[0] = 0x87d81; 29203 } 29204 29205 static void 29206 Opcode_ae_lp24f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29207 { 29208 slotbuf[0] = 0x87701; 29209 } 29210 29211 static void 29212 Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29213 { 29214 slotbuf[0] = 0x7d81; 29215 } 29216 29217 static void 29218 Opcode_ae_lp16f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29219 { 29220 slotbuf[0] = 0x7d01; 29221 } 29222 29223 static void 29224 Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29225 { 29226 slotbuf[0] = 0x7581; 29227 } 29228 29229 static void 29230 Opcode_ae_lq56_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29231 { 29232 slotbuf[0] = 0x207501; 29233 } 29234 29235 static void 29236 Opcode_ae_sq56s_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29237 { 29238 slotbuf[0] = 0x87f81; 29239 } 29240 29241 static void 29242 Opcode_ae_lq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29243 { 29244 slotbuf[0] = 0x407501; 29245 } 29246 29247 static void 29248 Opcode_ae_sq32f_c_Slot_ae_slot0_encode (xtensa_insnbuf slotbuf) 29249 { 29250 slotbuf[0] = 0x7f81; 29251 } 29252 29253 static void 29254 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 29255 { 29256 slotbuf[0] = 0x6e03e; 29257 } 29258 29259 static void 29260 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 29261 { 29262 slotbuf[0] = 0xe63f; 29263 } 29264 29265 static void 29266 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf) 29267 { 29268 slotbuf[0] = 0xe0; 29269 } 29270 29271 static void 29272 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 29273 { 29274 slotbuf[0] = 0x1e0; 29275 } 29276 29277 static void 29278 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 29279 { 29280 slotbuf[0] = 0x21e0; 29281 } 29282 29283 static void 29284 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf) 29285 { 29286 slotbuf[0] = 0x2e0; 29287 } 29288 29289 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = { 29290 Opcode_excw_Slot_inst_encode, 0, 0, 0, 0 29291 }; 29292 29293 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = { 29294 Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0 29295 }; 29296 29297 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = { 29298 Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0 29299 }; 29300 29301 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = { 29302 Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0 29303 }; 29304 29305 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = { 29306 Opcode_call12_Slot_inst_encode, 0, 0, 0, 0 29307 }; 29308 29309 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = { 29310 Opcode_call8_Slot_inst_encode, 0, 0, 0, 0 29311 }; 29312 29313 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = { 29314 Opcode_call4_Slot_inst_encode, 0, 0, 0, 0 29315 }; 29316 29317 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = { 29318 Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0 29319 }; 29320 29321 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = { 29322 Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0 29323 }; 29324 29325 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = { 29326 Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0 29327 }; 29328 29329 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = { 29330 Opcode_entry_Slot_inst_encode, 0, 0, 0, 0 29331 }; 29332 29333 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = { 29334 Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0 29335 }; 29336 29337 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = { 29338 Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0 29339 }; 29340 29341 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = { 29342 Opcode_retw_Slot_inst_encode, 0, 0, 0, 0 29343 }; 29344 29345 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = { 29346 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0 29347 }; 29348 29349 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = { 29350 Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0 29351 }; 29352 29353 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = { 29354 Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0 29355 }; 29356 29357 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = { 29358 Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0 29359 }; 29360 29361 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = { 29362 Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0 29363 }; 29364 29365 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = { 29366 Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 29367 }; 29368 29369 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = { 29370 Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 29371 }; 29372 29373 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = { 29374 Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0 29375 }; 29376 29377 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = { 29378 Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 29379 }; 29380 29381 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = { 29382 Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 29383 }; 29384 29385 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = { 29386 Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0 29387 }; 29388 29389 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = { 29390 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0 29391 }; 29392 29393 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = { 29394 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0 29395 }; 29396 29397 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = { 29398 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0 29399 }; 29400 29401 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = { 29402 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0 29403 }; 29404 29405 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = { 29406 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0 29407 }; 29408 29409 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = { 29410 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0 29411 }; 29412 29413 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = { 29414 0, 0, Opcode_mov_n_Slot_inst16b_encode, 0, 0 29415 }; 29416 29417 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = { 29418 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0 29419 }; 29420 29421 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = { 29422 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0 29423 }; 29424 29425 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = { 29426 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0 29427 }; 29428 29429 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = { 29430 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0 29431 }; 29432 29433 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = { 29434 Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0 29435 }; 29436 29437 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = { 29438 Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0 29439 }; 29440 29441 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = { 29442 Opcode_addi_Slot_inst_encode, 0, 0, 0, Opcode_addi_Slot_ae_slot0_encode 29443 }; 29444 29445 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = { 29446 Opcode_addmi_Slot_inst_encode, 0, 0, 0, Opcode_addmi_Slot_ae_slot0_encode 29447 }; 29448 29449 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = { 29450 Opcode_add_Slot_inst_encode, 0, 0, 0, Opcode_add_Slot_ae_slot0_encode 29451 }; 29452 29453 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = { 29454 Opcode_sub_Slot_inst_encode, 0, 0, 0, Opcode_sub_Slot_ae_slot0_encode 29455 }; 29456 29457 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = { 29458 Opcode_addx2_Slot_inst_encode, 0, 0, 0, Opcode_addx2_Slot_ae_slot0_encode 29459 }; 29460 29461 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = { 29462 Opcode_addx4_Slot_inst_encode, 0, 0, 0, Opcode_addx4_Slot_ae_slot0_encode 29463 }; 29464 29465 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = { 29466 Opcode_addx8_Slot_inst_encode, 0, 0, 0, Opcode_addx8_Slot_ae_slot0_encode 29467 }; 29468 29469 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = { 29470 Opcode_subx2_Slot_inst_encode, 0, 0, 0, Opcode_subx2_Slot_ae_slot0_encode 29471 }; 29472 29473 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = { 29474 Opcode_subx4_Slot_inst_encode, 0, 0, 0, Opcode_subx4_Slot_ae_slot0_encode 29475 }; 29476 29477 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = { 29478 Opcode_subx8_Slot_inst_encode, 0, 0, 0, Opcode_subx8_Slot_ae_slot0_encode 29479 }; 29480 29481 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = { 29482 Opcode_and_Slot_inst_encode, 0, 0, 0, Opcode_and_Slot_ae_slot0_encode 29483 }; 29484 29485 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = { 29486 Opcode_or_Slot_inst_encode, 0, 0, 0, Opcode_or_Slot_ae_slot0_encode 29487 }; 29488 29489 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = { 29490 Opcode_xor_Slot_inst_encode, 0, 0, 0, Opcode_xor_Slot_ae_slot0_encode 29491 }; 29492 29493 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = { 29494 Opcode_beqi_Slot_inst_encode, 0, 0, 0, Opcode_beqi_Slot_ae_slot0_encode 29495 }; 29496 29497 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = { 29498 Opcode_bnei_Slot_inst_encode, 0, 0, 0, Opcode_bnei_Slot_ae_slot0_encode 29499 }; 29500 29501 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = { 29502 Opcode_bgei_Slot_inst_encode, 0, 0, 0, Opcode_bgei_Slot_ae_slot0_encode 29503 }; 29504 29505 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = { 29506 Opcode_blti_Slot_inst_encode, 0, 0, 0, Opcode_blti_Slot_ae_slot0_encode 29507 }; 29508 29509 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = { 29510 Opcode_bbci_Slot_inst_encode, 0, 0, 0, Opcode_bbci_Slot_ae_slot0_encode 29511 }; 29512 29513 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = { 29514 Opcode_bbsi_Slot_inst_encode, 0, 0, 0, Opcode_bbsi_Slot_ae_slot0_encode 29515 }; 29516 29517 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = { 29518 Opcode_bgeui_Slot_inst_encode, 0, 0, 0, Opcode_bgeui_Slot_ae_slot0_encode 29519 }; 29520 29521 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = { 29522 Opcode_bltui_Slot_inst_encode, 0, 0, 0, Opcode_bltui_Slot_ae_slot0_encode 29523 }; 29524 29525 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = { 29526 Opcode_beq_Slot_inst_encode, 0, 0, 0, Opcode_beq_Slot_ae_slot0_encode 29527 }; 29528 29529 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = { 29530 Opcode_bne_Slot_inst_encode, 0, 0, 0, Opcode_bne_Slot_ae_slot0_encode 29531 }; 29532 29533 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = { 29534 Opcode_bge_Slot_inst_encode, 0, 0, 0, Opcode_bge_Slot_ae_slot0_encode 29535 }; 29536 29537 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = { 29538 Opcode_blt_Slot_inst_encode, 0, 0, 0, Opcode_blt_Slot_ae_slot0_encode 29539 }; 29540 29541 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = { 29542 Opcode_bgeu_Slot_inst_encode, 0, 0, 0, Opcode_bgeu_Slot_ae_slot0_encode 29543 }; 29544 29545 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = { 29546 Opcode_bltu_Slot_inst_encode, 0, 0, 0, Opcode_bltu_Slot_ae_slot0_encode 29547 }; 29548 29549 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = { 29550 Opcode_bany_Slot_inst_encode, 0, 0, 0, Opcode_bany_Slot_ae_slot0_encode 29551 }; 29552 29553 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = { 29554 Opcode_bnone_Slot_inst_encode, 0, 0, 0, Opcode_bnone_Slot_ae_slot0_encode 29555 }; 29556 29557 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = { 29558 Opcode_ball_Slot_inst_encode, 0, 0, 0, Opcode_ball_Slot_ae_slot0_encode 29559 }; 29560 29561 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = { 29562 Opcode_bnall_Slot_inst_encode, 0, 0, 0, Opcode_bnall_Slot_ae_slot0_encode 29563 }; 29564 29565 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = { 29566 Opcode_bbc_Slot_inst_encode, 0, 0, 0, Opcode_bbc_Slot_ae_slot0_encode 29567 }; 29568 29569 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = { 29570 Opcode_bbs_Slot_inst_encode, 0, 0, 0, Opcode_bbs_Slot_ae_slot0_encode 29571 }; 29572 29573 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = { 29574 Opcode_beqz_Slot_inst_encode, 0, 0, 0, Opcode_beqz_Slot_ae_slot0_encode 29575 }; 29576 29577 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = { 29578 Opcode_bnez_Slot_inst_encode, 0, 0, 0, Opcode_bnez_Slot_ae_slot0_encode 29579 }; 29580 29581 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = { 29582 Opcode_bgez_Slot_inst_encode, 0, 0, 0, Opcode_bgez_Slot_ae_slot0_encode 29583 }; 29584 29585 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = { 29586 Opcode_bltz_Slot_inst_encode, 0, 0, 0, Opcode_bltz_Slot_ae_slot0_encode 29587 }; 29588 29589 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = { 29590 Opcode_call0_Slot_inst_encode, 0, 0, 0, 0 29591 }; 29592 29593 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = { 29594 Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0 29595 }; 29596 29597 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = { 29598 Opcode_extui_Slot_inst_encode, 0, 0, 0, Opcode_extui_Slot_ae_slot0_encode 29599 }; 29600 29601 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = { 29602 Opcode_ill_Slot_inst_encode, 0, 0, 0, 0 29603 }; 29604 29605 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = { 29606 Opcode_j_Slot_inst_encode, 0, 0, 0, Opcode_j_Slot_ae_slot0_encode 29607 }; 29608 29609 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = { 29610 Opcode_jx_Slot_inst_encode, 0, 0, 0, Opcode_jx_Slot_ae_slot0_encode 29611 }; 29612 29613 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = { 29614 Opcode_l16ui_Slot_inst_encode, 0, 0, 0, Opcode_l16ui_Slot_ae_slot0_encode 29615 }; 29616 29617 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = { 29618 Opcode_l16si_Slot_inst_encode, 0, 0, 0, Opcode_l16si_Slot_ae_slot0_encode 29619 }; 29620 29621 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = { 29622 Opcode_l32i_Slot_inst_encode, 0, 0, 0, Opcode_l32i_Slot_ae_slot0_encode 29623 }; 29624 29625 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = { 29626 Opcode_l32r_Slot_inst_encode, 0, 0, 0, Opcode_l32r_Slot_ae_slot0_encode 29627 }; 29628 29629 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = { 29630 Opcode_l8ui_Slot_inst_encode, 0, 0, 0, Opcode_l8ui_Slot_ae_slot0_encode 29631 }; 29632 29633 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = { 29634 Opcode_loop_Slot_inst_encode, 0, 0, 0, 0 29635 }; 29636 29637 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = { 29638 Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0 29639 }; 29640 29641 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = { 29642 Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0 29643 }; 29644 29645 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = { 29646 Opcode_movi_Slot_inst_encode, 0, 0, 0, Opcode_movi_Slot_ae_slot0_encode 29647 }; 29648 29649 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = { 29650 Opcode_moveqz_Slot_inst_encode, 0, 0, 0, Opcode_moveqz_Slot_ae_slot0_encode 29651 }; 29652 29653 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = { 29654 Opcode_movnez_Slot_inst_encode, 0, 0, 0, Opcode_movnez_Slot_ae_slot0_encode 29655 }; 29656 29657 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = { 29658 Opcode_movltz_Slot_inst_encode, 0, 0, 0, Opcode_movltz_Slot_ae_slot0_encode 29659 }; 29660 29661 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = { 29662 Opcode_movgez_Slot_inst_encode, 0, 0, 0, Opcode_movgez_Slot_ae_slot0_encode 29663 }; 29664 29665 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = { 29666 Opcode_neg_Slot_inst_encode, 0, 0, 0, Opcode_neg_Slot_ae_slot0_encode 29667 }; 29668 29669 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = { 29670 Opcode_abs_Slot_inst_encode, 0, 0, 0, Opcode_abs_Slot_ae_slot0_encode 29671 }; 29672 29673 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = { 29674 Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_ae_slot1_encode, Opcode_nop_Slot_ae_slot0_encode 29675 }; 29676 29677 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = { 29678 Opcode_ret_Slot_inst_encode, 0, 0, 0, 0 29679 }; 29680 29681 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = { 29682 Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0 29683 }; 29684 29685 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = { 29686 Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode 29687 }; 29688 29689 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = { 29690 Opcode_s32i_Slot_inst_encode, 0, 0, 0, Opcode_s32i_Slot_ae_slot0_encode 29691 }; 29692 29693 static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = { 29694 Opcode_s32nb_Slot_inst_encode, 0, 0, 0, 0 29695 }; 29696 29697 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = { 29698 Opcode_s8i_Slot_inst_encode, 0, 0, 0, Opcode_s8i_Slot_ae_slot0_encode 29699 }; 29700 29701 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = { 29702 Opcode_ssr_Slot_inst_encode, 0, 0, 0, Opcode_ssr_Slot_ae_slot0_encode 29703 }; 29704 29705 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = { 29706 Opcode_ssl_Slot_inst_encode, 0, 0, 0, Opcode_ssl_Slot_ae_slot0_encode 29707 }; 29708 29709 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = { 29710 Opcode_ssa8l_Slot_inst_encode, 0, 0, 0, Opcode_ssa8l_Slot_ae_slot0_encode 29711 }; 29712 29713 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = { 29714 Opcode_ssa8b_Slot_inst_encode, 0, 0, 0, Opcode_ssa8b_Slot_ae_slot0_encode 29715 }; 29716 29717 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = { 29718 Opcode_ssai_Slot_inst_encode, 0, 0, 0, Opcode_ssai_Slot_ae_slot0_encode 29719 }; 29720 29721 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = { 29722 Opcode_sll_Slot_inst_encode, 0, 0, 0, Opcode_sll_Slot_ae_slot0_encode 29723 }; 29724 29725 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = { 29726 Opcode_src_Slot_inst_encode, 0, 0, 0, Opcode_src_Slot_ae_slot0_encode 29727 }; 29728 29729 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = { 29730 Opcode_srl_Slot_inst_encode, 0, 0, 0, Opcode_srl_Slot_ae_slot0_encode 29731 }; 29732 29733 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = { 29734 Opcode_sra_Slot_inst_encode, 0, 0, 0, Opcode_sra_Slot_ae_slot0_encode 29735 }; 29736 29737 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = { 29738 Opcode_slli_Slot_inst_encode, 0, 0, 0, Opcode_slli_Slot_ae_slot0_encode 29739 }; 29740 29741 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = { 29742 Opcode_srai_Slot_inst_encode, 0, 0, 0, Opcode_srai_Slot_ae_slot0_encode 29743 }; 29744 29745 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = { 29746 Opcode_srli_Slot_inst_encode, 0, 0, 0, Opcode_srli_Slot_ae_slot0_encode 29747 }; 29748 29749 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = { 29750 Opcode_memw_Slot_inst_encode, 0, 0, 0, 0 29751 }; 29752 29753 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = { 29754 Opcode_extw_Slot_inst_encode, 0, 0, 0, 0 29755 }; 29756 29757 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = { 29758 Opcode_isync_Slot_inst_encode, 0, 0, 0, 0 29759 }; 29760 29761 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = { 29762 Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0 29763 }; 29764 29765 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = { 29766 Opcode_esync_Slot_inst_encode, 0, 0, 0, 0 29767 }; 29768 29769 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = { 29770 Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0 29771 }; 29772 29773 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = { 29774 Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0 29775 }; 29776 29777 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = { 29778 Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0 29779 }; 29780 29781 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = { 29782 Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0 29783 }; 29784 29785 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = { 29786 Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0 29787 }; 29788 29789 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = { 29790 Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0 29791 }; 29792 29793 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = { 29794 Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0 29795 }; 29796 29797 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = { 29798 Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0 29799 }; 29800 29801 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = { 29802 Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 29803 }; 29804 29805 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = { 29806 Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 29807 }; 29808 29809 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = { 29810 Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0 29811 }; 29812 29813 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = { 29814 Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0 29815 }; 29816 29817 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = { 29818 Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0 29819 }; 29820 29821 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = { 29822 Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0 29823 }; 29824 29825 static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = { 29826 Opcode_rsr_memctl_Slot_inst_encode, 0, 0, 0, 0 29827 }; 29828 29829 static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = { 29830 Opcode_wsr_memctl_Slot_inst_encode, 0, 0, 0, 0 29831 }; 29832 29833 static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = { 29834 Opcode_xsr_memctl_Slot_inst_encode, 0, 0, 0, 0 29835 }; 29836 29837 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = { 29838 Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0 29839 }; 29840 29841 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = { 29842 Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0 29843 }; 29844 29845 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = { 29846 Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0 29847 }; 29848 29849 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = { 29850 Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0 29851 }; 29852 29853 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = { 29854 Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0 29855 }; 29856 29857 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = { 29858 Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0 29859 }; 29860 29861 static xtensa_opcode_encode_fn Opcode_rsr_243_encode_fns[] = { 29862 Opcode_rsr_243_Slot_inst_encode, 0, 0, 0, 0 29863 }; 29864 29865 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = { 29866 Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0 29867 }; 29868 29869 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = { 29870 Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0 29871 }; 29872 29873 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = { 29874 Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0 29875 }; 29876 29877 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = { 29878 Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0 29879 }; 29880 29881 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = { 29882 Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0 29883 }; 29884 29885 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = { 29886 Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0 29887 }; 29888 29889 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = { 29890 Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 29891 }; 29892 29893 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = { 29894 Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 29895 }; 29896 29897 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = { 29898 Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0 29899 }; 29900 29901 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = { 29902 Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0 29903 }; 29904 29905 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = { 29906 Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0 29907 }; 29908 29909 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = { 29910 Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0 29911 }; 29912 29913 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = { 29914 Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 29915 }; 29916 29917 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = { 29918 Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 29919 }; 29920 29921 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = { 29922 Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0 29923 }; 29924 29925 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = { 29926 Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0 29927 }; 29928 29929 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = { 29930 Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0 29931 }; 29932 29933 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = { 29934 Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0 29935 }; 29936 29937 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = { 29938 Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 29939 }; 29940 29941 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = { 29942 Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 29943 }; 29944 29945 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = { 29946 Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0 29947 }; 29948 29949 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = { 29950 Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0 29951 }; 29952 29953 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = { 29954 Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0 29955 }; 29956 29957 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = { 29958 Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0 29959 }; 29960 29961 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = { 29962 Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 29963 }; 29964 29965 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = { 29966 Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 29967 }; 29968 29969 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = { 29970 Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0 29971 }; 29972 29973 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = { 29974 Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0 29975 }; 29976 29977 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = { 29978 Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0 29979 }; 29980 29981 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = { 29982 Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0 29983 }; 29984 29985 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = { 29986 Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 29987 }; 29988 29989 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = { 29990 Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 29991 }; 29992 29993 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = { 29994 Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0 29995 }; 29996 29997 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = { 29998 Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0 29999 }; 30000 30001 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = { 30002 Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0 30003 }; 30004 30005 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = { 30006 Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0 30007 }; 30008 30009 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = { 30010 Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 30011 }; 30012 30013 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = { 30014 Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 30015 }; 30016 30017 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = { 30018 Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0 30019 }; 30020 30021 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = { 30022 Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0 30023 }; 30024 30025 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = { 30026 Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0 30027 }; 30028 30029 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = { 30030 Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0 30031 }; 30032 30033 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = { 30034 Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 30035 }; 30036 30037 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = { 30038 Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 30039 }; 30040 30041 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = { 30042 Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0 30043 }; 30044 30045 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = { 30046 Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0 30047 }; 30048 30049 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = { 30050 Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0 30051 }; 30052 30053 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = { 30054 Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0 30055 }; 30056 30057 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = { 30058 Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0 30059 }; 30060 30061 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = { 30062 Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0 30063 }; 30064 30065 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = { 30066 Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0 30067 }; 30068 30069 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = { 30070 Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0 30071 }; 30072 30073 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = { 30074 Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0 30075 }; 30076 30077 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = { 30078 Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0 30079 }; 30080 30081 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = { 30082 Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0 30083 }; 30084 30085 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = { 30086 Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0 30087 }; 30088 30089 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = { 30090 Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0 30091 }; 30092 30093 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = { 30094 Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0 30095 }; 30096 30097 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = { 30098 Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0 30099 }; 30100 30101 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = { 30102 Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0 30103 }; 30104 30105 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = { 30106 Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0 30107 }; 30108 30109 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = { 30110 Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0 30111 }; 30112 30113 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = { 30114 Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0 30115 }; 30116 30117 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = { 30118 Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 30119 }; 30120 30121 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = { 30122 Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 30123 }; 30124 30125 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = { 30126 Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0 30127 }; 30128 30129 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = { 30130 Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0 30131 }; 30132 30133 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = { 30134 Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0 30135 }; 30136 30137 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = { 30138 Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0 30139 }; 30140 30141 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = { 30142 Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0 30143 }; 30144 30145 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = { 30146 Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0 30147 }; 30148 30149 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = { 30150 Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0 30151 }; 30152 30153 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = { 30154 Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0 30155 }; 30156 30157 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = { 30158 Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0 30159 }; 30160 30161 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = { 30162 Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0 30163 }; 30164 30165 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = { 30166 Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0 30167 }; 30168 30169 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = { 30170 Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0 30171 }; 30172 30173 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = { 30174 Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0 30175 }; 30176 30177 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = { 30178 Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0 30179 }; 30180 30181 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = { 30182 Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 30183 }; 30184 30185 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = { 30186 Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 30187 }; 30188 30189 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = { 30190 Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0 30191 }; 30192 30193 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = { 30194 Opcode_mul16u_Slot_inst_encode, 0, 0, 0, 0 30195 }; 30196 30197 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = { 30198 Opcode_mul16s_Slot_inst_encode, 0, 0, 0, 0 30199 }; 30200 30201 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = { 30202 Opcode_mull_Slot_inst_encode, 0, 0, 0, 0 30203 }; 30204 30205 static xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = { 30206 Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0 30207 }; 30208 30209 static xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = { 30210 Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0 30211 }; 30212 30213 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = { 30214 Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 30215 }; 30216 30217 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = { 30218 Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 30219 }; 30220 30221 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = { 30222 Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 30223 }; 30224 30225 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = { 30226 Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 30227 }; 30228 30229 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = { 30230 Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0 30231 }; 30232 30233 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = { 30234 Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0 30235 }; 30236 30237 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = { 30238 Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0 30239 }; 30240 30241 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = { 30242 Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0 30243 }; 30244 30245 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = { 30246 Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0 30247 }; 30248 30249 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = { 30250 Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0 30251 }; 30252 30253 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = { 30254 Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0 30255 }; 30256 30257 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = { 30258 Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0 30259 }; 30260 30261 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = { 30262 Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0 30263 }; 30264 30265 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = { 30266 Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0 30267 }; 30268 30269 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = { 30270 Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0 30271 }; 30272 30273 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = { 30274 Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0 30275 }; 30276 30277 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = { 30278 Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0 30279 }; 30280 30281 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = { 30282 Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0 30283 }; 30284 30285 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = { 30286 Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0 30287 }; 30288 30289 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = { 30290 Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0 30291 }; 30292 30293 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = { 30294 Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0 30295 }; 30296 30297 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = { 30298 Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0 30299 }; 30300 30301 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = { 30302 Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0 30303 }; 30304 30305 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = { 30306 Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0 30307 }; 30308 30309 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = { 30310 Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0 30311 }; 30312 30313 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = { 30314 Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0 30315 }; 30316 30317 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = { 30318 Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0 30319 }; 30320 30321 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = { 30322 Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0 30323 }; 30324 30325 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = { 30326 Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0 30327 }; 30328 30329 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = { 30330 Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0 30331 }; 30332 30333 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = { 30334 Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0 30335 }; 30336 30337 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = { 30338 Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0 30339 }; 30340 30341 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = { 30342 Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0 30343 }; 30344 30345 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = { 30346 Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0 30347 }; 30348 30349 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = { 30350 Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0 30351 }; 30352 30353 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = { 30354 Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0 30355 }; 30356 30357 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = { 30358 Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0 30359 }; 30360 30361 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = { 30362 Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0 30363 }; 30364 30365 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = { 30366 Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0 30367 }; 30368 30369 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = { 30370 Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0 30371 }; 30372 30373 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = { 30374 Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0 30375 }; 30376 30377 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = { 30378 Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0 30379 }; 30380 30381 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = { 30382 Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0 30383 }; 30384 30385 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = { 30386 Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0 30387 }; 30388 30389 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = { 30390 Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0 30391 }; 30392 30393 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = { 30394 Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0 30395 }; 30396 30397 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = { 30398 Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0 30399 }; 30400 30401 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = { 30402 Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0 30403 }; 30404 30405 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = { 30406 Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0 30407 }; 30408 30409 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = { 30410 Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0 30411 }; 30412 30413 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = { 30414 Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0 30415 }; 30416 30417 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = { 30418 Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0 30419 }; 30420 30421 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = { 30422 Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 30423 }; 30424 30425 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = { 30426 Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 30427 }; 30428 30429 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = { 30430 Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 30431 }; 30432 30433 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = { 30434 Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 30435 }; 30436 30437 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = { 30438 Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 30439 }; 30440 30441 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = { 30442 Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 30443 }; 30444 30445 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = { 30446 Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 30447 }; 30448 30449 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = { 30450 Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 30451 }; 30452 30453 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = { 30454 Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0 30455 }; 30456 30457 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = { 30458 Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0 30459 }; 30460 30461 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = { 30462 Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0 30463 }; 30464 30465 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = { 30466 Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0 30467 }; 30468 30469 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = { 30470 Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0 30471 }; 30472 30473 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = { 30474 Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0 30475 }; 30476 30477 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = { 30478 Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0 30479 }; 30480 30481 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = { 30482 Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0 30483 }; 30484 30485 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = { 30486 Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0 30487 }; 30488 30489 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = { 30490 Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0 30491 }; 30492 30493 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = { 30494 Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0 30495 }; 30496 30497 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = { 30498 Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0 30499 }; 30500 30501 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = { 30502 Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0 30503 }; 30504 30505 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = { 30506 Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0 30507 }; 30508 30509 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = { 30510 Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0 30511 }; 30512 30513 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = { 30514 Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0 30515 }; 30516 30517 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = { 30518 Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0 30519 }; 30520 30521 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = { 30522 Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0 30523 }; 30524 30525 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = { 30526 Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0 30527 }; 30528 30529 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = { 30530 Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0 30531 }; 30532 30533 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = { 30534 Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0 30535 }; 30536 30537 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = { 30538 Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0 30539 }; 30540 30541 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = { 30542 Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0 30543 }; 30544 30545 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = { 30546 Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0 30547 }; 30548 30549 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = { 30550 Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0 30551 }; 30552 30553 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = { 30554 Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0 30555 }; 30556 30557 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = { 30558 Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0 30559 }; 30560 30561 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = { 30562 Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0 30563 }; 30564 30565 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = { 30566 Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0 30567 }; 30568 30569 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = { 30570 Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0 30571 }; 30572 30573 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = { 30574 Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0 30575 }; 30576 30577 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = { 30578 Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0 30579 }; 30580 30581 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = { 30582 Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0 30583 }; 30584 30585 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = { 30586 Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0 30587 }; 30588 30589 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = { 30590 Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0 30591 }; 30592 30593 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = { 30594 Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0 30595 }; 30596 30597 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = { 30598 Opcode_break_Slot_inst_encode, 0, 0, 0, 0 30599 }; 30600 30601 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = { 30602 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0 30603 }; 30604 30605 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = { 30606 Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 30607 }; 30608 30609 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = { 30610 Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 30611 }; 30612 30613 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = { 30614 Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0 30615 }; 30616 30617 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = { 30618 Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 30619 }; 30620 30621 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = { 30622 Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 30623 }; 30624 30625 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = { 30626 Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0 30627 }; 30628 30629 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = { 30630 Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 30631 }; 30632 30633 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = { 30634 Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 30635 }; 30636 30637 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = { 30638 Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0 30639 }; 30640 30641 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = { 30642 Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 30643 }; 30644 30645 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = { 30646 Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 30647 }; 30648 30649 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = { 30650 Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0 30651 }; 30652 30653 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = { 30654 Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 30655 }; 30656 30657 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = { 30658 Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 30659 }; 30660 30661 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = { 30662 Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0 30663 }; 30664 30665 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = { 30666 Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 30667 }; 30668 30669 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = { 30670 Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 30671 }; 30672 30673 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = { 30674 Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0 30675 }; 30676 30677 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = { 30678 Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 30679 }; 30680 30681 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = { 30682 Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 30683 }; 30684 30685 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = { 30686 Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0 30687 }; 30688 30689 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = { 30690 Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 30691 }; 30692 30693 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = { 30694 Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 30695 }; 30696 30697 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = { 30698 Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0 30699 }; 30700 30701 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = { 30702 Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0 30703 }; 30704 30705 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = { 30706 Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0 30707 }; 30708 30709 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = { 30710 Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0 30711 }; 30712 30713 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = { 30714 Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 30715 }; 30716 30717 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = { 30718 Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 30719 }; 30720 30721 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = { 30722 Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0 30723 }; 30724 30725 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = { 30726 Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0 30727 }; 30728 30729 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = { 30730 Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0 30731 }; 30732 30733 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = { 30734 Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0 30735 }; 30736 30737 static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = { 30738 Opcode_lddr32_p_Slot_inst_encode, 0, 0, 0, 0 30739 }; 30740 30741 static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = { 30742 Opcode_sddr32_p_Slot_inst_encode, 0, 0, 0, 0 30743 }; 30744 30745 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = { 30746 Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0 30747 }; 30748 30749 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = { 30750 Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0 30751 }; 30752 30753 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = { 30754 Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0 30755 }; 30756 30757 static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = { 30758 Opcode_andb_Slot_inst_encode, 0, 0, 0, Opcode_andb_Slot_ae_slot0_encode 30759 }; 30760 30761 static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = { 30762 Opcode_andbc_Slot_inst_encode, 0, 0, 0, Opcode_andbc_Slot_ae_slot0_encode 30763 }; 30764 30765 static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = { 30766 Opcode_orb_Slot_inst_encode, 0, 0, 0, Opcode_orb_Slot_ae_slot0_encode 30767 }; 30768 30769 static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = { 30770 Opcode_orbc_Slot_inst_encode, 0, 0, 0, Opcode_orbc_Slot_ae_slot0_encode 30771 }; 30772 30773 static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = { 30774 Opcode_xorb_Slot_inst_encode, 0, 0, 0, Opcode_xorb_Slot_ae_slot0_encode 30775 }; 30776 30777 static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = { 30778 Opcode_any4_Slot_inst_encode, 0, 0, 0, Opcode_any4_Slot_ae_slot0_encode 30779 }; 30780 30781 static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = { 30782 Opcode_all4_Slot_inst_encode, 0, 0, 0, Opcode_all4_Slot_ae_slot0_encode 30783 }; 30784 30785 static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = { 30786 Opcode_any8_Slot_inst_encode, 0, 0, 0, Opcode_any8_Slot_ae_slot0_encode 30787 }; 30788 30789 static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = { 30790 Opcode_all8_Slot_inst_encode, 0, 0, 0, Opcode_all8_Slot_ae_slot0_encode 30791 }; 30792 30793 static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = { 30794 Opcode_bf_Slot_inst_encode, 0, 0, 0, Opcode_bf_Slot_ae_slot0_encode 30795 }; 30796 30797 static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = { 30798 Opcode_bt_Slot_inst_encode, 0, 0, 0, Opcode_bt_Slot_ae_slot0_encode 30799 }; 30800 30801 static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = { 30802 Opcode_movf_Slot_inst_encode, 0, 0, 0, Opcode_movf_Slot_ae_slot0_encode 30803 }; 30804 30805 static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = { 30806 Opcode_movt_Slot_inst_encode, 0, 0, 0, Opcode_movt_Slot_ae_slot0_encode 30807 }; 30808 30809 static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = { 30810 Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0 30811 }; 30812 30813 static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = { 30814 Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0 30815 }; 30816 30817 static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = { 30818 Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0 30819 }; 30820 30821 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = { 30822 Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0 30823 }; 30824 30825 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = { 30826 Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0 30827 }; 30828 30829 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = { 30830 Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0 30831 }; 30832 30833 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = { 30834 Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 30835 }; 30836 30837 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = { 30838 Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 30839 }; 30840 30841 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = { 30842 Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0 30843 }; 30844 30845 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = { 30846 Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 30847 }; 30848 30849 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = { 30850 Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 30851 }; 30852 30853 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = { 30854 Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0 30855 }; 30856 30857 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = { 30858 Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 30859 }; 30860 30861 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = { 30862 Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 30863 }; 30864 30865 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = { 30866 Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0 30867 }; 30868 30869 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = { 30870 Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0 30871 }; 30872 30873 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = { 30874 Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0 30875 }; 30876 30877 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = { 30878 Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0 30879 }; 30880 30881 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = { 30882 Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0 30883 }; 30884 30885 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = { 30886 Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0 30887 }; 30888 30889 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = { 30890 Opcode_iii_Slot_inst_encode, 0, 0, 0, 0 30891 }; 30892 30893 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = { 30894 Opcode_lict_Slot_inst_encode, 0, 0, 0, 0 30895 }; 30896 30897 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = { 30898 Opcode_licw_Slot_inst_encode, 0, 0, 0, 0 30899 }; 30900 30901 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = { 30902 Opcode_sict_Slot_inst_encode, 0, 0, 0, 0 30903 }; 30904 30905 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = { 30906 Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0 30907 }; 30908 30909 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = { 30910 Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0 30911 }; 30912 30913 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = { 30914 Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0 30915 }; 30916 30917 static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = { 30918 Opcode_diwbui_p_Slot_inst_encode, 0, 0, 0, 0 30919 }; 30920 30921 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = { 30922 Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0 30923 }; 30924 30925 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = { 30926 Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0 30927 }; 30928 30929 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = { 30930 Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0 30931 }; 30932 30933 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = { 30934 Opcode_dii_Slot_inst_encode, 0, 0, 0, 0 30935 }; 30936 30937 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = { 30938 Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0 30939 }; 30940 30941 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = { 30942 Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0 30943 }; 30944 30945 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = { 30946 Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0 30947 }; 30948 30949 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = { 30950 Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0 30951 }; 30952 30953 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = { 30954 Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0 30955 }; 30956 30957 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = { 30958 Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0 30959 }; 30960 30961 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = { 30962 Opcode_diu_Slot_inst_encode, 0, 0, 0, 0 30963 }; 30964 30965 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = { 30966 Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0 30967 }; 30968 30969 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = { 30970 Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0 30971 }; 30972 30973 static xtensa_opcode_encode_fn Opcode_rsr_prefctl_encode_fns[] = { 30974 Opcode_rsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 30975 }; 30976 30977 static xtensa_opcode_encode_fn Opcode_wsr_prefctl_encode_fns[] = { 30978 Opcode_wsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 30979 }; 30980 30981 static xtensa_opcode_encode_fn Opcode_xsr_prefctl_encode_fns[] = { 30982 Opcode_xsr_prefctl_Slot_inst_encode, 0, 0, 0, 0 30983 }; 30984 30985 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = { 30986 Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 30987 }; 30988 30989 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = { 30990 Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 30991 }; 30992 30993 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = { 30994 Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0 30995 }; 30996 30997 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = { 30998 Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0 30999 }; 31000 31001 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = { 31002 Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0 31003 }; 31004 31005 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = { 31006 Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0 31007 }; 31008 31009 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = { 31010 Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 31011 }; 31012 31013 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = { 31014 Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 31015 }; 31016 31017 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = { 31018 Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0 31019 }; 31020 31021 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = { 31022 Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 31023 }; 31024 31025 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = { 31026 Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 31027 }; 31028 31029 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = { 31030 Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0 31031 }; 31032 31033 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = { 31034 Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0 31035 }; 31036 31037 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = { 31038 Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0 31039 }; 31040 31041 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = { 31042 Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0 31043 }; 31044 31045 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = { 31046 Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0 31047 }; 31048 31049 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = { 31050 Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0 31051 }; 31052 31053 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = { 31054 Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0 31055 }; 31056 31057 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = { 31058 Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0 31059 }; 31060 31061 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = { 31062 Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0 31063 }; 31064 31065 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = { 31066 Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0 31067 }; 31068 31069 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = { 31070 Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0 31071 }; 31072 31073 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = { 31074 Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0 31075 }; 31076 31077 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = { 31078 Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0 31079 }; 31080 31081 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = { 31082 Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0 31083 }; 31084 31085 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = { 31086 Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 31087 }; 31088 31089 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = { 31090 Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 31091 }; 31092 31093 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = { 31094 Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0 31095 }; 31096 31097 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = { 31098 Opcode_clamps_Slot_inst_encode, 0, 0, 0, Opcode_clamps_Slot_ae_slot0_encode 31099 }; 31100 31101 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = { 31102 Opcode_min_Slot_inst_encode, 0, 0, 0, Opcode_min_Slot_ae_slot0_encode 31103 }; 31104 31105 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = { 31106 Opcode_max_Slot_inst_encode, 0, 0, 0, Opcode_max_Slot_ae_slot0_encode 31107 }; 31108 31109 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = { 31110 Opcode_minu_Slot_inst_encode, 0, 0, 0, Opcode_minu_Slot_ae_slot0_encode 31111 }; 31112 31113 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = { 31114 Opcode_maxu_Slot_inst_encode, 0, 0, 0, Opcode_maxu_Slot_ae_slot0_encode 31115 }; 31116 31117 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = { 31118 Opcode_nsa_Slot_inst_encode, 0, 0, 0, 0 31119 }; 31120 31121 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = { 31122 Opcode_nsau_Slot_inst_encode, 0, 0, 0, 0 31123 }; 31124 31125 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = { 31126 Opcode_sext_Slot_inst_encode, 0, 0, 0, Opcode_sext_Slot_ae_slot0_encode 31127 }; 31128 31129 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = { 31130 Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0 31131 }; 31132 31133 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = { 31134 Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0 31135 }; 31136 31137 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = { 31138 Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0 31139 }; 31140 31141 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = { 31142 Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 31143 }; 31144 31145 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = { 31146 Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 31147 }; 31148 31149 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = { 31150 Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0 31151 }; 31152 31153 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = { 31154 Opcode_rsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 31155 }; 31156 31157 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = { 31158 Opcode_wsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 31159 }; 31160 31161 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = { 31162 Opcode_xsr_atomctl_Slot_inst_encode, 0, 0, 0, 0 31163 }; 31164 31165 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = { 31166 Opcode_quou_Slot_inst_encode, 0, 0, 0, 0 31167 }; 31168 31169 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = { 31170 Opcode_quos_Slot_inst_encode, 0, 0, 0, 0 31171 }; 31172 31173 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = { 31174 Opcode_remu_Slot_inst_encode, 0, 0, 0, 0 31175 }; 31176 31177 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = { 31178 Opcode_rems_Slot_inst_encode, 0, 0, 0, 0 31179 }; 31180 31181 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = { 31182 Opcode_rer_Slot_inst_encode, 0, 0, 0, 0 31183 }; 31184 31185 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = { 31186 Opcode_wer_Slot_inst_encode, 0, 0, 0, 0 31187 }; 31188 31189 static xtensa_opcode_encode_fn Opcode_rur_ae_ovf_sar_encode_fns[] = { 31190 Opcode_rur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 31191 }; 31192 31193 static xtensa_opcode_encode_fn Opcode_wur_ae_ovf_sar_encode_fns[] = { 31194 Opcode_wur_ae_ovf_sar_Slot_inst_encode, 0, 0, 0, 0 31195 }; 31196 31197 static xtensa_opcode_encode_fn Opcode_rur_ae_bithead_encode_fns[] = { 31198 Opcode_rur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 31199 }; 31200 31201 static xtensa_opcode_encode_fn Opcode_wur_ae_bithead_encode_fns[] = { 31202 Opcode_wur_ae_bithead_Slot_inst_encode, 0, 0, 0, 0 31203 }; 31204 31205 static xtensa_opcode_encode_fn Opcode_rur_ae_ts_fts_bu_bp_encode_fns[] = { 31206 Opcode_rur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 31207 }; 31208 31209 static xtensa_opcode_encode_fn Opcode_wur_ae_ts_fts_bu_bp_encode_fns[] = { 31210 Opcode_wur_ae_ts_fts_bu_bp_Slot_inst_encode, 0, 0, 0, 0 31211 }; 31212 31213 static xtensa_opcode_encode_fn Opcode_rur_ae_sd_no_encode_fns[] = { 31214 Opcode_rur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 31215 }; 31216 31217 static xtensa_opcode_encode_fn Opcode_wur_ae_sd_no_encode_fns[] = { 31218 Opcode_wur_ae_sd_no_Slot_inst_encode, 0, 0, 0, 0 31219 }; 31220 31221 static xtensa_opcode_encode_fn Opcode_rur_ae_overflow_encode_fns[] = { 31222 Opcode_rur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 31223 }; 31224 31225 static xtensa_opcode_encode_fn Opcode_wur_ae_overflow_encode_fns[] = { 31226 Opcode_wur_ae_overflow_Slot_inst_encode, 0, 0, 0, 0 31227 }; 31228 31229 static xtensa_opcode_encode_fn Opcode_rur_ae_sar_encode_fns[] = { 31230 Opcode_rur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 31231 }; 31232 31233 static xtensa_opcode_encode_fn Opcode_wur_ae_sar_encode_fns[] = { 31234 Opcode_wur_ae_sar_Slot_inst_encode, 0, 0, 0, 0 31235 }; 31236 31237 static xtensa_opcode_encode_fn Opcode_rur_ae_bitptr_encode_fns[] = { 31238 Opcode_rur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 31239 }; 31240 31241 static xtensa_opcode_encode_fn Opcode_wur_ae_bitptr_encode_fns[] = { 31242 Opcode_wur_ae_bitptr_Slot_inst_encode, 0, 0, 0, 0 31243 }; 31244 31245 static xtensa_opcode_encode_fn Opcode_rur_ae_bitsused_encode_fns[] = { 31246 Opcode_rur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 31247 }; 31248 31249 static xtensa_opcode_encode_fn Opcode_wur_ae_bitsused_encode_fns[] = { 31250 Opcode_wur_ae_bitsused_Slot_inst_encode, 0, 0, 0, 0 31251 }; 31252 31253 static xtensa_opcode_encode_fn Opcode_rur_ae_tablesize_encode_fns[] = { 31254 Opcode_rur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 31255 }; 31256 31257 static xtensa_opcode_encode_fn Opcode_wur_ae_tablesize_encode_fns[] = { 31258 Opcode_wur_ae_tablesize_Slot_inst_encode, 0, 0, 0, 0 31259 }; 31260 31261 static xtensa_opcode_encode_fn Opcode_rur_ae_first_ts_encode_fns[] = { 31262 Opcode_rur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 31263 }; 31264 31265 static xtensa_opcode_encode_fn Opcode_wur_ae_first_ts_encode_fns[] = { 31266 Opcode_wur_ae_first_ts_Slot_inst_encode, 0, 0, 0, 0 31267 }; 31268 31269 static xtensa_opcode_encode_fn Opcode_rur_ae_nextoffset_encode_fns[] = { 31270 Opcode_rur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 31271 }; 31272 31273 static xtensa_opcode_encode_fn Opcode_wur_ae_nextoffset_encode_fns[] = { 31274 Opcode_wur_ae_nextoffset_Slot_inst_encode, 0, 0, 0, 0 31275 }; 31276 31277 static xtensa_opcode_encode_fn Opcode_rur_ae_searchdone_encode_fns[] = { 31278 Opcode_rur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 31279 }; 31280 31281 static xtensa_opcode_encode_fn Opcode_wur_ae_searchdone_encode_fns[] = { 31282 Opcode_wur_ae_searchdone_Slot_inst_encode, 0, 0, 0, 0 31283 }; 31284 31285 static xtensa_opcode_encode_fn Opcode_ae_lp16f_i_encode_fns[] = { 31286 Opcode_ae_lp16f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_i_Slot_ae_slot0_encode 31287 }; 31288 31289 static xtensa_opcode_encode_fn Opcode_ae_lp16f_iu_encode_fns[] = { 31290 Opcode_ae_lp16f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_iu_Slot_ae_slot0_encode 31291 }; 31292 31293 static xtensa_opcode_encode_fn Opcode_ae_lp16f_x_encode_fns[] = { 31294 Opcode_ae_lp16f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_x_Slot_ae_slot0_encode 31295 }; 31296 31297 static xtensa_opcode_encode_fn Opcode_ae_lp16f_xu_encode_fns[] = { 31298 Opcode_ae_lp16f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16f_xu_Slot_ae_slot0_encode 31299 }; 31300 31301 static xtensa_opcode_encode_fn Opcode_ae_lp24_i_encode_fns[] = { 31302 Opcode_ae_lp24_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_i_Slot_ae_slot0_encode 31303 }; 31304 31305 static xtensa_opcode_encode_fn Opcode_ae_lp24_iu_encode_fns[] = { 31306 Opcode_ae_lp24_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_iu_Slot_ae_slot0_encode 31307 }; 31308 31309 static xtensa_opcode_encode_fn Opcode_ae_lp24_x_encode_fns[] = { 31310 Opcode_ae_lp24_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_x_Slot_ae_slot0_encode 31311 }; 31312 31313 static xtensa_opcode_encode_fn Opcode_ae_lp24_xu_encode_fns[] = { 31314 Opcode_ae_lp24_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24_xu_Slot_ae_slot0_encode 31315 }; 31316 31317 static xtensa_opcode_encode_fn Opcode_ae_lp24f_i_encode_fns[] = { 31318 Opcode_ae_lp24f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_i_Slot_ae_slot0_encode 31319 }; 31320 31321 static xtensa_opcode_encode_fn Opcode_ae_lp24f_iu_encode_fns[] = { 31322 Opcode_ae_lp24f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_iu_Slot_ae_slot0_encode 31323 }; 31324 31325 static xtensa_opcode_encode_fn Opcode_ae_lp24f_x_encode_fns[] = { 31326 Opcode_ae_lp24f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_x_Slot_ae_slot0_encode 31327 }; 31328 31329 static xtensa_opcode_encode_fn Opcode_ae_lp24f_xu_encode_fns[] = { 31330 Opcode_ae_lp24f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24f_xu_Slot_ae_slot0_encode 31331 }; 31332 31333 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_i_encode_fns[] = { 31334 Opcode_ae_lp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_i_Slot_ae_slot0_encode 31335 }; 31336 31337 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_iu_encode_fns[] = { 31338 Opcode_ae_lp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_iu_Slot_ae_slot0_encode 31339 }; 31340 31341 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_x_encode_fns[] = { 31342 Opcode_ae_lp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_x_Slot_ae_slot0_encode 31343 }; 31344 31345 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_xu_encode_fns[] = { 31346 Opcode_ae_lp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp16x2f_xu_Slot_ae_slot0_encode 31347 }; 31348 31349 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_i_encode_fns[] = { 31350 Opcode_ae_lp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_i_Slot_ae_slot0_encode 31351 }; 31352 31353 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_iu_encode_fns[] = { 31354 Opcode_ae_lp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_iu_Slot_ae_slot0_encode 31355 }; 31356 31357 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_x_encode_fns[] = { 31358 Opcode_ae_lp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_x_Slot_ae_slot0_encode 31359 }; 31360 31361 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_xu_encode_fns[] = { 31362 Opcode_ae_lp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2f_xu_Slot_ae_slot0_encode 31363 }; 31364 31365 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_i_encode_fns[] = { 31366 Opcode_ae_lp24x2_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_i_Slot_ae_slot0_encode 31367 }; 31368 31369 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_iu_encode_fns[] = { 31370 Opcode_ae_lp24x2_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_iu_Slot_ae_slot0_encode 31371 }; 31372 31373 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_x_encode_fns[] = { 31374 Opcode_ae_lp24x2_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_x_Slot_ae_slot0_encode 31375 }; 31376 31377 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_xu_encode_fns[] = { 31378 Opcode_ae_lp24x2_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lp24x2_xu_Slot_ae_slot0_encode 31379 }; 31380 31381 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_i_encode_fns[] = { 31382 Opcode_ae_sp16x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_i_Slot_ae_slot0_encode 31383 }; 31384 31385 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_iu_encode_fns[] = { 31386 Opcode_ae_sp16x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_iu_Slot_ae_slot0_encode 31387 }; 31388 31389 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_x_encode_fns[] = { 31390 Opcode_ae_sp16x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_x_Slot_ae_slot0_encode 31391 }; 31392 31393 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_xu_encode_fns[] = { 31394 Opcode_ae_sp16x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16x2f_xu_Slot_ae_slot0_encode 31395 }; 31396 31397 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_i_encode_fns[] = { 31398 Opcode_ae_sp24x2s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_i_Slot_ae_slot0_encode 31399 }; 31400 31401 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_iu_encode_fns[] = { 31402 Opcode_ae_sp24x2s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_iu_Slot_ae_slot0_encode 31403 }; 31404 31405 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_x_encode_fns[] = { 31406 Opcode_ae_sp24x2s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_x_Slot_ae_slot0_encode 31407 }; 31408 31409 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_xu_encode_fns[] = { 31410 Opcode_ae_sp24x2s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2s_xu_Slot_ae_slot0_encode 31411 }; 31412 31413 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_i_encode_fns[] = { 31414 Opcode_ae_sp24x2f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_i_Slot_ae_slot0_encode 31415 }; 31416 31417 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_iu_encode_fns[] = { 31418 Opcode_ae_sp24x2f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_iu_Slot_ae_slot0_encode 31419 }; 31420 31421 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_x_encode_fns[] = { 31422 Opcode_ae_sp24x2f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_x_Slot_ae_slot0_encode 31423 }; 31424 31425 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_xu_encode_fns[] = { 31426 Opcode_ae_sp24x2f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24x2f_xu_Slot_ae_slot0_encode 31427 }; 31428 31429 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_i_encode_fns[] = { 31430 Opcode_ae_sp16f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_i_Slot_ae_slot0_encode 31431 }; 31432 31433 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_iu_encode_fns[] = { 31434 Opcode_ae_sp16f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_iu_Slot_ae_slot0_encode 31435 }; 31436 31437 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_x_encode_fns[] = { 31438 Opcode_ae_sp16f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_x_Slot_ae_slot0_encode 31439 }; 31440 31441 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_xu_encode_fns[] = { 31442 Opcode_ae_sp16f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp16f_l_xu_Slot_ae_slot0_encode 31443 }; 31444 31445 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_i_encode_fns[] = { 31446 Opcode_ae_sp24s_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_i_Slot_ae_slot0_encode 31447 }; 31448 31449 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_iu_encode_fns[] = { 31450 Opcode_ae_sp24s_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_iu_Slot_ae_slot0_encode 31451 }; 31452 31453 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_x_encode_fns[] = { 31454 Opcode_ae_sp24s_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_x_Slot_ae_slot0_encode 31455 }; 31456 31457 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_xu_encode_fns[] = { 31458 Opcode_ae_sp24s_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24s_l_xu_Slot_ae_slot0_encode 31459 }; 31460 31461 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_i_encode_fns[] = { 31462 Opcode_ae_sp24f_l_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_i_Slot_ae_slot0_encode 31463 }; 31464 31465 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_iu_encode_fns[] = { 31466 Opcode_ae_sp24f_l_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_iu_Slot_ae_slot0_encode 31467 }; 31468 31469 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_x_encode_fns[] = { 31470 Opcode_ae_sp24f_l_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_x_Slot_ae_slot0_encode 31471 }; 31472 31473 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_xu_encode_fns[] = { 31474 Opcode_ae_sp24f_l_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sp24f_l_xu_Slot_ae_slot0_encode 31475 }; 31476 31477 static xtensa_opcode_encode_fn Opcode_ae_lq56_i_encode_fns[] = { 31478 Opcode_ae_lq56_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_i_Slot_ae_slot0_encode 31479 }; 31480 31481 static xtensa_opcode_encode_fn Opcode_ae_lq56_iu_encode_fns[] = { 31482 Opcode_ae_lq56_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_iu_Slot_ae_slot0_encode 31483 }; 31484 31485 static xtensa_opcode_encode_fn Opcode_ae_lq56_x_encode_fns[] = { 31486 Opcode_ae_lq56_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_x_Slot_ae_slot0_encode 31487 }; 31488 31489 static xtensa_opcode_encode_fn Opcode_ae_lq56_xu_encode_fns[] = { 31490 Opcode_ae_lq56_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq56_xu_Slot_ae_slot0_encode 31491 }; 31492 31493 static xtensa_opcode_encode_fn Opcode_ae_lq32f_i_encode_fns[] = { 31494 Opcode_ae_lq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_i_Slot_ae_slot0_encode 31495 }; 31496 31497 static xtensa_opcode_encode_fn Opcode_ae_lq32f_iu_encode_fns[] = { 31498 Opcode_ae_lq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_iu_Slot_ae_slot0_encode 31499 }; 31500 31501 static xtensa_opcode_encode_fn Opcode_ae_lq32f_x_encode_fns[] = { 31502 Opcode_ae_lq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_x_Slot_ae_slot0_encode 31503 }; 31504 31505 static xtensa_opcode_encode_fn Opcode_ae_lq32f_xu_encode_fns[] = { 31506 Opcode_ae_lq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_lq32f_xu_Slot_ae_slot0_encode 31507 }; 31508 31509 static xtensa_opcode_encode_fn Opcode_ae_sq56s_i_encode_fns[] = { 31510 Opcode_ae_sq56s_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_i_Slot_ae_slot0_encode 31511 }; 31512 31513 static xtensa_opcode_encode_fn Opcode_ae_sq56s_iu_encode_fns[] = { 31514 Opcode_ae_sq56s_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_iu_Slot_ae_slot0_encode 31515 }; 31516 31517 static xtensa_opcode_encode_fn Opcode_ae_sq56s_x_encode_fns[] = { 31518 Opcode_ae_sq56s_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_x_Slot_ae_slot0_encode 31519 }; 31520 31521 static xtensa_opcode_encode_fn Opcode_ae_sq56s_xu_encode_fns[] = { 31522 Opcode_ae_sq56s_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq56s_xu_Slot_ae_slot0_encode 31523 }; 31524 31525 static xtensa_opcode_encode_fn Opcode_ae_sq32f_i_encode_fns[] = { 31526 Opcode_ae_sq32f_i_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_i_Slot_ae_slot0_encode 31527 }; 31528 31529 static xtensa_opcode_encode_fn Opcode_ae_sq32f_iu_encode_fns[] = { 31530 Opcode_ae_sq32f_iu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_iu_Slot_ae_slot0_encode 31531 }; 31532 31533 static xtensa_opcode_encode_fn Opcode_ae_sq32f_x_encode_fns[] = { 31534 Opcode_ae_sq32f_x_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_x_Slot_ae_slot0_encode 31535 }; 31536 31537 static xtensa_opcode_encode_fn Opcode_ae_sq32f_xu_encode_fns[] = { 31538 Opcode_ae_sq32f_xu_Slot_inst_encode, 0, 0, 0, Opcode_ae_sq32f_xu_Slot_ae_slot0_encode 31539 }; 31540 31541 static xtensa_opcode_encode_fn Opcode_ae_zerop48_encode_fns[] = { 31542 0, 0, 0, Opcode_ae_zerop48_Slot_ae_slot1_encode, 0 31543 }; 31544 31545 static xtensa_opcode_encode_fn Opcode_ae_movp48_encode_fns[] = { 31546 Opcode_ae_movp48_Slot_inst_encode, 0, 0, Opcode_ae_movp48_Slot_ae_slot1_encode, Opcode_ae_movp48_Slot_ae_slot0_encode 31547 }; 31548 31549 static xtensa_opcode_encode_fn Opcode_ae_selp24_ll_encode_fns[] = { 31550 0, 0, 0, Opcode_ae_selp24_ll_Slot_ae_slot1_encode, Opcode_ae_selp24_ll_Slot_ae_slot0_encode 31551 }; 31552 31553 static xtensa_opcode_encode_fn Opcode_ae_selp24_lh_encode_fns[] = { 31554 0, 0, 0, Opcode_ae_selp24_lh_Slot_ae_slot1_encode, Opcode_ae_selp24_lh_Slot_ae_slot0_encode 31555 }; 31556 31557 static xtensa_opcode_encode_fn Opcode_ae_selp24_hl_encode_fns[] = { 31558 0, 0, 0, Opcode_ae_selp24_hl_Slot_ae_slot1_encode, Opcode_ae_selp24_hl_Slot_ae_slot0_encode 31559 }; 31560 31561 static xtensa_opcode_encode_fn Opcode_ae_selp24_hh_encode_fns[] = { 31562 0, 0, 0, Opcode_ae_selp24_hh_Slot_ae_slot1_encode, Opcode_ae_selp24_hh_Slot_ae_slot0_encode 31563 }; 31564 31565 static xtensa_opcode_encode_fn Opcode_ae_movtp24x2_encode_fns[] = { 31566 0, 0, 0, Opcode_ae_movtp24x2_Slot_ae_slot1_encode, 0 31567 }; 31568 31569 static xtensa_opcode_encode_fn Opcode_ae_movfp24x2_encode_fns[] = { 31570 0, 0, 0, Opcode_ae_movfp24x2_Slot_ae_slot1_encode, 0 31571 }; 31572 31573 static xtensa_opcode_encode_fn Opcode_ae_movtp48_encode_fns[] = { 31574 0, 0, 0, Opcode_ae_movtp48_Slot_ae_slot1_encode, 0 31575 }; 31576 31577 static xtensa_opcode_encode_fn Opcode_ae_movfp48_encode_fns[] = { 31578 0, 0, 0, Opcode_ae_movfp48_Slot_ae_slot1_encode, 0 31579 }; 31580 31581 static xtensa_opcode_encode_fn Opcode_ae_movpa24x2_encode_fns[] = { 31582 Opcode_ae_movpa24x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_movpa24x2_Slot_ae_slot0_encode 31583 }; 31584 31585 static xtensa_opcode_encode_fn Opcode_ae_truncp24a32x2_encode_fns[] = { 31586 Opcode_ae_truncp24a32x2_Slot_inst_encode, 0, 0, 0, Opcode_ae_truncp24a32x2_Slot_ae_slot0_encode 31587 }; 31588 31589 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_l_encode_fns[] = { 31590 Opcode_ae_cvta32p24_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_l_Slot_ae_slot0_encode 31591 }; 31592 31593 static xtensa_opcode_encode_fn Opcode_ae_cvta32p24_h_encode_fns[] = { 31594 Opcode_ae_cvta32p24_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvta32p24_h_Slot_ae_slot0_encode 31595 }; 31596 31597 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_ll_encode_fns[] = { 31598 Opcode_ae_cvtp24a16x2_ll_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_ll_Slot_ae_slot0_encode 31599 }; 31600 31601 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_lh_encode_fns[] = { 31602 Opcode_ae_cvtp24a16x2_lh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_lh_Slot_ae_slot0_encode 31603 }; 31604 31605 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hl_encode_fns[] = { 31606 Opcode_ae_cvtp24a16x2_hl_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hl_Slot_ae_slot0_encode 31607 }; 31608 31609 static xtensa_opcode_encode_fn Opcode_ae_cvtp24a16x2_hh_encode_fns[] = { 31610 Opcode_ae_cvtp24a16x2_hh_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtp24a16x2_hh_Slot_ae_slot0_encode 31611 }; 31612 31613 static xtensa_opcode_encode_fn Opcode_ae_truncp24q48x2_encode_fns[] = { 31614 0, 0, 0, Opcode_ae_truncp24q48x2_Slot_ae_slot1_encode, 0 31615 }; 31616 31617 static xtensa_opcode_encode_fn Opcode_ae_truncp16_encode_fns[] = { 31618 0, 0, 0, Opcode_ae_truncp16_Slot_ae_slot1_encode, 0 31619 }; 31620 31621 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48sym_encode_fns[] = { 31622 0, 0, 0, Opcode_ae_roundsp24q48sym_Slot_ae_slot1_encode, 0 31623 }; 31624 31625 static xtensa_opcode_encode_fn Opcode_ae_roundsp24q48asym_encode_fns[] = { 31626 0, 0, 0, Opcode_ae_roundsp24q48asym_Slot_ae_slot1_encode, 0 31627 }; 31628 31629 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48sym_encode_fns[] = { 31630 0, 0, 0, Opcode_ae_roundsp16q48sym_Slot_ae_slot1_encode, 0 31631 }; 31632 31633 static xtensa_opcode_encode_fn Opcode_ae_roundsp16q48asym_encode_fns[] = { 31634 0, 0, 0, Opcode_ae_roundsp16q48asym_Slot_ae_slot1_encode, 0 31635 }; 31636 31637 static xtensa_opcode_encode_fn Opcode_ae_roundsp16sym_encode_fns[] = { 31638 0, 0, 0, Opcode_ae_roundsp16sym_Slot_ae_slot1_encode, 0 31639 }; 31640 31641 static xtensa_opcode_encode_fn Opcode_ae_roundsp16asym_encode_fns[] = { 31642 0, 0, 0, Opcode_ae_roundsp16asym_Slot_ae_slot1_encode, 0 31643 }; 31644 31645 static xtensa_opcode_encode_fn Opcode_ae_zeroq56_encode_fns[] = { 31646 0, 0, 0, Opcode_ae_zeroq56_Slot_ae_slot1_encode, 0 31647 }; 31648 31649 static xtensa_opcode_encode_fn Opcode_ae_movq56_encode_fns[] = { 31650 Opcode_ae_movq56_Slot_inst_encode, 0, 0, Opcode_ae_movq56_Slot_ae_slot1_encode, Opcode_ae_movq56_Slot_ae_slot0_encode 31651 }; 31652 31653 static xtensa_opcode_encode_fn Opcode_ae_movtq56_encode_fns[] = { 31654 Opcode_ae_movtq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movtq56_Slot_ae_slot0_encode 31655 }; 31656 31657 static xtensa_opcode_encode_fn Opcode_ae_movfq56_encode_fns[] = { 31658 Opcode_ae_movfq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_movfq56_Slot_ae_slot0_encode 31659 }; 31660 31661 static xtensa_opcode_encode_fn Opcode_ae_cvtq48a32s_encode_fns[] = { 31662 Opcode_ae_cvtq48a32s_Slot_inst_encode, 0, 0, 0, Opcode_ae_cvtq48a32s_Slot_ae_slot0_encode 31663 }; 31664 31665 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_l_encode_fns[] = { 31666 0, 0, 0, Opcode_ae_cvtq48p24s_l_Slot_ae_slot1_encode, 0 31667 }; 31668 31669 static xtensa_opcode_encode_fn Opcode_ae_cvtq48p24s_h_encode_fns[] = { 31670 0, 0, 0, Opcode_ae_cvtq48p24s_h_Slot_ae_slot1_encode, 0 31671 }; 31672 31673 static xtensa_opcode_encode_fn Opcode_ae_satq48s_encode_fns[] = { 31674 0, 0, 0, Opcode_ae_satq48s_Slot_ae_slot1_encode, 0 31675 }; 31676 31677 static xtensa_opcode_encode_fn Opcode_ae_truncq32_encode_fns[] = { 31678 0, 0, 0, Opcode_ae_truncq32_Slot_ae_slot1_encode, 0 31679 }; 31680 31681 static xtensa_opcode_encode_fn Opcode_ae_roundsq32sym_encode_fns[] = { 31682 0, 0, 0, Opcode_ae_roundsq32sym_Slot_ae_slot1_encode, 0 31683 }; 31684 31685 static xtensa_opcode_encode_fn Opcode_ae_roundsq32asym_encode_fns[] = { 31686 0, 0, 0, Opcode_ae_roundsq32asym_Slot_ae_slot1_encode, 0 31687 }; 31688 31689 static xtensa_opcode_encode_fn Opcode_ae_trunca32q48_encode_fns[] = { 31690 Opcode_ae_trunca32q48_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca32q48_Slot_ae_slot0_encode 31691 }; 31692 31693 static xtensa_opcode_encode_fn Opcode_ae_movap24s_l_encode_fns[] = { 31694 Opcode_ae_movap24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_l_Slot_ae_slot0_encode 31695 }; 31696 31697 static xtensa_opcode_encode_fn Opcode_ae_movap24s_h_encode_fns[] = { 31698 Opcode_ae_movap24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_movap24s_h_Slot_ae_slot0_encode 31699 }; 31700 31701 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_l_encode_fns[] = { 31702 Opcode_ae_trunca16p24s_l_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_l_Slot_ae_slot0_encode 31703 }; 31704 31705 static xtensa_opcode_encode_fn Opcode_ae_trunca16p24s_h_encode_fns[] = { 31706 Opcode_ae_trunca16p24s_h_Slot_inst_encode, 0, 0, 0, Opcode_ae_trunca16p24s_h_Slot_ae_slot0_encode 31707 }; 31708 31709 static xtensa_opcode_encode_fn Opcode_ae_addp24_encode_fns[] = { 31710 0, 0, 0, Opcode_ae_addp24_Slot_ae_slot1_encode, 0 31711 }; 31712 31713 static xtensa_opcode_encode_fn Opcode_ae_subp24_encode_fns[] = { 31714 0, 0, 0, Opcode_ae_subp24_Slot_ae_slot1_encode, 0 31715 }; 31716 31717 static xtensa_opcode_encode_fn Opcode_ae_negp24_encode_fns[] = { 31718 0, 0, 0, Opcode_ae_negp24_Slot_ae_slot1_encode, 0 31719 }; 31720 31721 static xtensa_opcode_encode_fn Opcode_ae_absp24_encode_fns[] = { 31722 0, 0, 0, Opcode_ae_absp24_Slot_ae_slot1_encode, 0 31723 }; 31724 31725 static xtensa_opcode_encode_fn Opcode_ae_maxp24s_encode_fns[] = { 31726 0, 0, 0, Opcode_ae_maxp24s_Slot_ae_slot1_encode, 0 31727 }; 31728 31729 static xtensa_opcode_encode_fn Opcode_ae_minp24s_encode_fns[] = { 31730 0, 0, 0, Opcode_ae_minp24s_Slot_ae_slot1_encode, 0 31731 }; 31732 31733 static xtensa_opcode_encode_fn Opcode_ae_maxbp24s_encode_fns[] = { 31734 0, 0, 0, Opcode_ae_maxbp24s_Slot_ae_slot1_encode, 0 31735 }; 31736 31737 static xtensa_opcode_encode_fn Opcode_ae_minbp24s_encode_fns[] = { 31738 0, 0, 0, Opcode_ae_minbp24s_Slot_ae_slot1_encode, 0 31739 }; 31740 31741 static xtensa_opcode_encode_fn Opcode_ae_addsp24s_encode_fns[] = { 31742 0, 0, 0, Opcode_ae_addsp24s_Slot_ae_slot1_encode, 0 31743 }; 31744 31745 static xtensa_opcode_encode_fn Opcode_ae_subsp24s_encode_fns[] = { 31746 0, 0, 0, Opcode_ae_subsp24s_Slot_ae_slot1_encode, 0 31747 }; 31748 31749 static xtensa_opcode_encode_fn Opcode_ae_negsp24s_encode_fns[] = { 31750 0, 0, 0, Opcode_ae_negsp24s_Slot_ae_slot1_encode, 0 31751 }; 31752 31753 static xtensa_opcode_encode_fn Opcode_ae_abssp24s_encode_fns[] = { 31754 0, 0, 0, Opcode_ae_abssp24s_Slot_ae_slot1_encode, 0 31755 }; 31756 31757 static xtensa_opcode_encode_fn Opcode_ae_andp48_encode_fns[] = { 31758 0, 0, 0, Opcode_ae_andp48_Slot_ae_slot1_encode, 0 31759 }; 31760 31761 static xtensa_opcode_encode_fn Opcode_ae_nandp48_encode_fns[] = { 31762 0, 0, 0, Opcode_ae_nandp48_Slot_ae_slot1_encode, 0 31763 }; 31764 31765 static xtensa_opcode_encode_fn Opcode_ae_orp48_encode_fns[] = { 31766 0, 0, 0, Opcode_ae_orp48_Slot_ae_slot1_encode, 0 31767 }; 31768 31769 static xtensa_opcode_encode_fn Opcode_ae_xorp48_encode_fns[] = { 31770 0, 0, 0, Opcode_ae_xorp48_Slot_ae_slot1_encode, 0 31771 }; 31772 31773 static xtensa_opcode_encode_fn Opcode_ae_ltp24s_encode_fns[] = { 31774 0, 0, 0, Opcode_ae_ltp24s_Slot_ae_slot1_encode, 0 31775 }; 31776 31777 static xtensa_opcode_encode_fn Opcode_ae_lep24s_encode_fns[] = { 31778 0, 0, 0, Opcode_ae_lep24s_Slot_ae_slot1_encode, 0 31779 }; 31780 31781 static xtensa_opcode_encode_fn Opcode_ae_eqp24_encode_fns[] = { 31782 0, 0, 0, Opcode_ae_eqp24_Slot_ae_slot1_encode, 0 31783 }; 31784 31785 static xtensa_opcode_encode_fn Opcode_ae_addq56_encode_fns[] = { 31786 0, 0, 0, Opcode_ae_addq56_Slot_ae_slot1_encode, 0 31787 }; 31788 31789 static xtensa_opcode_encode_fn Opcode_ae_subq56_encode_fns[] = { 31790 0, 0, 0, Opcode_ae_subq56_Slot_ae_slot1_encode, 0 31791 }; 31792 31793 static xtensa_opcode_encode_fn Opcode_ae_negq56_encode_fns[] = { 31794 0, 0, 0, Opcode_ae_negq56_Slot_ae_slot1_encode, 0 31795 }; 31796 31797 static xtensa_opcode_encode_fn Opcode_ae_absq56_encode_fns[] = { 31798 0, 0, 0, Opcode_ae_absq56_Slot_ae_slot1_encode, 0 31799 }; 31800 31801 static xtensa_opcode_encode_fn Opcode_ae_maxq56s_encode_fns[] = { 31802 0, 0, 0, Opcode_ae_maxq56s_Slot_ae_slot1_encode, 0 31803 }; 31804 31805 static xtensa_opcode_encode_fn Opcode_ae_minq56s_encode_fns[] = { 31806 0, 0, 0, Opcode_ae_minq56s_Slot_ae_slot1_encode, 0 31807 }; 31808 31809 static xtensa_opcode_encode_fn Opcode_ae_maxbq56s_encode_fns[] = { 31810 0, 0, 0, Opcode_ae_maxbq56s_Slot_ae_slot1_encode, 0 31811 }; 31812 31813 static xtensa_opcode_encode_fn Opcode_ae_minbq56s_encode_fns[] = { 31814 0, 0, 0, Opcode_ae_minbq56s_Slot_ae_slot1_encode, 0 31815 }; 31816 31817 static xtensa_opcode_encode_fn Opcode_ae_addsq56s_encode_fns[] = { 31818 0, 0, 0, Opcode_ae_addsq56s_Slot_ae_slot1_encode, 0 31819 }; 31820 31821 static xtensa_opcode_encode_fn Opcode_ae_subsq56s_encode_fns[] = { 31822 0, 0, 0, Opcode_ae_subsq56s_Slot_ae_slot1_encode, 0 31823 }; 31824 31825 static xtensa_opcode_encode_fn Opcode_ae_negsq56s_encode_fns[] = { 31826 0, 0, 0, Opcode_ae_negsq56s_Slot_ae_slot1_encode, 0 31827 }; 31828 31829 static xtensa_opcode_encode_fn Opcode_ae_abssq56s_encode_fns[] = { 31830 0, 0, 0, Opcode_ae_abssq56s_Slot_ae_slot1_encode, 0 31831 }; 31832 31833 static xtensa_opcode_encode_fn Opcode_ae_andq56_encode_fns[] = { 31834 0, 0, 0, Opcode_ae_andq56_Slot_ae_slot1_encode, 0 31835 }; 31836 31837 static xtensa_opcode_encode_fn Opcode_ae_nandq56_encode_fns[] = { 31838 0, 0, 0, Opcode_ae_nandq56_Slot_ae_slot1_encode, 0 31839 }; 31840 31841 static xtensa_opcode_encode_fn Opcode_ae_orq56_encode_fns[] = { 31842 0, 0, 0, Opcode_ae_orq56_Slot_ae_slot1_encode, 0 31843 }; 31844 31845 static xtensa_opcode_encode_fn Opcode_ae_xorq56_encode_fns[] = { 31846 0, 0, 0, Opcode_ae_xorq56_Slot_ae_slot1_encode, 0 31847 }; 31848 31849 static xtensa_opcode_encode_fn Opcode_ae_sllip24_encode_fns[] = { 31850 0, 0, 0, Opcode_ae_sllip24_Slot_ae_slot1_encode, 0 31851 }; 31852 31853 static xtensa_opcode_encode_fn Opcode_ae_srlip24_encode_fns[] = { 31854 0, 0, 0, Opcode_ae_srlip24_Slot_ae_slot1_encode, 0 31855 }; 31856 31857 static xtensa_opcode_encode_fn Opcode_ae_sraip24_encode_fns[] = { 31858 0, 0, 0, Opcode_ae_sraip24_Slot_ae_slot1_encode, 0 31859 }; 31860 31861 static xtensa_opcode_encode_fn Opcode_ae_sllsp24_encode_fns[] = { 31862 0, 0, 0, Opcode_ae_sllsp24_Slot_ae_slot1_encode, 0 31863 }; 31864 31865 static xtensa_opcode_encode_fn Opcode_ae_srlsp24_encode_fns[] = { 31866 0, 0, 0, Opcode_ae_srlsp24_Slot_ae_slot1_encode, 0 31867 }; 31868 31869 static xtensa_opcode_encode_fn Opcode_ae_srasp24_encode_fns[] = { 31870 0, 0, 0, Opcode_ae_srasp24_Slot_ae_slot1_encode, 0 31871 }; 31872 31873 static xtensa_opcode_encode_fn Opcode_ae_sllisp24s_encode_fns[] = { 31874 0, 0, 0, Opcode_ae_sllisp24s_Slot_ae_slot1_encode, 0 31875 }; 31876 31877 static xtensa_opcode_encode_fn Opcode_ae_sllssp24s_encode_fns[] = { 31878 0, 0, 0, Opcode_ae_sllssp24s_Slot_ae_slot1_encode, 0 31879 }; 31880 31881 static xtensa_opcode_encode_fn Opcode_ae_slliq56_encode_fns[] = { 31882 Opcode_ae_slliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_slliq56_Slot_ae_slot0_encode 31883 }; 31884 31885 static xtensa_opcode_encode_fn Opcode_ae_srliq56_encode_fns[] = { 31886 Opcode_ae_srliq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srliq56_Slot_ae_slot0_encode 31887 }; 31888 31889 static xtensa_opcode_encode_fn Opcode_ae_sraiq56_encode_fns[] = { 31890 Opcode_ae_sraiq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraiq56_Slot_ae_slot0_encode 31891 }; 31892 31893 static xtensa_opcode_encode_fn Opcode_ae_sllsq56_encode_fns[] = { 31894 Opcode_ae_sllsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllsq56_Slot_ae_slot0_encode 31895 }; 31896 31897 static xtensa_opcode_encode_fn Opcode_ae_srlsq56_encode_fns[] = { 31898 Opcode_ae_srlsq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlsq56_Slot_ae_slot0_encode 31899 }; 31900 31901 static xtensa_opcode_encode_fn Opcode_ae_srasq56_encode_fns[] = { 31902 Opcode_ae_srasq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srasq56_Slot_ae_slot0_encode 31903 }; 31904 31905 static xtensa_opcode_encode_fn Opcode_ae_sllaq56_encode_fns[] = { 31906 Opcode_ae_sllaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllaq56_Slot_ae_slot0_encode 31907 }; 31908 31909 static xtensa_opcode_encode_fn Opcode_ae_srlaq56_encode_fns[] = { 31910 Opcode_ae_srlaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_srlaq56_Slot_ae_slot0_encode 31911 }; 31912 31913 static xtensa_opcode_encode_fn Opcode_ae_sraaq56_encode_fns[] = { 31914 Opcode_ae_sraaq56_Slot_inst_encode, 0, 0, 0, Opcode_ae_sraaq56_Slot_ae_slot0_encode 31915 }; 31916 31917 static xtensa_opcode_encode_fn Opcode_ae_sllisq56s_encode_fns[] = { 31918 Opcode_ae_sllisq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllisq56s_Slot_ae_slot0_encode 31919 }; 31920 31921 static xtensa_opcode_encode_fn Opcode_ae_sllssq56s_encode_fns[] = { 31922 Opcode_ae_sllssq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllssq56s_Slot_ae_slot0_encode 31923 }; 31924 31925 static xtensa_opcode_encode_fn Opcode_ae_sllasq56s_encode_fns[] = { 31926 Opcode_ae_sllasq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_sllasq56s_Slot_ae_slot0_encode 31927 }; 31928 31929 static xtensa_opcode_encode_fn Opcode_ae_ltq56s_encode_fns[] = { 31930 0, 0, 0, Opcode_ae_ltq56s_Slot_ae_slot1_encode, 0 31931 }; 31932 31933 static xtensa_opcode_encode_fn Opcode_ae_leq56s_encode_fns[] = { 31934 0, 0, 0, Opcode_ae_leq56s_Slot_ae_slot1_encode, 0 31935 }; 31936 31937 static xtensa_opcode_encode_fn Opcode_ae_eqq56_encode_fns[] = { 31938 0, 0, 0, Opcode_ae_eqq56_Slot_ae_slot1_encode, 0 31939 }; 31940 31941 static xtensa_opcode_encode_fn Opcode_ae_nsaq56s_encode_fns[] = { 31942 Opcode_ae_nsaq56s_Slot_inst_encode, 0, 0, 0, Opcode_ae_nsaq56s_Slot_ae_slot0_encode 31943 }; 31944 31945 static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_h_encode_fns[] = { 31946 0, 0, 0, Opcode_ae_mulsrfq32sp24s_h_Slot_ae_slot1_encode, 0 31947 }; 31948 31949 static xtensa_opcode_encode_fn Opcode_ae_mulsrfq32sp24s_l_encode_fns[] = { 31950 0, 0, 0, Opcode_ae_mulsrfq32sp24s_l_Slot_ae_slot1_encode, 0 31951 }; 31952 31953 static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_h_encode_fns[] = { 31954 0, 0, 0, Opcode_ae_mularfq32sp24s_h_Slot_ae_slot1_encode, 0 31955 }; 31956 31957 static xtensa_opcode_encode_fn Opcode_ae_mularfq32sp24s_l_encode_fns[] = { 31958 0, 0, 0, Opcode_ae_mularfq32sp24s_l_Slot_ae_slot1_encode, 0 31959 }; 31960 31961 static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_h_encode_fns[] = { 31962 0, 0, 0, Opcode_ae_mulrfq32sp24s_h_Slot_ae_slot1_encode, 0 31963 }; 31964 31965 static xtensa_opcode_encode_fn Opcode_ae_mulrfq32sp24s_l_encode_fns[] = { 31966 0, 0, 0, Opcode_ae_mulrfq32sp24s_l_Slot_ae_slot1_encode, 0 31967 }; 31968 31969 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_h_encode_fns[] = { 31970 0, 0, 0, Opcode_ae_mulsfq32sp24s_h_Slot_ae_slot1_encode, 0 31971 }; 31972 31973 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp24s_l_encode_fns[] = { 31974 0, 0, 0, Opcode_ae_mulsfq32sp24s_l_Slot_ae_slot1_encode, 0 31975 }; 31976 31977 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_h_encode_fns[] = { 31978 0, 0, 0, Opcode_ae_mulafq32sp24s_h_Slot_ae_slot1_encode, 0 31979 }; 31980 31981 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp24s_l_encode_fns[] = { 31982 0, 0, 0, Opcode_ae_mulafq32sp24s_l_Slot_ae_slot1_encode, 0 31983 }; 31984 31985 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_h_encode_fns[] = { 31986 0, 0, 0, Opcode_ae_mulfq32sp24s_h_Slot_ae_slot1_encode, 0 31987 }; 31988 31989 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp24s_l_encode_fns[] = { 31990 0, 0, 0, Opcode_ae_mulfq32sp24s_l_Slot_ae_slot1_encode, 0 31991 }; 31992 31993 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_ll_encode_fns[] = { 31994 0, 0, 0, Opcode_ae_mulfs32p16s_ll_Slot_ae_slot1_encode, 0 31995 }; 31996 31997 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_ll_encode_fns[] = { 31998 0, 0, 0, Opcode_ae_mulfp24s_ll_Slot_ae_slot1_encode, 0 31999 }; 32000 32001 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_ll_encode_fns[] = { 32002 0, 0, 0, Opcode_ae_mulp24s_ll_Slot_ae_slot1_encode, 0 32003 }; 32004 32005 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_lh_encode_fns[] = { 32006 0, 0, 0, Opcode_ae_mulfs32p16s_lh_Slot_ae_slot1_encode, 0 32007 }; 32008 32009 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_lh_encode_fns[] = { 32010 0, 0, 0, Opcode_ae_mulfp24s_lh_Slot_ae_slot1_encode, 0 32011 }; 32012 32013 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_lh_encode_fns[] = { 32014 0, 0, 0, Opcode_ae_mulp24s_lh_Slot_ae_slot1_encode, 0 32015 }; 32016 32017 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hl_encode_fns[] = { 32018 0, 0, 0, Opcode_ae_mulfs32p16s_hl_Slot_ae_slot1_encode, 0 32019 }; 32020 32021 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hl_encode_fns[] = { 32022 0, 0, 0, Opcode_ae_mulfp24s_hl_Slot_ae_slot1_encode, 0 32023 }; 32024 32025 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hl_encode_fns[] = { 32026 0, 0, 0, Opcode_ae_mulp24s_hl_Slot_ae_slot1_encode, 0 32027 }; 32028 32029 static xtensa_opcode_encode_fn Opcode_ae_mulfs32p16s_hh_encode_fns[] = { 32030 0, 0, 0, Opcode_ae_mulfs32p16s_hh_Slot_ae_slot1_encode, 0 32031 }; 32032 32033 static xtensa_opcode_encode_fn Opcode_ae_mulfp24s_hh_encode_fns[] = { 32034 0, 0, 0, Opcode_ae_mulfp24s_hh_Slot_ae_slot1_encode, 0 32035 }; 32036 32037 static xtensa_opcode_encode_fn Opcode_ae_mulp24s_hh_encode_fns[] = { 32038 0, 0, 0, Opcode_ae_mulp24s_hh_Slot_ae_slot1_encode, 0 32039 }; 32040 32041 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_ll_encode_fns[] = { 32042 0, 0, 0, Opcode_ae_mulafs32p16s_ll_Slot_ae_slot1_encode, 0 32043 }; 32044 32045 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_ll_encode_fns[] = { 32046 0, 0, 0, Opcode_ae_mulafp24s_ll_Slot_ae_slot1_encode, 0 32047 }; 32048 32049 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_ll_encode_fns[] = { 32050 0, 0, 0, Opcode_ae_mulap24s_ll_Slot_ae_slot1_encode, 0 32051 }; 32052 32053 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_lh_encode_fns[] = { 32054 0, 0, 0, Opcode_ae_mulafs32p16s_lh_Slot_ae_slot1_encode, 0 32055 }; 32056 32057 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_lh_encode_fns[] = { 32058 0, 0, 0, Opcode_ae_mulafp24s_lh_Slot_ae_slot1_encode, 0 32059 }; 32060 32061 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_lh_encode_fns[] = { 32062 0, 0, 0, Opcode_ae_mulap24s_lh_Slot_ae_slot1_encode, 0 32063 }; 32064 32065 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hl_encode_fns[] = { 32066 0, 0, 0, Opcode_ae_mulafs32p16s_hl_Slot_ae_slot1_encode, 0 32067 }; 32068 32069 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hl_encode_fns[] = { 32070 0, 0, 0, Opcode_ae_mulafp24s_hl_Slot_ae_slot1_encode, 0 32071 }; 32072 32073 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hl_encode_fns[] = { 32074 0, 0, 0, Opcode_ae_mulap24s_hl_Slot_ae_slot1_encode, 0 32075 }; 32076 32077 static xtensa_opcode_encode_fn Opcode_ae_mulafs32p16s_hh_encode_fns[] = { 32078 0, 0, 0, Opcode_ae_mulafs32p16s_hh_Slot_ae_slot1_encode, 0 32079 }; 32080 32081 static xtensa_opcode_encode_fn Opcode_ae_mulafp24s_hh_encode_fns[] = { 32082 0, 0, 0, Opcode_ae_mulafp24s_hh_Slot_ae_slot1_encode, 0 32083 }; 32084 32085 static xtensa_opcode_encode_fn Opcode_ae_mulap24s_hh_encode_fns[] = { 32086 0, 0, 0, Opcode_ae_mulap24s_hh_Slot_ae_slot1_encode, 0 32087 }; 32088 32089 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_ll_encode_fns[] = { 32090 0, 0, 0, Opcode_ae_mulsfs32p16s_ll_Slot_ae_slot1_encode, 0 32091 }; 32092 32093 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_ll_encode_fns[] = { 32094 0, 0, 0, Opcode_ae_mulsfp24s_ll_Slot_ae_slot1_encode, 0 32095 }; 32096 32097 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_ll_encode_fns[] = { 32098 0, 0, 0, Opcode_ae_mulsp24s_ll_Slot_ae_slot1_encode, 0 32099 }; 32100 32101 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_lh_encode_fns[] = { 32102 0, 0, 0, Opcode_ae_mulsfs32p16s_lh_Slot_ae_slot1_encode, 0 32103 }; 32104 32105 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_lh_encode_fns[] = { 32106 0, 0, 0, Opcode_ae_mulsfp24s_lh_Slot_ae_slot1_encode, 0 32107 }; 32108 32109 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_lh_encode_fns[] = { 32110 0, 0, 0, Opcode_ae_mulsp24s_lh_Slot_ae_slot1_encode, 0 32111 }; 32112 32113 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hl_encode_fns[] = { 32114 0, 0, 0, Opcode_ae_mulsfs32p16s_hl_Slot_ae_slot1_encode, 0 32115 }; 32116 32117 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hl_encode_fns[] = { 32118 0, 0, 0, Opcode_ae_mulsfp24s_hl_Slot_ae_slot1_encode, 0 32119 }; 32120 32121 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hl_encode_fns[] = { 32122 0, 0, 0, Opcode_ae_mulsp24s_hl_Slot_ae_slot1_encode, 0 32123 }; 32124 32125 static xtensa_opcode_encode_fn Opcode_ae_mulsfs32p16s_hh_encode_fns[] = { 32126 0, 0, 0, Opcode_ae_mulsfs32p16s_hh_Slot_ae_slot1_encode, 0 32127 }; 32128 32129 static xtensa_opcode_encode_fn Opcode_ae_mulsfp24s_hh_encode_fns[] = { 32130 0, 0, 0, Opcode_ae_mulsfp24s_hh_Slot_ae_slot1_encode, 0 32131 }; 32132 32133 static xtensa_opcode_encode_fn Opcode_ae_mulsp24s_hh_encode_fns[] = { 32134 0, 0, 0, Opcode_ae_mulsp24s_hh_Slot_ae_slot1_encode, 0 32135 }; 32136 32137 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_ll_encode_fns[] = { 32138 0, 0, 0, Opcode_ae_mulafs56p24s_ll_Slot_ae_slot1_encode, 0 32139 }; 32140 32141 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_ll_encode_fns[] = { 32142 0, 0, 0, Opcode_ae_mulas56p24s_ll_Slot_ae_slot1_encode, 0 32143 }; 32144 32145 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_lh_encode_fns[] = { 32146 0, 0, 0, Opcode_ae_mulafs56p24s_lh_Slot_ae_slot1_encode, 0 32147 }; 32148 32149 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_lh_encode_fns[] = { 32150 0, 0, 0, Opcode_ae_mulas56p24s_lh_Slot_ae_slot1_encode, 0 32151 }; 32152 32153 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hl_encode_fns[] = { 32154 0, 0, 0, Opcode_ae_mulafs56p24s_hl_Slot_ae_slot1_encode, 0 32155 }; 32156 32157 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hl_encode_fns[] = { 32158 0, 0, 0, Opcode_ae_mulas56p24s_hl_Slot_ae_slot1_encode, 0 32159 }; 32160 32161 static xtensa_opcode_encode_fn Opcode_ae_mulafs56p24s_hh_encode_fns[] = { 32162 0, 0, 0, Opcode_ae_mulafs56p24s_hh_Slot_ae_slot1_encode, 0 32163 }; 32164 32165 static xtensa_opcode_encode_fn Opcode_ae_mulas56p24s_hh_encode_fns[] = { 32166 0, 0, 0, Opcode_ae_mulas56p24s_hh_Slot_ae_slot1_encode, 0 32167 }; 32168 32169 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_ll_encode_fns[] = { 32170 0, 0, 0, Opcode_ae_mulsfs56p24s_ll_Slot_ae_slot1_encode, 0 32171 }; 32172 32173 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_ll_encode_fns[] = { 32174 0, 0, 0, Opcode_ae_mulss56p24s_ll_Slot_ae_slot1_encode, 0 32175 }; 32176 32177 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_lh_encode_fns[] = { 32178 0, 0, 0, Opcode_ae_mulsfs56p24s_lh_Slot_ae_slot1_encode, 0 32179 }; 32180 32181 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_lh_encode_fns[] = { 32182 0, 0, 0, Opcode_ae_mulss56p24s_lh_Slot_ae_slot1_encode, 0 32183 }; 32184 32185 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hl_encode_fns[] = { 32186 0, 0, 0, Opcode_ae_mulsfs56p24s_hl_Slot_ae_slot1_encode, 0 32187 }; 32188 32189 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hl_encode_fns[] = { 32190 0, 0, 0, Opcode_ae_mulss56p24s_hl_Slot_ae_slot1_encode, 0 32191 }; 32192 32193 static xtensa_opcode_encode_fn Opcode_ae_mulsfs56p24s_hh_encode_fns[] = { 32194 0, 0, 0, Opcode_ae_mulsfs56p24s_hh_Slot_ae_slot1_encode, 0 32195 }; 32196 32197 static xtensa_opcode_encode_fn Opcode_ae_mulss56p24s_hh_encode_fns[] = { 32198 0, 0, 0, Opcode_ae_mulss56p24s_hh_Slot_ae_slot1_encode, 0 32199 }; 32200 32201 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_l_encode_fns[] = { 32202 0, 0, 0, Opcode_ae_mulfq32sp16s_l_Slot_ae_slot1_encode, 0 32203 }; 32204 32205 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16s_h_encode_fns[] = { 32206 0, 0, 0, Opcode_ae_mulfq32sp16s_h_Slot_ae_slot1_encode, 0 32207 }; 32208 32209 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_l_encode_fns[] = { 32210 0, 0, 0, Opcode_ae_mulfq32sp16u_l_Slot_ae_slot1_encode, 0 32211 }; 32212 32213 static xtensa_opcode_encode_fn Opcode_ae_mulfq32sp16u_h_encode_fns[] = { 32214 0, 0, 0, Opcode_ae_mulfq32sp16u_h_Slot_ae_slot1_encode, 0 32215 }; 32216 32217 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_l_encode_fns[] = { 32218 0, 0, 0, Opcode_ae_mulq32sp16s_l_Slot_ae_slot1_encode, 0 32219 }; 32220 32221 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16s_h_encode_fns[] = { 32222 0, 0, 0, Opcode_ae_mulq32sp16s_h_Slot_ae_slot1_encode, 0 32223 }; 32224 32225 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_l_encode_fns[] = { 32226 0, 0, 0, Opcode_ae_mulq32sp16u_l_Slot_ae_slot1_encode, 0 32227 }; 32228 32229 static xtensa_opcode_encode_fn Opcode_ae_mulq32sp16u_h_encode_fns[] = { 32230 0, 0, 0, Opcode_ae_mulq32sp16u_h_Slot_ae_slot1_encode, 0 32231 }; 32232 32233 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_l_encode_fns[] = { 32234 0, 0, 0, Opcode_ae_mulafq32sp16s_l_Slot_ae_slot1_encode, 0 32235 }; 32236 32237 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16s_h_encode_fns[] = { 32238 0, 0, 0, Opcode_ae_mulafq32sp16s_h_Slot_ae_slot1_encode, 0 32239 }; 32240 32241 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_l_encode_fns[] = { 32242 0, 0, 0, Opcode_ae_mulafq32sp16u_l_Slot_ae_slot1_encode, 0 32243 }; 32244 32245 static xtensa_opcode_encode_fn Opcode_ae_mulafq32sp16u_h_encode_fns[] = { 32246 0, 0, 0, Opcode_ae_mulafq32sp16u_h_Slot_ae_slot1_encode, 0 32247 }; 32248 32249 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_l_encode_fns[] = { 32250 0, 0, 0, Opcode_ae_mulaq32sp16s_l_Slot_ae_slot1_encode, 0 32251 }; 32252 32253 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16s_h_encode_fns[] = { 32254 0, 0, 0, Opcode_ae_mulaq32sp16s_h_Slot_ae_slot1_encode, 0 32255 }; 32256 32257 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_l_encode_fns[] = { 32258 0, 0, 0, Opcode_ae_mulaq32sp16u_l_Slot_ae_slot1_encode, 0 32259 }; 32260 32261 static xtensa_opcode_encode_fn Opcode_ae_mulaq32sp16u_h_encode_fns[] = { 32262 0, 0, 0, Opcode_ae_mulaq32sp16u_h_Slot_ae_slot1_encode, 0 32263 }; 32264 32265 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_l_encode_fns[] = { 32266 0, 0, 0, Opcode_ae_mulsfq32sp16s_l_Slot_ae_slot1_encode, 0 32267 }; 32268 32269 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16s_h_encode_fns[] = { 32270 0, 0, 0, Opcode_ae_mulsfq32sp16s_h_Slot_ae_slot1_encode, 0 32271 }; 32272 32273 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_l_encode_fns[] = { 32274 0, 0, 0, Opcode_ae_mulsfq32sp16u_l_Slot_ae_slot1_encode, 0 32275 }; 32276 32277 static xtensa_opcode_encode_fn Opcode_ae_mulsfq32sp16u_h_encode_fns[] = { 32278 0, 0, 0, Opcode_ae_mulsfq32sp16u_h_Slot_ae_slot1_encode, 0 32279 }; 32280 32281 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_l_encode_fns[] = { 32282 0, 0, 0, Opcode_ae_mulsq32sp16s_l_Slot_ae_slot1_encode, 0 32283 }; 32284 32285 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16s_h_encode_fns[] = { 32286 0, 0, 0, Opcode_ae_mulsq32sp16s_h_Slot_ae_slot1_encode, 0 32287 }; 32288 32289 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_l_encode_fns[] = { 32290 0, 0, 0, Opcode_ae_mulsq32sp16u_l_Slot_ae_slot1_encode, 0 32291 }; 32292 32293 static xtensa_opcode_encode_fn Opcode_ae_mulsq32sp16u_h_encode_fns[] = { 32294 0, 0, 0, Opcode_ae_mulsq32sp16u_h_Slot_ae_slot1_encode, 0 32295 }; 32296 32297 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_ll_encode_fns[] = { 32298 0, 0, 0, Opcode_ae_mulzaaq32sp16s_ll_Slot_ae_slot1_encode, 0 32299 }; 32300 32301 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_ll_encode_fns[] = { 32302 0, 0, 0, Opcode_ae_mulzaafq32sp16s_ll_Slot_ae_slot1_encode, 0 32303 }; 32304 32305 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_ll_encode_fns[] = { 32306 0, 0, 0, Opcode_ae_mulzaaq32sp16u_ll_Slot_ae_slot1_encode, 0 32307 }; 32308 32309 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_ll_encode_fns[] = { 32310 0, 0, 0, Opcode_ae_mulzaafq32sp16u_ll_Slot_ae_slot1_encode, 0 32311 }; 32312 32313 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_hh_encode_fns[] = { 32314 0, 0, 0, Opcode_ae_mulzaaq32sp16s_hh_Slot_ae_slot1_encode, 0 32315 }; 32316 32317 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_hh_encode_fns[] = { 32318 0, 0, 0, Opcode_ae_mulzaafq32sp16s_hh_Slot_ae_slot1_encode, 0 32319 }; 32320 32321 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_hh_encode_fns[] = { 32322 0, 0, 0, Opcode_ae_mulzaaq32sp16u_hh_Slot_ae_slot1_encode, 0 32323 }; 32324 32325 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_hh_encode_fns[] = { 32326 0, 0, 0, Opcode_ae_mulzaafq32sp16u_hh_Slot_ae_slot1_encode, 0 32327 }; 32328 32329 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16s_lh_encode_fns[] = { 32330 0, 0, 0, Opcode_ae_mulzaaq32sp16s_lh_Slot_ae_slot1_encode, 0 32331 }; 32332 32333 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16s_lh_encode_fns[] = { 32334 0, 0, 0, Opcode_ae_mulzaafq32sp16s_lh_Slot_ae_slot1_encode, 0 32335 }; 32336 32337 static xtensa_opcode_encode_fn Opcode_ae_mulzaaq32sp16u_lh_encode_fns[] = { 32338 0, 0, 0, Opcode_ae_mulzaaq32sp16u_lh_Slot_ae_slot1_encode, 0 32339 }; 32340 32341 static xtensa_opcode_encode_fn Opcode_ae_mulzaafq32sp16u_lh_encode_fns[] = { 32342 0, 0, 0, Opcode_ae_mulzaafq32sp16u_lh_Slot_ae_slot1_encode, 0 32343 }; 32344 32345 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_ll_encode_fns[] = { 32346 0, 0, 0, Opcode_ae_mulzasq32sp16s_ll_Slot_ae_slot1_encode, 0 32347 }; 32348 32349 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_ll_encode_fns[] = { 32350 0, 0, 0, Opcode_ae_mulzasfq32sp16s_ll_Slot_ae_slot1_encode, 0 32351 }; 32352 32353 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_ll_encode_fns[] = { 32354 0, 0, 0, Opcode_ae_mulzasq32sp16u_ll_Slot_ae_slot1_encode, 0 32355 }; 32356 32357 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_ll_encode_fns[] = { 32358 0, 0, 0, Opcode_ae_mulzasfq32sp16u_ll_Slot_ae_slot1_encode, 0 32359 }; 32360 32361 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_hh_encode_fns[] = { 32362 0, 0, 0, Opcode_ae_mulzasq32sp16s_hh_Slot_ae_slot1_encode, 0 32363 }; 32364 32365 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_hh_encode_fns[] = { 32366 0, 0, 0, Opcode_ae_mulzasfq32sp16s_hh_Slot_ae_slot1_encode, 0 32367 }; 32368 32369 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_hh_encode_fns[] = { 32370 0, 0, 0, Opcode_ae_mulzasq32sp16u_hh_Slot_ae_slot1_encode, 0 32371 }; 32372 32373 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_hh_encode_fns[] = { 32374 0, 0, 0, Opcode_ae_mulzasfq32sp16u_hh_Slot_ae_slot1_encode, 0 32375 }; 32376 32377 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16s_lh_encode_fns[] = { 32378 0, 0, 0, Opcode_ae_mulzasq32sp16s_lh_Slot_ae_slot1_encode, 0 32379 }; 32380 32381 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16s_lh_encode_fns[] = { 32382 0, 0, 0, Opcode_ae_mulzasfq32sp16s_lh_Slot_ae_slot1_encode, 0 32383 }; 32384 32385 static xtensa_opcode_encode_fn Opcode_ae_mulzasq32sp16u_lh_encode_fns[] = { 32386 0, 0, 0, Opcode_ae_mulzasq32sp16u_lh_Slot_ae_slot1_encode, 0 32387 }; 32388 32389 static xtensa_opcode_encode_fn Opcode_ae_mulzasfq32sp16u_lh_encode_fns[] = { 32390 0, 0, 0, Opcode_ae_mulzasfq32sp16u_lh_Slot_ae_slot1_encode, 0 32391 }; 32392 32393 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_ll_encode_fns[] = { 32394 0, 0, 0, Opcode_ae_mulzsaq32sp16s_ll_Slot_ae_slot1_encode, 0 32395 }; 32396 32397 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_ll_encode_fns[] = { 32398 0, 0, 0, Opcode_ae_mulzsafq32sp16s_ll_Slot_ae_slot1_encode, 0 32399 }; 32400 32401 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_ll_encode_fns[] = { 32402 0, 0, 0, Opcode_ae_mulzsaq32sp16u_ll_Slot_ae_slot1_encode, 0 32403 }; 32404 32405 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_ll_encode_fns[] = { 32406 0, 0, 0, Opcode_ae_mulzsafq32sp16u_ll_Slot_ae_slot1_encode, 0 32407 }; 32408 32409 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_hh_encode_fns[] = { 32410 0, 0, 0, Opcode_ae_mulzsaq32sp16s_hh_Slot_ae_slot1_encode, 0 32411 }; 32412 32413 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_hh_encode_fns[] = { 32414 0, 0, 0, Opcode_ae_mulzsafq32sp16s_hh_Slot_ae_slot1_encode, 0 32415 }; 32416 32417 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_hh_encode_fns[] = { 32418 0, 0, 0, Opcode_ae_mulzsaq32sp16u_hh_Slot_ae_slot1_encode, 0 32419 }; 32420 32421 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_hh_encode_fns[] = { 32422 0, 0, 0, Opcode_ae_mulzsafq32sp16u_hh_Slot_ae_slot1_encode, 0 32423 }; 32424 32425 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16s_lh_encode_fns[] = { 32426 0, 0, 0, Opcode_ae_mulzsaq32sp16s_lh_Slot_ae_slot1_encode, 0 32427 }; 32428 32429 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16s_lh_encode_fns[] = { 32430 0, 0, 0, Opcode_ae_mulzsafq32sp16s_lh_Slot_ae_slot1_encode, 0 32431 }; 32432 32433 static xtensa_opcode_encode_fn Opcode_ae_mulzsaq32sp16u_lh_encode_fns[] = { 32434 0, 0, 0, Opcode_ae_mulzsaq32sp16u_lh_Slot_ae_slot1_encode, 0 32435 }; 32436 32437 static xtensa_opcode_encode_fn Opcode_ae_mulzsafq32sp16u_lh_encode_fns[] = { 32438 0, 0, 0, Opcode_ae_mulzsafq32sp16u_lh_Slot_ae_slot1_encode, 0 32439 }; 32440 32441 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_ll_encode_fns[] = { 32442 0, 0, 0, Opcode_ae_mulzssq32sp16s_ll_Slot_ae_slot1_encode, 0 32443 }; 32444 32445 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_ll_encode_fns[] = { 32446 0, 0, 0, Opcode_ae_mulzssfq32sp16s_ll_Slot_ae_slot1_encode, 0 32447 }; 32448 32449 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_ll_encode_fns[] = { 32450 0, 0, 0, Opcode_ae_mulzssq32sp16u_ll_Slot_ae_slot1_encode, 0 32451 }; 32452 32453 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_ll_encode_fns[] = { 32454 0, 0, 0, Opcode_ae_mulzssfq32sp16u_ll_Slot_ae_slot1_encode, 0 32455 }; 32456 32457 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_hh_encode_fns[] = { 32458 0, 0, 0, Opcode_ae_mulzssq32sp16s_hh_Slot_ae_slot1_encode, 0 32459 }; 32460 32461 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_hh_encode_fns[] = { 32462 0, 0, 0, Opcode_ae_mulzssfq32sp16s_hh_Slot_ae_slot1_encode, 0 32463 }; 32464 32465 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_hh_encode_fns[] = { 32466 0, 0, 0, Opcode_ae_mulzssq32sp16u_hh_Slot_ae_slot1_encode, 0 32467 }; 32468 32469 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_hh_encode_fns[] = { 32470 0, 0, 0, Opcode_ae_mulzssfq32sp16u_hh_Slot_ae_slot1_encode, 0 32471 }; 32472 32473 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16s_lh_encode_fns[] = { 32474 0, 0, 0, Opcode_ae_mulzssq32sp16s_lh_Slot_ae_slot1_encode, 0 32475 }; 32476 32477 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16s_lh_encode_fns[] = { 32478 0, 0, 0, Opcode_ae_mulzssfq32sp16s_lh_Slot_ae_slot1_encode, 0 32479 }; 32480 32481 static xtensa_opcode_encode_fn Opcode_ae_mulzssq32sp16u_lh_encode_fns[] = { 32482 0, 0, 0, Opcode_ae_mulzssq32sp16u_lh_Slot_ae_slot1_encode, 0 32483 }; 32484 32485 static xtensa_opcode_encode_fn Opcode_ae_mulzssfq32sp16u_lh_encode_fns[] = { 32486 0, 0, 0, Opcode_ae_mulzssfq32sp16u_lh_Slot_ae_slot1_encode, 0 32487 }; 32488 32489 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hh_ll_encode_fns[] = { 32490 0, 0, 0, Opcode_ae_mulzaafp24s_hh_ll_Slot_ae_slot1_encode, 0 32491 }; 32492 32493 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hh_ll_encode_fns[] = { 32494 0, 0, 0, Opcode_ae_mulzaap24s_hh_ll_Slot_ae_slot1_encode, 0 32495 }; 32496 32497 static xtensa_opcode_encode_fn Opcode_ae_mulzaafp24s_hl_lh_encode_fns[] = { 32498 0, 0, 0, Opcode_ae_mulzaafp24s_hl_lh_Slot_ae_slot1_encode, 0 32499 }; 32500 32501 static xtensa_opcode_encode_fn Opcode_ae_mulzaap24s_hl_lh_encode_fns[] = { 32502 0, 0, 0, Opcode_ae_mulzaap24s_hl_lh_Slot_ae_slot1_encode, 0 32503 }; 32504 32505 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hh_ll_encode_fns[] = { 32506 0, 0, 0, Opcode_ae_mulzasfp24s_hh_ll_Slot_ae_slot1_encode, 0 32507 }; 32508 32509 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hh_ll_encode_fns[] = { 32510 0, 0, 0, Opcode_ae_mulzasp24s_hh_ll_Slot_ae_slot1_encode, 0 32511 }; 32512 32513 static xtensa_opcode_encode_fn Opcode_ae_mulzasfp24s_hl_lh_encode_fns[] = { 32514 0, 0, 0, Opcode_ae_mulzasfp24s_hl_lh_Slot_ae_slot1_encode, 0 32515 }; 32516 32517 static xtensa_opcode_encode_fn Opcode_ae_mulzasp24s_hl_lh_encode_fns[] = { 32518 0, 0, 0, Opcode_ae_mulzasp24s_hl_lh_Slot_ae_slot1_encode, 0 32519 }; 32520 32521 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hh_ll_encode_fns[] = { 32522 0, 0, 0, Opcode_ae_mulzsafp24s_hh_ll_Slot_ae_slot1_encode, 0 32523 }; 32524 32525 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hh_ll_encode_fns[] = { 32526 0, 0, 0, Opcode_ae_mulzsap24s_hh_ll_Slot_ae_slot1_encode, 0 32527 }; 32528 32529 static xtensa_opcode_encode_fn Opcode_ae_mulzsafp24s_hl_lh_encode_fns[] = { 32530 0, 0, 0, Opcode_ae_mulzsafp24s_hl_lh_Slot_ae_slot1_encode, 0 32531 }; 32532 32533 static xtensa_opcode_encode_fn Opcode_ae_mulzsap24s_hl_lh_encode_fns[] = { 32534 0, 0, 0, Opcode_ae_mulzsap24s_hl_lh_Slot_ae_slot1_encode, 0 32535 }; 32536 32537 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hh_ll_encode_fns[] = { 32538 0, 0, 0, Opcode_ae_mulzssfp24s_hh_ll_Slot_ae_slot1_encode, 0 32539 }; 32540 32541 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hh_ll_encode_fns[] = { 32542 0, 0, 0, Opcode_ae_mulzssp24s_hh_ll_Slot_ae_slot1_encode, 0 32543 }; 32544 32545 static xtensa_opcode_encode_fn Opcode_ae_mulzssfp24s_hl_lh_encode_fns[] = { 32546 0, 0, 0, Opcode_ae_mulzssfp24s_hl_lh_Slot_ae_slot1_encode, 0 32547 }; 32548 32549 static xtensa_opcode_encode_fn Opcode_ae_mulzssp24s_hl_lh_encode_fns[] = { 32550 0, 0, 0, Opcode_ae_mulzssp24s_hl_lh_Slot_ae_slot1_encode, 0 32551 }; 32552 32553 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hh_ll_encode_fns[] = { 32554 0, 0, 0, Opcode_ae_mulaafp24s_hh_ll_Slot_ae_slot1_encode, 0 32555 }; 32556 32557 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hh_ll_encode_fns[] = { 32558 0, 0, 0, Opcode_ae_mulaap24s_hh_ll_Slot_ae_slot1_encode, 0 32559 }; 32560 32561 static xtensa_opcode_encode_fn Opcode_ae_mulaafp24s_hl_lh_encode_fns[] = { 32562 0, 0, 0, Opcode_ae_mulaafp24s_hl_lh_Slot_ae_slot1_encode, 0 32563 }; 32564 32565 static xtensa_opcode_encode_fn Opcode_ae_mulaap24s_hl_lh_encode_fns[] = { 32566 0, 0, 0, Opcode_ae_mulaap24s_hl_lh_Slot_ae_slot1_encode, 0 32567 }; 32568 32569 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hh_ll_encode_fns[] = { 32570 0, 0, 0, Opcode_ae_mulasfp24s_hh_ll_Slot_ae_slot1_encode, 0 32571 }; 32572 32573 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hh_ll_encode_fns[] = { 32574 0, 0, 0, Opcode_ae_mulasp24s_hh_ll_Slot_ae_slot1_encode, 0 32575 }; 32576 32577 static xtensa_opcode_encode_fn Opcode_ae_mulasfp24s_hl_lh_encode_fns[] = { 32578 0, 0, 0, Opcode_ae_mulasfp24s_hl_lh_Slot_ae_slot1_encode, 0 32579 }; 32580 32581 static xtensa_opcode_encode_fn Opcode_ae_mulasp24s_hl_lh_encode_fns[] = { 32582 0, 0, 0, Opcode_ae_mulasp24s_hl_lh_Slot_ae_slot1_encode, 0 32583 }; 32584 32585 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hh_ll_encode_fns[] = { 32586 0, 0, 0, Opcode_ae_mulsafp24s_hh_ll_Slot_ae_slot1_encode, 0 32587 }; 32588 32589 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hh_ll_encode_fns[] = { 32590 0, 0, 0, Opcode_ae_mulsap24s_hh_ll_Slot_ae_slot1_encode, 0 32591 }; 32592 32593 static xtensa_opcode_encode_fn Opcode_ae_mulsafp24s_hl_lh_encode_fns[] = { 32594 0, 0, 0, Opcode_ae_mulsafp24s_hl_lh_Slot_ae_slot1_encode, 0 32595 }; 32596 32597 static xtensa_opcode_encode_fn Opcode_ae_mulsap24s_hl_lh_encode_fns[] = { 32598 0, 0, 0, Opcode_ae_mulsap24s_hl_lh_Slot_ae_slot1_encode, 0 32599 }; 32600 32601 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hh_ll_encode_fns[] = { 32602 0, 0, 0, Opcode_ae_mulssfp24s_hh_ll_Slot_ae_slot1_encode, 0 32603 }; 32604 32605 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hh_ll_encode_fns[] = { 32606 0, 0, 0, Opcode_ae_mulssp24s_hh_ll_Slot_ae_slot1_encode, 0 32607 }; 32608 32609 static xtensa_opcode_encode_fn Opcode_ae_mulssfp24s_hl_lh_encode_fns[] = { 32610 0, 0, 0, Opcode_ae_mulssfp24s_hl_lh_Slot_ae_slot1_encode, 0 32611 }; 32612 32613 static xtensa_opcode_encode_fn Opcode_ae_mulssp24s_hl_lh_encode_fns[] = { 32614 0, 0, 0, Opcode_ae_mulssp24s_hl_lh_Slot_ae_slot1_encode, 0 32615 }; 32616 32617 static xtensa_opcode_encode_fn Opcode_ae_sha32_encode_fns[] = { 32618 Opcode_ae_sha32_Slot_inst_encode, 0, 0, 0, 0 32619 }; 32620 32621 static xtensa_opcode_encode_fn Opcode_ae_vldl32t_encode_fns[] = { 32622 Opcode_ae_vldl32t_Slot_inst_encode, 0, 0, 0, 0 32623 }; 32624 32625 static xtensa_opcode_encode_fn Opcode_ae_vldl16t_encode_fns[] = { 32626 Opcode_ae_vldl16t_Slot_inst_encode, 0, 0, 0, 0 32627 }; 32628 32629 static xtensa_opcode_encode_fn Opcode_ae_vldl16c_encode_fns[] = { 32630 Opcode_ae_vldl16c_Slot_inst_encode, 0, 0, 0, 0 32631 }; 32632 32633 static xtensa_opcode_encode_fn Opcode_ae_vldsht_encode_fns[] = { 32634 Opcode_ae_vldsht_Slot_inst_encode, 0, 0, 0, 0 32635 }; 32636 32637 static xtensa_opcode_encode_fn Opcode_ae_lb_encode_fns[] = { 32638 Opcode_ae_lb_Slot_inst_encode, 0, 0, 0, 0 32639 }; 32640 32641 static xtensa_opcode_encode_fn Opcode_ae_lbi_encode_fns[] = { 32642 Opcode_ae_lbi_Slot_inst_encode, 0, 0, 0, 0 32643 }; 32644 32645 static xtensa_opcode_encode_fn Opcode_ae_lbk_encode_fns[] = { 32646 Opcode_ae_lbk_Slot_inst_encode, 0, 0, 0, 0 32647 }; 32648 32649 static xtensa_opcode_encode_fn Opcode_ae_lbki_encode_fns[] = { 32650 Opcode_ae_lbki_Slot_inst_encode, 0, 0, 0, 0 32651 }; 32652 32653 static xtensa_opcode_encode_fn Opcode_ae_db_encode_fns[] = { 32654 Opcode_ae_db_Slot_inst_encode, 0, 0, 0, 0 32655 }; 32656 32657 static xtensa_opcode_encode_fn Opcode_ae_dbi_encode_fns[] = { 32658 Opcode_ae_dbi_Slot_inst_encode, 0, 0, 0, 0 32659 }; 32660 32661 static xtensa_opcode_encode_fn Opcode_ae_vlel32t_encode_fns[] = { 32662 Opcode_ae_vlel32t_Slot_inst_encode, 0, 0, 0, 0 32663 }; 32664 32665 static xtensa_opcode_encode_fn Opcode_ae_vlel16t_encode_fns[] = { 32666 Opcode_ae_vlel16t_Slot_inst_encode, 0, 0, 0, 0 32667 }; 32668 32669 static xtensa_opcode_encode_fn Opcode_ae_sb_encode_fns[] = { 32670 Opcode_ae_sb_Slot_inst_encode, 0, 0, 0, 0 32671 }; 32672 32673 static xtensa_opcode_encode_fn Opcode_ae_sbi_encode_fns[] = { 32674 Opcode_ae_sbi_Slot_inst_encode, 0, 0, 0, 0 32675 }; 32676 32677 static xtensa_opcode_encode_fn Opcode_ae_vles16c_encode_fns[] = { 32678 Opcode_ae_vles16c_Slot_inst_encode, 0, 0, 0, 0 32679 }; 32680 32681 static xtensa_opcode_encode_fn Opcode_ae_sbf_encode_fns[] = { 32682 Opcode_ae_sbf_Slot_inst_encode, 0, 0, 0, 0 32683 }; 32684 32685 static xtensa_opcode_encode_fn Opcode_ae_slaasq56s_encode_fns[] = { 32686 0, 0, 0, 0, Opcode_ae_slaasq56s_Slot_ae_slot0_encode 32687 }; 32688 32689 static xtensa_opcode_encode_fn Opcode_ae_addbrba32_encode_fns[] = { 32690 0, 0, 0, 0, Opcode_ae_addbrba32_Slot_ae_slot0_encode 32691 }; 32692 32693 static xtensa_opcode_encode_fn Opcode_ae_minabssp24s_encode_fns[] = { 32694 0, 0, 0, Opcode_ae_minabssp24s_Slot_ae_slot1_encode, 0 32695 }; 32696 32697 static xtensa_opcode_encode_fn Opcode_ae_maxabssp24s_encode_fns[] = { 32698 0, 0, 0, Opcode_ae_maxabssp24s_Slot_ae_slot1_encode, 0 32699 }; 32700 32701 static xtensa_opcode_encode_fn Opcode_ae_minabssq56s_encode_fns[] = { 32702 0, 0, 0, Opcode_ae_minabssq56s_Slot_ae_slot1_encode, 0 32703 }; 32704 32705 static xtensa_opcode_encode_fn Opcode_ae_maxabssq56s_encode_fns[] = { 32706 0, 0, 0, Opcode_ae_maxabssq56s_Slot_ae_slot1_encode, 0 32707 }; 32708 32709 static xtensa_opcode_encode_fn Opcode_rur_ae_cbegin0_encode_fns[] = { 32710 Opcode_rur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 32711 }; 32712 32713 static xtensa_opcode_encode_fn Opcode_wur_ae_cbegin0_encode_fns[] = { 32714 Opcode_wur_ae_cbegin0_Slot_inst_encode, 0, 0, 0, 0 32715 }; 32716 32717 static xtensa_opcode_encode_fn Opcode_rur_ae_cend0_encode_fns[] = { 32718 Opcode_rur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 32719 }; 32720 32721 static xtensa_opcode_encode_fn Opcode_wur_ae_cend0_encode_fns[] = { 32722 Opcode_wur_ae_cend0_Slot_inst_encode, 0, 0, 0, 0 32723 }; 32724 32725 static xtensa_opcode_encode_fn Opcode_ae_lp24x2_c_encode_fns[] = { 32726 0, 0, 0, 0, Opcode_ae_lp24x2_c_Slot_ae_slot0_encode 32727 }; 32728 32729 static xtensa_opcode_encode_fn Opcode_ae_sp24x2s_c_encode_fns[] = { 32730 0, 0, 0, 0, Opcode_ae_sp24x2s_c_Slot_ae_slot0_encode 32731 }; 32732 32733 static xtensa_opcode_encode_fn Opcode_ae_lp24x2f_c_encode_fns[] = { 32734 0, 0, 0, 0, Opcode_ae_lp24x2f_c_Slot_ae_slot0_encode 32735 }; 32736 32737 static xtensa_opcode_encode_fn Opcode_ae_sp24x2f_c_encode_fns[] = { 32738 0, 0, 0, 0, Opcode_ae_sp24x2f_c_Slot_ae_slot0_encode 32739 }; 32740 32741 static xtensa_opcode_encode_fn Opcode_ae_lp16x2f_c_encode_fns[] = { 32742 0, 0, 0, 0, Opcode_ae_lp16x2f_c_Slot_ae_slot0_encode 32743 }; 32744 32745 static xtensa_opcode_encode_fn Opcode_ae_sp16x2f_c_encode_fns[] = { 32746 0, 0, 0, 0, Opcode_ae_sp16x2f_c_Slot_ae_slot0_encode 32747 }; 32748 32749 static xtensa_opcode_encode_fn Opcode_ae_lp24_c_encode_fns[] = { 32750 0, 0, 0, 0, Opcode_ae_lp24_c_Slot_ae_slot0_encode 32751 }; 32752 32753 static xtensa_opcode_encode_fn Opcode_ae_sp24s_l_c_encode_fns[] = { 32754 0, 0, 0, 0, Opcode_ae_sp24s_l_c_Slot_ae_slot0_encode 32755 }; 32756 32757 static xtensa_opcode_encode_fn Opcode_ae_lp24f_c_encode_fns[] = { 32758 0, 0, 0, 0, Opcode_ae_lp24f_c_Slot_ae_slot0_encode 32759 }; 32760 32761 static xtensa_opcode_encode_fn Opcode_ae_sp24f_l_c_encode_fns[] = { 32762 0, 0, 0, 0, Opcode_ae_sp24f_l_c_Slot_ae_slot0_encode 32763 }; 32764 32765 static xtensa_opcode_encode_fn Opcode_ae_lp16f_c_encode_fns[] = { 32766 0, 0, 0, 0, Opcode_ae_lp16f_c_Slot_ae_slot0_encode 32767 }; 32768 32769 static xtensa_opcode_encode_fn Opcode_ae_sp16f_l_c_encode_fns[] = { 32770 0, 0, 0, 0, Opcode_ae_sp16f_l_c_Slot_ae_slot0_encode 32771 }; 32772 32773 static xtensa_opcode_encode_fn Opcode_ae_lq56_c_encode_fns[] = { 32774 0, 0, 0, 0, Opcode_ae_lq56_c_Slot_ae_slot0_encode 32775 }; 32776 32777 static xtensa_opcode_encode_fn Opcode_ae_sq56s_c_encode_fns[] = { 32778 0, 0, 0, 0, Opcode_ae_sq56s_c_Slot_ae_slot0_encode 32779 }; 32780 32781 static xtensa_opcode_encode_fn Opcode_ae_lq32f_c_encode_fns[] = { 32782 0, 0, 0, 0, Opcode_ae_lq32f_c_Slot_ae_slot0_encode 32783 }; 32784 32785 static xtensa_opcode_encode_fn Opcode_ae_sq32f_c_encode_fns[] = { 32786 0, 0, 0, 0, Opcode_ae_sq32f_c_Slot_ae_slot0_encode 32787 }; 32788 32789 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = { 32790 Opcode_rur_expstate_Slot_inst_encode, 0, 0, 0, 0 32791 }; 32792 32793 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = { 32794 Opcode_wur_expstate_Slot_inst_encode, 0, 0, 0, 0 32795 }; 32796 32797 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = { 32798 Opcode_read_impwire_Slot_inst_encode, 0, 0, 0, 0 32799 }; 32800 32801 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = { 32802 Opcode_setb_expstate_Slot_inst_encode, 0, 0, 0, 0 32803 }; 32804 32805 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = { 32806 Opcode_clrb_expstate_Slot_inst_encode, 0, 0, 0, 0 32807 }; 32808 32809 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = { 32810 Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0, 0, 0 32811 }; 32812 32813 32814 32815 32816 32817 /* Opcode table. */ 32818 32819 static xtensa_funcUnit_use Opcode_ae_vldl32t_funcUnit_uses[] = { 32820 { FUNCUNIT_ae_add32, 3 } 32821 }; 32822 32823 static xtensa_funcUnit_use Opcode_ae_vldl16t_funcUnit_uses[] = { 32824 { FUNCUNIT_ae_add32, 3 } 32825 }; 32826 32827 static xtensa_funcUnit_use Opcode_ae_vldl16c_funcUnit_uses[] = { 32828 { FUNCUNIT_ae_shift32x4, 2 }, 32829 { FUNCUNIT_ae_shift32x5, 3 }, 32830 { FUNCUNIT_ae_add32, 3 } 32831 }; 32832 32833 static xtensa_funcUnit_use Opcode_ae_vldsht_funcUnit_uses[] = { 32834 { FUNCUNIT_ae_shift32x4, 2 }, 32835 { FUNCUNIT_ae_shift32x5, 3 }, 32836 { FUNCUNIT_ae_add32, 3 } 32837 }; 32838 32839 static xtensa_funcUnit_use Opcode_ae_lb_funcUnit_uses[] = { 32840 { FUNCUNIT_ae_subshift, 2 } 32841 }; 32842 32843 static xtensa_funcUnit_use Opcode_ae_lbi_funcUnit_uses[] = { 32844 { FUNCUNIT_ae_subshift, 2 } 32845 }; 32846 32847 static xtensa_funcUnit_use Opcode_ae_lbk_funcUnit_uses[] = { 32848 { FUNCUNIT_ae_subshift, 2 } 32849 }; 32850 32851 static xtensa_funcUnit_use Opcode_ae_lbki_funcUnit_uses[] = { 32852 { FUNCUNIT_ae_subshift, 2 } 32853 }; 32854 32855 static xtensa_funcUnit_use Opcode_ae_db_funcUnit_uses[] = { 32856 { FUNCUNIT_ae_shift32x4, 2 }, 32857 { FUNCUNIT_ae_subshift, 2 } 32858 }; 32859 32860 static xtensa_funcUnit_use Opcode_ae_dbi_funcUnit_uses[] = { 32861 { FUNCUNIT_ae_shift32x4, 2 }, 32862 { FUNCUNIT_ae_subshift, 2 } 32863 }; 32864 32865 static xtensa_funcUnit_use Opcode_ae_vlel32t_funcUnit_uses[] = { 32866 { FUNCUNIT_ae_add32, 3 } 32867 }; 32868 32869 static xtensa_funcUnit_use Opcode_ae_vlel16t_funcUnit_uses[] = { 32870 { FUNCUNIT_ae_add32, 3 } 32871 }; 32872 32873 static xtensa_funcUnit_use Opcode_ae_sb_funcUnit_uses[] = { 32874 { FUNCUNIT_ae_shift32x4, 2 }, 32875 { FUNCUNIT_ae_subshift, 2 } 32876 }; 32877 32878 static xtensa_funcUnit_use Opcode_ae_sbi_funcUnit_uses[] = { 32879 { FUNCUNIT_ae_shift32x4, 2 }, 32880 { FUNCUNIT_ae_subshift, 2 } 32881 }; 32882 32883 static xtensa_funcUnit_use Opcode_ae_vles16c_funcUnit_uses[] = { 32884 { FUNCUNIT_ae_shift32x4, 2 }, 32885 { FUNCUNIT_ae_subshift, 2 } 32886 }; 32887 32888 static xtensa_funcUnit_use Opcode_ae_sbf_funcUnit_uses[] = { 32889 { FUNCUNIT_ae_shift32x4, 2 }, 32890 { FUNCUNIT_ae_subshift, 2 } 32891 }; 32892 32893 static xtensa_opcode_internal opcodes[] = { 32894 { "excw", ICLASS_xt_iclass_excw, 32895 0, 32896 Opcode_excw_encode_fns, 0, 0 }, 32897 { "rfe", ICLASS_xt_iclass_rfe, 32898 XTENSA_OPCODE_IS_JUMP, 32899 Opcode_rfe_encode_fns, 0, 0 }, 32900 { "rfde", ICLASS_xt_iclass_rfde, 32901 XTENSA_OPCODE_IS_JUMP, 32902 Opcode_rfde_encode_fns, 0, 0 }, 32903 { "syscall", ICLASS_xt_iclass_syscall, 32904 0, 32905 Opcode_syscall_encode_fns, 0, 0 }, 32906 { "call12", ICLASS_xt_iclass_call12, 32907 XTENSA_OPCODE_IS_CALL, 32908 Opcode_call12_encode_fns, 0, 0 }, 32909 { "call8", ICLASS_xt_iclass_call8, 32910 XTENSA_OPCODE_IS_CALL, 32911 Opcode_call8_encode_fns, 0, 0 }, 32912 { "call4", ICLASS_xt_iclass_call4, 32913 XTENSA_OPCODE_IS_CALL, 32914 Opcode_call4_encode_fns, 0, 0 }, 32915 { "callx12", ICLASS_xt_iclass_callx12, 32916 XTENSA_OPCODE_IS_CALL, 32917 Opcode_callx12_encode_fns, 0, 0 }, 32918 { "callx8", ICLASS_xt_iclass_callx8, 32919 XTENSA_OPCODE_IS_CALL, 32920 Opcode_callx8_encode_fns, 0, 0 }, 32921 { "callx4", ICLASS_xt_iclass_callx4, 32922 XTENSA_OPCODE_IS_CALL, 32923 Opcode_callx4_encode_fns, 0, 0 }, 32924 { "entry", ICLASS_xt_iclass_entry, 32925 0, 32926 Opcode_entry_encode_fns, 0, 0 }, 32927 { "movsp", ICLASS_xt_iclass_movsp, 32928 0, 32929 Opcode_movsp_encode_fns, 0, 0 }, 32930 { "rotw", ICLASS_xt_iclass_rotw, 32931 0, 32932 Opcode_rotw_encode_fns, 0, 0 }, 32933 { "retw", ICLASS_xt_iclass_retw, 32934 XTENSA_OPCODE_IS_JUMP, 32935 Opcode_retw_encode_fns, 0, 0 }, 32936 { "retw.n", ICLASS_xt_iclass_retw, 32937 XTENSA_OPCODE_IS_JUMP, 32938 Opcode_retw_n_encode_fns, 0, 0 }, 32939 { "rfwo", ICLASS_xt_iclass_rfwou, 32940 XTENSA_OPCODE_IS_JUMP, 32941 Opcode_rfwo_encode_fns, 0, 0 }, 32942 { "rfwu", ICLASS_xt_iclass_rfwou, 32943 XTENSA_OPCODE_IS_JUMP, 32944 Opcode_rfwu_encode_fns, 0, 0 }, 32945 { "l32e", ICLASS_xt_iclass_l32e, 32946 0, 32947 Opcode_l32e_encode_fns, 0, 0 }, 32948 { "s32e", ICLASS_xt_iclass_s32e, 32949 0, 32950 Opcode_s32e_encode_fns, 0, 0 }, 32951 { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase, 32952 0, 32953 Opcode_rsr_windowbase_encode_fns, 0, 0 }, 32954 { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase, 32955 0, 32956 Opcode_wsr_windowbase_encode_fns, 0, 0 }, 32957 { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase, 32958 0, 32959 Opcode_xsr_windowbase_encode_fns, 0, 0 }, 32960 { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart, 32961 0, 32962 Opcode_rsr_windowstart_encode_fns, 0, 0 }, 32963 { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart, 32964 0, 32965 Opcode_wsr_windowstart_encode_fns, 0, 0 }, 32966 { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart, 32967 0, 32968 Opcode_xsr_windowstart_encode_fns, 0, 0 }, 32969 { "add.n", ICLASS_xt_iclass_add_n, 32970 0, 32971 Opcode_add_n_encode_fns, 0, 0 }, 32972 { "addi.n", ICLASS_xt_iclass_addi_n, 32973 0, 32974 Opcode_addi_n_encode_fns, 0, 0 }, 32975 { "beqz.n", ICLASS_xt_iclass_bz6, 32976 XTENSA_OPCODE_IS_BRANCH, 32977 Opcode_beqz_n_encode_fns, 0, 0 }, 32978 { "bnez.n", ICLASS_xt_iclass_bz6, 32979 XTENSA_OPCODE_IS_BRANCH, 32980 Opcode_bnez_n_encode_fns, 0, 0 }, 32981 { "ill.n", ICLASS_xt_iclass_ill_n, 32982 0, 32983 Opcode_ill_n_encode_fns, 0, 0 }, 32984 { "l32i.n", ICLASS_xt_iclass_loadi4, 32985 0, 32986 Opcode_l32i_n_encode_fns, 0, 0 }, 32987 { "mov.n", ICLASS_xt_iclass_mov_n, 32988 0, 32989 Opcode_mov_n_encode_fns, 0, 0 }, 32990 { "movi.n", ICLASS_xt_iclass_movi_n, 32991 0, 32992 Opcode_movi_n_encode_fns, 0, 0 }, 32993 { "nop.n", ICLASS_xt_iclass_nopn, 32994 0, 32995 Opcode_nop_n_encode_fns, 0, 0 }, 32996 { "ret.n", ICLASS_xt_iclass_retn, 32997 XTENSA_OPCODE_IS_JUMP, 32998 Opcode_ret_n_encode_fns, 0, 0 }, 32999 { "s32i.n", ICLASS_xt_iclass_storei4, 33000 0, 33001 Opcode_s32i_n_encode_fns, 0, 0 }, 33002 { "rur.threadptr", ICLASS_rur_threadptr, 33003 0, 33004 Opcode_rur_threadptr_encode_fns, 0, 0 }, 33005 { "wur.threadptr", ICLASS_wur_threadptr, 33006 0, 33007 Opcode_wur_threadptr_encode_fns, 0, 0 }, 33008 { "addi", ICLASS_xt_iclass_addi, 33009 0, 33010 Opcode_addi_encode_fns, 0, 0 }, 33011 { "addmi", ICLASS_xt_iclass_addmi, 33012 0, 33013 Opcode_addmi_encode_fns, 0, 0 }, 33014 { "add", ICLASS_xt_iclass_addsub, 33015 0, 33016 Opcode_add_encode_fns, 0, 0 }, 33017 { "sub", ICLASS_xt_iclass_addsub, 33018 0, 33019 Opcode_sub_encode_fns, 0, 0 }, 33020 { "addx2", ICLASS_xt_iclass_addsub, 33021 0, 33022 Opcode_addx2_encode_fns, 0, 0 }, 33023 { "addx4", ICLASS_xt_iclass_addsub, 33024 0, 33025 Opcode_addx4_encode_fns, 0, 0 }, 33026 { "addx8", ICLASS_xt_iclass_addsub, 33027 0, 33028 Opcode_addx8_encode_fns, 0, 0 }, 33029 { "subx2", ICLASS_xt_iclass_addsub, 33030 0, 33031 Opcode_subx2_encode_fns, 0, 0 }, 33032 { "subx4", ICLASS_xt_iclass_addsub, 33033 0, 33034 Opcode_subx4_encode_fns, 0, 0 }, 33035 { "subx8", ICLASS_xt_iclass_addsub, 33036 0, 33037 Opcode_subx8_encode_fns, 0, 0 }, 33038 { "and", ICLASS_xt_iclass_bit, 33039 0, 33040 Opcode_and_encode_fns, 0, 0 }, 33041 { "or", ICLASS_xt_iclass_bit, 33042 0, 33043 Opcode_or_encode_fns, 0, 0 }, 33044 { "xor", ICLASS_xt_iclass_bit, 33045 0, 33046 Opcode_xor_encode_fns, 0, 0 }, 33047 { "beqi", ICLASS_xt_iclass_bsi8, 33048 XTENSA_OPCODE_IS_BRANCH, 33049 Opcode_beqi_encode_fns, 0, 0 }, 33050 { "bnei", ICLASS_xt_iclass_bsi8, 33051 XTENSA_OPCODE_IS_BRANCH, 33052 Opcode_bnei_encode_fns, 0, 0 }, 33053 { "bgei", ICLASS_xt_iclass_bsi8, 33054 XTENSA_OPCODE_IS_BRANCH, 33055 Opcode_bgei_encode_fns, 0, 0 }, 33056 { "blti", ICLASS_xt_iclass_bsi8, 33057 XTENSA_OPCODE_IS_BRANCH, 33058 Opcode_blti_encode_fns, 0, 0 }, 33059 { "bbci", ICLASS_xt_iclass_bsi8b, 33060 XTENSA_OPCODE_IS_BRANCH, 33061 Opcode_bbci_encode_fns, 0, 0 }, 33062 { "bbsi", ICLASS_xt_iclass_bsi8b, 33063 XTENSA_OPCODE_IS_BRANCH, 33064 Opcode_bbsi_encode_fns, 0, 0 }, 33065 { "bgeui", ICLASS_xt_iclass_bsi8u, 33066 XTENSA_OPCODE_IS_BRANCH, 33067 Opcode_bgeui_encode_fns, 0, 0 }, 33068 { "bltui", ICLASS_xt_iclass_bsi8u, 33069 XTENSA_OPCODE_IS_BRANCH, 33070 Opcode_bltui_encode_fns, 0, 0 }, 33071 { "beq", ICLASS_xt_iclass_bst8, 33072 XTENSA_OPCODE_IS_BRANCH, 33073 Opcode_beq_encode_fns, 0, 0 }, 33074 { "bne", ICLASS_xt_iclass_bst8, 33075 XTENSA_OPCODE_IS_BRANCH, 33076 Opcode_bne_encode_fns, 0, 0 }, 33077 { "bge", ICLASS_xt_iclass_bst8, 33078 XTENSA_OPCODE_IS_BRANCH, 33079 Opcode_bge_encode_fns, 0, 0 }, 33080 { "blt", ICLASS_xt_iclass_bst8, 33081 XTENSA_OPCODE_IS_BRANCH, 33082 Opcode_blt_encode_fns, 0, 0 }, 33083 { "bgeu", ICLASS_xt_iclass_bst8, 33084 XTENSA_OPCODE_IS_BRANCH, 33085 Opcode_bgeu_encode_fns, 0, 0 }, 33086 { "bltu", ICLASS_xt_iclass_bst8, 33087 XTENSA_OPCODE_IS_BRANCH, 33088 Opcode_bltu_encode_fns, 0, 0 }, 33089 { "bany", ICLASS_xt_iclass_bst8, 33090 XTENSA_OPCODE_IS_BRANCH, 33091 Opcode_bany_encode_fns, 0, 0 }, 33092 { "bnone", ICLASS_xt_iclass_bst8, 33093 XTENSA_OPCODE_IS_BRANCH, 33094 Opcode_bnone_encode_fns, 0, 0 }, 33095 { "ball", ICLASS_xt_iclass_bst8, 33096 XTENSA_OPCODE_IS_BRANCH, 33097 Opcode_ball_encode_fns, 0, 0 }, 33098 { "bnall", ICLASS_xt_iclass_bst8, 33099 XTENSA_OPCODE_IS_BRANCH, 33100 Opcode_bnall_encode_fns, 0, 0 }, 33101 { "bbc", ICLASS_xt_iclass_bst8, 33102 XTENSA_OPCODE_IS_BRANCH, 33103 Opcode_bbc_encode_fns, 0, 0 }, 33104 { "bbs", ICLASS_xt_iclass_bst8, 33105 XTENSA_OPCODE_IS_BRANCH, 33106 Opcode_bbs_encode_fns, 0, 0 }, 33107 { "beqz", ICLASS_xt_iclass_bsz12, 33108 XTENSA_OPCODE_IS_BRANCH, 33109 Opcode_beqz_encode_fns, 0, 0 }, 33110 { "bnez", ICLASS_xt_iclass_bsz12, 33111 XTENSA_OPCODE_IS_BRANCH, 33112 Opcode_bnez_encode_fns, 0, 0 }, 33113 { "bgez", ICLASS_xt_iclass_bsz12, 33114 XTENSA_OPCODE_IS_BRANCH, 33115 Opcode_bgez_encode_fns, 0, 0 }, 33116 { "bltz", ICLASS_xt_iclass_bsz12, 33117 XTENSA_OPCODE_IS_BRANCH, 33118 Opcode_bltz_encode_fns, 0, 0 }, 33119 { "call0", ICLASS_xt_iclass_call0, 33120 XTENSA_OPCODE_IS_CALL, 33121 Opcode_call0_encode_fns, 0, 0 }, 33122 { "callx0", ICLASS_xt_iclass_callx0, 33123 XTENSA_OPCODE_IS_CALL, 33124 Opcode_callx0_encode_fns, 0, 0 }, 33125 { "extui", ICLASS_xt_iclass_exti, 33126 0, 33127 Opcode_extui_encode_fns, 0, 0 }, 33128 { "ill", ICLASS_xt_iclass_ill, 33129 0, 33130 Opcode_ill_encode_fns, 0, 0 }, 33131 { "j", ICLASS_xt_iclass_jump, 33132 XTENSA_OPCODE_IS_JUMP, 33133 Opcode_j_encode_fns, 0, 0 }, 33134 { "jx", ICLASS_xt_iclass_jumpx, 33135 XTENSA_OPCODE_IS_JUMP, 33136 Opcode_jx_encode_fns, 0, 0 }, 33137 { "l16ui", ICLASS_xt_iclass_l16ui, 33138 0, 33139 Opcode_l16ui_encode_fns, 0, 0 }, 33140 { "l16si", ICLASS_xt_iclass_l16si, 33141 0, 33142 Opcode_l16si_encode_fns, 0, 0 }, 33143 { "l32i", ICLASS_xt_iclass_l32i, 33144 0, 33145 Opcode_l32i_encode_fns, 0, 0 }, 33146 { "l32r", ICLASS_xt_iclass_l32r, 33147 0, 33148 Opcode_l32r_encode_fns, 0, 0 }, 33149 { "l8ui", ICLASS_xt_iclass_l8i, 33150 0, 33151 Opcode_l8ui_encode_fns, 0, 0 }, 33152 { "loop", ICLASS_xt_iclass_loop, 33153 XTENSA_OPCODE_IS_LOOP, 33154 Opcode_loop_encode_fns, 0, 0 }, 33155 { "loopnez", ICLASS_xt_iclass_loopz, 33156 XTENSA_OPCODE_IS_LOOP, 33157 Opcode_loopnez_encode_fns, 0, 0 }, 33158 { "loopgtz", ICLASS_xt_iclass_loopz, 33159 XTENSA_OPCODE_IS_LOOP, 33160 Opcode_loopgtz_encode_fns, 0, 0 }, 33161 { "movi", ICLASS_xt_iclass_movi, 33162 0, 33163 Opcode_movi_encode_fns, 0, 0 }, 33164 { "moveqz", ICLASS_xt_iclass_movz, 33165 0, 33166 Opcode_moveqz_encode_fns, 0, 0 }, 33167 { "movnez", ICLASS_xt_iclass_movz, 33168 0, 33169 Opcode_movnez_encode_fns, 0, 0 }, 33170 { "movltz", ICLASS_xt_iclass_movz, 33171 0, 33172 Opcode_movltz_encode_fns, 0, 0 }, 33173 { "movgez", ICLASS_xt_iclass_movz, 33174 0, 33175 Opcode_movgez_encode_fns, 0, 0 }, 33176 { "neg", ICLASS_xt_iclass_neg, 33177 0, 33178 Opcode_neg_encode_fns, 0, 0 }, 33179 { "abs", ICLASS_xt_iclass_neg, 33180 0, 33181 Opcode_abs_encode_fns, 0, 0 }, 33182 { "nop", ICLASS_xt_iclass_nop, 33183 0, 33184 Opcode_nop_encode_fns, 0, 0 }, 33185 { "ret", ICLASS_xt_iclass_return, 33186 XTENSA_OPCODE_IS_JUMP, 33187 Opcode_ret_encode_fns, 0, 0 }, 33188 { "simcall", ICLASS_xt_iclass_simcall, 33189 0, 33190 Opcode_simcall_encode_fns, 0, 0 }, 33191 { "s16i", ICLASS_xt_iclass_s16i, 33192 0, 33193 Opcode_s16i_encode_fns, 0, 0 }, 33194 { "s32i", ICLASS_xt_iclass_s32i, 33195 0, 33196 Opcode_s32i_encode_fns, 0, 0 }, 33197 { "s32nb", ICLASS_xt_iclass_s32nb, 33198 0, 33199 Opcode_s32nb_encode_fns, 0, 0 }, 33200 { "s8i", ICLASS_xt_iclass_s8i, 33201 0, 33202 Opcode_s8i_encode_fns, 0, 0 }, 33203 { "ssr", ICLASS_xt_iclass_sar, 33204 0, 33205 Opcode_ssr_encode_fns, 0, 0 }, 33206 { "ssl", ICLASS_xt_iclass_sar, 33207 0, 33208 Opcode_ssl_encode_fns, 0, 0 }, 33209 { "ssa8l", ICLASS_xt_iclass_sar, 33210 0, 33211 Opcode_ssa8l_encode_fns, 0, 0 }, 33212 { "ssa8b", ICLASS_xt_iclass_sar, 33213 0, 33214 Opcode_ssa8b_encode_fns, 0, 0 }, 33215 { "ssai", ICLASS_xt_iclass_sari, 33216 0, 33217 Opcode_ssai_encode_fns, 0, 0 }, 33218 { "sll", ICLASS_xt_iclass_shifts, 33219 0, 33220 Opcode_sll_encode_fns, 0, 0 }, 33221 { "src", ICLASS_xt_iclass_shiftst, 33222 0, 33223 Opcode_src_encode_fns, 0, 0 }, 33224 { "srl", ICLASS_xt_iclass_shiftt, 33225 0, 33226 Opcode_srl_encode_fns, 0, 0 }, 33227 { "sra", ICLASS_xt_iclass_shiftt, 33228 0, 33229 Opcode_sra_encode_fns, 0, 0 }, 33230 { "slli", ICLASS_xt_iclass_slli, 33231 0, 33232 Opcode_slli_encode_fns, 0, 0 }, 33233 { "srai", ICLASS_xt_iclass_srai, 33234 0, 33235 Opcode_srai_encode_fns, 0, 0 }, 33236 { "srli", ICLASS_xt_iclass_srli, 33237 0, 33238 Opcode_srli_encode_fns, 0, 0 }, 33239 { "memw", ICLASS_xt_iclass_memw, 33240 0, 33241 Opcode_memw_encode_fns, 0, 0 }, 33242 { "extw", ICLASS_xt_iclass_extw, 33243 0, 33244 Opcode_extw_encode_fns, 0, 0 }, 33245 { "isync", ICLASS_xt_iclass_isync, 33246 0, 33247 Opcode_isync_encode_fns, 0, 0 }, 33248 { "rsync", ICLASS_xt_iclass_sync, 33249 0, 33250 Opcode_rsync_encode_fns, 0, 0 }, 33251 { "esync", ICLASS_xt_iclass_sync, 33252 0, 33253 Opcode_esync_encode_fns, 0, 0 }, 33254 { "dsync", ICLASS_xt_iclass_sync, 33255 0, 33256 Opcode_dsync_encode_fns, 0, 0 }, 33257 { "rsil", ICLASS_xt_iclass_rsil, 33258 0, 33259 Opcode_rsil_encode_fns, 0, 0 }, 33260 { "rsr.lend", ICLASS_xt_iclass_rsr_lend, 33261 0, 33262 Opcode_rsr_lend_encode_fns, 0, 0 }, 33263 { "wsr.lend", ICLASS_xt_iclass_wsr_lend, 33264 0, 33265 Opcode_wsr_lend_encode_fns, 0, 0 }, 33266 { "xsr.lend", ICLASS_xt_iclass_xsr_lend, 33267 0, 33268 Opcode_xsr_lend_encode_fns, 0, 0 }, 33269 { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount, 33270 0, 33271 Opcode_rsr_lcount_encode_fns, 0, 0 }, 33272 { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount, 33273 0, 33274 Opcode_wsr_lcount_encode_fns, 0, 0 }, 33275 { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount, 33276 0, 33277 Opcode_xsr_lcount_encode_fns, 0, 0 }, 33278 { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg, 33279 0, 33280 Opcode_rsr_lbeg_encode_fns, 0, 0 }, 33281 { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg, 33282 0, 33283 Opcode_wsr_lbeg_encode_fns, 0, 0 }, 33284 { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg, 33285 0, 33286 Opcode_xsr_lbeg_encode_fns, 0, 0 }, 33287 { "rsr.sar", ICLASS_xt_iclass_rsr_sar, 33288 0, 33289 Opcode_rsr_sar_encode_fns, 0, 0 }, 33290 { "wsr.sar", ICLASS_xt_iclass_wsr_sar, 33291 0, 33292 Opcode_wsr_sar_encode_fns, 0, 0 }, 33293 { "xsr.sar", ICLASS_xt_iclass_xsr_sar, 33294 0, 33295 Opcode_xsr_sar_encode_fns, 0, 0 }, 33296 { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl, 33297 0, 33298 Opcode_rsr_memctl_encode_fns, 0, 0 }, 33299 { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl, 33300 0, 33301 Opcode_wsr_memctl_encode_fns, 0, 0 }, 33302 { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl, 33303 0, 33304 Opcode_xsr_memctl_encode_fns, 0, 0 }, 33305 { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase, 33306 0, 33307 Opcode_rsr_litbase_encode_fns, 0, 0 }, 33308 { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase, 33309 0, 33310 Opcode_wsr_litbase_encode_fns, 0, 0 }, 33311 { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase, 33312 0, 33313 Opcode_xsr_litbase_encode_fns, 0, 0 }, 33314 { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0, 33315 0, 33316 Opcode_rsr_configid0_encode_fns, 0, 0 }, 33317 { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0, 33318 0, 33319 Opcode_wsr_configid0_encode_fns, 0, 0 }, 33320 { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1, 33321 0, 33322 Opcode_rsr_configid1_encode_fns, 0, 0 }, 33323 { "rsr.243", ICLASS_xt_iclass_rsr_243, 33324 0, 33325 Opcode_rsr_243_encode_fns, 0, 0 }, 33326 { "rsr.ps", ICLASS_xt_iclass_rsr_ps, 33327 0, 33328 Opcode_rsr_ps_encode_fns, 0, 0 }, 33329 { "wsr.ps", ICLASS_xt_iclass_wsr_ps, 33330 0, 33331 Opcode_wsr_ps_encode_fns, 0, 0 }, 33332 { "xsr.ps", ICLASS_xt_iclass_xsr_ps, 33333 0, 33334 Opcode_xsr_ps_encode_fns, 0, 0 }, 33335 { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1, 33336 0, 33337 Opcode_rsr_epc1_encode_fns, 0, 0 }, 33338 { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1, 33339 0, 33340 Opcode_wsr_epc1_encode_fns, 0, 0 }, 33341 { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1, 33342 0, 33343 Opcode_xsr_epc1_encode_fns, 0, 0 }, 33344 { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1, 33345 0, 33346 Opcode_rsr_excsave1_encode_fns, 0, 0 }, 33347 { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1, 33348 0, 33349 Opcode_wsr_excsave1_encode_fns, 0, 0 }, 33350 { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1, 33351 0, 33352 Opcode_xsr_excsave1_encode_fns, 0, 0 }, 33353 { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2, 33354 0, 33355 Opcode_rsr_epc2_encode_fns, 0, 0 }, 33356 { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2, 33357 0, 33358 Opcode_wsr_epc2_encode_fns, 0, 0 }, 33359 { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2, 33360 0, 33361 Opcode_xsr_epc2_encode_fns, 0, 0 }, 33362 { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2, 33363 0, 33364 Opcode_rsr_excsave2_encode_fns, 0, 0 }, 33365 { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2, 33366 0, 33367 Opcode_wsr_excsave2_encode_fns, 0, 0 }, 33368 { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2, 33369 0, 33370 Opcode_xsr_excsave2_encode_fns, 0, 0 }, 33371 { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3, 33372 0, 33373 Opcode_rsr_epc3_encode_fns, 0, 0 }, 33374 { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3, 33375 0, 33376 Opcode_wsr_epc3_encode_fns, 0, 0 }, 33377 { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3, 33378 0, 33379 Opcode_xsr_epc3_encode_fns, 0, 0 }, 33380 { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3, 33381 0, 33382 Opcode_rsr_excsave3_encode_fns, 0, 0 }, 33383 { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3, 33384 0, 33385 Opcode_wsr_excsave3_encode_fns, 0, 0 }, 33386 { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3, 33387 0, 33388 Opcode_xsr_excsave3_encode_fns, 0, 0 }, 33389 { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4, 33390 0, 33391 Opcode_rsr_epc4_encode_fns, 0, 0 }, 33392 { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4, 33393 0, 33394 Opcode_wsr_epc4_encode_fns, 0, 0 }, 33395 { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4, 33396 0, 33397 Opcode_xsr_epc4_encode_fns, 0, 0 }, 33398 { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4, 33399 0, 33400 Opcode_rsr_excsave4_encode_fns, 0, 0 }, 33401 { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4, 33402 0, 33403 Opcode_wsr_excsave4_encode_fns, 0, 0 }, 33404 { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4, 33405 0, 33406 Opcode_xsr_excsave4_encode_fns, 0, 0 }, 33407 { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5, 33408 0, 33409 Opcode_rsr_epc5_encode_fns, 0, 0 }, 33410 { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5, 33411 0, 33412 Opcode_wsr_epc5_encode_fns, 0, 0 }, 33413 { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5, 33414 0, 33415 Opcode_xsr_epc5_encode_fns, 0, 0 }, 33416 { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5, 33417 0, 33418 Opcode_rsr_excsave5_encode_fns, 0, 0 }, 33419 { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5, 33420 0, 33421 Opcode_wsr_excsave5_encode_fns, 0, 0 }, 33422 { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5, 33423 0, 33424 Opcode_xsr_excsave5_encode_fns, 0, 0 }, 33425 { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6, 33426 0, 33427 Opcode_rsr_epc6_encode_fns, 0, 0 }, 33428 { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6, 33429 0, 33430 Opcode_wsr_epc6_encode_fns, 0, 0 }, 33431 { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6, 33432 0, 33433 Opcode_xsr_epc6_encode_fns, 0, 0 }, 33434 { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6, 33435 0, 33436 Opcode_rsr_excsave6_encode_fns, 0, 0 }, 33437 { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6, 33438 0, 33439 Opcode_wsr_excsave6_encode_fns, 0, 0 }, 33440 { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6, 33441 0, 33442 Opcode_xsr_excsave6_encode_fns, 0, 0 }, 33443 { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7, 33444 0, 33445 Opcode_rsr_epc7_encode_fns, 0, 0 }, 33446 { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7, 33447 0, 33448 Opcode_wsr_epc7_encode_fns, 0, 0 }, 33449 { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7, 33450 0, 33451 Opcode_xsr_epc7_encode_fns, 0, 0 }, 33452 { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7, 33453 0, 33454 Opcode_rsr_excsave7_encode_fns, 0, 0 }, 33455 { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7, 33456 0, 33457 Opcode_wsr_excsave7_encode_fns, 0, 0 }, 33458 { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7, 33459 0, 33460 Opcode_xsr_excsave7_encode_fns, 0, 0 }, 33461 { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2, 33462 0, 33463 Opcode_rsr_eps2_encode_fns, 0, 0 }, 33464 { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2, 33465 0, 33466 Opcode_wsr_eps2_encode_fns, 0, 0 }, 33467 { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2, 33468 0, 33469 Opcode_xsr_eps2_encode_fns, 0, 0 }, 33470 { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3, 33471 0, 33472 Opcode_rsr_eps3_encode_fns, 0, 0 }, 33473 { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3, 33474 0, 33475 Opcode_wsr_eps3_encode_fns, 0, 0 }, 33476 { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3, 33477 0, 33478 Opcode_xsr_eps3_encode_fns, 0, 0 }, 33479 { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4, 33480 0, 33481 Opcode_rsr_eps4_encode_fns, 0, 0 }, 33482 { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4, 33483 0, 33484 Opcode_wsr_eps4_encode_fns, 0, 0 }, 33485 { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4, 33486 0, 33487 Opcode_xsr_eps4_encode_fns, 0, 0 }, 33488 { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5, 33489 0, 33490 Opcode_rsr_eps5_encode_fns, 0, 0 }, 33491 { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5, 33492 0, 33493 Opcode_wsr_eps5_encode_fns, 0, 0 }, 33494 { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5, 33495 0, 33496 Opcode_xsr_eps5_encode_fns, 0, 0 }, 33497 { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6, 33498 0, 33499 Opcode_rsr_eps6_encode_fns, 0, 0 }, 33500 { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6, 33501 0, 33502 Opcode_wsr_eps6_encode_fns, 0, 0 }, 33503 { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6, 33504 0, 33505 Opcode_xsr_eps6_encode_fns, 0, 0 }, 33506 { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7, 33507 0, 33508 Opcode_rsr_eps7_encode_fns, 0, 0 }, 33509 { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7, 33510 0, 33511 Opcode_wsr_eps7_encode_fns, 0, 0 }, 33512 { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7, 33513 0, 33514 Opcode_xsr_eps7_encode_fns, 0, 0 }, 33515 { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr, 33516 0, 33517 Opcode_rsr_excvaddr_encode_fns, 0, 0 }, 33518 { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr, 33519 0, 33520 Opcode_wsr_excvaddr_encode_fns, 0, 0 }, 33521 { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr, 33522 0, 33523 Opcode_xsr_excvaddr_encode_fns, 0, 0 }, 33524 { "rsr.depc", ICLASS_xt_iclass_rsr_depc, 33525 0, 33526 Opcode_rsr_depc_encode_fns, 0, 0 }, 33527 { "wsr.depc", ICLASS_xt_iclass_wsr_depc, 33528 0, 33529 Opcode_wsr_depc_encode_fns, 0, 0 }, 33530 { "xsr.depc", ICLASS_xt_iclass_xsr_depc, 33531 0, 33532 Opcode_xsr_depc_encode_fns, 0, 0 }, 33533 { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause, 33534 0, 33535 Opcode_rsr_exccause_encode_fns, 0, 0 }, 33536 { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause, 33537 0, 33538 Opcode_wsr_exccause_encode_fns, 0, 0 }, 33539 { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause, 33540 0, 33541 Opcode_xsr_exccause_encode_fns, 0, 0 }, 33542 { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0, 33543 0, 33544 Opcode_rsr_misc0_encode_fns, 0, 0 }, 33545 { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0, 33546 0, 33547 Opcode_wsr_misc0_encode_fns, 0, 0 }, 33548 { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0, 33549 0, 33550 Opcode_xsr_misc0_encode_fns, 0, 0 }, 33551 { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1, 33552 0, 33553 Opcode_rsr_misc1_encode_fns, 0, 0 }, 33554 { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1, 33555 0, 33556 Opcode_wsr_misc1_encode_fns, 0, 0 }, 33557 { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1, 33558 0, 33559 Opcode_xsr_misc1_encode_fns, 0, 0 }, 33560 { "rsr.prid", ICLASS_xt_iclass_rsr_prid, 33561 0, 33562 Opcode_rsr_prid_encode_fns, 0, 0 }, 33563 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase, 33564 0, 33565 Opcode_rsr_vecbase_encode_fns, 0, 0 }, 33566 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase, 33567 0, 33568 Opcode_wsr_vecbase_encode_fns, 0, 0 }, 33569 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase, 33570 0, 33571 Opcode_xsr_vecbase_encode_fns, 0, 0 }, 33572 { "mul16u", ICLASS_xt_mul16, 33573 0, 33574 Opcode_mul16u_encode_fns, 0, 0 }, 33575 { "mul16s", ICLASS_xt_mul16, 33576 0, 33577 Opcode_mul16s_encode_fns, 0, 0 }, 33578 { "mull", ICLASS_xt_mul32, 33579 0, 33580 Opcode_mull_encode_fns, 0, 0 }, 33581 { "muluh", ICLASS_xt_mul32h, 33582 0, 33583 Opcode_muluh_encode_fns, 0, 0 }, 33584 { "mulsh", ICLASS_xt_mul32h, 33585 0, 33586 Opcode_mulsh_encode_fns, 0, 0 }, 33587 { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa, 33588 0, 33589 Opcode_mul_aa_ll_encode_fns, 0, 0 }, 33590 { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa, 33591 0, 33592 Opcode_mul_aa_hl_encode_fns, 0, 0 }, 33593 { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa, 33594 0, 33595 Opcode_mul_aa_lh_encode_fns, 0, 0 }, 33596 { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa, 33597 0, 33598 Opcode_mul_aa_hh_encode_fns, 0, 0 }, 33599 { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa, 33600 0, 33601 Opcode_umul_aa_ll_encode_fns, 0, 0 }, 33602 { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa, 33603 0, 33604 Opcode_umul_aa_hl_encode_fns, 0, 0 }, 33605 { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa, 33606 0, 33607 Opcode_umul_aa_lh_encode_fns, 0, 0 }, 33608 { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa, 33609 0, 33610 Opcode_umul_aa_hh_encode_fns, 0, 0 }, 33611 { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad, 33612 0, 33613 Opcode_mul_ad_ll_encode_fns, 0, 0 }, 33614 { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad, 33615 0, 33616 Opcode_mul_ad_hl_encode_fns, 0, 0 }, 33617 { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad, 33618 0, 33619 Opcode_mul_ad_lh_encode_fns, 0, 0 }, 33620 { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad, 33621 0, 33622 Opcode_mul_ad_hh_encode_fns, 0, 0 }, 33623 { "mul.da.ll", ICLASS_xt_iclass_mac16_da, 33624 0, 33625 Opcode_mul_da_ll_encode_fns, 0, 0 }, 33626 { "mul.da.hl", ICLASS_xt_iclass_mac16_da, 33627 0, 33628 Opcode_mul_da_hl_encode_fns, 0, 0 }, 33629 { "mul.da.lh", ICLASS_xt_iclass_mac16_da, 33630 0, 33631 Opcode_mul_da_lh_encode_fns, 0, 0 }, 33632 { "mul.da.hh", ICLASS_xt_iclass_mac16_da, 33633 0, 33634 Opcode_mul_da_hh_encode_fns, 0, 0 }, 33635 { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd, 33636 0, 33637 Opcode_mul_dd_ll_encode_fns, 0, 0 }, 33638 { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd, 33639 0, 33640 Opcode_mul_dd_hl_encode_fns, 0, 0 }, 33641 { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd, 33642 0, 33643 Opcode_mul_dd_lh_encode_fns, 0, 0 }, 33644 { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd, 33645 0, 33646 Opcode_mul_dd_hh_encode_fns, 0, 0 }, 33647 { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa, 33648 0, 33649 Opcode_mula_aa_ll_encode_fns, 0, 0 }, 33650 { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa, 33651 0, 33652 Opcode_mula_aa_hl_encode_fns, 0, 0 }, 33653 { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa, 33654 0, 33655 Opcode_mula_aa_lh_encode_fns, 0, 0 }, 33656 { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa, 33657 0, 33658 Opcode_mula_aa_hh_encode_fns, 0, 0 }, 33659 { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa, 33660 0, 33661 Opcode_muls_aa_ll_encode_fns, 0, 0 }, 33662 { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa, 33663 0, 33664 Opcode_muls_aa_hl_encode_fns, 0, 0 }, 33665 { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa, 33666 0, 33667 Opcode_muls_aa_lh_encode_fns, 0, 0 }, 33668 { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa, 33669 0, 33670 Opcode_muls_aa_hh_encode_fns, 0, 0 }, 33671 { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad, 33672 0, 33673 Opcode_mula_ad_ll_encode_fns, 0, 0 }, 33674 { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad, 33675 0, 33676 Opcode_mula_ad_hl_encode_fns, 0, 0 }, 33677 { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad, 33678 0, 33679 Opcode_mula_ad_lh_encode_fns, 0, 0 }, 33680 { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad, 33681 0, 33682 Opcode_mula_ad_hh_encode_fns, 0, 0 }, 33683 { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad, 33684 0, 33685 Opcode_muls_ad_ll_encode_fns, 0, 0 }, 33686 { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad, 33687 0, 33688 Opcode_muls_ad_hl_encode_fns, 0, 0 }, 33689 { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad, 33690 0, 33691 Opcode_muls_ad_lh_encode_fns, 0, 0 }, 33692 { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad, 33693 0, 33694 Opcode_muls_ad_hh_encode_fns, 0, 0 }, 33695 { "mula.da.ll", ICLASS_xt_iclass_mac16a_da, 33696 0, 33697 Opcode_mula_da_ll_encode_fns, 0, 0 }, 33698 { "mula.da.hl", ICLASS_xt_iclass_mac16a_da, 33699 0, 33700 Opcode_mula_da_hl_encode_fns, 0, 0 }, 33701 { "mula.da.lh", ICLASS_xt_iclass_mac16a_da, 33702 0, 33703 Opcode_mula_da_lh_encode_fns, 0, 0 }, 33704 { "mula.da.hh", ICLASS_xt_iclass_mac16a_da, 33705 0, 33706 Opcode_mula_da_hh_encode_fns, 0, 0 }, 33707 { "muls.da.ll", ICLASS_xt_iclass_mac16a_da, 33708 0, 33709 Opcode_muls_da_ll_encode_fns, 0, 0 }, 33710 { "muls.da.hl", ICLASS_xt_iclass_mac16a_da, 33711 0, 33712 Opcode_muls_da_hl_encode_fns, 0, 0 }, 33713 { "muls.da.lh", ICLASS_xt_iclass_mac16a_da, 33714 0, 33715 Opcode_muls_da_lh_encode_fns, 0, 0 }, 33716 { "muls.da.hh", ICLASS_xt_iclass_mac16a_da, 33717 0, 33718 Opcode_muls_da_hh_encode_fns, 0, 0 }, 33719 { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd, 33720 0, 33721 Opcode_mula_dd_ll_encode_fns, 0, 0 }, 33722 { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd, 33723 0, 33724 Opcode_mula_dd_hl_encode_fns, 0, 0 }, 33725 { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd, 33726 0, 33727 Opcode_mula_dd_lh_encode_fns, 0, 0 }, 33728 { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd, 33729 0, 33730 Opcode_mula_dd_hh_encode_fns, 0, 0 }, 33731 { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd, 33732 0, 33733 Opcode_muls_dd_ll_encode_fns, 0, 0 }, 33734 { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd, 33735 0, 33736 Opcode_muls_dd_hl_encode_fns, 0, 0 }, 33737 { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd, 33738 0, 33739 Opcode_muls_dd_lh_encode_fns, 0, 0 }, 33740 { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd, 33741 0, 33742 Opcode_muls_dd_hh_encode_fns, 0, 0 }, 33743 { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da, 33744 0, 33745 Opcode_mula_da_ll_lddec_encode_fns, 0, 0 }, 33746 { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da, 33747 0, 33748 Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 }, 33749 { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da, 33750 0, 33751 Opcode_mula_da_hl_lddec_encode_fns, 0, 0 }, 33752 { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da, 33753 0, 33754 Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 }, 33755 { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da, 33756 0, 33757 Opcode_mula_da_lh_lddec_encode_fns, 0, 0 }, 33758 { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da, 33759 0, 33760 Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 }, 33761 { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da, 33762 0, 33763 Opcode_mula_da_hh_lddec_encode_fns, 0, 0 }, 33764 { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da, 33765 0, 33766 Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 }, 33767 { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd, 33768 0, 33769 Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 }, 33770 { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd, 33771 0, 33772 Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 }, 33773 { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd, 33774 0, 33775 Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 }, 33776 { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd, 33777 0, 33778 Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 }, 33779 { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd, 33780 0, 33781 Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 }, 33782 { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd, 33783 0, 33784 Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 }, 33785 { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd, 33786 0, 33787 Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 }, 33788 { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd, 33789 0, 33790 Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 }, 33791 { "lddec", ICLASS_xt_iclass_mac16_l, 33792 0, 33793 Opcode_lddec_encode_fns, 0, 0 }, 33794 { "ldinc", ICLASS_xt_iclass_mac16_l, 33795 0, 33796 Opcode_ldinc_encode_fns, 0, 0 }, 33797 { "rsr.m0", ICLASS_xt_iclass_rsr_m0, 33798 0, 33799 Opcode_rsr_m0_encode_fns, 0, 0 }, 33800 { "wsr.m0", ICLASS_xt_iclass_wsr_m0, 33801 0, 33802 Opcode_wsr_m0_encode_fns, 0, 0 }, 33803 { "xsr.m0", ICLASS_xt_iclass_xsr_m0, 33804 0, 33805 Opcode_xsr_m0_encode_fns, 0, 0 }, 33806 { "rsr.m1", ICLASS_xt_iclass_rsr_m1, 33807 0, 33808 Opcode_rsr_m1_encode_fns, 0, 0 }, 33809 { "wsr.m1", ICLASS_xt_iclass_wsr_m1, 33810 0, 33811 Opcode_wsr_m1_encode_fns, 0, 0 }, 33812 { "xsr.m1", ICLASS_xt_iclass_xsr_m1, 33813 0, 33814 Opcode_xsr_m1_encode_fns, 0, 0 }, 33815 { "rsr.m2", ICLASS_xt_iclass_rsr_m2, 33816 0, 33817 Opcode_rsr_m2_encode_fns, 0, 0 }, 33818 { "wsr.m2", ICLASS_xt_iclass_wsr_m2, 33819 0, 33820 Opcode_wsr_m2_encode_fns, 0, 0 }, 33821 { "xsr.m2", ICLASS_xt_iclass_xsr_m2, 33822 0, 33823 Opcode_xsr_m2_encode_fns, 0, 0 }, 33824 { "rsr.m3", ICLASS_xt_iclass_rsr_m3, 33825 0, 33826 Opcode_rsr_m3_encode_fns, 0, 0 }, 33827 { "wsr.m3", ICLASS_xt_iclass_wsr_m3, 33828 0, 33829 Opcode_wsr_m3_encode_fns, 0, 0 }, 33830 { "xsr.m3", ICLASS_xt_iclass_xsr_m3, 33831 0, 33832 Opcode_xsr_m3_encode_fns, 0, 0 }, 33833 { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo, 33834 0, 33835 Opcode_rsr_acclo_encode_fns, 0, 0 }, 33836 { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo, 33837 0, 33838 Opcode_wsr_acclo_encode_fns, 0, 0 }, 33839 { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo, 33840 0, 33841 Opcode_xsr_acclo_encode_fns, 0, 0 }, 33842 { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi, 33843 0, 33844 Opcode_rsr_acchi_encode_fns, 0, 0 }, 33845 { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi, 33846 0, 33847 Opcode_wsr_acchi_encode_fns, 0, 0 }, 33848 { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi, 33849 0, 33850 Opcode_xsr_acchi_encode_fns, 0, 0 }, 33851 { "rfi", ICLASS_xt_iclass_rfi, 33852 XTENSA_OPCODE_IS_JUMP, 33853 Opcode_rfi_encode_fns, 0, 0 }, 33854 { "waiti", ICLASS_xt_iclass_wait, 33855 0, 33856 Opcode_waiti_encode_fns, 0, 0 }, 33857 { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt, 33858 0, 33859 Opcode_rsr_interrupt_encode_fns, 0, 0 }, 33860 { "wsr.intset", ICLASS_xt_iclass_wsr_intset, 33861 0, 33862 Opcode_wsr_intset_encode_fns, 0, 0 }, 33863 { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear, 33864 0, 33865 Opcode_wsr_intclear_encode_fns, 0, 0 }, 33866 { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable, 33867 0, 33868 Opcode_rsr_intenable_encode_fns, 0, 0 }, 33869 { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable, 33870 0, 33871 Opcode_wsr_intenable_encode_fns, 0, 0 }, 33872 { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable, 33873 0, 33874 Opcode_xsr_intenable_encode_fns, 0, 0 }, 33875 { "break", ICLASS_xt_iclass_break, 33876 0, 33877 Opcode_break_encode_fns, 0, 0 }, 33878 { "break.n", ICLASS_xt_iclass_break_n, 33879 0, 33880 Opcode_break_n_encode_fns, 0, 0 }, 33881 { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0, 33882 0, 33883 Opcode_rsr_dbreaka0_encode_fns, 0, 0 }, 33884 { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0, 33885 0, 33886 Opcode_wsr_dbreaka0_encode_fns, 0, 0 }, 33887 { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0, 33888 0, 33889 Opcode_xsr_dbreaka0_encode_fns, 0, 0 }, 33890 { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0, 33891 0, 33892 Opcode_rsr_dbreakc0_encode_fns, 0, 0 }, 33893 { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0, 33894 0, 33895 Opcode_wsr_dbreakc0_encode_fns, 0, 0 }, 33896 { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0, 33897 0, 33898 Opcode_xsr_dbreakc0_encode_fns, 0, 0 }, 33899 { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1, 33900 0, 33901 Opcode_rsr_dbreaka1_encode_fns, 0, 0 }, 33902 { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1, 33903 0, 33904 Opcode_wsr_dbreaka1_encode_fns, 0, 0 }, 33905 { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1, 33906 0, 33907 Opcode_xsr_dbreaka1_encode_fns, 0, 0 }, 33908 { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1, 33909 0, 33910 Opcode_rsr_dbreakc1_encode_fns, 0, 0 }, 33911 { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1, 33912 0, 33913 Opcode_wsr_dbreakc1_encode_fns, 0, 0 }, 33914 { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1, 33915 0, 33916 Opcode_xsr_dbreakc1_encode_fns, 0, 0 }, 33917 { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0, 33918 0, 33919 Opcode_rsr_ibreaka0_encode_fns, 0, 0 }, 33920 { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0, 33921 0, 33922 Opcode_wsr_ibreaka0_encode_fns, 0, 0 }, 33923 { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0, 33924 0, 33925 Opcode_xsr_ibreaka0_encode_fns, 0, 0 }, 33926 { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1, 33927 0, 33928 Opcode_rsr_ibreaka1_encode_fns, 0, 0 }, 33929 { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1, 33930 0, 33931 Opcode_wsr_ibreaka1_encode_fns, 0, 0 }, 33932 { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1, 33933 0, 33934 Opcode_xsr_ibreaka1_encode_fns, 0, 0 }, 33935 { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable, 33936 0, 33937 Opcode_rsr_ibreakenable_encode_fns, 0, 0 }, 33938 { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable, 33939 0, 33940 Opcode_wsr_ibreakenable_encode_fns, 0, 0 }, 33941 { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable, 33942 0, 33943 Opcode_xsr_ibreakenable_encode_fns, 0, 0 }, 33944 { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause, 33945 0, 33946 Opcode_rsr_debugcause_encode_fns, 0, 0 }, 33947 { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause, 33948 0, 33949 Opcode_wsr_debugcause_encode_fns, 0, 0 }, 33950 { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause, 33951 0, 33952 Opcode_xsr_debugcause_encode_fns, 0, 0 }, 33953 { "rsr.icount", ICLASS_xt_iclass_rsr_icount, 33954 0, 33955 Opcode_rsr_icount_encode_fns, 0, 0 }, 33956 { "wsr.icount", ICLASS_xt_iclass_wsr_icount, 33957 0, 33958 Opcode_wsr_icount_encode_fns, 0, 0 }, 33959 { "xsr.icount", ICLASS_xt_iclass_xsr_icount, 33960 0, 33961 Opcode_xsr_icount_encode_fns, 0, 0 }, 33962 { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel, 33963 0, 33964 Opcode_rsr_icountlevel_encode_fns, 0, 0 }, 33965 { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel, 33966 0, 33967 Opcode_wsr_icountlevel_encode_fns, 0, 0 }, 33968 { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel, 33969 0, 33970 Opcode_xsr_icountlevel_encode_fns, 0, 0 }, 33971 { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr, 33972 0, 33973 Opcode_rsr_ddr_encode_fns, 0, 0 }, 33974 { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr, 33975 0, 33976 Opcode_wsr_ddr_encode_fns, 0, 0 }, 33977 { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr, 33978 0, 33979 Opcode_xsr_ddr_encode_fns, 0, 0 }, 33980 { "lddr32.p", ICLASS_xt_iclass_lddr32_p, 33981 0, 33982 Opcode_lddr32_p_encode_fns, 0, 0 }, 33983 { "sddr32.p", ICLASS_xt_iclass_sddr32_p, 33984 0, 33985 Opcode_sddr32_p_encode_fns, 0, 0 }, 33986 { "rfdo", ICLASS_xt_iclass_rfdo, 33987 XTENSA_OPCODE_IS_JUMP, 33988 Opcode_rfdo_encode_fns, 0, 0 }, 33989 { "rfdd", ICLASS_xt_iclass_rfdd, 33990 XTENSA_OPCODE_IS_JUMP, 33991 Opcode_rfdd_encode_fns, 0, 0 }, 33992 { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid, 33993 0, 33994 Opcode_wsr_mmid_encode_fns, 0, 0 }, 33995 { "andb", ICLASS_xt_iclass_bbool1, 33996 0, 33997 Opcode_andb_encode_fns, 0, 0 }, 33998 { "andbc", ICLASS_xt_iclass_bbool1, 33999 0, 34000 Opcode_andbc_encode_fns, 0, 0 }, 34001 { "orb", ICLASS_xt_iclass_bbool1, 34002 0, 34003 Opcode_orb_encode_fns, 0, 0 }, 34004 { "orbc", ICLASS_xt_iclass_bbool1, 34005 0, 34006 Opcode_orbc_encode_fns, 0, 0 }, 34007 { "xorb", ICLASS_xt_iclass_bbool1, 34008 0, 34009 Opcode_xorb_encode_fns, 0, 0 }, 34010 { "any4", ICLASS_xt_iclass_bbool4, 34011 0, 34012 Opcode_any4_encode_fns, 0, 0 }, 34013 { "all4", ICLASS_xt_iclass_bbool4, 34014 0, 34015 Opcode_all4_encode_fns, 0, 0 }, 34016 { "any8", ICLASS_xt_iclass_bbool8, 34017 0, 34018 Opcode_any8_encode_fns, 0, 0 }, 34019 { "all8", ICLASS_xt_iclass_bbool8, 34020 0, 34021 Opcode_all8_encode_fns, 0, 0 }, 34022 { "bf", ICLASS_xt_iclass_bbranch, 34023 XTENSA_OPCODE_IS_BRANCH, 34024 Opcode_bf_encode_fns, 0, 0 }, 34025 { "bt", ICLASS_xt_iclass_bbranch, 34026 XTENSA_OPCODE_IS_BRANCH, 34027 Opcode_bt_encode_fns, 0, 0 }, 34028 { "movf", ICLASS_xt_iclass_bmove, 34029 0, 34030 Opcode_movf_encode_fns, 0, 0 }, 34031 { "movt", ICLASS_xt_iclass_bmove, 34032 0, 34033 Opcode_movt_encode_fns, 0, 0 }, 34034 { "rsr.br", ICLASS_xt_iclass_RSR_BR, 34035 0, 34036 Opcode_rsr_br_encode_fns, 0, 0 }, 34037 { "wsr.br", ICLASS_xt_iclass_WSR_BR, 34038 0, 34039 Opcode_wsr_br_encode_fns, 0, 0 }, 34040 { "xsr.br", ICLASS_xt_iclass_XSR_BR, 34041 0, 34042 Opcode_xsr_br_encode_fns, 0, 0 }, 34043 { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount, 34044 0, 34045 Opcode_rsr_ccount_encode_fns, 0, 0 }, 34046 { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount, 34047 0, 34048 Opcode_wsr_ccount_encode_fns, 0, 0 }, 34049 { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount, 34050 0, 34051 Opcode_xsr_ccount_encode_fns, 0, 0 }, 34052 { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0, 34053 0, 34054 Opcode_rsr_ccompare0_encode_fns, 0, 0 }, 34055 { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0, 34056 0, 34057 Opcode_wsr_ccompare0_encode_fns, 0, 0 }, 34058 { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0, 34059 0, 34060 Opcode_xsr_ccompare0_encode_fns, 0, 0 }, 34061 { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1, 34062 0, 34063 Opcode_rsr_ccompare1_encode_fns, 0, 0 }, 34064 { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1, 34065 0, 34066 Opcode_wsr_ccompare1_encode_fns, 0, 0 }, 34067 { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1, 34068 0, 34069 Opcode_xsr_ccompare1_encode_fns, 0, 0 }, 34070 { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2, 34071 0, 34072 Opcode_rsr_ccompare2_encode_fns, 0, 0 }, 34073 { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2, 34074 0, 34075 Opcode_wsr_ccompare2_encode_fns, 0, 0 }, 34076 { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2, 34077 0, 34078 Opcode_xsr_ccompare2_encode_fns, 0, 0 }, 34079 { "ipf", ICLASS_xt_iclass_icache, 34080 0, 34081 Opcode_ipf_encode_fns, 0, 0 }, 34082 { "ihi", ICLASS_xt_iclass_icache, 34083 0, 34084 Opcode_ihi_encode_fns, 0, 0 }, 34085 { "ipfl", ICLASS_xt_iclass_icache_lock, 34086 0, 34087 Opcode_ipfl_encode_fns, 0, 0 }, 34088 { "ihu", ICLASS_xt_iclass_icache_lock, 34089 0, 34090 Opcode_ihu_encode_fns, 0, 0 }, 34091 { "iiu", ICLASS_xt_iclass_icache_lock, 34092 0, 34093 Opcode_iiu_encode_fns, 0, 0 }, 34094 { "iii", ICLASS_xt_iclass_icache_inv, 34095 0, 34096 Opcode_iii_encode_fns, 0, 0 }, 34097 { "lict", ICLASS_xt_iclass_licx, 34098 0, 34099 Opcode_lict_encode_fns, 0, 0 }, 34100 { "licw", ICLASS_xt_iclass_licx, 34101 0, 34102 Opcode_licw_encode_fns, 0, 0 }, 34103 { "sict", ICLASS_xt_iclass_sicx, 34104 0, 34105 Opcode_sict_encode_fns, 0, 0 }, 34106 { "sicw", ICLASS_xt_iclass_sicx, 34107 0, 34108 Opcode_sicw_encode_fns, 0, 0 }, 34109 { "dhwb", ICLASS_xt_iclass_dcache, 34110 0, 34111 Opcode_dhwb_encode_fns, 0, 0 }, 34112 { "dhwbi", ICLASS_xt_iclass_dcache, 34113 0, 34114 Opcode_dhwbi_encode_fns, 0, 0 }, 34115 { "diwbui.p", ICLASS_xt_iclass_dcache_dyn, 34116 0, 34117 Opcode_diwbui_p_encode_fns, 0, 0 }, 34118 { "diwb", ICLASS_xt_iclass_dcache_ind, 34119 0, 34120 Opcode_diwb_encode_fns, 0, 0 }, 34121 { "diwbi", ICLASS_xt_iclass_dcache_ind, 34122 0, 34123 Opcode_diwbi_encode_fns, 0, 0 }, 34124 { "dhi", ICLASS_xt_iclass_dcache_inv, 34125 0, 34126 Opcode_dhi_encode_fns, 0, 0 }, 34127 { "dii", ICLASS_xt_iclass_dcache_inv, 34128 0, 34129 Opcode_dii_encode_fns, 0, 0 }, 34130 { "dpfr", ICLASS_xt_iclass_dpf, 34131 0, 34132 Opcode_dpfr_encode_fns, 0, 0 }, 34133 { "dpfw", ICLASS_xt_iclass_dpf, 34134 0, 34135 Opcode_dpfw_encode_fns, 0, 0 }, 34136 { "dpfro", ICLASS_xt_iclass_dpf, 34137 0, 34138 Opcode_dpfro_encode_fns, 0, 0 }, 34139 { "dpfwo", ICLASS_xt_iclass_dpf, 34140 0, 34141 Opcode_dpfwo_encode_fns, 0, 0 }, 34142 { "dpfl", ICLASS_xt_iclass_dcache_lock, 34143 0, 34144 Opcode_dpfl_encode_fns, 0, 0 }, 34145 { "dhu", ICLASS_xt_iclass_dcache_lock, 34146 0, 34147 Opcode_dhu_encode_fns, 0, 0 }, 34148 { "diu", ICLASS_xt_iclass_dcache_lock, 34149 0, 34150 Opcode_diu_encode_fns, 0, 0 }, 34151 { "sdct", ICLASS_xt_iclass_sdct, 34152 0, 34153 Opcode_sdct_encode_fns, 0, 0 }, 34154 { "ldct", ICLASS_xt_iclass_ldct, 34155 0, 34156 Opcode_ldct_encode_fns, 0, 0 }, 34157 { "rsr.prefctl", ICLASS_xt_iclass_rsr_prefctl, 34158 0, 34159 Opcode_rsr_prefctl_encode_fns, 0, 0 }, 34160 { "wsr.prefctl", ICLASS_xt_iclass_wsr_prefctl, 34161 0, 34162 Opcode_wsr_prefctl_encode_fns, 0, 0 }, 34163 { "xsr.prefctl", ICLASS_xt_iclass_xsr_prefctl, 34164 0, 34165 Opcode_xsr_prefctl_encode_fns, 0, 0 }, 34166 { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr, 34167 0, 34168 Opcode_wsr_ptevaddr_encode_fns, 0, 0 }, 34169 { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr, 34170 0, 34171 Opcode_rsr_ptevaddr_encode_fns, 0, 0 }, 34172 { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr, 34173 0, 34174 Opcode_xsr_ptevaddr_encode_fns, 0, 0 }, 34175 { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid, 34176 0, 34177 Opcode_rsr_rasid_encode_fns, 0, 0 }, 34178 { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid, 34179 0, 34180 Opcode_wsr_rasid_encode_fns, 0, 0 }, 34181 { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid, 34182 0, 34183 Opcode_xsr_rasid_encode_fns, 0, 0 }, 34184 { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg, 34185 0, 34186 Opcode_rsr_itlbcfg_encode_fns, 0, 0 }, 34187 { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg, 34188 0, 34189 Opcode_wsr_itlbcfg_encode_fns, 0, 0 }, 34190 { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg, 34191 0, 34192 Opcode_xsr_itlbcfg_encode_fns, 0, 0 }, 34193 { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg, 34194 0, 34195 Opcode_rsr_dtlbcfg_encode_fns, 0, 0 }, 34196 { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg, 34197 0, 34198 Opcode_wsr_dtlbcfg_encode_fns, 0, 0 }, 34199 { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg, 34200 0, 34201 Opcode_xsr_dtlbcfg_encode_fns, 0, 0 }, 34202 { "idtlb", ICLASS_xt_iclass_idtlb, 34203 0, 34204 Opcode_idtlb_encode_fns, 0, 0 }, 34205 { "pdtlb", ICLASS_xt_iclass_rdtlb, 34206 0, 34207 Opcode_pdtlb_encode_fns, 0, 0 }, 34208 { "rdtlb0", ICLASS_xt_iclass_rdtlb, 34209 0, 34210 Opcode_rdtlb0_encode_fns, 0, 0 }, 34211 { "rdtlb1", ICLASS_xt_iclass_rdtlb, 34212 0, 34213 Opcode_rdtlb1_encode_fns, 0, 0 }, 34214 { "wdtlb", ICLASS_xt_iclass_wdtlb, 34215 0, 34216 Opcode_wdtlb_encode_fns, 0, 0 }, 34217 { "iitlb", ICLASS_xt_iclass_iitlb, 34218 0, 34219 Opcode_iitlb_encode_fns, 0, 0 }, 34220 { "pitlb", ICLASS_xt_iclass_ritlb, 34221 0, 34222 Opcode_pitlb_encode_fns, 0, 0 }, 34223 { "ritlb0", ICLASS_xt_iclass_ritlb, 34224 0, 34225 Opcode_ritlb0_encode_fns, 0, 0 }, 34226 { "ritlb1", ICLASS_xt_iclass_ritlb, 34227 0, 34228 Opcode_ritlb1_encode_fns, 0, 0 }, 34229 { "witlb", ICLASS_xt_iclass_witlb, 34230 0, 34231 Opcode_witlb_encode_fns, 0, 0 }, 34232 { "ldpte", ICLASS_xt_iclass_ldpte, 34233 0, 34234 Opcode_ldpte_encode_fns, 0, 0 }, 34235 { "hwwitlba", ICLASS_xt_iclass_hwwitlba, 34236 XTENSA_OPCODE_IS_BRANCH, 34237 Opcode_hwwitlba_encode_fns, 0, 0 }, 34238 { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba, 34239 0, 34240 Opcode_hwwdtlba_encode_fns, 0, 0 }, 34241 { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable, 34242 0, 34243 Opcode_rsr_cpenable_encode_fns, 0, 0 }, 34244 { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable, 34245 0, 34246 Opcode_wsr_cpenable_encode_fns, 0, 0 }, 34247 { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable, 34248 0, 34249 Opcode_xsr_cpenable_encode_fns, 0, 0 }, 34250 { "clamps", ICLASS_xt_iclass_clamp, 34251 0, 34252 Opcode_clamps_encode_fns, 0, 0 }, 34253 { "min", ICLASS_xt_iclass_minmax, 34254 0, 34255 Opcode_min_encode_fns, 0, 0 }, 34256 { "max", ICLASS_xt_iclass_minmax, 34257 0, 34258 Opcode_max_encode_fns, 0, 0 }, 34259 { "minu", ICLASS_xt_iclass_minmax, 34260 0, 34261 Opcode_minu_encode_fns, 0, 0 }, 34262 { "maxu", ICLASS_xt_iclass_minmax, 34263 0, 34264 Opcode_maxu_encode_fns, 0, 0 }, 34265 { "nsa", ICLASS_xt_iclass_nsa, 34266 0, 34267 Opcode_nsa_encode_fns, 0, 0 }, 34268 { "nsau", ICLASS_xt_iclass_nsa, 34269 0, 34270 Opcode_nsau_encode_fns, 0, 0 }, 34271 { "sext", ICLASS_xt_iclass_sx, 34272 0, 34273 Opcode_sext_encode_fns, 0, 0 }, 34274 { "l32ai", ICLASS_xt_iclass_l32ai, 34275 0, 34276 Opcode_l32ai_encode_fns, 0, 0 }, 34277 { "s32ri", ICLASS_xt_iclass_s32ri, 34278 0, 34279 Opcode_s32ri_encode_fns, 0, 0 }, 34280 { "s32c1i", ICLASS_xt_iclass_s32c1i, 34281 0, 34282 Opcode_s32c1i_encode_fns, 0, 0 }, 34283 { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1, 34284 0, 34285 Opcode_rsr_scompare1_encode_fns, 0, 0 }, 34286 { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1, 34287 0, 34288 Opcode_wsr_scompare1_encode_fns, 0, 0 }, 34289 { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1, 34290 0, 34291 Opcode_xsr_scompare1_encode_fns, 0, 0 }, 34292 { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl, 34293 0, 34294 Opcode_rsr_atomctl_encode_fns, 0, 0 }, 34295 { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl, 34296 0, 34297 Opcode_wsr_atomctl_encode_fns, 0, 0 }, 34298 { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl, 34299 0, 34300 Opcode_xsr_atomctl_encode_fns, 0, 0 }, 34301 { "quou", ICLASS_xt_iclass_div, 34302 0, 34303 Opcode_quou_encode_fns, 0, 0 }, 34304 { "quos", ICLASS_xt_iclass_div, 34305 0, 34306 Opcode_quos_encode_fns, 0, 0 }, 34307 { "remu", ICLASS_xt_iclass_div, 34308 0, 34309 Opcode_remu_encode_fns, 0, 0 }, 34310 { "rems", ICLASS_xt_iclass_div, 34311 0, 34312 Opcode_rems_encode_fns, 0, 0 }, 34313 { "rer", ICLASS_xt_iclass_rer, 34314 0, 34315 Opcode_rer_encode_fns, 0, 0 }, 34316 { "wer", ICLASS_xt_iclass_wer, 34317 0, 34318 Opcode_wer_encode_fns, 0, 0 }, 34319 { "rur.ae_ovf_sar", ICLASS_rur_ae_ovf_sar, 34320 0, 34321 Opcode_rur_ae_ovf_sar_encode_fns, 0, 0 }, 34322 { "wur.ae_ovf_sar", ICLASS_wur_ae_ovf_sar, 34323 0, 34324 Opcode_wur_ae_ovf_sar_encode_fns, 0, 0 }, 34325 { "rur.ae_bithead", ICLASS_rur_ae_bithead, 34326 0, 34327 Opcode_rur_ae_bithead_encode_fns, 0, 0 }, 34328 { "wur.ae_bithead", ICLASS_wur_ae_bithead, 34329 0, 34330 Opcode_wur_ae_bithead_encode_fns, 0, 0 }, 34331 { "rur.ae_ts_fts_bu_bp", ICLASS_rur_ae_ts_fts_bu_bp, 34332 0, 34333 Opcode_rur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, 34334 { "wur.ae_ts_fts_bu_bp", ICLASS_wur_ae_ts_fts_bu_bp, 34335 0, 34336 Opcode_wur_ae_ts_fts_bu_bp_encode_fns, 0, 0 }, 34337 { "rur.ae_sd_no", ICLASS_rur_ae_sd_no, 34338 0, 34339 Opcode_rur_ae_sd_no_encode_fns, 0, 0 }, 34340 { "wur.ae_sd_no", ICLASS_wur_ae_sd_no, 34341 0, 34342 Opcode_wur_ae_sd_no_encode_fns, 0, 0 }, 34343 { "rur.ae_overflow", ICLASS_ae_iclass_rur_ae_overflow, 34344 0, 34345 Opcode_rur_ae_overflow_encode_fns, 0, 0 }, 34346 { "wur.ae_overflow", ICLASS_ae_iclass_wur_ae_overflow, 34347 0, 34348 Opcode_wur_ae_overflow_encode_fns, 0, 0 }, 34349 { "rur.ae_sar", ICLASS_ae_iclass_rur_ae_sar, 34350 0, 34351 Opcode_rur_ae_sar_encode_fns, 0, 0 }, 34352 { "wur.ae_sar", ICLASS_ae_iclass_wur_ae_sar, 34353 0, 34354 Opcode_wur_ae_sar_encode_fns, 0, 0 }, 34355 { "rur.ae_bitptr", ICLASS_ae_iclass_rur_ae_bitptr, 34356 0, 34357 Opcode_rur_ae_bitptr_encode_fns, 0, 0 }, 34358 { "wur.ae_bitptr", ICLASS_ae_iclass_wur_ae_bitptr, 34359 0, 34360 Opcode_wur_ae_bitptr_encode_fns, 0, 0 }, 34361 { "rur.ae_bitsused", ICLASS_ae_iclass_rur_ae_bitsused, 34362 0, 34363 Opcode_rur_ae_bitsused_encode_fns, 0, 0 }, 34364 { "wur.ae_bitsused", ICLASS_ae_iclass_wur_ae_bitsused, 34365 0, 34366 Opcode_wur_ae_bitsused_encode_fns, 0, 0 }, 34367 { "rur.ae_tablesize", ICLASS_ae_iclass_rur_ae_tablesize, 34368 0, 34369 Opcode_rur_ae_tablesize_encode_fns, 0, 0 }, 34370 { "wur.ae_tablesize", ICLASS_ae_iclass_wur_ae_tablesize, 34371 0, 34372 Opcode_wur_ae_tablesize_encode_fns, 0, 0 }, 34373 { "rur.ae_first_ts", ICLASS_ae_iclass_rur_ae_first_ts, 34374 0, 34375 Opcode_rur_ae_first_ts_encode_fns, 0, 0 }, 34376 { "wur.ae_first_ts", ICLASS_ae_iclass_wur_ae_first_ts, 34377 0, 34378 Opcode_wur_ae_first_ts_encode_fns, 0, 0 }, 34379 { "rur.ae_nextoffset", ICLASS_ae_iclass_rur_ae_nextoffset, 34380 0, 34381 Opcode_rur_ae_nextoffset_encode_fns, 0, 0 }, 34382 { "wur.ae_nextoffset", ICLASS_ae_iclass_wur_ae_nextoffset, 34383 0, 34384 Opcode_wur_ae_nextoffset_encode_fns, 0, 0 }, 34385 { "rur.ae_searchdone", ICLASS_ae_iclass_rur_ae_searchdone, 34386 0, 34387 Opcode_rur_ae_searchdone_encode_fns, 0, 0 }, 34388 { "wur.ae_searchdone", ICLASS_ae_iclass_wur_ae_searchdone, 34389 0, 34390 Opcode_wur_ae_searchdone_encode_fns, 0, 0 }, 34391 { "ae_lp16f.i", ICLASS_ae_iclass_lp16f_i, 34392 0, 34393 Opcode_ae_lp16f_i_encode_fns, 0, 0 }, 34394 { "ae_lp16f.iu", ICLASS_ae_iclass_lp16f_iu, 34395 0, 34396 Opcode_ae_lp16f_iu_encode_fns, 0, 0 }, 34397 { "ae_lp16f.x", ICLASS_ae_iclass_lp16f_x, 34398 0, 34399 Opcode_ae_lp16f_x_encode_fns, 0, 0 }, 34400 { "ae_lp16f.xu", ICLASS_ae_iclass_lp16f_xu, 34401 0, 34402 Opcode_ae_lp16f_xu_encode_fns, 0, 0 }, 34403 { "ae_lp24.i", ICLASS_ae_iclass_lp24_i, 34404 0, 34405 Opcode_ae_lp24_i_encode_fns, 0, 0 }, 34406 { "ae_lp24.iu", ICLASS_ae_iclass_lp24_iu, 34407 0, 34408 Opcode_ae_lp24_iu_encode_fns, 0, 0 }, 34409 { "ae_lp24.x", ICLASS_ae_iclass_lp24_x, 34410 0, 34411 Opcode_ae_lp24_x_encode_fns, 0, 0 }, 34412 { "ae_lp24.xu", ICLASS_ae_iclass_lp24_xu, 34413 0, 34414 Opcode_ae_lp24_xu_encode_fns, 0, 0 }, 34415 { "ae_lp24f.i", ICLASS_ae_iclass_lp24f_i, 34416 0, 34417 Opcode_ae_lp24f_i_encode_fns, 0, 0 }, 34418 { "ae_lp24f.iu", ICLASS_ae_iclass_lp24f_iu, 34419 0, 34420 Opcode_ae_lp24f_iu_encode_fns, 0, 0 }, 34421 { "ae_lp24f.x", ICLASS_ae_iclass_lp24f_x, 34422 0, 34423 Opcode_ae_lp24f_x_encode_fns, 0, 0 }, 34424 { "ae_lp24f.xu", ICLASS_ae_iclass_lp24f_xu, 34425 0, 34426 Opcode_ae_lp24f_xu_encode_fns, 0, 0 }, 34427 { "ae_lp16x2f.i", ICLASS_ae_iclass_lp16x2f_i, 34428 0, 34429 Opcode_ae_lp16x2f_i_encode_fns, 0, 0 }, 34430 { "ae_lp16x2f.iu", ICLASS_ae_iclass_lp16x2f_iu, 34431 0, 34432 Opcode_ae_lp16x2f_iu_encode_fns, 0, 0 }, 34433 { "ae_lp16x2f.x", ICLASS_ae_iclass_lp16x2f_x, 34434 0, 34435 Opcode_ae_lp16x2f_x_encode_fns, 0, 0 }, 34436 { "ae_lp16x2f.xu", ICLASS_ae_iclass_lp16x2f_xu, 34437 0, 34438 Opcode_ae_lp16x2f_xu_encode_fns, 0, 0 }, 34439 { "ae_lp24x2f.i", ICLASS_ae_iclass_lp24x2f_i, 34440 0, 34441 Opcode_ae_lp24x2f_i_encode_fns, 0, 0 }, 34442 { "ae_lp24x2f.iu", ICLASS_ae_iclass_lp24x2f_iu, 34443 0, 34444 Opcode_ae_lp24x2f_iu_encode_fns, 0, 0 }, 34445 { "ae_lp24x2f.x", ICLASS_ae_iclass_lp24x2f_x, 34446 0, 34447 Opcode_ae_lp24x2f_x_encode_fns, 0, 0 }, 34448 { "ae_lp24x2f.xu", ICLASS_ae_iclass_lp24x2f_xu, 34449 0, 34450 Opcode_ae_lp24x2f_xu_encode_fns, 0, 0 }, 34451 { "ae_lp24x2.i", ICLASS_ae_iclass_lp24x2_i, 34452 0, 34453 Opcode_ae_lp24x2_i_encode_fns, 0, 0 }, 34454 { "ae_lp24x2.iu", ICLASS_ae_iclass_lp24x2_iu, 34455 0, 34456 Opcode_ae_lp24x2_iu_encode_fns, 0, 0 }, 34457 { "ae_lp24x2.x", ICLASS_ae_iclass_lp24x2_x, 34458 0, 34459 Opcode_ae_lp24x2_x_encode_fns, 0, 0 }, 34460 { "ae_lp24x2.xu", ICLASS_ae_iclass_lp24x2_xu, 34461 0, 34462 Opcode_ae_lp24x2_xu_encode_fns, 0, 0 }, 34463 { "ae_sp16x2f.i", ICLASS_ae_iclass_sp16x2f_i, 34464 0, 34465 Opcode_ae_sp16x2f_i_encode_fns, 0, 0 }, 34466 { "ae_sp16x2f.iu", ICLASS_ae_iclass_sp16x2f_iu, 34467 0, 34468 Opcode_ae_sp16x2f_iu_encode_fns, 0, 0 }, 34469 { "ae_sp16x2f.x", ICLASS_ae_iclass_sp16x2f_x, 34470 0, 34471 Opcode_ae_sp16x2f_x_encode_fns, 0, 0 }, 34472 { "ae_sp16x2f.xu", ICLASS_ae_iclass_sp16x2f_xu, 34473 0, 34474 Opcode_ae_sp16x2f_xu_encode_fns, 0, 0 }, 34475 { "ae_sp24x2s.i", ICLASS_ae_iclass_sp24x2s_i, 34476 0, 34477 Opcode_ae_sp24x2s_i_encode_fns, 0, 0 }, 34478 { "ae_sp24x2s.iu", ICLASS_ae_iclass_sp24x2s_iu, 34479 0, 34480 Opcode_ae_sp24x2s_iu_encode_fns, 0, 0 }, 34481 { "ae_sp24x2s.x", ICLASS_ae_iclass_sp24x2s_x, 34482 0, 34483 Opcode_ae_sp24x2s_x_encode_fns, 0, 0 }, 34484 { "ae_sp24x2s.xu", ICLASS_ae_iclass_sp24x2s_xu, 34485 0, 34486 Opcode_ae_sp24x2s_xu_encode_fns, 0, 0 }, 34487 { "ae_sp24x2f.i", ICLASS_ae_iclass_sp24x2f_i, 34488 0, 34489 Opcode_ae_sp24x2f_i_encode_fns, 0, 0 }, 34490 { "ae_sp24x2f.iu", ICLASS_ae_iclass_sp24x2f_iu, 34491 0, 34492 Opcode_ae_sp24x2f_iu_encode_fns, 0, 0 }, 34493 { "ae_sp24x2f.x", ICLASS_ae_iclass_sp24x2f_x, 34494 0, 34495 Opcode_ae_sp24x2f_x_encode_fns, 0, 0 }, 34496 { "ae_sp24x2f.xu", ICLASS_ae_iclass_sp24x2f_xu, 34497 0, 34498 Opcode_ae_sp24x2f_xu_encode_fns, 0, 0 }, 34499 { "ae_sp16f.l.i", ICLASS_ae_iclass_sp16f_l_i, 34500 0, 34501 Opcode_ae_sp16f_l_i_encode_fns, 0, 0 }, 34502 { "ae_sp16f.l.iu", ICLASS_ae_iclass_sp16f_l_iu, 34503 0, 34504 Opcode_ae_sp16f_l_iu_encode_fns, 0, 0 }, 34505 { "ae_sp16f.l.x", ICLASS_ae_iclass_sp16f_l_x, 34506 0, 34507 Opcode_ae_sp16f_l_x_encode_fns, 0, 0 }, 34508 { "ae_sp16f.l.xu", ICLASS_ae_iclass_sp16f_l_xu, 34509 0, 34510 Opcode_ae_sp16f_l_xu_encode_fns, 0, 0 }, 34511 { "ae_sp24s.l.i", ICLASS_ae_iclass_sp24s_l_i, 34512 0, 34513 Opcode_ae_sp24s_l_i_encode_fns, 0, 0 }, 34514 { "ae_sp24s.l.iu", ICLASS_ae_iclass_sp24s_l_iu, 34515 0, 34516 Opcode_ae_sp24s_l_iu_encode_fns, 0, 0 }, 34517 { "ae_sp24s.l.x", ICLASS_ae_iclass_sp24s_l_x, 34518 0, 34519 Opcode_ae_sp24s_l_x_encode_fns, 0, 0 }, 34520 { "ae_sp24s.l.xu", ICLASS_ae_iclass_sp24s_l_xu, 34521 0, 34522 Opcode_ae_sp24s_l_xu_encode_fns, 0, 0 }, 34523 { "ae_sp24f.l.i", ICLASS_ae_iclass_sp24f_l_i, 34524 0, 34525 Opcode_ae_sp24f_l_i_encode_fns, 0, 0 }, 34526 { "ae_sp24f.l.iu", ICLASS_ae_iclass_sp24f_l_iu, 34527 0, 34528 Opcode_ae_sp24f_l_iu_encode_fns, 0, 0 }, 34529 { "ae_sp24f.l.x", ICLASS_ae_iclass_sp24f_l_x, 34530 0, 34531 Opcode_ae_sp24f_l_x_encode_fns, 0, 0 }, 34532 { "ae_sp24f.l.xu", ICLASS_ae_iclass_sp24f_l_xu, 34533 0, 34534 Opcode_ae_sp24f_l_xu_encode_fns, 0, 0 }, 34535 { "ae_lq56.i", ICLASS_ae_iclass_lq56_i, 34536 0, 34537 Opcode_ae_lq56_i_encode_fns, 0, 0 }, 34538 { "ae_lq56.iu", ICLASS_ae_iclass_lq56_iu, 34539 0, 34540 Opcode_ae_lq56_iu_encode_fns, 0, 0 }, 34541 { "ae_lq56.x", ICLASS_ae_iclass_lq56_x, 34542 0, 34543 Opcode_ae_lq56_x_encode_fns, 0, 0 }, 34544 { "ae_lq56.xu", ICLASS_ae_iclass_lq56_xu, 34545 0, 34546 Opcode_ae_lq56_xu_encode_fns, 0, 0 }, 34547 { "ae_lq32f.i", ICLASS_ae_iclass_lq32f_i, 34548 0, 34549 Opcode_ae_lq32f_i_encode_fns, 0, 0 }, 34550 { "ae_lq32f.iu", ICLASS_ae_iclass_lq32f_iu, 34551 0, 34552 Opcode_ae_lq32f_iu_encode_fns, 0, 0 }, 34553 { "ae_lq32f.x", ICLASS_ae_iclass_lq32f_x, 34554 0, 34555 Opcode_ae_lq32f_x_encode_fns, 0, 0 }, 34556 { "ae_lq32f.xu", ICLASS_ae_iclass_lq32f_xu, 34557 0, 34558 Opcode_ae_lq32f_xu_encode_fns, 0, 0 }, 34559 { "ae_sq56s.i", ICLASS_ae_iclass_sq56s_i, 34560 0, 34561 Opcode_ae_sq56s_i_encode_fns, 0, 0 }, 34562 { "ae_sq56s.iu", ICLASS_ae_iclass_sq56s_iu, 34563 0, 34564 Opcode_ae_sq56s_iu_encode_fns, 0, 0 }, 34565 { "ae_sq56s.x", ICLASS_ae_iclass_sq56s_x, 34566 0, 34567 Opcode_ae_sq56s_x_encode_fns, 0, 0 }, 34568 { "ae_sq56s.xu", ICLASS_ae_iclass_sq56s_xu, 34569 0, 34570 Opcode_ae_sq56s_xu_encode_fns, 0, 0 }, 34571 { "ae_sq32f.i", ICLASS_ae_iclass_sq32f_i, 34572 0, 34573 Opcode_ae_sq32f_i_encode_fns, 0, 0 }, 34574 { "ae_sq32f.iu", ICLASS_ae_iclass_sq32f_iu, 34575 0, 34576 Opcode_ae_sq32f_iu_encode_fns, 0, 0 }, 34577 { "ae_sq32f.x", ICLASS_ae_iclass_sq32f_x, 34578 0, 34579 Opcode_ae_sq32f_x_encode_fns, 0, 0 }, 34580 { "ae_sq32f.xu", ICLASS_ae_iclass_sq32f_xu, 34581 0, 34582 Opcode_ae_sq32f_xu_encode_fns, 0, 0 }, 34583 { "ae_zerop48", ICLASS_ae_iclass_zerop48, 34584 0, 34585 Opcode_ae_zerop48_encode_fns, 0, 0 }, 34586 { "ae_movp48", ICLASS_ae_iclass_movp48, 34587 0, 34588 Opcode_ae_movp48_encode_fns, 0, 0 }, 34589 { "ae_selp24.ll", ICLASS_ae_iclass_selp24_ll, 34590 0, 34591 Opcode_ae_selp24_ll_encode_fns, 0, 0 }, 34592 { "ae_selp24.lh", ICLASS_ae_iclass_selp24_lh, 34593 0, 34594 Opcode_ae_selp24_lh_encode_fns, 0, 0 }, 34595 { "ae_selp24.hl", ICLASS_ae_iclass_selp24_hl, 34596 0, 34597 Opcode_ae_selp24_hl_encode_fns, 0, 0 }, 34598 { "ae_selp24.hh", ICLASS_ae_iclass_selp24_hh, 34599 0, 34600 Opcode_ae_selp24_hh_encode_fns, 0, 0 }, 34601 { "ae_movtp24x2", ICLASS_ae_iclass_movtp24x2, 34602 0, 34603 Opcode_ae_movtp24x2_encode_fns, 0, 0 }, 34604 { "ae_movfp24x2", ICLASS_ae_iclass_movfp24x2, 34605 0, 34606 Opcode_ae_movfp24x2_encode_fns, 0, 0 }, 34607 { "ae_movtp48", ICLASS_ae_iclass_movtp48, 34608 0, 34609 Opcode_ae_movtp48_encode_fns, 0, 0 }, 34610 { "ae_movfp48", ICLASS_ae_iclass_movfp48, 34611 0, 34612 Opcode_ae_movfp48_encode_fns, 0, 0 }, 34613 { "ae_movpa24x2", ICLASS_ae_iclass_movpa24x2, 34614 0, 34615 Opcode_ae_movpa24x2_encode_fns, 0, 0 }, 34616 { "ae_truncp24a32x2", ICLASS_ae_iclass_truncp24a32x2, 34617 0, 34618 Opcode_ae_truncp24a32x2_encode_fns, 0, 0 }, 34619 { "ae_cvta32p24.l", ICLASS_ae_iclass_cvta32p24_l, 34620 0, 34621 Opcode_ae_cvta32p24_l_encode_fns, 0, 0 }, 34622 { "ae_cvta32p24.h", ICLASS_ae_iclass_cvta32p24_h, 34623 0, 34624 Opcode_ae_cvta32p24_h_encode_fns, 0, 0 }, 34625 { "ae_cvtp24a16x2.ll", ICLASS_ae_iclass_cvtp24a16x2_ll, 34626 0, 34627 Opcode_ae_cvtp24a16x2_ll_encode_fns, 0, 0 }, 34628 { "ae_cvtp24a16x2.lh", ICLASS_ae_iclass_cvtp24a16x2_lh, 34629 0, 34630 Opcode_ae_cvtp24a16x2_lh_encode_fns, 0, 0 }, 34631 { "ae_cvtp24a16x2.hl", ICLASS_ae_iclass_cvtp24a16x2_hl, 34632 0, 34633 Opcode_ae_cvtp24a16x2_hl_encode_fns, 0, 0 }, 34634 { "ae_cvtp24a16x2.hh", ICLASS_ae_iclass_cvtp24a16x2_hh, 34635 0, 34636 Opcode_ae_cvtp24a16x2_hh_encode_fns, 0, 0 }, 34637 { "ae_truncp24q48x2", ICLASS_ae_iclass_truncp24q48x2, 34638 0, 34639 Opcode_ae_truncp24q48x2_encode_fns, 0, 0 }, 34640 { "ae_truncp16", ICLASS_ae_iclass_truncp16, 34641 0, 34642 Opcode_ae_truncp16_encode_fns, 0, 0 }, 34643 { "ae_roundsp24q48sym", ICLASS_ae_iclass_roundsp24q48sym, 34644 0, 34645 Opcode_ae_roundsp24q48sym_encode_fns, 0, 0 }, 34646 { "ae_roundsp24q48asym", ICLASS_ae_iclass_roundsp24q48asym, 34647 0, 34648 Opcode_ae_roundsp24q48asym_encode_fns, 0, 0 }, 34649 { "ae_roundsp16q48sym", ICLASS_ae_iclass_roundsp16q48sym, 34650 0, 34651 Opcode_ae_roundsp16q48sym_encode_fns, 0, 0 }, 34652 { "ae_roundsp16q48asym", ICLASS_ae_iclass_roundsp16q48asym, 34653 0, 34654 Opcode_ae_roundsp16q48asym_encode_fns, 0, 0 }, 34655 { "ae_roundsp16sym", ICLASS_ae_iclass_roundsp16sym, 34656 0, 34657 Opcode_ae_roundsp16sym_encode_fns, 0, 0 }, 34658 { "ae_roundsp16asym", ICLASS_ae_iclass_roundsp16asym, 34659 0, 34660 Opcode_ae_roundsp16asym_encode_fns, 0, 0 }, 34661 { "ae_zeroq56", ICLASS_ae_iclass_zeroq56, 34662 0, 34663 Opcode_ae_zeroq56_encode_fns, 0, 0 }, 34664 { "ae_movq56", ICLASS_ae_iclass_movq56, 34665 0, 34666 Opcode_ae_movq56_encode_fns, 0, 0 }, 34667 { "ae_movtq56", ICLASS_ae_iclass_movtq56, 34668 0, 34669 Opcode_ae_movtq56_encode_fns, 0, 0 }, 34670 { "ae_movfq56", ICLASS_ae_iclass_movfq56, 34671 0, 34672 Opcode_ae_movfq56_encode_fns, 0, 0 }, 34673 { "ae_cvtq48a32s", ICLASS_ae_iclass_cvtq48a32s, 34674 0, 34675 Opcode_ae_cvtq48a32s_encode_fns, 0, 0 }, 34676 { "ae_cvtq48p24s.l", ICLASS_ae_iclass_cvtq48p24s_l, 34677 0, 34678 Opcode_ae_cvtq48p24s_l_encode_fns, 0, 0 }, 34679 { "ae_cvtq48p24s.h", ICLASS_ae_iclass_cvtq48p24s_h, 34680 0, 34681 Opcode_ae_cvtq48p24s_h_encode_fns, 0, 0 }, 34682 { "ae_satq48s", ICLASS_ae_iclass_satq48s, 34683 0, 34684 Opcode_ae_satq48s_encode_fns, 0, 0 }, 34685 { "ae_truncq32", ICLASS_ae_iclass_truncq32, 34686 0, 34687 Opcode_ae_truncq32_encode_fns, 0, 0 }, 34688 { "ae_roundsq32sym", ICLASS_ae_iclass_roundsq32sym, 34689 0, 34690 Opcode_ae_roundsq32sym_encode_fns, 0, 0 }, 34691 { "ae_roundsq32asym", ICLASS_ae_iclass_roundsq32asym, 34692 0, 34693 Opcode_ae_roundsq32asym_encode_fns, 0, 0 }, 34694 { "ae_trunca32q48", ICLASS_ae_iclass_trunca32q48, 34695 0, 34696 Opcode_ae_trunca32q48_encode_fns, 0, 0 }, 34697 { "ae_movap24s.l", ICLASS_ae_iclass_movap24s_l, 34698 0, 34699 Opcode_ae_movap24s_l_encode_fns, 0, 0 }, 34700 { "ae_movap24s.h", ICLASS_ae_iclass_movap24s_h, 34701 0, 34702 Opcode_ae_movap24s_h_encode_fns, 0, 0 }, 34703 { "ae_trunca16p24s.l", ICLASS_ae_iclass_trunca16p24s_l, 34704 0, 34705 Opcode_ae_trunca16p24s_l_encode_fns, 0, 0 }, 34706 { "ae_trunca16p24s.h", ICLASS_ae_iclass_trunca16p24s_h, 34707 0, 34708 Opcode_ae_trunca16p24s_h_encode_fns, 0, 0 }, 34709 { "ae_addp24", ICLASS_ae_iclass_addp24, 34710 0, 34711 Opcode_ae_addp24_encode_fns, 0, 0 }, 34712 { "ae_subp24", ICLASS_ae_iclass_subp24, 34713 0, 34714 Opcode_ae_subp24_encode_fns, 0, 0 }, 34715 { "ae_negp24", ICLASS_ae_iclass_negp24, 34716 0, 34717 Opcode_ae_negp24_encode_fns, 0, 0 }, 34718 { "ae_absp24", ICLASS_ae_iclass_absp24, 34719 0, 34720 Opcode_ae_absp24_encode_fns, 0, 0 }, 34721 { "ae_maxp24s", ICLASS_ae_iclass_maxp24s, 34722 0, 34723 Opcode_ae_maxp24s_encode_fns, 0, 0 }, 34724 { "ae_minp24s", ICLASS_ae_iclass_minp24s, 34725 0, 34726 Opcode_ae_minp24s_encode_fns, 0, 0 }, 34727 { "ae_maxbp24s", ICLASS_ae_iclass_maxbp24s, 34728 0, 34729 Opcode_ae_maxbp24s_encode_fns, 0, 0 }, 34730 { "ae_minbp24s", ICLASS_ae_iclass_minbp24s, 34731 0, 34732 Opcode_ae_minbp24s_encode_fns, 0, 0 }, 34733 { "ae_addsp24s", ICLASS_ae_iclass_addsp24s, 34734 0, 34735 Opcode_ae_addsp24s_encode_fns, 0, 0 }, 34736 { "ae_subsp24s", ICLASS_ae_iclass_subsp24s, 34737 0, 34738 Opcode_ae_subsp24s_encode_fns, 0, 0 }, 34739 { "ae_negsp24s", ICLASS_ae_iclass_negsp24s, 34740 0, 34741 Opcode_ae_negsp24s_encode_fns, 0, 0 }, 34742 { "ae_abssp24s", ICLASS_ae_iclass_abssp24s, 34743 0, 34744 Opcode_ae_abssp24s_encode_fns, 0, 0 }, 34745 { "ae_andp48", ICLASS_ae_iclass_andp48, 34746 0, 34747 Opcode_ae_andp48_encode_fns, 0, 0 }, 34748 { "ae_nandp48", ICLASS_ae_iclass_nandp48, 34749 0, 34750 Opcode_ae_nandp48_encode_fns, 0, 0 }, 34751 { "ae_orp48", ICLASS_ae_iclass_orp48, 34752 0, 34753 Opcode_ae_orp48_encode_fns, 0, 0 }, 34754 { "ae_xorp48", ICLASS_ae_iclass_xorp48, 34755 0, 34756 Opcode_ae_xorp48_encode_fns, 0, 0 }, 34757 { "ae_ltp24s", ICLASS_ae_iclass_ltp24s, 34758 0, 34759 Opcode_ae_ltp24s_encode_fns, 0, 0 }, 34760 { "ae_lep24s", ICLASS_ae_iclass_lep24s, 34761 0, 34762 Opcode_ae_lep24s_encode_fns, 0, 0 }, 34763 { "ae_eqp24", ICLASS_ae_iclass_eqp24, 34764 0, 34765 Opcode_ae_eqp24_encode_fns, 0, 0 }, 34766 { "ae_addq56", ICLASS_ae_iclass_addq56, 34767 0, 34768 Opcode_ae_addq56_encode_fns, 0, 0 }, 34769 { "ae_subq56", ICLASS_ae_iclass_subq56, 34770 0, 34771 Opcode_ae_subq56_encode_fns, 0, 0 }, 34772 { "ae_negq56", ICLASS_ae_iclass_negq56, 34773 0, 34774 Opcode_ae_negq56_encode_fns, 0, 0 }, 34775 { "ae_absq56", ICLASS_ae_iclass_absq56, 34776 0, 34777 Opcode_ae_absq56_encode_fns, 0, 0 }, 34778 { "ae_maxq56s", ICLASS_ae_iclass_maxq56s, 34779 0, 34780 Opcode_ae_maxq56s_encode_fns, 0, 0 }, 34781 { "ae_minq56s", ICLASS_ae_iclass_minq56s, 34782 0, 34783 Opcode_ae_minq56s_encode_fns, 0, 0 }, 34784 { "ae_maxbq56s", ICLASS_ae_iclass_maxbq56s, 34785 0, 34786 Opcode_ae_maxbq56s_encode_fns, 0, 0 }, 34787 { "ae_minbq56s", ICLASS_ae_iclass_minbq56s, 34788 0, 34789 Opcode_ae_minbq56s_encode_fns, 0, 0 }, 34790 { "ae_addsq56s", ICLASS_ae_iclass_addsq56s, 34791 0, 34792 Opcode_ae_addsq56s_encode_fns, 0, 0 }, 34793 { "ae_subsq56s", ICLASS_ae_iclass_subsq56s, 34794 0, 34795 Opcode_ae_subsq56s_encode_fns, 0, 0 }, 34796 { "ae_negsq56s", ICLASS_ae_iclass_negsq56s, 34797 0, 34798 Opcode_ae_negsq56s_encode_fns, 0, 0 }, 34799 { "ae_abssq56s", ICLASS_ae_iclass_abssq56s, 34800 0, 34801 Opcode_ae_abssq56s_encode_fns, 0, 0 }, 34802 { "ae_andq56", ICLASS_ae_iclass_andq56, 34803 0, 34804 Opcode_ae_andq56_encode_fns, 0, 0 }, 34805 { "ae_nandq56", ICLASS_ae_iclass_nandq56, 34806 0, 34807 Opcode_ae_nandq56_encode_fns, 0, 0 }, 34808 { "ae_orq56", ICLASS_ae_iclass_orq56, 34809 0, 34810 Opcode_ae_orq56_encode_fns, 0, 0 }, 34811 { "ae_xorq56", ICLASS_ae_iclass_xorq56, 34812 0, 34813 Opcode_ae_xorq56_encode_fns, 0, 0 }, 34814 { "ae_sllip24", ICLASS_ae_iclass_sllip24, 34815 0, 34816 Opcode_ae_sllip24_encode_fns, 0, 0 }, 34817 { "ae_srlip24", ICLASS_ae_iclass_srlip24, 34818 0, 34819 Opcode_ae_srlip24_encode_fns, 0, 0 }, 34820 { "ae_sraip24", ICLASS_ae_iclass_sraip24, 34821 0, 34822 Opcode_ae_sraip24_encode_fns, 0, 0 }, 34823 { "ae_sllsp24", ICLASS_ae_iclass_sllsp24, 34824 0, 34825 Opcode_ae_sllsp24_encode_fns, 0, 0 }, 34826 { "ae_srlsp24", ICLASS_ae_iclass_srlsp24, 34827 0, 34828 Opcode_ae_srlsp24_encode_fns, 0, 0 }, 34829 { "ae_srasp24", ICLASS_ae_iclass_srasp24, 34830 0, 34831 Opcode_ae_srasp24_encode_fns, 0, 0 }, 34832 { "ae_sllisp24s", ICLASS_ae_iclass_sllisp24s, 34833 0, 34834 Opcode_ae_sllisp24s_encode_fns, 0, 0 }, 34835 { "ae_sllssp24s", ICLASS_ae_iclass_sllssp24s, 34836 0, 34837 Opcode_ae_sllssp24s_encode_fns, 0, 0 }, 34838 { "ae_slliq56", ICLASS_ae_iclass_slliq56, 34839 0, 34840 Opcode_ae_slliq56_encode_fns, 0, 0 }, 34841 { "ae_srliq56", ICLASS_ae_iclass_srliq56, 34842 0, 34843 Opcode_ae_srliq56_encode_fns, 0, 0 }, 34844 { "ae_sraiq56", ICLASS_ae_iclass_sraiq56, 34845 0, 34846 Opcode_ae_sraiq56_encode_fns, 0, 0 }, 34847 { "ae_sllsq56", ICLASS_ae_iclass_sllsq56, 34848 0, 34849 Opcode_ae_sllsq56_encode_fns, 0, 0 }, 34850 { "ae_srlsq56", ICLASS_ae_iclass_srlsq56, 34851 0, 34852 Opcode_ae_srlsq56_encode_fns, 0, 0 }, 34853 { "ae_srasq56", ICLASS_ae_iclass_srasq56, 34854 0, 34855 Opcode_ae_srasq56_encode_fns, 0, 0 }, 34856 { "ae_sllaq56", ICLASS_ae_iclass_sllaq56, 34857 0, 34858 Opcode_ae_sllaq56_encode_fns, 0, 0 }, 34859 { "ae_srlaq56", ICLASS_ae_iclass_srlaq56, 34860 0, 34861 Opcode_ae_srlaq56_encode_fns, 0, 0 }, 34862 { "ae_sraaq56", ICLASS_ae_iclass_sraaq56, 34863 0, 34864 Opcode_ae_sraaq56_encode_fns, 0, 0 }, 34865 { "ae_sllisq56s", ICLASS_ae_iclass_sllisq56s, 34866 0, 34867 Opcode_ae_sllisq56s_encode_fns, 0, 0 }, 34868 { "ae_sllssq56s", ICLASS_ae_iclass_sllssq56s, 34869 0, 34870 Opcode_ae_sllssq56s_encode_fns, 0, 0 }, 34871 { "ae_sllasq56s", ICLASS_ae_iclass_sllasq56s, 34872 0, 34873 Opcode_ae_sllasq56s_encode_fns, 0, 0 }, 34874 { "ae_ltq56s", ICLASS_ae_iclass_ltq56s, 34875 0, 34876 Opcode_ae_ltq56s_encode_fns, 0, 0 }, 34877 { "ae_leq56s", ICLASS_ae_iclass_leq56s, 34878 0, 34879 Opcode_ae_leq56s_encode_fns, 0, 0 }, 34880 { "ae_eqq56", ICLASS_ae_iclass_eqq56, 34881 0, 34882 Opcode_ae_eqq56_encode_fns, 0, 0 }, 34883 { "ae_nsaq56s", ICLASS_ae_iclass_nsaq56s, 34884 0, 34885 Opcode_ae_nsaq56s_encode_fns, 0, 0 }, 34886 { "ae_mulsrfq32sp24s.h", ICLASS_ae_iclass_mulsrfq32sp24s_h, 34887 0, 34888 Opcode_ae_mulsrfq32sp24s_h_encode_fns, 0, 0 }, 34889 { "ae_mulsrfq32sp24s.l", ICLASS_ae_iclass_mulsrfq32sp24s_l, 34890 0, 34891 Opcode_ae_mulsrfq32sp24s_l_encode_fns, 0, 0 }, 34892 { "ae_mularfq32sp24s.h", ICLASS_ae_iclass_mularfq32sp24s_h, 34893 0, 34894 Opcode_ae_mularfq32sp24s_h_encode_fns, 0, 0 }, 34895 { "ae_mularfq32sp24s.l", ICLASS_ae_iclass_mularfq32sp24s_l, 34896 0, 34897 Opcode_ae_mularfq32sp24s_l_encode_fns, 0, 0 }, 34898 { "ae_mulrfq32sp24s.h", ICLASS_ae_iclass_mulrfq32sp24s_h, 34899 0, 34900 Opcode_ae_mulrfq32sp24s_h_encode_fns, 0, 0 }, 34901 { "ae_mulrfq32sp24s.l", ICLASS_ae_iclass_mulrfq32sp24s_l, 34902 0, 34903 Opcode_ae_mulrfq32sp24s_l_encode_fns, 0, 0 }, 34904 { "ae_mulsfq32sp24s.h", ICLASS_ae_iclass_mulsfq32sp24s_h, 34905 0, 34906 Opcode_ae_mulsfq32sp24s_h_encode_fns, 0, 0 }, 34907 { "ae_mulsfq32sp24s.l", ICLASS_ae_iclass_mulsfq32sp24s_l, 34908 0, 34909 Opcode_ae_mulsfq32sp24s_l_encode_fns, 0, 0 }, 34910 { "ae_mulafq32sp24s.h", ICLASS_ae_iclass_mulafq32sp24s_h, 34911 0, 34912 Opcode_ae_mulafq32sp24s_h_encode_fns, 0, 0 }, 34913 { "ae_mulafq32sp24s.l", ICLASS_ae_iclass_mulafq32sp24s_l, 34914 0, 34915 Opcode_ae_mulafq32sp24s_l_encode_fns, 0, 0 }, 34916 { "ae_mulfq32sp24s.h", ICLASS_ae_iclass_mulfq32sp24s_h, 34917 0, 34918 Opcode_ae_mulfq32sp24s_h_encode_fns, 0, 0 }, 34919 { "ae_mulfq32sp24s.l", ICLASS_ae_iclass_mulfq32sp24s_l, 34920 0, 34921 Opcode_ae_mulfq32sp24s_l_encode_fns, 0, 0 }, 34922 { "ae_mulfs32p16s.ll", ICLASS_ae_iclass_mulfs32p16s_ll, 34923 0, 34924 Opcode_ae_mulfs32p16s_ll_encode_fns, 0, 0 }, 34925 { "ae_mulfp24s.ll", ICLASS_ae_iclass_mulfp24s_ll, 34926 0, 34927 Opcode_ae_mulfp24s_ll_encode_fns, 0, 0 }, 34928 { "ae_mulp24s.ll", ICLASS_ae_iclass_mulp24s_ll, 34929 0, 34930 Opcode_ae_mulp24s_ll_encode_fns, 0, 0 }, 34931 { "ae_mulfs32p16s.lh", ICLASS_ae_iclass_mulfs32p16s_lh, 34932 0, 34933 Opcode_ae_mulfs32p16s_lh_encode_fns, 0, 0 }, 34934 { "ae_mulfp24s.lh", ICLASS_ae_iclass_mulfp24s_lh, 34935 0, 34936 Opcode_ae_mulfp24s_lh_encode_fns, 0, 0 }, 34937 { "ae_mulp24s.lh", ICLASS_ae_iclass_mulp24s_lh, 34938 0, 34939 Opcode_ae_mulp24s_lh_encode_fns, 0, 0 }, 34940 { "ae_mulfs32p16s.hl", ICLASS_ae_iclass_mulfs32p16s_hl, 34941 0, 34942 Opcode_ae_mulfs32p16s_hl_encode_fns, 0, 0 }, 34943 { "ae_mulfp24s.hl", ICLASS_ae_iclass_mulfp24s_hl, 34944 0, 34945 Opcode_ae_mulfp24s_hl_encode_fns, 0, 0 }, 34946 { "ae_mulp24s.hl", ICLASS_ae_iclass_mulp24s_hl, 34947 0, 34948 Opcode_ae_mulp24s_hl_encode_fns, 0, 0 }, 34949 { "ae_mulfs32p16s.hh", ICLASS_ae_iclass_mulfs32p16s_hh, 34950 0, 34951 Opcode_ae_mulfs32p16s_hh_encode_fns, 0, 0 }, 34952 { "ae_mulfp24s.hh", ICLASS_ae_iclass_mulfp24s_hh, 34953 0, 34954 Opcode_ae_mulfp24s_hh_encode_fns, 0, 0 }, 34955 { "ae_mulp24s.hh", ICLASS_ae_iclass_mulp24s_hh, 34956 0, 34957 Opcode_ae_mulp24s_hh_encode_fns, 0, 0 }, 34958 { "ae_mulafs32p16s.ll", ICLASS_ae_iclass_mulafs32p16s_ll, 34959 0, 34960 Opcode_ae_mulafs32p16s_ll_encode_fns, 0, 0 }, 34961 { "ae_mulafp24s.ll", ICLASS_ae_iclass_mulafp24s_ll, 34962 0, 34963 Opcode_ae_mulafp24s_ll_encode_fns, 0, 0 }, 34964 { "ae_mulap24s.ll", ICLASS_ae_iclass_mulap24s_ll, 34965 0, 34966 Opcode_ae_mulap24s_ll_encode_fns, 0, 0 }, 34967 { "ae_mulafs32p16s.lh", ICLASS_ae_iclass_mulafs32p16s_lh, 34968 0, 34969 Opcode_ae_mulafs32p16s_lh_encode_fns, 0, 0 }, 34970 { "ae_mulafp24s.lh", ICLASS_ae_iclass_mulafp24s_lh, 34971 0, 34972 Opcode_ae_mulafp24s_lh_encode_fns, 0, 0 }, 34973 { "ae_mulap24s.lh", ICLASS_ae_iclass_mulap24s_lh, 34974 0, 34975 Opcode_ae_mulap24s_lh_encode_fns, 0, 0 }, 34976 { "ae_mulafs32p16s.hl", ICLASS_ae_iclass_mulafs32p16s_hl, 34977 0, 34978 Opcode_ae_mulafs32p16s_hl_encode_fns, 0, 0 }, 34979 { "ae_mulafp24s.hl", ICLASS_ae_iclass_mulafp24s_hl, 34980 0, 34981 Opcode_ae_mulafp24s_hl_encode_fns, 0, 0 }, 34982 { "ae_mulap24s.hl", ICLASS_ae_iclass_mulap24s_hl, 34983 0, 34984 Opcode_ae_mulap24s_hl_encode_fns, 0, 0 }, 34985 { "ae_mulafs32p16s.hh", ICLASS_ae_iclass_mulafs32p16s_hh, 34986 0, 34987 Opcode_ae_mulafs32p16s_hh_encode_fns, 0, 0 }, 34988 { "ae_mulafp24s.hh", ICLASS_ae_iclass_mulafp24s_hh, 34989 0, 34990 Opcode_ae_mulafp24s_hh_encode_fns, 0, 0 }, 34991 { "ae_mulap24s.hh", ICLASS_ae_iclass_mulap24s_hh, 34992 0, 34993 Opcode_ae_mulap24s_hh_encode_fns, 0, 0 }, 34994 { "ae_mulsfs32p16s.ll", ICLASS_ae_iclass_mulsfs32p16s_ll, 34995 0, 34996 Opcode_ae_mulsfs32p16s_ll_encode_fns, 0, 0 }, 34997 { "ae_mulsfp24s.ll", ICLASS_ae_iclass_mulsfp24s_ll, 34998 0, 34999 Opcode_ae_mulsfp24s_ll_encode_fns, 0, 0 }, 35000 { "ae_mulsp24s.ll", ICLASS_ae_iclass_mulsp24s_ll, 35001 0, 35002 Opcode_ae_mulsp24s_ll_encode_fns, 0, 0 }, 35003 { "ae_mulsfs32p16s.lh", ICLASS_ae_iclass_mulsfs32p16s_lh, 35004 0, 35005 Opcode_ae_mulsfs32p16s_lh_encode_fns, 0, 0 }, 35006 { "ae_mulsfp24s.lh", ICLASS_ae_iclass_mulsfp24s_lh, 35007 0, 35008 Opcode_ae_mulsfp24s_lh_encode_fns, 0, 0 }, 35009 { "ae_mulsp24s.lh", ICLASS_ae_iclass_mulsp24s_lh, 35010 0, 35011 Opcode_ae_mulsp24s_lh_encode_fns, 0, 0 }, 35012 { "ae_mulsfs32p16s.hl", ICLASS_ae_iclass_mulsfs32p16s_hl, 35013 0, 35014 Opcode_ae_mulsfs32p16s_hl_encode_fns, 0, 0 }, 35015 { "ae_mulsfp24s.hl", ICLASS_ae_iclass_mulsfp24s_hl, 35016 0, 35017 Opcode_ae_mulsfp24s_hl_encode_fns, 0, 0 }, 35018 { "ae_mulsp24s.hl", ICLASS_ae_iclass_mulsp24s_hl, 35019 0, 35020 Opcode_ae_mulsp24s_hl_encode_fns, 0, 0 }, 35021 { "ae_mulsfs32p16s.hh", ICLASS_ae_iclass_mulsfs32p16s_hh, 35022 0, 35023 Opcode_ae_mulsfs32p16s_hh_encode_fns, 0, 0 }, 35024 { "ae_mulsfp24s.hh", ICLASS_ae_iclass_mulsfp24s_hh, 35025 0, 35026 Opcode_ae_mulsfp24s_hh_encode_fns, 0, 0 }, 35027 { "ae_mulsp24s.hh", ICLASS_ae_iclass_mulsp24s_hh, 35028 0, 35029 Opcode_ae_mulsp24s_hh_encode_fns, 0, 0 }, 35030 { "ae_mulafs56p24s.ll", ICLASS_ae_iclass_mulafs56p24s_ll, 35031 0, 35032 Opcode_ae_mulafs56p24s_ll_encode_fns, 0, 0 }, 35033 { "ae_mulas56p24s.ll", ICLASS_ae_iclass_mulas56p24s_ll, 35034 0, 35035 Opcode_ae_mulas56p24s_ll_encode_fns, 0, 0 }, 35036 { "ae_mulafs56p24s.lh", ICLASS_ae_iclass_mulafs56p24s_lh, 35037 0, 35038 Opcode_ae_mulafs56p24s_lh_encode_fns, 0, 0 }, 35039 { "ae_mulas56p24s.lh", ICLASS_ae_iclass_mulas56p24s_lh, 35040 0, 35041 Opcode_ae_mulas56p24s_lh_encode_fns, 0, 0 }, 35042 { "ae_mulafs56p24s.hl", ICLASS_ae_iclass_mulafs56p24s_hl, 35043 0, 35044 Opcode_ae_mulafs56p24s_hl_encode_fns, 0, 0 }, 35045 { "ae_mulas56p24s.hl", ICLASS_ae_iclass_mulas56p24s_hl, 35046 0, 35047 Opcode_ae_mulas56p24s_hl_encode_fns, 0, 0 }, 35048 { "ae_mulafs56p24s.hh", ICLASS_ae_iclass_mulafs56p24s_hh, 35049 0, 35050 Opcode_ae_mulafs56p24s_hh_encode_fns, 0, 0 }, 35051 { "ae_mulas56p24s.hh", ICLASS_ae_iclass_mulas56p24s_hh, 35052 0, 35053 Opcode_ae_mulas56p24s_hh_encode_fns, 0, 0 }, 35054 { "ae_mulsfs56p24s.ll", ICLASS_ae_iclass_mulsfs56p24s_ll, 35055 0, 35056 Opcode_ae_mulsfs56p24s_ll_encode_fns, 0, 0 }, 35057 { "ae_mulss56p24s.ll", ICLASS_ae_iclass_mulss56p24s_ll, 35058 0, 35059 Opcode_ae_mulss56p24s_ll_encode_fns, 0, 0 }, 35060 { "ae_mulsfs56p24s.lh", ICLASS_ae_iclass_mulsfs56p24s_lh, 35061 0, 35062 Opcode_ae_mulsfs56p24s_lh_encode_fns, 0, 0 }, 35063 { "ae_mulss56p24s.lh", ICLASS_ae_iclass_mulss56p24s_lh, 35064 0, 35065 Opcode_ae_mulss56p24s_lh_encode_fns, 0, 0 }, 35066 { "ae_mulsfs56p24s.hl", ICLASS_ae_iclass_mulsfs56p24s_hl, 35067 0, 35068 Opcode_ae_mulsfs56p24s_hl_encode_fns, 0, 0 }, 35069 { "ae_mulss56p24s.hl", ICLASS_ae_iclass_mulss56p24s_hl, 35070 0, 35071 Opcode_ae_mulss56p24s_hl_encode_fns, 0, 0 }, 35072 { "ae_mulsfs56p24s.hh", ICLASS_ae_iclass_mulsfs56p24s_hh, 35073 0, 35074 Opcode_ae_mulsfs56p24s_hh_encode_fns, 0, 0 }, 35075 { "ae_mulss56p24s.hh", ICLASS_ae_iclass_mulss56p24s_hh, 35076 0, 35077 Opcode_ae_mulss56p24s_hh_encode_fns, 0, 0 }, 35078 { "ae_mulfq32sp16s.l", ICLASS_ae_iclass_mulfq32sp16s_l, 35079 0, 35080 Opcode_ae_mulfq32sp16s_l_encode_fns, 0, 0 }, 35081 { "ae_mulfq32sp16s.h", ICLASS_ae_iclass_mulfq32sp16s_h, 35082 0, 35083 Opcode_ae_mulfq32sp16s_h_encode_fns, 0, 0 }, 35084 { "ae_mulfq32sp16u.l", ICLASS_ae_iclass_mulfq32sp16u_l, 35085 0, 35086 Opcode_ae_mulfq32sp16u_l_encode_fns, 0, 0 }, 35087 { "ae_mulfq32sp16u.h", ICLASS_ae_iclass_mulfq32sp16u_h, 35088 0, 35089 Opcode_ae_mulfq32sp16u_h_encode_fns, 0, 0 }, 35090 { "ae_mulq32sp16s.l", ICLASS_ae_iclass_mulq32sp16s_l, 35091 0, 35092 Opcode_ae_mulq32sp16s_l_encode_fns, 0, 0 }, 35093 { "ae_mulq32sp16s.h", ICLASS_ae_iclass_mulq32sp16s_h, 35094 0, 35095 Opcode_ae_mulq32sp16s_h_encode_fns, 0, 0 }, 35096 { "ae_mulq32sp16u.l", ICLASS_ae_iclass_mulq32sp16u_l, 35097 0, 35098 Opcode_ae_mulq32sp16u_l_encode_fns, 0, 0 }, 35099 { "ae_mulq32sp16u.h", ICLASS_ae_iclass_mulq32sp16u_h, 35100 0, 35101 Opcode_ae_mulq32sp16u_h_encode_fns, 0, 0 }, 35102 { "ae_mulafq32sp16s.l", ICLASS_ae_iclass_mulafq32sp16s_l, 35103 0, 35104 Opcode_ae_mulafq32sp16s_l_encode_fns, 0, 0 }, 35105 { "ae_mulafq32sp16s.h", ICLASS_ae_iclass_mulafq32sp16s_h, 35106 0, 35107 Opcode_ae_mulafq32sp16s_h_encode_fns, 0, 0 }, 35108 { "ae_mulafq32sp16u.l", ICLASS_ae_iclass_mulafq32sp16u_l, 35109 0, 35110 Opcode_ae_mulafq32sp16u_l_encode_fns, 0, 0 }, 35111 { "ae_mulafq32sp16u.h", ICLASS_ae_iclass_mulafq32sp16u_h, 35112 0, 35113 Opcode_ae_mulafq32sp16u_h_encode_fns, 0, 0 }, 35114 { "ae_mulaq32sp16s.l", ICLASS_ae_iclass_mulaq32sp16s_l, 35115 0, 35116 Opcode_ae_mulaq32sp16s_l_encode_fns, 0, 0 }, 35117 { "ae_mulaq32sp16s.h", ICLASS_ae_iclass_mulaq32sp16s_h, 35118 0, 35119 Opcode_ae_mulaq32sp16s_h_encode_fns, 0, 0 }, 35120 { "ae_mulaq32sp16u.l", ICLASS_ae_iclass_mulaq32sp16u_l, 35121 0, 35122 Opcode_ae_mulaq32sp16u_l_encode_fns, 0, 0 }, 35123 { "ae_mulaq32sp16u.h", ICLASS_ae_iclass_mulaq32sp16u_h, 35124 0, 35125 Opcode_ae_mulaq32sp16u_h_encode_fns, 0, 0 }, 35126 { "ae_mulsfq32sp16s.l", ICLASS_ae_iclass_mulsfq32sp16s_l, 35127 0, 35128 Opcode_ae_mulsfq32sp16s_l_encode_fns, 0, 0 }, 35129 { "ae_mulsfq32sp16s.h", ICLASS_ae_iclass_mulsfq32sp16s_h, 35130 0, 35131 Opcode_ae_mulsfq32sp16s_h_encode_fns, 0, 0 }, 35132 { "ae_mulsfq32sp16u.l", ICLASS_ae_iclass_mulsfq32sp16u_l, 35133 0, 35134 Opcode_ae_mulsfq32sp16u_l_encode_fns, 0, 0 }, 35135 { "ae_mulsfq32sp16u.h", ICLASS_ae_iclass_mulsfq32sp16u_h, 35136 0, 35137 Opcode_ae_mulsfq32sp16u_h_encode_fns, 0, 0 }, 35138 { "ae_mulsq32sp16s.l", ICLASS_ae_iclass_mulsq32sp16s_l, 35139 0, 35140 Opcode_ae_mulsq32sp16s_l_encode_fns, 0, 0 }, 35141 { "ae_mulsq32sp16s.h", ICLASS_ae_iclass_mulsq32sp16s_h, 35142 0, 35143 Opcode_ae_mulsq32sp16s_h_encode_fns, 0, 0 }, 35144 { "ae_mulsq32sp16u.l", ICLASS_ae_iclass_mulsq32sp16u_l, 35145 0, 35146 Opcode_ae_mulsq32sp16u_l_encode_fns, 0, 0 }, 35147 { "ae_mulsq32sp16u.h", ICLASS_ae_iclass_mulsq32sp16u_h, 35148 0, 35149 Opcode_ae_mulsq32sp16u_h_encode_fns, 0, 0 }, 35150 { "ae_mulzaaq32sp16s.ll", ICLASS_ae_iclass_mulzaaq32sp16s_ll, 35151 0, 35152 Opcode_ae_mulzaaq32sp16s_ll_encode_fns, 0, 0 }, 35153 { "ae_mulzaafq32sp16s.ll", ICLASS_ae_iclass_mulzaafq32sp16s_ll, 35154 0, 35155 Opcode_ae_mulzaafq32sp16s_ll_encode_fns, 0, 0 }, 35156 { "ae_mulzaaq32sp16u.ll", ICLASS_ae_iclass_mulzaaq32sp16u_ll, 35157 0, 35158 Opcode_ae_mulzaaq32sp16u_ll_encode_fns, 0, 0 }, 35159 { "ae_mulzaafq32sp16u.ll", ICLASS_ae_iclass_mulzaafq32sp16u_ll, 35160 0, 35161 Opcode_ae_mulzaafq32sp16u_ll_encode_fns, 0, 0 }, 35162 { "ae_mulzaaq32sp16s.hh", ICLASS_ae_iclass_mulzaaq32sp16s_hh, 35163 0, 35164 Opcode_ae_mulzaaq32sp16s_hh_encode_fns, 0, 0 }, 35165 { "ae_mulzaafq32sp16s.hh", ICLASS_ae_iclass_mulzaafq32sp16s_hh, 35166 0, 35167 Opcode_ae_mulzaafq32sp16s_hh_encode_fns, 0, 0 }, 35168 { "ae_mulzaaq32sp16u.hh", ICLASS_ae_iclass_mulzaaq32sp16u_hh, 35169 0, 35170 Opcode_ae_mulzaaq32sp16u_hh_encode_fns, 0, 0 }, 35171 { "ae_mulzaafq32sp16u.hh", ICLASS_ae_iclass_mulzaafq32sp16u_hh, 35172 0, 35173 Opcode_ae_mulzaafq32sp16u_hh_encode_fns, 0, 0 }, 35174 { "ae_mulzaaq32sp16s.lh", ICLASS_ae_iclass_mulzaaq32sp16s_lh, 35175 0, 35176 Opcode_ae_mulzaaq32sp16s_lh_encode_fns, 0, 0 }, 35177 { "ae_mulzaafq32sp16s.lh", ICLASS_ae_iclass_mulzaafq32sp16s_lh, 35178 0, 35179 Opcode_ae_mulzaafq32sp16s_lh_encode_fns, 0, 0 }, 35180 { "ae_mulzaaq32sp16u.lh", ICLASS_ae_iclass_mulzaaq32sp16u_lh, 35181 0, 35182 Opcode_ae_mulzaaq32sp16u_lh_encode_fns, 0, 0 }, 35183 { "ae_mulzaafq32sp16u.lh", ICLASS_ae_iclass_mulzaafq32sp16u_lh, 35184 0, 35185 Opcode_ae_mulzaafq32sp16u_lh_encode_fns, 0, 0 }, 35186 { "ae_mulzasq32sp16s.ll", ICLASS_ae_iclass_mulzasq32sp16s_ll, 35187 0, 35188 Opcode_ae_mulzasq32sp16s_ll_encode_fns, 0, 0 }, 35189 { "ae_mulzasfq32sp16s.ll", ICLASS_ae_iclass_mulzasfq32sp16s_ll, 35190 0, 35191 Opcode_ae_mulzasfq32sp16s_ll_encode_fns, 0, 0 }, 35192 { "ae_mulzasq32sp16u.ll", ICLASS_ae_iclass_mulzasq32sp16u_ll, 35193 0, 35194 Opcode_ae_mulzasq32sp16u_ll_encode_fns, 0, 0 }, 35195 { "ae_mulzasfq32sp16u.ll", ICLASS_ae_iclass_mulzasfq32sp16u_ll, 35196 0, 35197 Opcode_ae_mulzasfq32sp16u_ll_encode_fns, 0, 0 }, 35198 { "ae_mulzasq32sp16s.hh", ICLASS_ae_iclass_mulzasq32sp16s_hh, 35199 0, 35200 Opcode_ae_mulzasq32sp16s_hh_encode_fns, 0, 0 }, 35201 { "ae_mulzasfq32sp16s.hh", ICLASS_ae_iclass_mulzasfq32sp16s_hh, 35202 0, 35203 Opcode_ae_mulzasfq32sp16s_hh_encode_fns, 0, 0 }, 35204 { "ae_mulzasq32sp16u.hh", ICLASS_ae_iclass_mulzasq32sp16u_hh, 35205 0, 35206 Opcode_ae_mulzasq32sp16u_hh_encode_fns, 0, 0 }, 35207 { "ae_mulzasfq32sp16u.hh", ICLASS_ae_iclass_mulzasfq32sp16u_hh, 35208 0, 35209 Opcode_ae_mulzasfq32sp16u_hh_encode_fns, 0, 0 }, 35210 { "ae_mulzasq32sp16s.lh", ICLASS_ae_iclass_mulzasq32sp16s_lh, 35211 0, 35212 Opcode_ae_mulzasq32sp16s_lh_encode_fns, 0, 0 }, 35213 { "ae_mulzasfq32sp16s.lh", ICLASS_ae_iclass_mulzasfq32sp16s_lh, 35214 0, 35215 Opcode_ae_mulzasfq32sp16s_lh_encode_fns, 0, 0 }, 35216 { "ae_mulzasq32sp16u.lh", ICLASS_ae_iclass_mulzasq32sp16u_lh, 35217 0, 35218 Opcode_ae_mulzasq32sp16u_lh_encode_fns, 0, 0 }, 35219 { "ae_mulzasfq32sp16u.lh", ICLASS_ae_iclass_mulzasfq32sp16u_lh, 35220 0, 35221 Opcode_ae_mulzasfq32sp16u_lh_encode_fns, 0, 0 }, 35222 { "ae_mulzsaq32sp16s.ll", ICLASS_ae_iclass_mulzsaq32sp16s_ll, 35223 0, 35224 Opcode_ae_mulzsaq32sp16s_ll_encode_fns, 0, 0 }, 35225 { "ae_mulzsafq32sp16s.ll", ICLASS_ae_iclass_mulzsafq32sp16s_ll, 35226 0, 35227 Opcode_ae_mulzsafq32sp16s_ll_encode_fns, 0, 0 }, 35228 { "ae_mulzsaq32sp16u.ll", ICLASS_ae_iclass_mulzsaq32sp16u_ll, 35229 0, 35230 Opcode_ae_mulzsaq32sp16u_ll_encode_fns, 0, 0 }, 35231 { "ae_mulzsafq32sp16u.ll", ICLASS_ae_iclass_mulzsafq32sp16u_ll, 35232 0, 35233 Opcode_ae_mulzsafq32sp16u_ll_encode_fns, 0, 0 }, 35234 { "ae_mulzsaq32sp16s.hh", ICLASS_ae_iclass_mulzsaq32sp16s_hh, 35235 0, 35236 Opcode_ae_mulzsaq32sp16s_hh_encode_fns, 0, 0 }, 35237 { "ae_mulzsafq32sp16s.hh", ICLASS_ae_iclass_mulzsafq32sp16s_hh, 35238 0, 35239 Opcode_ae_mulzsafq32sp16s_hh_encode_fns, 0, 0 }, 35240 { "ae_mulzsaq32sp16u.hh", ICLASS_ae_iclass_mulzsaq32sp16u_hh, 35241 0, 35242 Opcode_ae_mulzsaq32sp16u_hh_encode_fns, 0, 0 }, 35243 { "ae_mulzsafq32sp16u.hh", ICLASS_ae_iclass_mulzsafq32sp16u_hh, 35244 0, 35245 Opcode_ae_mulzsafq32sp16u_hh_encode_fns, 0, 0 }, 35246 { "ae_mulzsaq32sp16s.lh", ICLASS_ae_iclass_mulzsaq32sp16s_lh, 35247 0, 35248 Opcode_ae_mulzsaq32sp16s_lh_encode_fns, 0, 0 }, 35249 { "ae_mulzsafq32sp16s.lh", ICLASS_ae_iclass_mulzsafq32sp16s_lh, 35250 0, 35251 Opcode_ae_mulzsafq32sp16s_lh_encode_fns, 0, 0 }, 35252 { "ae_mulzsaq32sp16u.lh", ICLASS_ae_iclass_mulzsaq32sp16u_lh, 35253 0, 35254 Opcode_ae_mulzsaq32sp16u_lh_encode_fns, 0, 0 }, 35255 { "ae_mulzsafq32sp16u.lh", ICLASS_ae_iclass_mulzsafq32sp16u_lh, 35256 0, 35257 Opcode_ae_mulzsafq32sp16u_lh_encode_fns, 0, 0 }, 35258 { "ae_mulzssq32sp16s.ll", ICLASS_ae_iclass_mulzssq32sp16s_ll, 35259 0, 35260 Opcode_ae_mulzssq32sp16s_ll_encode_fns, 0, 0 }, 35261 { "ae_mulzssfq32sp16s.ll", ICLASS_ae_iclass_mulzssfq32sp16s_ll, 35262 0, 35263 Opcode_ae_mulzssfq32sp16s_ll_encode_fns, 0, 0 }, 35264 { "ae_mulzssq32sp16u.ll", ICLASS_ae_iclass_mulzssq32sp16u_ll, 35265 0, 35266 Opcode_ae_mulzssq32sp16u_ll_encode_fns, 0, 0 }, 35267 { "ae_mulzssfq32sp16u.ll", ICLASS_ae_iclass_mulzssfq32sp16u_ll, 35268 0, 35269 Opcode_ae_mulzssfq32sp16u_ll_encode_fns, 0, 0 }, 35270 { "ae_mulzssq32sp16s.hh", ICLASS_ae_iclass_mulzssq32sp16s_hh, 35271 0, 35272 Opcode_ae_mulzssq32sp16s_hh_encode_fns, 0, 0 }, 35273 { "ae_mulzssfq32sp16s.hh", ICLASS_ae_iclass_mulzssfq32sp16s_hh, 35274 0, 35275 Opcode_ae_mulzssfq32sp16s_hh_encode_fns, 0, 0 }, 35276 { "ae_mulzssq32sp16u.hh", ICLASS_ae_iclass_mulzssq32sp16u_hh, 35277 0, 35278 Opcode_ae_mulzssq32sp16u_hh_encode_fns, 0, 0 }, 35279 { "ae_mulzssfq32sp16u.hh", ICLASS_ae_iclass_mulzssfq32sp16u_hh, 35280 0, 35281 Opcode_ae_mulzssfq32sp16u_hh_encode_fns, 0, 0 }, 35282 { "ae_mulzssq32sp16s.lh", ICLASS_ae_iclass_mulzssq32sp16s_lh, 35283 0, 35284 Opcode_ae_mulzssq32sp16s_lh_encode_fns, 0, 0 }, 35285 { "ae_mulzssfq32sp16s.lh", ICLASS_ae_iclass_mulzssfq32sp16s_lh, 35286 0, 35287 Opcode_ae_mulzssfq32sp16s_lh_encode_fns, 0, 0 }, 35288 { "ae_mulzssq32sp16u.lh", ICLASS_ae_iclass_mulzssq32sp16u_lh, 35289 0, 35290 Opcode_ae_mulzssq32sp16u_lh_encode_fns, 0, 0 }, 35291 { "ae_mulzssfq32sp16u.lh", ICLASS_ae_iclass_mulzssfq32sp16u_lh, 35292 0, 35293 Opcode_ae_mulzssfq32sp16u_lh_encode_fns, 0, 0 }, 35294 { "ae_mulzaafp24s.hh.ll", ICLASS_ae_iclass_mulzaafp24s_hh_ll, 35295 0, 35296 Opcode_ae_mulzaafp24s_hh_ll_encode_fns, 0, 0 }, 35297 { "ae_mulzaap24s.hh.ll", ICLASS_ae_iclass_mulzaap24s_hh_ll, 35298 0, 35299 Opcode_ae_mulzaap24s_hh_ll_encode_fns, 0, 0 }, 35300 { "ae_mulzaafp24s.hl.lh", ICLASS_ae_iclass_mulzaafp24s_hl_lh, 35301 0, 35302 Opcode_ae_mulzaafp24s_hl_lh_encode_fns, 0, 0 }, 35303 { "ae_mulzaap24s.hl.lh", ICLASS_ae_iclass_mulzaap24s_hl_lh, 35304 0, 35305 Opcode_ae_mulzaap24s_hl_lh_encode_fns, 0, 0 }, 35306 { "ae_mulzasfp24s.hh.ll", ICLASS_ae_iclass_mulzasfp24s_hh_ll, 35307 0, 35308 Opcode_ae_mulzasfp24s_hh_ll_encode_fns, 0, 0 }, 35309 { "ae_mulzasp24s.hh.ll", ICLASS_ae_iclass_mulzasp24s_hh_ll, 35310 0, 35311 Opcode_ae_mulzasp24s_hh_ll_encode_fns, 0, 0 }, 35312 { "ae_mulzasfp24s.hl.lh", ICLASS_ae_iclass_mulzasfp24s_hl_lh, 35313 0, 35314 Opcode_ae_mulzasfp24s_hl_lh_encode_fns, 0, 0 }, 35315 { "ae_mulzasp24s.hl.lh", ICLASS_ae_iclass_mulzasp24s_hl_lh, 35316 0, 35317 Opcode_ae_mulzasp24s_hl_lh_encode_fns, 0, 0 }, 35318 { "ae_mulzsafp24s.hh.ll", ICLASS_ae_iclass_mulzsafp24s_hh_ll, 35319 0, 35320 Opcode_ae_mulzsafp24s_hh_ll_encode_fns, 0, 0 }, 35321 { "ae_mulzsap24s.hh.ll", ICLASS_ae_iclass_mulzsap24s_hh_ll, 35322 0, 35323 Opcode_ae_mulzsap24s_hh_ll_encode_fns, 0, 0 }, 35324 { "ae_mulzsafp24s.hl.lh", ICLASS_ae_iclass_mulzsafp24s_hl_lh, 35325 0, 35326 Opcode_ae_mulzsafp24s_hl_lh_encode_fns, 0, 0 }, 35327 { "ae_mulzsap24s.hl.lh", ICLASS_ae_iclass_mulzsap24s_hl_lh, 35328 0, 35329 Opcode_ae_mulzsap24s_hl_lh_encode_fns, 0, 0 }, 35330 { "ae_mulzssfp24s.hh.ll", ICLASS_ae_iclass_mulzssfp24s_hh_ll, 35331 0, 35332 Opcode_ae_mulzssfp24s_hh_ll_encode_fns, 0, 0 }, 35333 { "ae_mulzssp24s.hh.ll", ICLASS_ae_iclass_mulzssp24s_hh_ll, 35334 0, 35335 Opcode_ae_mulzssp24s_hh_ll_encode_fns, 0, 0 }, 35336 { "ae_mulzssfp24s.hl.lh", ICLASS_ae_iclass_mulzssfp24s_hl_lh, 35337 0, 35338 Opcode_ae_mulzssfp24s_hl_lh_encode_fns, 0, 0 }, 35339 { "ae_mulzssp24s.hl.lh", ICLASS_ae_iclass_mulzssp24s_hl_lh, 35340 0, 35341 Opcode_ae_mulzssp24s_hl_lh_encode_fns, 0, 0 }, 35342 { "ae_mulaafp24s.hh.ll", ICLASS_ae_iclass_mulaafp24s_hh_ll, 35343 0, 35344 Opcode_ae_mulaafp24s_hh_ll_encode_fns, 0, 0 }, 35345 { "ae_mulaap24s.hh.ll", ICLASS_ae_iclass_mulaap24s_hh_ll, 35346 0, 35347 Opcode_ae_mulaap24s_hh_ll_encode_fns, 0, 0 }, 35348 { "ae_mulaafp24s.hl.lh", ICLASS_ae_iclass_mulaafp24s_hl_lh, 35349 0, 35350 Opcode_ae_mulaafp24s_hl_lh_encode_fns, 0, 0 }, 35351 { "ae_mulaap24s.hl.lh", ICLASS_ae_iclass_mulaap24s_hl_lh, 35352 0, 35353 Opcode_ae_mulaap24s_hl_lh_encode_fns, 0, 0 }, 35354 { "ae_mulasfp24s.hh.ll", ICLASS_ae_iclass_mulasfp24s_hh_ll, 35355 0, 35356 Opcode_ae_mulasfp24s_hh_ll_encode_fns, 0, 0 }, 35357 { "ae_mulasp24s.hh.ll", ICLASS_ae_iclass_mulasp24s_hh_ll, 35358 0, 35359 Opcode_ae_mulasp24s_hh_ll_encode_fns, 0, 0 }, 35360 { "ae_mulasfp24s.hl.lh", ICLASS_ae_iclass_mulasfp24s_hl_lh, 35361 0, 35362 Opcode_ae_mulasfp24s_hl_lh_encode_fns, 0, 0 }, 35363 { "ae_mulasp24s.hl.lh", ICLASS_ae_iclass_mulasp24s_hl_lh, 35364 0, 35365 Opcode_ae_mulasp24s_hl_lh_encode_fns, 0, 0 }, 35366 { "ae_mulsafp24s.hh.ll", ICLASS_ae_iclass_mulsafp24s_hh_ll, 35367 0, 35368 Opcode_ae_mulsafp24s_hh_ll_encode_fns, 0, 0 }, 35369 { "ae_mulsap24s.hh.ll", ICLASS_ae_iclass_mulsap24s_hh_ll, 35370 0, 35371 Opcode_ae_mulsap24s_hh_ll_encode_fns, 0, 0 }, 35372 { "ae_mulsafp24s.hl.lh", ICLASS_ae_iclass_mulsafp24s_hl_lh, 35373 0, 35374 Opcode_ae_mulsafp24s_hl_lh_encode_fns, 0, 0 }, 35375 { "ae_mulsap24s.hl.lh", ICLASS_ae_iclass_mulsap24s_hl_lh, 35376 0, 35377 Opcode_ae_mulsap24s_hl_lh_encode_fns, 0, 0 }, 35378 { "ae_mulssfp24s.hh.ll", ICLASS_ae_iclass_mulssfp24s_hh_ll, 35379 0, 35380 Opcode_ae_mulssfp24s_hh_ll_encode_fns, 0, 0 }, 35381 { "ae_mulssp24s.hh.ll", ICLASS_ae_iclass_mulssp24s_hh_ll, 35382 0, 35383 Opcode_ae_mulssp24s_hh_ll_encode_fns, 0, 0 }, 35384 { "ae_mulssfp24s.hl.lh", ICLASS_ae_iclass_mulssfp24s_hl_lh, 35385 0, 35386 Opcode_ae_mulssfp24s_hl_lh_encode_fns, 0, 0 }, 35387 { "ae_mulssp24s.hl.lh", ICLASS_ae_iclass_mulssp24s_hl_lh, 35388 0, 35389 Opcode_ae_mulssp24s_hl_lh_encode_fns, 0, 0 }, 35390 { "ae_sha32", ICLASS_ae_iclass_sha32, 35391 0, 35392 Opcode_ae_sha32_encode_fns, 0, 0 }, 35393 { "ae_vldl32t", ICLASS_ae_iclass_vldl32t, 35394 0, 35395 Opcode_ae_vldl32t_encode_fns, 1, Opcode_ae_vldl32t_funcUnit_uses }, 35396 { "ae_vldl16t", ICLASS_ae_iclass_vldl16t, 35397 0, 35398 Opcode_ae_vldl16t_encode_fns, 1, Opcode_ae_vldl16t_funcUnit_uses }, 35399 { "ae_vldl16c", ICLASS_ae_iclass_vldl16c, 35400 0, 35401 Opcode_ae_vldl16c_encode_fns, 3, Opcode_ae_vldl16c_funcUnit_uses }, 35402 { "ae_vldsht", ICLASS_ae_iclass_vldsht, 35403 0, 35404 Opcode_ae_vldsht_encode_fns, 3, Opcode_ae_vldsht_funcUnit_uses }, 35405 { "ae_lb", ICLASS_ae_iclass_lb, 35406 0, 35407 Opcode_ae_lb_encode_fns, 1, Opcode_ae_lb_funcUnit_uses }, 35408 { "ae_lbi", ICLASS_ae_iclass_lbi, 35409 0, 35410 Opcode_ae_lbi_encode_fns, 1, Opcode_ae_lbi_funcUnit_uses }, 35411 { "ae_lbk", ICLASS_ae_iclass_lbk, 35412 0, 35413 Opcode_ae_lbk_encode_fns, 1, Opcode_ae_lbk_funcUnit_uses }, 35414 { "ae_lbki", ICLASS_ae_iclass_lbki, 35415 0, 35416 Opcode_ae_lbki_encode_fns, 1, Opcode_ae_lbki_funcUnit_uses }, 35417 { "ae_db", ICLASS_ae_iclass_db, 35418 0, 35419 Opcode_ae_db_encode_fns, 2, Opcode_ae_db_funcUnit_uses }, 35420 { "ae_dbi", ICLASS_ae_iclass_dbi, 35421 0, 35422 Opcode_ae_dbi_encode_fns, 2, Opcode_ae_dbi_funcUnit_uses }, 35423 { "ae_vlel32t", ICLASS_ae_iclass_vlel32t, 35424 0, 35425 Opcode_ae_vlel32t_encode_fns, 1, Opcode_ae_vlel32t_funcUnit_uses }, 35426 { "ae_vlel16t", ICLASS_ae_iclass_vlel16t, 35427 0, 35428 Opcode_ae_vlel16t_encode_fns, 1, Opcode_ae_vlel16t_funcUnit_uses }, 35429 { "ae_sb", ICLASS_ae_iclass_sb, 35430 0, 35431 Opcode_ae_sb_encode_fns, 2, Opcode_ae_sb_funcUnit_uses }, 35432 { "ae_sbi", ICLASS_ae_iclass_sbi, 35433 0, 35434 Opcode_ae_sbi_encode_fns, 2, Opcode_ae_sbi_funcUnit_uses }, 35435 { "ae_vles16c", ICLASS_ae_iclass_vles16c, 35436 0, 35437 Opcode_ae_vles16c_encode_fns, 2, Opcode_ae_vles16c_funcUnit_uses }, 35438 { "ae_sbf", ICLASS_ae_iclass_sbf, 35439 0, 35440 Opcode_ae_sbf_encode_fns, 2, Opcode_ae_sbf_funcUnit_uses }, 35441 { "ae_slaasq56s", ICLASS_icls_AE_SLAASQ56S, 35442 0, 35443 Opcode_ae_slaasq56s_encode_fns, 0, 0 }, 35444 { "ae_addbrba32", ICLASS_icls_AE_ADDBRBA32, 35445 0, 35446 Opcode_ae_addbrba32_encode_fns, 0, 0 }, 35447 { "ae_minabssp24s", ICLASS_icls_AE_MINABSSP24S, 35448 0, 35449 Opcode_ae_minabssp24s_encode_fns, 0, 0 }, 35450 { "ae_maxabssp24s", ICLASS_icls_AE_MAXABSSP24S, 35451 0, 35452 Opcode_ae_maxabssp24s_encode_fns, 0, 0 }, 35453 { "ae_minabssq56s", ICLASS_icls_AE_MINABSSQ56S, 35454 0, 35455 Opcode_ae_minabssq56s_encode_fns, 0, 0 }, 35456 { "ae_maxabssq56s", ICLASS_icls_AE_MAXABSSQ56S, 35457 0, 35458 Opcode_ae_maxabssq56s_encode_fns, 0, 0 }, 35459 { "rur.ae_cbegin0", ICLASS_rur_ae_cbegin0, 35460 0, 35461 Opcode_rur_ae_cbegin0_encode_fns, 0, 0 }, 35462 { "wur.ae_cbegin0", ICLASS_wur_ae_cbegin0, 35463 0, 35464 Opcode_wur_ae_cbegin0_encode_fns, 0, 0 }, 35465 { "rur.ae_cend0", ICLASS_rur_ae_cend0, 35466 0, 35467 Opcode_rur_ae_cend0_encode_fns, 0, 0 }, 35468 { "wur.ae_cend0", ICLASS_wur_ae_cend0, 35469 0, 35470 Opcode_wur_ae_cend0_encode_fns, 0, 0 }, 35471 { "ae_lp24x2.c", ICLASS_icls_AE_LP24X2_C, 35472 0, 35473 Opcode_ae_lp24x2_c_encode_fns, 0, 0 }, 35474 { "ae_sp24x2s.c", ICLASS_icls_AE_SP24X2S_C, 35475 0, 35476 Opcode_ae_sp24x2s_c_encode_fns, 0, 0 }, 35477 { "ae_lp24x2f.c", ICLASS_icls_AE_LP24X2F_C, 35478 0, 35479 Opcode_ae_lp24x2f_c_encode_fns, 0, 0 }, 35480 { "ae_sp24x2f.c", ICLASS_icls_AE_SP24X2F_C, 35481 0, 35482 Opcode_ae_sp24x2f_c_encode_fns, 0, 0 }, 35483 { "ae_lp16x2f.c", ICLASS_icls_AE_LP16X2F_C, 35484 0, 35485 Opcode_ae_lp16x2f_c_encode_fns, 0, 0 }, 35486 { "ae_sp16x2f.c", ICLASS_icls_AE_SP16X2F_C, 35487 0, 35488 Opcode_ae_sp16x2f_c_encode_fns, 0, 0 }, 35489 { "ae_lp24.c", ICLASS_icls_AE_LP24_C, 35490 0, 35491 Opcode_ae_lp24_c_encode_fns, 0, 0 }, 35492 { "ae_sp24s.l.c", ICLASS_icls_AE_SP24S_L_C, 35493 0, 35494 Opcode_ae_sp24s_l_c_encode_fns, 0, 0 }, 35495 { "ae_lp24f.c", ICLASS_icls_AE_LP24F_C, 35496 0, 35497 Opcode_ae_lp24f_c_encode_fns, 0, 0 }, 35498 { "ae_sp24f.l.c", ICLASS_icls_AE_SP24F_L_C, 35499 0, 35500 Opcode_ae_sp24f_l_c_encode_fns, 0, 0 }, 35501 { "ae_lp16f.c", ICLASS_icls_AE_LP16F_C, 35502 0, 35503 Opcode_ae_lp16f_c_encode_fns, 0, 0 }, 35504 { "ae_sp16f.l.c", ICLASS_icls_AE_SP16F_L_C, 35505 0, 35506 Opcode_ae_sp16f_l_c_encode_fns, 0, 0 }, 35507 { "ae_lq56.c", ICLASS_icls_AE_LQ56_C, 35508 0, 35509 Opcode_ae_lq56_c_encode_fns, 0, 0 }, 35510 { "ae_sq56s.c", ICLASS_icls_AE_SQ56S_C, 35511 0, 35512 Opcode_ae_sq56s_c_encode_fns, 0, 0 }, 35513 { "ae_lq32f.c", ICLASS_icls_AE_LQ32F_C, 35514 0, 35515 Opcode_ae_lq32f_c_encode_fns, 0, 0 }, 35516 { "ae_sq32f.c", ICLASS_icls_AE_SQ32F_C, 35517 0, 35518 Opcode_ae_sq32f_c_encode_fns, 0, 0 }, 35519 { "rur.expstate", ICLASS_rur_expstate, 35520 0, 35521 Opcode_rur_expstate_encode_fns, 0, 0 }, 35522 { "wur.expstate", ICLASS_wur_expstate, 35523 0, 35524 Opcode_wur_expstate_encode_fns, 0, 0 }, 35525 { "read_impwire", ICLASS_iclass_READ_IMPWIRE, 35526 0, 35527 Opcode_read_impwire_encode_fns, 0, 0 }, 35528 { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE, 35529 0, 35530 Opcode_setb_expstate_encode_fns, 0, 0 }, 35531 { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE, 35532 0, 35533 Opcode_clrb_expstate_encode_fns, 0, 0 }, 35534 { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE, 35535 0, 35536 Opcode_wrmsk_expstate_encode_fns, 0, 0 } 35537 }; 35538 35539 enum xtensa_opcode_id { 35540 OPCODE_EXCW, 35541 OPCODE_RFE, 35542 OPCODE_RFDE, 35543 OPCODE_SYSCALL, 35544 OPCODE_CALL12, 35545 OPCODE_CALL8, 35546 OPCODE_CALL4, 35547 OPCODE_CALLX12, 35548 OPCODE_CALLX8, 35549 OPCODE_CALLX4, 35550 OPCODE_ENTRY, 35551 OPCODE_MOVSP, 35552 OPCODE_ROTW, 35553 OPCODE_RETW, 35554 OPCODE_RETW_N, 35555 OPCODE_RFWO, 35556 OPCODE_RFWU, 35557 OPCODE_L32E, 35558 OPCODE_S32E, 35559 OPCODE_RSR_WINDOWBASE, 35560 OPCODE_WSR_WINDOWBASE, 35561 OPCODE_XSR_WINDOWBASE, 35562 OPCODE_RSR_WINDOWSTART, 35563 OPCODE_WSR_WINDOWSTART, 35564 OPCODE_XSR_WINDOWSTART, 35565 OPCODE_ADD_N, 35566 OPCODE_ADDI_N, 35567 OPCODE_BEQZ_N, 35568 OPCODE_BNEZ_N, 35569 OPCODE_ILL_N, 35570 OPCODE_L32I_N, 35571 OPCODE_MOV_N, 35572 OPCODE_MOVI_N, 35573 OPCODE_NOP_N, 35574 OPCODE_RET_N, 35575 OPCODE_S32I_N, 35576 OPCODE_RUR_THREADPTR, 35577 OPCODE_WUR_THREADPTR, 35578 OPCODE_ADDI, 35579 OPCODE_ADDMI, 35580 OPCODE_ADD, 35581 OPCODE_SUB, 35582 OPCODE_ADDX2, 35583 OPCODE_ADDX4, 35584 OPCODE_ADDX8, 35585 OPCODE_SUBX2, 35586 OPCODE_SUBX4, 35587 OPCODE_SUBX8, 35588 OPCODE_AND, 35589 OPCODE_OR, 35590 OPCODE_XOR, 35591 OPCODE_BEQI, 35592 OPCODE_BNEI, 35593 OPCODE_BGEI, 35594 OPCODE_BLTI, 35595 OPCODE_BBCI, 35596 OPCODE_BBSI, 35597 OPCODE_BGEUI, 35598 OPCODE_BLTUI, 35599 OPCODE_BEQ, 35600 OPCODE_BNE, 35601 OPCODE_BGE, 35602 OPCODE_BLT, 35603 OPCODE_BGEU, 35604 OPCODE_BLTU, 35605 OPCODE_BANY, 35606 OPCODE_BNONE, 35607 OPCODE_BALL, 35608 OPCODE_BNALL, 35609 OPCODE_BBC, 35610 OPCODE_BBS, 35611 OPCODE_BEQZ, 35612 OPCODE_BNEZ, 35613 OPCODE_BGEZ, 35614 OPCODE_BLTZ, 35615 OPCODE_CALL0, 35616 OPCODE_CALLX0, 35617 OPCODE_EXTUI, 35618 OPCODE_ILL, 35619 OPCODE_J, 35620 OPCODE_JX, 35621 OPCODE_L16UI, 35622 OPCODE_L16SI, 35623 OPCODE_L32I, 35624 OPCODE_L32R, 35625 OPCODE_L8UI, 35626 OPCODE_LOOP, 35627 OPCODE_LOOPNEZ, 35628 OPCODE_LOOPGTZ, 35629 OPCODE_MOVI, 35630 OPCODE_MOVEQZ, 35631 OPCODE_MOVNEZ, 35632 OPCODE_MOVLTZ, 35633 OPCODE_MOVGEZ, 35634 OPCODE_NEG, 35635 OPCODE_ABS, 35636 OPCODE_NOP, 35637 OPCODE_RET, 35638 OPCODE_SIMCALL, 35639 OPCODE_S16I, 35640 OPCODE_S32I, 35641 OPCODE_S32NB, 35642 OPCODE_S8I, 35643 OPCODE_SSR, 35644 OPCODE_SSL, 35645 OPCODE_SSA8L, 35646 OPCODE_SSA8B, 35647 OPCODE_SSAI, 35648 OPCODE_SLL, 35649 OPCODE_SRC, 35650 OPCODE_SRL, 35651 OPCODE_SRA, 35652 OPCODE_SLLI, 35653 OPCODE_SRAI, 35654 OPCODE_SRLI, 35655 OPCODE_MEMW, 35656 OPCODE_EXTW, 35657 OPCODE_ISYNC, 35658 OPCODE_RSYNC, 35659 OPCODE_ESYNC, 35660 OPCODE_DSYNC, 35661 OPCODE_RSIL, 35662 OPCODE_RSR_LEND, 35663 OPCODE_WSR_LEND, 35664 OPCODE_XSR_LEND, 35665 OPCODE_RSR_LCOUNT, 35666 OPCODE_WSR_LCOUNT, 35667 OPCODE_XSR_LCOUNT, 35668 OPCODE_RSR_LBEG, 35669 OPCODE_WSR_LBEG, 35670 OPCODE_XSR_LBEG, 35671 OPCODE_RSR_SAR, 35672 OPCODE_WSR_SAR, 35673 OPCODE_XSR_SAR, 35674 OPCODE_RSR_MEMCTL, 35675 OPCODE_WSR_MEMCTL, 35676 OPCODE_XSR_MEMCTL, 35677 OPCODE_RSR_LITBASE, 35678 OPCODE_WSR_LITBASE, 35679 OPCODE_XSR_LITBASE, 35680 OPCODE_RSR_CONFIGID0, 35681 OPCODE_WSR_CONFIGID0, 35682 OPCODE_RSR_CONFIGID1, 35683 OPCODE_RSR_243, 35684 OPCODE_RSR_PS, 35685 OPCODE_WSR_PS, 35686 OPCODE_XSR_PS, 35687 OPCODE_RSR_EPC1, 35688 OPCODE_WSR_EPC1, 35689 OPCODE_XSR_EPC1, 35690 OPCODE_RSR_EXCSAVE1, 35691 OPCODE_WSR_EXCSAVE1, 35692 OPCODE_XSR_EXCSAVE1, 35693 OPCODE_RSR_EPC2, 35694 OPCODE_WSR_EPC2, 35695 OPCODE_XSR_EPC2, 35696 OPCODE_RSR_EXCSAVE2, 35697 OPCODE_WSR_EXCSAVE2, 35698 OPCODE_XSR_EXCSAVE2, 35699 OPCODE_RSR_EPC3, 35700 OPCODE_WSR_EPC3, 35701 OPCODE_XSR_EPC3, 35702 OPCODE_RSR_EXCSAVE3, 35703 OPCODE_WSR_EXCSAVE3, 35704 OPCODE_XSR_EXCSAVE3, 35705 OPCODE_RSR_EPC4, 35706 OPCODE_WSR_EPC4, 35707 OPCODE_XSR_EPC4, 35708 OPCODE_RSR_EXCSAVE4, 35709 OPCODE_WSR_EXCSAVE4, 35710 OPCODE_XSR_EXCSAVE4, 35711 OPCODE_RSR_EPC5, 35712 OPCODE_WSR_EPC5, 35713 OPCODE_XSR_EPC5, 35714 OPCODE_RSR_EXCSAVE5, 35715 OPCODE_WSR_EXCSAVE5, 35716 OPCODE_XSR_EXCSAVE5, 35717 OPCODE_RSR_EPC6, 35718 OPCODE_WSR_EPC6, 35719 OPCODE_XSR_EPC6, 35720 OPCODE_RSR_EXCSAVE6, 35721 OPCODE_WSR_EXCSAVE6, 35722 OPCODE_XSR_EXCSAVE6, 35723 OPCODE_RSR_EPC7, 35724 OPCODE_WSR_EPC7, 35725 OPCODE_XSR_EPC7, 35726 OPCODE_RSR_EXCSAVE7, 35727 OPCODE_WSR_EXCSAVE7, 35728 OPCODE_XSR_EXCSAVE7, 35729 OPCODE_RSR_EPS2, 35730 OPCODE_WSR_EPS2, 35731 OPCODE_XSR_EPS2, 35732 OPCODE_RSR_EPS3, 35733 OPCODE_WSR_EPS3, 35734 OPCODE_XSR_EPS3, 35735 OPCODE_RSR_EPS4, 35736 OPCODE_WSR_EPS4, 35737 OPCODE_XSR_EPS4, 35738 OPCODE_RSR_EPS5, 35739 OPCODE_WSR_EPS5, 35740 OPCODE_XSR_EPS5, 35741 OPCODE_RSR_EPS6, 35742 OPCODE_WSR_EPS6, 35743 OPCODE_XSR_EPS6, 35744 OPCODE_RSR_EPS7, 35745 OPCODE_WSR_EPS7, 35746 OPCODE_XSR_EPS7, 35747 OPCODE_RSR_EXCVADDR, 35748 OPCODE_WSR_EXCVADDR, 35749 OPCODE_XSR_EXCVADDR, 35750 OPCODE_RSR_DEPC, 35751 OPCODE_WSR_DEPC, 35752 OPCODE_XSR_DEPC, 35753 OPCODE_RSR_EXCCAUSE, 35754 OPCODE_WSR_EXCCAUSE, 35755 OPCODE_XSR_EXCCAUSE, 35756 OPCODE_RSR_MISC0, 35757 OPCODE_WSR_MISC0, 35758 OPCODE_XSR_MISC0, 35759 OPCODE_RSR_MISC1, 35760 OPCODE_WSR_MISC1, 35761 OPCODE_XSR_MISC1, 35762 OPCODE_RSR_PRID, 35763 OPCODE_RSR_VECBASE, 35764 OPCODE_WSR_VECBASE, 35765 OPCODE_XSR_VECBASE, 35766 OPCODE_MUL16U, 35767 OPCODE_MUL16S, 35768 OPCODE_MULL, 35769 OPCODE_MULUH, 35770 OPCODE_MULSH, 35771 OPCODE_MUL_AA_LL, 35772 OPCODE_MUL_AA_HL, 35773 OPCODE_MUL_AA_LH, 35774 OPCODE_MUL_AA_HH, 35775 OPCODE_UMUL_AA_LL, 35776 OPCODE_UMUL_AA_HL, 35777 OPCODE_UMUL_AA_LH, 35778 OPCODE_UMUL_AA_HH, 35779 OPCODE_MUL_AD_LL, 35780 OPCODE_MUL_AD_HL, 35781 OPCODE_MUL_AD_LH, 35782 OPCODE_MUL_AD_HH, 35783 OPCODE_MUL_DA_LL, 35784 OPCODE_MUL_DA_HL, 35785 OPCODE_MUL_DA_LH, 35786 OPCODE_MUL_DA_HH, 35787 OPCODE_MUL_DD_LL, 35788 OPCODE_MUL_DD_HL, 35789 OPCODE_MUL_DD_LH, 35790 OPCODE_MUL_DD_HH, 35791 OPCODE_MULA_AA_LL, 35792 OPCODE_MULA_AA_HL, 35793 OPCODE_MULA_AA_LH, 35794 OPCODE_MULA_AA_HH, 35795 OPCODE_MULS_AA_LL, 35796 OPCODE_MULS_AA_HL, 35797 OPCODE_MULS_AA_LH, 35798 OPCODE_MULS_AA_HH, 35799 OPCODE_MULA_AD_LL, 35800 OPCODE_MULA_AD_HL, 35801 OPCODE_MULA_AD_LH, 35802 OPCODE_MULA_AD_HH, 35803 OPCODE_MULS_AD_LL, 35804 OPCODE_MULS_AD_HL, 35805 OPCODE_MULS_AD_LH, 35806 OPCODE_MULS_AD_HH, 35807 OPCODE_MULA_DA_LL, 35808 OPCODE_MULA_DA_HL, 35809 OPCODE_MULA_DA_LH, 35810 OPCODE_MULA_DA_HH, 35811 OPCODE_MULS_DA_LL, 35812 OPCODE_MULS_DA_HL, 35813 OPCODE_MULS_DA_LH, 35814 OPCODE_MULS_DA_HH, 35815 OPCODE_MULA_DD_LL, 35816 OPCODE_MULA_DD_HL, 35817 OPCODE_MULA_DD_LH, 35818 OPCODE_MULA_DD_HH, 35819 OPCODE_MULS_DD_LL, 35820 OPCODE_MULS_DD_HL, 35821 OPCODE_MULS_DD_LH, 35822 OPCODE_MULS_DD_HH, 35823 OPCODE_MULA_DA_LL_LDDEC, 35824 OPCODE_MULA_DA_LL_LDINC, 35825 OPCODE_MULA_DA_HL_LDDEC, 35826 OPCODE_MULA_DA_HL_LDINC, 35827 OPCODE_MULA_DA_LH_LDDEC, 35828 OPCODE_MULA_DA_LH_LDINC, 35829 OPCODE_MULA_DA_HH_LDDEC, 35830 OPCODE_MULA_DA_HH_LDINC, 35831 OPCODE_MULA_DD_LL_LDDEC, 35832 OPCODE_MULA_DD_LL_LDINC, 35833 OPCODE_MULA_DD_HL_LDDEC, 35834 OPCODE_MULA_DD_HL_LDINC, 35835 OPCODE_MULA_DD_LH_LDDEC, 35836 OPCODE_MULA_DD_LH_LDINC, 35837 OPCODE_MULA_DD_HH_LDDEC, 35838 OPCODE_MULA_DD_HH_LDINC, 35839 OPCODE_LDDEC, 35840 OPCODE_LDINC, 35841 OPCODE_RSR_M0, 35842 OPCODE_WSR_M0, 35843 OPCODE_XSR_M0, 35844 OPCODE_RSR_M1, 35845 OPCODE_WSR_M1, 35846 OPCODE_XSR_M1, 35847 OPCODE_RSR_M2, 35848 OPCODE_WSR_M2, 35849 OPCODE_XSR_M2, 35850 OPCODE_RSR_M3, 35851 OPCODE_WSR_M3, 35852 OPCODE_XSR_M3, 35853 OPCODE_RSR_ACCLO, 35854 OPCODE_WSR_ACCLO, 35855 OPCODE_XSR_ACCLO, 35856 OPCODE_RSR_ACCHI, 35857 OPCODE_WSR_ACCHI, 35858 OPCODE_XSR_ACCHI, 35859 OPCODE_RFI, 35860 OPCODE_WAITI, 35861 OPCODE_RSR_INTERRUPT, 35862 OPCODE_WSR_INTSET, 35863 OPCODE_WSR_INTCLEAR, 35864 OPCODE_RSR_INTENABLE, 35865 OPCODE_WSR_INTENABLE, 35866 OPCODE_XSR_INTENABLE, 35867 OPCODE_BREAK, 35868 OPCODE_BREAK_N, 35869 OPCODE_RSR_DBREAKA0, 35870 OPCODE_WSR_DBREAKA0, 35871 OPCODE_XSR_DBREAKA0, 35872 OPCODE_RSR_DBREAKC0, 35873 OPCODE_WSR_DBREAKC0, 35874 OPCODE_XSR_DBREAKC0, 35875 OPCODE_RSR_DBREAKA1, 35876 OPCODE_WSR_DBREAKA1, 35877 OPCODE_XSR_DBREAKA1, 35878 OPCODE_RSR_DBREAKC1, 35879 OPCODE_WSR_DBREAKC1, 35880 OPCODE_XSR_DBREAKC1, 35881 OPCODE_RSR_IBREAKA0, 35882 OPCODE_WSR_IBREAKA0, 35883 OPCODE_XSR_IBREAKA0, 35884 OPCODE_RSR_IBREAKA1, 35885 OPCODE_WSR_IBREAKA1, 35886 OPCODE_XSR_IBREAKA1, 35887 OPCODE_RSR_IBREAKENABLE, 35888 OPCODE_WSR_IBREAKENABLE, 35889 OPCODE_XSR_IBREAKENABLE, 35890 OPCODE_RSR_DEBUGCAUSE, 35891 OPCODE_WSR_DEBUGCAUSE, 35892 OPCODE_XSR_DEBUGCAUSE, 35893 OPCODE_RSR_ICOUNT, 35894 OPCODE_WSR_ICOUNT, 35895 OPCODE_XSR_ICOUNT, 35896 OPCODE_RSR_ICOUNTLEVEL, 35897 OPCODE_WSR_ICOUNTLEVEL, 35898 OPCODE_XSR_ICOUNTLEVEL, 35899 OPCODE_RSR_DDR, 35900 OPCODE_WSR_DDR, 35901 OPCODE_XSR_DDR, 35902 OPCODE_LDDR32_P, 35903 OPCODE_SDDR32_P, 35904 OPCODE_RFDO, 35905 OPCODE_RFDD, 35906 OPCODE_WSR_MMID, 35907 OPCODE_ANDB, 35908 OPCODE_ANDBC, 35909 OPCODE_ORB, 35910 OPCODE_ORBC, 35911 OPCODE_XORB, 35912 OPCODE_ANY4, 35913 OPCODE_ALL4, 35914 OPCODE_ANY8, 35915 OPCODE_ALL8, 35916 OPCODE_BF, 35917 OPCODE_BT, 35918 OPCODE_MOVF, 35919 OPCODE_MOVT, 35920 OPCODE_RSR_BR, 35921 OPCODE_WSR_BR, 35922 OPCODE_XSR_BR, 35923 OPCODE_RSR_CCOUNT, 35924 OPCODE_WSR_CCOUNT, 35925 OPCODE_XSR_CCOUNT, 35926 OPCODE_RSR_CCOMPARE0, 35927 OPCODE_WSR_CCOMPARE0, 35928 OPCODE_XSR_CCOMPARE0, 35929 OPCODE_RSR_CCOMPARE1, 35930 OPCODE_WSR_CCOMPARE1, 35931 OPCODE_XSR_CCOMPARE1, 35932 OPCODE_RSR_CCOMPARE2, 35933 OPCODE_WSR_CCOMPARE2, 35934 OPCODE_XSR_CCOMPARE2, 35935 OPCODE_IPF, 35936 OPCODE_IHI, 35937 OPCODE_IPFL, 35938 OPCODE_IHU, 35939 OPCODE_IIU, 35940 OPCODE_III, 35941 OPCODE_LICT, 35942 OPCODE_LICW, 35943 OPCODE_SICT, 35944 OPCODE_SICW, 35945 OPCODE_DHWB, 35946 OPCODE_DHWBI, 35947 OPCODE_DIWBUI_P, 35948 OPCODE_DIWB, 35949 OPCODE_DIWBI, 35950 OPCODE_DHI, 35951 OPCODE_DII, 35952 OPCODE_DPFR, 35953 OPCODE_DPFW, 35954 OPCODE_DPFRO, 35955 OPCODE_DPFWO, 35956 OPCODE_DPFL, 35957 OPCODE_DHU, 35958 OPCODE_DIU, 35959 OPCODE_SDCT, 35960 OPCODE_LDCT, 35961 OPCODE_RSR_PREFCTL, 35962 OPCODE_WSR_PREFCTL, 35963 OPCODE_XSR_PREFCTL, 35964 OPCODE_WSR_PTEVADDR, 35965 OPCODE_RSR_PTEVADDR, 35966 OPCODE_XSR_PTEVADDR, 35967 OPCODE_RSR_RASID, 35968 OPCODE_WSR_RASID, 35969 OPCODE_XSR_RASID, 35970 OPCODE_RSR_ITLBCFG, 35971 OPCODE_WSR_ITLBCFG, 35972 OPCODE_XSR_ITLBCFG, 35973 OPCODE_RSR_DTLBCFG, 35974 OPCODE_WSR_DTLBCFG, 35975 OPCODE_XSR_DTLBCFG, 35976 OPCODE_IDTLB, 35977 OPCODE_PDTLB, 35978 OPCODE_RDTLB0, 35979 OPCODE_RDTLB1, 35980 OPCODE_WDTLB, 35981 OPCODE_IITLB, 35982 OPCODE_PITLB, 35983 OPCODE_RITLB0, 35984 OPCODE_RITLB1, 35985 OPCODE_WITLB, 35986 OPCODE_LDPTE, 35987 OPCODE_HWWITLBA, 35988 OPCODE_HWWDTLBA, 35989 OPCODE_RSR_CPENABLE, 35990 OPCODE_WSR_CPENABLE, 35991 OPCODE_XSR_CPENABLE, 35992 OPCODE_CLAMPS, 35993 OPCODE_MIN, 35994 OPCODE_MAX, 35995 OPCODE_MINU, 35996 OPCODE_MAXU, 35997 OPCODE_NSA, 35998 OPCODE_NSAU, 35999 OPCODE_SEXT, 36000 OPCODE_L32AI, 36001 OPCODE_S32RI, 36002 OPCODE_S32C1I, 36003 OPCODE_RSR_SCOMPARE1, 36004 OPCODE_WSR_SCOMPARE1, 36005 OPCODE_XSR_SCOMPARE1, 36006 OPCODE_RSR_ATOMCTL, 36007 OPCODE_WSR_ATOMCTL, 36008 OPCODE_XSR_ATOMCTL, 36009 OPCODE_QUOU, 36010 OPCODE_QUOS, 36011 OPCODE_REMU, 36012 OPCODE_REMS, 36013 OPCODE_RER, 36014 OPCODE_WER, 36015 OPCODE_RUR_AE_OVF_SAR, 36016 OPCODE_WUR_AE_OVF_SAR, 36017 OPCODE_RUR_AE_BITHEAD, 36018 OPCODE_WUR_AE_BITHEAD, 36019 OPCODE_RUR_AE_TS_FTS_BU_BP, 36020 OPCODE_WUR_AE_TS_FTS_BU_BP, 36021 OPCODE_RUR_AE_SD_NO, 36022 OPCODE_WUR_AE_SD_NO, 36023 OPCODE_RUR_AE_OVERFLOW, 36024 OPCODE_WUR_AE_OVERFLOW, 36025 OPCODE_RUR_AE_SAR, 36026 OPCODE_WUR_AE_SAR, 36027 OPCODE_RUR_AE_BITPTR, 36028 OPCODE_WUR_AE_BITPTR, 36029 OPCODE_RUR_AE_BITSUSED, 36030 OPCODE_WUR_AE_BITSUSED, 36031 OPCODE_RUR_AE_TABLESIZE, 36032 OPCODE_WUR_AE_TABLESIZE, 36033 OPCODE_RUR_AE_FIRST_TS, 36034 OPCODE_WUR_AE_FIRST_TS, 36035 OPCODE_RUR_AE_NEXTOFFSET, 36036 OPCODE_WUR_AE_NEXTOFFSET, 36037 OPCODE_RUR_AE_SEARCHDONE, 36038 OPCODE_WUR_AE_SEARCHDONE, 36039 OPCODE_AE_LP16F_I, 36040 OPCODE_AE_LP16F_IU, 36041 OPCODE_AE_LP16F_X, 36042 OPCODE_AE_LP16F_XU, 36043 OPCODE_AE_LP24_I, 36044 OPCODE_AE_LP24_IU, 36045 OPCODE_AE_LP24_X, 36046 OPCODE_AE_LP24_XU, 36047 OPCODE_AE_LP24F_I, 36048 OPCODE_AE_LP24F_IU, 36049 OPCODE_AE_LP24F_X, 36050 OPCODE_AE_LP24F_XU, 36051 OPCODE_AE_LP16X2F_I, 36052 OPCODE_AE_LP16X2F_IU, 36053 OPCODE_AE_LP16X2F_X, 36054 OPCODE_AE_LP16X2F_XU, 36055 OPCODE_AE_LP24X2F_I, 36056 OPCODE_AE_LP24X2F_IU, 36057 OPCODE_AE_LP24X2F_X, 36058 OPCODE_AE_LP24X2F_XU, 36059 OPCODE_AE_LP24X2_I, 36060 OPCODE_AE_LP24X2_IU, 36061 OPCODE_AE_LP24X2_X, 36062 OPCODE_AE_LP24X2_XU, 36063 OPCODE_AE_SP16X2F_I, 36064 OPCODE_AE_SP16X2F_IU, 36065 OPCODE_AE_SP16X2F_X, 36066 OPCODE_AE_SP16X2F_XU, 36067 OPCODE_AE_SP24X2S_I, 36068 OPCODE_AE_SP24X2S_IU, 36069 OPCODE_AE_SP24X2S_X, 36070 OPCODE_AE_SP24X2S_XU, 36071 OPCODE_AE_SP24X2F_I, 36072 OPCODE_AE_SP24X2F_IU, 36073 OPCODE_AE_SP24X2F_X, 36074 OPCODE_AE_SP24X2F_XU, 36075 OPCODE_AE_SP16F_L_I, 36076 OPCODE_AE_SP16F_L_IU, 36077 OPCODE_AE_SP16F_L_X, 36078 OPCODE_AE_SP16F_L_XU, 36079 OPCODE_AE_SP24S_L_I, 36080 OPCODE_AE_SP24S_L_IU, 36081 OPCODE_AE_SP24S_L_X, 36082 OPCODE_AE_SP24S_L_XU, 36083 OPCODE_AE_SP24F_L_I, 36084 OPCODE_AE_SP24F_L_IU, 36085 OPCODE_AE_SP24F_L_X, 36086 OPCODE_AE_SP24F_L_XU, 36087 OPCODE_AE_LQ56_I, 36088 OPCODE_AE_LQ56_IU, 36089 OPCODE_AE_LQ56_X, 36090 OPCODE_AE_LQ56_XU, 36091 OPCODE_AE_LQ32F_I, 36092 OPCODE_AE_LQ32F_IU, 36093 OPCODE_AE_LQ32F_X, 36094 OPCODE_AE_LQ32F_XU, 36095 OPCODE_AE_SQ56S_I, 36096 OPCODE_AE_SQ56S_IU, 36097 OPCODE_AE_SQ56S_X, 36098 OPCODE_AE_SQ56S_XU, 36099 OPCODE_AE_SQ32F_I, 36100 OPCODE_AE_SQ32F_IU, 36101 OPCODE_AE_SQ32F_X, 36102 OPCODE_AE_SQ32F_XU, 36103 OPCODE_AE_ZEROP48, 36104 OPCODE_AE_MOVP48, 36105 OPCODE_AE_SELP24_LL, 36106 OPCODE_AE_SELP24_LH, 36107 OPCODE_AE_SELP24_HL, 36108 OPCODE_AE_SELP24_HH, 36109 OPCODE_AE_MOVTP24X2, 36110 OPCODE_AE_MOVFP24X2, 36111 OPCODE_AE_MOVTP48, 36112 OPCODE_AE_MOVFP48, 36113 OPCODE_AE_MOVPA24X2, 36114 OPCODE_AE_TRUNCP24A32X2, 36115 OPCODE_AE_CVTA32P24_L, 36116 OPCODE_AE_CVTA32P24_H, 36117 OPCODE_AE_CVTP24A16X2_LL, 36118 OPCODE_AE_CVTP24A16X2_LH, 36119 OPCODE_AE_CVTP24A16X2_HL, 36120 OPCODE_AE_CVTP24A16X2_HH, 36121 OPCODE_AE_TRUNCP24Q48X2, 36122 OPCODE_AE_TRUNCP16, 36123 OPCODE_AE_ROUNDSP24Q48SYM, 36124 OPCODE_AE_ROUNDSP24Q48ASYM, 36125 OPCODE_AE_ROUNDSP16Q48SYM, 36126 OPCODE_AE_ROUNDSP16Q48ASYM, 36127 OPCODE_AE_ROUNDSP16SYM, 36128 OPCODE_AE_ROUNDSP16ASYM, 36129 OPCODE_AE_ZEROQ56, 36130 OPCODE_AE_MOVQ56, 36131 OPCODE_AE_MOVTQ56, 36132 OPCODE_AE_MOVFQ56, 36133 OPCODE_AE_CVTQ48A32S, 36134 OPCODE_AE_CVTQ48P24S_L, 36135 OPCODE_AE_CVTQ48P24S_H, 36136 OPCODE_AE_SATQ48S, 36137 OPCODE_AE_TRUNCQ32, 36138 OPCODE_AE_ROUNDSQ32SYM, 36139 OPCODE_AE_ROUNDSQ32ASYM, 36140 OPCODE_AE_TRUNCA32Q48, 36141 OPCODE_AE_MOVAP24S_L, 36142 OPCODE_AE_MOVAP24S_H, 36143 OPCODE_AE_TRUNCA16P24S_L, 36144 OPCODE_AE_TRUNCA16P24S_H, 36145 OPCODE_AE_ADDP24, 36146 OPCODE_AE_SUBP24, 36147 OPCODE_AE_NEGP24, 36148 OPCODE_AE_ABSP24, 36149 OPCODE_AE_MAXP24S, 36150 OPCODE_AE_MINP24S, 36151 OPCODE_AE_MAXBP24S, 36152 OPCODE_AE_MINBP24S, 36153 OPCODE_AE_ADDSP24S, 36154 OPCODE_AE_SUBSP24S, 36155 OPCODE_AE_NEGSP24S, 36156 OPCODE_AE_ABSSP24S, 36157 OPCODE_AE_ANDP48, 36158 OPCODE_AE_NANDP48, 36159 OPCODE_AE_ORP48, 36160 OPCODE_AE_XORP48, 36161 OPCODE_AE_LTP24S, 36162 OPCODE_AE_LEP24S, 36163 OPCODE_AE_EQP24, 36164 OPCODE_AE_ADDQ56, 36165 OPCODE_AE_SUBQ56, 36166 OPCODE_AE_NEGQ56, 36167 OPCODE_AE_ABSQ56, 36168 OPCODE_AE_MAXQ56S, 36169 OPCODE_AE_MINQ56S, 36170 OPCODE_AE_MAXBQ56S, 36171 OPCODE_AE_MINBQ56S, 36172 OPCODE_AE_ADDSQ56S, 36173 OPCODE_AE_SUBSQ56S, 36174 OPCODE_AE_NEGSQ56S, 36175 OPCODE_AE_ABSSQ56S, 36176 OPCODE_AE_ANDQ56, 36177 OPCODE_AE_NANDQ56, 36178 OPCODE_AE_ORQ56, 36179 OPCODE_AE_XORQ56, 36180 OPCODE_AE_SLLIP24, 36181 OPCODE_AE_SRLIP24, 36182 OPCODE_AE_SRAIP24, 36183 OPCODE_AE_SLLSP24, 36184 OPCODE_AE_SRLSP24, 36185 OPCODE_AE_SRASP24, 36186 OPCODE_AE_SLLISP24S, 36187 OPCODE_AE_SLLSSP24S, 36188 OPCODE_AE_SLLIQ56, 36189 OPCODE_AE_SRLIQ56, 36190 OPCODE_AE_SRAIQ56, 36191 OPCODE_AE_SLLSQ56, 36192 OPCODE_AE_SRLSQ56, 36193 OPCODE_AE_SRASQ56, 36194 OPCODE_AE_SLLAQ56, 36195 OPCODE_AE_SRLAQ56, 36196 OPCODE_AE_SRAAQ56, 36197 OPCODE_AE_SLLISQ56S, 36198 OPCODE_AE_SLLSSQ56S, 36199 OPCODE_AE_SLLASQ56S, 36200 OPCODE_AE_LTQ56S, 36201 OPCODE_AE_LEQ56S, 36202 OPCODE_AE_EQQ56, 36203 OPCODE_AE_NSAQ56S, 36204 OPCODE_AE_MULSRFQ32SP24S_H, 36205 OPCODE_AE_MULSRFQ32SP24S_L, 36206 OPCODE_AE_MULARFQ32SP24S_H, 36207 OPCODE_AE_MULARFQ32SP24S_L, 36208 OPCODE_AE_MULRFQ32SP24S_H, 36209 OPCODE_AE_MULRFQ32SP24S_L, 36210 OPCODE_AE_MULSFQ32SP24S_H, 36211 OPCODE_AE_MULSFQ32SP24S_L, 36212 OPCODE_AE_MULAFQ32SP24S_H, 36213 OPCODE_AE_MULAFQ32SP24S_L, 36214 OPCODE_AE_MULFQ32SP24S_H, 36215 OPCODE_AE_MULFQ32SP24S_L, 36216 OPCODE_AE_MULFS32P16S_LL, 36217 OPCODE_AE_MULFP24S_LL, 36218 OPCODE_AE_MULP24S_LL, 36219 OPCODE_AE_MULFS32P16S_LH, 36220 OPCODE_AE_MULFP24S_LH, 36221 OPCODE_AE_MULP24S_LH, 36222 OPCODE_AE_MULFS32P16S_HL, 36223 OPCODE_AE_MULFP24S_HL, 36224 OPCODE_AE_MULP24S_HL, 36225 OPCODE_AE_MULFS32P16S_HH, 36226 OPCODE_AE_MULFP24S_HH, 36227 OPCODE_AE_MULP24S_HH, 36228 OPCODE_AE_MULAFS32P16S_LL, 36229 OPCODE_AE_MULAFP24S_LL, 36230 OPCODE_AE_MULAP24S_LL, 36231 OPCODE_AE_MULAFS32P16S_LH, 36232 OPCODE_AE_MULAFP24S_LH, 36233 OPCODE_AE_MULAP24S_LH, 36234 OPCODE_AE_MULAFS32P16S_HL, 36235 OPCODE_AE_MULAFP24S_HL, 36236 OPCODE_AE_MULAP24S_HL, 36237 OPCODE_AE_MULAFS32P16S_HH, 36238 OPCODE_AE_MULAFP24S_HH, 36239 OPCODE_AE_MULAP24S_HH, 36240 OPCODE_AE_MULSFS32P16S_LL, 36241 OPCODE_AE_MULSFP24S_LL, 36242 OPCODE_AE_MULSP24S_LL, 36243 OPCODE_AE_MULSFS32P16S_LH, 36244 OPCODE_AE_MULSFP24S_LH, 36245 OPCODE_AE_MULSP24S_LH, 36246 OPCODE_AE_MULSFS32P16S_HL, 36247 OPCODE_AE_MULSFP24S_HL, 36248 OPCODE_AE_MULSP24S_HL, 36249 OPCODE_AE_MULSFS32P16S_HH, 36250 OPCODE_AE_MULSFP24S_HH, 36251 OPCODE_AE_MULSP24S_HH, 36252 OPCODE_AE_MULAFS56P24S_LL, 36253 OPCODE_AE_MULAS56P24S_LL, 36254 OPCODE_AE_MULAFS56P24S_LH, 36255 OPCODE_AE_MULAS56P24S_LH, 36256 OPCODE_AE_MULAFS56P24S_HL, 36257 OPCODE_AE_MULAS56P24S_HL, 36258 OPCODE_AE_MULAFS56P24S_HH, 36259 OPCODE_AE_MULAS56P24S_HH, 36260 OPCODE_AE_MULSFS56P24S_LL, 36261 OPCODE_AE_MULSS56P24S_LL, 36262 OPCODE_AE_MULSFS56P24S_LH, 36263 OPCODE_AE_MULSS56P24S_LH, 36264 OPCODE_AE_MULSFS56P24S_HL, 36265 OPCODE_AE_MULSS56P24S_HL, 36266 OPCODE_AE_MULSFS56P24S_HH, 36267 OPCODE_AE_MULSS56P24S_HH, 36268 OPCODE_AE_MULFQ32SP16S_L, 36269 OPCODE_AE_MULFQ32SP16S_H, 36270 OPCODE_AE_MULFQ32SP16U_L, 36271 OPCODE_AE_MULFQ32SP16U_H, 36272 OPCODE_AE_MULQ32SP16S_L, 36273 OPCODE_AE_MULQ32SP16S_H, 36274 OPCODE_AE_MULQ32SP16U_L, 36275 OPCODE_AE_MULQ32SP16U_H, 36276 OPCODE_AE_MULAFQ32SP16S_L, 36277 OPCODE_AE_MULAFQ32SP16S_H, 36278 OPCODE_AE_MULAFQ32SP16U_L, 36279 OPCODE_AE_MULAFQ32SP16U_H, 36280 OPCODE_AE_MULAQ32SP16S_L, 36281 OPCODE_AE_MULAQ32SP16S_H, 36282 OPCODE_AE_MULAQ32SP16U_L, 36283 OPCODE_AE_MULAQ32SP16U_H, 36284 OPCODE_AE_MULSFQ32SP16S_L, 36285 OPCODE_AE_MULSFQ32SP16S_H, 36286 OPCODE_AE_MULSFQ32SP16U_L, 36287 OPCODE_AE_MULSFQ32SP16U_H, 36288 OPCODE_AE_MULSQ32SP16S_L, 36289 OPCODE_AE_MULSQ32SP16S_H, 36290 OPCODE_AE_MULSQ32SP16U_L, 36291 OPCODE_AE_MULSQ32SP16U_H, 36292 OPCODE_AE_MULZAAQ32SP16S_LL, 36293 OPCODE_AE_MULZAAFQ32SP16S_LL, 36294 OPCODE_AE_MULZAAQ32SP16U_LL, 36295 OPCODE_AE_MULZAAFQ32SP16U_LL, 36296 OPCODE_AE_MULZAAQ32SP16S_HH, 36297 OPCODE_AE_MULZAAFQ32SP16S_HH, 36298 OPCODE_AE_MULZAAQ32SP16U_HH, 36299 OPCODE_AE_MULZAAFQ32SP16U_HH, 36300 OPCODE_AE_MULZAAQ32SP16S_LH, 36301 OPCODE_AE_MULZAAFQ32SP16S_LH, 36302 OPCODE_AE_MULZAAQ32SP16U_LH, 36303 OPCODE_AE_MULZAAFQ32SP16U_LH, 36304 OPCODE_AE_MULZASQ32SP16S_LL, 36305 OPCODE_AE_MULZASFQ32SP16S_LL, 36306 OPCODE_AE_MULZASQ32SP16U_LL, 36307 OPCODE_AE_MULZASFQ32SP16U_LL, 36308 OPCODE_AE_MULZASQ32SP16S_HH, 36309 OPCODE_AE_MULZASFQ32SP16S_HH, 36310 OPCODE_AE_MULZASQ32SP16U_HH, 36311 OPCODE_AE_MULZASFQ32SP16U_HH, 36312 OPCODE_AE_MULZASQ32SP16S_LH, 36313 OPCODE_AE_MULZASFQ32SP16S_LH, 36314 OPCODE_AE_MULZASQ32SP16U_LH, 36315 OPCODE_AE_MULZASFQ32SP16U_LH, 36316 OPCODE_AE_MULZSAQ32SP16S_LL, 36317 OPCODE_AE_MULZSAFQ32SP16S_LL, 36318 OPCODE_AE_MULZSAQ32SP16U_LL, 36319 OPCODE_AE_MULZSAFQ32SP16U_LL, 36320 OPCODE_AE_MULZSAQ32SP16S_HH, 36321 OPCODE_AE_MULZSAFQ32SP16S_HH, 36322 OPCODE_AE_MULZSAQ32SP16U_HH, 36323 OPCODE_AE_MULZSAFQ32SP16U_HH, 36324 OPCODE_AE_MULZSAQ32SP16S_LH, 36325 OPCODE_AE_MULZSAFQ32SP16S_LH, 36326 OPCODE_AE_MULZSAQ32SP16U_LH, 36327 OPCODE_AE_MULZSAFQ32SP16U_LH, 36328 OPCODE_AE_MULZSSQ32SP16S_LL, 36329 OPCODE_AE_MULZSSFQ32SP16S_LL, 36330 OPCODE_AE_MULZSSQ32SP16U_LL, 36331 OPCODE_AE_MULZSSFQ32SP16U_LL, 36332 OPCODE_AE_MULZSSQ32SP16S_HH, 36333 OPCODE_AE_MULZSSFQ32SP16S_HH, 36334 OPCODE_AE_MULZSSQ32SP16U_HH, 36335 OPCODE_AE_MULZSSFQ32SP16U_HH, 36336 OPCODE_AE_MULZSSQ32SP16S_LH, 36337 OPCODE_AE_MULZSSFQ32SP16S_LH, 36338 OPCODE_AE_MULZSSQ32SP16U_LH, 36339 OPCODE_AE_MULZSSFQ32SP16U_LH, 36340 OPCODE_AE_MULZAAFP24S_HH_LL, 36341 OPCODE_AE_MULZAAP24S_HH_LL, 36342 OPCODE_AE_MULZAAFP24S_HL_LH, 36343 OPCODE_AE_MULZAAP24S_HL_LH, 36344 OPCODE_AE_MULZASFP24S_HH_LL, 36345 OPCODE_AE_MULZASP24S_HH_LL, 36346 OPCODE_AE_MULZASFP24S_HL_LH, 36347 OPCODE_AE_MULZASP24S_HL_LH, 36348 OPCODE_AE_MULZSAFP24S_HH_LL, 36349 OPCODE_AE_MULZSAP24S_HH_LL, 36350 OPCODE_AE_MULZSAFP24S_HL_LH, 36351 OPCODE_AE_MULZSAP24S_HL_LH, 36352 OPCODE_AE_MULZSSFP24S_HH_LL, 36353 OPCODE_AE_MULZSSP24S_HH_LL, 36354 OPCODE_AE_MULZSSFP24S_HL_LH, 36355 OPCODE_AE_MULZSSP24S_HL_LH, 36356 OPCODE_AE_MULAAFP24S_HH_LL, 36357 OPCODE_AE_MULAAP24S_HH_LL, 36358 OPCODE_AE_MULAAFP24S_HL_LH, 36359 OPCODE_AE_MULAAP24S_HL_LH, 36360 OPCODE_AE_MULASFP24S_HH_LL, 36361 OPCODE_AE_MULASP24S_HH_LL, 36362 OPCODE_AE_MULASFP24S_HL_LH, 36363 OPCODE_AE_MULASP24S_HL_LH, 36364 OPCODE_AE_MULSAFP24S_HH_LL, 36365 OPCODE_AE_MULSAP24S_HH_LL, 36366 OPCODE_AE_MULSAFP24S_HL_LH, 36367 OPCODE_AE_MULSAP24S_HL_LH, 36368 OPCODE_AE_MULSSFP24S_HH_LL, 36369 OPCODE_AE_MULSSP24S_HH_LL, 36370 OPCODE_AE_MULSSFP24S_HL_LH, 36371 OPCODE_AE_MULSSP24S_HL_LH, 36372 OPCODE_AE_SHA32, 36373 OPCODE_AE_VLDL32T, 36374 OPCODE_AE_VLDL16T, 36375 OPCODE_AE_VLDL16C, 36376 OPCODE_AE_VLDSHT, 36377 OPCODE_AE_LB, 36378 OPCODE_AE_LBI, 36379 OPCODE_AE_LBK, 36380 OPCODE_AE_LBKI, 36381 OPCODE_AE_DB, 36382 OPCODE_AE_DBI, 36383 OPCODE_AE_VLEL32T, 36384 OPCODE_AE_VLEL16T, 36385 OPCODE_AE_SB, 36386 OPCODE_AE_SBI, 36387 OPCODE_AE_VLES16C, 36388 OPCODE_AE_SBF, 36389 OPCODE_AE_SLAASQ56S, 36390 OPCODE_AE_ADDBRBA32, 36391 OPCODE_AE_MINABSSP24S, 36392 OPCODE_AE_MAXABSSP24S, 36393 OPCODE_AE_MINABSSQ56S, 36394 OPCODE_AE_MAXABSSQ56S, 36395 OPCODE_RUR_AE_CBEGIN0, 36396 OPCODE_WUR_AE_CBEGIN0, 36397 OPCODE_RUR_AE_CEND0, 36398 OPCODE_WUR_AE_CEND0, 36399 OPCODE_AE_LP24X2_C, 36400 OPCODE_AE_SP24X2S_C, 36401 OPCODE_AE_LP24X2F_C, 36402 OPCODE_AE_SP24X2F_C, 36403 OPCODE_AE_LP16X2F_C, 36404 OPCODE_AE_SP16X2F_C, 36405 OPCODE_AE_LP24_C, 36406 OPCODE_AE_SP24S_L_C, 36407 OPCODE_AE_LP24F_C, 36408 OPCODE_AE_SP24F_L_C, 36409 OPCODE_AE_LP16F_C, 36410 OPCODE_AE_SP16F_L_C, 36411 OPCODE_AE_LQ56_C, 36412 OPCODE_AE_SQ56S_C, 36413 OPCODE_AE_LQ32F_C, 36414 OPCODE_AE_SQ32F_C, 36415 OPCODE_RUR_EXPSTATE, 36416 OPCODE_WUR_EXPSTATE, 36417 OPCODE_READ_IMPWIRE, 36418 OPCODE_SETB_EXPSTATE, 36419 OPCODE_CLRB_EXPSTATE, 36420 OPCODE_WRMSK_EXPSTATE 36421 }; 36422 36423 36424 /* Slot-specific opcode decode functions. */ 36425 36426 static int 36427 Slot_inst_decode (const xtensa_insnbuf insn) 36428 { 36429 if (Field_op0_Slot_inst_get (insn) == 0) 36430 { 36431 if (Field_op1_Slot_inst_get (insn) == 0) 36432 { 36433 if (Field_op2_Slot_inst_get (insn) == 0) 36434 { 36435 if (Field_r_Slot_inst_get (insn) == 0) 36436 { 36437 if (Field_m_Slot_inst_get (insn) == 0 && 36438 Field_s_Slot_inst_get (insn) == 0 && 36439 Field_n_Slot_inst_get (insn) == 0) 36440 return OPCODE_ILL; 36441 if (Field_m_Slot_inst_get (insn) == 2) 36442 { 36443 if (Field_n_Slot_inst_get (insn) == 0) 36444 return OPCODE_RET; 36445 if (Field_n_Slot_inst_get (insn) == 1) 36446 return OPCODE_RETW; 36447 if (Field_n_Slot_inst_get (insn) == 2) 36448 return OPCODE_JX; 36449 } 36450 if (Field_m_Slot_inst_get (insn) == 3) 36451 { 36452 if (Field_n_Slot_inst_get (insn) == 0) 36453 return OPCODE_CALLX0; 36454 if (Field_n_Slot_inst_get (insn) == 1) 36455 return OPCODE_CALLX4; 36456 if (Field_n_Slot_inst_get (insn) == 2) 36457 return OPCODE_CALLX8; 36458 if (Field_n_Slot_inst_get (insn) == 3) 36459 return OPCODE_CALLX12; 36460 } 36461 } 36462 if (Field_r_Slot_inst_get (insn) == 1) 36463 return OPCODE_MOVSP; 36464 if (Field_r_Slot_inst_get (insn) == 2) 36465 { 36466 if (Field_s_Slot_inst_get (insn) == 0) 36467 { 36468 if (Field_t_Slot_inst_get (insn) == 0) 36469 return OPCODE_ISYNC; 36470 if (Field_t_Slot_inst_get (insn) == 1) 36471 return OPCODE_RSYNC; 36472 if (Field_t_Slot_inst_get (insn) == 2) 36473 return OPCODE_ESYNC; 36474 if (Field_t_Slot_inst_get (insn) == 3) 36475 return OPCODE_DSYNC; 36476 if (Field_t_Slot_inst_get (insn) == 8) 36477 return OPCODE_EXCW; 36478 if (Field_t_Slot_inst_get (insn) == 12) 36479 return OPCODE_MEMW; 36480 if (Field_t_Slot_inst_get (insn) == 13) 36481 return OPCODE_EXTW; 36482 if (Field_t_Slot_inst_get (insn) == 15) 36483 return OPCODE_NOP; 36484 } 36485 } 36486 if (Field_r_Slot_inst_get (insn) == 3) 36487 { 36488 if (Field_t_Slot_inst_get (insn) == 0) 36489 { 36490 if (Field_s_Slot_inst_get (insn) == 0) 36491 return OPCODE_RFE; 36492 if (Field_s_Slot_inst_get (insn) == 2) 36493 return OPCODE_RFDE; 36494 if (Field_s_Slot_inst_get (insn) == 4) 36495 return OPCODE_RFWO; 36496 if (Field_s_Slot_inst_get (insn) == 5) 36497 return OPCODE_RFWU; 36498 } 36499 if (Field_t_Slot_inst_get (insn) == 1) 36500 return OPCODE_RFI; 36501 } 36502 if (Field_r_Slot_inst_get (insn) == 4) 36503 return OPCODE_BREAK; 36504 if (Field_r_Slot_inst_get (insn) == 5) 36505 { 36506 if (Field_s_Slot_inst_get (insn) == 0 && 36507 Field_t_Slot_inst_get (insn) == 0) 36508 return OPCODE_SYSCALL; 36509 if (Field_s_Slot_inst_get (insn) == 1 && 36510 Field_t_Slot_inst_get (insn) == 0) 36511 return OPCODE_SIMCALL; 36512 } 36513 if (Field_r_Slot_inst_get (insn) == 6) 36514 return OPCODE_RSIL; 36515 if (Field_r_Slot_inst_get (insn) == 7 && 36516 Field_t_Slot_inst_get (insn) == 0) 36517 return OPCODE_WAITI; 36518 if (Field_r_Slot_inst_get (insn) == 7) 36519 { 36520 if (Field_t_Slot_inst_get (insn) == 14) 36521 return OPCODE_LDDR32_P; 36522 if (Field_t_Slot_inst_get (insn) == 15) 36523 return OPCODE_SDDR32_P; 36524 } 36525 if (Field_r_Slot_inst_get (insn) == 8) 36526 return OPCODE_ANY4; 36527 if (Field_r_Slot_inst_get (insn) == 9) 36528 return OPCODE_ALL4; 36529 if (Field_r_Slot_inst_get (insn) == 10) 36530 return OPCODE_ANY8; 36531 if (Field_r_Slot_inst_get (insn) == 11) 36532 return OPCODE_ALL8; 36533 } 36534 if (Field_op2_Slot_inst_get (insn) == 1) 36535 return OPCODE_AND; 36536 if (Field_op2_Slot_inst_get (insn) == 2) 36537 return OPCODE_OR; 36538 if (Field_op2_Slot_inst_get (insn) == 3) 36539 return OPCODE_XOR; 36540 if (Field_op2_Slot_inst_get (insn) == 4) 36541 { 36542 if (Field_r_Slot_inst_get (insn) == 0 && 36543 Field_t_Slot_inst_get (insn) == 0) 36544 return OPCODE_SSR; 36545 if (Field_r_Slot_inst_get (insn) == 1 && 36546 Field_t_Slot_inst_get (insn) == 0) 36547 return OPCODE_SSL; 36548 if (Field_r_Slot_inst_get (insn) == 2 && 36549 Field_t_Slot_inst_get (insn) == 0) 36550 return OPCODE_SSA8L; 36551 if (Field_r_Slot_inst_get (insn) == 3 && 36552 Field_t_Slot_inst_get (insn) == 0) 36553 return OPCODE_SSA8B; 36554 if (Field_r_Slot_inst_get (insn) == 4 && 36555 Field_thi3_Slot_inst_get (insn) == 0) 36556 return OPCODE_SSAI; 36557 if (Field_r_Slot_inst_get (insn) == 6) 36558 return OPCODE_RER; 36559 if (Field_r_Slot_inst_get (insn) == 7) 36560 return OPCODE_WER; 36561 if (Field_r_Slot_inst_get (insn) == 8 && 36562 Field_s_Slot_inst_get (insn) == 0) 36563 return OPCODE_ROTW; 36564 if (Field_r_Slot_inst_get (insn) == 14) 36565 return OPCODE_NSA; 36566 if (Field_r_Slot_inst_get (insn) == 15) 36567 return OPCODE_NSAU; 36568 } 36569 if (Field_op2_Slot_inst_get (insn) == 5) 36570 { 36571 if (Field_r_Slot_inst_get (insn) == 1) 36572 return OPCODE_HWWITLBA; 36573 if (Field_r_Slot_inst_get (insn) == 3) 36574 return OPCODE_RITLB0; 36575 if (Field_r_Slot_inst_get (insn) == 4 && 36576 Field_t_Slot_inst_get (insn) == 0) 36577 return OPCODE_IITLB; 36578 if (Field_r_Slot_inst_get (insn) == 5) 36579 return OPCODE_PITLB; 36580 if (Field_r_Slot_inst_get (insn) == 6) 36581 return OPCODE_WITLB; 36582 if (Field_r_Slot_inst_get (insn) == 7) 36583 return OPCODE_RITLB1; 36584 if (Field_r_Slot_inst_get (insn) == 9) 36585 return OPCODE_HWWDTLBA; 36586 if (Field_r_Slot_inst_get (insn) == 11) 36587 return OPCODE_RDTLB0; 36588 if (Field_r_Slot_inst_get (insn) == 12 && 36589 Field_t_Slot_inst_get (insn) == 0) 36590 return OPCODE_IDTLB; 36591 if (Field_r_Slot_inst_get (insn) == 13) 36592 return OPCODE_PDTLB; 36593 if (Field_r_Slot_inst_get (insn) == 14) 36594 return OPCODE_WDTLB; 36595 if (Field_r_Slot_inst_get (insn) == 15) 36596 return OPCODE_RDTLB1; 36597 } 36598 if (Field_op2_Slot_inst_get (insn) == 6) 36599 { 36600 if (Field_s_Slot_inst_get (insn) == 0) 36601 return OPCODE_NEG; 36602 if (Field_s_Slot_inst_get (insn) == 1) 36603 return OPCODE_ABS; 36604 } 36605 if (Field_op2_Slot_inst_get (insn) == 8) 36606 return OPCODE_ADD; 36607 if (Field_op2_Slot_inst_get (insn) == 9) 36608 return OPCODE_ADDX2; 36609 if (Field_op2_Slot_inst_get (insn) == 10) 36610 return OPCODE_ADDX4; 36611 if (Field_op2_Slot_inst_get (insn) == 11) 36612 return OPCODE_ADDX8; 36613 if (Field_op2_Slot_inst_get (insn) == 12) 36614 return OPCODE_SUB; 36615 if (Field_op2_Slot_inst_get (insn) == 13) 36616 return OPCODE_SUBX2; 36617 if (Field_op2_Slot_inst_get (insn) == 14) 36618 return OPCODE_SUBX4; 36619 if (Field_op2_Slot_inst_get (insn) == 15) 36620 return OPCODE_SUBX8; 36621 } 36622 if (Field_op1_Slot_inst_get (insn) == 1) 36623 { 36624 if ((Field_op2_Slot_inst_get (insn) == 0 || 36625 Field_op2_Slot_inst_get (insn) == 1)) 36626 return OPCODE_SLLI; 36627 if ((Field_op2_Slot_inst_get (insn) == 2 || 36628 Field_op2_Slot_inst_get (insn) == 3)) 36629 return OPCODE_SRAI; 36630 if (Field_op2_Slot_inst_get (insn) == 4) 36631 return OPCODE_SRLI; 36632 if (Field_op2_Slot_inst_get (insn) == 6) 36633 { 36634 if (Field_sr_Slot_inst_get (insn) == 0) 36635 return OPCODE_XSR_LBEG; 36636 if (Field_sr_Slot_inst_get (insn) == 1) 36637 return OPCODE_XSR_LEND; 36638 if (Field_sr_Slot_inst_get (insn) == 2) 36639 return OPCODE_XSR_LCOUNT; 36640 if (Field_sr_Slot_inst_get (insn) == 3) 36641 return OPCODE_XSR_SAR; 36642 if (Field_sr_Slot_inst_get (insn) == 4) 36643 return OPCODE_XSR_BR; 36644 if (Field_sr_Slot_inst_get (insn) == 5) 36645 return OPCODE_XSR_LITBASE; 36646 if (Field_sr_Slot_inst_get (insn) == 12) 36647 return OPCODE_XSR_SCOMPARE1; 36648 if (Field_sr_Slot_inst_get (insn) == 16) 36649 return OPCODE_XSR_ACCLO; 36650 if (Field_sr_Slot_inst_get (insn) == 17) 36651 return OPCODE_XSR_ACCHI; 36652 if (Field_sr_Slot_inst_get (insn) == 32) 36653 return OPCODE_XSR_M0; 36654 if (Field_sr_Slot_inst_get (insn) == 33) 36655 return OPCODE_XSR_M1; 36656 if (Field_sr_Slot_inst_get (insn) == 34) 36657 return OPCODE_XSR_M2; 36658 if (Field_sr_Slot_inst_get (insn) == 35) 36659 return OPCODE_XSR_M3; 36660 if (Field_sr_Slot_inst_get (insn) == 40) 36661 return OPCODE_XSR_PREFCTL; 36662 if (Field_sr_Slot_inst_get (insn) == 72) 36663 return OPCODE_XSR_WINDOWBASE; 36664 if (Field_sr_Slot_inst_get (insn) == 73) 36665 return OPCODE_XSR_WINDOWSTART; 36666 if (Field_sr_Slot_inst_get (insn) == 83) 36667 return OPCODE_XSR_PTEVADDR; 36668 if (Field_sr_Slot_inst_get (insn) == 90) 36669 return OPCODE_XSR_RASID; 36670 if (Field_sr_Slot_inst_get (insn) == 91) 36671 return OPCODE_XSR_ITLBCFG; 36672 if (Field_sr_Slot_inst_get (insn) == 92) 36673 return OPCODE_XSR_DTLBCFG; 36674 if (Field_sr_Slot_inst_get (insn) == 96) 36675 return OPCODE_XSR_IBREAKENABLE; 36676 if (Field_sr_Slot_inst_get (insn) == 97) 36677 return OPCODE_XSR_MEMCTL; 36678 if (Field_sr_Slot_inst_get (insn) == 99) 36679 return OPCODE_XSR_ATOMCTL; 36680 if (Field_sr_Slot_inst_get (insn) == 104) 36681 return OPCODE_XSR_DDR; 36682 if (Field_sr_Slot_inst_get (insn) == 128) 36683 return OPCODE_XSR_IBREAKA0; 36684 if (Field_sr_Slot_inst_get (insn) == 129) 36685 return OPCODE_XSR_IBREAKA1; 36686 if (Field_sr_Slot_inst_get (insn) == 144) 36687 return OPCODE_XSR_DBREAKA0; 36688 if (Field_sr_Slot_inst_get (insn) == 145) 36689 return OPCODE_XSR_DBREAKA1; 36690 if (Field_sr_Slot_inst_get (insn) == 160) 36691 return OPCODE_XSR_DBREAKC0; 36692 if (Field_sr_Slot_inst_get (insn) == 161) 36693 return OPCODE_XSR_DBREAKC1; 36694 if (Field_sr_Slot_inst_get (insn) == 177) 36695 return OPCODE_XSR_EPC1; 36696 if (Field_sr_Slot_inst_get (insn) == 178) 36697 return OPCODE_XSR_EPC2; 36698 if (Field_sr_Slot_inst_get (insn) == 179) 36699 return OPCODE_XSR_EPC3; 36700 if (Field_sr_Slot_inst_get (insn) == 180) 36701 return OPCODE_XSR_EPC4; 36702 if (Field_sr_Slot_inst_get (insn) == 181) 36703 return OPCODE_XSR_EPC5; 36704 if (Field_sr_Slot_inst_get (insn) == 182) 36705 return OPCODE_XSR_EPC6; 36706 if (Field_sr_Slot_inst_get (insn) == 183) 36707 return OPCODE_XSR_EPC7; 36708 if (Field_sr_Slot_inst_get (insn) == 192) 36709 return OPCODE_XSR_DEPC; 36710 if (Field_sr_Slot_inst_get (insn) == 194) 36711 return OPCODE_XSR_EPS2; 36712 if (Field_sr_Slot_inst_get (insn) == 195) 36713 return OPCODE_XSR_EPS3; 36714 if (Field_sr_Slot_inst_get (insn) == 196) 36715 return OPCODE_XSR_EPS4; 36716 if (Field_sr_Slot_inst_get (insn) == 197) 36717 return OPCODE_XSR_EPS5; 36718 if (Field_sr_Slot_inst_get (insn) == 198) 36719 return OPCODE_XSR_EPS6; 36720 if (Field_sr_Slot_inst_get (insn) == 199) 36721 return OPCODE_XSR_EPS7; 36722 if (Field_sr_Slot_inst_get (insn) == 209) 36723 return OPCODE_XSR_EXCSAVE1; 36724 if (Field_sr_Slot_inst_get (insn) == 210) 36725 return OPCODE_XSR_EXCSAVE2; 36726 if (Field_sr_Slot_inst_get (insn) == 211) 36727 return OPCODE_XSR_EXCSAVE3; 36728 if (Field_sr_Slot_inst_get (insn) == 212) 36729 return OPCODE_XSR_EXCSAVE4; 36730 if (Field_sr_Slot_inst_get (insn) == 213) 36731 return OPCODE_XSR_EXCSAVE5; 36732 if (Field_sr_Slot_inst_get (insn) == 214) 36733 return OPCODE_XSR_EXCSAVE6; 36734 if (Field_sr_Slot_inst_get (insn) == 215) 36735 return OPCODE_XSR_EXCSAVE7; 36736 if (Field_sr_Slot_inst_get (insn) == 224) 36737 return OPCODE_XSR_CPENABLE; 36738 if (Field_sr_Slot_inst_get (insn) == 228) 36739 return OPCODE_XSR_INTENABLE; 36740 if (Field_sr_Slot_inst_get (insn) == 230) 36741 return OPCODE_XSR_PS; 36742 if (Field_sr_Slot_inst_get (insn) == 231) 36743 return OPCODE_XSR_VECBASE; 36744 if (Field_sr_Slot_inst_get (insn) == 232) 36745 return OPCODE_XSR_EXCCAUSE; 36746 if (Field_sr_Slot_inst_get (insn) == 233) 36747 return OPCODE_XSR_DEBUGCAUSE; 36748 if (Field_sr_Slot_inst_get (insn) == 234) 36749 return OPCODE_XSR_CCOUNT; 36750 if (Field_sr_Slot_inst_get (insn) == 236) 36751 return OPCODE_XSR_ICOUNT; 36752 if (Field_sr_Slot_inst_get (insn) == 237) 36753 return OPCODE_XSR_ICOUNTLEVEL; 36754 if (Field_sr_Slot_inst_get (insn) == 238) 36755 return OPCODE_XSR_EXCVADDR; 36756 if (Field_sr_Slot_inst_get (insn) == 240) 36757 return OPCODE_XSR_CCOMPARE0; 36758 if (Field_sr_Slot_inst_get (insn) == 241) 36759 return OPCODE_XSR_CCOMPARE1; 36760 if (Field_sr_Slot_inst_get (insn) == 242) 36761 return OPCODE_XSR_CCOMPARE2; 36762 if (Field_sr_Slot_inst_get (insn) == 244) 36763 return OPCODE_XSR_MISC0; 36764 if (Field_sr_Slot_inst_get (insn) == 245) 36765 return OPCODE_XSR_MISC1; 36766 } 36767 if (Field_op2_Slot_inst_get (insn) == 8) 36768 return OPCODE_SRC; 36769 if (Field_op2_Slot_inst_get (insn) == 9 && 36770 Field_s_Slot_inst_get (insn) == 0) 36771 return OPCODE_SRL; 36772 if (Field_op2_Slot_inst_get (insn) == 10 && 36773 Field_t_Slot_inst_get (insn) == 0) 36774 return OPCODE_SLL; 36775 if (Field_op2_Slot_inst_get (insn) == 11 && 36776 Field_s_Slot_inst_get (insn) == 0) 36777 return OPCODE_SRA; 36778 if (Field_op2_Slot_inst_get (insn) == 12) 36779 return OPCODE_MUL16U; 36780 if (Field_op2_Slot_inst_get (insn) == 13) 36781 return OPCODE_MUL16S; 36782 if (Field_op2_Slot_inst_get (insn) == 15) 36783 { 36784 if (Field_r_Slot_inst_get (insn) == 0) 36785 return OPCODE_LICT; 36786 if (Field_r_Slot_inst_get (insn) == 1) 36787 return OPCODE_SICT; 36788 if (Field_r_Slot_inst_get (insn) == 2) 36789 return OPCODE_LICW; 36790 if (Field_r_Slot_inst_get (insn) == 3) 36791 return OPCODE_SICW; 36792 if (Field_r_Slot_inst_get (insn) == 8) 36793 return OPCODE_LDCT; 36794 if (Field_r_Slot_inst_get (insn) == 9) 36795 return OPCODE_SDCT; 36796 if (Field_r_Slot_inst_get (insn) == 14 && 36797 Field_t_Slot_inst_get (insn) == 0) 36798 return OPCODE_RFDO; 36799 if (Field_r_Slot_inst_get (insn) == 14 && 36800 Field_t_Slot_inst_get (insn) == 1) 36801 return OPCODE_RFDD; 36802 if (Field_r_Slot_inst_get (insn) == 15) 36803 return OPCODE_LDPTE; 36804 } 36805 } 36806 if (Field_op1_Slot_inst_get (insn) == 2) 36807 { 36808 if (Field_op2_Slot_inst_get (insn) == 0) 36809 return OPCODE_ANDB; 36810 if (Field_op2_Slot_inst_get (insn) == 1) 36811 return OPCODE_ANDBC; 36812 if (Field_op2_Slot_inst_get (insn) == 2) 36813 return OPCODE_ORB; 36814 if (Field_op2_Slot_inst_get (insn) == 3) 36815 return OPCODE_ORBC; 36816 if (Field_op2_Slot_inst_get (insn) == 4) 36817 return OPCODE_XORB; 36818 if (Field_op2_Slot_inst_get (insn) == 8) 36819 return OPCODE_MULL; 36820 if (Field_op2_Slot_inst_get (insn) == 10) 36821 return OPCODE_MULUH; 36822 if (Field_op2_Slot_inst_get (insn) == 11) 36823 return OPCODE_MULSH; 36824 if (Field_op2_Slot_inst_get (insn) == 12) 36825 return OPCODE_QUOU; 36826 if (Field_op2_Slot_inst_get (insn) == 13) 36827 return OPCODE_QUOS; 36828 if (Field_op2_Slot_inst_get (insn) == 14) 36829 return OPCODE_REMU; 36830 if (Field_op2_Slot_inst_get (insn) == 15) 36831 return OPCODE_REMS; 36832 } 36833 if (Field_op1_Slot_inst_get (insn) == 3) 36834 { 36835 if (Field_op2_Slot_inst_get (insn) == 0) 36836 { 36837 if (Field_sr_Slot_inst_get (insn) == 0) 36838 return OPCODE_RSR_LBEG; 36839 if (Field_sr_Slot_inst_get (insn) == 1) 36840 return OPCODE_RSR_LEND; 36841 if (Field_sr_Slot_inst_get (insn) == 2) 36842 return OPCODE_RSR_LCOUNT; 36843 if (Field_sr_Slot_inst_get (insn) == 3) 36844 return OPCODE_RSR_SAR; 36845 if (Field_sr_Slot_inst_get (insn) == 4) 36846 return OPCODE_RSR_BR; 36847 if (Field_sr_Slot_inst_get (insn) == 5) 36848 return OPCODE_RSR_LITBASE; 36849 if (Field_sr_Slot_inst_get (insn) == 12) 36850 return OPCODE_RSR_SCOMPARE1; 36851 if (Field_sr_Slot_inst_get (insn) == 16) 36852 return OPCODE_RSR_ACCLO; 36853 if (Field_sr_Slot_inst_get (insn) == 17) 36854 return OPCODE_RSR_ACCHI; 36855 if (Field_sr_Slot_inst_get (insn) == 32) 36856 return OPCODE_RSR_M0; 36857 if (Field_sr_Slot_inst_get (insn) == 33) 36858 return OPCODE_RSR_M1; 36859 if (Field_sr_Slot_inst_get (insn) == 34) 36860 return OPCODE_RSR_M2; 36861 if (Field_sr_Slot_inst_get (insn) == 35) 36862 return OPCODE_RSR_M3; 36863 if (Field_sr_Slot_inst_get (insn) == 40) 36864 return OPCODE_RSR_PREFCTL; 36865 if (Field_sr_Slot_inst_get (insn) == 72) 36866 return OPCODE_RSR_WINDOWBASE; 36867 if (Field_sr_Slot_inst_get (insn) == 73) 36868 return OPCODE_RSR_WINDOWSTART; 36869 if (Field_sr_Slot_inst_get (insn) == 83) 36870 return OPCODE_RSR_PTEVADDR; 36871 if (Field_sr_Slot_inst_get (insn) == 90) 36872 return OPCODE_RSR_RASID; 36873 if (Field_sr_Slot_inst_get (insn) == 91) 36874 return OPCODE_RSR_ITLBCFG; 36875 if (Field_sr_Slot_inst_get (insn) == 92) 36876 return OPCODE_RSR_DTLBCFG; 36877 if (Field_sr_Slot_inst_get (insn) == 96) 36878 return OPCODE_RSR_IBREAKENABLE; 36879 if (Field_sr_Slot_inst_get (insn) == 97) 36880 return OPCODE_RSR_MEMCTL; 36881 if (Field_sr_Slot_inst_get (insn) == 99) 36882 return OPCODE_RSR_ATOMCTL; 36883 if (Field_sr_Slot_inst_get (insn) == 104) 36884 return OPCODE_RSR_DDR; 36885 if (Field_sr_Slot_inst_get (insn) == 128) 36886 return OPCODE_RSR_IBREAKA0; 36887 if (Field_sr_Slot_inst_get (insn) == 129) 36888 return OPCODE_RSR_IBREAKA1; 36889 if (Field_sr_Slot_inst_get (insn) == 144) 36890 return OPCODE_RSR_DBREAKA0; 36891 if (Field_sr_Slot_inst_get (insn) == 145) 36892 return OPCODE_RSR_DBREAKA1; 36893 if (Field_sr_Slot_inst_get (insn) == 160) 36894 return OPCODE_RSR_DBREAKC0; 36895 if (Field_sr_Slot_inst_get (insn) == 161) 36896 return OPCODE_RSR_DBREAKC1; 36897 if (Field_sr_Slot_inst_get (insn) == 176) 36898 return OPCODE_RSR_CONFIGID0; 36899 if (Field_sr_Slot_inst_get (insn) == 177) 36900 return OPCODE_RSR_EPC1; 36901 if (Field_sr_Slot_inst_get (insn) == 178) 36902 return OPCODE_RSR_EPC2; 36903 if (Field_sr_Slot_inst_get (insn) == 179) 36904 return OPCODE_RSR_EPC3; 36905 if (Field_sr_Slot_inst_get (insn) == 180) 36906 return OPCODE_RSR_EPC4; 36907 if (Field_sr_Slot_inst_get (insn) == 181) 36908 return OPCODE_RSR_EPC5; 36909 if (Field_sr_Slot_inst_get (insn) == 182) 36910 return OPCODE_RSR_EPC6; 36911 if (Field_sr_Slot_inst_get (insn) == 183) 36912 return OPCODE_RSR_EPC7; 36913 if (Field_sr_Slot_inst_get (insn) == 192) 36914 return OPCODE_RSR_DEPC; 36915 if (Field_sr_Slot_inst_get (insn) == 194) 36916 return OPCODE_RSR_EPS2; 36917 if (Field_sr_Slot_inst_get (insn) == 195) 36918 return OPCODE_RSR_EPS3; 36919 if (Field_sr_Slot_inst_get (insn) == 196) 36920 return OPCODE_RSR_EPS4; 36921 if (Field_sr_Slot_inst_get (insn) == 197) 36922 return OPCODE_RSR_EPS5; 36923 if (Field_sr_Slot_inst_get (insn) == 198) 36924 return OPCODE_RSR_EPS6; 36925 if (Field_sr_Slot_inst_get (insn) == 199) 36926 return OPCODE_RSR_EPS7; 36927 if (Field_sr_Slot_inst_get (insn) == 208) 36928 return OPCODE_RSR_CONFIGID1; 36929 if (Field_sr_Slot_inst_get (insn) == 209) 36930 return OPCODE_RSR_EXCSAVE1; 36931 if (Field_sr_Slot_inst_get (insn) == 210) 36932 return OPCODE_RSR_EXCSAVE2; 36933 if (Field_sr_Slot_inst_get (insn) == 211) 36934 return OPCODE_RSR_EXCSAVE3; 36935 if (Field_sr_Slot_inst_get (insn) == 212) 36936 return OPCODE_RSR_EXCSAVE4; 36937 if (Field_sr_Slot_inst_get (insn) == 213) 36938 return OPCODE_RSR_EXCSAVE5; 36939 if (Field_sr_Slot_inst_get (insn) == 214) 36940 return OPCODE_RSR_EXCSAVE6; 36941 if (Field_sr_Slot_inst_get (insn) == 215) 36942 return OPCODE_RSR_EXCSAVE7; 36943 if (Field_sr_Slot_inst_get (insn) == 224) 36944 return OPCODE_RSR_CPENABLE; 36945 if (Field_sr_Slot_inst_get (insn) == 226) 36946 return OPCODE_RSR_INTERRUPT; 36947 if (Field_sr_Slot_inst_get (insn) == 228) 36948 return OPCODE_RSR_INTENABLE; 36949 if (Field_sr_Slot_inst_get (insn) == 230) 36950 return OPCODE_RSR_PS; 36951 if (Field_sr_Slot_inst_get (insn) == 231) 36952 return OPCODE_RSR_VECBASE; 36953 if (Field_sr_Slot_inst_get (insn) == 232) 36954 return OPCODE_RSR_EXCCAUSE; 36955 if (Field_sr_Slot_inst_get (insn) == 233) 36956 return OPCODE_RSR_DEBUGCAUSE; 36957 if (Field_sr_Slot_inst_get (insn) == 234) 36958 return OPCODE_RSR_CCOUNT; 36959 if (Field_sr_Slot_inst_get (insn) == 235) 36960 return OPCODE_RSR_PRID; 36961 if (Field_sr_Slot_inst_get (insn) == 236) 36962 return OPCODE_RSR_ICOUNT; 36963 if (Field_sr_Slot_inst_get (insn) == 237) 36964 return OPCODE_RSR_ICOUNTLEVEL; 36965 if (Field_sr_Slot_inst_get (insn) == 238) 36966 return OPCODE_RSR_EXCVADDR; 36967 if (Field_sr_Slot_inst_get (insn) == 240) 36968 return OPCODE_RSR_CCOMPARE0; 36969 if (Field_sr_Slot_inst_get (insn) == 241) 36970 return OPCODE_RSR_CCOMPARE1; 36971 if (Field_sr_Slot_inst_get (insn) == 242) 36972 return OPCODE_RSR_CCOMPARE2; 36973 if (Field_sr_Slot_inst_get (insn) == 243) 36974 return OPCODE_RSR_243; 36975 if (Field_sr_Slot_inst_get (insn) == 244) 36976 return OPCODE_RSR_MISC0; 36977 if (Field_sr_Slot_inst_get (insn) == 245) 36978 return OPCODE_RSR_MISC1; 36979 } 36980 if (Field_op2_Slot_inst_get (insn) == 1) 36981 { 36982 if (Field_sr_Slot_inst_get (insn) == 0) 36983 return OPCODE_WSR_LBEG; 36984 if (Field_sr_Slot_inst_get (insn) == 1) 36985 return OPCODE_WSR_LEND; 36986 if (Field_sr_Slot_inst_get (insn) == 2) 36987 return OPCODE_WSR_LCOUNT; 36988 if (Field_sr_Slot_inst_get (insn) == 3) 36989 return OPCODE_WSR_SAR; 36990 if (Field_sr_Slot_inst_get (insn) == 4) 36991 return OPCODE_WSR_BR; 36992 if (Field_sr_Slot_inst_get (insn) == 5) 36993 return OPCODE_WSR_LITBASE; 36994 if (Field_sr_Slot_inst_get (insn) == 12) 36995 return OPCODE_WSR_SCOMPARE1; 36996 if (Field_sr_Slot_inst_get (insn) == 16) 36997 return OPCODE_WSR_ACCLO; 36998 if (Field_sr_Slot_inst_get (insn) == 17) 36999 return OPCODE_WSR_ACCHI; 37000 if (Field_sr_Slot_inst_get (insn) == 32) 37001 return OPCODE_WSR_M0; 37002 if (Field_sr_Slot_inst_get (insn) == 33) 37003 return OPCODE_WSR_M1; 37004 if (Field_sr_Slot_inst_get (insn) == 34) 37005 return OPCODE_WSR_M2; 37006 if (Field_sr_Slot_inst_get (insn) == 35) 37007 return OPCODE_WSR_M3; 37008 if (Field_sr_Slot_inst_get (insn) == 40) 37009 return OPCODE_WSR_PREFCTL; 37010 if (Field_sr_Slot_inst_get (insn) == 72) 37011 return OPCODE_WSR_WINDOWBASE; 37012 if (Field_sr_Slot_inst_get (insn) == 73) 37013 return OPCODE_WSR_WINDOWSTART; 37014 if (Field_sr_Slot_inst_get (insn) == 83) 37015 return OPCODE_WSR_PTEVADDR; 37016 if (Field_sr_Slot_inst_get (insn) == 89) 37017 return OPCODE_WSR_MMID; 37018 if (Field_sr_Slot_inst_get (insn) == 90) 37019 return OPCODE_WSR_RASID; 37020 if (Field_sr_Slot_inst_get (insn) == 91) 37021 return OPCODE_WSR_ITLBCFG; 37022 if (Field_sr_Slot_inst_get (insn) == 92) 37023 return OPCODE_WSR_DTLBCFG; 37024 if (Field_sr_Slot_inst_get (insn) == 96) 37025 return OPCODE_WSR_IBREAKENABLE; 37026 if (Field_sr_Slot_inst_get (insn) == 97) 37027 return OPCODE_WSR_MEMCTL; 37028 if (Field_sr_Slot_inst_get (insn) == 99) 37029 return OPCODE_WSR_ATOMCTL; 37030 if (Field_sr_Slot_inst_get (insn) == 104) 37031 return OPCODE_WSR_DDR; 37032 if (Field_sr_Slot_inst_get (insn) == 128) 37033 return OPCODE_WSR_IBREAKA0; 37034 if (Field_sr_Slot_inst_get (insn) == 129) 37035 return OPCODE_WSR_IBREAKA1; 37036 if (Field_sr_Slot_inst_get (insn) == 144) 37037 return OPCODE_WSR_DBREAKA0; 37038 if (Field_sr_Slot_inst_get (insn) == 145) 37039 return OPCODE_WSR_DBREAKA1; 37040 if (Field_sr_Slot_inst_get (insn) == 160) 37041 return OPCODE_WSR_DBREAKC0; 37042 if (Field_sr_Slot_inst_get (insn) == 161) 37043 return OPCODE_WSR_DBREAKC1; 37044 if (Field_sr_Slot_inst_get (insn) == 176) 37045 return OPCODE_WSR_CONFIGID0; 37046 if (Field_sr_Slot_inst_get (insn) == 177) 37047 return OPCODE_WSR_EPC1; 37048 if (Field_sr_Slot_inst_get (insn) == 178) 37049 return OPCODE_WSR_EPC2; 37050 if (Field_sr_Slot_inst_get (insn) == 179) 37051 return OPCODE_WSR_EPC3; 37052 if (Field_sr_Slot_inst_get (insn) == 180) 37053 return OPCODE_WSR_EPC4; 37054 if (Field_sr_Slot_inst_get (insn) == 181) 37055 return OPCODE_WSR_EPC5; 37056 if (Field_sr_Slot_inst_get (insn) == 182) 37057 return OPCODE_WSR_EPC6; 37058 if (Field_sr_Slot_inst_get (insn) == 183) 37059 return OPCODE_WSR_EPC7; 37060 if (Field_sr_Slot_inst_get (insn) == 192) 37061 return OPCODE_WSR_DEPC; 37062 if (Field_sr_Slot_inst_get (insn) == 194) 37063 return OPCODE_WSR_EPS2; 37064 if (Field_sr_Slot_inst_get (insn) == 195) 37065 return OPCODE_WSR_EPS3; 37066 if (Field_sr_Slot_inst_get (insn) == 196) 37067 return OPCODE_WSR_EPS4; 37068 if (Field_sr_Slot_inst_get (insn) == 197) 37069 return OPCODE_WSR_EPS5; 37070 if (Field_sr_Slot_inst_get (insn) == 198) 37071 return OPCODE_WSR_EPS6; 37072 if (Field_sr_Slot_inst_get (insn) == 199) 37073 return OPCODE_WSR_EPS7; 37074 if (Field_sr_Slot_inst_get (insn) == 209) 37075 return OPCODE_WSR_EXCSAVE1; 37076 if (Field_sr_Slot_inst_get (insn) == 210) 37077 return OPCODE_WSR_EXCSAVE2; 37078 if (Field_sr_Slot_inst_get (insn) == 211) 37079 return OPCODE_WSR_EXCSAVE3; 37080 if (Field_sr_Slot_inst_get (insn) == 212) 37081 return OPCODE_WSR_EXCSAVE4; 37082 if (Field_sr_Slot_inst_get (insn) == 213) 37083 return OPCODE_WSR_EXCSAVE5; 37084 if (Field_sr_Slot_inst_get (insn) == 214) 37085 return OPCODE_WSR_EXCSAVE6; 37086 if (Field_sr_Slot_inst_get (insn) == 215) 37087 return OPCODE_WSR_EXCSAVE7; 37088 if (Field_sr_Slot_inst_get (insn) == 224) 37089 return OPCODE_WSR_CPENABLE; 37090 if (Field_sr_Slot_inst_get (insn) == 226) 37091 return OPCODE_WSR_INTSET; 37092 if (Field_sr_Slot_inst_get (insn) == 227) 37093 return OPCODE_WSR_INTCLEAR; 37094 if (Field_sr_Slot_inst_get (insn) == 228) 37095 return OPCODE_WSR_INTENABLE; 37096 if (Field_sr_Slot_inst_get (insn) == 230) 37097 return OPCODE_WSR_PS; 37098 if (Field_sr_Slot_inst_get (insn) == 231) 37099 return OPCODE_WSR_VECBASE; 37100 if (Field_sr_Slot_inst_get (insn) == 232) 37101 return OPCODE_WSR_EXCCAUSE; 37102 if (Field_sr_Slot_inst_get (insn) == 233) 37103 return OPCODE_WSR_DEBUGCAUSE; 37104 if (Field_sr_Slot_inst_get (insn) == 234) 37105 return OPCODE_WSR_CCOUNT; 37106 if (Field_sr_Slot_inst_get (insn) == 236) 37107 return OPCODE_WSR_ICOUNT; 37108 if (Field_sr_Slot_inst_get (insn) == 237) 37109 return OPCODE_WSR_ICOUNTLEVEL; 37110 if (Field_sr_Slot_inst_get (insn) == 238) 37111 return OPCODE_WSR_EXCVADDR; 37112 if (Field_sr_Slot_inst_get (insn) == 240) 37113 return OPCODE_WSR_CCOMPARE0; 37114 if (Field_sr_Slot_inst_get (insn) == 241) 37115 return OPCODE_WSR_CCOMPARE1; 37116 if (Field_sr_Slot_inst_get (insn) == 242) 37117 return OPCODE_WSR_CCOMPARE2; 37118 if (Field_sr_Slot_inst_get (insn) == 244) 37119 return OPCODE_WSR_MISC0; 37120 if (Field_sr_Slot_inst_get (insn) == 245) 37121 return OPCODE_WSR_MISC1; 37122 } 37123 if (Field_op2_Slot_inst_get (insn) == 2) 37124 return OPCODE_SEXT; 37125 if (Field_op2_Slot_inst_get (insn) == 3) 37126 return OPCODE_CLAMPS; 37127 if (Field_op2_Slot_inst_get (insn) == 4) 37128 return OPCODE_MIN; 37129 if (Field_op2_Slot_inst_get (insn) == 5) 37130 return OPCODE_MAX; 37131 if (Field_op2_Slot_inst_get (insn) == 6) 37132 return OPCODE_MINU; 37133 if (Field_op2_Slot_inst_get (insn) == 7) 37134 return OPCODE_MAXU; 37135 if (Field_op2_Slot_inst_get (insn) == 8) 37136 return OPCODE_MOVEQZ; 37137 if (Field_op2_Slot_inst_get (insn) == 9) 37138 return OPCODE_MOVNEZ; 37139 if (Field_op2_Slot_inst_get (insn) == 10) 37140 return OPCODE_MOVLTZ; 37141 if (Field_op2_Slot_inst_get (insn) == 11) 37142 return OPCODE_MOVGEZ; 37143 if (Field_op2_Slot_inst_get (insn) == 12) 37144 return OPCODE_MOVF; 37145 if (Field_op2_Slot_inst_get (insn) == 13) 37146 return OPCODE_MOVT; 37147 if (Field_op2_Slot_inst_get (insn) == 14) 37148 { 37149 if (Field_st_Slot_inst_get (insn) == 230) 37150 return OPCODE_RUR_EXPSTATE; 37151 if (Field_st_Slot_inst_get (insn) == 231) 37152 return OPCODE_RUR_THREADPTR; 37153 if (Field_st_Slot_inst_get (insn) == 240) 37154 return OPCODE_RUR_AE_OVF_SAR; 37155 if (Field_st_Slot_inst_get (insn) == 241) 37156 return OPCODE_RUR_AE_BITHEAD; 37157 if (Field_st_Slot_inst_get (insn) == 242) 37158 return OPCODE_RUR_AE_TS_FTS_BU_BP; 37159 if (Field_st_Slot_inst_get (insn) == 243) 37160 return OPCODE_RUR_AE_SD_NO; 37161 if (Field_st_Slot_inst_get (insn) == 246) 37162 return OPCODE_RUR_AE_CBEGIN0; 37163 if (Field_st_Slot_inst_get (insn) == 247) 37164 return OPCODE_RUR_AE_CEND0; 37165 } 37166 if (Field_op2_Slot_inst_get (insn) == 15) 37167 { 37168 if (Field_sr_Slot_inst_get (insn) == 230) 37169 return OPCODE_WUR_EXPSTATE; 37170 if (Field_sr_Slot_inst_get (insn) == 231) 37171 return OPCODE_WUR_THREADPTR; 37172 if (Field_sr_Slot_inst_get (insn) == 240) 37173 return OPCODE_WUR_AE_OVF_SAR; 37174 if (Field_sr_Slot_inst_get (insn) == 241) 37175 return OPCODE_WUR_AE_BITHEAD; 37176 if (Field_sr_Slot_inst_get (insn) == 242) 37177 return OPCODE_WUR_AE_TS_FTS_BU_BP; 37178 if (Field_sr_Slot_inst_get (insn) == 243) 37179 return OPCODE_WUR_AE_SD_NO; 37180 if (Field_sr_Slot_inst_get (insn) == 246) 37181 return OPCODE_WUR_AE_CBEGIN0; 37182 if (Field_sr_Slot_inst_get (insn) == 247) 37183 return OPCODE_WUR_AE_CEND0; 37184 } 37185 } 37186 if ((Field_op1_Slot_inst_get (insn) == 4 || 37187 Field_op1_Slot_inst_get (insn) == 5)) 37188 return OPCODE_EXTUI; 37189 if (Field_op1_Slot_inst_get (insn) == 9) 37190 { 37191 if (Field_op2_Slot_inst_get (insn) == 0) 37192 return OPCODE_L32E; 37193 if (Field_op2_Slot_inst_get (insn) == 4) 37194 return OPCODE_S32E; 37195 if (Field_op2_Slot_inst_get (insn) == 5) 37196 return OPCODE_S32NB; 37197 } 37198 if (Field_r_Slot_inst_get (insn) == 0 && 37199 Field_s_Slot_inst_get (insn) == 0 && 37200 Field_op2_Slot_inst_get (insn) == 0 && 37201 Field_op1_Slot_inst_get (insn) == 14) 37202 return OPCODE_READ_IMPWIRE; 37203 if (Field_r_Slot_inst_get (insn) == 1 && 37204 Field_s3to1_Slot_inst_get (insn) == 0 && 37205 Field_op2_Slot_inst_get (insn) == 0 && 37206 Field_op1_Slot_inst_get (insn) == 14) 37207 return OPCODE_SETB_EXPSTATE; 37208 if (Field_r_Slot_inst_get (insn) == 1 && 37209 Field_s3to1_Slot_inst_get (insn) == 1 && 37210 Field_op2_Slot_inst_get (insn) == 0 && 37211 Field_op1_Slot_inst_get (insn) == 14) 37212 return OPCODE_CLRB_EXPSTATE; 37213 if (Field_r_Slot_inst_get (insn) == 2 && 37214 Field_op2_Slot_inst_get (insn) == 0 && 37215 Field_op1_Slot_inst_get (insn) == 14) 37216 return OPCODE_WRMSK_EXPSTATE; 37217 } 37218 if (Field_op0_Slot_inst_get (insn) == 1) 37219 return OPCODE_L32R; 37220 if (Field_op0_Slot_inst_get (insn) == 2) 37221 { 37222 if (Field_r_Slot_inst_get (insn) == 0) 37223 return OPCODE_L8UI; 37224 if (Field_r_Slot_inst_get (insn) == 1) 37225 return OPCODE_L16UI; 37226 if (Field_r_Slot_inst_get (insn) == 2) 37227 return OPCODE_L32I; 37228 if (Field_r_Slot_inst_get (insn) == 4) 37229 return OPCODE_S8I; 37230 if (Field_r_Slot_inst_get (insn) == 5) 37231 return OPCODE_S16I; 37232 if (Field_r_Slot_inst_get (insn) == 6) 37233 return OPCODE_S32I; 37234 if (Field_r_Slot_inst_get (insn) == 7) 37235 { 37236 if (Field_t_Slot_inst_get (insn) == 0) 37237 return OPCODE_DPFR; 37238 if (Field_t_Slot_inst_get (insn) == 1) 37239 return OPCODE_DPFW; 37240 if (Field_t_Slot_inst_get (insn) == 2) 37241 return OPCODE_DPFRO; 37242 if (Field_t_Slot_inst_get (insn) == 3) 37243 return OPCODE_DPFWO; 37244 if (Field_t_Slot_inst_get (insn) == 4) 37245 return OPCODE_DHWB; 37246 if (Field_t_Slot_inst_get (insn) == 5) 37247 return OPCODE_DHWBI; 37248 if (Field_t_Slot_inst_get (insn) == 6) 37249 return OPCODE_DHI; 37250 if (Field_t_Slot_inst_get (insn) == 7) 37251 return OPCODE_DII; 37252 if (Field_t_Slot_inst_get (insn) == 8) 37253 { 37254 if (Field_op1_Slot_inst_get (insn) == 0) 37255 return OPCODE_DPFL; 37256 if (Field_op1_Slot_inst_get (insn) == 2) 37257 return OPCODE_DHU; 37258 if (Field_op1_Slot_inst_get (insn) == 3) 37259 return OPCODE_DIU; 37260 if (Field_op1_Slot_inst_get (insn) == 4) 37261 return OPCODE_DIWB; 37262 if (Field_op1_Slot_inst_get (insn) == 5) 37263 return OPCODE_DIWBI; 37264 if (Field_op1_Slot_inst_get (insn) == 15 && 37265 Field_op2_Slot_inst_get (insn) == 0) 37266 return OPCODE_DIWBUI_P; 37267 } 37268 if (Field_t_Slot_inst_get (insn) == 12) 37269 return OPCODE_IPF; 37270 if (Field_t_Slot_inst_get (insn) == 13) 37271 { 37272 if (Field_op1_Slot_inst_get (insn) == 0) 37273 return OPCODE_IPFL; 37274 if (Field_op1_Slot_inst_get (insn) == 2) 37275 return OPCODE_IHU; 37276 if (Field_op1_Slot_inst_get (insn) == 3) 37277 return OPCODE_IIU; 37278 } 37279 if (Field_t_Slot_inst_get (insn) == 14) 37280 return OPCODE_IHI; 37281 if (Field_t_Slot_inst_get (insn) == 15) 37282 return OPCODE_III; 37283 } 37284 if (Field_r_Slot_inst_get (insn) == 9) 37285 return OPCODE_L16SI; 37286 if (Field_r_Slot_inst_get (insn) == 10) 37287 return OPCODE_MOVI; 37288 if (Field_r_Slot_inst_get (insn) == 11) 37289 return OPCODE_L32AI; 37290 if (Field_r_Slot_inst_get (insn) == 12) 37291 return OPCODE_ADDI; 37292 if (Field_r_Slot_inst_get (insn) == 13) 37293 return OPCODE_ADDMI; 37294 if (Field_r_Slot_inst_get (insn) == 14) 37295 return OPCODE_S32C1I; 37296 if (Field_r_Slot_inst_get (insn) == 15) 37297 return OPCODE_S32RI; 37298 } 37299 if (Field_op0_Slot_inst_get (insn) == 4) 37300 { 37301 if (Field_ae_r10_Slot_inst_get (insn) == 0 && 37302 Field_op1_Slot_inst_get (insn) == 1 && 37303 Field_op2_Slot_inst_get (insn) == 12) 37304 return OPCODE_AE_LQ56_I; 37305 if (Field_ae_r10_Slot_inst_get (insn) == 0 && 37306 Field_op1_Slot_inst_get (insn) == 2 && 37307 Field_op2_Slot_inst_get (insn) == 12) 37308 return OPCODE_AE_LQ56_X; 37309 if (Field_ae_r10_Slot_inst_get (insn) == 1 && 37310 Field_op1_Slot_inst_get (insn) == 1 && 37311 Field_op2_Slot_inst_get (insn) == 12) 37312 return OPCODE_AE_LQ32F_I; 37313 if (Field_ae_r10_Slot_inst_get (insn) == 1 && 37314 Field_op1_Slot_inst_get (insn) == 2 && 37315 Field_op2_Slot_inst_get (insn) == 12) 37316 return OPCODE_AE_LQ32F_X; 37317 if (Field_ae_r10_Slot_inst_get (insn) == 2 && 37318 Field_op1_Slot_inst_get (insn) == 1 && 37319 Field_op2_Slot_inst_get (insn) == 12) 37320 return OPCODE_AE_LQ56_IU; 37321 if (Field_ae_r10_Slot_inst_get (insn) == 2 && 37322 Field_op1_Slot_inst_get (insn) == 2 && 37323 Field_op2_Slot_inst_get (insn) == 12) 37324 return OPCODE_AE_LQ56_XU; 37325 if (Field_ae_r10_Slot_inst_get (insn) == 2 && 37326 Field_op1_Slot_inst_get (insn) == 7 && 37327 Field_t_Slot_inst_get (insn) == 3 && 37328 Field_op2_Slot_inst_get (insn) == 14) 37329 return OPCODE_AE_CVTQ48A32S; 37330 if (Field_ae_r10_Slot_inst_get (insn) == 3 && 37331 Field_op1_Slot_inst_get (insn) == 1 && 37332 Field_op2_Slot_inst_get (insn) == 12) 37333 return OPCODE_AE_LQ32F_IU; 37334 if (Field_ae_r10_Slot_inst_get (insn) == 3 && 37335 Field_op1_Slot_inst_get (insn) == 2 && 37336 Field_op2_Slot_inst_get (insn) == 12) 37337 return OPCODE_AE_LQ32F_XU; 37338 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37339 Field_op1_Slot_inst_get (insn) == 5 && 37340 Field_op2_Slot_inst_get (insn) == 10) 37341 return OPCODE_AE_LP16F_I; 37342 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37343 Field_op1_Slot_inst_get (insn) == 9 && 37344 Field_op2_Slot_inst_get (insn) == 10) 37345 return OPCODE_AE_LP16F_IU; 37346 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37347 Field_op1_Slot_inst_get (insn) == 12 && 37348 Field_op2_Slot_inst_get (insn) == 10) 37349 return OPCODE_AE_LP16F_X; 37350 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37351 Field_op1_Slot_inst_get (insn) == 15 && 37352 Field_op2_Slot_inst_get (insn) == 10) 37353 return OPCODE_AE_LP16F_XU; 37354 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37355 Field_op1_Slot_inst_get (insn) == 6 && 37356 Field_op2_Slot_inst_get (insn) == 10) 37357 return OPCODE_AE_LP24F_I; 37358 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37359 Field_op1_Slot_inst_get (insn) == 10 && 37360 Field_op2_Slot_inst_get (insn) == 10) 37361 return OPCODE_AE_LP24F_IU; 37362 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37363 Field_op1_Slot_inst_get (insn) == 13 && 37364 Field_op2_Slot_inst_get (insn) == 10) 37365 return OPCODE_AE_LP24F_X; 37366 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37367 Field_op1_Slot_inst_get (insn) == 0 && 37368 Field_op2_Slot_inst_get (insn) == 11) 37369 return OPCODE_AE_LP24F_XU; 37370 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37371 Field_op1_Slot_inst_get (insn) == 7 && 37372 Field_op2_Slot_inst_get (insn) == 10) 37373 return OPCODE_AE_LP24X2F_I; 37374 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37375 Field_op1_Slot_inst_get (insn) == 11 && 37376 Field_op2_Slot_inst_get (insn) == 10) 37377 return OPCODE_AE_LP24X2F_IU; 37378 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37379 Field_op1_Slot_inst_get (insn) == 14 && 37380 Field_op2_Slot_inst_get (insn) == 10) 37381 return OPCODE_AE_LP24X2F_X; 37382 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37383 Field_op1_Slot_inst_get (insn) == 1 && 37384 Field_op2_Slot_inst_get (insn) == 11) 37385 return OPCODE_AE_LP24X2F_XU; 37386 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37387 Field_op1_Slot_inst_get (insn) == 2 && 37388 Field_op2_Slot_inst_get (insn) == 11) 37389 return OPCODE_AE_SP16X2F_I; 37390 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37391 Field_op1_Slot_inst_get (insn) == 5 && 37392 Field_op2_Slot_inst_get (insn) == 11) 37393 return OPCODE_AE_SP16X2F_IU; 37394 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37395 Field_op1_Slot_inst_get (insn) == 8 && 37396 Field_op2_Slot_inst_get (insn) == 11) 37397 return OPCODE_AE_SP16X2F_X; 37398 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37399 Field_op1_Slot_inst_get (insn) == 11 && 37400 Field_op2_Slot_inst_get (insn) == 11) 37401 return OPCODE_AE_SP16X2F_XU; 37402 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37403 Field_op1_Slot_inst_get (insn) == 3 && 37404 Field_op2_Slot_inst_get (insn) == 11) 37405 return OPCODE_AE_SP24X2F_I; 37406 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37407 Field_op1_Slot_inst_get (insn) == 6 && 37408 Field_op2_Slot_inst_get (insn) == 11) 37409 return OPCODE_AE_SP24X2F_IU; 37410 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37411 Field_op1_Slot_inst_get (insn) == 9 && 37412 Field_op2_Slot_inst_get (insn) == 11) 37413 return OPCODE_AE_SP24X2F_X; 37414 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37415 Field_op1_Slot_inst_get (insn) == 12 && 37416 Field_op2_Slot_inst_get (insn) == 11) 37417 return OPCODE_AE_SP24X2F_XU; 37418 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37419 Field_op1_Slot_inst_get (insn) == 4 && 37420 Field_op2_Slot_inst_get (insn) == 11) 37421 return OPCODE_AE_SP24S_L_I; 37422 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37423 Field_op1_Slot_inst_get (insn) == 7 && 37424 Field_op2_Slot_inst_get (insn) == 11) 37425 return OPCODE_AE_SP24S_L_IU; 37426 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37427 Field_op1_Slot_inst_get (insn) == 10 && 37428 Field_op2_Slot_inst_get (insn) == 11) 37429 return OPCODE_AE_SP24S_L_X; 37430 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37431 Field_op1_Slot_inst_get (insn) == 13 && 37432 Field_op2_Slot_inst_get (insn) == 11) 37433 return OPCODE_AE_SP24S_L_XU; 37434 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37435 Field_ae_s3_Slot_inst_get (insn) == 0 && 37436 Field_t_Slot_inst_get (insn) == 0 && 37437 Field_op1_Slot_inst_get (insn) == 9 && 37438 Field_op2_Slot_inst_get (insn) == 12) 37439 return OPCODE_AE_MOVP48; 37440 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37441 Field_op1_Slot_inst_get (insn) == 0 && 37442 Field_op2_Slot_inst_get (insn) == 12) 37443 return OPCODE_AE_MOVPA24X2; 37444 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37445 Field_t_Slot_inst_get (insn) == 0 && 37446 Field_op1_Slot_inst_get (insn) == 11 && 37447 Field_op2_Slot_inst_get (insn) == 12) 37448 return OPCODE_AE_CVTA32P24_L; 37449 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37450 Field_op1_Slot_inst_get (insn) == 14 && 37451 Field_op2_Slot_inst_get (insn) == 11) 37452 return OPCODE_AE_CVTP24A16X2_LL; 37453 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37454 Field_op1_Slot_inst_get (insn) == 15 && 37455 Field_op2_Slot_inst_get (insn) == 11) 37456 return OPCODE_AE_CVTP24A16X2_HL; 37457 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37458 Field_t_Slot_inst_get (insn) == 0 && 37459 Field_op1_Slot_inst_get (insn) == 7 && 37460 Field_op2_Slot_inst_get (insn) == 12) 37461 return OPCODE_AE_MOVAP24S_L; 37462 if (Field_ae_r3_Slot_inst_get (insn) == 0 && 37463 Field_t_Slot_inst_get (insn) == 0 && 37464 Field_op1_Slot_inst_get (insn) == 8 && 37465 Field_op2_Slot_inst_get (insn) == 12) 37466 return OPCODE_AE_TRUNCA16P24S_L; 37467 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37468 Field_op1_Slot_inst_get (insn) == 5 && 37469 Field_op2_Slot_inst_get (insn) == 10) 37470 return OPCODE_AE_LP24_I; 37471 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37472 Field_op1_Slot_inst_get (insn) == 9 && 37473 Field_op2_Slot_inst_get (insn) == 10) 37474 return OPCODE_AE_LP24_IU; 37475 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37476 Field_op1_Slot_inst_get (insn) == 12 && 37477 Field_op2_Slot_inst_get (insn) == 10) 37478 return OPCODE_AE_LP24_X; 37479 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37480 Field_op1_Slot_inst_get (insn) == 15 && 37481 Field_op2_Slot_inst_get (insn) == 10) 37482 return OPCODE_AE_LP24_XU; 37483 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37484 Field_op1_Slot_inst_get (insn) == 6 && 37485 Field_op2_Slot_inst_get (insn) == 10) 37486 return OPCODE_AE_LP16X2F_I; 37487 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37488 Field_op1_Slot_inst_get (insn) == 10 && 37489 Field_op2_Slot_inst_get (insn) == 10) 37490 return OPCODE_AE_LP16X2F_IU; 37491 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37492 Field_op1_Slot_inst_get (insn) == 13 && 37493 Field_op2_Slot_inst_get (insn) == 10) 37494 return OPCODE_AE_LP16X2F_X; 37495 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37496 Field_op1_Slot_inst_get (insn) == 0 && 37497 Field_op2_Slot_inst_get (insn) == 11) 37498 return OPCODE_AE_LP16X2F_XU; 37499 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37500 Field_op1_Slot_inst_get (insn) == 7 && 37501 Field_op2_Slot_inst_get (insn) == 10) 37502 return OPCODE_AE_LP24X2_I; 37503 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37504 Field_op1_Slot_inst_get (insn) == 11 && 37505 Field_op2_Slot_inst_get (insn) == 10) 37506 return OPCODE_AE_LP24X2_IU; 37507 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37508 Field_op1_Slot_inst_get (insn) == 14 && 37509 Field_op2_Slot_inst_get (insn) == 10) 37510 return OPCODE_AE_LP24X2_X; 37511 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37512 Field_op1_Slot_inst_get (insn) == 1 && 37513 Field_op2_Slot_inst_get (insn) == 11) 37514 return OPCODE_AE_LP24X2_XU; 37515 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37516 Field_op1_Slot_inst_get (insn) == 2 && 37517 Field_op2_Slot_inst_get (insn) == 11) 37518 return OPCODE_AE_SP24X2S_I; 37519 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37520 Field_op1_Slot_inst_get (insn) == 5 && 37521 Field_op2_Slot_inst_get (insn) == 11) 37522 return OPCODE_AE_SP24X2S_IU; 37523 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37524 Field_op1_Slot_inst_get (insn) == 8 && 37525 Field_op2_Slot_inst_get (insn) == 11) 37526 return OPCODE_AE_SP24X2S_X; 37527 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37528 Field_op1_Slot_inst_get (insn) == 11 && 37529 Field_op2_Slot_inst_get (insn) == 11) 37530 return OPCODE_AE_SP24X2S_XU; 37531 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37532 Field_op1_Slot_inst_get (insn) == 3 && 37533 Field_op2_Slot_inst_get (insn) == 11) 37534 return OPCODE_AE_SP16F_L_I; 37535 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37536 Field_op1_Slot_inst_get (insn) == 6 && 37537 Field_op2_Slot_inst_get (insn) == 11) 37538 return OPCODE_AE_SP16F_L_IU; 37539 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37540 Field_op1_Slot_inst_get (insn) == 9 && 37541 Field_op2_Slot_inst_get (insn) == 11) 37542 return OPCODE_AE_SP16F_L_X; 37543 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37544 Field_op1_Slot_inst_get (insn) == 12 && 37545 Field_op2_Slot_inst_get (insn) == 11) 37546 return OPCODE_AE_SP16F_L_XU; 37547 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37548 Field_op1_Slot_inst_get (insn) == 4 && 37549 Field_op2_Slot_inst_get (insn) == 11) 37550 return OPCODE_AE_SP24F_L_I; 37551 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37552 Field_op1_Slot_inst_get (insn) == 7 && 37553 Field_op2_Slot_inst_get (insn) == 11) 37554 return OPCODE_AE_SP24F_L_IU; 37555 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37556 Field_op1_Slot_inst_get (insn) == 10 && 37557 Field_op2_Slot_inst_get (insn) == 11) 37558 return OPCODE_AE_SP24F_L_X; 37559 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37560 Field_op1_Slot_inst_get (insn) == 13 && 37561 Field_op2_Slot_inst_get (insn) == 11) 37562 return OPCODE_AE_SP24F_L_XU; 37563 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37564 Field_op1_Slot_inst_get (insn) == 0 && 37565 Field_op2_Slot_inst_get (insn) == 12) 37566 return OPCODE_AE_TRUNCP24A32X2; 37567 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37568 Field_t_Slot_inst_get (insn) == 0 && 37569 Field_op1_Slot_inst_get (insn) == 11 && 37570 Field_op2_Slot_inst_get (insn) == 12) 37571 return OPCODE_AE_CVTA32P24_H; 37572 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37573 Field_op1_Slot_inst_get (insn) == 14 && 37574 Field_op2_Slot_inst_get (insn) == 11) 37575 return OPCODE_AE_CVTP24A16X2_LH; 37576 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37577 Field_op1_Slot_inst_get (insn) == 15 && 37578 Field_op2_Slot_inst_get (insn) == 11) 37579 return OPCODE_AE_CVTP24A16X2_HH; 37580 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37581 Field_t_Slot_inst_get (insn) == 0 && 37582 Field_op1_Slot_inst_get (insn) == 7 && 37583 Field_op2_Slot_inst_get (insn) == 12) 37584 return OPCODE_AE_MOVAP24S_H; 37585 if (Field_ae_r3_Slot_inst_get (insn) == 1 && 37586 Field_t_Slot_inst_get (insn) == 0 && 37587 Field_op1_Slot_inst_get (insn) == 8 && 37588 Field_op2_Slot_inst_get (insn) == 12) 37589 return OPCODE_AE_TRUNCA16P24S_H; 37590 if (Field_ae_r32_Slot_inst_get (insn) == 0 && 37591 Field_op1_Slot_inst_get (insn) == 3 && 37592 Field_op2_Slot_inst_get (insn) == 12) 37593 return OPCODE_AE_SQ56S_I; 37594 if (Field_ae_r32_Slot_inst_get (insn) == 0 && 37595 Field_op1_Slot_inst_get (insn) == 4 && 37596 Field_op2_Slot_inst_get (insn) == 12) 37597 return OPCODE_AE_SQ56S_X; 37598 if (Field_ae_r32_Slot_inst_get (insn) == 0 && 37599 Field_op1_Slot_inst_get (insn) == 7 && 37600 Field_t_Slot_inst_get (insn) == 1 && 37601 Field_op2_Slot_inst_get (insn) == 14) 37602 return OPCODE_AE_TRUNCA32Q48; 37603 if (Field_ae_r32_Slot_inst_get (insn) == 1 && 37604 Field_op1_Slot_inst_get (insn) == 3 && 37605 Field_op2_Slot_inst_get (insn) == 12) 37606 return OPCODE_AE_SQ32F_I; 37607 if (Field_ae_r32_Slot_inst_get (insn) == 1 && 37608 Field_op1_Slot_inst_get (insn) == 4 && 37609 Field_op2_Slot_inst_get (insn) == 12) 37610 return OPCODE_AE_SQ32F_X; 37611 if (Field_ae_r32_Slot_inst_get (insn) == 1 && 37612 Field_op1_Slot_inst_get (insn) == 7 && 37613 Field_t_Slot_inst_get (insn) == 1 && 37614 Field_op2_Slot_inst_get (insn) == 14) 37615 return OPCODE_AE_NSAQ56S; 37616 if (Field_ae_r32_Slot_inst_get (insn) == 2 && 37617 Field_op1_Slot_inst_get (insn) == 3 && 37618 Field_op2_Slot_inst_get (insn) == 12) 37619 return OPCODE_AE_SQ56S_IU; 37620 if (Field_ae_r32_Slot_inst_get (insn) == 2 && 37621 Field_op1_Slot_inst_get (insn) == 4 && 37622 Field_op2_Slot_inst_get (insn) == 12) 37623 return OPCODE_AE_SQ56S_XU; 37624 if (Field_ae_r32_Slot_inst_get (insn) == 3 && 37625 Field_op1_Slot_inst_get (insn) == 3 && 37626 Field_op2_Slot_inst_get (insn) == 12) 37627 return OPCODE_AE_SQ32F_IU; 37628 if (Field_ae_r32_Slot_inst_get (insn) == 3 && 37629 Field_op1_Slot_inst_get (insn) == 4 && 37630 Field_op2_Slot_inst_get (insn) == 12) 37631 return OPCODE_AE_SQ32F_XU; 37632 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 && 37633 Field_op1_Slot_inst_get (insn) == 5 && 37634 Field_op2_Slot_inst_get (insn) == 12) 37635 return OPCODE_AE_SLLIQ56; 37636 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 && 37637 Field_op1_Slot_inst_get (insn) == 5 && 37638 Field_op2_Slot_inst_get (insn) == 12) 37639 return OPCODE_AE_SRLIQ56; 37640 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 && 37641 Field_op1_Slot_inst_get (insn) == 5 && 37642 Field_op2_Slot_inst_get (insn) == 12) 37643 return OPCODE_AE_SRAIQ56; 37644 if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 && 37645 Field_op1_Slot_inst_get (insn) == 5 && 37646 Field_op2_Slot_inst_get (insn) == 12) 37647 return OPCODE_AE_SLLISQ56S; 37648 if (Field_op1_Slot_inst_get (insn) == 0 && 37649 Field_t_Slot_inst_get (insn) == 1 && 37650 Field_op2_Slot_inst_get (insn) == 14) 37651 return OPCODE_AE_SHA32; 37652 if (Field_op1_Slot_inst_get (insn) == 0 && 37653 Field_op2_Slot_inst_get (insn) == 10) 37654 return OPCODE_AE_VLDL32T; 37655 if (Field_op1_Slot_inst_get (insn) == 1 && 37656 Field_t_Slot_inst_get (insn) == 1 && 37657 Field_op2_Slot_inst_get (insn) == 14) 37658 return OPCODE_AE_SLLAQ56; 37659 if (Field_op1_Slot_inst_get (insn) == 1 && 37660 Field_op2_Slot_inst_get (insn) == 10) 37661 return OPCODE_AE_VLDL16T; 37662 if (Field_op1_Slot_inst_get (insn) == 2 && 37663 Field_t_Slot_inst_get (insn) == 1 && 37664 Field_op2_Slot_inst_get (insn) == 14) 37665 return OPCODE_AE_SRLAQ56; 37666 if (Field_op1_Slot_inst_get (insn) == 2 && 37667 Field_op2_Slot_inst_get (insn) == 10) 37668 return OPCODE_AE_LBK; 37669 if (Field_op1_Slot_inst_get (insn) == 3 && 37670 Field_t_Slot_inst_get (insn) == 1 && 37671 Field_op2_Slot_inst_get (insn) == 14) 37672 return OPCODE_AE_SRAAQ56; 37673 if (Field_op1_Slot_inst_get (insn) == 3 && 37674 Field_op2_Slot_inst_get (insn) == 10) 37675 return OPCODE_AE_VLEL32T; 37676 if (Field_op1_Slot_inst_get (insn) == 4 && 37677 Field_t_Slot_inst_get (insn) == 1 && 37678 Field_op2_Slot_inst_get (insn) == 14) 37679 return OPCODE_AE_SLLASQ56S; 37680 if (Field_op1_Slot_inst_get (insn) == 4 && 37681 Field_op2_Slot_inst_get (insn) == 10) 37682 return OPCODE_AE_VLEL16T; 37683 if (Field_op1_Slot_inst_get (insn) == 5 && 37684 Field_t_Slot_inst_get (insn) == 1 && 37685 Field_op2_Slot_inst_get (insn) == 14) 37686 return OPCODE_AE_MOVTQ56; 37687 if (Field_op1_Slot_inst_get (insn) == 6 && 37688 Field_t_Slot_inst_get (insn) == 1 && 37689 Field_op2_Slot_inst_get (insn) == 14) 37690 return OPCODE_AE_MOVFQ56; 37691 if (Field_op2_Slot_inst_get (insn) == 0) 37692 { 37693 if (Field_op1_Slot_inst_get (insn) == 8 && 37694 Field_t3_Slot_inst_get (insn) == 0 && 37695 Field_tlo_Slot_inst_get (insn) == 0 && 37696 Field_r3_Slot_inst_get (insn) == 0) 37697 return OPCODE_MULA_DD_LL_LDINC; 37698 if (Field_op1_Slot_inst_get (insn) == 9 && 37699 Field_t3_Slot_inst_get (insn) == 0 && 37700 Field_tlo_Slot_inst_get (insn) == 0 && 37701 Field_r3_Slot_inst_get (insn) == 0) 37702 return OPCODE_MULA_DD_HL_LDINC; 37703 if (Field_op1_Slot_inst_get (insn) == 10 && 37704 Field_t3_Slot_inst_get (insn) == 0 && 37705 Field_tlo_Slot_inst_get (insn) == 0 && 37706 Field_r3_Slot_inst_get (insn) == 0) 37707 return OPCODE_MULA_DD_LH_LDINC; 37708 if (Field_op1_Slot_inst_get (insn) == 11 && 37709 Field_t3_Slot_inst_get (insn) == 0 && 37710 Field_tlo_Slot_inst_get (insn) == 0 && 37711 Field_r3_Slot_inst_get (insn) == 0) 37712 return OPCODE_MULA_DD_HH_LDINC; 37713 } 37714 if (Field_op2_Slot_inst_get (insn) == 1) 37715 { 37716 if (Field_op1_Slot_inst_get (insn) == 8 && 37717 Field_t3_Slot_inst_get (insn) == 0 && 37718 Field_tlo_Slot_inst_get (insn) == 0 && 37719 Field_r3_Slot_inst_get (insn) == 0) 37720 return OPCODE_MULA_DD_LL_LDDEC; 37721 if (Field_op1_Slot_inst_get (insn) == 9 && 37722 Field_t3_Slot_inst_get (insn) == 0 && 37723 Field_tlo_Slot_inst_get (insn) == 0 && 37724 Field_r3_Slot_inst_get (insn) == 0) 37725 return OPCODE_MULA_DD_HL_LDDEC; 37726 if (Field_op1_Slot_inst_get (insn) == 10 && 37727 Field_t3_Slot_inst_get (insn) == 0 && 37728 Field_tlo_Slot_inst_get (insn) == 0 && 37729 Field_r3_Slot_inst_get (insn) == 0) 37730 return OPCODE_MULA_DD_LH_LDDEC; 37731 if (Field_op1_Slot_inst_get (insn) == 11 && 37732 Field_t3_Slot_inst_get (insn) == 0 && 37733 Field_tlo_Slot_inst_get (insn) == 0 && 37734 Field_r3_Slot_inst_get (insn) == 0) 37735 return OPCODE_MULA_DD_HH_LDDEC; 37736 } 37737 if (Field_op2_Slot_inst_get (insn) == 2) 37738 { 37739 if (Field_op1_Slot_inst_get (insn) == 4 && 37740 Field_s_Slot_inst_get (insn) == 0 && 37741 Field_w_Slot_inst_get (insn) == 0 && 37742 Field_r3_Slot_inst_get (insn) == 0 && 37743 Field_t3_Slot_inst_get (insn) == 0 && 37744 Field_tlo_Slot_inst_get (insn) == 0) 37745 return OPCODE_MUL_DD_LL; 37746 if (Field_op1_Slot_inst_get (insn) == 5 && 37747 Field_s_Slot_inst_get (insn) == 0 && 37748 Field_w_Slot_inst_get (insn) == 0 && 37749 Field_r3_Slot_inst_get (insn) == 0 && 37750 Field_t3_Slot_inst_get (insn) == 0 && 37751 Field_tlo_Slot_inst_get (insn) == 0) 37752 return OPCODE_MUL_DD_HL; 37753 if (Field_op1_Slot_inst_get (insn) == 6 && 37754 Field_s_Slot_inst_get (insn) == 0 && 37755 Field_w_Slot_inst_get (insn) == 0 && 37756 Field_r3_Slot_inst_get (insn) == 0 && 37757 Field_t3_Slot_inst_get (insn) == 0 && 37758 Field_tlo_Slot_inst_get (insn) == 0) 37759 return OPCODE_MUL_DD_LH; 37760 if (Field_op1_Slot_inst_get (insn) == 7 && 37761 Field_s_Slot_inst_get (insn) == 0 && 37762 Field_w_Slot_inst_get (insn) == 0 && 37763 Field_r3_Slot_inst_get (insn) == 0 && 37764 Field_t3_Slot_inst_get (insn) == 0 && 37765 Field_tlo_Slot_inst_get (insn) == 0) 37766 return OPCODE_MUL_DD_HH; 37767 if (Field_op1_Slot_inst_get (insn) == 8 && 37768 Field_s_Slot_inst_get (insn) == 0 && 37769 Field_w_Slot_inst_get (insn) == 0 && 37770 Field_r3_Slot_inst_get (insn) == 0 && 37771 Field_t3_Slot_inst_get (insn) == 0 && 37772 Field_tlo_Slot_inst_get (insn) == 0) 37773 return OPCODE_MULA_DD_LL; 37774 if (Field_op1_Slot_inst_get (insn) == 9 && 37775 Field_s_Slot_inst_get (insn) == 0 && 37776 Field_w_Slot_inst_get (insn) == 0 && 37777 Field_r3_Slot_inst_get (insn) == 0 && 37778 Field_t3_Slot_inst_get (insn) == 0 && 37779 Field_tlo_Slot_inst_get (insn) == 0) 37780 return OPCODE_MULA_DD_HL; 37781 if (Field_op1_Slot_inst_get (insn) == 10 && 37782 Field_s_Slot_inst_get (insn) == 0 && 37783 Field_w_Slot_inst_get (insn) == 0 && 37784 Field_r3_Slot_inst_get (insn) == 0 && 37785 Field_t3_Slot_inst_get (insn) == 0 && 37786 Field_tlo_Slot_inst_get (insn) == 0) 37787 return OPCODE_MULA_DD_LH; 37788 if (Field_op1_Slot_inst_get (insn) == 11 && 37789 Field_s_Slot_inst_get (insn) == 0 && 37790 Field_w_Slot_inst_get (insn) == 0 && 37791 Field_r3_Slot_inst_get (insn) == 0 && 37792 Field_t3_Slot_inst_get (insn) == 0 && 37793 Field_tlo_Slot_inst_get (insn) == 0) 37794 return OPCODE_MULA_DD_HH; 37795 if (Field_op1_Slot_inst_get (insn) == 12 && 37796 Field_s_Slot_inst_get (insn) == 0 && 37797 Field_w_Slot_inst_get (insn) == 0 && 37798 Field_r3_Slot_inst_get (insn) == 0 && 37799 Field_t3_Slot_inst_get (insn) == 0 && 37800 Field_tlo_Slot_inst_get (insn) == 0) 37801 return OPCODE_MULS_DD_LL; 37802 if (Field_op1_Slot_inst_get (insn) == 13 && 37803 Field_s_Slot_inst_get (insn) == 0 && 37804 Field_w_Slot_inst_get (insn) == 0 && 37805 Field_r3_Slot_inst_get (insn) == 0 && 37806 Field_t3_Slot_inst_get (insn) == 0 && 37807 Field_tlo_Slot_inst_get (insn) == 0) 37808 return OPCODE_MULS_DD_HL; 37809 if (Field_op1_Slot_inst_get (insn) == 14 && 37810 Field_s_Slot_inst_get (insn) == 0 && 37811 Field_w_Slot_inst_get (insn) == 0 && 37812 Field_r3_Slot_inst_get (insn) == 0 && 37813 Field_t3_Slot_inst_get (insn) == 0 && 37814 Field_tlo_Slot_inst_get (insn) == 0) 37815 return OPCODE_MULS_DD_LH; 37816 if (Field_op1_Slot_inst_get (insn) == 15 && 37817 Field_s_Slot_inst_get (insn) == 0 && 37818 Field_w_Slot_inst_get (insn) == 0 && 37819 Field_r3_Slot_inst_get (insn) == 0 && 37820 Field_t3_Slot_inst_get (insn) == 0 && 37821 Field_tlo_Slot_inst_get (insn) == 0) 37822 return OPCODE_MULS_DD_HH; 37823 } 37824 if (Field_op2_Slot_inst_get (insn) == 3) 37825 { 37826 if (Field_op1_Slot_inst_get (insn) == 4 && 37827 Field_r_Slot_inst_get (insn) == 0 && 37828 Field_t3_Slot_inst_get (insn) == 0 && 37829 Field_tlo_Slot_inst_get (insn) == 0) 37830 return OPCODE_MUL_AD_LL; 37831 if (Field_op1_Slot_inst_get (insn) == 5 && 37832 Field_r_Slot_inst_get (insn) == 0 && 37833 Field_t3_Slot_inst_get (insn) == 0 && 37834 Field_tlo_Slot_inst_get (insn) == 0) 37835 return OPCODE_MUL_AD_HL; 37836 if (Field_op1_Slot_inst_get (insn) == 6 && 37837 Field_r_Slot_inst_get (insn) == 0 && 37838 Field_t3_Slot_inst_get (insn) == 0 && 37839 Field_tlo_Slot_inst_get (insn) == 0) 37840 return OPCODE_MUL_AD_LH; 37841 if (Field_op1_Slot_inst_get (insn) == 7 && 37842 Field_r_Slot_inst_get (insn) == 0 && 37843 Field_t3_Slot_inst_get (insn) == 0 && 37844 Field_tlo_Slot_inst_get (insn) == 0) 37845 return OPCODE_MUL_AD_HH; 37846 if (Field_op1_Slot_inst_get (insn) == 8 && 37847 Field_r_Slot_inst_get (insn) == 0 && 37848 Field_t3_Slot_inst_get (insn) == 0 && 37849 Field_tlo_Slot_inst_get (insn) == 0) 37850 return OPCODE_MULA_AD_LL; 37851 if (Field_op1_Slot_inst_get (insn) == 9 && 37852 Field_r_Slot_inst_get (insn) == 0 && 37853 Field_t3_Slot_inst_get (insn) == 0 && 37854 Field_tlo_Slot_inst_get (insn) == 0) 37855 return OPCODE_MULA_AD_HL; 37856 if (Field_op1_Slot_inst_get (insn) == 10 && 37857 Field_r_Slot_inst_get (insn) == 0 && 37858 Field_t3_Slot_inst_get (insn) == 0 && 37859 Field_tlo_Slot_inst_get (insn) == 0) 37860 return OPCODE_MULA_AD_LH; 37861 if (Field_op1_Slot_inst_get (insn) == 11 && 37862 Field_r_Slot_inst_get (insn) == 0 && 37863 Field_t3_Slot_inst_get (insn) == 0 && 37864 Field_tlo_Slot_inst_get (insn) == 0) 37865 return OPCODE_MULA_AD_HH; 37866 if (Field_op1_Slot_inst_get (insn) == 12 && 37867 Field_r_Slot_inst_get (insn) == 0 && 37868 Field_t3_Slot_inst_get (insn) == 0 && 37869 Field_tlo_Slot_inst_get (insn) == 0) 37870 return OPCODE_MULS_AD_LL; 37871 if (Field_op1_Slot_inst_get (insn) == 13 && 37872 Field_r_Slot_inst_get (insn) == 0 && 37873 Field_t3_Slot_inst_get (insn) == 0 && 37874 Field_tlo_Slot_inst_get (insn) == 0) 37875 return OPCODE_MULS_AD_HL; 37876 if (Field_op1_Slot_inst_get (insn) == 14 && 37877 Field_r_Slot_inst_get (insn) == 0 && 37878 Field_t3_Slot_inst_get (insn) == 0 && 37879 Field_tlo_Slot_inst_get (insn) == 0) 37880 return OPCODE_MULS_AD_LH; 37881 if (Field_op1_Slot_inst_get (insn) == 15 && 37882 Field_r_Slot_inst_get (insn) == 0 && 37883 Field_t3_Slot_inst_get (insn) == 0 && 37884 Field_tlo_Slot_inst_get (insn) == 0) 37885 return OPCODE_MULS_AD_HH; 37886 } 37887 if (Field_op2_Slot_inst_get (insn) == 4) 37888 { 37889 if (Field_op1_Slot_inst_get (insn) == 8 && 37890 Field_r3_Slot_inst_get (insn) == 0) 37891 return OPCODE_MULA_DA_LL_LDINC; 37892 if (Field_op1_Slot_inst_get (insn) == 9 && 37893 Field_r3_Slot_inst_get (insn) == 0) 37894 return OPCODE_MULA_DA_HL_LDINC; 37895 if (Field_op1_Slot_inst_get (insn) == 10 && 37896 Field_r3_Slot_inst_get (insn) == 0) 37897 return OPCODE_MULA_DA_LH_LDINC; 37898 if (Field_op1_Slot_inst_get (insn) == 11 && 37899 Field_r3_Slot_inst_get (insn) == 0) 37900 return OPCODE_MULA_DA_HH_LDINC; 37901 } 37902 if (Field_op2_Slot_inst_get (insn) == 5) 37903 { 37904 if (Field_op1_Slot_inst_get (insn) == 8 && 37905 Field_r3_Slot_inst_get (insn) == 0) 37906 return OPCODE_MULA_DA_LL_LDDEC; 37907 if (Field_op1_Slot_inst_get (insn) == 9 && 37908 Field_r3_Slot_inst_get (insn) == 0) 37909 return OPCODE_MULA_DA_HL_LDDEC; 37910 if (Field_op1_Slot_inst_get (insn) == 10 && 37911 Field_r3_Slot_inst_get (insn) == 0) 37912 return OPCODE_MULA_DA_LH_LDDEC; 37913 if (Field_op1_Slot_inst_get (insn) == 11 && 37914 Field_r3_Slot_inst_get (insn) == 0) 37915 return OPCODE_MULA_DA_HH_LDDEC; 37916 } 37917 if (Field_op2_Slot_inst_get (insn) == 6) 37918 { 37919 if (Field_op1_Slot_inst_get (insn) == 4 && 37920 Field_s_Slot_inst_get (insn) == 0 && 37921 Field_w_Slot_inst_get (insn) == 0 && 37922 Field_r3_Slot_inst_get (insn) == 0) 37923 return OPCODE_MUL_DA_LL; 37924 if (Field_op1_Slot_inst_get (insn) == 5 && 37925 Field_s_Slot_inst_get (insn) == 0 && 37926 Field_w_Slot_inst_get (insn) == 0 && 37927 Field_r3_Slot_inst_get (insn) == 0) 37928 return OPCODE_MUL_DA_HL; 37929 if (Field_op1_Slot_inst_get (insn) == 6 && 37930 Field_s_Slot_inst_get (insn) == 0 && 37931 Field_w_Slot_inst_get (insn) == 0 && 37932 Field_r3_Slot_inst_get (insn) == 0) 37933 return OPCODE_MUL_DA_LH; 37934 if (Field_op1_Slot_inst_get (insn) == 7 && 37935 Field_s_Slot_inst_get (insn) == 0 && 37936 Field_w_Slot_inst_get (insn) == 0 && 37937 Field_r3_Slot_inst_get (insn) == 0) 37938 return OPCODE_MUL_DA_HH; 37939 if (Field_op1_Slot_inst_get (insn) == 8 && 37940 Field_s_Slot_inst_get (insn) == 0 && 37941 Field_w_Slot_inst_get (insn) == 0 && 37942 Field_r3_Slot_inst_get (insn) == 0) 37943 return OPCODE_MULA_DA_LL; 37944 if (Field_op1_Slot_inst_get (insn) == 9 && 37945 Field_s_Slot_inst_get (insn) == 0 && 37946 Field_w_Slot_inst_get (insn) == 0 && 37947 Field_r3_Slot_inst_get (insn) == 0) 37948 return OPCODE_MULA_DA_HL; 37949 if (Field_op1_Slot_inst_get (insn) == 10 && 37950 Field_s_Slot_inst_get (insn) == 0 && 37951 Field_w_Slot_inst_get (insn) == 0 && 37952 Field_r3_Slot_inst_get (insn) == 0) 37953 return OPCODE_MULA_DA_LH; 37954 if (Field_op1_Slot_inst_get (insn) == 11 && 37955 Field_s_Slot_inst_get (insn) == 0 && 37956 Field_w_Slot_inst_get (insn) == 0 && 37957 Field_r3_Slot_inst_get (insn) == 0) 37958 return OPCODE_MULA_DA_HH; 37959 if (Field_op1_Slot_inst_get (insn) == 12 && 37960 Field_s_Slot_inst_get (insn) == 0 && 37961 Field_w_Slot_inst_get (insn) == 0 && 37962 Field_r3_Slot_inst_get (insn) == 0) 37963 return OPCODE_MULS_DA_LL; 37964 if (Field_op1_Slot_inst_get (insn) == 13 && 37965 Field_s_Slot_inst_get (insn) == 0 && 37966 Field_w_Slot_inst_get (insn) == 0 && 37967 Field_r3_Slot_inst_get (insn) == 0) 37968 return OPCODE_MULS_DA_HL; 37969 if (Field_op1_Slot_inst_get (insn) == 14 && 37970 Field_s_Slot_inst_get (insn) == 0 && 37971 Field_w_Slot_inst_get (insn) == 0 && 37972 Field_r3_Slot_inst_get (insn) == 0) 37973 return OPCODE_MULS_DA_LH; 37974 if (Field_op1_Slot_inst_get (insn) == 15 && 37975 Field_s_Slot_inst_get (insn) == 0 && 37976 Field_w_Slot_inst_get (insn) == 0 && 37977 Field_r3_Slot_inst_get (insn) == 0) 37978 return OPCODE_MULS_DA_HH; 37979 } 37980 if (Field_op2_Slot_inst_get (insn) == 7) 37981 { 37982 if (Field_op1_Slot_inst_get (insn) == 0 && 37983 Field_r_Slot_inst_get (insn) == 0) 37984 return OPCODE_UMUL_AA_LL; 37985 if (Field_op1_Slot_inst_get (insn) == 1 && 37986 Field_r_Slot_inst_get (insn) == 0) 37987 return OPCODE_UMUL_AA_HL; 37988 if (Field_op1_Slot_inst_get (insn) == 2 && 37989 Field_r_Slot_inst_get (insn) == 0) 37990 return OPCODE_UMUL_AA_LH; 37991 if (Field_op1_Slot_inst_get (insn) == 3 && 37992 Field_r_Slot_inst_get (insn) == 0) 37993 return OPCODE_UMUL_AA_HH; 37994 if (Field_op1_Slot_inst_get (insn) == 4 && 37995 Field_r_Slot_inst_get (insn) == 0) 37996 return OPCODE_MUL_AA_LL; 37997 if (Field_op1_Slot_inst_get (insn) == 5 && 37998 Field_r_Slot_inst_get (insn) == 0) 37999 return OPCODE_MUL_AA_HL; 38000 if (Field_op1_Slot_inst_get (insn) == 6 && 38001 Field_r_Slot_inst_get (insn) == 0) 38002 return OPCODE_MUL_AA_LH; 38003 if (Field_op1_Slot_inst_get (insn) == 7 && 38004 Field_r_Slot_inst_get (insn) == 0) 38005 return OPCODE_MUL_AA_HH; 38006 if (Field_op1_Slot_inst_get (insn) == 8 && 38007 Field_r_Slot_inst_get (insn) == 0) 38008 return OPCODE_MULA_AA_LL; 38009 if (Field_op1_Slot_inst_get (insn) == 9 && 38010 Field_r_Slot_inst_get (insn) == 0) 38011 return OPCODE_MULA_AA_HL; 38012 if (Field_op1_Slot_inst_get (insn) == 10 && 38013 Field_r_Slot_inst_get (insn) == 0) 38014 return OPCODE_MULA_AA_LH; 38015 if (Field_op1_Slot_inst_get (insn) == 11 && 38016 Field_r_Slot_inst_get (insn) == 0) 38017 return OPCODE_MULA_AA_HH; 38018 if (Field_op1_Slot_inst_get (insn) == 12 && 38019 Field_r_Slot_inst_get (insn) == 0) 38020 return OPCODE_MULS_AA_LL; 38021 if (Field_op1_Slot_inst_get (insn) == 13 && 38022 Field_r_Slot_inst_get (insn) == 0) 38023 return OPCODE_MULS_AA_HL; 38024 if (Field_op1_Slot_inst_get (insn) == 14 && 38025 Field_r_Slot_inst_get (insn) == 0) 38026 return OPCODE_MULS_AA_LH; 38027 if (Field_op1_Slot_inst_get (insn) == 15 && 38028 Field_r_Slot_inst_get (insn) == 0) 38029 return OPCODE_MULS_AA_HH; 38030 } 38031 if (Field_op2_Slot_inst_get (insn) == 8) 38032 { 38033 if (Field_op1_Slot_inst_get (insn) == 0 && 38034 Field_t_Slot_inst_get (insn) == 0 && 38035 Field_rhi_Slot_inst_get (insn) == 0) 38036 return OPCODE_LDINC; 38037 } 38038 if (Field_op2_Slot_inst_get (insn) == 9) 38039 { 38040 if (Field_op1_Slot_inst_get (insn) == 0 && 38041 Field_t_Slot_inst_get (insn) == 0 && 38042 Field_rhi_Slot_inst_get (insn) == 0) 38043 return OPCODE_LDDEC; 38044 } 38045 if (Field_r_Slot_inst_get (insn) == 0 && 38046 Field_s_Slot_inst_get (insn) == 0 && 38047 Field_op1_Slot_inst_get (insn) == 10 && 38048 Field_op2_Slot_inst_get (insn) == 12) 38049 return OPCODE_WUR_AE_OVERFLOW; 38050 if (Field_r_Slot_inst_get (insn) == 0 && 38051 Field_op2_Slot_inst_get (insn) == 15) 38052 return OPCODE_AE_SBI; 38053 if (Field_r_Slot_inst_get (insn) == 1 && 38054 Field_s_Slot_inst_get (insn) == 0 && 38055 Field_op1_Slot_inst_get (insn) == 10 && 38056 Field_op2_Slot_inst_get (insn) == 12) 38057 return OPCODE_WUR_AE_SAR; 38058 if (Field_r_Slot_inst_get (insn) == 1 && 38059 Field_op1_Slot_inst_get (insn) == 0 && 38060 Field_op2_Slot_inst_get (insn) == 15) 38061 return OPCODE_AE_DB; 38062 if (Field_r_Slot_inst_get (insn) == 1 && 38063 Field_op1_Slot_inst_get (insn) == 1 && 38064 Field_op2_Slot_inst_get (insn) == 15) 38065 return OPCODE_AE_SB; 38066 if (Field_r_Slot_inst_get (insn) == 2 && 38067 Field_s_Slot_inst_get (insn) == 0 && 38068 Field_op1_Slot_inst_get (insn) == 10 && 38069 Field_op2_Slot_inst_get (insn) == 12) 38070 return OPCODE_WUR_AE_BITPTR; 38071 if (Field_r_Slot_inst_get (insn) == 3 && 38072 Field_s_Slot_inst_get (insn) == 0 && 38073 Field_op1_Slot_inst_get (insn) == 10 && 38074 Field_op2_Slot_inst_get (insn) == 12) 38075 return OPCODE_WUR_AE_BITSUSED; 38076 if (Field_r_Slot_inst_get (insn) == 4 && 38077 Field_s_Slot_inst_get (insn) == 0 && 38078 Field_op1_Slot_inst_get (insn) == 10 && 38079 Field_op2_Slot_inst_get (insn) == 12) 38080 return OPCODE_WUR_AE_TABLESIZE; 38081 if (Field_r_Slot_inst_get (insn) == 5 && 38082 Field_s_Slot_inst_get (insn) == 0 && 38083 Field_op1_Slot_inst_get (insn) == 10 && 38084 Field_op2_Slot_inst_get (insn) == 12) 38085 return OPCODE_WUR_AE_FIRST_TS; 38086 if (Field_r_Slot_inst_get (insn) == 6 && 38087 Field_s_Slot_inst_get (insn) == 0 && 38088 Field_op1_Slot_inst_get (insn) == 10 && 38089 Field_op2_Slot_inst_get (insn) == 12) 38090 return OPCODE_WUR_AE_NEXTOFFSET; 38091 if (Field_r_Slot_inst_get (insn) == 7 && 38092 Field_s_Slot_inst_get (insn) == 0 && 38093 Field_op1_Slot_inst_get (insn) == 10 && 38094 Field_op2_Slot_inst_get (insn) == 12) 38095 return OPCODE_WUR_AE_SEARCHDONE; 38096 if (Field_r_Slot_inst_get (insn) == 8 && 38097 Field_s_Slot_inst_get (insn) == 0 && 38098 Field_op1_Slot_inst_get (insn) == 10 && 38099 Field_op2_Slot_inst_get (insn) == 12) 38100 return OPCODE_AE_VLDSHT; 38101 if (Field_r_Slot_inst_get (insn) == 12 && 38102 Field_op1_Slot_inst_get (insn) == 7 && 38103 Field_t_Slot_inst_get (insn) == 1 && 38104 Field_op2_Slot_inst_get (insn) == 14) 38105 return OPCODE_AE_VLES16C; 38106 if (Field_r_Slot_inst_get (insn) == 13 && 38107 Field_op1_Slot_inst_get (insn) == 7 && 38108 Field_t_Slot_inst_get (insn) == 1 && 38109 Field_op2_Slot_inst_get (insn) == 14) 38110 return OPCODE_AE_SBF; 38111 if (Field_r_Slot_inst_get (insn) == 14 && 38112 Field_op1_Slot_inst_get (insn) == 7 && 38113 Field_t_Slot_inst_get (insn) == 1 && 38114 Field_op2_Slot_inst_get (insn) == 14) 38115 return OPCODE_AE_VLDL16C; 38116 if (Field_s_Slot_inst_get (insn) == 0 && 38117 Field_t_Slot_inst_get (insn) == 1 && 38118 Field_op1_Slot_inst_get (insn) == 9 && 38119 Field_op2_Slot_inst_get (insn) == 12) 38120 return OPCODE_AE_SLLSQ56; 38121 if (Field_s_Slot_inst_get (insn) == 0 && 38122 Field_op1_Slot_inst_get (insn) == 6 && 38123 Field_op2_Slot_inst_get (insn) == 12) 38124 return OPCODE_AE_LB; 38125 if (Field_s_Slot_inst_get (insn) == 1 && 38126 Field_t_Slot_inst_get (insn) == 1 && 38127 Field_op1_Slot_inst_get (insn) == 9 && 38128 Field_op2_Slot_inst_get (insn) == 12) 38129 return OPCODE_AE_SRLSQ56; 38130 if (Field_s_Slot_inst_get (insn) == 2 && 38131 Field_t_Slot_inst_get (insn) == 1 && 38132 Field_op1_Slot_inst_get (insn) == 9 && 38133 Field_op2_Slot_inst_get (insn) == 12) 38134 return OPCODE_AE_SRASQ56; 38135 if (Field_s_Slot_inst_get (insn) == 3 && 38136 Field_t_Slot_inst_get (insn) == 1 && 38137 Field_op1_Slot_inst_get (insn) == 9 && 38138 Field_op2_Slot_inst_get (insn) == 12) 38139 return OPCODE_AE_SLLSSQ56S; 38140 if (Field_s_Slot_inst_get (insn) == 4 && 38141 Field_t_Slot_inst_get (insn) == 1 && 38142 Field_op1_Slot_inst_get (insn) == 9 && 38143 Field_op2_Slot_inst_get (insn) == 12) 38144 return OPCODE_AE_MOVQ56; 38145 if (Field_s_Slot_inst_get (insn) == 8 && 38146 Field_t_Slot_inst_get (insn) == 0 && 38147 Field_op1_Slot_inst_get (insn) == 9 && 38148 Field_op2_Slot_inst_get (insn) == 12) 38149 return OPCODE_RUR_AE_OVERFLOW; 38150 if (Field_s_Slot_inst_get (insn) == 9 && 38151 Field_t_Slot_inst_get (insn) == 0 && 38152 Field_op1_Slot_inst_get (insn) == 9 && 38153 Field_op2_Slot_inst_get (insn) == 12) 38154 return OPCODE_RUR_AE_SAR; 38155 if (Field_s_Slot_inst_get (insn) == 10 && 38156 Field_t_Slot_inst_get (insn) == 0 && 38157 Field_op1_Slot_inst_get (insn) == 9 && 38158 Field_op2_Slot_inst_get (insn) == 12) 38159 return OPCODE_RUR_AE_BITPTR; 38160 if (Field_s_Slot_inst_get (insn) == 11 && 38161 Field_t_Slot_inst_get (insn) == 0 && 38162 Field_op1_Slot_inst_get (insn) == 9 && 38163 Field_op2_Slot_inst_get (insn) == 12) 38164 return OPCODE_RUR_AE_BITSUSED; 38165 if (Field_s_Slot_inst_get (insn) == 12 && 38166 Field_t_Slot_inst_get (insn) == 0 && 38167 Field_op1_Slot_inst_get (insn) == 9 && 38168 Field_op2_Slot_inst_get (insn) == 12) 38169 return OPCODE_RUR_AE_TABLESIZE; 38170 if (Field_s_Slot_inst_get (insn) == 13 && 38171 Field_t_Slot_inst_get (insn) == 0 && 38172 Field_op1_Slot_inst_get (insn) == 9 && 38173 Field_op2_Slot_inst_get (insn) == 12) 38174 return OPCODE_RUR_AE_FIRST_TS; 38175 if (Field_s_Slot_inst_get (insn) == 14 && 38176 Field_t_Slot_inst_get (insn) == 0 && 38177 Field_op1_Slot_inst_get (insn) == 9 && 38178 Field_op2_Slot_inst_get (insn) == 12) 38179 return OPCODE_RUR_AE_NEXTOFFSET; 38180 if (Field_s_Slot_inst_get (insn) == 15 && 38181 Field_t_Slot_inst_get (insn) == 0 && 38182 Field_op1_Slot_inst_get (insn) == 9 && 38183 Field_op2_Slot_inst_get (insn) == 12) 38184 return OPCODE_RUR_AE_SEARCHDONE; 38185 if (Field_t_Slot_inst_get (insn) == 0 && 38186 Field_op2_Slot_inst_get (insn) == 14) 38187 return OPCODE_AE_LBKI; 38188 if (Field_t_Slot_inst_get (insn) == 0 && 38189 Field_r_Slot_inst_get (insn) == 2 && 38190 Field_op2_Slot_inst_get (insn) == 15) 38191 return OPCODE_AE_DBI; 38192 if (Field_t_Slot_inst_get (insn) == 2 && 38193 Field_s_Slot_inst_get (insn) == 0 && 38194 Field_op2_Slot_inst_get (insn) == 14) 38195 return OPCODE_AE_LBI; 38196 } 38197 if (Field_op0_Slot_inst_get (insn) == 5) 38198 { 38199 if (Field_n_Slot_inst_get (insn) == 0) 38200 return OPCODE_CALL0; 38201 if (Field_n_Slot_inst_get (insn) == 1) 38202 return OPCODE_CALL4; 38203 if (Field_n_Slot_inst_get (insn) == 2) 38204 return OPCODE_CALL8; 38205 if (Field_n_Slot_inst_get (insn) == 3) 38206 return OPCODE_CALL12; 38207 } 38208 if (Field_op0_Slot_inst_get (insn) == 6) 38209 { 38210 if (Field_n_Slot_inst_get (insn) == 0) 38211 return OPCODE_J; 38212 if (Field_n_Slot_inst_get (insn) == 1) 38213 { 38214 if (Field_m_Slot_inst_get (insn) == 0) 38215 return OPCODE_BEQZ; 38216 if (Field_m_Slot_inst_get (insn) == 1) 38217 return OPCODE_BNEZ; 38218 if (Field_m_Slot_inst_get (insn) == 2) 38219 return OPCODE_BLTZ; 38220 if (Field_m_Slot_inst_get (insn) == 3) 38221 return OPCODE_BGEZ; 38222 } 38223 if (Field_n_Slot_inst_get (insn) == 2) 38224 { 38225 if (Field_m_Slot_inst_get (insn) == 0) 38226 return OPCODE_BEQI; 38227 if (Field_m_Slot_inst_get (insn) == 1) 38228 return OPCODE_BNEI; 38229 if (Field_m_Slot_inst_get (insn) == 2) 38230 return OPCODE_BLTI; 38231 if (Field_m_Slot_inst_get (insn) == 3) 38232 return OPCODE_BGEI; 38233 } 38234 if (Field_n_Slot_inst_get (insn) == 3) 38235 { 38236 if (Field_m_Slot_inst_get (insn) == 0) 38237 return OPCODE_ENTRY; 38238 if (Field_m_Slot_inst_get (insn) == 1) 38239 { 38240 if (Field_r_Slot_inst_get (insn) == 0) 38241 return OPCODE_BF; 38242 if (Field_r_Slot_inst_get (insn) == 1) 38243 return OPCODE_BT; 38244 if (Field_r_Slot_inst_get (insn) == 8) 38245 return OPCODE_LOOP; 38246 if (Field_r_Slot_inst_get (insn) == 9) 38247 return OPCODE_LOOPNEZ; 38248 if (Field_r_Slot_inst_get (insn) == 10) 38249 return OPCODE_LOOPGTZ; 38250 } 38251 if (Field_m_Slot_inst_get (insn) == 2) 38252 return OPCODE_BLTUI; 38253 if (Field_m_Slot_inst_get (insn) == 3) 38254 return OPCODE_BGEUI; 38255 } 38256 } 38257 if (Field_op0_Slot_inst_get (insn) == 7) 38258 { 38259 if (Field_r_Slot_inst_get (insn) == 0) 38260 return OPCODE_BNONE; 38261 if (Field_r_Slot_inst_get (insn) == 1) 38262 return OPCODE_BEQ; 38263 if (Field_r_Slot_inst_get (insn) == 2) 38264 return OPCODE_BLT; 38265 if (Field_r_Slot_inst_get (insn) == 3) 38266 return OPCODE_BLTU; 38267 if (Field_r_Slot_inst_get (insn) == 4) 38268 return OPCODE_BALL; 38269 if (Field_r_Slot_inst_get (insn) == 5) 38270 return OPCODE_BBC; 38271 if ((Field_r_Slot_inst_get (insn) == 6 || 38272 Field_r_Slot_inst_get (insn) == 7)) 38273 return OPCODE_BBCI; 38274 if (Field_r_Slot_inst_get (insn) == 8) 38275 return OPCODE_BANY; 38276 if (Field_r_Slot_inst_get (insn) == 9) 38277 return OPCODE_BNE; 38278 if (Field_r_Slot_inst_get (insn) == 10) 38279 return OPCODE_BGE; 38280 if (Field_r_Slot_inst_get (insn) == 11) 38281 return OPCODE_BGEU; 38282 if (Field_r_Slot_inst_get (insn) == 12) 38283 return OPCODE_BNALL; 38284 if (Field_r_Slot_inst_get (insn) == 13) 38285 return OPCODE_BBS; 38286 if ((Field_r_Slot_inst_get (insn) == 14 || 38287 Field_r_Slot_inst_get (insn) == 15)) 38288 return OPCODE_BBSI; 38289 } 38290 return XTENSA_UNDEFINED; 38291 } 38292 38293 static int 38294 Slot_inst16b_decode (const xtensa_insnbuf insn) 38295 { 38296 if (Field_op0_Slot_inst16b_get (insn) == 12) 38297 { 38298 if (Field_i_Slot_inst16b_get (insn) == 0) 38299 return OPCODE_MOVI_N; 38300 if (Field_i_Slot_inst16b_get (insn) == 1) 38301 { 38302 if (Field_z_Slot_inst16b_get (insn) == 0) 38303 return OPCODE_BEQZ_N; 38304 if (Field_z_Slot_inst16b_get (insn) == 1) 38305 return OPCODE_BNEZ_N; 38306 } 38307 } 38308 if (Field_op0_Slot_inst16b_get (insn) == 13) 38309 { 38310 if (Field_r_Slot_inst16b_get (insn) == 0) 38311 return OPCODE_MOV_N; 38312 if (Field_r_Slot_inst16b_get (insn) == 15) 38313 { 38314 if (Field_t_Slot_inst16b_get (insn) == 0) 38315 return OPCODE_RET_N; 38316 if (Field_t_Slot_inst16b_get (insn) == 1) 38317 return OPCODE_RETW_N; 38318 if (Field_t_Slot_inst16b_get (insn) == 2) 38319 return OPCODE_BREAK_N; 38320 if (Field_t_Slot_inst16b_get (insn) == 3 && 38321 Field_s_Slot_inst16b_get (insn) == 0) 38322 return OPCODE_NOP_N; 38323 if (Field_t_Slot_inst16b_get (insn) == 6 && 38324 Field_s_Slot_inst16b_get (insn) == 0) 38325 return OPCODE_ILL_N; 38326 } 38327 } 38328 return XTENSA_UNDEFINED; 38329 } 38330 38331 static int 38332 Slot_inst16a_decode (const xtensa_insnbuf insn) 38333 { 38334 if (Field_op0_Slot_inst16a_get (insn) == 8) 38335 return OPCODE_L32I_N; 38336 if (Field_op0_Slot_inst16a_get (insn) == 9) 38337 return OPCODE_S32I_N; 38338 if (Field_op0_Slot_inst16a_get (insn) == 10) 38339 return OPCODE_ADD_N; 38340 if (Field_op0_Slot_inst16a_get (insn) == 11) 38341 return OPCODE_ADDI_N; 38342 return XTENSA_UNDEFINED; 38343 } 38344 38345 static int 38346 Slot_ae_slot0_decode (const xtensa_insnbuf insn) 38347 { 38348 if (Field_ae_s20_Slot_ae_slot0_get (insn) == 3 && 38349 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && 38350 Field_ftsf378ae_slot0_Slot_ae_slot0_get (insn) == 0) 38351 return OPCODE_BT; 38352 if (Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38353 Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && 38354 Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && 38355 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38356 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && 38357 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38358 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && 38359 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38360 Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) 38361 return OPCODE_AE_SELP24_HH; 38362 if (Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38363 Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && 38364 Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && 38365 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38366 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && 38367 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38368 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && 38369 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38370 Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0) 38371 return OPCODE_AE_SELP24_HL; 38372 if (Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38373 Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && 38374 Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && 38375 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38376 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && 38377 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38378 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && 38379 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38380 Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && 38381 Field_combined2c0b5f72_fld47_Slot_ae_slot0_get (insn) == 0) 38382 return OPCODE_AE_SELP24_LH; 38383 if (Field_combined2c0b5f72_fld123_Slot_ae_slot0_get (insn) == 1 && 38384 Field_combined2c0b5f72_fld121_Slot_ae_slot0_get (insn) == 1 && 38385 Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38386 Field_ftsf315_Slot_ae_slot0_get (insn) == 0 && 38387 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38388 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 2 && 38389 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38390 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38391 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38392 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38393 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38394 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38395 return OPCODE_AE_SLAASQ56S; 38396 if (Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38397 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38398 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38399 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38400 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38401 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38402 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38403 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38404 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38405 return OPCODE_AE_LP16F_C; 38406 if (Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38407 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38408 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38409 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38410 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38411 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38412 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38413 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38414 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38415 return OPCODE_AE_LP16X2F_C; 38416 if (Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38417 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38418 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38419 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38420 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38421 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38422 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38423 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38424 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38425 return OPCODE_AE_LP24_C; 38426 if (Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38427 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38428 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38429 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38430 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38431 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38432 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38433 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38434 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38435 return OPCODE_AE_LP24F_C; 38436 if (Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38437 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38438 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38439 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38440 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38441 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38442 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38443 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38444 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38445 return OPCODE_AE_LP24X2_C; 38446 if (Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38447 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38448 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38449 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38450 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38451 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38452 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38453 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38454 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38455 return OPCODE_AE_LP24X2F_C; 38456 if (Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38457 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38458 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38459 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38460 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38461 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38462 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38463 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38464 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38465 return OPCODE_AE_SP16F_L_C; 38466 if (Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38467 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38468 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38469 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38470 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38471 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38472 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38473 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38474 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38475 return OPCODE_AE_SP16X2F_C; 38476 if (Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38477 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38478 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38479 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38480 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38481 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38482 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38483 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38484 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38485 return OPCODE_AE_SP24F_L_C; 38486 if (Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38487 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38488 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38489 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38490 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38491 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38492 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38493 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38494 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38495 return OPCODE_AE_SP24S_L_C; 38496 if (Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38497 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38498 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38499 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38500 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38501 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38502 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38503 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38504 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38505 return OPCODE_AE_SP24X2F_C; 38506 if (Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38507 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38508 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38509 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38510 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38511 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38512 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38513 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38514 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 38515 return OPCODE_AE_SP24X2S_C; 38516 if (Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38517 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38518 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38519 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38520 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38521 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38522 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38523 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38524 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && 38525 Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) 38526 return OPCODE_AE_SQ32F_C; 38527 if (Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38528 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38529 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38530 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 1 && 38531 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38532 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 1 && 38533 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38534 Field_ftsf362_Slot_ae_slot0_get (insn) == 1 && 38535 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && 38536 Field_combined2c0b5f72_fld46_Slot_ae_slot0_get (insn) == 0) 38537 return OPCODE_AE_SQ56S_C; 38538 if (Field_combined2c0b5f72_fld52_Slot_ae_slot0_get (insn) == 1 && 38539 Field_combined1e9fefee_fld96_Slot_ae_slot0_get (insn) == 1 && 38540 Field_combined1e9fefee_fld98_Slot_ae_slot0_get (insn) == 0 && 38541 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38542 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 0 && 38543 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38544 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 0 && 38545 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38546 Field_op0_s4_s4_s4_Slot_ae_slot0_get (insn) == 0 && 38547 Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get (insn) == 0) 38548 return OPCODE_AE_SELP24_LL; 38549 if (Field_ftsf211ae_slot0_Slot_ae_slot0_get (insn) == 0 && 38550 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38551 return OPCODE_J; 38552 if (Field_ftsf212ae_slot0_Slot_ae_slot0_get (insn) == 1 && 38553 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38554 return OPCODE_EXTUI; 38555 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 && 38556 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38557 return OPCODE_BEQZ; 38558 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 3 && 38559 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38560 return OPCODE_BNEZ; 38561 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 5 && 38562 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38563 return OPCODE_BGEZ; 38564 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 6 && 38565 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38566 return OPCODE_MOVI; 38567 if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 13 && 38568 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38569 return OPCODE_BLTZ; 38570 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 && 38571 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38572 return OPCODE_SRAI; 38573 if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 && 38574 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38575 return OPCODE_SLLI; 38576 if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 43 && 38577 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38578 return OPCODE_AE_CVTP24A16X2_HH; 38579 if (Field_ftsf217ae_slot0_Slot_ae_slot0_get (insn) == 299 && 38580 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38581 return OPCODE_AE_LP16F_I; 38582 if (Field_ftsf218ae_slot0_Slot_ae_slot0_get (insn) == 46 && 38583 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38584 return OPCODE_AE_CVTP24A16X2_HL; 38585 if (Field_ftsf219ae_slot0_Slot_ae_slot0_get (insn) == 47 && 38586 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38587 return OPCODE_AE_LP16F_IU; 38588 if (Field_ftsf220ae_slot0_Slot_ae_slot0_get (insn) == 302 && 38589 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38590 return OPCODE_AE_LP16F_X; 38591 if (Field_ftsf221ae_slot0_Slot_ae_slot0_get (insn) == 303 && 38592 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38593 return OPCODE_AE_LP16F_XU; 38594 if (Field_ftsf222ae_slot0_Slot_ae_slot0_get (insn) == 58 && 38595 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38596 return OPCODE_AE_CVTP24A16X2_LH; 38597 if (Field_ftsf223ae_slot0_Slot_ae_slot0_get (insn) == 59 && 38598 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38599 return OPCODE_AE_LP16X2F_I; 38600 if (Field_ftsf224ae_slot0_Slot_ae_slot0_get (insn) == 62 && 38601 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38602 return OPCODE_AE_LP16X2F_IU; 38603 if (Field_ftsf225ae_slot0_Slot_ae_slot0_get (insn) == 63 && 38604 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38605 return OPCODE_AE_LP16X2F_XU; 38606 if (Field_ftsf226ae_slot0_Slot_ae_slot0_get (insn) == 314 && 38607 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38608 return OPCODE_AE_LP16X2F_X; 38609 if (Field_ftsf227ae_slot0_Slot_ae_slot0_get (insn) == 315 && 38610 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38611 return OPCODE_AE_LP24_I; 38612 if (Field_ftsf228ae_slot0_Slot_ae_slot0_get (insn) == 318 && 38613 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38614 return OPCODE_AE_LP24_IU; 38615 if (Field_ftsf229ae_slot0_Slot_ae_slot0_get (insn) == 319 && 38616 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38617 return OPCODE_AE_LP24_X; 38618 if (Field_ftsf230ae_slot0_Slot_ae_slot0_get (insn) == 170 && 38619 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38620 return OPCODE_AE_CVTP24A16X2_LL; 38621 if (Field_ftsf231ae_slot0_Slot_ae_slot0_get (insn) == 171 && 38622 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38623 return OPCODE_AE_LP24_XU; 38624 if (Field_ftsf232ae_slot0_Slot_ae_slot0_get (insn) == 174 && 38625 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38626 return OPCODE_AE_LP24F_I; 38627 if (Field_ftsf233ae_slot0_Slot_ae_slot0_get (insn) == 175 && 38628 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38629 return OPCODE_AE_LP24F_XU; 38630 if (Field_ftsf234ae_slot0_Slot_ae_slot0_get (insn) == 186 && 38631 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38632 return OPCODE_AE_LP24F_IU; 38633 if (Field_ftsf235ae_slot0_Slot_ae_slot0_get (insn) == 187 && 38634 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38635 return OPCODE_AE_LP24X2_I; 38636 if (Field_ftsf236ae_slot0_Slot_ae_slot0_get (insn) == 190 && 38637 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38638 return OPCODE_AE_LP24X2_IU; 38639 if (Field_ftsf237ae_slot0_Slot_ae_slot0_get (insn) == 191 && 38640 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38641 return OPCODE_AE_LP24X2_X; 38642 if (Field_ftsf238ae_slot0_Slot_ae_slot0_get (insn) == 426 && 38643 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38644 return OPCODE_AE_LP24F_X; 38645 if (Field_ftsf239ae_slot0_Slot_ae_slot0_get (insn) == 427 && 38646 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38647 return OPCODE_AE_LP24X2_XU; 38648 if (Field_ftsf240ae_slot0_Slot_ae_slot0_get (insn) == 430 && 38649 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38650 return OPCODE_AE_LP24X2F_I; 38651 if (Field_ftsf241ae_slot0_Slot_ae_slot0_get (insn) == 431 && 38652 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38653 return OPCODE_AE_LP24X2F_X; 38654 if (Field_ftsf242ae_slot0_Slot_ae_slot0_get (insn) == 442 && 38655 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38656 return OPCODE_AE_LP24X2F_IU; 38657 if (Field_ftsf243ae_slot0_Slot_ae_slot0_get (insn) == 443 && 38658 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38659 return OPCODE_AE_LP24X2F_XU; 38660 if (Field_ftsf244ae_slot0_Slot_ae_slot0_get (insn) == 446 && 38661 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38662 return OPCODE_AE_MOVPA24X2; 38663 if (Field_ftsf245ae_slot0_Slot_ae_slot0_get (insn) == 447 && 38664 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38665 return OPCODE_AE_SP16F_L_I; 38666 if (Field_ftsf246ae_slot0_Slot_ae_slot0_get (insn) == 75 && 38667 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38668 return OPCODE_AE_SP16F_L_IU; 38669 if (Field_ftsf247ae_slot0_Slot_ae_slot0_get (insn) == 331 && 38670 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38671 return OPCODE_AE_SP16X2F_X; 38672 if (Field_ftsf248ae_slot0_Slot_ae_slot0_get (insn) == 78 && 38673 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38674 return OPCODE_AE_SP16F_L_X; 38675 if (Field_ftsf249ae_slot0_Slot_ae_slot0_get (insn) == 79 && 38676 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38677 return OPCODE_AE_SP16X2F_XU; 38678 if (Field_ftsf250ae_slot0_Slot_ae_slot0_get (insn) == 334 && 38679 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38680 return OPCODE_AE_SP24F_L_I; 38681 if (Field_ftsf251ae_slot0_Slot_ae_slot0_get (insn) == 335 && 38682 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38683 return OPCODE_AE_SP24F_L_IU; 38684 if (Field_ftsf252ae_slot0_Slot_ae_slot0_get (insn) == 90 && 38685 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38686 return OPCODE_AE_SP16F_L_XU; 38687 if (Field_ftsf253ae_slot0_Slot_ae_slot0_get (insn) == 91 && 38688 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38689 return OPCODE_AE_SP24F_L_X; 38690 if (Field_ftsf254ae_slot0_Slot_ae_slot0_get (insn) == 94 && 38691 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38692 return OPCODE_AE_SP24F_L_XU; 38693 if (Field_ftsf255ae_slot0_Slot_ae_slot0_get (insn) == 95 && 38694 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38695 return OPCODE_AE_SP24S_L_IU; 38696 if (Field_ftsf256ae_slot0_Slot_ae_slot0_get (insn) == 346 && 38697 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38698 return OPCODE_AE_SP24S_L_I; 38699 if (Field_ftsf257ae_slot0_Slot_ae_slot0_get (insn) == 347 && 38700 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38701 return OPCODE_AE_SP24S_L_X; 38702 if (Field_ftsf258ae_slot0_Slot_ae_slot0_get (insn) == 350 && 38703 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38704 return OPCODE_AE_SP24S_L_XU; 38705 if (Field_ftsf259ae_slot0_Slot_ae_slot0_get (insn) == 351 && 38706 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38707 return OPCODE_AE_SP24X2F_I; 38708 if (Field_ftsf260ae_slot0_Slot_ae_slot0_get (insn) == 106 && 38709 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38710 return OPCODE_AE_SP16X2F_I; 38711 if (Field_ftsf261ae_slot0_Slot_ae_slot0_get (insn) == 107 && 38712 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38713 return OPCODE_AE_SP24X2F_IU; 38714 if (Field_ftsf262ae_slot0_Slot_ae_slot0_get (insn) == 110 && 38715 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38716 return OPCODE_AE_SP24X2F_X; 38717 if (Field_ftsf263ae_slot0_Slot_ae_slot0_get (insn) == 111 && 38718 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38719 return OPCODE_AE_SP24X2S_IU; 38720 if (Field_ftsf264ae_slot0_Slot_ae_slot0_get (insn) == 122 && 38721 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38722 return OPCODE_AE_SP24X2F_XU; 38723 if (Field_ftsf265ae_slot0_Slot_ae_slot0_get (insn) == 123 && 38724 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38725 return OPCODE_AE_SP24X2S_X; 38726 if (Field_ftsf266ae_slot0_Slot_ae_slot0_get (insn) == 126 && 38727 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38728 return OPCODE_AE_SP24X2S_XU; 38729 if (Field_ftsf267ae_slot0_Slot_ae_slot0_get (insn) == 127 && 38730 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38731 return OPCODE_AE_TRUNCP24A32X2; 38732 if (Field_ftsf268ae_slot0_Slot_ae_slot0_get (insn) == 362 && 38733 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38734 return OPCODE_AE_SP24X2S_I; 38735 if (Field_ftsf269ae_slot0_Slot_ae_slot0_get (insn) == 363 && 38736 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38737 return OPCODE_AE_SQ32F_I; 38738 if (Field_ftsf270ae_slot0_Slot_ae_slot0_get (insn) == 875 && 38739 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38740 return OPCODE_AE_SQ32F_XU; 38741 if (Field_ftsf271ae_slot0_Slot_ae_slot0_get (insn) == 366 && 38742 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38743 return OPCODE_AE_SQ32F_IU; 38744 if (Field_ftsf272ae_slot0_Slot_ae_slot0_get (insn) == 367 && 38745 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38746 return OPCODE_AE_SQ56S_I; 38747 if (Field_ftsf273ae_slot0_Slot_ae_slot0_get (insn) == 878 && 38748 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38749 return OPCODE_AE_SQ56S_IU; 38750 if (Field_ftsf274ae_slot0_Slot_ae_slot0_get (insn) == 879 && 38751 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38752 return OPCODE_AE_SQ56S_X; 38753 if (Field_ftsf275ae_slot0_Slot_ae_slot0_get (insn) == 378 && 38754 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38755 return OPCODE_AE_SQ32F_X; 38756 if (Field_ftsf276ae_slot0_Slot_ae_slot0_get (insn) == 379 && 38757 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38758 return OPCODE_AE_SQ56S_XU; 38759 if (Field_ftsf277ae_slot0_Slot_ae_slot0_get (insn) == 890 && 38760 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38761 return OPCODE_AE_NSAQ56S; 38762 if (Field_ftsf278ae_slot0_Slot_ae_slot0_get (insn) == 891 && 38763 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38764 return OPCODE_AE_TRUNCA32Q48; 38765 if (Field_ftsf279ae_slot0_Slot_ae_slot0_get (insn) == 2938 && 38766 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38767 Field_s8_Slot_ae_slot0_get (insn) == 0) 38768 return OPCODE_JX; 38769 if (Field_ftsf280_Slot_ae_slot0_get (insn) == 0 && 38770 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 38771 return OPCODE_BBCI; 38772 if (Field_ftsf280_Slot_ae_slot0_get (insn) == 1 && 38773 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 38774 return OPCODE_BBSI; 38775 if (Field_ftsf281ae_slot0_Slot_ae_slot0_get (insn) == 2939 && 38776 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38777 Field_s8_Slot_ae_slot0_get (insn) == 0) 38778 return OPCODE_SSR; 38779 if (Field_ftsf282ae_slot0_Slot_ae_slot0_get (insn) == 1981 && 38780 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38781 Field_ftsf361ae_slot0_Slot_ae_slot0_get (insn) == 0) 38782 return OPCODE_NOP; 38783 if (Field_ftsf284ae_slot0_Slot_ae_slot0_get (insn) == 957 && 38784 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38785 Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0) 38786 return OPCODE_SSA8B; 38787 if (Field_ftsf285ae_slot0_Slot_ae_slot0_get (insn) == 957 && 38788 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38789 Field_ftsf366ae_slot0_Slot_ae_slot0_get (insn) == 0) 38790 return OPCODE_SSA8L; 38791 if (Field_ftsf287ae_slot0_Slot_ae_slot0_get (insn) == 957 && 38792 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38793 Field_ftsf368ae_slot0_Slot_ae_slot0_get (insn) == 0) 38794 return OPCODE_SSL; 38795 if (Field_ftsf288_Slot_ae_slot0_get (insn) == 1 && 38796 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && 38797 Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) 38798 return OPCODE_BLTUI; 38799 if (Field_ftsf289ae_slot0_Slot_ae_slot0_get (insn) == 382 && 38800 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38801 return OPCODE_AE_CVTA32P24_H; 38802 if (Field_ftsf290ae_slot0_Slot_ae_slot0_get (insn) == 383 && 38803 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38804 return OPCODE_AE_CVTA32P24_L; 38805 if (Field_ftsf291ae_slot0_Slot_ae_slot0_get (insn) == 447 && 38806 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38807 Field_ftsf362_Slot_ae_slot0_get (insn) == 0) 38808 return OPCODE_AE_MOVAP24S_H; 38809 if (Field_ftsf292ae_slot0_Slot_ae_slot0_get (insn) == 447 && 38810 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38811 Field_ftsf382ae_slot0_Slot_ae_slot0_get (insn) == 0) 38812 return OPCODE_AE_MOVAP24S_L; 38813 if (Field_ftsf293ae_slot0_Slot_ae_slot0_get (insn) == 447 && 38814 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38815 Field_ftsf384ae_slot0_Slot_ae_slot0_get (insn) == 0) 38816 return OPCODE_AE_TRUNCA16P24S_H; 38817 if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 447 && 38818 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38819 Field_ftsf383ae_slot0_Slot_ae_slot0_get (insn) == 0) 38820 return OPCODE_AE_TRUNCA16P24S_L; 38821 if (Field_ftsf295ae_slot0_Slot_ae_slot0_get (insn) == 202 && 38822 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38823 return OPCODE_AE_SP16X2F_IU; 38824 if (Field_ftsf296ae_slot0_Slot_ae_slot0_get (insn) == 4298 && 38825 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38826 Field_ftsf315_Slot_ae_slot0_get (insn) == 0) 38827 return OPCODE_AE_MOVP48; 38828 if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 4554 && 38829 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38830 return OPCODE_ALL4; 38831 if (Field_ftsf297ae_slot0_Slot_ae_slot0_get (insn) == 12746 && 38832 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38833 Field_ftsf309_Slot_ae_slot0_get (insn) == 0) 38834 return OPCODE_SSAI; 38835 if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 2506 && 38836 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38837 Field_ftsf373ae_slot0_Slot_ae_slot0_get (insn) == 0) 38838 return OPCODE_ANY4; 38839 if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 1482 && 38840 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38841 Field_ftsf370ae_slot0_Slot_ae_slot0_get (insn) == 0) 38842 return OPCODE_ALL8; 38843 if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 970 && 38844 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38845 Field_ftsf376ae_slot0_Slot_ae_slot0_get (insn) == 0) 38846 return OPCODE_ANY8; 38847 if (Field_ftsf304ae_slot0_Slot_ae_slot0_get (insn) == 203 && 38848 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38849 return OPCODE_AE_LQ32F_I; 38850 if (Field_ftsf305ae_slot0_Slot_ae_slot0_get (insn) == 459 && 38851 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38852 return OPCODE_AE_LQ56_I; 38853 if (Field_ftsf306ae_slot0_Slot_ae_slot0_get (insn) == 715 && 38854 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38855 return OPCODE_AE_LQ56_IU; 38856 if (Field_ftsf307ae_slot0_Slot_ae_slot0_get (insn) == 971 && 38857 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38858 return OPCODE_AE_LQ56_X; 38859 if (Field_ftsf308ae_slot0_Slot_ae_slot0_get (insn) == 206 && 38860 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38861 Field_s8_Slot_ae_slot0_get (insn) == 0) 38862 return OPCODE_AE_LQ32F_IU; 38863 if (Field_ftsf309_Slot_ae_slot0_get (insn) == 1 && 38864 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 38865 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 38866 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 38867 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 38868 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 38869 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 38870 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 38871 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1 && 38872 Field_s8_Slot_ae_slot0_get (insn) == 0) 38873 return OPCODE_AE_LQ56_C; 38874 if (Field_ftsf310ae_slot0_Slot_ae_slot0_get (insn) == 207 && 38875 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38876 Field_s8_Slot_ae_slot0_get (insn) == 0) 38877 return OPCODE_AE_LQ56_XU; 38878 if (Field_ftsf311ae_slot0_Slot_ae_slot0_get (insn) == 231 && 38879 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38880 Field_ftsf386ae_slot0_Slot_ae_slot0_get (insn) == 0) 38881 return OPCODE_AE_CVTQ48A32S; 38882 if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 219 && 38883 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38884 return OPCODE_AE_SLLIQ56; 38885 if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 222 && 38886 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38887 return OPCODE_AE_SLLISQ56S; 38888 if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 475 && 38889 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38890 return OPCODE_AE_SRAIQ56; 38891 if (Field_ftsf312ae_slot0_Slot_ae_slot0_get (insn) == 731 && 38892 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38893 return OPCODE_AE_SRLIQ56; 38894 if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 987 && 38895 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38896 return OPCODE_ABS; 38897 if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 2011 && 38898 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38899 return OPCODE_NEG; 38900 if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 3035 && 38901 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38902 return OPCODE_SRA; 38903 if (Field_ftsf313ae_slot0_Slot_ae_slot0_get (insn) == 4059 && 38904 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38905 return OPCODE_SRL; 38906 if (Field_ftsf314ae_slot0_Slot_ae_slot0_get (insn) == 478 && 38907 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38908 Field_ae_s20_Slot_ae_slot0_get (insn) == 0) 38909 return OPCODE_AE_MOVQ56; 38910 if (Field_ftsf316ae_slot0_Slot_ae_slot0_get (insn) == 1502 && 38911 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38912 Field_ae_s20_Slot_ae_slot0_get (insn) == 0) 38913 return OPCODE_AE_SLLSSQ56S; 38914 if (Field_ftsf317ae_slot0_Slot_ae_slot0_get (insn) == 1502 && 38915 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38916 Field_ftsf389ae_slot0_Slot_ae_slot0_get (insn) == 0) 38917 return OPCODE_AE_SRASQ56; 38918 if (Field_ftsf319ae_slot0_Slot_ae_slot0_get (insn) == 1502 && 38919 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38920 Field_ftsf388ae_slot0_Slot_ae_slot0_get (insn) == 0) 38921 return OPCODE_AE_SRLSQ56; 38922 if (Field_ftsf320ae_slot0_Slot_ae_slot0_get (insn) == 478 && 38923 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38924 Field_ftsf387ae_slot0_Slot_ae_slot0_get (insn) == 0) 38925 return OPCODE_AE_SLLSQ56; 38926 if (Field_ftsf322ae_slot0_Slot_ae_slot0_get (insn) == 223 && 38927 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38928 return OPCODE_AE_MOVFQ56; 38929 if (Field_ftsf323ae_slot0_Slot_ae_slot0_get (insn) == 479 && 38930 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38931 return OPCODE_AE_MOVTQ56; 38932 if (Field_ftsf324ae_slot0_Slot_ae_slot0_get (insn) == 735 && 38933 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38934 return OPCODE_AE_SLLAQ56; 38935 if (Field_ftsf325ae_slot0_Slot_ae_slot0_get (insn) == 991 && 38936 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38937 return OPCODE_AE_SRLAQ56; 38938 if (Field_ftsf326ae_slot0_Slot_ae_slot0_get (insn) == 735 && 38939 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38940 Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) 38941 return OPCODE_AE_SLLASQ56S; 38942 if (Field_ftsf327ae_slot0_Slot_ae_slot0_get (insn) == 991 && 38943 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38944 Field_ftsf363ae_slot0_Slot_ae_slot0_get (insn) == 0) 38945 return OPCODE_SLL; 38946 if (Field_ftsf328ae_slot0_Slot_ae_slot0_get (insn) == 479 && 38947 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38948 Field_ftsf360ae_slot0_Slot_ae_slot0_get (insn) == 0) 38949 return OPCODE_AE_SRAAQ56; 38950 if (Field_ftsf329ae_slot0_Slot_ae_slot0_get (insn) == 31 && 38951 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 38952 Field_ftsf379ae_slot0_Slot_ae_slot0_get (insn) == 0) 38953 return OPCODE_AE_LQ32F_XU; 38954 if (Field_imm8_Slot_ae_slot0_get (insn) == 11 && 38955 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38956 return OPCODE_MOVGEZ; 38957 if (Field_imm8_Slot_ae_slot0_get (insn) == 14 && 38958 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38959 return OPCODE_MOVLTZ; 38960 if (Field_imm8_Slot_ae_slot0_get (insn) == 15 && 38961 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38962 return OPCODE_ORBC; 38963 if (Field_imm8_Slot_ae_slot0_get (insn) == 23 && 38964 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38965 return OPCODE_ADD; 38966 if (Field_imm8_Slot_ae_slot0_get (insn) == 26 && 38967 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38968 return OPCODE_MOVNEZ; 38969 if (Field_imm8_Slot_ae_slot0_get (insn) == 27 && 38970 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38971 return OPCODE_SRLI; 38972 if (Field_imm8_Slot_ae_slot0_get (insn) == 30 && 38973 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38974 return OPCODE_SUB; 38975 if (Field_imm8_Slot_ae_slot0_get (insn) == 31 && 38976 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38977 return OPCODE_SUBX4; 38978 if (Field_imm8_Slot_ae_slot0_get (insn) == 39 && 38979 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38980 return OPCODE_ADDX2; 38981 if (Field_imm8_Slot_ae_slot0_get (insn) == 42 && 38982 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38983 return OPCODE_MOVT; 38984 if (Field_imm8_Slot_ae_slot0_get (insn) == 55 && 38985 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38986 return OPCODE_AND; 38987 if (Field_imm8_Slot_ae_slot0_get (insn) == 71 && 38988 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38989 return OPCODE_ADDX4; 38990 if (Field_imm8_Slot_ae_slot0_get (insn) == 74 && 38991 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38992 return OPCODE_OR; 38993 if (Field_imm8_Slot_ae_slot0_get (insn) == 87 && 38994 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38995 return OPCODE_CLAMPS; 38996 if (Field_imm8_Slot_ae_slot0_get (insn) == 103 && 38997 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 38998 return OPCODE_MAX; 38999 if (Field_imm8_Slot_ae_slot0_get (insn) == 119 && 39000 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39001 return OPCODE_MIN; 39002 if (Field_imm8_Slot_ae_slot0_get (insn) == 139 && 39003 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39004 return OPCODE_ORB; 39005 if (Field_imm8_Slot_ae_slot0_get (insn) == 142 && 39006 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39007 return OPCODE_SEXT; 39008 if (Field_imm8_Slot_ae_slot0_get (insn) == 143 && 39009 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39010 return OPCODE_SRC; 39011 if (Field_imm8_Slot_ae_slot0_get (insn) == 151 && 39012 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39013 return OPCODE_ADDX8; 39014 if (Field_imm8_Slot_ae_slot0_get (insn) == 154 && 39015 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39016 return OPCODE_SUBX2; 39017 if (Field_imm8_Slot_ae_slot0_get (insn) == 155 && 39018 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39019 return OPCODE_SUBX8; 39020 if (Field_imm8_Slot_ae_slot0_get (insn) == 158 && 39021 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39022 return OPCODE_XOR; 39023 if (Field_imm8_Slot_ae_slot0_get (insn) == 159 && 39024 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39025 return OPCODE_XORB; 39026 if (Field_imm8_Slot_ae_slot0_get (insn) == 167 && 39027 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39028 return OPCODE_ANDB; 39029 if (Field_imm8_Slot_ae_slot0_get (insn) == 183 && 39030 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39031 return OPCODE_ANDBC; 39032 if (Field_imm8_Slot_ae_slot0_get (insn) == 199 && 39033 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39034 return OPCODE_MAXU; 39035 if (Field_imm8_Slot_ae_slot0_get (insn) == 215 && 39036 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39037 return OPCODE_MINU; 39038 if (Field_imm8_Slot_ae_slot0_get (insn) == 218 && 39039 Field_op0_s4_Slot_ae_slot0_get (insn) == 1 && 39040 Field_ae_r10_Slot_ae_slot0_get (insn) == 0) 39041 return OPCODE_AE_LQ32F_X; 39042 if (Field_imm8_Slot_ae_slot0_get (insn) == 231 && 39043 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39044 return OPCODE_MOVEQZ; 39045 if (Field_imm8_Slot_ae_slot0_get (insn) == 247 && 39046 Field_op0_s4_Slot_ae_slot0_get (insn) == 1) 39047 return OPCODE_MOVF; 39048 if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5) 39049 return OPCODE_L32R; 39050 if (Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 0 && 39051 Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get (insn) == 0) 39052 return OPCODE_AE_ADDBRBA32; 39053 if (Field_r_Slot_ae_slot0_get (insn) == 0 && 39054 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39055 return OPCODE_BNE; 39056 if (Field_r_Slot_ae_slot0_get (insn) == 1 && 39057 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39058 return OPCODE_BNONE; 39059 if (Field_r_Slot_ae_slot0_get (insn) == 2 && 39060 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39061 return OPCODE_ADDI; 39062 if (Field_r_Slot_ae_slot0_get (insn) == 2 && 39063 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39064 return OPCODE_L16SI; 39065 if (Field_r_Slot_ae_slot0_get (insn) == 3 && 39066 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39067 return OPCODE_BALL; 39068 if (Field_r_Slot_ae_slot0_get (insn) == 3 && 39069 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39070 return OPCODE_L8UI; 39071 if (Field_r_Slot_ae_slot0_get (insn) == 4 && 39072 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39073 return OPCODE_ADDMI; 39074 if (Field_r_Slot_ae_slot0_get (insn) == 4 && 39075 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39076 return OPCODE_L16UI; 39077 if (Field_r_Slot_ae_slot0_get (insn) == 5 && 39078 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39079 return OPCODE_BBS; 39080 if (Field_r_Slot_ae_slot0_get (insn) == 5 && 39081 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39082 return OPCODE_S16I; 39083 if (Field_r_Slot_ae_slot0_get (insn) == 6 && 39084 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39085 return OPCODE_BEQ; 39086 if (Field_r_Slot_ae_slot0_get (insn) == 6 && 39087 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39088 return OPCODE_S32I; 39089 if (Field_r_Slot_ae_slot0_get (insn) == 7 && 39090 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39091 return OPCODE_BGEU; 39092 if (Field_r_Slot_ae_slot0_get (insn) == 7 && 39093 Field_op0_s4_Slot_ae_slot0_get (insn) == 4) 39094 return OPCODE_S8I; 39095 if (Field_r_Slot_ae_slot0_get (insn) == 10 && 39096 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39097 return OPCODE_BANY; 39098 if (Field_r_Slot_ae_slot0_get (insn) == 11 && 39099 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39100 return OPCODE_BBC; 39101 if (Field_r_Slot_ae_slot0_get (insn) == 12 && 39102 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39103 return OPCODE_BGE; 39104 if (Field_r_Slot_ae_slot0_get (insn) == 13 && 39105 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39106 return OPCODE_BLT; 39107 if (Field_r_Slot_ae_slot0_get (insn) == 14 && 39108 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39109 return OPCODE_BLTU; 39110 if (Field_r_Slot_ae_slot0_get (insn) == 15 && 39111 Field_op0_s4_Slot_ae_slot0_get (insn) == 2) 39112 return OPCODE_BNALL; 39113 if (Field_s8_Slot_ae_slot0_get (insn) == 1 && 39114 Field_op0_s4_Slot_ae_slot0_get (insn) == 4 && 39115 Field_ftsf280_Slot_ae_slot0_get (insn) == 0) 39116 return OPCODE_L32I; 39117 if (Field_s8_Slot_ae_slot0_get (insn) == 1 && 39118 Field_ftsf309_Slot_ae_slot0_get (insn) == 0 && 39119 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get (insn) == 1 && 39120 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get (insn) == 3 && 39121 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get (insn) == 0 && 39122 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get (insn) == 1 && 39123 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get (insn) == 0 && 39124 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get (insn) == 1 && 39125 Field_ftsf362_Slot_ae_slot0_get (insn) == 0 && 39126 Field_op0_s4_s4_Slot_ae_slot0_get (insn) == 1) 39127 return OPCODE_AE_LQ32F_C; 39128 if (Field_t_Slot_ae_slot0_get (insn) == 0 && 39129 Field_op0_s4_Slot_ae_slot0_get (insn) == 3) 39130 return OPCODE_BEQI; 39131 if (Field_t_Slot_ae_slot0_get (insn) == 1 && 39132 Field_op0_s4_Slot_ae_slot0_get (insn) == 3) 39133 return OPCODE_BGEI; 39134 if (Field_t_Slot_ae_slot0_get (insn) == 2 && 39135 Field_op0_s4_Slot_ae_slot0_get (insn) == 3) 39136 return OPCODE_BGEUI; 39137 if (Field_t_Slot_ae_slot0_get (insn) == 3 && 39138 Field_op0_s4_Slot_ae_slot0_get (insn) == 3) 39139 return OPCODE_BNEI; 39140 if (Field_t_Slot_ae_slot0_get (insn) == 4 && 39141 Field_op0_s4_Slot_ae_slot0_get (insn) == 3) 39142 return OPCODE_BLTI; 39143 if (Field_t_Slot_ae_slot0_get (insn) == 5 && 39144 Field_op0_s4_Slot_ae_slot0_get (insn) == 3 && 39145 Field_r_Slot_ae_slot0_get (insn) == 0) 39146 return OPCODE_BF; 39147 return XTENSA_UNDEFINED; 39148 } 39149 39150 static int 39151 Slot_ae_slot1_decode (const xtensa_insnbuf insn) 39152 { 39153 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 50 && 39154 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39155 return OPCODE_AE_MULFQ32SP24S_L; 39156 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 82 && 39157 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39158 return OPCODE_AE_MULARFQ32SP24S_L; 39159 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 114 && 39160 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39161 return OPCODE_AE_MULSFQ32SP24S_L; 39162 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 146 && 39163 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39164 return OPCODE_AE_MULRFQ32SP24S_L; 39165 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 178 && 39166 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39167 return OPCODE_AE_MULAFQ32SP24S_L; 39168 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 210 && 39169 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39170 return OPCODE_AE_MULSRFQ32SP24S_L; 39171 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 274 && 39172 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39173 return OPCODE_AE_MULRFQ32SP24S_H; 39174 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 306 && 39175 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39176 return OPCODE_AE_MULAFQ32SP24S_H; 39177 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 338 && 39178 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39179 return OPCODE_AE_MULSRFQ32SP24S_H; 39180 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 402 && 39181 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39182 return OPCODE_AE_MULARFQ32SP24S_H; 39183 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 434 && 39184 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39185 return OPCODE_AE_MULSFQ32SP24S_H; 39186 if (Field_ae_mul32x24fld_Slot_ae_slot1_get (insn) == 466 && 39187 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39188 return OPCODE_AE_MULFQ32SP24S_H; 39189 if (Field_ae_r20_Slot_ae_slot1_get (insn) == 1 && 39190 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39191 Field_ftsf343ae_slot1_Slot_ae_slot1_get (insn) == 0) 39192 return OPCODE_AE_LTQ56S; 39193 if (Field_ae_s20_Slot_ae_slot1_get (insn) == 3 && 39194 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && 39195 Field_ftsf340ae_slot1_Slot_ae_slot1_get (insn) == 0) 39196 return OPCODE_AE_MULZAAP24S_HL_LH; 39197 if (Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39198 Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && 39199 Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && 39200 Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && 39201 Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && 39202 Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && 39203 Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) 39204 return OPCODE_AE_MAXABSSP24S; 39205 if (Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39206 Field_combined2c0b5f72_fld69_Slot_ae_slot1_get (insn) == 1 && 39207 Field_ftsf91_Slot_ae_slot1_get (insn) == 1 && 39208 Field_combined2c0b5f72_fld68_Slot_ae_slot1_get (insn) == 2 && 39209 Field_combined2c0b5f72_fld19_Slot_ae_slot1_get (insn) == 0 && 39210 Field_combined2c0b5f72_fld22_Slot_ae_slot1_get (insn) == 0 && 39211 Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 1) 39212 return OPCODE_AE_MINABSSP24S; 39213 if (Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 1 && 39214 Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39215 Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && 39216 Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39217 Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && 39218 Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && 39219 Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && 39220 Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && 39221 Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && 39222 Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5 && 39223 Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get (insn) == 0) 39224 return OPCODE_AE_MINABSSQ56S; 39225 if (Field_combined2c0b5f72_fld79_Slot_ae_slot1_get (insn) == 1 && 39226 Field_combined2c0b5f72_fld74_Slot_ae_slot1_get (insn) == 0 && 39227 Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39228 Field_combined2c0b5f72_fld66_Slot_ae_slot1_get (insn) == 0 && 39229 Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39230 Field_combined2c0b5f72_fld91_Slot_ae_slot1_get (insn) == 0 && 39231 Field_combined2c0b5f72_fld90_Slot_ae_slot1_get (insn) == 0 && 39232 Field_combined2c0b5f72_fld88_Slot_ae_slot1_get (insn) == 0 && 39233 Field_combined2c0b5f72_fld65_Slot_ae_slot1_get (insn) == 0 && 39234 Field_combined2c0b5f72_fld24_Slot_ae_slot1_get (insn) == 0 && 39235 Field_op0_s3_s3_Slot_ae_slot1_get (insn) == 5) 39236 return OPCODE_AE_MAXABSSQ56S; 39237 if (Field_ftsf101ae_slot1_Slot_ae_slot1_get (insn) == 43 && 39238 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39239 Field_ftsf335_Slot_ae_slot1_get (insn) == 0) 39240 return OPCODE_AE_MULSQ32SP16U_H; 39241 if (Field_ftsf102ae_slot1_Slot_ae_slot1_get (insn) == 7 && 39242 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39243 Field_ftsf336ae_slot1_Slot_ae_slot1_get (insn) == 0) 39244 return OPCODE_AE_MULSFQ32SP16U_H; 39245 if (Field_ftsf103ae_slot1_Slot_ae_slot1_get (insn) == 3 && 39246 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39247 Field_ftsf337ae_slot1_Slot_ae_slot1_get (insn) == 0) 39248 return OPCODE_AE_MULAFQ32SP16S_H; 39249 if (Field_ftsf106ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39250 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39251 return OPCODE_AE_MAXBQ56S; 39252 if (Field_ftsf107ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39253 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39254 return OPCODE_AE_MINBQ56S; 39255 if (Field_ftsf108ae_slot1_Slot_ae_slot1_get (insn) == 2 && 39256 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39257 Field_ae_r32_Slot_ae_slot1_get (insn) == 0) 39258 return OPCODE_AE_EQQ56; 39259 if (Field_ftsf109ae_slot1_Slot_ae_slot1_get (insn) == 3 && 39260 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39261 return OPCODE_AE_ADDSQ56S; 39262 if (Field_ftsf110ae_slot1_Slot_ae_slot1_get (insn) == 67 && 39263 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39264 return OPCODE_AE_ANDQ56; 39265 if (Field_ftsf111ae_slot1_Slot_ae_slot1_get (insn) == 131 && 39266 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39267 return OPCODE_AE_MAXQ56S; 39268 if (Field_ftsf112ae_slot1_Slot_ae_slot1_get (insn) == 195 && 39269 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39270 return OPCODE_AE_ORQ56; 39271 if (Field_ftsf113ae_slot1_Slot_ae_slot1_get (insn) == 259 && 39272 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39273 return OPCODE_AE_MINQ56S; 39274 if (Field_ftsf114ae_slot1_Slot_ae_slot1_get (insn) == 323 && 39275 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39276 return OPCODE_AE_SUBQ56; 39277 if (Field_ftsf115ae_slot1_Slot_ae_slot1_get (insn) == 387 && 39278 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39279 return OPCODE_AE_SUBSQ56S; 39280 if (Field_ftsf116ae_slot1_Slot_ae_slot1_get (insn) == 451 && 39281 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39282 return OPCODE_AE_XORQ56; 39283 if (Field_ftsf117ae_slot1_Slot_ae_slot1_get (insn) == 515 && 39284 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39285 return OPCODE_AE_NANDQ56; 39286 if (Field_ftsf118ae_slot1_Slot_ae_slot1_get (insn) == 2307 && 39287 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39288 return OPCODE_AE_ABSQ56; 39289 if (Field_ftsf120ae_slot1_Slot_ae_slot1_get (insn) == 2315 && 39290 Field_op0_s3_Slot_ae_slot1_get (insn) == 5) 39291 return OPCODE_AE_NEGSQ56S; 39292 if (Field_ftsf121ae_slot1_Slot_ae_slot1_get (insn) == 1163 && 39293 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39294 Field_ftsf91_Slot_ae_slot1_get (insn) == 0) 39295 return OPCODE_AE_SATQ48S; 39296 if (Field_ftsf123ae_slot1_Slot_ae_slot1_get (insn) == 323 && 39297 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39298 Field_ftsf349ae_slot1_Slot_ae_slot1_get (insn) == 0) 39299 return OPCODE_AE_ABSSQ56S; 39300 if (Field_ftsf124ae_slot1_Slot_ae_slot1_get (insn) == 195 && 39301 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39302 Field_ftsf352ae_slot1_Slot_ae_slot1_get (insn) == 0) 39303 return OPCODE_AE_NEGQ56; 39304 if (Field_ftsf125ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39305 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39306 Field_ftsf342ae_slot1_Slot_ae_slot1_get (insn) == 0) 39307 return OPCODE_AE_LEQ56S; 39308 if (Field_ftsf126ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39309 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39310 Field_ftsf357ae_slot1_Slot_ae_slot1_get (insn) == 0) 39311 return OPCODE_AE_TRUNCP24Q48X2; 39312 if (Field_ftsf127ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39313 Field_op0_s3_Slot_ae_slot1_get (insn) == 5 && 39314 Field_ftsf350ae_slot1_Slot_ae_slot1_get (insn) == 0) 39315 return OPCODE_AE_ADDQ56; 39316 if (Field_ftsf128ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39317 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39318 return OPCODE_AE_MULAAFP24S_HH_LL; 39319 if (Field_ftsf129ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39320 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39321 return OPCODE_AE_MULAAFP24S_HL_LH; 39322 if (Field_ftsf130ae_slot1_Slot_ae_slot1_get (insn) == 2 && 39323 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39324 return OPCODE_AE_MULAAP24S_HH_LL; 39325 if (Field_ftsf131ae_slot1_Slot_ae_slot1_get (insn) == 3 && 39326 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39327 return OPCODE_AE_MULAFS32P16S_HL; 39328 if (Field_ftsf132ae_slot1_Slot_ae_slot1_get (insn) == 4 && 39329 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39330 return OPCODE_AE_MULAAP24S_HL_LH; 39331 if (Field_ftsf133ae_slot1_Slot_ae_slot1_get (insn) == 5 && 39332 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39333 return OPCODE_AE_MULAFS32P16S_LH; 39334 if (Field_ftsf134ae_slot1_Slot_ae_slot1_get (insn) == 6 && 39335 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39336 return OPCODE_AE_MULAFS32P16S_LL; 39337 if (Field_ftsf135ae_slot1_Slot_ae_slot1_get (insn) == 7 && 39338 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39339 return OPCODE_AE_MULAFS56P24S_HH; 39340 if (Field_ftsf136ae_slot1_Slot_ae_slot1_get (insn) == 8 && 39341 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39342 return OPCODE_AE_MULAFP24S_HH; 39343 if (Field_ftsf137ae_slot1_Slot_ae_slot1_get (insn) == 9 && 39344 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39345 return OPCODE_AE_MULAFS56P24S_HL; 39346 if (Field_ftsf138ae_slot1_Slot_ae_slot1_get (insn) == 10 && 39347 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39348 return OPCODE_AE_MULAFS56P24S_LH; 39349 if (Field_ftsf139ae_slot1_Slot_ae_slot1_get (insn) == 11 && 39350 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39351 return OPCODE_AE_MULAP24S_HH; 39352 if (Field_ftsf140ae_slot1_Slot_ae_slot1_get (insn) == 12 && 39353 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39354 return OPCODE_AE_MULAFS56P24S_LL; 39355 if (Field_ftsf141ae_slot1_Slot_ae_slot1_get (insn) == 13 && 39356 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39357 return OPCODE_AE_MULAP24S_HL; 39358 if (Field_ftsf142ae_slot1_Slot_ae_slot1_get (insn) == 14 && 39359 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39360 return OPCODE_AE_MULAP24S_LH; 39361 if (Field_ftsf143ae_slot1_Slot_ae_slot1_get (insn) == 15 && 39362 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39363 return OPCODE_AE_MULAP24S_LL; 39364 if (Field_ftsf144ae_slot1_Slot_ae_slot1_get (insn) == 16 && 39365 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39366 return OPCODE_AE_MULAFP24S_HL; 39367 if (Field_ftsf145ae_slot1_Slot_ae_slot1_get (insn) == 17 && 39368 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39369 return OPCODE_AE_MULAS56P24S_HH; 39370 if (Field_ftsf146ae_slot1_Slot_ae_slot1_get (insn) == 18 && 39371 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39372 return OPCODE_AE_MULAS56P24S_HL; 39373 if (Field_ftsf147ae_slot1_Slot_ae_slot1_get (insn) == 19 && 39374 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39375 return OPCODE_AE_MULASFP24S_HH_LL; 39376 if (Field_ftsf148ae_slot1_Slot_ae_slot1_get (insn) == 20 && 39377 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39378 return OPCODE_AE_MULAS56P24S_LH; 39379 if (Field_ftsf149ae_slot1_Slot_ae_slot1_get (insn) == 21 && 39380 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39381 return OPCODE_AE_MULASFP24S_HL_LH; 39382 if (Field_ftsf150ae_slot1_Slot_ae_slot1_get (insn) == 22 && 39383 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39384 return OPCODE_AE_MULASP24S_HH_LL; 39385 if (Field_ftsf151ae_slot1_Slot_ae_slot1_get (insn) == 23 && 39386 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39387 return OPCODE_AE_MULASP24S_HL_LH; 39388 if (Field_ftsf152ae_slot1_Slot_ae_slot1_get (insn) == 24 && 39389 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39390 return OPCODE_AE_MULAS56P24S_LL; 39391 if (Field_ftsf153ae_slot1_Slot_ae_slot1_get (insn) == 25 && 39392 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39393 return OPCODE_AE_MULFP24S_HH; 39394 if (Field_ftsf154ae_slot1_Slot_ae_slot1_get (insn) == 26 && 39395 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39396 return OPCODE_AE_MULFP24S_HL; 39397 if (Field_ftsf155ae_slot1_Slot_ae_slot1_get (insn) == 27 && 39398 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39399 return OPCODE_AE_MULFP24S_LL; 39400 if (Field_ftsf156ae_slot1_Slot_ae_slot1_get (insn) == 28 && 39401 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39402 return OPCODE_AE_MULFP24S_LH; 39403 if (Field_ftsf157ae_slot1_Slot_ae_slot1_get (insn) == 29 && 39404 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39405 return OPCODE_AE_MULFS32P16S_HH; 39406 if (Field_ftsf158ae_slot1_Slot_ae_slot1_get (insn) == 30 && 39407 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39408 return OPCODE_AE_MULFS32P16S_HL; 39409 if (Field_ftsf159ae_slot1_Slot_ae_slot1_get (insn) == 31 && 39410 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39411 return OPCODE_AE_MULFS32P16S_LH; 39412 if (Field_ftsf160ae_slot1_Slot_ae_slot1_get (insn) == 32 && 39413 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39414 return OPCODE_AE_MULAFP24S_LH; 39415 if (Field_ftsf161ae_slot1_Slot_ae_slot1_get (insn) == 33 && 39416 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39417 return OPCODE_AE_MULFS32P16S_LL; 39418 if (Field_ftsf162ae_slot1_Slot_ae_slot1_get (insn) == 34 && 39419 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39420 return OPCODE_AE_MULP24S_HH; 39421 if (Field_ftsf163ae_slot1_Slot_ae_slot1_get (insn) == 35 && 39422 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39423 return OPCODE_AE_MULSAFP24S_HH_LL; 39424 if (Field_ftsf164ae_slot1_Slot_ae_slot1_get (insn) == 36 && 39425 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39426 return OPCODE_AE_MULP24S_HL; 39427 if (Field_ftsf165ae_slot1_Slot_ae_slot1_get (insn) == 37 && 39428 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39429 return OPCODE_AE_MULSAFP24S_HL_LH; 39430 if (Field_ftsf166ae_slot1_Slot_ae_slot1_get (insn) == 38 && 39431 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39432 return OPCODE_AE_MULSAP24S_HH_LL; 39433 if (Field_ftsf167ae_slot1_Slot_ae_slot1_get (insn) == 39 && 39434 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39435 return OPCODE_AE_MULSAP24S_HL_LH; 39436 if (Field_ftsf168ae_slot1_Slot_ae_slot1_get (insn) == 40 && 39437 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39438 return OPCODE_AE_MULP24S_LH; 39439 if (Field_ftsf169ae_slot1_Slot_ae_slot1_get (insn) == 41 && 39440 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39441 return OPCODE_AE_MULSFP24S_HH; 39442 if (Field_ftsf170ae_slot1_Slot_ae_slot1_get (insn) == 42 && 39443 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39444 return OPCODE_AE_MULSFP24S_HL; 39445 if (Field_ftsf171ae_slot1_Slot_ae_slot1_get (insn) == 43 && 39446 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39447 return OPCODE_AE_MULSFP24S_LL; 39448 if (Field_ftsf172ae_slot1_Slot_ae_slot1_get (insn) == 44 && 39449 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39450 return OPCODE_AE_MULSFP24S_LH; 39451 if (Field_ftsf173ae_slot1_Slot_ae_slot1_get (insn) == 45 && 39452 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39453 return OPCODE_AE_MULSFS32P16S_HH; 39454 if (Field_ftsf174ae_slot1_Slot_ae_slot1_get (insn) == 46 && 39455 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39456 return OPCODE_AE_MULSFS32P16S_HL; 39457 if (Field_ftsf175ae_slot1_Slot_ae_slot1_get (insn) == 47 && 39458 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39459 return OPCODE_AE_MULSFS32P16S_LH; 39460 if (Field_ftsf176ae_slot1_Slot_ae_slot1_get (insn) == 48 && 39461 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39462 return OPCODE_AE_MULP24S_LL; 39463 if (Field_ftsf177ae_slot1_Slot_ae_slot1_get (insn) == 49 && 39464 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39465 return OPCODE_AE_MULSFS32P16S_LL; 39466 if (Field_ftsf178ae_slot1_Slot_ae_slot1_get (insn) == 50 && 39467 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39468 return OPCODE_AE_MULSFS56P24S_HH; 39469 if (Field_ftsf179ae_slot1_Slot_ae_slot1_get (insn) == 51 && 39470 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39471 return OPCODE_AE_MULSFS56P24S_LL; 39472 if (Field_ftsf180ae_slot1_Slot_ae_slot1_get (insn) == 52 && 39473 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39474 return OPCODE_AE_MULSFS56P24S_HL; 39475 if (Field_ftsf181ae_slot1_Slot_ae_slot1_get (insn) == 53 && 39476 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39477 return OPCODE_AE_MULSP24S_HH; 39478 if (Field_ftsf182ae_slot1_Slot_ae_slot1_get (insn) == 54 && 39479 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39480 return OPCODE_AE_MULSP24S_HL; 39481 if (Field_ftsf183ae_slot1_Slot_ae_slot1_get (insn) == 55 && 39482 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39483 return OPCODE_AE_MULSP24S_LH; 39484 if (Field_ftsf184ae_slot1_Slot_ae_slot1_get (insn) == 56 && 39485 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39486 return OPCODE_AE_MULSFS56P24S_LH; 39487 if (Field_ftsf185ae_slot1_Slot_ae_slot1_get (insn) == 57 && 39488 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39489 return OPCODE_AE_MULSP24S_LL; 39490 if (Field_ftsf186ae_slot1_Slot_ae_slot1_get (insn) == 58 && 39491 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39492 return OPCODE_AE_MULSS56P24S_HH; 39493 if (Field_ftsf187ae_slot1_Slot_ae_slot1_get (insn) == 59 && 39494 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39495 return OPCODE_AE_MULSS56P24S_LH; 39496 if (Field_ftsf188ae_slot1_Slot_ae_slot1_get (insn) == 60 && 39497 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39498 return OPCODE_AE_MULSS56P24S_HL; 39499 if (Field_ftsf189ae_slot1_Slot_ae_slot1_get (insn) == 61 && 39500 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39501 return OPCODE_AE_MULSS56P24S_LL; 39502 if (Field_ftsf190ae_slot1_Slot_ae_slot1_get (insn) == 62 && 39503 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39504 return OPCODE_AE_MULSSFP24S_HH_LL; 39505 if (Field_ftsf191ae_slot1_Slot_ae_slot1_get (insn) == 63 && 39506 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39507 return OPCODE_AE_MULSSFP24S_HL_LH; 39508 if (Field_ftsf192ae_slot1_Slot_ae_slot1_get (insn) == 64 && 39509 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39510 return OPCODE_AE_MULAFP24S_LL; 39511 if (Field_ftsf193ae_slot1_Slot_ae_slot1_get (insn) == 65 && 39512 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39513 return OPCODE_AE_MULSSP24S_HH_LL; 39514 if (Field_ftsf194ae_slot1_Slot_ae_slot1_get (insn) == 66 && 39515 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39516 return OPCODE_AE_MULSSP24S_HL_LH; 39517 if (Field_ftsf195ae_slot1_Slot_ae_slot1_get (insn) == 67 && 39518 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39519 return OPCODE_AE_MULZASFP24S_HH_LL; 39520 if (Field_ftsf196ae_slot1_Slot_ae_slot1_get (insn) == 68 && 39521 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39522 return OPCODE_AE_MULZAAFP24S_HH_LL; 39523 if (Field_ftsf197ae_slot1_Slot_ae_slot1_get (insn) == 69 && 39524 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39525 return OPCODE_AE_MULZASFP24S_HL_LH; 39526 if (Field_ftsf198ae_slot1_Slot_ae_slot1_get (insn) == 70 && 39527 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39528 return OPCODE_AE_MULZASP24S_HH_LL; 39529 if (Field_ftsf199ae_slot1_Slot_ae_slot1_get (insn) == 71 && 39530 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39531 return OPCODE_AE_MULZASP24S_HL_LH; 39532 if (Field_ftsf200ae_slot1_Slot_ae_slot1_get (insn) == 72 && 39533 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39534 return OPCODE_AE_MULZAAFP24S_HL_LH; 39535 if (Field_ftsf201ae_slot1_Slot_ae_slot1_get (insn) == 73 && 39536 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39537 return OPCODE_AE_MULZSAFP24S_HH_LL; 39538 if (Field_ftsf202ae_slot1_Slot_ae_slot1_get (insn) == 74 && 39539 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39540 return OPCODE_AE_MULZSAFP24S_HL_LH; 39541 if (Field_ftsf203ae_slot1_Slot_ae_slot1_get (insn) == 75 && 39542 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39543 return OPCODE_AE_MULZSAP24S_HL_LH; 39544 if (Field_ftsf204ae_slot1_Slot_ae_slot1_get (insn) == 76 && 39545 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39546 return OPCODE_AE_MULZSAP24S_HH_LL; 39547 if (Field_ftsf205ae_slot1_Slot_ae_slot1_get (insn) == 77 && 39548 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39549 return OPCODE_AE_MULZSSFP24S_HH_LL; 39550 if (Field_ftsf206ae_slot1_Slot_ae_slot1_get (insn) == 78 && 39551 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39552 return OPCODE_AE_MULZSSFP24S_HL_LH; 39553 if (Field_ftsf207ae_slot1_Slot_ae_slot1_get (insn) == 79 && 39554 Field_op0_s3_Slot_ae_slot1_get (insn) == 6) 39555 return OPCODE_AE_MULZSSP24S_HH_LL; 39556 if (Field_ftsf208ae_slot1_Slot_ae_slot1_get (insn) == 10 && 39557 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && 39558 Field_ftsf341ae_slot1_Slot_ae_slot1_get (insn) == 0) 39559 return OPCODE_AE_MULZAAP24S_HH_LL; 39560 if (Field_ftsf20ae_slot1_Slot_ae_slot1_get (insn) == 0 && 39561 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39562 return OPCODE_AE_MAXBP24S; 39563 if (Field_ftsf210ae_slot1_Slot_ae_slot1_get (insn) == 11 && 39564 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && 39565 Field_ftsf339ae_slot1_Slot_ae_slot1_get (insn) == 0) 39566 return OPCODE_AE_MULZSSP24S_HL_LH; 39567 if (Field_ftsf21ae_slot1_Slot_ae_slot1_get (insn) == 1 && 39568 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39569 return OPCODE_AE_MINBP24S; 39570 if (Field_ftsf22ae_slot1_Slot_ae_slot1_get (insn) == 4 && 39571 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39572 return OPCODE_AE_MOVFP48; 39573 if (Field_ftsf23ae_slot1_Slot_ae_slot1_get (insn) == 5 && 39574 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39575 return OPCODE_AE_ADDP24; 39576 if (Field_ftsf24ae_slot1_Slot_ae_slot1_get (insn) == 69 && 39577 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39578 return OPCODE_AE_MAXP24S; 39579 if (Field_ftsf25ae_slot1_Slot_ae_slot1_get (insn) == 20 && 39580 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39581 return OPCODE_AE_ADDSP24S; 39582 if (Field_ftsf26ae_slot1_Slot_ae_slot1_get (insn) == 21 && 39583 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39584 return OPCODE_AE_MINP24S; 39585 if (Field_ftsf27ae_slot1_Slot_ae_slot1_get (insn) == 84 && 39586 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39587 return OPCODE_AE_NANDP48; 39588 if (Field_ftsf28ae_slot1_Slot_ae_slot1_get (insn) == 85 && 39589 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39590 return OPCODE_AE_ORP48; 39591 if (Field_ftsf29ae_slot1_Slot_ae_slot1_get (insn) == 36 && 39592 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39593 return OPCODE_AE_ANDP48; 39594 if (Field_ftsf30ae_slot1_Slot_ae_slot1_get (insn) == 37 && 39595 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39596 return OPCODE_AE_SELP24_HH; 39597 if (Field_ftsf31ae_slot1_Slot_ae_slot1_get (insn) == 52 && 39598 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39599 return OPCODE_AE_SELP24_HL; 39600 if (Field_ftsf32ae_slot1_Slot_ae_slot1_get (insn) == 53 && 39601 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39602 return OPCODE_AE_SELP24_LL; 39603 if (Field_ftsf33ae_slot1_Slot_ae_slot1_get (insn) == 100 && 39604 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39605 return OPCODE_AE_SELP24_LH; 39606 if (Field_ftsf34ae_slot1_Slot_ae_slot1_get (insn) == 101 && 39607 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39608 return OPCODE_AE_SUBP24; 39609 if (Field_ftsf35ae_slot1_Slot_ae_slot1_get (insn) == 116 && 39610 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39611 return OPCODE_AE_SUBSP24S; 39612 if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 117 && 39613 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39614 return OPCODE_AE_XORP48; 39615 if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 && 39616 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39617 return OPCODE_AE_MOVTP48; 39618 if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 24 && 39619 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39620 return OPCODE_AE_ABSP24; 39621 if (Field_ftsf40ae_slot1_Slot_ae_slot1_get (insn) == 88 && 39622 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39623 return OPCODE_AE_NEGP24; 39624 if (Field_ftsf41ae_slot1_Slot_ae_slot1_get (insn) == 152 && 39625 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39626 return OPCODE_AE_NEGSP24S; 39627 if (Field_ftsf42ae_slot1_Slot_ae_slot1_get (insn) == 216 && 39628 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39629 Field_ftsf333ae_slot1_Slot_ae_slot1_get (insn) == 0) 39630 return OPCODE_NOP; 39631 if (Field_ftsf43ae_slot1_Slot_ae_slot1_get (insn) == 88 && 39632 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39633 Field_ftsf359ae_slot1_Slot_ae_slot1_get (insn) == 0) 39634 return OPCODE_AE_ZEROP48; 39635 if (Field_ftsf45ae_slot1_Slot_ae_slot1_get (insn) == 704 && 39636 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39637 return OPCODE_AE_MOVP48; 39638 if (Field_ftsf47ae_slot1_Slot_ae_slot1_get (insn) == 708 && 39639 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39640 return OPCODE_AE_ROUNDSP16ASYM; 39641 if (Field_ftsf48ae_slot1_Slot_ae_slot1_get (insn) == 712 && 39642 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39643 return OPCODE_AE_ROUNDSP16SYM; 39644 if (Field_ftsf49ae_slot1_Slot_ae_slot1_get (insn) == 716 && 39645 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39646 return OPCODE_AE_SLLSSP24S; 39647 if (Field_ftsf50ae_slot1_Slot_ae_slot1_get (insn) == 720 && 39648 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39649 return OPCODE_AE_SLLSP24; 39650 if (Field_ftsf51ae_slot1_Slot_ae_slot1_get (insn) == 724 && 39651 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39652 return OPCODE_AE_SRASP24; 39653 if (Field_ftsf52ae_slot1_Slot_ae_slot1_get (insn) == 728 && 39654 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39655 return OPCODE_AE_SRLSP24; 39656 if (Field_ftsf53ae_slot1_Slot_ae_slot1_get (insn) == 732 && 39657 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39658 return OPCODE_AE_TRUNCP16; 39659 if (Field_ftsf54ae_slot1_Slot_ae_slot1_get (insn) == 24 && 39660 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39661 Field_ftsf356ae_slot1_Slot_ae_slot1_get (insn) == 0) 39662 return OPCODE_AE_ABSSP24S; 39663 if (Field_ftsf56ae_slot1_Slot_ae_slot1_get (insn) == 9 && 39664 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39665 return OPCODE_AE_EQP24; 39666 if (Field_ftsf57ae_slot1_Slot_ae_slot1_get (insn) == 25 && 39667 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39668 return OPCODE_AE_LTP24S; 39669 if (Field_ftsf58ae_slot1_Slot_ae_slot1_get (insn) == 25 && 39670 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39671 Field_ftsf354ae_slot1_Slot_ae_slot1_get (insn) == 0) 39672 return OPCODE_AE_MOVFP24X2; 39673 if (Field_ftsf60ae_slot1_Slot_ae_slot1_get (insn) == 25 && 39674 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39675 Field_ftsf355ae_slot1_Slot_ae_slot1_get (insn) == 0) 39676 return OPCODE_AE_MOVTP24X2; 39677 if (Field_ftsf61_Slot_ae_slot1_get (insn) == 1 && 39678 Field_op0_s3_Slot_ae_slot1_get (insn) == 6 && 39679 Field_ftsf334ae_slot1_Slot_ae_slot1_get (insn) == 0) 39680 return OPCODE_AE_MULAFS32P16S_HH; 39681 if (Field_ftsf62ae_slot1_Slot_ae_slot1_get (insn) == 12 && 39682 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39683 Field_ae_s20_Slot_ae_slot1_get (insn) == 0) 39684 return OPCODE_AE_LEP24S; 39685 if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 97 && 39686 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39687 Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) 39688 return OPCODE_AE_ROUNDSP16Q48ASYM; 39689 if (Field_ftsf63ae_slot1_Slot_ae_slot1_get (insn) == 101 && 39690 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39691 Field_ftsf344ae_slot1_Slot_ae_slot1_get (insn) == 0) 39692 return OPCODE_AE_ROUNDSP16Q48SYM; 39693 if (Field_ftsf64ae_slot1_Slot_ae_slot1_get (insn) == 53 && 39694 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39695 Field_ftsf345ae_slot1_Slot_ae_slot1_get (insn) == 0) 39696 return OPCODE_AE_ROUNDSP24Q48ASYM; 39697 if (Field_ftsf66ae_slot1_Slot_ae_slot1_get (insn) == 29 && 39698 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39699 Field_ftsf347ae_slot1_Slot_ae_slot1_get (insn) == 0) 39700 return OPCODE_AE_ROUNDSP24Q48SYM; 39701 if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 2 && 39702 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39703 return OPCODE_AE_SLLIP24; 39704 if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 3 && 39705 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39706 return OPCODE_AE_SLLISP24S; 39707 if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 6 && 39708 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39709 return OPCODE_AE_SRAIP24; 39710 if (Field_ftsf68ae_slot1_Slot_ae_slot1_get (insn) == 10 && 39711 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39712 return OPCODE_AE_SRLIP24; 39713 if (Field_ftsf69ae_slot1_Slot_ae_slot1_get (insn) == 7 && 39714 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39715 return OPCODE_AE_MULAFQ32SP16S_L; 39716 if (Field_ftsf70ae_slot1_Slot_ae_slot1_get (insn) == 39 && 39717 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39718 return OPCODE_AE_MULAFQ32SP16U_H; 39719 if (Field_ftsf71ae_slot1_Slot_ae_slot1_get (insn) == 71 && 39720 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39721 return OPCODE_AE_MULAFQ32SP16U_L; 39722 if (Field_ftsf72ae_slot1_Slot_ae_slot1_get (insn) == 103 && 39723 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39724 return OPCODE_AE_MULAQ32SP16U_H; 39725 if (Field_ftsf73ae_slot1_Slot_ae_slot1_get (insn) == 135 && 39726 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39727 return OPCODE_AE_MULAQ32SP16S_H; 39728 if (Field_ftsf74ae_slot1_Slot_ae_slot1_get (insn) == 167 && 39729 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39730 return OPCODE_AE_MULAQ32SP16U_L; 39731 if (Field_ftsf75ae_slot1_Slot_ae_slot1_get (insn) == 199 && 39732 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39733 return OPCODE_AE_MULFQ32SP16S_H; 39734 if (Field_ftsf76ae_slot1_Slot_ae_slot1_get (insn) == 231 && 39735 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39736 return OPCODE_AE_MULFQ32SP16S_L; 39737 if (Field_ftsf77ae_slot1_Slot_ae_slot1_get (insn) == 263 && 39738 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39739 return OPCODE_AE_MULAQ32SP16S_L; 39740 if (Field_ftsf78ae_slot1_Slot_ae_slot1_get (insn) == 295 && 39741 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39742 return OPCODE_AE_MULFQ32SP16U_H; 39743 if (Field_ftsf79ae_slot1_Slot_ae_slot1_get (insn) == 327 && 39744 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39745 return OPCODE_AE_MULFQ32SP16U_L; 39746 if (Field_ftsf80ae_slot1_Slot_ae_slot1_get (insn) == 359 && 39747 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39748 return OPCODE_AE_MULQ32SP16S_L; 39749 if (Field_ftsf81ae_slot1_Slot_ae_slot1_get (insn) == 391 && 39750 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39751 return OPCODE_AE_MULQ32SP16S_H; 39752 if (Field_ftsf82ae_slot1_Slot_ae_slot1_get (insn) == 423 && 39753 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39754 return OPCODE_AE_MULQ32SP16U_H; 39755 if (Field_ftsf83ae_slot1_Slot_ae_slot1_get (insn) == 455 && 39756 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39757 return OPCODE_AE_MULQ32SP16U_L; 39758 if (Field_ftsf84ae_slot1_Slot_ae_slot1_get (insn) == 487 && 39759 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39760 return OPCODE_AE_MULSFQ32SP16S_H; 39761 if (Field_ftsf85ae_slot1_Slot_ae_slot1_get (insn) == 11 && 39762 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39763 return OPCODE_AE_MULSFQ32SP16S_L; 39764 if (Field_ftsf86ae_slot1_Slot_ae_slot1_get (insn) == 43 && 39765 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39766 return OPCODE_AE_MULSFQ32SP16U_L; 39767 if (Field_ftsf87ae_slot1_Slot_ae_slot1_get (insn) == 75 && 39768 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39769 return OPCODE_AE_MULSQ32SP16S_H; 39770 if (Field_ftsf88ae_slot1_Slot_ae_slot1_get (insn) == 107 && 39771 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39772 return OPCODE_AE_MULSQ32SP16U_L; 39773 if (Field_ftsf89ae_slot1_Slot_ae_slot1_get (insn) == 139 && 39774 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39775 return OPCODE_AE_MULSQ32SP16S_L; 39776 if (Field_ftsf90ae_slot1_Slot_ae_slot1_get (insn) == 331 && 39777 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39778 Field_ftsf55_Slot_ae_slot1_get (insn) == 0) 39779 return OPCODE_AE_CVTQ48P24S_H; 39780 if (Field_ftsf92ae_slot1_Slot_ae_slot1_get (insn) == 363 && 39781 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39782 Field_ftsf358ae_slot1_Slot_ae_slot1_get (insn) == 0) 39783 return OPCODE_AE_ZEROQ56; 39784 if (Field_ftsf93ae_slot1_Slot_ae_slot1_get (insn) == 203 && 39785 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39786 Field_ae_r10_Slot_ae_slot1_get (insn) == 0) 39787 return OPCODE_AE_CVTQ48P24S_L; 39788 if (Field_ftsf94ae_slot1_Slot_ae_slot1_get (insn) == 1803 && 39789 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39790 return OPCODE_AE_MOVQ56; 39791 if (Field_ftsf96ae_slot1_Slot_ae_slot1_get (insn) == 1835 && 39792 Field_op0_s3_Slot_ae_slot1_get (insn) == 1) 39793 return OPCODE_AE_ROUNDSQ32ASYM; 39794 if (Field_ftsf97ae_slot1_Slot_ae_slot1_get (insn) == 939 && 39795 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39796 Field_ftsf348ae_slot1_Slot_ae_slot1_get (insn) == 0) 39797 return OPCODE_AE_ROUNDSQ32SYM; 39798 if (Field_ftsf99ae_slot1_Slot_ae_slot1_get (insn) == 491 && 39799 Field_op0_s3_Slot_ae_slot1_get (insn) == 1 && 39800 Field_ftsf351_Slot_ae_slot1_get (insn) == 0) 39801 return OPCODE_AE_TRUNCQ32; 39802 if (Field_t_Slot_ae_slot1_get (insn) == 0 && 39803 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39804 return OPCODE_AE_MULZAAFQ32SP16S_HH; 39805 if (Field_t_Slot_ae_slot1_get (insn) == 0 && 39806 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39807 return OPCODE_AE_MULZASFQ32SP16U_LH; 39808 if (Field_t_Slot_ae_slot1_get (insn) == 0 && 39809 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39810 return OPCODE_AE_MULZSAQ32SP16S_LL; 39811 if (Field_t_Slot_ae_slot1_get (insn) == 1 && 39812 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39813 return OPCODE_AE_MULZAAFQ32SP16S_LH; 39814 if (Field_t_Slot_ae_slot1_get (insn) == 1 && 39815 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39816 return OPCODE_AE_MULZASFQ32SP16U_LL; 39817 if (Field_t_Slot_ae_slot1_get (insn) == 1 && 39818 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39819 return OPCODE_AE_MULZSAQ32SP16U_HH; 39820 if (Field_t_Slot_ae_slot1_get (insn) == 2 && 39821 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39822 return OPCODE_AE_MULZAAFQ32SP16S_LL; 39823 if (Field_t_Slot_ae_slot1_get (insn) == 2 && 39824 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39825 return OPCODE_AE_MULZASQ32SP16S_HH; 39826 if (Field_t_Slot_ae_slot1_get (insn) == 2 && 39827 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39828 return OPCODE_AE_MULZSAQ32SP16U_LH; 39829 if (Field_t_Slot_ae_slot1_get (insn) == 3 && 39830 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39831 return OPCODE_AE_MULZAAFQ32SP16U_LL; 39832 if (Field_t_Slot_ae_slot1_get (insn) == 3 && 39833 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39834 return OPCODE_AE_MULZASQ32SP16U_HH; 39835 if (Field_t_Slot_ae_slot1_get (insn) == 3 && 39836 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39837 return OPCODE_AE_MULZSSFQ32SP16S_LH; 39838 if (Field_t_Slot_ae_slot1_get (insn) == 4 && 39839 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39840 return OPCODE_AE_MULZAAFQ32SP16U_HH; 39841 if (Field_t_Slot_ae_slot1_get (insn) == 4 && 39842 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39843 return OPCODE_AE_MULZASQ32SP16S_LH; 39844 if (Field_t_Slot_ae_slot1_get (insn) == 4 && 39845 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39846 return OPCODE_AE_MULZSAQ32SP16U_LL; 39847 if (Field_t_Slot_ae_slot1_get (insn) == 5 && 39848 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39849 return OPCODE_AE_MULZAAQ32SP16S_HH; 39850 if (Field_t_Slot_ae_slot1_get (insn) == 5 && 39851 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39852 return OPCODE_AE_MULZASQ32SP16U_LH; 39853 if (Field_t_Slot_ae_slot1_get (insn) == 5 && 39854 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39855 return OPCODE_AE_MULZSSFQ32SP16S_LL; 39856 if (Field_t_Slot_ae_slot1_get (insn) == 6 && 39857 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39858 return OPCODE_AE_MULZAAQ32SP16S_LH; 39859 if (Field_t_Slot_ae_slot1_get (insn) == 6 && 39860 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39861 return OPCODE_AE_MULZASQ32SP16U_LL; 39862 if (Field_t_Slot_ae_slot1_get (insn) == 6 && 39863 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39864 return OPCODE_AE_MULZSSFQ32SP16U_HH; 39865 if (Field_t_Slot_ae_slot1_get (insn) == 7 && 39866 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39867 return OPCODE_AE_MULZAAQ32SP16S_LL; 39868 if (Field_t_Slot_ae_slot1_get (insn) == 7 && 39869 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39870 return OPCODE_AE_MULZSAFQ32SP16S_HH; 39871 if (Field_t_Slot_ae_slot1_get (insn) == 7 && 39872 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39873 return OPCODE_AE_MULZSSFQ32SP16U_LH; 39874 if (Field_t_Slot_ae_slot1_get (insn) == 8 && 39875 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39876 return OPCODE_AE_MULZAAFQ32SP16U_LH; 39877 if (Field_t_Slot_ae_slot1_get (insn) == 8 && 39878 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39879 return OPCODE_AE_MULZASQ32SP16S_LL; 39880 if (Field_t_Slot_ae_slot1_get (insn) == 8 && 39881 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39882 return OPCODE_AE_MULZSSFQ32SP16S_HH; 39883 if (Field_t_Slot_ae_slot1_get (insn) == 9 && 39884 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39885 return OPCODE_AE_MULZAAQ32SP16U_HH; 39886 if (Field_t_Slot_ae_slot1_get (insn) == 9 && 39887 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39888 return OPCODE_AE_MULZSAFQ32SP16S_LH; 39889 if (Field_t_Slot_ae_slot1_get (insn) == 9 && 39890 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39891 return OPCODE_AE_MULZSSFQ32SP16U_LL; 39892 if (Field_t_Slot_ae_slot1_get (insn) == 10 && 39893 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39894 return OPCODE_AE_MULZAAQ32SP16U_LH; 39895 if (Field_t_Slot_ae_slot1_get (insn) == 10 && 39896 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39897 return OPCODE_AE_MULZSAFQ32SP16S_LL; 39898 if (Field_t_Slot_ae_slot1_get (insn) == 10 && 39899 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39900 return OPCODE_AE_MULZSSQ32SP16S_HH; 39901 if (Field_t_Slot_ae_slot1_get (insn) == 11 && 39902 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39903 return OPCODE_AE_MULZASFQ32SP16S_HH; 39904 if (Field_t_Slot_ae_slot1_get (insn) == 11 && 39905 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39906 return OPCODE_AE_MULZSAFQ32SP16U_LH; 39907 if (Field_t_Slot_ae_slot1_get (insn) == 11 && 39908 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39909 return OPCODE_AE_MULZSSQ32SP16S_LL; 39910 if (Field_t_Slot_ae_slot1_get (insn) == 12 && 39911 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39912 return OPCODE_AE_MULZAAQ32SP16U_LL; 39913 if (Field_t_Slot_ae_slot1_get (insn) == 12 && 39914 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39915 return OPCODE_AE_MULZSAFQ32SP16U_HH; 39916 if (Field_t_Slot_ae_slot1_get (insn) == 12 && 39917 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39918 return OPCODE_AE_MULZSSQ32SP16S_LH; 39919 if (Field_t_Slot_ae_slot1_get (insn) == 13 && 39920 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39921 return OPCODE_AE_MULZASFQ32SP16S_LH; 39922 if (Field_t_Slot_ae_slot1_get (insn) == 13 && 39923 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39924 return OPCODE_AE_MULZSAFQ32SP16U_LL; 39925 if (Field_t_Slot_ae_slot1_get (insn) == 13 && 39926 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39927 return OPCODE_AE_MULZSSQ32SP16U_HH; 39928 if (Field_t_Slot_ae_slot1_get (insn) == 14 && 39929 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39930 return OPCODE_AE_MULZASFQ32SP16S_LL; 39931 if (Field_t_Slot_ae_slot1_get (insn) == 14 && 39932 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39933 return OPCODE_AE_MULZSAQ32SP16S_HH; 39934 if (Field_t_Slot_ae_slot1_get (insn) == 14 && 39935 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39936 return OPCODE_AE_MULZSSQ32SP16U_LH; 39937 if (Field_t_Slot_ae_slot1_get (insn) == 15 && 39938 Field_op0_s3_Slot_ae_slot1_get (insn) == 2) 39939 return OPCODE_AE_MULZASFQ32SP16U_HH; 39940 if (Field_t_Slot_ae_slot1_get (insn) == 15 && 39941 Field_op0_s3_Slot_ae_slot1_get (insn) == 3) 39942 return OPCODE_AE_MULZSAQ32SP16S_LH; 39943 if (Field_t_Slot_ae_slot1_get (insn) == 15 && 39944 Field_op0_s3_Slot_ae_slot1_get (insn) == 4) 39945 return OPCODE_AE_MULZSSQ32SP16U_LL; 39946 return XTENSA_UNDEFINED; 39947 } 39948 39949 39950 /* Instruction slots. */ 39951 39952 static void 39953 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn, 39954 xtensa_insnbuf slotbuf) 39955 { 39956 slotbuf[1] = 0; 39957 slotbuf[0] = ((insn[1] & 0xffffff00) >> 8); 39958 } 39959 39960 static void 39961 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn, 39962 const xtensa_insnbuf slotbuf) 39963 { 39964 insn[1] = (insn[1] & ~0xffffff00) | ((slotbuf[0] & 0xffffff) << 8); 39965 } 39966 39967 static void 39968 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn, 39969 xtensa_insnbuf slotbuf) 39970 { 39971 slotbuf[1] = 0; 39972 slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); 39973 } 39974 39975 static void 39976 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn, 39977 const xtensa_insnbuf slotbuf) 39978 { 39979 insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); 39980 } 39981 39982 static void 39983 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn, 39984 xtensa_insnbuf slotbuf) 39985 { 39986 slotbuf[1] = 0; 39987 slotbuf[0] = ((insn[1] & 0xffff0000) >> 16); 39988 } 39989 39990 static void 39991 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn, 39992 const xtensa_insnbuf slotbuf) 39993 { 39994 insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16); 39995 } 39996 39997 static void 39998 Slot_ae_format_Format_ae_slot1_10_get (const xtensa_insnbuf insn, 39999 xtensa_insnbuf slotbuf) 40000 { 40001 slotbuf[1] = 0; 40002 slotbuf[0] = ((insn[0] & 0xfffffc00) >> 10); 40003 slotbuf[0] = (slotbuf[0] & ~0x400000) | ((insn[1] & 0x1) << 22); 40004 } 40005 40006 static void 40007 Slot_ae_format_Format_ae_slot1_10_set (xtensa_insnbuf insn, 40008 const xtensa_insnbuf slotbuf) 40009 { 40010 insn[0] = (insn[0] & ~0xfffffc00) | ((slotbuf[0] & 0x3fffff) << 10); 40011 insn[1] = (insn[1] & ~0x1) | ((slotbuf[0] & 0x400000) >> 22); 40012 } 40013 40014 static void 40015 Slot_ae_format_Format_ae_slot0_33_get (const xtensa_insnbuf insn, 40016 xtensa_insnbuf slotbuf) 40017 { 40018 slotbuf[1] = 0; 40019 slotbuf[0] = ((insn[1] & 0xffffffe) >> 1); 40020 } 40021 40022 static void 40023 Slot_ae_format_Format_ae_slot0_33_set (xtensa_insnbuf insn, 40024 const xtensa_insnbuf slotbuf) 40025 { 40026 insn[1] = (insn[1] & ~0xffffffe) | ((slotbuf[0] & 0x7ffffff) << 1); 40027 } 40028 40029 static xtensa_get_field_fn 40030 Slot_inst_get_field_fns[] = { 40031 Field_t_Slot_inst_get, 40032 Field_bbi4_Slot_inst_get, 40033 Field_bbi_Slot_inst_get, 40034 Field_imm12_Slot_inst_get, 40035 Field_imm8_Slot_inst_get, 40036 Field_s_Slot_inst_get, 40037 Field_imm12b_Slot_inst_get, 40038 Field_imm16_Slot_inst_get, 40039 Field_m_Slot_inst_get, 40040 Field_n_Slot_inst_get, 40041 Field_offset_Slot_inst_get, 40042 Field_op0_Slot_inst_get, 40043 Field_op1_Slot_inst_get, 40044 Field_op2_Slot_inst_get, 40045 Field_r_Slot_inst_get, 40046 Field_sa4_Slot_inst_get, 40047 Field_sae4_Slot_inst_get, 40048 Field_sae_Slot_inst_get, 40049 Field_sal_Slot_inst_get, 40050 Field_sargt_Slot_inst_get, 40051 Field_sas4_Slot_inst_get, 40052 Field_sas_Slot_inst_get, 40053 Field_sr_Slot_inst_get, 40054 Field_st_Slot_inst_get, 40055 Field_thi3_Slot_inst_get, 40056 Field_imm4_Slot_inst_get, 40057 Field_mn_Slot_inst_get, 40058 0, 40059 0, 40060 0, 40061 0, 40062 0, 40063 0, 40064 0, 40065 0, 40066 Field_r3_Slot_inst_get, 40067 Field_rbit2_Slot_inst_get, 40068 Field_rhi_Slot_inst_get, 40069 Field_t3_Slot_inst_get, 40070 Field_tbit2_Slot_inst_get, 40071 Field_tlo_Slot_inst_get, 40072 Field_w_Slot_inst_get, 40073 Field_y_Slot_inst_get, 40074 Field_x_Slot_inst_get, 40075 Field_t2_Slot_inst_get, 40076 Field_s2_Slot_inst_get, 40077 Field_r2_Slot_inst_get, 40078 Field_t4_Slot_inst_get, 40079 Field_s4_Slot_inst_get, 40080 Field_r4_Slot_inst_get, 40081 Field_t8_Slot_inst_get, 40082 Field_s8_Slot_inst_get, 40083 Field_r8_Slot_inst_get, 40084 Field_xt_wbr15_imm_Slot_inst_get, 40085 Field_xt_wbr18_imm_Slot_inst_get, 40086 Field_ae_r3_Slot_inst_get, 40087 Field_ae_s_non_samt_Slot_inst_get, 40088 Field_ae_s3_Slot_inst_get, 40089 Field_ae_r32_Slot_inst_get, 40090 Field_ae_samt_s_t_Slot_inst_get, 40091 Field_ae_r20_Slot_inst_get, 40092 Field_ae_r10_Slot_inst_get, 40093 Field_ae_s20_Slot_inst_get, 40094 Field_ae_fld_ohba_Slot_inst_get, 40095 Field_ae_fld_ohba2_Slot_inst_get, 40096 0, 40097 Field_ftsf11_Slot_inst_get, 40098 Field_ftsf12_Slot_inst_get, 40099 0, 40100 0, 40101 0, 40102 0, 40103 0, 40104 0, 40105 0, 40106 0, 40107 0, 40108 0, 40109 0, 40110 0, 40111 0, 40112 0, 40113 0, 40114 0, 40115 0, 40116 0, 40117 0, 40118 0, 40119 0, 40120 0, 40121 0, 40122 0, 40123 0, 40124 0, 40125 0, 40126 0, 40127 0, 40128 0, 40129 0, 40130 0, 40131 0, 40132 0, 40133 0, 40134 0, 40135 0, 40136 0, 40137 0, 40138 0, 40139 0, 40140 0, 40141 0, 40142 0, 40143 0, 40144 0, 40145 0, 40146 0, 40147 0, 40148 0, 40149 0, 40150 0, 40151 0, 40152 0, 40153 0, 40154 0, 40155 0, 40156 0, 40157 0, 40158 0, 40159 0, 40160 0, 40161 0, 40162 0, 40163 0, 40164 0, 40165 0, 40166 0, 40167 0, 40168 0, 40169 0, 40170 0, 40171 0, 40172 0, 40173 0, 40174 0, 40175 0, 40176 0, 40177 0, 40178 0, 40179 0, 40180 0, 40181 0, 40182 0, 40183 0, 40184 0, 40185 0, 40186 0, 40187 0, 40188 0, 40189 0, 40190 0, 40191 0, 40192 0, 40193 0, 40194 0, 40195 0, 40196 0, 40197 0, 40198 0, 40199 0, 40200 0, 40201 0, 40202 0, 40203 0, 40204 0, 40205 0, 40206 0, 40207 0, 40208 0, 40209 0, 40210 0, 40211 0, 40212 0, 40213 0, 40214 0, 40215 0, 40216 0, 40217 0, 40218 0, 40219 0, 40220 0, 40221 0, 40222 0, 40223 0, 40224 0, 40225 0, 40226 0, 40227 0, 40228 0, 40229 0, 40230 0, 40231 0, 40232 0, 40233 0, 40234 0, 40235 0, 40236 0, 40237 0, 40238 0, 40239 0, 40240 0, 40241 0, 40242 0, 40243 0, 40244 0, 40245 0, 40246 0, 40247 0, 40248 0, 40249 0, 40250 0, 40251 0, 40252 0, 40253 0, 40254 0, 40255 0, 40256 0, 40257 0, 40258 0, 40259 0, 40260 0, 40261 0, 40262 0, 40263 0, 40264 0, 40265 0, 40266 0, 40267 0, 40268 0, 40269 0, 40270 0, 40271 0, 40272 0, 40273 0, 40274 0, 40275 0, 40276 0, 40277 0, 40278 0, 40279 0, 40280 0, 40281 0, 40282 0, 40283 0, 40284 0, 40285 0, 40286 0, 40287 0, 40288 0, 40289 0, 40290 0, 40291 0, 40292 0, 40293 0, 40294 0, 40295 0, 40296 0, 40297 0, 40298 0, 40299 0, 40300 0, 40301 0, 40302 0, 40303 0, 40304 0, 40305 0, 40306 0, 40307 0, 40308 0, 40309 0, 40310 0, 40311 0, 40312 0, 40313 0, 40314 0, 40315 0, 40316 0, 40317 0, 40318 0, 40319 0, 40320 0, 40321 0, 40322 0, 40323 0, 40324 0, 40325 0, 40326 0, 40327 0, 40328 0, 40329 0, 40330 0, 40331 0, 40332 0, 40333 0, 40334 0, 40335 0, 40336 0, 40337 0, 40338 0, 40339 0, 40340 0, 40341 0, 40342 0, 40343 0, 40344 0, 40345 0, 40346 0, 40347 0, 40348 0, 40349 0, 40350 0, 40351 0, 40352 0, 40353 0, 40354 0, 40355 0, 40356 0, 40357 0, 40358 0, 40359 0, 40360 0, 40361 0, 40362 0, 40363 0, 40364 0, 40365 0, 40366 0, 40367 0, 40368 0, 40369 0, 40370 0, 40371 0, 40372 0, 40373 0, 40374 0, 40375 0, 40376 0, 40377 0, 40378 0, 40379 0, 40380 0, 40381 0, 40382 0, 40383 0, 40384 0, 40385 0, 40386 0, 40387 0, 40388 0, 40389 0, 40390 0, 40391 0, 40392 0, 40393 0, 40394 0, 40395 0, 40396 0, 40397 0, 40398 0, 40399 0, 40400 0, 40401 0, 40402 0, 40403 0, 40404 0, 40405 0, 40406 0, 40407 0, 40408 0, 40409 0, 40410 0, 40411 0, 40412 0, 40413 0, 40414 0, 40415 0, 40416 0, 40417 0, 40418 0, 40419 0, 40420 0, 40421 0, 40422 0, 40423 0, 40424 0, 40425 0, 40426 0, 40427 0, 40428 0, 40429 0, 40430 0, 40431 0, 40432 0, 40433 0, 40434 0, 40435 0, 40436 0, 40437 0, 40438 0, 40439 0, 40440 0, 40441 0, 40442 0, 40443 0, 40444 0, 40445 0, 40446 0, 40447 0, 40448 0, 40449 0, 40450 0, 40451 0, 40452 0, 40453 0, 40454 0, 40455 0, 40456 0, 40457 0, 40458 0, 40459 0, 40460 0, 40461 0, 40462 0, 40463 0, 40464 0, 40465 0, 40466 0, 40467 0, 40468 0, 40469 0, 40470 0, 40471 0, 40472 0, 40473 0, 40474 0, 40475 0, 40476 0, 40477 0, 40478 0, 40479 0, 40480 0, 40481 0, 40482 0, 40483 0, 40484 0, 40485 Field_bitindex_Slot_inst_get, 40486 Field_s3to1_Slot_inst_get, 40487 Implicit_Field_ar0_get, 40488 Implicit_Field_ar4_get, 40489 Implicit_Field_ar8_get, 40490 Implicit_Field_ar12_get, 40491 Implicit_Field_mr0_get, 40492 Implicit_Field_mr1_get, 40493 Implicit_Field_mr2_get, 40494 Implicit_Field_mr3_get, 40495 Implicit_Field_bt16_get, 40496 Implicit_Field_bs16_get, 40497 Implicit_Field_br16_get, 40498 Implicit_Field_brall_get 40499 }; 40500 40501 static xtensa_set_field_fn 40502 Slot_inst_set_field_fns[] = { 40503 Field_t_Slot_inst_set, 40504 Field_bbi4_Slot_inst_set, 40505 Field_bbi_Slot_inst_set, 40506 Field_imm12_Slot_inst_set, 40507 Field_imm8_Slot_inst_set, 40508 Field_s_Slot_inst_set, 40509 Field_imm12b_Slot_inst_set, 40510 Field_imm16_Slot_inst_set, 40511 Field_m_Slot_inst_set, 40512 Field_n_Slot_inst_set, 40513 Field_offset_Slot_inst_set, 40514 Field_op0_Slot_inst_set, 40515 Field_op1_Slot_inst_set, 40516 Field_op2_Slot_inst_set, 40517 Field_r_Slot_inst_set, 40518 Field_sa4_Slot_inst_set, 40519 Field_sae4_Slot_inst_set, 40520 Field_sae_Slot_inst_set, 40521 Field_sal_Slot_inst_set, 40522 Field_sargt_Slot_inst_set, 40523 Field_sas4_Slot_inst_set, 40524 Field_sas_Slot_inst_set, 40525 Field_sr_Slot_inst_set, 40526 Field_st_Slot_inst_set, 40527 Field_thi3_Slot_inst_set, 40528 Field_imm4_Slot_inst_set, 40529 Field_mn_Slot_inst_set, 40530 0, 40531 0, 40532 0, 40533 0, 40534 0, 40535 0, 40536 0, 40537 0, 40538 Field_r3_Slot_inst_set, 40539 Field_rbit2_Slot_inst_set, 40540 Field_rhi_Slot_inst_set, 40541 Field_t3_Slot_inst_set, 40542 Field_tbit2_Slot_inst_set, 40543 Field_tlo_Slot_inst_set, 40544 Field_w_Slot_inst_set, 40545 Field_y_Slot_inst_set, 40546 Field_x_Slot_inst_set, 40547 Field_t2_Slot_inst_set, 40548 Field_s2_Slot_inst_set, 40549 Field_r2_Slot_inst_set, 40550 Field_t4_Slot_inst_set, 40551 Field_s4_Slot_inst_set, 40552 Field_r4_Slot_inst_set, 40553 Field_t8_Slot_inst_set, 40554 Field_s8_Slot_inst_set, 40555 Field_r8_Slot_inst_set, 40556 Field_xt_wbr15_imm_Slot_inst_set, 40557 Field_xt_wbr18_imm_Slot_inst_set, 40558 Field_ae_r3_Slot_inst_set, 40559 Field_ae_s_non_samt_Slot_inst_set, 40560 Field_ae_s3_Slot_inst_set, 40561 Field_ae_r32_Slot_inst_set, 40562 Field_ae_samt_s_t_Slot_inst_set, 40563 Field_ae_r20_Slot_inst_set, 40564 Field_ae_r10_Slot_inst_set, 40565 Field_ae_s20_Slot_inst_set, 40566 Field_ae_fld_ohba_Slot_inst_set, 40567 Field_ae_fld_ohba2_Slot_inst_set, 40568 0, 40569 Field_ftsf11_Slot_inst_set, 40570 Field_ftsf12_Slot_inst_set, 40571 0, 40572 0, 40573 0, 40574 0, 40575 0, 40576 0, 40577 0, 40578 0, 40579 0, 40580 0, 40581 0, 40582 0, 40583 0, 40584 0, 40585 0, 40586 0, 40587 0, 40588 0, 40589 0, 40590 0, 40591 0, 40592 0, 40593 0, 40594 0, 40595 0, 40596 0, 40597 0, 40598 0, 40599 0, 40600 0, 40601 0, 40602 0, 40603 0, 40604 0, 40605 0, 40606 0, 40607 0, 40608 0, 40609 0, 40610 0, 40611 0, 40612 0, 40613 0, 40614 0, 40615 0, 40616 0, 40617 0, 40618 0, 40619 0, 40620 0, 40621 0, 40622 0, 40623 0, 40624 0, 40625 0, 40626 0, 40627 0, 40628 0, 40629 0, 40630 0, 40631 0, 40632 0, 40633 0, 40634 0, 40635 0, 40636 0, 40637 0, 40638 0, 40639 0, 40640 0, 40641 0, 40642 0, 40643 0, 40644 0, 40645 0, 40646 0, 40647 0, 40648 0, 40649 0, 40650 0, 40651 0, 40652 0, 40653 0, 40654 0, 40655 0, 40656 0, 40657 0, 40658 0, 40659 0, 40660 0, 40661 0, 40662 0, 40663 0, 40664 0, 40665 0, 40666 0, 40667 0, 40668 0, 40669 0, 40670 0, 40671 0, 40672 0, 40673 0, 40674 0, 40675 0, 40676 0, 40677 0, 40678 0, 40679 0, 40680 0, 40681 0, 40682 0, 40683 0, 40684 0, 40685 0, 40686 0, 40687 0, 40688 0, 40689 0, 40690 0, 40691 0, 40692 0, 40693 0, 40694 0, 40695 0, 40696 0, 40697 0, 40698 0, 40699 0, 40700 0, 40701 0, 40702 0, 40703 0, 40704 0, 40705 0, 40706 0, 40707 0, 40708 0, 40709 0, 40710 0, 40711 0, 40712 0, 40713 0, 40714 0, 40715 0, 40716 0, 40717 0, 40718 0, 40719 0, 40720 0, 40721 0, 40722 0, 40723 0, 40724 0, 40725 0, 40726 0, 40727 0, 40728 0, 40729 0, 40730 0, 40731 0, 40732 0, 40733 0, 40734 0, 40735 0, 40736 0, 40737 0, 40738 0, 40739 0, 40740 0, 40741 0, 40742 0, 40743 0, 40744 0, 40745 0, 40746 0, 40747 0, 40748 0, 40749 0, 40750 0, 40751 0, 40752 0, 40753 0, 40754 0, 40755 0, 40756 0, 40757 0, 40758 0, 40759 0, 40760 0, 40761 0, 40762 0, 40763 0, 40764 0, 40765 0, 40766 0, 40767 0, 40768 0, 40769 0, 40770 0, 40771 0, 40772 0, 40773 0, 40774 0, 40775 0, 40776 0, 40777 0, 40778 0, 40779 0, 40780 0, 40781 0, 40782 0, 40783 0, 40784 0, 40785 0, 40786 0, 40787 0, 40788 0, 40789 0, 40790 0, 40791 0, 40792 0, 40793 0, 40794 0, 40795 0, 40796 0, 40797 0, 40798 0, 40799 0, 40800 0, 40801 0, 40802 0, 40803 0, 40804 0, 40805 0, 40806 0, 40807 0, 40808 0, 40809 0, 40810 0, 40811 0, 40812 0, 40813 0, 40814 0, 40815 0, 40816 0, 40817 0, 40818 0, 40819 0, 40820 0, 40821 0, 40822 0, 40823 0, 40824 0, 40825 0, 40826 0, 40827 0, 40828 0, 40829 0, 40830 0, 40831 0, 40832 0, 40833 0, 40834 0, 40835 0, 40836 0, 40837 0, 40838 0, 40839 0, 40840 0, 40841 0, 40842 0, 40843 0, 40844 0, 40845 0, 40846 0, 40847 0, 40848 0, 40849 0, 40850 0, 40851 0, 40852 0, 40853 0, 40854 0, 40855 0, 40856 0, 40857 0, 40858 0, 40859 0, 40860 0, 40861 0, 40862 0, 40863 0, 40864 0, 40865 0, 40866 0, 40867 0, 40868 0, 40869 0, 40870 0, 40871 0, 40872 0, 40873 0, 40874 0, 40875 0, 40876 0, 40877 0, 40878 0, 40879 0, 40880 0, 40881 0, 40882 0, 40883 0, 40884 0, 40885 0, 40886 0, 40887 0, 40888 0, 40889 0, 40890 0, 40891 0, 40892 0, 40893 0, 40894 0, 40895 0, 40896 0, 40897 0, 40898 0, 40899 0, 40900 0, 40901 0, 40902 0, 40903 0, 40904 0, 40905 0, 40906 0, 40907 0, 40908 0, 40909 0, 40910 0, 40911 0, 40912 0, 40913 0, 40914 0, 40915 0, 40916 0, 40917 0, 40918 0, 40919 0, 40920 0, 40921 0, 40922 0, 40923 0, 40924 0, 40925 0, 40926 0, 40927 0, 40928 0, 40929 0, 40930 0, 40931 0, 40932 0, 40933 0, 40934 0, 40935 0, 40936 0, 40937 0, 40938 0, 40939 0, 40940 0, 40941 0, 40942 0, 40943 0, 40944 0, 40945 0, 40946 0, 40947 0, 40948 0, 40949 0, 40950 0, 40951 0, 40952 0, 40953 0, 40954 0, 40955 0, 40956 0, 40957 Field_bitindex_Slot_inst_set, 40958 Field_s3to1_Slot_inst_set, 40959 Implicit_Field_set, 40960 Implicit_Field_set, 40961 Implicit_Field_set, 40962 Implicit_Field_set, 40963 Implicit_Field_set, 40964 Implicit_Field_set, 40965 Implicit_Field_set, 40966 Implicit_Field_set, 40967 Implicit_Field_set, 40968 Implicit_Field_set, 40969 Implicit_Field_set, 40970 Implicit_Field_set 40971 }; 40972 40973 static xtensa_get_field_fn 40974 Slot_inst16a_get_field_fns[] = { 40975 Field_t_Slot_inst16a_get, 40976 0, 40977 0, 40978 0, 40979 0, 40980 Field_s_Slot_inst16a_get, 40981 0, 40982 0, 40983 0, 40984 0, 40985 0, 40986 Field_op0_Slot_inst16a_get, 40987 0, 40988 0, 40989 Field_r_Slot_inst16a_get, 40990 0, 40991 0, 40992 0, 40993 0, 40994 0, 40995 0, 40996 0, 40997 Field_sr_Slot_inst16a_get, 40998 Field_st_Slot_inst16a_get, 40999 0, 41000 Field_imm4_Slot_inst16a_get, 41001 0, 41002 Field_i_Slot_inst16a_get, 41003 Field_imm6lo_Slot_inst16a_get, 41004 Field_imm6hi_Slot_inst16a_get, 41005 Field_imm7lo_Slot_inst16a_get, 41006 Field_imm7hi_Slot_inst16a_get, 41007 Field_z_Slot_inst16a_get, 41008 Field_imm6_Slot_inst16a_get, 41009 Field_imm7_Slot_inst16a_get, 41010 0, 41011 0, 41012 0, 41013 0, 41014 0, 41015 0, 41016 0, 41017 0, 41018 0, 41019 Field_t2_Slot_inst16a_get, 41020 Field_s2_Slot_inst16a_get, 41021 Field_r2_Slot_inst16a_get, 41022 Field_t4_Slot_inst16a_get, 41023 Field_s4_Slot_inst16a_get, 41024 Field_r4_Slot_inst16a_get, 41025 Field_t8_Slot_inst16a_get, 41026 Field_s8_Slot_inst16a_get, 41027 Field_r8_Slot_inst16a_get, 41028 0, 41029 0, 41030 0, 41031 0, 41032 0, 41033 0, 41034 0, 41035 0, 41036 0, 41037 0, 41038 0, 41039 0, 41040 0, 41041 0, 41042 0, 41043 0, 41044 0, 41045 0, 41046 0, 41047 0, 41048 0, 41049 0, 41050 0, 41051 0, 41052 0, 41053 0, 41054 0, 41055 0, 41056 0, 41057 0, 41058 0, 41059 0, 41060 0, 41061 0, 41062 0, 41063 0, 41064 0, 41065 0, 41066 0, 41067 0, 41068 0, 41069 0, 41070 0, 41071 0, 41072 0, 41073 0, 41074 0, 41075 0, 41076 0, 41077 0, 41078 0, 41079 0, 41080 0, 41081 0, 41082 0, 41083 0, 41084 0, 41085 0, 41086 0, 41087 0, 41088 0, 41089 0, 41090 0, 41091 0, 41092 0, 41093 0, 41094 0, 41095 0, 41096 0, 41097 0, 41098 0, 41099 0, 41100 0, 41101 0, 41102 0, 41103 0, 41104 0, 41105 0, 41106 0, 41107 0, 41108 0, 41109 0, 41110 0, 41111 0, 41112 0, 41113 0, 41114 0, 41115 0, 41116 0, 41117 0, 41118 0, 41119 0, 41120 0, 41121 0, 41122 0, 41123 0, 41124 0, 41125 0, 41126 0, 41127 0, 41128 0, 41129 0, 41130 0, 41131 0, 41132 0, 41133 0, 41134 0, 41135 0, 41136 0, 41137 0, 41138 0, 41139 0, 41140 0, 41141 0, 41142 0, 41143 0, 41144 0, 41145 0, 41146 0, 41147 0, 41148 0, 41149 0, 41150 0, 41151 0, 41152 0, 41153 0, 41154 0, 41155 0, 41156 0, 41157 0, 41158 0, 41159 0, 41160 0, 41161 0, 41162 0, 41163 0, 41164 0, 41165 0, 41166 0, 41167 0, 41168 0, 41169 0, 41170 0, 41171 0, 41172 0, 41173 0, 41174 0, 41175 0, 41176 0, 41177 0, 41178 0, 41179 0, 41180 0, 41181 0, 41182 0, 41183 0, 41184 0, 41185 0, 41186 0, 41187 0, 41188 0, 41189 0, 41190 0, 41191 0, 41192 0, 41193 0, 41194 0, 41195 0, 41196 0, 41197 0, 41198 0, 41199 0, 41200 0, 41201 0, 41202 0, 41203 0, 41204 0, 41205 0, 41206 0, 41207 0, 41208 0, 41209 0, 41210 0, 41211 0, 41212 0, 41213 0, 41214 0, 41215 0, 41216 0, 41217 0, 41218 0, 41219 0, 41220 0, 41221 0, 41222 0, 41223 0, 41224 0, 41225 0, 41226 0, 41227 0, 41228 0, 41229 0, 41230 0, 41231 0, 41232 0, 41233 0, 41234 0, 41235 0, 41236 0, 41237 0, 41238 0, 41239 0, 41240 0, 41241 0, 41242 0, 41243 0, 41244 0, 41245 0, 41246 0, 41247 0, 41248 0, 41249 0, 41250 0, 41251 0, 41252 0, 41253 0, 41254 0, 41255 0, 41256 0, 41257 0, 41258 0, 41259 0, 41260 0, 41261 0, 41262 0, 41263 0, 41264 0, 41265 0, 41266 0, 41267 0, 41268 0, 41269 0, 41270 0, 41271 0, 41272 0, 41273 0, 41274 0, 41275 0, 41276 0, 41277 0, 41278 0, 41279 0, 41280 0, 41281 0, 41282 0, 41283 0, 41284 0, 41285 0, 41286 0, 41287 0, 41288 0, 41289 0, 41290 0, 41291 0, 41292 0, 41293 0, 41294 0, 41295 0, 41296 0, 41297 0, 41298 0, 41299 0, 41300 0, 41301 0, 41302 0, 41303 0, 41304 0, 41305 0, 41306 0, 41307 0, 41308 0, 41309 0, 41310 0, 41311 0, 41312 0, 41313 0, 41314 0, 41315 0, 41316 0, 41317 0, 41318 0, 41319 0, 41320 0, 41321 0, 41322 0, 41323 0, 41324 0, 41325 0, 41326 0, 41327 0, 41328 0, 41329 0, 41330 0, 41331 0, 41332 0, 41333 0, 41334 0, 41335 0, 41336 0, 41337 0, 41338 0, 41339 0, 41340 0, 41341 0, 41342 0, 41343 0, 41344 0, 41345 0, 41346 0, 41347 0, 41348 0, 41349 0, 41350 0, 41351 0, 41352 0, 41353 0, 41354 0, 41355 0, 41356 0, 41357 0, 41358 0, 41359 0, 41360 0, 41361 0, 41362 0, 41363 0, 41364 0, 41365 0, 41366 0, 41367 0, 41368 0, 41369 0, 41370 0, 41371 0, 41372 0, 41373 0, 41374 0, 41375 0, 41376 0, 41377 0, 41378 0, 41379 0, 41380 0, 41381 0, 41382 0, 41383 0, 41384 0, 41385 0, 41386 0, 41387 0, 41388 0, 41389 0, 41390 0, 41391 0, 41392 0, 41393 0, 41394 0, 41395 0, 41396 0, 41397 0, 41398 0, 41399 0, 41400 0, 41401 0, 41402 0, 41403 0, 41404 0, 41405 0, 41406 0, 41407 0, 41408 0, 41409 0, 41410 0, 41411 0, 41412 0, 41413 0, 41414 0, 41415 0, 41416 0, 41417 0, 41418 0, 41419 0, 41420 0, 41421 0, 41422 0, 41423 0, 41424 0, 41425 0, 41426 0, 41427 0, 41428 0, 41429 Field_bitindex_Slot_inst16a_get, 41430 Field_s3to1_Slot_inst16a_get, 41431 Implicit_Field_ar0_get, 41432 Implicit_Field_ar4_get, 41433 Implicit_Field_ar8_get, 41434 Implicit_Field_ar12_get, 41435 Implicit_Field_mr0_get, 41436 Implicit_Field_mr1_get, 41437 Implicit_Field_mr2_get, 41438 Implicit_Field_mr3_get, 41439 Implicit_Field_bt16_get, 41440 Implicit_Field_bs16_get, 41441 Implicit_Field_br16_get, 41442 Implicit_Field_brall_get 41443 }; 41444 41445 static xtensa_set_field_fn 41446 Slot_inst16a_set_field_fns[] = { 41447 Field_t_Slot_inst16a_set, 41448 0, 41449 0, 41450 0, 41451 0, 41452 Field_s_Slot_inst16a_set, 41453 0, 41454 0, 41455 0, 41456 0, 41457 0, 41458 Field_op0_Slot_inst16a_set, 41459 0, 41460 0, 41461 Field_r_Slot_inst16a_set, 41462 0, 41463 0, 41464 0, 41465 0, 41466 0, 41467 0, 41468 0, 41469 Field_sr_Slot_inst16a_set, 41470 Field_st_Slot_inst16a_set, 41471 0, 41472 Field_imm4_Slot_inst16a_set, 41473 0, 41474 Field_i_Slot_inst16a_set, 41475 Field_imm6lo_Slot_inst16a_set, 41476 Field_imm6hi_Slot_inst16a_set, 41477 Field_imm7lo_Slot_inst16a_set, 41478 Field_imm7hi_Slot_inst16a_set, 41479 Field_z_Slot_inst16a_set, 41480 Field_imm6_Slot_inst16a_set, 41481 Field_imm7_Slot_inst16a_set, 41482 0, 41483 0, 41484 0, 41485 0, 41486 0, 41487 0, 41488 0, 41489 0, 41490 0, 41491 Field_t2_Slot_inst16a_set, 41492 Field_s2_Slot_inst16a_set, 41493 Field_r2_Slot_inst16a_set, 41494 Field_t4_Slot_inst16a_set, 41495 Field_s4_Slot_inst16a_set, 41496 Field_r4_Slot_inst16a_set, 41497 Field_t8_Slot_inst16a_set, 41498 Field_s8_Slot_inst16a_set, 41499 Field_r8_Slot_inst16a_set, 41500 0, 41501 0, 41502 0, 41503 0, 41504 0, 41505 0, 41506 0, 41507 0, 41508 0, 41509 0, 41510 0, 41511 0, 41512 0, 41513 0, 41514 0, 41515 0, 41516 0, 41517 0, 41518 0, 41519 0, 41520 0, 41521 0, 41522 0, 41523 0, 41524 0, 41525 0, 41526 0, 41527 0, 41528 0, 41529 0, 41530 0, 41531 0, 41532 0, 41533 0, 41534 0, 41535 0, 41536 0, 41537 0, 41538 0, 41539 0, 41540 0, 41541 0, 41542 0, 41543 0, 41544 0, 41545 0, 41546 0, 41547 0, 41548 0, 41549 0, 41550 0, 41551 0, 41552 0, 41553 0, 41554 0, 41555 0, 41556 0, 41557 0, 41558 0, 41559 0, 41560 0, 41561 0, 41562 0, 41563 0, 41564 0, 41565 0, 41566 0, 41567 0, 41568 0, 41569 0, 41570 0, 41571 0, 41572 0, 41573 0, 41574 0, 41575 0, 41576 0, 41577 0, 41578 0, 41579 0, 41580 0, 41581 0, 41582 0, 41583 0, 41584 0, 41585 0, 41586 0, 41587 0, 41588 0, 41589 0, 41590 0, 41591 0, 41592 0, 41593 0, 41594 0, 41595 0, 41596 0, 41597 0, 41598 0, 41599 0, 41600 0, 41601 0, 41602 0, 41603 0, 41604 0, 41605 0, 41606 0, 41607 0, 41608 0, 41609 0, 41610 0, 41611 0, 41612 0, 41613 0, 41614 0, 41615 0, 41616 0, 41617 0, 41618 0, 41619 0, 41620 0, 41621 0, 41622 0, 41623 0, 41624 0, 41625 0, 41626 0, 41627 0, 41628 0, 41629 0, 41630 0, 41631 0, 41632 0, 41633 0, 41634 0, 41635 0, 41636 0, 41637 0, 41638 0, 41639 0, 41640 0, 41641 0, 41642 0, 41643 0, 41644 0, 41645 0, 41646 0, 41647 0, 41648 0, 41649 0, 41650 0, 41651 0, 41652 0, 41653 0, 41654 0, 41655 0, 41656 0, 41657 0, 41658 0, 41659 0, 41660 0, 41661 0, 41662 0, 41663 0, 41664 0, 41665 0, 41666 0, 41667 0, 41668 0, 41669 0, 41670 0, 41671 0, 41672 0, 41673 0, 41674 0, 41675 0, 41676 0, 41677 0, 41678 0, 41679 0, 41680 0, 41681 0, 41682 0, 41683 0, 41684 0, 41685 0, 41686 0, 41687 0, 41688 0, 41689 0, 41690 0, 41691 0, 41692 0, 41693 0, 41694 0, 41695 0, 41696 0, 41697 0, 41698 0, 41699 0, 41700 0, 41701 0, 41702 0, 41703 0, 41704 0, 41705 0, 41706 0, 41707 0, 41708 0, 41709 0, 41710 0, 41711 0, 41712 0, 41713 0, 41714 0, 41715 0, 41716 0, 41717 0, 41718 0, 41719 0, 41720 0, 41721 0, 41722 0, 41723 0, 41724 0, 41725 0, 41726 0, 41727 0, 41728 0, 41729 0, 41730 0, 41731 0, 41732 0, 41733 0, 41734 0, 41735 0, 41736 0, 41737 0, 41738 0, 41739 0, 41740 0, 41741 0, 41742 0, 41743 0, 41744 0, 41745 0, 41746 0, 41747 0, 41748 0, 41749 0, 41750 0, 41751 0, 41752 0, 41753 0, 41754 0, 41755 0, 41756 0, 41757 0, 41758 0, 41759 0, 41760 0, 41761 0, 41762 0, 41763 0, 41764 0, 41765 0, 41766 0, 41767 0, 41768 0, 41769 0, 41770 0, 41771 0, 41772 0, 41773 0, 41774 0, 41775 0, 41776 0, 41777 0, 41778 0, 41779 0, 41780 0, 41781 0, 41782 0, 41783 0, 41784 0, 41785 0, 41786 0, 41787 0, 41788 0, 41789 0, 41790 0, 41791 0, 41792 0, 41793 0, 41794 0, 41795 0, 41796 0, 41797 0, 41798 0, 41799 0, 41800 0, 41801 0, 41802 0, 41803 0, 41804 0, 41805 0, 41806 0, 41807 0, 41808 0, 41809 0, 41810 0, 41811 0, 41812 0, 41813 0, 41814 0, 41815 0, 41816 0, 41817 0, 41818 0, 41819 0, 41820 0, 41821 0, 41822 0, 41823 0, 41824 0, 41825 0, 41826 0, 41827 0, 41828 0, 41829 0, 41830 0, 41831 0, 41832 0, 41833 0, 41834 0, 41835 0, 41836 0, 41837 0, 41838 0, 41839 0, 41840 0, 41841 0, 41842 0, 41843 0, 41844 0, 41845 0, 41846 0, 41847 0, 41848 0, 41849 0, 41850 0, 41851 0, 41852 0, 41853 0, 41854 0, 41855 0, 41856 0, 41857 0, 41858 0, 41859 0, 41860 0, 41861 0, 41862 0, 41863 0, 41864 0, 41865 0, 41866 0, 41867 0, 41868 0, 41869 0, 41870 0, 41871 0, 41872 0, 41873 0, 41874 0, 41875 0, 41876 0, 41877 0, 41878 0, 41879 0, 41880 0, 41881 0, 41882 0, 41883 0, 41884 0, 41885 0, 41886 0, 41887 0, 41888 0, 41889 0, 41890 0, 41891 0, 41892 0, 41893 0, 41894 0, 41895 0, 41896 0, 41897 0, 41898 0, 41899 0, 41900 0, 41901 Field_bitindex_Slot_inst16a_set, 41902 Field_s3to1_Slot_inst16a_set, 41903 Implicit_Field_set, 41904 Implicit_Field_set, 41905 Implicit_Field_set, 41906 Implicit_Field_set, 41907 Implicit_Field_set, 41908 Implicit_Field_set, 41909 Implicit_Field_set, 41910 Implicit_Field_set, 41911 Implicit_Field_set, 41912 Implicit_Field_set, 41913 Implicit_Field_set, 41914 Implicit_Field_set 41915 }; 41916 41917 static xtensa_get_field_fn 41918 Slot_inst16b_get_field_fns[] = { 41919 Field_t_Slot_inst16b_get, 41920 0, 41921 0, 41922 0, 41923 0, 41924 Field_s_Slot_inst16b_get, 41925 0, 41926 0, 41927 0, 41928 0, 41929 0, 41930 Field_op0_Slot_inst16b_get, 41931 0, 41932 0, 41933 Field_r_Slot_inst16b_get, 41934 0, 41935 0, 41936 0, 41937 0, 41938 0, 41939 0, 41940 0, 41941 Field_sr_Slot_inst16b_get, 41942 Field_st_Slot_inst16b_get, 41943 0, 41944 Field_imm4_Slot_inst16b_get, 41945 0, 41946 Field_i_Slot_inst16b_get, 41947 Field_imm6lo_Slot_inst16b_get, 41948 Field_imm6hi_Slot_inst16b_get, 41949 Field_imm7lo_Slot_inst16b_get, 41950 Field_imm7hi_Slot_inst16b_get, 41951 Field_z_Slot_inst16b_get, 41952 Field_imm6_Slot_inst16b_get, 41953 Field_imm7_Slot_inst16b_get, 41954 0, 41955 0, 41956 0, 41957 0, 41958 0, 41959 0, 41960 0, 41961 0, 41962 0, 41963 Field_t2_Slot_inst16b_get, 41964 Field_s2_Slot_inst16b_get, 41965 Field_r2_Slot_inst16b_get, 41966 Field_t4_Slot_inst16b_get, 41967 Field_s4_Slot_inst16b_get, 41968 Field_r4_Slot_inst16b_get, 41969 Field_t8_Slot_inst16b_get, 41970 Field_s8_Slot_inst16b_get, 41971 Field_r8_Slot_inst16b_get, 41972 0, 41973 0, 41974 0, 41975 0, 41976 0, 41977 0, 41978 0, 41979 0, 41980 0, 41981 0, 41982 0, 41983 0, 41984 0, 41985 0, 41986 0, 41987 0, 41988 0, 41989 0, 41990 0, 41991 0, 41992 0, 41993 0, 41994 0, 41995 0, 41996 0, 41997 0, 41998 0, 41999 0, 42000 0, 42001 0, 42002 0, 42003 0, 42004 0, 42005 0, 42006 0, 42007 0, 42008 0, 42009 0, 42010 0, 42011 0, 42012 0, 42013 0, 42014 0, 42015 0, 42016 0, 42017 0, 42018 0, 42019 0, 42020 0, 42021 0, 42022 0, 42023 0, 42024 0, 42025 0, 42026 0, 42027 0, 42028 0, 42029 0, 42030 0, 42031 0, 42032 0, 42033 0, 42034 0, 42035 0, 42036 0, 42037 0, 42038 0, 42039 0, 42040 0, 42041 0, 42042 0, 42043 0, 42044 0, 42045 0, 42046 0, 42047 0, 42048 0, 42049 0, 42050 0, 42051 0, 42052 0, 42053 0, 42054 0, 42055 0, 42056 0, 42057 0, 42058 0, 42059 0, 42060 0, 42061 0, 42062 0, 42063 0, 42064 0, 42065 0, 42066 0, 42067 0, 42068 0, 42069 0, 42070 0, 42071 0, 42072 0, 42073 0, 42074 0, 42075 0, 42076 0, 42077 0, 42078 0, 42079 0, 42080 0, 42081 0, 42082 0, 42083 0, 42084 0, 42085 0, 42086 0, 42087 0, 42088 0, 42089 0, 42090 0, 42091 0, 42092 0, 42093 0, 42094 0, 42095 0, 42096 0, 42097 0, 42098 0, 42099 0, 42100 0, 42101 0, 42102 0, 42103 0, 42104 0, 42105 0, 42106 0, 42107 0, 42108 0, 42109 0, 42110 0, 42111 0, 42112 0, 42113 0, 42114 0, 42115 0, 42116 0, 42117 0, 42118 0, 42119 0, 42120 0, 42121 0, 42122 0, 42123 0, 42124 0, 42125 0, 42126 0, 42127 0, 42128 0, 42129 0, 42130 0, 42131 0, 42132 0, 42133 0, 42134 0, 42135 0, 42136 0, 42137 0, 42138 0, 42139 0, 42140 0, 42141 0, 42142 0, 42143 0, 42144 0, 42145 0, 42146 0, 42147 0, 42148 0, 42149 0, 42150 0, 42151 0, 42152 0, 42153 0, 42154 0, 42155 0, 42156 0, 42157 0, 42158 0, 42159 0, 42160 0, 42161 0, 42162 0, 42163 0, 42164 0, 42165 0, 42166 0, 42167 0, 42168 0, 42169 0, 42170 0, 42171 0, 42172 0, 42173 0, 42174 0, 42175 0, 42176 0, 42177 0, 42178 0, 42179 0, 42180 0, 42181 0, 42182 0, 42183 0, 42184 0, 42185 0, 42186 0, 42187 0, 42188 0, 42189 0, 42190 0, 42191 0, 42192 0, 42193 0, 42194 0, 42195 0, 42196 0, 42197 0, 42198 0, 42199 0, 42200 0, 42201 0, 42202 0, 42203 0, 42204 0, 42205 0, 42206 0, 42207 0, 42208 0, 42209 0, 42210 0, 42211 0, 42212 0, 42213 0, 42214 0, 42215 0, 42216 0, 42217 0, 42218 0, 42219 0, 42220 0, 42221 0, 42222 0, 42223 0, 42224 0, 42225 0, 42226 0, 42227 0, 42228 0, 42229 0, 42230 0, 42231 0, 42232 0, 42233 0, 42234 0, 42235 0, 42236 0, 42237 0, 42238 0, 42239 0, 42240 0, 42241 0, 42242 0, 42243 0, 42244 0, 42245 0, 42246 0, 42247 0, 42248 0, 42249 0, 42250 0, 42251 0, 42252 0, 42253 0, 42254 0, 42255 0, 42256 0, 42257 0, 42258 0, 42259 0, 42260 0, 42261 0, 42262 0, 42263 0, 42264 0, 42265 0, 42266 0, 42267 0, 42268 0, 42269 0, 42270 0, 42271 0, 42272 0, 42273 0, 42274 0, 42275 0, 42276 0, 42277 0, 42278 0, 42279 0, 42280 0, 42281 0, 42282 0, 42283 0, 42284 0, 42285 0, 42286 0, 42287 0, 42288 0, 42289 0, 42290 0, 42291 0, 42292 0, 42293 0, 42294 0, 42295 0, 42296 0, 42297 0, 42298 0, 42299 0, 42300 0, 42301 0, 42302 0, 42303 0, 42304 0, 42305 0, 42306 0, 42307 0, 42308 0, 42309 0, 42310 0, 42311 0, 42312 0, 42313 0, 42314 0, 42315 0, 42316 0, 42317 0, 42318 0, 42319 0, 42320 0, 42321 0, 42322 0, 42323 0, 42324 0, 42325 0, 42326 0, 42327 0, 42328 0, 42329 0, 42330 0, 42331 0, 42332 0, 42333 0, 42334 0, 42335 0, 42336 0, 42337 0, 42338 0, 42339 0, 42340 0, 42341 0, 42342 0, 42343 0, 42344 0, 42345 0, 42346 0, 42347 0, 42348 0, 42349 0, 42350 0, 42351 0, 42352 0, 42353 0, 42354 0, 42355 0, 42356 0, 42357 0, 42358 0, 42359 0, 42360 0, 42361 0, 42362 0, 42363 0, 42364 0, 42365 0, 42366 0, 42367 0, 42368 0, 42369 0, 42370 0, 42371 0, 42372 0, 42373 Field_bitindex_Slot_inst16b_get, 42374 Field_s3to1_Slot_inst16b_get, 42375 Implicit_Field_ar0_get, 42376 Implicit_Field_ar4_get, 42377 Implicit_Field_ar8_get, 42378 Implicit_Field_ar12_get, 42379 Implicit_Field_mr0_get, 42380 Implicit_Field_mr1_get, 42381 Implicit_Field_mr2_get, 42382 Implicit_Field_mr3_get, 42383 Implicit_Field_bt16_get, 42384 Implicit_Field_bs16_get, 42385 Implicit_Field_br16_get, 42386 Implicit_Field_brall_get 42387 }; 42388 42389 static xtensa_set_field_fn 42390 Slot_inst16b_set_field_fns[] = { 42391 Field_t_Slot_inst16b_set, 42392 0, 42393 0, 42394 0, 42395 0, 42396 Field_s_Slot_inst16b_set, 42397 0, 42398 0, 42399 0, 42400 0, 42401 0, 42402 Field_op0_Slot_inst16b_set, 42403 0, 42404 0, 42405 Field_r_Slot_inst16b_set, 42406 0, 42407 0, 42408 0, 42409 0, 42410 0, 42411 0, 42412 0, 42413 Field_sr_Slot_inst16b_set, 42414 Field_st_Slot_inst16b_set, 42415 0, 42416 Field_imm4_Slot_inst16b_set, 42417 0, 42418 Field_i_Slot_inst16b_set, 42419 Field_imm6lo_Slot_inst16b_set, 42420 Field_imm6hi_Slot_inst16b_set, 42421 Field_imm7lo_Slot_inst16b_set, 42422 Field_imm7hi_Slot_inst16b_set, 42423 Field_z_Slot_inst16b_set, 42424 Field_imm6_Slot_inst16b_set, 42425 Field_imm7_Slot_inst16b_set, 42426 0, 42427 0, 42428 0, 42429 0, 42430 0, 42431 0, 42432 0, 42433 0, 42434 0, 42435 Field_t2_Slot_inst16b_set, 42436 Field_s2_Slot_inst16b_set, 42437 Field_r2_Slot_inst16b_set, 42438 Field_t4_Slot_inst16b_set, 42439 Field_s4_Slot_inst16b_set, 42440 Field_r4_Slot_inst16b_set, 42441 Field_t8_Slot_inst16b_set, 42442 Field_s8_Slot_inst16b_set, 42443 Field_r8_Slot_inst16b_set, 42444 0, 42445 0, 42446 0, 42447 0, 42448 0, 42449 0, 42450 0, 42451 0, 42452 0, 42453 0, 42454 0, 42455 0, 42456 0, 42457 0, 42458 0, 42459 0, 42460 0, 42461 0, 42462 0, 42463 0, 42464 0, 42465 0, 42466 0, 42467 0, 42468 0, 42469 0, 42470 0, 42471 0, 42472 0, 42473 0, 42474 0, 42475 0, 42476 0, 42477 0, 42478 0, 42479 0, 42480 0, 42481 0, 42482 0, 42483 0, 42484 0, 42485 0, 42486 0, 42487 0, 42488 0, 42489 0, 42490 0, 42491 0, 42492 0, 42493 0, 42494 0, 42495 0, 42496 0, 42497 0, 42498 0, 42499 0, 42500 0, 42501 0, 42502 0, 42503 0, 42504 0, 42505 0, 42506 0, 42507 0, 42508 0, 42509 0, 42510 0, 42511 0, 42512 0, 42513 0, 42514 0, 42515 0, 42516 0, 42517 0, 42518 0, 42519 0, 42520 0, 42521 0, 42522 0, 42523 0, 42524 0, 42525 0, 42526 0, 42527 0, 42528 0, 42529 0, 42530 0, 42531 0, 42532 0, 42533 0, 42534 0, 42535 0, 42536 0, 42537 0, 42538 0, 42539 0, 42540 0, 42541 0, 42542 0, 42543 0, 42544 0, 42545 0, 42546 0, 42547 0, 42548 0, 42549 0, 42550 0, 42551 0, 42552 0, 42553 0, 42554 0, 42555 0, 42556 0, 42557 0, 42558 0, 42559 0, 42560 0, 42561 0, 42562 0, 42563 0, 42564 0, 42565 0, 42566 0, 42567 0, 42568 0, 42569 0, 42570 0, 42571 0, 42572 0, 42573 0, 42574 0, 42575 0, 42576 0, 42577 0, 42578 0, 42579 0, 42580 0, 42581 0, 42582 0, 42583 0, 42584 0, 42585 0, 42586 0, 42587 0, 42588 0, 42589 0, 42590 0, 42591 0, 42592 0, 42593 0, 42594 0, 42595 0, 42596 0, 42597 0, 42598 0, 42599 0, 42600 0, 42601 0, 42602 0, 42603 0, 42604 0, 42605 0, 42606 0, 42607 0, 42608 0, 42609 0, 42610 0, 42611 0, 42612 0, 42613 0, 42614 0, 42615 0, 42616 0, 42617 0, 42618 0, 42619 0, 42620 0, 42621 0, 42622 0, 42623 0, 42624 0, 42625 0, 42626 0, 42627 0, 42628 0, 42629 0, 42630 0, 42631 0, 42632 0, 42633 0, 42634 0, 42635 0, 42636 0, 42637 0, 42638 0, 42639 0, 42640 0, 42641 0, 42642 0, 42643 0, 42644 0, 42645 0, 42646 0, 42647 0, 42648 0, 42649 0, 42650 0, 42651 0, 42652 0, 42653 0, 42654 0, 42655 0, 42656 0, 42657 0, 42658 0, 42659 0, 42660 0, 42661 0, 42662 0, 42663 0, 42664 0, 42665 0, 42666 0, 42667 0, 42668 0, 42669 0, 42670 0, 42671 0, 42672 0, 42673 0, 42674 0, 42675 0, 42676 0, 42677 0, 42678 0, 42679 0, 42680 0, 42681 0, 42682 0, 42683 0, 42684 0, 42685 0, 42686 0, 42687 0, 42688 0, 42689 0, 42690 0, 42691 0, 42692 0, 42693 0, 42694 0, 42695 0, 42696 0, 42697 0, 42698 0, 42699 0, 42700 0, 42701 0, 42702 0, 42703 0, 42704 0, 42705 0, 42706 0, 42707 0, 42708 0, 42709 0, 42710 0, 42711 0, 42712 0, 42713 0, 42714 0, 42715 0, 42716 0, 42717 0, 42718 0, 42719 0, 42720 0, 42721 0, 42722 0, 42723 0, 42724 0, 42725 0, 42726 0, 42727 0, 42728 0, 42729 0, 42730 0, 42731 0, 42732 0, 42733 0, 42734 0, 42735 0, 42736 0, 42737 0, 42738 0, 42739 0, 42740 0, 42741 0, 42742 0, 42743 0, 42744 0, 42745 0, 42746 0, 42747 0, 42748 0, 42749 0, 42750 0, 42751 0, 42752 0, 42753 0, 42754 0, 42755 0, 42756 0, 42757 0, 42758 0, 42759 0, 42760 0, 42761 0, 42762 0, 42763 0, 42764 0, 42765 0, 42766 0, 42767 0, 42768 0, 42769 0, 42770 0, 42771 0, 42772 0, 42773 0, 42774 0, 42775 0, 42776 0, 42777 0, 42778 0, 42779 0, 42780 0, 42781 0, 42782 0, 42783 0, 42784 0, 42785 0, 42786 0, 42787 0, 42788 0, 42789 0, 42790 0, 42791 0, 42792 0, 42793 0, 42794 0, 42795 0, 42796 0, 42797 0, 42798 0, 42799 0, 42800 0, 42801 0, 42802 0, 42803 0, 42804 0, 42805 0, 42806 0, 42807 0, 42808 0, 42809 0, 42810 0, 42811 0, 42812 0, 42813 0, 42814 0, 42815 0, 42816 0, 42817 0, 42818 0, 42819 0, 42820 0, 42821 0, 42822 0, 42823 0, 42824 0, 42825 0, 42826 0, 42827 0, 42828 0, 42829 0, 42830 0, 42831 0, 42832 0, 42833 0, 42834 0, 42835 0, 42836 0, 42837 0, 42838 0, 42839 0, 42840 0, 42841 0, 42842 0, 42843 0, 42844 0, 42845 Field_bitindex_Slot_inst16b_set, 42846 Field_s3to1_Slot_inst16b_set, 42847 Implicit_Field_set, 42848 Implicit_Field_set, 42849 Implicit_Field_set, 42850 Implicit_Field_set, 42851 Implicit_Field_set, 42852 Implicit_Field_set, 42853 Implicit_Field_set, 42854 Implicit_Field_set, 42855 Implicit_Field_set, 42856 Implicit_Field_set, 42857 Implicit_Field_set, 42858 Implicit_Field_set 42859 }; 42860 42861 static xtensa_get_field_fn 42862 Slot_ae_slot1_get_field_fns[] = { 42863 Field_t_Slot_ae_slot1_get, 42864 0, 42865 0, 42866 0, 42867 0, 42868 0, 42869 0, 42870 0, 42871 0, 42872 0, 42873 0, 42874 0, 42875 0, 42876 0, 42877 0, 42878 0, 42879 0, 42880 0, 42881 0, 42882 0, 42883 0, 42884 0, 42885 0, 42886 0, 42887 0, 42888 0, 42889 0, 42890 0, 42891 0, 42892 0, 42893 0, 42894 0, 42895 0, 42896 0, 42897 0, 42898 0, 42899 0, 42900 0, 42901 0, 42902 0, 42903 0, 42904 0, 42905 0, 42906 0, 42907 Field_t2_Slot_ae_slot1_get, 42908 0, 42909 0, 42910 0, 42911 0, 42912 0, 42913 0, 42914 0, 42915 0, 42916 0, 42917 0, 42918 0, 42919 0, 42920 0, 42921 Field_ae_r32_Slot_ae_slot1_get, 42922 0, 42923 Field_ae_r20_Slot_ae_slot1_get, 42924 Field_ae_r10_Slot_ae_slot1_get, 42925 Field_ae_s20_Slot_ae_slot1_get, 42926 0, 42927 0, 42928 Field_op0_s3_Slot_ae_slot1_get, 42929 Field_ftsf11_Slot_ae_slot1_get, 42930 Field_ftsf12_Slot_ae_slot1_get, 42931 Field_ftsf13_Slot_ae_slot1_get, 42932 Field_ftsf20ae_slot1_Slot_ae_slot1_get, 42933 Field_ftsf21ae_slot1_Slot_ae_slot1_get, 42934 Field_ftsf22ae_slot1_Slot_ae_slot1_get, 42935 Field_ftsf23ae_slot1_Slot_ae_slot1_get, 42936 Field_ftsf24ae_slot1_Slot_ae_slot1_get, 42937 Field_ftsf25ae_slot1_Slot_ae_slot1_get, 42938 Field_ftsf26ae_slot1_Slot_ae_slot1_get, 42939 Field_ftsf27ae_slot1_Slot_ae_slot1_get, 42940 Field_ftsf28ae_slot1_Slot_ae_slot1_get, 42941 Field_ftsf29ae_slot1_Slot_ae_slot1_get, 42942 Field_ftsf30ae_slot1_Slot_ae_slot1_get, 42943 Field_ftsf31ae_slot1_Slot_ae_slot1_get, 42944 Field_ftsf32ae_slot1_Slot_ae_slot1_get, 42945 Field_ftsf33ae_slot1_Slot_ae_slot1_get, 42946 Field_ftsf34ae_slot1_Slot_ae_slot1_get, 42947 Field_ftsf35ae_slot1_Slot_ae_slot1_get, 42948 Field_ftsf36ae_slot1_Slot_ae_slot1_get, 42949 Field_ftsf37ae_slot1_Slot_ae_slot1_get, 42950 Field_ftsf38ae_slot1_Slot_ae_slot1_get, 42951 Field_ftsf40ae_slot1_Slot_ae_slot1_get, 42952 Field_ftsf41ae_slot1_Slot_ae_slot1_get, 42953 Field_ftsf42ae_slot1_Slot_ae_slot1_get, 42954 Field_ftsf43ae_slot1_Slot_ae_slot1_get, 42955 Field_ftsf45ae_slot1_Slot_ae_slot1_get, 42956 Field_ftsf47ae_slot1_Slot_ae_slot1_get, 42957 Field_ftsf48ae_slot1_Slot_ae_slot1_get, 42958 Field_ftsf49ae_slot1_Slot_ae_slot1_get, 42959 Field_ftsf50ae_slot1_Slot_ae_slot1_get, 42960 Field_ftsf51ae_slot1_Slot_ae_slot1_get, 42961 Field_ftsf52ae_slot1_Slot_ae_slot1_get, 42962 Field_ftsf53ae_slot1_Slot_ae_slot1_get, 42963 Field_ftsf54ae_slot1_Slot_ae_slot1_get, 42964 Field_ftsf55_Slot_ae_slot1_get, 42965 Field_ftsf56ae_slot1_Slot_ae_slot1_get, 42966 Field_ftsf57ae_slot1_Slot_ae_slot1_get, 42967 Field_ftsf58ae_slot1_Slot_ae_slot1_get, 42968 Field_ftsf60ae_slot1_Slot_ae_slot1_get, 42969 Field_ftsf61_Slot_ae_slot1_get, 42970 Field_ftsf62ae_slot1_Slot_ae_slot1_get, 42971 Field_ftsf63ae_slot1_Slot_ae_slot1_get, 42972 Field_ftsf64ae_slot1_Slot_ae_slot1_get, 42973 Field_ftsf66ae_slot1_Slot_ae_slot1_get, 42974 Field_ftsf68ae_slot1_Slot_ae_slot1_get, 42975 Field_ftsf69ae_slot1_Slot_ae_slot1_get, 42976 Field_ftsf70ae_slot1_Slot_ae_slot1_get, 42977 Field_ftsf71ae_slot1_Slot_ae_slot1_get, 42978 Field_ftsf72ae_slot1_Slot_ae_slot1_get, 42979 Field_ftsf73ae_slot1_Slot_ae_slot1_get, 42980 Field_ftsf74ae_slot1_Slot_ae_slot1_get, 42981 Field_ftsf75ae_slot1_Slot_ae_slot1_get, 42982 Field_ftsf76ae_slot1_Slot_ae_slot1_get, 42983 Field_ftsf77ae_slot1_Slot_ae_slot1_get, 42984 Field_ftsf78ae_slot1_Slot_ae_slot1_get, 42985 Field_ftsf79ae_slot1_Slot_ae_slot1_get, 42986 Field_ftsf80ae_slot1_Slot_ae_slot1_get, 42987 Field_ftsf81ae_slot1_Slot_ae_slot1_get, 42988 Field_ftsf82ae_slot1_Slot_ae_slot1_get, 42989 Field_ftsf83ae_slot1_Slot_ae_slot1_get, 42990 Field_ftsf84ae_slot1_Slot_ae_slot1_get, 42991 Field_ftsf85ae_slot1_Slot_ae_slot1_get, 42992 Field_ftsf86ae_slot1_Slot_ae_slot1_get, 42993 Field_ftsf87ae_slot1_Slot_ae_slot1_get, 42994 Field_ftsf88ae_slot1_Slot_ae_slot1_get, 42995 Field_ftsf89ae_slot1_Slot_ae_slot1_get, 42996 Field_ftsf90ae_slot1_Slot_ae_slot1_get, 42997 Field_ftsf91_Slot_ae_slot1_get, 42998 Field_ftsf92ae_slot1_Slot_ae_slot1_get, 42999 Field_ftsf93ae_slot1_Slot_ae_slot1_get, 43000 Field_ftsf94ae_slot1_Slot_ae_slot1_get, 43001 Field_ftsf96ae_slot1_Slot_ae_slot1_get, 43002 Field_ftsf97ae_slot1_Slot_ae_slot1_get, 43003 Field_ftsf99ae_slot1_Slot_ae_slot1_get, 43004 Field_ftsf101ae_slot1_Slot_ae_slot1_get, 43005 Field_ftsf102ae_slot1_Slot_ae_slot1_get, 43006 Field_ftsf103ae_slot1_Slot_ae_slot1_get, 43007 Field_ftsf106ae_slot1_Slot_ae_slot1_get, 43008 Field_ftsf107ae_slot1_Slot_ae_slot1_get, 43009 Field_ftsf108ae_slot1_Slot_ae_slot1_get, 43010 Field_ftsf109ae_slot1_Slot_ae_slot1_get, 43011 Field_ftsf110ae_slot1_Slot_ae_slot1_get, 43012 Field_ftsf111ae_slot1_Slot_ae_slot1_get, 43013 Field_ftsf112ae_slot1_Slot_ae_slot1_get, 43014 Field_ftsf113ae_slot1_Slot_ae_slot1_get, 43015 Field_ftsf114ae_slot1_Slot_ae_slot1_get, 43016 Field_ftsf115ae_slot1_Slot_ae_slot1_get, 43017 Field_ftsf116ae_slot1_Slot_ae_slot1_get, 43018 Field_ftsf117ae_slot1_Slot_ae_slot1_get, 43019 Field_ftsf118ae_slot1_Slot_ae_slot1_get, 43020 Field_ftsf120ae_slot1_Slot_ae_slot1_get, 43021 Field_ftsf121ae_slot1_Slot_ae_slot1_get, 43022 Field_ftsf123ae_slot1_Slot_ae_slot1_get, 43023 Field_ftsf124ae_slot1_Slot_ae_slot1_get, 43024 Field_ftsf125ae_slot1_Slot_ae_slot1_get, 43025 Field_ftsf126ae_slot1_Slot_ae_slot1_get, 43026 Field_ftsf127ae_slot1_Slot_ae_slot1_get, 43027 Field_ftsf128ae_slot1_Slot_ae_slot1_get, 43028 Field_ftsf129ae_slot1_Slot_ae_slot1_get, 43029 Field_ftsf130ae_slot1_Slot_ae_slot1_get, 43030 Field_ftsf131ae_slot1_Slot_ae_slot1_get, 43031 Field_ftsf132ae_slot1_Slot_ae_slot1_get, 43032 Field_ftsf133ae_slot1_Slot_ae_slot1_get, 43033 Field_ftsf134ae_slot1_Slot_ae_slot1_get, 43034 Field_ftsf135ae_slot1_Slot_ae_slot1_get, 43035 Field_ftsf136ae_slot1_Slot_ae_slot1_get, 43036 Field_ftsf137ae_slot1_Slot_ae_slot1_get, 43037 Field_ftsf138ae_slot1_Slot_ae_slot1_get, 43038 Field_ftsf139ae_slot1_Slot_ae_slot1_get, 43039 Field_ftsf140ae_slot1_Slot_ae_slot1_get, 43040 Field_ftsf141ae_slot1_Slot_ae_slot1_get, 43041 Field_ftsf142ae_slot1_Slot_ae_slot1_get, 43042 Field_ftsf143ae_slot1_Slot_ae_slot1_get, 43043 Field_ftsf144ae_slot1_Slot_ae_slot1_get, 43044 Field_ftsf145ae_slot1_Slot_ae_slot1_get, 43045 Field_ftsf146ae_slot1_Slot_ae_slot1_get, 43046 Field_ftsf147ae_slot1_Slot_ae_slot1_get, 43047 Field_ftsf148ae_slot1_Slot_ae_slot1_get, 43048 Field_ftsf149ae_slot1_Slot_ae_slot1_get, 43049 Field_ftsf150ae_slot1_Slot_ae_slot1_get, 43050 Field_ftsf151ae_slot1_Slot_ae_slot1_get, 43051 Field_ftsf152ae_slot1_Slot_ae_slot1_get, 43052 Field_ftsf153ae_slot1_Slot_ae_slot1_get, 43053 Field_ftsf154ae_slot1_Slot_ae_slot1_get, 43054 Field_ftsf155ae_slot1_Slot_ae_slot1_get, 43055 Field_ftsf156ae_slot1_Slot_ae_slot1_get, 43056 Field_ftsf157ae_slot1_Slot_ae_slot1_get, 43057 Field_ftsf158ae_slot1_Slot_ae_slot1_get, 43058 Field_ftsf159ae_slot1_Slot_ae_slot1_get, 43059 Field_ftsf160ae_slot1_Slot_ae_slot1_get, 43060 Field_ftsf161ae_slot1_Slot_ae_slot1_get, 43061 Field_ftsf162ae_slot1_Slot_ae_slot1_get, 43062 Field_ftsf163ae_slot1_Slot_ae_slot1_get, 43063 Field_ftsf164ae_slot1_Slot_ae_slot1_get, 43064 Field_ftsf165ae_slot1_Slot_ae_slot1_get, 43065 Field_ftsf166ae_slot1_Slot_ae_slot1_get, 43066 Field_ftsf167ae_slot1_Slot_ae_slot1_get, 43067 Field_ftsf168ae_slot1_Slot_ae_slot1_get, 43068 Field_ftsf169ae_slot1_Slot_ae_slot1_get, 43069 Field_ftsf170ae_slot1_Slot_ae_slot1_get, 43070 Field_ftsf171ae_slot1_Slot_ae_slot1_get, 43071 Field_ftsf172ae_slot1_Slot_ae_slot1_get, 43072 Field_ftsf173ae_slot1_Slot_ae_slot1_get, 43073 Field_ftsf174ae_slot1_Slot_ae_slot1_get, 43074 Field_ftsf175ae_slot1_Slot_ae_slot1_get, 43075 Field_ftsf176ae_slot1_Slot_ae_slot1_get, 43076 Field_ftsf177ae_slot1_Slot_ae_slot1_get, 43077 Field_ftsf178ae_slot1_Slot_ae_slot1_get, 43078 Field_ftsf179ae_slot1_Slot_ae_slot1_get, 43079 Field_ftsf180ae_slot1_Slot_ae_slot1_get, 43080 Field_ftsf181ae_slot1_Slot_ae_slot1_get, 43081 Field_ftsf182ae_slot1_Slot_ae_slot1_get, 43082 Field_ftsf183ae_slot1_Slot_ae_slot1_get, 43083 Field_ftsf184ae_slot1_Slot_ae_slot1_get, 43084 Field_ftsf185ae_slot1_Slot_ae_slot1_get, 43085 Field_ftsf186ae_slot1_Slot_ae_slot1_get, 43086 Field_ftsf187ae_slot1_Slot_ae_slot1_get, 43087 Field_ftsf188ae_slot1_Slot_ae_slot1_get, 43088 Field_ftsf189ae_slot1_Slot_ae_slot1_get, 43089 Field_ftsf190ae_slot1_Slot_ae_slot1_get, 43090 Field_ftsf191ae_slot1_Slot_ae_slot1_get, 43091 Field_ftsf192ae_slot1_Slot_ae_slot1_get, 43092 Field_ftsf193ae_slot1_Slot_ae_slot1_get, 43093 Field_ftsf194ae_slot1_Slot_ae_slot1_get, 43094 Field_ftsf195ae_slot1_Slot_ae_slot1_get, 43095 Field_ftsf196ae_slot1_Slot_ae_slot1_get, 43096 Field_ftsf197ae_slot1_Slot_ae_slot1_get, 43097 Field_ftsf198ae_slot1_Slot_ae_slot1_get, 43098 Field_ftsf199ae_slot1_Slot_ae_slot1_get, 43099 Field_ftsf200ae_slot1_Slot_ae_slot1_get, 43100 Field_ftsf201ae_slot1_Slot_ae_slot1_get, 43101 Field_ftsf202ae_slot1_Slot_ae_slot1_get, 43102 Field_ftsf203ae_slot1_Slot_ae_slot1_get, 43103 Field_ftsf204ae_slot1_Slot_ae_slot1_get, 43104 Field_ftsf205ae_slot1_Slot_ae_slot1_get, 43105 Field_ftsf206ae_slot1_Slot_ae_slot1_get, 43106 Field_ftsf207ae_slot1_Slot_ae_slot1_get, 43107 Field_ftsf208ae_slot1_Slot_ae_slot1_get, 43108 Field_ftsf210ae_slot1_Slot_ae_slot1_get, 43109 Field_ftsf333ae_slot1_Slot_ae_slot1_get, 43110 Field_ftsf334ae_slot1_Slot_ae_slot1_get, 43111 Field_ftsf335_Slot_ae_slot1_get, 43112 Field_ftsf336ae_slot1_Slot_ae_slot1_get, 43113 Field_ftsf337ae_slot1_Slot_ae_slot1_get, 43114 Field_ftsf339ae_slot1_Slot_ae_slot1_get, 43115 Field_ftsf340ae_slot1_Slot_ae_slot1_get, 43116 Field_ftsf341ae_slot1_Slot_ae_slot1_get, 43117 Field_ftsf342ae_slot1_Slot_ae_slot1_get, 43118 Field_ftsf343ae_slot1_Slot_ae_slot1_get, 43119 Field_ftsf344ae_slot1_Slot_ae_slot1_get, 43120 Field_ftsf345ae_slot1_Slot_ae_slot1_get, 43121 Field_ftsf347ae_slot1_Slot_ae_slot1_get, 43122 Field_ftsf348ae_slot1_Slot_ae_slot1_get, 43123 Field_ftsf349ae_slot1_Slot_ae_slot1_get, 43124 Field_ftsf350ae_slot1_Slot_ae_slot1_get, 43125 Field_ftsf351_Slot_ae_slot1_get, 43126 Field_ftsf352ae_slot1_Slot_ae_slot1_get, 43127 Field_ftsf354ae_slot1_Slot_ae_slot1_get, 43128 Field_ftsf355ae_slot1_Slot_ae_slot1_get, 43129 Field_ftsf356ae_slot1_Slot_ae_slot1_get, 43130 Field_ftsf357ae_slot1_Slot_ae_slot1_get, 43131 Field_ftsf358ae_slot1_Slot_ae_slot1_get, 43132 Field_ftsf359ae_slot1_Slot_ae_slot1_get, 43133 0, 43134 0, 43135 0, 43136 0, 43137 0, 43138 0, 43139 0, 43140 0, 43141 0, 43142 0, 43143 0, 43144 0, 43145 0, 43146 0, 43147 0, 43148 0, 43149 0, 43150 0, 43151 0, 43152 0, 43153 0, 43154 0, 43155 0, 43156 0, 43157 0, 43158 0, 43159 0, 43160 0, 43161 0, 43162 0, 43163 0, 43164 0, 43165 0, 43166 0, 43167 0, 43168 0, 43169 0, 43170 0, 43171 0, 43172 0, 43173 0, 43174 0, 43175 0, 43176 0, 43177 0, 43178 0, 43179 0, 43180 0, 43181 0, 43182 0, 43183 0, 43184 0, 43185 0, 43186 0, 43187 0, 43188 0, 43189 0, 43190 0, 43191 0, 43192 0, 43193 0, 43194 0, 43195 0, 43196 0, 43197 0, 43198 0, 43199 0, 43200 0, 43201 0, 43202 0, 43203 0, 43204 0, 43205 0, 43206 0, 43207 0, 43208 0, 43209 0, 43210 0, 43211 0, 43212 0, 43213 0, 43214 0, 43215 0, 43216 0, 43217 0, 43218 0, 43219 0, 43220 0, 43221 0, 43222 0, 43223 0, 43224 0, 43225 0, 43226 0, 43227 0, 43228 0, 43229 0, 43230 0, 43231 0, 43232 0, 43233 0, 43234 0, 43235 0, 43236 0, 43237 0, 43238 0, 43239 0, 43240 0, 43241 0, 43242 0, 43243 0, 43244 0, 43245 0, 43246 0, 43247 0, 43248 0, 43249 0, 43250 0, 43251 0, 43252 0, 43253 0, 43254 0, 43255 0, 43256 0, 43257 0, 43258 0, 43259 0, 43260 0, 43261 0, 43262 0, 43263 0, 43264 Field_ae_mul32x24fld_Slot_ae_slot1_get, 43265 0, 43266 0, 43267 0, 43268 0, 43269 0, 43270 0, 43271 0, 43272 0, 43273 0, 43274 0, 43275 0, 43276 0, 43277 0, 43278 0, 43279 0, 43280 0, 43281 0, 43282 0, 43283 0, 43284 0, 43285 0, 43286 0, 43287 0, 43288 0, 43289 0, 43290 0, 43291 0, 43292 0, 43293 0, 43294 0, 43295 0, 43296 0, 43297 0, 43298 0, 43299 0, 43300 0, 43301 Field_op0_s3_s3_Slot_ae_slot1_get, 43302 Field_combined2c0b5f72_fld19_Slot_ae_slot1_get, 43303 Field_combined2c0b5f72_fld22_Slot_ae_slot1_get, 43304 Field_combined2c0b5f72_fld24_Slot_ae_slot1_get, 43305 Field_combined2c0b5f72_fld65_Slot_ae_slot1_get, 43306 Field_combined2c0b5f72_fld66_Slot_ae_slot1_get, 43307 Field_combined2c0b5f72_fld68_Slot_ae_slot1_get, 43308 Field_combined2c0b5f72_fld69_Slot_ae_slot1_get, 43309 Field_combined2c0b5f72_fld74_Slot_ae_slot1_get, 43310 Field_combined2c0b5f72_fld79_Slot_ae_slot1_get, 43311 Field_combined2c0b5f72_fld88_Slot_ae_slot1_get, 43312 Field_combined2c0b5f72_fld90_Slot_ae_slot1_get, 43313 Field_combined2c0b5f72_fld91_Slot_ae_slot1_get, 43314 Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_get, 43315 Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_get, 43316 Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_get, 43317 0, 43318 0, 43319 Implicit_Field_ar0_get, 43320 Implicit_Field_ar4_get, 43321 Implicit_Field_ar8_get, 43322 Implicit_Field_ar12_get, 43323 Implicit_Field_mr0_get, 43324 Implicit_Field_mr1_get, 43325 Implicit_Field_mr2_get, 43326 Implicit_Field_mr3_get, 43327 Implicit_Field_bt16_get, 43328 Implicit_Field_bs16_get, 43329 Implicit_Field_br16_get, 43330 Implicit_Field_brall_get 43331 }; 43332 43333 static xtensa_set_field_fn 43334 Slot_ae_slot1_set_field_fns[] = { 43335 Field_t_Slot_ae_slot1_set, 43336 0, 43337 0, 43338 0, 43339 0, 43340 0, 43341 0, 43342 0, 43343 0, 43344 0, 43345 0, 43346 0, 43347 0, 43348 0, 43349 0, 43350 0, 43351 0, 43352 0, 43353 0, 43354 0, 43355 0, 43356 0, 43357 0, 43358 0, 43359 0, 43360 0, 43361 0, 43362 0, 43363 0, 43364 0, 43365 0, 43366 0, 43367 0, 43368 0, 43369 0, 43370 0, 43371 0, 43372 0, 43373 0, 43374 0, 43375 0, 43376 0, 43377 0, 43378 0, 43379 Field_t2_Slot_ae_slot1_set, 43380 0, 43381 0, 43382 0, 43383 0, 43384 0, 43385 0, 43386 0, 43387 0, 43388 0, 43389 0, 43390 0, 43391 0, 43392 0, 43393 Field_ae_r32_Slot_ae_slot1_set, 43394 0, 43395 Field_ae_r20_Slot_ae_slot1_set, 43396 Field_ae_r10_Slot_ae_slot1_set, 43397 Field_ae_s20_Slot_ae_slot1_set, 43398 0, 43399 0, 43400 Field_op0_s3_Slot_ae_slot1_set, 43401 Field_ftsf11_Slot_ae_slot1_set, 43402 Field_ftsf12_Slot_ae_slot1_set, 43403 Field_ftsf13_Slot_ae_slot1_set, 43404 Field_ftsf20ae_slot1_Slot_ae_slot1_set, 43405 Field_ftsf21ae_slot1_Slot_ae_slot1_set, 43406 Field_ftsf22ae_slot1_Slot_ae_slot1_set, 43407 Field_ftsf23ae_slot1_Slot_ae_slot1_set, 43408 Field_ftsf24ae_slot1_Slot_ae_slot1_set, 43409 Field_ftsf25ae_slot1_Slot_ae_slot1_set, 43410 Field_ftsf26ae_slot1_Slot_ae_slot1_set, 43411 Field_ftsf27ae_slot1_Slot_ae_slot1_set, 43412 Field_ftsf28ae_slot1_Slot_ae_slot1_set, 43413 Field_ftsf29ae_slot1_Slot_ae_slot1_set, 43414 Field_ftsf30ae_slot1_Slot_ae_slot1_set, 43415 Field_ftsf31ae_slot1_Slot_ae_slot1_set, 43416 Field_ftsf32ae_slot1_Slot_ae_slot1_set, 43417 Field_ftsf33ae_slot1_Slot_ae_slot1_set, 43418 Field_ftsf34ae_slot1_Slot_ae_slot1_set, 43419 Field_ftsf35ae_slot1_Slot_ae_slot1_set, 43420 Field_ftsf36ae_slot1_Slot_ae_slot1_set, 43421 Field_ftsf37ae_slot1_Slot_ae_slot1_set, 43422 Field_ftsf38ae_slot1_Slot_ae_slot1_set, 43423 Field_ftsf40ae_slot1_Slot_ae_slot1_set, 43424 Field_ftsf41ae_slot1_Slot_ae_slot1_set, 43425 Field_ftsf42ae_slot1_Slot_ae_slot1_set, 43426 Field_ftsf43ae_slot1_Slot_ae_slot1_set, 43427 Field_ftsf45ae_slot1_Slot_ae_slot1_set, 43428 Field_ftsf47ae_slot1_Slot_ae_slot1_set, 43429 Field_ftsf48ae_slot1_Slot_ae_slot1_set, 43430 Field_ftsf49ae_slot1_Slot_ae_slot1_set, 43431 Field_ftsf50ae_slot1_Slot_ae_slot1_set, 43432 Field_ftsf51ae_slot1_Slot_ae_slot1_set, 43433 Field_ftsf52ae_slot1_Slot_ae_slot1_set, 43434 Field_ftsf53ae_slot1_Slot_ae_slot1_set, 43435 Field_ftsf54ae_slot1_Slot_ae_slot1_set, 43436 Field_ftsf55_Slot_ae_slot1_set, 43437 Field_ftsf56ae_slot1_Slot_ae_slot1_set, 43438 Field_ftsf57ae_slot1_Slot_ae_slot1_set, 43439 Field_ftsf58ae_slot1_Slot_ae_slot1_set, 43440 Field_ftsf60ae_slot1_Slot_ae_slot1_set, 43441 Field_ftsf61_Slot_ae_slot1_set, 43442 Field_ftsf62ae_slot1_Slot_ae_slot1_set, 43443 Field_ftsf63ae_slot1_Slot_ae_slot1_set, 43444 Field_ftsf64ae_slot1_Slot_ae_slot1_set, 43445 Field_ftsf66ae_slot1_Slot_ae_slot1_set, 43446 Field_ftsf68ae_slot1_Slot_ae_slot1_set, 43447 Field_ftsf69ae_slot1_Slot_ae_slot1_set, 43448 Field_ftsf70ae_slot1_Slot_ae_slot1_set, 43449 Field_ftsf71ae_slot1_Slot_ae_slot1_set, 43450 Field_ftsf72ae_slot1_Slot_ae_slot1_set, 43451 Field_ftsf73ae_slot1_Slot_ae_slot1_set, 43452 Field_ftsf74ae_slot1_Slot_ae_slot1_set, 43453 Field_ftsf75ae_slot1_Slot_ae_slot1_set, 43454 Field_ftsf76ae_slot1_Slot_ae_slot1_set, 43455 Field_ftsf77ae_slot1_Slot_ae_slot1_set, 43456 Field_ftsf78ae_slot1_Slot_ae_slot1_set, 43457 Field_ftsf79ae_slot1_Slot_ae_slot1_set, 43458 Field_ftsf80ae_slot1_Slot_ae_slot1_set, 43459 Field_ftsf81ae_slot1_Slot_ae_slot1_set, 43460 Field_ftsf82ae_slot1_Slot_ae_slot1_set, 43461 Field_ftsf83ae_slot1_Slot_ae_slot1_set, 43462 Field_ftsf84ae_slot1_Slot_ae_slot1_set, 43463 Field_ftsf85ae_slot1_Slot_ae_slot1_set, 43464 Field_ftsf86ae_slot1_Slot_ae_slot1_set, 43465 Field_ftsf87ae_slot1_Slot_ae_slot1_set, 43466 Field_ftsf88ae_slot1_Slot_ae_slot1_set, 43467 Field_ftsf89ae_slot1_Slot_ae_slot1_set, 43468 Field_ftsf90ae_slot1_Slot_ae_slot1_set, 43469 Field_ftsf91_Slot_ae_slot1_set, 43470 Field_ftsf92ae_slot1_Slot_ae_slot1_set, 43471 Field_ftsf93ae_slot1_Slot_ae_slot1_set, 43472 Field_ftsf94ae_slot1_Slot_ae_slot1_set, 43473 Field_ftsf96ae_slot1_Slot_ae_slot1_set, 43474 Field_ftsf97ae_slot1_Slot_ae_slot1_set, 43475 Field_ftsf99ae_slot1_Slot_ae_slot1_set, 43476 Field_ftsf101ae_slot1_Slot_ae_slot1_set, 43477 Field_ftsf102ae_slot1_Slot_ae_slot1_set, 43478 Field_ftsf103ae_slot1_Slot_ae_slot1_set, 43479 Field_ftsf106ae_slot1_Slot_ae_slot1_set, 43480 Field_ftsf107ae_slot1_Slot_ae_slot1_set, 43481 Field_ftsf108ae_slot1_Slot_ae_slot1_set, 43482 Field_ftsf109ae_slot1_Slot_ae_slot1_set, 43483 Field_ftsf110ae_slot1_Slot_ae_slot1_set, 43484 Field_ftsf111ae_slot1_Slot_ae_slot1_set, 43485 Field_ftsf112ae_slot1_Slot_ae_slot1_set, 43486 Field_ftsf113ae_slot1_Slot_ae_slot1_set, 43487 Field_ftsf114ae_slot1_Slot_ae_slot1_set, 43488 Field_ftsf115ae_slot1_Slot_ae_slot1_set, 43489 Field_ftsf116ae_slot1_Slot_ae_slot1_set, 43490 Field_ftsf117ae_slot1_Slot_ae_slot1_set, 43491 Field_ftsf118ae_slot1_Slot_ae_slot1_set, 43492 Field_ftsf120ae_slot1_Slot_ae_slot1_set, 43493 Field_ftsf121ae_slot1_Slot_ae_slot1_set, 43494 Field_ftsf123ae_slot1_Slot_ae_slot1_set, 43495 Field_ftsf124ae_slot1_Slot_ae_slot1_set, 43496 Field_ftsf125ae_slot1_Slot_ae_slot1_set, 43497 Field_ftsf126ae_slot1_Slot_ae_slot1_set, 43498 Field_ftsf127ae_slot1_Slot_ae_slot1_set, 43499 Field_ftsf128ae_slot1_Slot_ae_slot1_set, 43500 Field_ftsf129ae_slot1_Slot_ae_slot1_set, 43501 Field_ftsf130ae_slot1_Slot_ae_slot1_set, 43502 Field_ftsf131ae_slot1_Slot_ae_slot1_set, 43503 Field_ftsf132ae_slot1_Slot_ae_slot1_set, 43504 Field_ftsf133ae_slot1_Slot_ae_slot1_set, 43505 Field_ftsf134ae_slot1_Slot_ae_slot1_set, 43506 Field_ftsf135ae_slot1_Slot_ae_slot1_set, 43507 Field_ftsf136ae_slot1_Slot_ae_slot1_set, 43508 Field_ftsf137ae_slot1_Slot_ae_slot1_set, 43509 Field_ftsf138ae_slot1_Slot_ae_slot1_set, 43510 Field_ftsf139ae_slot1_Slot_ae_slot1_set, 43511 Field_ftsf140ae_slot1_Slot_ae_slot1_set, 43512 Field_ftsf141ae_slot1_Slot_ae_slot1_set, 43513 Field_ftsf142ae_slot1_Slot_ae_slot1_set, 43514 Field_ftsf143ae_slot1_Slot_ae_slot1_set, 43515 Field_ftsf144ae_slot1_Slot_ae_slot1_set, 43516 Field_ftsf145ae_slot1_Slot_ae_slot1_set, 43517 Field_ftsf146ae_slot1_Slot_ae_slot1_set, 43518 Field_ftsf147ae_slot1_Slot_ae_slot1_set, 43519 Field_ftsf148ae_slot1_Slot_ae_slot1_set, 43520 Field_ftsf149ae_slot1_Slot_ae_slot1_set, 43521 Field_ftsf150ae_slot1_Slot_ae_slot1_set, 43522 Field_ftsf151ae_slot1_Slot_ae_slot1_set, 43523 Field_ftsf152ae_slot1_Slot_ae_slot1_set, 43524 Field_ftsf153ae_slot1_Slot_ae_slot1_set, 43525 Field_ftsf154ae_slot1_Slot_ae_slot1_set, 43526 Field_ftsf155ae_slot1_Slot_ae_slot1_set, 43527 Field_ftsf156ae_slot1_Slot_ae_slot1_set, 43528 Field_ftsf157ae_slot1_Slot_ae_slot1_set, 43529 Field_ftsf158ae_slot1_Slot_ae_slot1_set, 43530 Field_ftsf159ae_slot1_Slot_ae_slot1_set, 43531 Field_ftsf160ae_slot1_Slot_ae_slot1_set, 43532 Field_ftsf161ae_slot1_Slot_ae_slot1_set, 43533 Field_ftsf162ae_slot1_Slot_ae_slot1_set, 43534 Field_ftsf163ae_slot1_Slot_ae_slot1_set, 43535 Field_ftsf164ae_slot1_Slot_ae_slot1_set, 43536 Field_ftsf165ae_slot1_Slot_ae_slot1_set, 43537 Field_ftsf166ae_slot1_Slot_ae_slot1_set, 43538 Field_ftsf167ae_slot1_Slot_ae_slot1_set, 43539 Field_ftsf168ae_slot1_Slot_ae_slot1_set, 43540 Field_ftsf169ae_slot1_Slot_ae_slot1_set, 43541 Field_ftsf170ae_slot1_Slot_ae_slot1_set, 43542 Field_ftsf171ae_slot1_Slot_ae_slot1_set, 43543 Field_ftsf172ae_slot1_Slot_ae_slot1_set, 43544 Field_ftsf173ae_slot1_Slot_ae_slot1_set, 43545 Field_ftsf174ae_slot1_Slot_ae_slot1_set, 43546 Field_ftsf175ae_slot1_Slot_ae_slot1_set, 43547 Field_ftsf176ae_slot1_Slot_ae_slot1_set, 43548 Field_ftsf177ae_slot1_Slot_ae_slot1_set, 43549 Field_ftsf178ae_slot1_Slot_ae_slot1_set, 43550 Field_ftsf179ae_slot1_Slot_ae_slot1_set, 43551 Field_ftsf180ae_slot1_Slot_ae_slot1_set, 43552 Field_ftsf181ae_slot1_Slot_ae_slot1_set, 43553 Field_ftsf182ae_slot1_Slot_ae_slot1_set, 43554 Field_ftsf183ae_slot1_Slot_ae_slot1_set, 43555 Field_ftsf184ae_slot1_Slot_ae_slot1_set, 43556 Field_ftsf185ae_slot1_Slot_ae_slot1_set, 43557 Field_ftsf186ae_slot1_Slot_ae_slot1_set, 43558 Field_ftsf187ae_slot1_Slot_ae_slot1_set, 43559 Field_ftsf188ae_slot1_Slot_ae_slot1_set, 43560 Field_ftsf189ae_slot1_Slot_ae_slot1_set, 43561 Field_ftsf190ae_slot1_Slot_ae_slot1_set, 43562 Field_ftsf191ae_slot1_Slot_ae_slot1_set, 43563 Field_ftsf192ae_slot1_Slot_ae_slot1_set, 43564 Field_ftsf193ae_slot1_Slot_ae_slot1_set, 43565 Field_ftsf194ae_slot1_Slot_ae_slot1_set, 43566 Field_ftsf195ae_slot1_Slot_ae_slot1_set, 43567 Field_ftsf196ae_slot1_Slot_ae_slot1_set, 43568 Field_ftsf197ae_slot1_Slot_ae_slot1_set, 43569 Field_ftsf198ae_slot1_Slot_ae_slot1_set, 43570 Field_ftsf199ae_slot1_Slot_ae_slot1_set, 43571 Field_ftsf200ae_slot1_Slot_ae_slot1_set, 43572 Field_ftsf201ae_slot1_Slot_ae_slot1_set, 43573 Field_ftsf202ae_slot1_Slot_ae_slot1_set, 43574 Field_ftsf203ae_slot1_Slot_ae_slot1_set, 43575 Field_ftsf204ae_slot1_Slot_ae_slot1_set, 43576 Field_ftsf205ae_slot1_Slot_ae_slot1_set, 43577 Field_ftsf206ae_slot1_Slot_ae_slot1_set, 43578 Field_ftsf207ae_slot1_Slot_ae_slot1_set, 43579 Field_ftsf208ae_slot1_Slot_ae_slot1_set, 43580 Field_ftsf210ae_slot1_Slot_ae_slot1_set, 43581 Field_ftsf333ae_slot1_Slot_ae_slot1_set, 43582 Field_ftsf334ae_slot1_Slot_ae_slot1_set, 43583 Field_ftsf335_Slot_ae_slot1_set, 43584 Field_ftsf336ae_slot1_Slot_ae_slot1_set, 43585 Field_ftsf337ae_slot1_Slot_ae_slot1_set, 43586 Field_ftsf339ae_slot1_Slot_ae_slot1_set, 43587 Field_ftsf340ae_slot1_Slot_ae_slot1_set, 43588 Field_ftsf341ae_slot1_Slot_ae_slot1_set, 43589 Field_ftsf342ae_slot1_Slot_ae_slot1_set, 43590 Field_ftsf343ae_slot1_Slot_ae_slot1_set, 43591 Field_ftsf344ae_slot1_Slot_ae_slot1_set, 43592 Field_ftsf345ae_slot1_Slot_ae_slot1_set, 43593 Field_ftsf347ae_slot1_Slot_ae_slot1_set, 43594 Field_ftsf348ae_slot1_Slot_ae_slot1_set, 43595 Field_ftsf349ae_slot1_Slot_ae_slot1_set, 43596 Field_ftsf350ae_slot1_Slot_ae_slot1_set, 43597 Field_ftsf351_Slot_ae_slot1_set, 43598 Field_ftsf352ae_slot1_Slot_ae_slot1_set, 43599 Field_ftsf354ae_slot1_Slot_ae_slot1_set, 43600 Field_ftsf355ae_slot1_Slot_ae_slot1_set, 43601 Field_ftsf356ae_slot1_Slot_ae_slot1_set, 43602 Field_ftsf357ae_slot1_Slot_ae_slot1_set, 43603 Field_ftsf358ae_slot1_Slot_ae_slot1_set, 43604 Field_ftsf359ae_slot1_Slot_ae_slot1_set, 43605 0, 43606 0, 43607 0, 43608 0, 43609 0, 43610 0, 43611 0, 43612 0, 43613 0, 43614 0, 43615 0, 43616 0, 43617 0, 43618 0, 43619 0, 43620 0, 43621 0, 43622 0, 43623 0, 43624 0, 43625 0, 43626 0, 43627 0, 43628 0, 43629 0, 43630 0, 43631 0, 43632 0, 43633 0, 43634 0, 43635 0, 43636 0, 43637 0, 43638 0, 43639 0, 43640 0, 43641 0, 43642 0, 43643 0, 43644 0, 43645 0, 43646 0, 43647 0, 43648 0, 43649 0, 43650 0, 43651 0, 43652 0, 43653 0, 43654 0, 43655 0, 43656 0, 43657 0, 43658 0, 43659 0, 43660 0, 43661 0, 43662 0, 43663 0, 43664 0, 43665 0, 43666 0, 43667 0, 43668 0, 43669 0, 43670 0, 43671 0, 43672 0, 43673 0, 43674 0, 43675 0, 43676 0, 43677 0, 43678 0, 43679 0, 43680 0, 43681 0, 43682 0, 43683 0, 43684 0, 43685 0, 43686 0, 43687 0, 43688 0, 43689 0, 43690 0, 43691 0, 43692 0, 43693 0, 43694 0, 43695 0, 43696 0, 43697 0, 43698 0, 43699 0, 43700 0, 43701 0, 43702 0, 43703 0, 43704 0, 43705 0, 43706 0, 43707 0, 43708 0, 43709 0, 43710 0, 43711 0, 43712 0, 43713 0, 43714 0, 43715 0, 43716 0, 43717 0, 43718 0, 43719 0, 43720 0, 43721 0, 43722 0, 43723 0, 43724 0, 43725 0, 43726 0, 43727 0, 43728 0, 43729 0, 43730 0, 43731 0, 43732 0, 43733 0, 43734 0, 43735 0, 43736 Field_ae_mul32x24fld_Slot_ae_slot1_set, 43737 0, 43738 0, 43739 0, 43740 0, 43741 0, 43742 0, 43743 0, 43744 0, 43745 0, 43746 0, 43747 0, 43748 0, 43749 0, 43750 0, 43751 0, 43752 0, 43753 0, 43754 0, 43755 0, 43756 0, 43757 0, 43758 0, 43759 0, 43760 0, 43761 0, 43762 0, 43763 0, 43764 0, 43765 0, 43766 0, 43767 0, 43768 0, 43769 0, 43770 0, 43771 0, 43772 0, 43773 Field_op0_s3_s3_Slot_ae_slot1_set, 43774 Field_combined2c0b5f72_fld19_Slot_ae_slot1_set, 43775 Field_combined2c0b5f72_fld22_Slot_ae_slot1_set, 43776 Field_combined2c0b5f72_fld24_Slot_ae_slot1_set, 43777 Field_combined2c0b5f72_fld65_Slot_ae_slot1_set, 43778 Field_combined2c0b5f72_fld66_Slot_ae_slot1_set, 43779 Field_combined2c0b5f72_fld68_Slot_ae_slot1_set, 43780 Field_combined2c0b5f72_fld69_Slot_ae_slot1_set, 43781 Field_combined2c0b5f72_fld74_Slot_ae_slot1_set, 43782 Field_combined2c0b5f72_fld79_Slot_ae_slot1_set, 43783 Field_combined2c0b5f72_fld88_Slot_ae_slot1_set, 43784 Field_combined2c0b5f72_fld90_Slot_ae_slot1_set, 43785 Field_combined2c0b5f72_fld91_Slot_ae_slot1_set, 43786 Field_combined2c0b5f72_fld131ae_slot1_Slot_ae_slot1_set, 43787 Field_combined2c0b5f72_fld132ae_slot1_Slot_ae_slot1_set, 43788 Field_combined2c0b5f72_fld147ae_slot1_Slot_ae_slot1_set, 43789 0, 43790 0, 43791 Implicit_Field_set, 43792 Implicit_Field_set, 43793 Implicit_Field_set, 43794 Implicit_Field_set, 43795 Implicit_Field_set, 43796 Implicit_Field_set, 43797 Implicit_Field_set, 43798 Implicit_Field_set, 43799 Implicit_Field_set, 43800 Implicit_Field_set, 43801 Implicit_Field_set, 43802 Implicit_Field_set 43803 }; 43804 43805 static xtensa_get_field_fn 43806 Slot_ae_slot0_get_field_fns[] = { 43807 Field_t_Slot_ae_slot0_get, 43808 0, 43809 Field_bbi_Slot_ae_slot0_get, 43810 Field_imm12_Slot_ae_slot0_get, 43811 Field_imm8_Slot_ae_slot0_get, 43812 Field_s_Slot_ae_slot0_get, 43813 Field_imm12b_Slot_ae_slot0_get, 43814 Field_imm16_Slot_ae_slot0_get, 43815 0, 43816 0, 43817 Field_offset_Slot_ae_slot0_get, 43818 0, 43819 0, 43820 Field_op2_Slot_ae_slot0_get, 43821 Field_r_Slot_ae_slot0_get, 43822 0, 43823 0, 43824 Field_sae_Slot_ae_slot0_get, 43825 Field_sal_Slot_ae_slot0_get, 43826 Field_sargt_Slot_ae_slot0_get, 43827 0, 43828 Field_sas_Slot_ae_slot0_get, 43829 0, 43830 0, 43831 0, 43832 0, 43833 0, 43834 0, 43835 0, 43836 0, 43837 0, 43838 0, 43839 0, 43840 0, 43841 0, 43842 0, 43843 0, 43844 0, 43845 0, 43846 0, 43847 0, 43848 0, 43849 0, 43850 0, 43851 0, 43852 0, 43853 0, 43854 0, 43855 Field_s4_Slot_ae_slot0_get, 43856 0, 43857 0, 43858 Field_s8_Slot_ae_slot0_get, 43859 0, 43860 0, 43861 0, 43862 0, 43863 0, 43864 0, 43865 Field_ae_r32_Slot_ae_slot0_get, 43866 Field_ae_samt_s_t_Slot_ae_slot0_get, 43867 Field_ae_r20_Slot_ae_slot0_get, 43868 Field_ae_r10_Slot_ae_slot0_get, 43869 Field_ae_s20_Slot_ae_slot0_get, 43870 0, 43871 0, 43872 0, 43873 Field_ftsf11_Slot_ae_slot0_get, 43874 0, 43875 0, 43876 0, 43877 0, 43878 0, 43879 0, 43880 0, 43881 0, 43882 0, 43883 0, 43884 0, 43885 0, 43886 0, 43887 0, 43888 0, 43889 0, 43890 0, 43891 0, 43892 0, 43893 0, 43894 0, 43895 0, 43896 0, 43897 0, 43898 0, 43899 0, 43900 0, 43901 0, 43902 0, 43903 0, 43904 0, 43905 0, 43906 0, 43907 0, 43908 0, 43909 0, 43910 0, 43911 0, 43912 0, 43913 0, 43914 0, 43915 0, 43916 0, 43917 0, 43918 0, 43919 0, 43920 0, 43921 0, 43922 0, 43923 0, 43924 0, 43925 0, 43926 0, 43927 0, 43928 0, 43929 0, 43930 0, 43931 0, 43932 0, 43933 0, 43934 0, 43935 0, 43936 0, 43937 0, 43938 0, 43939 0, 43940 0, 43941 0, 43942 0, 43943 0, 43944 0, 43945 0, 43946 0, 43947 0, 43948 0, 43949 0, 43950 0, 43951 0, 43952 0, 43953 0, 43954 0, 43955 0, 43956 0, 43957 0, 43958 0, 43959 0, 43960 0, 43961 0, 43962 0, 43963 0, 43964 0, 43965 0, 43966 0, 43967 0, 43968 0, 43969 0, 43970 0, 43971 0, 43972 0, 43973 0, 43974 0, 43975 0, 43976 0, 43977 0, 43978 0, 43979 0, 43980 0, 43981 0, 43982 0, 43983 0, 43984 0, 43985 0, 43986 0, 43987 0, 43988 0, 43989 0, 43990 0, 43991 0, 43992 0, 43993 0, 43994 0, 43995 0, 43996 0, 43997 0, 43998 0, 43999 0, 44000 0, 44001 0, 44002 0, 44003 0, 44004 0, 44005 0, 44006 0, 44007 0, 44008 0, 44009 0, 44010 0, 44011 0, 44012 0, 44013 0, 44014 0, 44015 0, 44016 0, 44017 0, 44018 0, 44019 0, 44020 0, 44021 0, 44022 0, 44023 0, 44024 0, 44025 0, 44026 0, 44027 0, 44028 0, 44029 0, 44030 0, 44031 0, 44032 0, 44033 0, 44034 0, 44035 0, 44036 0, 44037 0, 44038 0, 44039 0, 44040 0, 44041 0, 44042 0, 44043 0, 44044 0, 44045 0, 44046 0, 44047 0, 44048 0, 44049 0, 44050 0, 44051 0, 44052 0, 44053 0, 44054 0, 44055 0, 44056 0, 44057 0, 44058 0, 44059 0, 44060 0, 44061 0, 44062 0, 44063 0, 44064 0, 44065 0, 44066 0, 44067 0, 44068 0, 44069 0, 44070 0, 44071 0, 44072 0, 44073 0, 44074 0, 44075 0, 44076 0, 44077 Field_op0_s4_Slot_ae_slot0_get, 44078 Field_ftsf211ae_slot0_Slot_ae_slot0_get, 44079 Field_ftsf212ae_slot0_Slot_ae_slot0_get, 44080 Field_ftsf213ae_slot0_Slot_ae_slot0_get, 44081 Field_ftsf214ae_slot0_Slot_ae_slot0_get, 44082 Field_ftsf215ae_slot0_Slot_ae_slot0_get, 44083 Field_ftsf217ae_slot0_Slot_ae_slot0_get, 44084 Field_ftsf218ae_slot0_Slot_ae_slot0_get, 44085 Field_ftsf219ae_slot0_Slot_ae_slot0_get, 44086 Field_ftsf220ae_slot0_Slot_ae_slot0_get, 44087 Field_ftsf221ae_slot0_Slot_ae_slot0_get, 44088 Field_ftsf222ae_slot0_Slot_ae_slot0_get, 44089 Field_ftsf223ae_slot0_Slot_ae_slot0_get, 44090 Field_ftsf224ae_slot0_Slot_ae_slot0_get, 44091 Field_ftsf225ae_slot0_Slot_ae_slot0_get, 44092 Field_ftsf226ae_slot0_Slot_ae_slot0_get, 44093 Field_ftsf227ae_slot0_Slot_ae_slot0_get, 44094 Field_ftsf228ae_slot0_Slot_ae_slot0_get, 44095 Field_ftsf229ae_slot0_Slot_ae_slot0_get, 44096 Field_ftsf230ae_slot0_Slot_ae_slot0_get, 44097 Field_ftsf231ae_slot0_Slot_ae_slot0_get, 44098 Field_ftsf232ae_slot0_Slot_ae_slot0_get, 44099 Field_ftsf233ae_slot0_Slot_ae_slot0_get, 44100 Field_ftsf234ae_slot0_Slot_ae_slot0_get, 44101 Field_ftsf235ae_slot0_Slot_ae_slot0_get, 44102 Field_ftsf236ae_slot0_Slot_ae_slot0_get, 44103 Field_ftsf237ae_slot0_Slot_ae_slot0_get, 44104 Field_ftsf238ae_slot0_Slot_ae_slot0_get, 44105 Field_ftsf239ae_slot0_Slot_ae_slot0_get, 44106 Field_ftsf240ae_slot0_Slot_ae_slot0_get, 44107 Field_ftsf241ae_slot0_Slot_ae_slot0_get, 44108 Field_ftsf242ae_slot0_Slot_ae_slot0_get, 44109 Field_ftsf243ae_slot0_Slot_ae_slot0_get, 44110 Field_ftsf244ae_slot0_Slot_ae_slot0_get, 44111 Field_ftsf245ae_slot0_Slot_ae_slot0_get, 44112 Field_ftsf246ae_slot0_Slot_ae_slot0_get, 44113 Field_ftsf247ae_slot0_Slot_ae_slot0_get, 44114 Field_ftsf248ae_slot0_Slot_ae_slot0_get, 44115 Field_ftsf249ae_slot0_Slot_ae_slot0_get, 44116 Field_ftsf250ae_slot0_Slot_ae_slot0_get, 44117 Field_ftsf251ae_slot0_Slot_ae_slot0_get, 44118 Field_ftsf252ae_slot0_Slot_ae_slot0_get, 44119 Field_ftsf253ae_slot0_Slot_ae_slot0_get, 44120 Field_ftsf254ae_slot0_Slot_ae_slot0_get, 44121 Field_ftsf255ae_slot0_Slot_ae_slot0_get, 44122 Field_ftsf256ae_slot0_Slot_ae_slot0_get, 44123 Field_ftsf257ae_slot0_Slot_ae_slot0_get, 44124 Field_ftsf258ae_slot0_Slot_ae_slot0_get, 44125 Field_ftsf259ae_slot0_Slot_ae_slot0_get, 44126 Field_ftsf260ae_slot0_Slot_ae_slot0_get, 44127 Field_ftsf261ae_slot0_Slot_ae_slot0_get, 44128 Field_ftsf262ae_slot0_Slot_ae_slot0_get, 44129 Field_ftsf263ae_slot0_Slot_ae_slot0_get, 44130 Field_ftsf264ae_slot0_Slot_ae_slot0_get, 44131 Field_ftsf265ae_slot0_Slot_ae_slot0_get, 44132 Field_ftsf266ae_slot0_Slot_ae_slot0_get, 44133 Field_ftsf267ae_slot0_Slot_ae_slot0_get, 44134 Field_ftsf268ae_slot0_Slot_ae_slot0_get, 44135 Field_ftsf269ae_slot0_Slot_ae_slot0_get, 44136 Field_ftsf270ae_slot0_Slot_ae_slot0_get, 44137 Field_ftsf271ae_slot0_Slot_ae_slot0_get, 44138 Field_ftsf272ae_slot0_Slot_ae_slot0_get, 44139 Field_ftsf273ae_slot0_Slot_ae_slot0_get, 44140 Field_ftsf274ae_slot0_Slot_ae_slot0_get, 44141 Field_ftsf275ae_slot0_Slot_ae_slot0_get, 44142 Field_ftsf276ae_slot0_Slot_ae_slot0_get, 44143 Field_ftsf277ae_slot0_Slot_ae_slot0_get, 44144 Field_ftsf278ae_slot0_Slot_ae_slot0_get, 44145 Field_ftsf279ae_slot0_Slot_ae_slot0_get, 44146 Field_ftsf280_Slot_ae_slot0_get, 44147 Field_ftsf281ae_slot0_Slot_ae_slot0_get, 44148 Field_ftsf282ae_slot0_Slot_ae_slot0_get, 44149 Field_ftsf284ae_slot0_Slot_ae_slot0_get, 44150 Field_ftsf285ae_slot0_Slot_ae_slot0_get, 44151 Field_ftsf287ae_slot0_Slot_ae_slot0_get, 44152 Field_ftsf288_Slot_ae_slot0_get, 44153 Field_ftsf289ae_slot0_Slot_ae_slot0_get, 44154 Field_ftsf290ae_slot0_Slot_ae_slot0_get, 44155 Field_ftsf291ae_slot0_Slot_ae_slot0_get, 44156 Field_ftsf292ae_slot0_Slot_ae_slot0_get, 44157 Field_ftsf293ae_slot0_Slot_ae_slot0_get, 44158 Field_ftsf294ae_slot0_Slot_ae_slot0_get, 44159 Field_ftsf295ae_slot0_Slot_ae_slot0_get, 44160 Field_ftsf296ae_slot0_Slot_ae_slot0_get, 44161 Field_ftsf297ae_slot0_Slot_ae_slot0_get, 44162 Field_ftsf298ae_slot0_Slot_ae_slot0_get, 44163 Field_ftsf300ae_slot0_Slot_ae_slot0_get, 44164 Field_ftsf302ae_slot0_Slot_ae_slot0_get, 44165 Field_ftsf304ae_slot0_Slot_ae_slot0_get, 44166 Field_ftsf305ae_slot0_Slot_ae_slot0_get, 44167 Field_ftsf306ae_slot0_Slot_ae_slot0_get, 44168 Field_ftsf307ae_slot0_Slot_ae_slot0_get, 44169 Field_ftsf308ae_slot0_Slot_ae_slot0_get, 44170 Field_ftsf309_Slot_ae_slot0_get, 44171 Field_ftsf310ae_slot0_Slot_ae_slot0_get, 44172 Field_ftsf311ae_slot0_Slot_ae_slot0_get, 44173 Field_ftsf312ae_slot0_Slot_ae_slot0_get, 44174 Field_ftsf313ae_slot0_Slot_ae_slot0_get, 44175 Field_ftsf314ae_slot0_Slot_ae_slot0_get, 44176 Field_ftsf315_Slot_ae_slot0_get, 44177 Field_ftsf316ae_slot0_Slot_ae_slot0_get, 44178 Field_ftsf317ae_slot0_Slot_ae_slot0_get, 44179 Field_ftsf319ae_slot0_Slot_ae_slot0_get, 44180 Field_ftsf320ae_slot0_Slot_ae_slot0_get, 44181 Field_ftsf322ae_slot0_Slot_ae_slot0_get, 44182 Field_ftsf323ae_slot0_Slot_ae_slot0_get, 44183 Field_ftsf324ae_slot0_Slot_ae_slot0_get, 44184 Field_ftsf325ae_slot0_Slot_ae_slot0_get, 44185 Field_ftsf326ae_slot0_Slot_ae_slot0_get, 44186 Field_ftsf327ae_slot0_Slot_ae_slot0_get, 44187 Field_ftsf328ae_slot0_Slot_ae_slot0_get, 44188 Field_ftsf329ae_slot0_Slot_ae_slot0_get, 44189 Field_ftsf360ae_slot0_Slot_ae_slot0_get, 44190 Field_ftsf361ae_slot0_Slot_ae_slot0_get, 44191 Field_ftsf362_Slot_ae_slot0_get, 44192 Field_ftsf363ae_slot0_Slot_ae_slot0_get, 44193 Field_ftsf364ae_slot0_Slot_ae_slot0_get, 44194 Field_ftsf366ae_slot0_Slot_ae_slot0_get, 44195 Field_ftsf368ae_slot0_Slot_ae_slot0_get, 44196 Field_ftsf370ae_slot0_Slot_ae_slot0_get, 44197 Field_ftsf373ae_slot0_Slot_ae_slot0_get, 44198 Field_ftsf376ae_slot0_Slot_ae_slot0_get, 44199 Field_ftsf378ae_slot0_Slot_ae_slot0_get, 44200 Field_ftsf379ae_slot0_Slot_ae_slot0_get, 44201 Field_ftsf382ae_slot0_Slot_ae_slot0_get, 44202 Field_ftsf383ae_slot0_Slot_ae_slot0_get, 44203 Field_ftsf384ae_slot0_Slot_ae_slot0_get, 44204 Field_ftsf386ae_slot0_Slot_ae_slot0_get, 44205 Field_ftsf387ae_slot0_Slot_ae_slot0_get, 44206 Field_ftsf388ae_slot0_Slot_ae_slot0_get, 44207 Field_ftsf389ae_slot0_Slot_ae_slot0_get, 44208 0, 44209 Field_op0_s4_s4_Slot_ae_slot0_get, 44210 Field_combined2c0b5f72_fld28_Slot_ae_slot0_get, 44211 Field_combined2c0b5f72_fld37_Slot_ae_slot0_get, 44212 Field_combined2c0b5f72_fld39_Slot_ae_slot0_get, 44213 Field_combined2c0b5f72_fld40_Slot_ae_slot0_get, 44214 Field_combined2c0b5f72_fld46_Slot_ae_slot0_get, 44215 Field_combined2c0b5f72_fld47_Slot_ae_slot0_get, 44216 Field_combined2c0b5f72_fld49_Slot_ae_slot0_get, 44217 Field_combined2c0b5f72_fld50_Slot_ae_slot0_get, 44218 Field_combined2c0b5f72_fld52_Slot_ae_slot0_get, 44219 Field_combined2c0b5f72_fld121_Slot_ae_slot0_get, 44220 Field_combined2c0b5f72_fld123_Slot_ae_slot0_get, 44221 Field_combined2c0b5f72_fld127_Slot_ae_slot0_get, 44222 Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_get, 44223 Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_get, 44224 Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_get, 44225 Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_get, 44226 Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_get, 44227 Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_get, 44228 Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_get, 44229 Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_get, 44230 Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_get, 44231 Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_get, 44232 Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_get, 44233 Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_get, 44234 Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_get, 44235 Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_get, 44236 Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_get, 44237 Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_get, 44238 Field_op0_s4_s4_s4_Slot_ae_slot0_get, 44239 Field_combined1e9fefee_fld96_Slot_ae_slot0_get, 44240 Field_combined1e9fefee_fld98_Slot_ae_slot0_get, 44241 Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_get, 44242 Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_get, 44243 Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_get, 44244 Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_get, 44245 0, 44246 0, 44247 0, 44248 0, 44249 0, 44250 0, 44251 0, 44252 0, 44253 0, 44254 0, 44255 0, 44256 0, 44257 0, 44258 0, 44259 0, 44260 0, 44261 Field_bitindex_Slot_ae_slot0_get, 44262 Field_s3to1_Slot_ae_slot0_get, 44263 Implicit_Field_ar0_get, 44264 Implicit_Field_ar4_get, 44265 Implicit_Field_ar8_get, 44266 Implicit_Field_ar12_get, 44267 Implicit_Field_mr0_get, 44268 Implicit_Field_mr1_get, 44269 Implicit_Field_mr2_get, 44270 Implicit_Field_mr3_get, 44271 Implicit_Field_bt16_get, 44272 Implicit_Field_bs16_get, 44273 Implicit_Field_br16_get, 44274 Implicit_Field_brall_get 44275 }; 44276 44277 static xtensa_set_field_fn 44278 Slot_ae_slot0_set_field_fns[] = { 44279 Field_t_Slot_ae_slot0_set, 44280 0, 44281 Field_bbi_Slot_ae_slot0_set, 44282 Field_imm12_Slot_ae_slot0_set, 44283 Field_imm8_Slot_ae_slot0_set, 44284 Field_s_Slot_ae_slot0_set, 44285 Field_imm12b_Slot_ae_slot0_set, 44286 Field_imm16_Slot_ae_slot0_set, 44287 0, 44288 0, 44289 Field_offset_Slot_ae_slot0_set, 44290 0, 44291 0, 44292 Field_op2_Slot_ae_slot0_set, 44293 Field_r_Slot_ae_slot0_set, 44294 0, 44295 0, 44296 Field_sae_Slot_ae_slot0_set, 44297 Field_sal_Slot_ae_slot0_set, 44298 Field_sargt_Slot_ae_slot0_set, 44299 0, 44300 Field_sas_Slot_ae_slot0_set, 44301 0, 44302 0, 44303 0, 44304 0, 44305 0, 44306 0, 44307 0, 44308 0, 44309 0, 44310 0, 44311 0, 44312 0, 44313 0, 44314 0, 44315 0, 44316 0, 44317 0, 44318 0, 44319 0, 44320 0, 44321 0, 44322 0, 44323 0, 44324 0, 44325 0, 44326 0, 44327 Field_s4_Slot_ae_slot0_set, 44328 0, 44329 0, 44330 Field_s8_Slot_ae_slot0_set, 44331 0, 44332 0, 44333 0, 44334 0, 44335 0, 44336 0, 44337 Field_ae_r32_Slot_ae_slot0_set, 44338 Field_ae_samt_s_t_Slot_ae_slot0_set, 44339 Field_ae_r20_Slot_ae_slot0_set, 44340 Field_ae_r10_Slot_ae_slot0_set, 44341 Field_ae_s20_Slot_ae_slot0_set, 44342 0, 44343 0, 44344 0, 44345 Field_ftsf11_Slot_ae_slot0_set, 44346 0, 44347 0, 44348 0, 44349 0, 44350 0, 44351 0, 44352 0, 44353 0, 44354 0, 44355 0, 44356 0, 44357 0, 44358 0, 44359 0, 44360 0, 44361 0, 44362 0, 44363 0, 44364 0, 44365 0, 44366 0, 44367 0, 44368 0, 44369 0, 44370 0, 44371 0, 44372 0, 44373 0, 44374 0, 44375 0, 44376 0, 44377 0, 44378 0, 44379 0, 44380 0, 44381 0, 44382 0, 44383 0, 44384 0, 44385 0, 44386 0, 44387 0, 44388 0, 44389 0, 44390 0, 44391 0, 44392 0, 44393 0, 44394 0, 44395 0, 44396 0, 44397 0, 44398 0, 44399 0, 44400 0, 44401 0, 44402 0, 44403 0, 44404 0, 44405 0, 44406 0, 44407 0, 44408 0, 44409 0, 44410 0, 44411 0, 44412 0, 44413 0, 44414 0, 44415 0, 44416 0, 44417 0, 44418 0, 44419 0, 44420 0, 44421 0, 44422 0, 44423 0, 44424 0, 44425 0, 44426 0, 44427 0, 44428 0, 44429 0, 44430 0, 44431 0, 44432 0, 44433 0, 44434 0, 44435 0, 44436 0, 44437 0, 44438 0, 44439 0, 44440 0, 44441 0, 44442 0, 44443 0, 44444 0, 44445 0, 44446 0, 44447 0, 44448 0, 44449 0, 44450 0, 44451 0, 44452 0, 44453 0, 44454 0, 44455 0, 44456 0, 44457 0, 44458 0, 44459 0, 44460 0, 44461 0, 44462 0, 44463 0, 44464 0, 44465 0, 44466 0, 44467 0, 44468 0, 44469 0, 44470 0, 44471 0, 44472 0, 44473 0, 44474 0, 44475 0, 44476 0, 44477 0, 44478 0, 44479 0, 44480 0, 44481 0, 44482 0, 44483 0, 44484 0, 44485 0, 44486 0, 44487 0, 44488 0, 44489 0, 44490 0, 44491 0, 44492 0, 44493 0, 44494 0, 44495 0, 44496 0, 44497 0, 44498 0, 44499 0, 44500 0, 44501 0, 44502 0, 44503 0, 44504 0, 44505 0, 44506 0, 44507 0, 44508 0, 44509 0, 44510 0, 44511 0, 44512 0, 44513 0, 44514 0, 44515 0, 44516 0, 44517 0, 44518 0, 44519 0, 44520 0, 44521 0, 44522 0, 44523 0, 44524 0, 44525 0, 44526 0, 44527 0, 44528 0, 44529 0, 44530 0, 44531 0, 44532 0, 44533 0, 44534 0, 44535 0, 44536 0, 44537 0, 44538 0, 44539 0, 44540 0, 44541 0, 44542 0, 44543 0, 44544 0, 44545 0, 44546 0, 44547 0, 44548 0, 44549 Field_op0_s4_Slot_ae_slot0_set, 44550 Field_ftsf211ae_slot0_Slot_ae_slot0_set, 44551 Field_ftsf212ae_slot0_Slot_ae_slot0_set, 44552 Field_ftsf213ae_slot0_Slot_ae_slot0_set, 44553 Field_ftsf214ae_slot0_Slot_ae_slot0_set, 44554 Field_ftsf215ae_slot0_Slot_ae_slot0_set, 44555 Field_ftsf217ae_slot0_Slot_ae_slot0_set, 44556 Field_ftsf218ae_slot0_Slot_ae_slot0_set, 44557 Field_ftsf219ae_slot0_Slot_ae_slot0_set, 44558 Field_ftsf220ae_slot0_Slot_ae_slot0_set, 44559 Field_ftsf221ae_slot0_Slot_ae_slot0_set, 44560 Field_ftsf222ae_slot0_Slot_ae_slot0_set, 44561 Field_ftsf223ae_slot0_Slot_ae_slot0_set, 44562 Field_ftsf224ae_slot0_Slot_ae_slot0_set, 44563 Field_ftsf225ae_slot0_Slot_ae_slot0_set, 44564 Field_ftsf226ae_slot0_Slot_ae_slot0_set, 44565 Field_ftsf227ae_slot0_Slot_ae_slot0_set, 44566 Field_ftsf228ae_slot0_Slot_ae_slot0_set, 44567 Field_ftsf229ae_slot0_Slot_ae_slot0_set, 44568 Field_ftsf230ae_slot0_Slot_ae_slot0_set, 44569 Field_ftsf231ae_slot0_Slot_ae_slot0_set, 44570 Field_ftsf232ae_slot0_Slot_ae_slot0_set, 44571 Field_ftsf233ae_slot0_Slot_ae_slot0_set, 44572 Field_ftsf234ae_slot0_Slot_ae_slot0_set, 44573 Field_ftsf235ae_slot0_Slot_ae_slot0_set, 44574 Field_ftsf236ae_slot0_Slot_ae_slot0_set, 44575 Field_ftsf237ae_slot0_Slot_ae_slot0_set, 44576 Field_ftsf238ae_slot0_Slot_ae_slot0_set, 44577 Field_ftsf239ae_slot0_Slot_ae_slot0_set, 44578 Field_ftsf240ae_slot0_Slot_ae_slot0_set, 44579 Field_ftsf241ae_slot0_Slot_ae_slot0_set, 44580 Field_ftsf242ae_slot0_Slot_ae_slot0_set, 44581 Field_ftsf243ae_slot0_Slot_ae_slot0_set, 44582 Field_ftsf244ae_slot0_Slot_ae_slot0_set, 44583 Field_ftsf245ae_slot0_Slot_ae_slot0_set, 44584 Field_ftsf246ae_slot0_Slot_ae_slot0_set, 44585 Field_ftsf247ae_slot0_Slot_ae_slot0_set, 44586 Field_ftsf248ae_slot0_Slot_ae_slot0_set, 44587 Field_ftsf249ae_slot0_Slot_ae_slot0_set, 44588 Field_ftsf250ae_slot0_Slot_ae_slot0_set, 44589 Field_ftsf251ae_slot0_Slot_ae_slot0_set, 44590 Field_ftsf252ae_slot0_Slot_ae_slot0_set, 44591 Field_ftsf253ae_slot0_Slot_ae_slot0_set, 44592 Field_ftsf254ae_slot0_Slot_ae_slot0_set, 44593 Field_ftsf255ae_slot0_Slot_ae_slot0_set, 44594 Field_ftsf256ae_slot0_Slot_ae_slot0_set, 44595 Field_ftsf257ae_slot0_Slot_ae_slot0_set, 44596 Field_ftsf258ae_slot0_Slot_ae_slot0_set, 44597 Field_ftsf259ae_slot0_Slot_ae_slot0_set, 44598 Field_ftsf260ae_slot0_Slot_ae_slot0_set, 44599 Field_ftsf261ae_slot0_Slot_ae_slot0_set, 44600 Field_ftsf262ae_slot0_Slot_ae_slot0_set, 44601 Field_ftsf263ae_slot0_Slot_ae_slot0_set, 44602 Field_ftsf264ae_slot0_Slot_ae_slot0_set, 44603 Field_ftsf265ae_slot0_Slot_ae_slot0_set, 44604 Field_ftsf266ae_slot0_Slot_ae_slot0_set, 44605 Field_ftsf267ae_slot0_Slot_ae_slot0_set, 44606 Field_ftsf268ae_slot0_Slot_ae_slot0_set, 44607 Field_ftsf269ae_slot0_Slot_ae_slot0_set, 44608 Field_ftsf270ae_slot0_Slot_ae_slot0_set, 44609 Field_ftsf271ae_slot0_Slot_ae_slot0_set, 44610 Field_ftsf272ae_slot0_Slot_ae_slot0_set, 44611 Field_ftsf273ae_slot0_Slot_ae_slot0_set, 44612 Field_ftsf274ae_slot0_Slot_ae_slot0_set, 44613 Field_ftsf275ae_slot0_Slot_ae_slot0_set, 44614 Field_ftsf276ae_slot0_Slot_ae_slot0_set, 44615 Field_ftsf277ae_slot0_Slot_ae_slot0_set, 44616 Field_ftsf278ae_slot0_Slot_ae_slot0_set, 44617 Field_ftsf279ae_slot0_Slot_ae_slot0_set, 44618 Field_ftsf280_Slot_ae_slot0_set, 44619 Field_ftsf281ae_slot0_Slot_ae_slot0_set, 44620 Field_ftsf282ae_slot0_Slot_ae_slot0_set, 44621 Field_ftsf284ae_slot0_Slot_ae_slot0_set, 44622 Field_ftsf285ae_slot0_Slot_ae_slot0_set, 44623 Field_ftsf287ae_slot0_Slot_ae_slot0_set, 44624 Field_ftsf288_Slot_ae_slot0_set, 44625 Field_ftsf289ae_slot0_Slot_ae_slot0_set, 44626 Field_ftsf290ae_slot0_Slot_ae_slot0_set, 44627 Field_ftsf291ae_slot0_Slot_ae_slot0_set, 44628 Field_ftsf292ae_slot0_Slot_ae_slot0_set, 44629 Field_ftsf293ae_slot0_Slot_ae_slot0_set, 44630 Field_ftsf294ae_slot0_Slot_ae_slot0_set, 44631 Field_ftsf295ae_slot0_Slot_ae_slot0_set, 44632 Field_ftsf296ae_slot0_Slot_ae_slot0_set, 44633 Field_ftsf297ae_slot0_Slot_ae_slot0_set, 44634 Field_ftsf298ae_slot0_Slot_ae_slot0_set, 44635 Field_ftsf300ae_slot0_Slot_ae_slot0_set, 44636 Field_ftsf302ae_slot0_Slot_ae_slot0_set, 44637 Field_ftsf304ae_slot0_Slot_ae_slot0_set, 44638 Field_ftsf305ae_slot0_Slot_ae_slot0_set, 44639 Field_ftsf306ae_slot0_Slot_ae_slot0_set, 44640 Field_ftsf307ae_slot0_Slot_ae_slot0_set, 44641 Field_ftsf308ae_slot0_Slot_ae_slot0_set, 44642 Field_ftsf309_Slot_ae_slot0_set, 44643 Field_ftsf310ae_slot0_Slot_ae_slot0_set, 44644 Field_ftsf311ae_slot0_Slot_ae_slot0_set, 44645 Field_ftsf312ae_slot0_Slot_ae_slot0_set, 44646 Field_ftsf313ae_slot0_Slot_ae_slot0_set, 44647 Field_ftsf314ae_slot0_Slot_ae_slot0_set, 44648 Field_ftsf315_Slot_ae_slot0_set, 44649 Field_ftsf316ae_slot0_Slot_ae_slot0_set, 44650 Field_ftsf317ae_slot0_Slot_ae_slot0_set, 44651 Field_ftsf319ae_slot0_Slot_ae_slot0_set, 44652 Field_ftsf320ae_slot0_Slot_ae_slot0_set, 44653 Field_ftsf322ae_slot0_Slot_ae_slot0_set, 44654 Field_ftsf323ae_slot0_Slot_ae_slot0_set, 44655 Field_ftsf324ae_slot0_Slot_ae_slot0_set, 44656 Field_ftsf325ae_slot0_Slot_ae_slot0_set, 44657 Field_ftsf326ae_slot0_Slot_ae_slot0_set, 44658 Field_ftsf327ae_slot0_Slot_ae_slot0_set, 44659 Field_ftsf328ae_slot0_Slot_ae_slot0_set, 44660 Field_ftsf329ae_slot0_Slot_ae_slot0_set, 44661 Field_ftsf360ae_slot0_Slot_ae_slot0_set, 44662 Field_ftsf361ae_slot0_Slot_ae_slot0_set, 44663 Field_ftsf362_Slot_ae_slot0_set, 44664 Field_ftsf363ae_slot0_Slot_ae_slot0_set, 44665 Field_ftsf364ae_slot0_Slot_ae_slot0_set, 44666 Field_ftsf366ae_slot0_Slot_ae_slot0_set, 44667 Field_ftsf368ae_slot0_Slot_ae_slot0_set, 44668 Field_ftsf370ae_slot0_Slot_ae_slot0_set, 44669 Field_ftsf373ae_slot0_Slot_ae_slot0_set, 44670 Field_ftsf376ae_slot0_Slot_ae_slot0_set, 44671 Field_ftsf378ae_slot0_Slot_ae_slot0_set, 44672 Field_ftsf379ae_slot0_Slot_ae_slot0_set, 44673 Field_ftsf382ae_slot0_Slot_ae_slot0_set, 44674 Field_ftsf383ae_slot0_Slot_ae_slot0_set, 44675 Field_ftsf384ae_slot0_Slot_ae_slot0_set, 44676 Field_ftsf386ae_slot0_Slot_ae_slot0_set, 44677 Field_ftsf387ae_slot0_Slot_ae_slot0_set, 44678 Field_ftsf388ae_slot0_Slot_ae_slot0_set, 44679 Field_ftsf389ae_slot0_Slot_ae_slot0_set, 44680 0, 44681 Field_op0_s4_s4_Slot_ae_slot0_set, 44682 Field_combined2c0b5f72_fld28_Slot_ae_slot0_set, 44683 Field_combined2c0b5f72_fld37_Slot_ae_slot0_set, 44684 Field_combined2c0b5f72_fld39_Slot_ae_slot0_set, 44685 Field_combined2c0b5f72_fld40_Slot_ae_slot0_set, 44686 Field_combined2c0b5f72_fld46_Slot_ae_slot0_set, 44687 Field_combined2c0b5f72_fld47_Slot_ae_slot0_set, 44688 Field_combined2c0b5f72_fld49_Slot_ae_slot0_set, 44689 Field_combined2c0b5f72_fld50_Slot_ae_slot0_set, 44690 Field_combined2c0b5f72_fld52_Slot_ae_slot0_set, 44691 Field_combined2c0b5f72_fld121_Slot_ae_slot0_set, 44692 Field_combined2c0b5f72_fld123_Slot_ae_slot0_set, 44693 Field_combined2c0b5f72_fld127_Slot_ae_slot0_set, 44694 Field_combined2c0b5f72_fld133ae_slot0_Slot_ae_slot0_set, 44695 Field_combined2c0b5f72_fld134ae_slot0_Slot_ae_slot0_set, 44696 Field_combined2c0b5f72_fld135ae_slot0_Slot_ae_slot0_set, 44697 Field_combined2c0b5f72_fld136ae_slot0_Slot_ae_slot0_set, 44698 Field_combined2c0b5f72_fld137ae_slot0_Slot_ae_slot0_set, 44699 Field_combined2c0b5f72_fld138ae_slot0_Slot_ae_slot0_set, 44700 Field_combined2c0b5f72_fld139ae_slot0_Slot_ae_slot0_set, 44701 Field_combined2c0b5f72_fld140ae_slot0_Slot_ae_slot0_set, 44702 Field_combined2c0b5f72_fld141ae_slot0_Slot_ae_slot0_set, 44703 Field_combined2c0b5f72_fld142ae_slot0_Slot_ae_slot0_set, 44704 Field_combined2c0b5f72_fld143ae_slot0_Slot_ae_slot0_set, 44705 Field_combined2c0b5f72_fld144ae_slot0_Slot_ae_slot0_set, 44706 Field_combined2c0b5f72_fld145ae_slot0_Slot_ae_slot0_set, 44707 Field_combined2c0b5f72_fld146ae_slot0_Slot_ae_slot0_set, 44708 Field_combined2c0b5f72_fld148ae_slot0_Slot_ae_slot0_set, 44709 Field_combined2c0b5f72_fld149ae_slot0_Slot_ae_slot0_set, 44710 Field_op0_s4_s4_s4_Slot_ae_slot0_set, 44711 Field_combined1e9fefee_fld96_Slot_ae_slot0_set, 44712 Field_combined1e9fefee_fld98_Slot_ae_slot0_set, 44713 Field_combined1e9fefee_fld106ae_slot0_Slot_ae_slot0_set, 44714 Field_combined1e9fefee_fld107ae_slot0_Slot_ae_slot0_set, 44715 Field_combined1e9fefee_fld108ae_slot0_Slot_ae_slot0_set, 44716 Field_combined1e9fefee_fld109ae_slot0_Slot_ae_slot0_set, 44717 0, 44718 0, 44719 0, 44720 0, 44721 0, 44722 0, 44723 0, 44724 0, 44725 0, 44726 0, 44727 0, 44728 0, 44729 0, 44730 0, 44731 0, 44732 0, 44733 Field_bitindex_Slot_ae_slot0_set, 44734 Field_s3to1_Slot_ae_slot0_set, 44735 Implicit_Field_set, 44736 Implicit_Field_set, 44737 Implicit_Field_set, 44738 Implicit_Field_set, 44739 Implicit_Field_set, 44740 Implicit_Field_set, 44741 Implicit_Field_set, 44742 Implicit_Field_set, 44743 Implicit_Field_set, 44744 Implicit_Field_set, 44745 Implicit_Field_set, 44746 Implicit_Field_set 44747 }; 44748 44749 static xtensa_slot_internal slots[] = { 44750 { "Inst", "x24", 0, 44751 Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set, 44752 Slot_inst_get_field_fns, Slot_inst_set_field_fns, 44753 Slot_inst_decode, "nop" }, 44754 { "Inst16a", "x16a", 0, 44755 Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set, 44756 Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns, 44757 Slot_inst16a_decode, "" }, 44758 { "Inst16b", "x16b", 0, 44759 Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set, 44760 Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns, 44761 Slot_inst16b_decode, "nop.n" }, 44762 { "ae_slot1", "ae_format", 1, 44763 Slot_ae_format_Format_ae_slot1_10_get, Slot_ae_format_Format_ae_slot1_10_set, 44764 Slot_ae_slot1_get_field_fns, Slot_ae_slot1_set_field_fns, 44765 Slot_ae_slot1_decode, "nop" }, 44766 { "ae_slot0", "ae_format", 0, 44767 Slot_ae_format_Format_ae_slot0_33_get, Slot_ae_format_Format_ae_slot0_33_set, 44768 Slot_ae_slot0_get_field_fns, Slot_ae_slot0_set_field_fns, 44769 Slot_ae_slot0_decode, "nop" } 44770 }; 44771 44772 44773 /* Instruction formats. */ 44774 44775 static void 44776 Format_x24_encode (xtensa_insnbuf insn) 44777 { 44778 insn[0] = 0; 44779 insn[1] = 0; 44780 } 44781 44782 static void 44783 Format_x16a_encode (xtensa_insnbuf insn) 44784 { 44785 insn[0] = 0; 44786 insn[1] = 0x80000000; 44787 } 44788 44789 static void 44790 Format_x16b_encode (xtensa_insnbuf insn) 44791 { 44792 insn[0] = 0; 44793 insn[1] = 0xc0000000; 44794 } 44795 44796 static void 44797 Format_ae_format_encode (xtensa_insnbuf insn) 44798 { 44799 insn[0] = 0; 44800 insn[1] = 0xf0000000; 44801 } 44802 44803 static int Format_x24_slots[] = { 0 }; 44804 44805 static int Format_x16a_slots[] = { 1 }; 44806 44807 static int Format_x16b_slots[] = { 2 }; 44808 44809 static int Format_ae_format_slots[] = { 3, 4 }; 44810 44811 static xtensa_format_internal formats[] = { 44812 { "x24", 3, Format_x24_encode, 1, Format_x24_slots }, 44813 { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots }, 44814 { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }, 44815 { "ae_format", 8, Format_ae_format_encode, 2, Format_ae_format_slots } 44816 }; 44817 44818 44819 static int 44820 format_decoder (const xtensa_insnbuf insn) 44821 { 44822 if ((insn[0] & 0) == 0 && (insn[1] & 0x80000000) == 0) 44823 return 0; /* x24 */ 44824 if ((insn[0] & 0) == 0 && (insn[1] & 0xc0000000) == 0x80000000) 44825 return 1; /* x16a */ 44826 if ((insn[0] & 0) == 0 && (insn[1] & 0xe0000000) == 0xc0000000) 44827 return 2; /* x16b */ 44828 if ((insn[0] & 0x3ff) == 0 && (insn[1] & 0xf0000000) == 0xf0000000) 44829 return 3; /* ae_format */ 44830 return -1; 44831 } 44832 44833 static int length_table[256] = { 44834 3, 44835 3, 44836 3, 44837 3, 44838 3, 44839 3, 44840 3, 44841 3, 44842 3, 44843 3, 44844 3, 44845 3, 44846 3, 44847 3, 44848 3, 44849 3, 44850 3, 44851 3, 44852 3, 44853 3, 44854 3, 44855 3, 44856 3, 44857 3, 44858 3, 44859 3, 44860 3, 44861 3, 44862 3, 44863 3, 44864 3, 44865 3, 44866 3, 44867 3, 44868 3, 44869 3, 44870 3, 44871 3, 44872 3, 44873 3, 44874 3, 44875 3, 44876 3, 44877 3, 44878 3, 44879 3, 44880 3, 44881 3, 44882 3, 44883 3, 44884 3, 44885 3, 44886 3, 44887 3, 44888 3, 44889 3, 44890 3, 44891 3, 44892 3, 44893 3, 44894 3, 44895 3, 44896 3, 44897 3, 44898 3, 44899 3, 44900 3, 44901 3, 44902 3, 44903 3, 44904 3, 44905 3, 44906 3, 44907 3, 44908 3, 44909 3, 44910 3, 44911 3, 44912 3, 44913 3, 44914 3, 44915 3, 44916 3, 44917 3, 44918 3, 44919 3, 44920 3, 44921 3, 44922 3, 44923 3, 44924 3, 44925 3, 44926 3, 44927 3, 44928 3, 44929 3, 44930 3, 44931 3, 44932 3, 44933 3, 44934 3, 44935 3, 44936 3, 44937 3, 44938 3, 44939 3, 44940 3, 44941 3, 44942 3, 44943 3, 44944 3, 44945 3, 44946 3, 44947 3, 44948 3, 44949 3, 44950 3, 44951 3, 44952 3, 44953 3, 44954 3, 44955 3, 44956 3, 44957 3, 44958 3, 44959 3, 44960 3, 44961 3, 44962 2, 44963 2, 44964 2, 44965 2, 44966 2, 44967 2, 44968 2, 44969 2, 44970 2, 44971 2, 44972 2, 44973 2, 44974 2, 44975 2, 44976 2, 44977 2, 44978 2, 44979 2, 44980 2, 44981 2, 44982 2, 44983 2, 44984 2, 44985 2, 44986 2, 44987 2, 44988 2, 44989 2, 44990 2, 44991 2, 44992 2, 44993 2, 44994 2, 44995 2, 44996 2, 44997 2, 44998 2, 44999 2, 45000 2, 45001 2, 45002 2, 45003 2, 45004 2, 45005 2, 45006 2, 45007 2, 45008 2, 45009 2, 45010 2, 45011 2, 45012 2, 45013 2, 45014 2, 45015 2, 45016 2, 45017 2, 45018 2, 45019 2, 45020 2, 45021 2, 45022 2, 45023 2, 45024 2, 45025 2, 45026 2, 45027 2, 45028 2, 45029 2, 45030 2, 45031 2, 45032 2, 45033 2, 45034 2, 45035 2, 45036 2, 45037 2, 45038 2, 45039 2, 45040 2, 45041 2, 45042 2, 45043 2, 45044 2, 45045 2, 45046 2, 45047 2, 45048 2, 45049 2, 45050 2, 45051 2, 45052 2, 45053 2, 45054 2, 45055 2, 45056 2, 45057 2, 45058 -1, 45059 -1, 45060 -1, 45061 -1, 45062 -1, 45063 -1, 45064 -1, 45065 -1, 45066 -1, 45067 -1, 45068 -1, 45069 -1, 45070 -1, 45071 -1, 45072 -1, 45073 -1, 45074 8, 45075 8, 45076 8, 45077 8, 45078 8, 45079 8, 45080 8, 45081 8, 45082 8, 45083 8, 45084 8, 45085 8, 45086 8, 45087 8, 45088 8, 45089 8 45090 }; 45091 45092 static int 45093 length_decoder (const unsigned char *insn) 45094 { 45095 int l = insn[0]; 45096 return length_table[l]; 45097 } 45098 45099 45100 /* Top-level ISA structure. */ 45101 45102 xtensa_isa_internal xtensa_modules = { 45103 1 /* big-endian */, 45104 8 /* insn_size */, 0, 45105 4, formats, format_decoder, length_decoder, 45106 5, slots, 45107 468 /* num_fields */, 45108 536, operands, 45109 746, iclasses, 45110 881, opcodes, 0, 45111 9, regfiles, 45112 NUM_STATES, states, 0, 45113 NUM_SYSREGS, sysregs, 0, 45114 { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 }, 45115 6, interfaces, 0, 45116 4, funcUnits, 0 45117 };