xtensa-modules.c.inc - qemu - FORK: QEMU emulator

xtensa-modules.c.inc (275958B)
      1 /* Xtensa configuration-specific ISA information.
      2 
      3    Copyright (c) 2003-2016 Tensilica Inc.
      4 
      5    Permission is hereby granted, free of charge, to any person obtaining
      6    a copy of this software and associated documentation files (the
      7    "Software"), to deal in the Software without restriction, including
      8    without limitation the rights to use, copy, modify, merge, publish,
      9    distribute, sublicense, and/or sell copies of the Software, and to
     10    permit persons to whom the Software is furnished to do so, subject to
     11    the following conditions:
     12 
     13    The above copyright notice and this permission notice shall be included
     14    in all copies or substantial portions of the Software.
     15 
     16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     17    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     18    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
     19    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
     20    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     21    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     22    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
     23 
     24 #include "qemu/osdep.h"
     25 #include "xtensa-isa.h"
     26 #include "xtensa-isa-internal.h"
     27 
     28 
     29 /* Sysregs.  */
     30 
     31 static xtensa_sysreg_internal sysregs[] = {
     32   { "MMID", 89, 0 },
     33   { "DDR", 104, 0 },
     34   { "CONFIGID0", 176, 0 },
     35   { "CONFIGID1", 208, 0 },
     36   { "INTERRUPT", 226, 0 },
     37   { "INTCLEAR", 227, 0 },
     38   { "CCOUNT", 234, 0 },
     39   { "PRID", 235, 0 },
     40   { "ICOUNT", 236, 0 },
     41   { "CCOMPARE0", 240, 0 },
     42   { "CCOMPARE1", 241, 0 },
     43   { "CCOMPARE2", 242, 0 },
     44   { "VECBASE", 231, 0 },
     45   { "EPC1", 177, 0 },
     46   { "EPC2", 178, 0 },
     47   { "EPC3", 179, 0 },
     48   { "EPC4", 180, 0 },
     49   { "EPC5", 181, 0 },
     50   { "EPC6", 182, 0 },
     51   { "EPC7", 183, 0 },
     52   { "EXCSAVE1", 209, 0 },
     53   { "EXCSAVE2", 210, 0 },
     54   { "EXCSAVE3", 211, 0 },
     55   { "EXCSAVE4", 212, 0 },
     56   { "EXCSAVE5", 213, 0 },
     57   { "EXCSAVE6", 214, 0 },
     58   { "EXCSAVE7", 215, 0 },
     59   { "EPS2", 194, 0 },
     60   { "EPS3", 195, 0 },
     61   { "EPS4", 196, 0 },
     62   { "EPS5", 197, 0 },
     63   { "EPS6", 198, 0 },
     64   { "EPS7", 199, 0 },
     65   { "EXCCAUSE", 232, 0 },
     66   { "DEPC", 192, 0 },
     67   { "EXCVADDR", 238, 0 },
     68   { "WINDOWBASE", 72, 0 },
     69   { "WINDOWSTART", 73, 0 },
     70   { "SAR", 3, 0 },
     71   { "PS", 230, 0 },
     72   { "MISC0", 244, 0 },
     73   { "MISC1", 245, 0 },
     74   { "INTENABLE", 228, 0 },
     75   { "DBREAKA0", 144, 0 },
     76   { "DBREAKC0", 160, 0 },
     77   { "DBREAKA1", 145, 0 },
     78   { "DBREAKC1", 161, 0 },
     79   { "IBREAKA0", 128, 0 },
     80   { "IBREAKA1", 129, 0 },
     81   { "IBREAKENABLE", 96, 0 },
     82   { "ICOUNTLEVEL", 237, 0 },
     83   { "DEBUGCAUSE", 233, 0 },
     84   { "SCOMPARE1", 12, 0 },
     85   { "ATOMCTL", 99, 0 },
     86   { "EXPSTATE", 230, 1 }
     87 };
     88 
     89 #define NUM_SYSREGS 55
     90 #define MAX_SPECIAL_REG 245
     91 #define MAX_USER_REG 230
     92 
     93 
     94 /* Processor states.  */
     95 
     96 static xtensa_state_internal states[] = {
     97   { "PC", 32, 0 },
     98   { "ICOUNT", 32, 0 },
     99   { "DDR", 32, 0 },
    100   { "INTERRUPT", 22, 0 },
    101   { "CCOUNT", 32, 0 },
    102   { "XTSYNC", 1, 0 },
    103   { "VECBASE", 22, 0 },
    104   { "EPC1", 32, 0 },
    105   { "EPC2", 32, 0 },
    106   { "EPC3", 32, 0 },
    107   { "EPC4", 32, 0 },
    108   { "EPC5", 32, 0 },
    109   { "EPC6", 32, 0 },
    110   { "EPC7", 32, 0 },
    111   { "EXCSAVE1", 32, 0 },
    112   { "EXCSAVE2", 32, 0 },
    113   { "EXCSAVE3", 32, 0 },
    114   { "EXCSAVE4", 32, 0 },
    115   { "EXCSAVE5", 32, 0 },
    116   { "EXCSAVE6", 32, 0 },
    117   { "EXCSAVE7", 32, 0 },
    118   { "EPS2", 13, 0 },
    119   { "EPS3", 13, 0 },
    120   { "EPS4", 13, 0 },
    121   { "EPS5", 13, 0 },
    122   { "EPS6", 13, 0 },
    123   { "EPS7", 13, 0 },
    124   { "EXCCAUSE", 6, 0 },
    125   { "PSINTLEVEL", 4, 0 },
    126   { "PSUM", 1, 0 },
    127   { "PSWOE", 1, 0 },
    128   { "PSEXCM", 1, 0 },
    129   { "DEPC", 32, 0 },
    130   { "EXCVADDR", 32, 0 },
    131   { "WindowBase", 3, 0 },
    132   { "WindowStart", 8, 0 },
    133   { "PSCALLINC", 2, 0 },
    134   { "PSOWB", 4, 0 },
    135   { "SAR", 6, 0 },
    136   { "MISC0", 32, 0 },
    137   { "MISC1", 32, 0 },
    138   { "InOCDMode", 1, 0 },
    139   { "INTENABLE", 22, 0 },
    140   { "DBREAKA0", 32, 0 },
    141   { "DBREAKC0", 8, 0 },
    142   { "DBREAKA1", 32, 0 },
    143   { "DBREAKC1", 8, 0 },
    144   { "IBREAKA0", 32, 0 },
    145   { "IBREAKA1", 32, 0 },
    146   { "IBREAKENABLE", 2, 0 },
    147   { "ICOUNTLEVEL", 4, 0 },
    148   { "DEBUGCAUSE", 6, 0 },
    149   { "DBNUM", 4, 0 },
    150   { "CCOMPARE0", 32, 0 },
    151   { "CCOMPARE1", 32, 0 },
    152   { "CCOMPARE2", 32, 0 },
    153   { "SCOMPARE1", 32, 0 },
    154   { "ATOMCTL", 6, 0 },
    155   { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
    156 };
    157 
    158 #define NUM_STATES 59
    159 
    160 enum xtensa_state_id {
    161   STATE_PC,
    162   STATE_ICOUNT,
    163   STATE_DDR,
    164   STATE_INTERRUPT,
    165   STATE_CCOUNT,
    166   STATE_XTSYNC,
    167   STATE_VECBASE,
    168   STATE_EPC1,
    169   STATE_EPC2,
    170   STATE_EPC3,
    171   STATE_EPC4,
    172   STATE_EPC5,
    173   STATE_EPC6,
    174   STATE_EPC7,
    175   STATE_EXCSAVE1,
    176   STATE_EXCSAVE2,
    177   STATE_EXCSAVE3,
    178   STATE_EXCSAVE4,
    179   STATE_EXCSAVE5,
    180   STATE_EXCSAVE6,
    181   STATE_EXCSAVE7,
    182   STATE_EPS2,
    183   STATE_EPS3,
    184   STATE_EPS4,
    185   STATE_EPS5,
    186   STATE_EPS6,
    187   STATE_EPS7,
    188   STATE_EXCCAUSE,
    189   STATE_PSINTLEVEL,
    190   STATE_PSUM,
    191   STATE_PSWOE,
    192   STATE_PSEXCM,
    193   STATE_DEPC,
    194   STATE_EXCVADDR,
    195   STATE_WindowBase,
    196   STATE_WindowStart,
    197   STATE_PSCALLINC,
    198   STATE_PSOWB,
    199   STATE_SAR,
    200   STATE_MISC0,
    201   STATE_MISC1,
    202   STATE_InOCDMode,
    203   STATE_INTENABLE,
    204   STATE_DBREAKA0,
    205   STATE_DBREAKC0,
    206   STATE_DBREAKA1,
    207   STATE_DBREAKC1,
    208   STATE_IBREAKA0,
    209   STATE_IBREAKA1,
    210   STATE_IBREAKENABLE,
    211   STATE_ICOUNTLEVEL,
    212   STATE_DEBUGCAUSE,
    213   STATE_DBNUM,
    214   STATE_CCOMPARE0,
    215   STATE_CCOMPARE1,
    216   STATE_CCOMPARE2,
    217   STATE_SCOMPARE1,
    218   STATE_ATOMCTL,
    219   STATE_EXPSTATE
    220 };
    221 
    222 
    223 /* Field definitions.  */
    224 
    225 static unsigned
    226 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
    227 {
    228   unsigned tie_t = 0;
    229   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    230   return tie_t;
    231 }
    232 
    233 static void
    234 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    235 {
    236   uint32 tie_t;
    237   tie_t = (val << 28) >> 28;
    238   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    239 }
    240 
    241 static unsigned
    242 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
    243 {
    244   unsigned tie_t = 0;
    245   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    246   return tie_t;
    247 }
    248 
    249 static void
    250 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    251 {
    252   uint32 tie_t;
    253   tie_t = (val << 28) >> 28;
    254   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    255 }
    256 
    257 static unsigned
    258 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
    259 {
    260   unsigned tie_t = 0;
    261   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    262   return tie_t;
    263 }
    264 
    265 static void
    266 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    267 {
    268   uint32 tie_t;
    269   tie_t = (val << 28) >> 28;
    270   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    271 }
    272 
    273 static unsigned
    274 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
    275 {
    276   unsigned tie_t = 0;
    277   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
    278   return tie_t;
    279 }
    280 
    281 static void
    282 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    283 {
    284   uint32 tie_t;
    285   tie_t = (val << 28) >> 28;
    286   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
    287 }
    288 
    289 static unsigned
    290 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
    291 {
    292   unsigned tie_t = 0;
    293   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
    294   return tie_t;
    295 }
    296 
    297 static void
    298 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    299 {
    300   uint32 tie_t;
    301   tie_t = (val << 28) >> 28;
    302   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
    303 }
    304 
    305 static unsigned
    306 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
    307 {
    308   unsigned tie_t = 0;
    309   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    310   return tie_t;
    311 }
    312 
    313 static void
    314 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    315 {
    316   uint32 tie_t;
    317   tie_t = (val << 28) >> 28;
    318   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    319 }
    320 
    321 static unsigned
    322 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
    323 {
    324   unsigned tie_t = 0;
    325   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    326   return tie_t;
    327 }
    328 
    329 static void
    330 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    331 {
    332   uint32 tie_t;
    333   tie_t = (val << 30) >> 30;
    334   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    335 }
    336 
    337 static unsigned
    338 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
    339 {
    340   unsigned tie_t = 0;
    341   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
    342   return tie_t;
    343 }
    344 
    345 static void
    346 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    347 {
    348   uint32 tie_t;
    349   tie_t = (val << 30) >> 30;
    350   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
    351 }
    352 
    353 static unsigned
    354 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
    355 {
    356   unsigned tie_t = 0;
    357   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    358   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    359   return tie_t;
    360 }
    361 
    362 static void
    363 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    364 {
    365   uint32 tie_t;
    366   tie_t = (val << 28) >> 28;
    367   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    368   tie_t = (val << 24) >> 28;
    369   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    370 }
    371 
    372 static unsigned
    373 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
    374 {
    375   unsigned tie_t = 0;
    376   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
    377   return tie_t;
    378 }
    379 
    380 static void
    381 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    382 {
    383   uint32 tie_t;
    384   tie_t = (val << 29) >> 29;
    385   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
    386 }
    387 
    388 static unsigned
    389 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
    390 {
    391   unsigned tie_t = 0;
    392   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    393   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    394   return tie_t;
    395 }
    396 
    397 static void
    398 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    399 {
    400   uint32 tie_t;
    401   tie_t = (val << 28) >> 28;
    402   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    403   tie_t = (val << 24) >> 28;
    404   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    405 }
    406 
    407 static unsigned
    408 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
    409 {
    410   unsigned tie_t = 0;
    411   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
    412   return tie_t;
    413 }
    414 
    415 static void
    416 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    417 {
    418   uint32 tie_t;
    419   tie_t = (val << 29) >> 29;
    420   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
    421 }
    422 
    423 static unsigned
    424 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
    425 {
    426   unsigned tie_t = 0;
    427   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    428   return tie_t;
    429 }
    430 
    431 static void
    432 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    433 {
    434   uint32 tie_t;
    435   tie_t = (val << 28) >> 28;
    436   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    437 }
    438 
    439 static unsigned
    440 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
    441 {
    442   unsigned tie_t = 0;
    443   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    444   return tie_t;
    445 }
    446 
    447 static void
    448 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    449 {
    450   uint32 tie_t;
    451   tie_t = (val << 28) >> 28;
    452   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    453 }
    454 
    455 static unsigned
    456 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
    457 {
    458   unsigned tie_t = 0;
    459   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    460   return tie_t;
    461 }
    462 
    463 static void
    464 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    465 {
    466   uint32 tie_t;
    467   tie_t = (val << 28) >> 28;
    468   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    469 }
    470 
    471 static unsigned
    472 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
    473 {
    474   unsigned tie_t = 0;
    475   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    476   return tie_t;
    477 }
    478 
    479 static void
    480 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    481 {
    482   uint32 tie_t;
    483   tie_t = (val << 28) >> 28;
    484   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    485 }
    486 
    487 static unsigned
    488 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
    489 {
    490   unsigned tie_t = 0;
    491   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
    492   return tie_t;
    493 }
    494 
    495 static void
    496 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    497 {
    498   uint32 tie_t;
    499   tie_t = (val << 31) >> 31;
    500   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
    501 }
    502 
    503 static unsigned
    504 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
    505 {
    506   unsigned tie_t = 0;
    507   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    508   return tie_t;
    509 }
    510 
    511 static void
    512 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    513 {
    514   uint32 tie_t;
    515   tie_t = (val << 31) >> 31;
    516   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    517 }
    518 
    519 static unsigned
    520 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
    521 {
    522   unsigned tie_t = 0;
    523   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    524   return tie_t;
    525 }
    526 
    527 static void
    528 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    529 {
    530   uint32 tie_t;
    531   tie_t = (val << 28) >> 28;
    532   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    533 }
    534 
    535 static unsigned
    536 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
    537 {
    538   unsigned tie_t = 0;
    539   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    540   return tie_t;
    541 }
    542 
    543 static void
    544 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    545 {
    546   uint32 tie_t;
    547   tie_t = (val << 28) >> 28;
    548   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    549 }
    550 
    551 static unsigned
    552 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
    553 {
    554   unsigned tie_t = 0;
    555   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    556   return tie_t;
    557 }
    558 
    559 static void
    560 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    561 {
    562   uint32 tie_t;
    563   tie_t = (val << 31) >> 31;
    564   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    565 }
    566 
    567 static unsigned
    568 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
    569 {
    570   unsigned tie_t = 0;
    571   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    572   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    573   return tie_t;
    574 }
    575 
    576 static void
    577 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    578 {
    579   uint32 tie_t;
    580   tie_t = (val << 28) >> 28;
    581   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    582   tie_t = (val << 27) >> 31;
    583   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    584 }
    585 
    586 static unsigned
    587 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
    588 {
    589   unsigned tie_t = 0;
    590   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
    591   return tie_t;
    592 }
    593 
    594 static void
    595 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    596 {
    597   uint32 tie_t;
    598   tie_t = (val << 20) >> 20;
    599   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
    600 }
    601 
    602 static unsigned
    603 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
    604 {
    605   unsigned tie_t = 0;
    606   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    607   return tie_t;
    608 }
    609 
    610 static void
    611 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    612 {
    613   uint32 tie_t;
    614   tie_t = (val << 24) >> 24;
    615   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    616 }
    617 
    618 static unsigned
    619 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
    620 {
    621   unsigned tie_t = 0;
    622   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    623   return tie_t;
    624 }
    625 
    626 static void
    627 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    628 {
    629   uint32 tie_t;
    630   tie_t = (val << 28) >> 28;
    631   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    632 }
    633 
    634 static unsigned
    635 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
    636 {
    637   unsigned tie_t = 0;
    638   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    639   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    640   return tie_t;
    641 }
    642 
    643 static void
    644 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    645 {
    646   uint32 tie_t;
    647   tie_t = (val << 24) >> 24;
    648   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    649   tie_t = (val << 20) >> 28;
    650   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    651 }
    652 
    653 static unsigned
    654 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
    655 {
    656   unsigned tie_t = 0;
    657   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
    658   return tie_t;
    659 }
    660 
    661 static void
    662 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    663 {
    664   uint32 tie_t;
    665   tie_t = (val << 16) >> 16;
    666   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
    667 }
    668 
    669 static unsigned
    670 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
    671 {
    672   unsigned tie_t = 0;
    673   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
    674   return tie_t;
    675 }
    676 
    677 static void
    678 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    679 {
    680   uint32 tie_t;
    681   tie_t = (val << 14) >> 14;
    682   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
    683 }
    684 
    685 static unsigned
    686 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
    687 {
    688   unsigned tie_t = 0;
    689   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    690   return tie_t;
    691 }
    692 
    693 static void
    694 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    695 {
    696   uint32 tie_t;
    697   tie_t = (val << 28) >> 28;
    698   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    699 }
    700 
    701 static unsigned
    702 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
    703 {
    704   unsigned tie_t = 0;
    705   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    706   return tie_t;
    707 }
    708 
    709 static void
    710 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    711 {
    712   uint32 tie_t;
    713   tie_t = (val << 31) >> 31;
    714   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    715 }
    716 
    717 static unsigned
    718 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
    719 {
    720   unsigned tie_t = 0;
    721   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    722   return tie_t;
    723 }
    724 
    725 static void
    726 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    727 {
    728   uint32 tie_t;
    729   tie_t = (val << 31) >> 31;
    730   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    731 }
    732 
    733 static unsigned
    734 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
    735 {
    736   unsigned tie_t = 0;
    737   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    738   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    739   return tie_t;
    740 }
    741 
    742 static void
    743 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    744 {
    745   uint32 tie_t;
    746   tie_t = (val << 28) >> 28;
    747   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    748   tie_t = (val << 27) >> 31;
    749   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    750 }
    751 
    752 static unsigned
    753 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
    754 {
    755   unsigned tie_t = 0;
    756   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    757   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    758   return tie_t;
    759 }
    760 
    761 static void
    762 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    763 {
    764   uint32 tie_t;
    765   tie_t = (val << 28) >> 28;
    766   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    767   tie_t = (val << 27) >> 31;
    768   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    769 }
    770 
    771 static unsigned
    772 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
    773 {
    774   unsigned tie_t = 0;
    775   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    776   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    777   return tie_t;
    778 }
    779 
    780 static void
    781 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    782 {
    783   uint32 tie_t;
    784   tie_t = (val << 28) >> 28;
    785   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    786   tie_t = (val << 27) >> 31;
    787   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    788 }
    789 
    790 static unsigned
    791 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
    792 {
    793   unsigned tie_t = 0;
    794   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
    795   return tie_t;
    796 }
    797 
    798 static void
    799 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    800 {
    801   uint32 tie_t;
    802   tie_t = (val << 31) >> 31;
    803   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
    804 }
    805 
    806 static unsigned
    807 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
    808 {
    809   unsigned tie_t = 0;
    810   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
    811   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    812   return tie_t;
    813 }
    814 
    815 static void
    816 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    817 {
    818   uint32 tie_t;
    819   tie_t = (val << 28) >> 28;
    820   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    821   tie_t = (val << 27) >> 31;
    822   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
    823 }
    824 
    825 static unsigned
    826 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
    827 {
    828   unsigned tie_t = 0;
    829   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    830   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    831   return tie_t;
    832 }
    833 
    834 static void
    835 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    836 {
    837   uint32 tie_t;
    838   tie_t = (val << 28) >> 28;
    839   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    840   tie_t = (val << 24) >> 28;
    841   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    842 }
    843 
    844 static unsigned
    845 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
    846 {
    847   unsigned tie_t = 0;
    848   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    849   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    850   return tie_t;
    851 }
    852 
    853 static void
    854 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    855 {
    856   uint32 tie_t;
    857   tie_t = (val << 28) >> 28;
    858   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    859   tie_t = (val << 24) >> 28;
    860   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    861 }
    862 
    863 static unsigned
    864 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
    865 {
    866   unsigned tie_t = 0;
    867   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    868   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    869   return tie_t;
    870 }
    871 
    872 static void
    873 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    874 {
    875   uint32 tie_t;
    876   tie_t = (val << 28) >> 28;
    877   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    878   tie_t = (val << 24) >> 28;
    879   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    880 }
    881 
    882 static unsigned
    883 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
    884 {
    885   unsigned tie_t = 0;
    886   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    887   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    888   return tie_t;
    889 }
    890 
    891 static void
    892 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    893 {
    894   uint32 tie_t;
    895   tie_t = (val << 28) >> 28;
    896   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    897   tie_t = (val << 24) >> 28;
    898   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    899 }
    900 
    901 static unsigned
    902 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
    903 {
    904   unsigned tie_t = 0;
    905   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    906   return tie_t;
    907 }
    908 
    909 static void
    910 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    911 {
    912   uint32 tie_t;
    913   tie_t = (val << 28) >> 28;
    914   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    915 }
    916 
    917 static unsigned
    918 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
    919 {
    920   unsigned tie_t = 0;
    921   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    922   return tie_t;
    923 }
    924 
    925 static void
    926 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    927 {
    928   uint32 tie_t;
    929   tie_t = (val << 28) >> 28;
    930   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    931 }
    932 
    933 static unsigned
    934 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
    935 {
    936   unsigned tie_t = 0;
    937   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    938   return tie_t;
    939 }
    940 
    941 static void
    942 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    943 {
    944   uint32 tie_t;
    945   tie_t = (val << 28) >> 28;
    946   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    947 }
    948 
    949 static unsigned
    950 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
    951 {
    952   unsigned tie_t = 0;
    953   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
    954   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    955   return tie_t;
    956 }
    957 
    958 static void
    959 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    960 {
    961   uint32 tie_t;
    962   tie_t = (val << 30) >> 30;
    963   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    964   tie_t = (val << 28) >> 30;
    965   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
    966 }
    967 
    968 static unsigned
    969 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
    970 {
    971   unsigned tie_t = 0;
    972   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    973   return tie_t;
    974 }
    975 
    976 static void
    977 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    978 {
    979   uint32 tie_t;
    980   tie_t = (val << 31) >> 31;
    981   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    982 }
    983 
    984 static unsigned
    985 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
    986 {
    987   unsigned tie_t = 0;
    988   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    989   return tie_t;
    990 }
    991 
    992 static void
    993 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    994 {
    995   uint32 tie_t;
    996   tie_t = (val << 28) >> 28;
    997   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    998 }
    999 
   1000 static unsigned
   1001 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1002 {
   1003   unsigned tie_t = 0;
   1004   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1005   return tie_t;
   1006 }
   1007 
   1008 static void
   1009 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1010 {
   1011   uint32 tie_t;
   1012   tie_t = (val << 28) >> 28;
   1013   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1014 }
   1015 
   1016 static unsigned
   1017 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1018 {
   1019   unsigned tie_t = 0;
   1020   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1021   return tie_t;
   1022 }
   1023 
   1024 static void
   1025 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1026 {
   1027   uint32 tie_t;
   1028   tie_t = (val << 30) >> 30;
   1029   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1030 }
   1031 
   1032 static unsigned
   1033 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1034 {
   1035   unsigned tie_t = 0;
   1036   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1037   return tie_t;
   1038 }
   1039 
   1040 static void
   1041 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1042 {
   1043   uint32 tie_t;
   1044   tie_t = (val << 30) >> 30;
   1045   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1046 }
   1047 
   1048 static unsigned
   1049 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
   1050 {
   1051   unsigned tie_t = 0;
   1052   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1053   return tie_t;
   1054 }
   1055 
   1056 static void
   1057 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1058 {
   1059   uint32 tie_t;
   1060   tie_t = (val << 28) >> 28;
   1061   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1062 }
   1063 
   1064 static unsigned
   1065 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1066 {
   1067   unsigned tie_t = 0;
   1068   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1069   return tie_t;
   1070 }
   1071 
   1072 static void
   1073 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1074 {
   1075   uint32 tie_t;
   1076   tie_t = (val << 28) >> 28;
   1077   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1078 }
   1079 
   1080 static unsigned
   1081 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1082 {
   1083   unsigned tie_t = 0;
   1084   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1085   return tie_t;
   1086 }
   1087 
   1088 static void
   1089 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1090 {
   1091   uint32 tie_t;
   1092   tie_t = (val << 29) >> 29;
   1093   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1094 }
   1095 
   1096 static unsigned
   1097 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1098 {
   1099   unsigned tie_t = 0;
   1100   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1101   return tie_t;
   1102 }
   1103 
   1104 static void
   1105 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1106 {
   1107   uint32 tie_t;
   1108   tie_t = (val << 29) >> 29;
   1109   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1110 }
   1111 
   1112 static unsigned
   1113 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
   1114 {
   1115   unsigned tie_t = 0;
   1116   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1117   return tie_t;
   1118 }
   1119 
   1120 static void
   1121 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1122 {
   1123   uint32 tie_t;
   1124   tie_t = (val << 31) >> 31;
   1125   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1126 }
   1127 
   1128 static unsigned
   1129 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
   1130 {
   1131   unsigned tie_t = 0;
   1132   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1133   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1134   return tie_t;
   1135 }
   1136 
   1137 static void
   1138 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1139 {
   1140   uint32 tie_t;
   1141   tie_t = (val << 28) >> 28;
   1142   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1143   tie_t = (val << 26) >> 30;
   1144   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1145 }
   1146 
   1147 static unsigned
   1148 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
   1149 {
   1150   unsigned tie_t = 0;
   1151   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1152   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1153   return tie_t;
   1154 }
   1155 
   1156 static void
   1157 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1158 {
   1159   uint32 tie_t;
   1160   tie_t = (val << 28) >> 28;
   1161   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1162   tie_t = (val << 26) >> 30;
   1163   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1164 }
   1165 
   1166 static unsigned
   1167 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
   1168 {
   1169   unsigned tie_t = 0;
   1170   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1171   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1172   return tie_t;
   1173 }
   1174 
   1175 static void
   1176 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1177 {
   1178   uint32 tie_t;
   1179   tie_t = (val << 28) >> 28;
   1180   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1181   tie_t = (val << 25) >> 29;
   1182   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1183 }
   1184 
   1185 static unsigned
   1186 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
   1187 {
   1188   unsigned tie_t = 0;
   1189   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1190   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1191   return tie_t;
   1192 }
   1193 
   1194 static void
   1195 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1196 {
   1197   uint32 tie_t;
   1198   tie_t = (val << 28) >> 28;
   1199   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1200   tie_t = (val << 25) >> 29;
   1201   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1202 }
   1203 
   1204 static unsigned
   1205 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1206 {
   1207   unsigned tie_t = 0;
   1208   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
   1209   return tie_t;
   1210 }
   1211 
   1212 static void
   1213 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1214 {
   1215   uint32 tie_t;
   1216   tie_t = (val << 17) >> 17;
   1217   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
   1218 }
   1219 
   1220 static unsigned
   1221 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1222 {
   1223   unsigned tie_t = 0;
   1224   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
   1225   return tie_t;
   1226 }
   1227 
   1228 static void
   1229 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1230 {
   1231   uint32 tie_t;
   1232   tie_t = (val << 14) >> 14;
   1233   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
   1234 }
   1235 
   1236 static unsigned
   1237 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
   1238 {
   1239   unsigned tie_t = 0;
   1240   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1241   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1242   return tie_t;
   1243 }
   1244 
   1245 static void
   1246 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1247 {
   1248   uint32 tie_t;
   1249   tie_t = (val << 28) >> 28;
   1250   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1251   tie_t = (val << 27) >> 31;
   1252   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1253 }
   1254 
   1255 static unsigned
   1256 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
   1257 {
   1258   unsigned tie_t = 0;
   1259   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1260   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1261   return tie_t;
   1262 }
   1263 
   1264 static void
   1265 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1266 {
   1267   uint32 tie_t;
   1268   tie_t = (val << 28) >> 28;
   1269   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1270   tie_t = (val << 27) >> 31;
   1271   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1272 }
   1273 
   1274 static unsigned
   1275 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
   1276 {
   1277   unsigned tie_t = 0;
   1278   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1279   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1280   return tie_t;
   1281 }
   1282 
   1283 static void
   1284 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1285 {
   1286   uint32 tie_t;
   1287   tie_t = (val << 28) >> 28;
   1288   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1289   tie_t = (val << 27) >> 31;
   1290   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1291 }
   1292 
   1293 static unsigned
   1294 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
   1295 {
   1296   unsigned tie_t = 0;
   1297   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
   1298   return tie_t;
   1299 }
   1300 
   1301 static void
   1302 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1303 {
   1304   uint32 tie_t;
   1305   tie_t = (val << 29) >> 29;
   1306   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
   1307 }
   1308 
   1309 static unsigned
   1310 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
   1311 {
   1312   unsigned tie_t = 0;
   1313   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
   1314   return tie_t;
   1315 }
   1316 
   1317 static void
   1318 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1319 {
   1320   uint32 tie_t;
   1321   tie_t = (val << 29) >> 29;
   1322   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
   1323 }
   1324 
   1325 static void
   1326 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
   1327 		    uint32 val ATTRIBUTE_UNUSED)
   1328 {
   1329   /* Do nothing.  */
   1330 }
   1331 
   1332 static unsigned
   1333 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1334 {
   1335   return 0;
   1336 }
   1337 
   1338 static unsigned
   1339 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1340 {
   1341   return 4;
   1342 }
   1343 
   1344 static unsigned
   1345 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1346 {
   1347   return 8;
   1348 }
   1349 
   1350 static unsigned
   1351 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1352 {
   1353   return 12;
   1354 }
   1355 
   1356 enum xtensa_field_id {
   1357   FIELD_t,
   1358   FIELD_bbi4,
   1359   FIELD_bbi,
   1360   FIELD_imm12,
   1361   FIELD_imm8,
   1362   FIELD_s,
   1363   FIELD_imm12b,
   1364   FIELD_imm16,
   1365   FIELD_m,
   1366   FIELD_n,
   1367   FIELD_offset,
   1368   FIELD_op0,
   1369   FIELD_op1,
   1370   FIELD_op2,
   1371   FIELD_r,
   1372   FIELD_sa4,
   1373   FIELD_sae4,
   1374   FIELD_sae,
   1375   FIELD_sal,
   1376   FIELD_sargt,
   1377   FIELD_sas4,
   1378   FIELD_sas,
   1379   FIELD_sr,
   1380   FIELD_st,
   1381   FIELD_thi3,
   1382   FIELD_imm4,
   1383   FIELD_mn,
   1384   FIELD_i,
   1385   FIELD_imm6lo,
   1386   FIELD_imm6hi,
   1387   FIELD_imm7lo,
   1388   FIELD_imm7hi,
   1389   FIELD_z,
   1390   FIELD_imm6,
   1391   FIELD_imm7,
   1392   FIELD_xt_wbr15_imm,
   1393   FIELD_xt_wbr18_imm,
   1394   FIELD_bitindex,
   1395   FIELD_s3to1,
   1396   FIELD__ar0,
   1397   FIELD__ar4,
   1398   FIELD__ar8,
   1399   FIELD__ar12
   1400 };
   1401 
   1402 
   1403 /* Functional units.  */
   1404 
   1405 #define funcUnits 0
   1406 
   1407 
   1408 /* Register files.  */
   1409 
   1410 enum xtensa_regfile_id {
   1411   REGFILE_AR
   1412 };
   1413 
   1414 static xtensa_regfile_internal regfiles[] = {
   1415   { "AR", "a", REGFILE_AR, 32, 32 }
   1416 };
   1417 
   1418 
   1419 /* Interfaces.  */
   1420 
   1421 static xtensa_interface_internal interfaces[] = {
   1422   { "IMPWIRE", 32, 0, 0, 'i' }
   1423 };
   1424 
   1425 enum xtensa_interface_id {
   1426   INTERFACE_IMPWIRE
   1427 };
   1428 
   1429 
   1430 /* Constant tables.  */
   1431 
   1432 /* constant table ai4c */
   1433 static const unsigned CONST_TBL_ai4c_0[] = {
   1434   0xffffffff,
   1435   0x1,
   1436   0x2,
   1437   0x3,
   1438   0x4,
   1439   0x5,
   1440   0x6,
   1441   0x7,
   1442   0x8,
   1443   0x9,
   1444   0xa,
   1445   0xb,
   1446   0xc,
   1447   0xd,
   1448   0xe,
   1449   0xf,
   1450   0
   1451 };
   1452 
   1453 /* constant table b4c */
   1454 static const unsigned CONST_TBL_b4c_0[] = {
   1455   0xffffffff,
   1456   0x1,
   1457   0x2,
   1458   0x3,
   1459   0x4,
   1460   0x5,
   1461   0x6,
   1462   0x7,
   1463   0x8,
   1464   0xa,
   1465   0xc,
   1466   0x10,
   1467   0x20,
   1468   0x40,
   1469   0x80,
   1470   0x100,
   1471   0
   1472 };
   1473 
   1474 /* constant table b4cu */
   1475 static const unsigned CONST_TBL_b4cu_0[] = {
   1476   0x8000,
   1477   0x10000,
   1478   0x2,
   1479   0x3,
   1480   0x4,
   1481   0x5,
   1482   0x6,
   1483   0x7,
   1484   0x8,
   1485   0xa,
   1486   0xc,
   1487   0x10,
   1488   0x20,
   1489   0x40,
   1490   0x80,
   1491   0x100,
   1492   0
   1493 };
   1494 
   1495 
   1496 /* Instruction operands.  */
   1497 
   1498 static int
   1499 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
   1500 {
   1501   unsigned soffsetx4_out_0;
   1502   unsigned soffsetx4_in_0;
   1503   soffsetx4_in_0 = *valp & 0x3ffff;
   1504   soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
   1505   *valp = soffsetx4_out_0;
   1506   return 0;
   1507 }
   1508 
   1509 static int
   1510 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
   1511 {
   1512   unsigned soffsetx4_in_0;
   1513   unsigned soffsetx4_out_0;
   1514   soffsetx4_out_0 = *valp;
   1515   soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
   1516   *valp = soffsetx4_in_0;
   1517   return 0;
   1518 }
   1519 
   1520 static int
   1521 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
   1522 {
   1523   unsigned uimm12x8_out_0;
   1524   unsigned uimm12x8_in_0;
   1525   uimm12x8_in_0 = *valp & 0xfff;
   1526   uimm12x8_out_0 = uimm12x8_in_0 << 3;
   1527   *valp = uimm12x8_out_0;
   1528   return 0;
   1529 }
   1530 
   1531 static int
   1532 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
   1533 {
   1534   unsigned uimm12x8_in_0;
   1535   unsigned uimm12x8_out_0;
   1536   uimm12x8_out_0 = *valp;
   1537   uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
   1538   *valp = uimm12x8_in_0;
   1539   return 0;
   1540 }
   1541 
   1542 static int
   1543 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
   1544 {
   1545   unsigned simm4_out_0;
   1546   unsigned simm4_in_0;
   1547   simm4_in_0 = *valp & 0xf;
   1548   simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
   1549   *valp = simm4_out_0;
   1550   return 0;
   1551 }
   1552 
   1553 static int
   1554 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
   1555 {
   1556   unsigned simm4_in_0;
   1557   unsigned simm4_out_0;
   1558   simm4_out_0 = *valp;
   1559   simm4_in_0 = (simm4_out_0 & 0xf);
   1560   *valp = simm4_in_0;
   1561   return 0;
   1562 }
   1563 
   1564 static int
   1565 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1566 {
   1567   return 0;
   1568 }
   1569 
   1570 static int
   1571 OperandSem_opnd_sem_AR_encode (uint32 *valp)
   1572 {
   1573   return (*valp >= 32);
   1574 }
   1575 
   1576 static int
   1577 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1578 {
   1579   return 0;
   1580 }
   1581 
   1582 static int
   1583 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
   1584 {
   1585   return (*valp >= 32);
   1586 }
   1587 
   1588 static int
   1589 OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1590 {
   1591   return 0;
   1592 }
   1593 
   1594 static int
   1595 OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
   1596 {
   1597   return (*valp >= 32);
   1598 }
   1599 
   1600 static int
   1601 OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1602 {
   1603   return 0;
   1604 }
   1605 
   1606 static int
   1607 OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
   1608 {
   1609   return (*valp >= 32);
   1610 }
   1611 
   1612 static int
   1613 OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1614 {
   1615   return 0;
   1616 }
   1617 
   1618 static int
   1619 OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
   1620 {
   1621   return (*valp >= 32);
   1622 }
   1623 
   1624 static int
   1625 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1626 {
   1627   return 0;
   1628 }
   1629 
   1630 static int
   1631 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
   1632 {
   1633   return (*valp >= 32);
   1634 }
   1635 
   1636 static int
   1637 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
   1638 {
   1639   unsigned immrx4_out_0;
   1640   unsigned immrx4_in_0;
   1641   immrx4_in_0 = *valp & 0xf;
   1642   immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
   1643   *valp = immrx4_out_0;
   1644   return 0;
   1645 }
   1646 
   1647 static int
   1648 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
   1649 {
   1650   unsigned immrx4_in_0;
   1651   unsigned immrx4_out_0;
   1652   immrx4_out_0 = *valp;
   1653   immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
   1654   *valp = immrx4_in_0;
   1655   return 0;
   1656 }
   1657 
   1658 static int
   1659 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
   1660 {
   1661   unsigned lsi4x4_out_0;
   1662   unsigned lsi4x4_in_0;
   1663   lsi4x4_in_0 = *valp & 0xf;
   1664   lsi4x4_out_0 = lsi4x4_in_0 << 2;
   1665   *valp = lsi4x4_out_0;
   1666   return 0;
   1667 }
   1668 
   1669 static int
   1670 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
   1671 {
   1672   unsigned lsi4x4_in_0;
   1673   unsigned lsi4x4_out_0;
   1674   lsi4x4_out_0 = *valp;
   1675   lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
   1676   *valp = lsi4x4_in_0;
   1677   return 0;
   1678 }
   1679 
   1680 static int
   1681 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
   1682 {
   1683   unsigned simm7_out_0;
   1684   unsigned simm7_in_0;
   1685   simm7_in_0 = *valp & 0x7f;
   1686   simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
   1687   *valp = simm7_out_0;
   1688   return 0;
   1689 }
   1690 
   1691 static int
   1692 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
   1693 {
   1694   unsigned simm7_in_0;
   1695   unsigned simm7_out_0;
   1696   simm7_out_0 = *valp;
   1697   simm7_in_0 = (simm7_out_0 & 0x7f);
   1698   *valp = simm7_in_0;
   1699   return 0;
   1700 }
   1701 
   1702 static int
   1703 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
   1704 {
   1705   unsigned uimm6_out_0;
   1706   unsigned uimm6_in_0;
   1707   uimm6_in_0 = *valp & 0x3f;
   1708   uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
   1709   *valp = uimm6_out_0;
   1710   return 0;
   1711 }
   1712 
   1713 static int
   1714 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
   1715 {
   1716   unsigned uimm6_in_0;
   1717   unsigned uimm6_out_0;
   1718   uimm6_out_0 = *valp;
   1719   uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
   1720   *valp = uimm6_in_0;
   1721   return 0;
   1722 }
   1723 
   1724 static int
   1725 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
   1726 {
   1727   unsigned ai4const_out_0;
   1728   unsigned ai4const_in_0;
   1729   ai4const_in_0 = *valp & 0xf;
   1730   ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
   1731   *valp = ai4const_out_0;
   1732   return 0;
   1733 }
   1734 
   1735 static int
   1736 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
   1737 {
   1738   unsigned ai4const_in_0;
   1739   unsigned ai4const_out_0;
   1740   ai4const_out_0 = *valp;
   1741   switch (ai4const_out_0)
   1742     {
   1743     case 0xffffffff: ai4const_in_0 = 0; break;
   1744     case 0x1: ai4const_in_0 = 0x1; break;
   1745     case 0x2: ai4const_in_0 = 0x2; break;
   1746     case 0x3: ai4const_in_0 = 0x3; break;
   1747     case 0x4: ai4const_in_0 = 0x4; break;
   1748     case 0x5: ai4const_in_0 = 0x5; break;
   1749     case 0x6: ai4const_in_0 = 0x6; break;
   1750     case 0x7: ai4const_in_0 = 0x7; break;
   1751     case 0x8: ai4const_in_0 = 0x8; break;
   1752     case 0x9: ai4const_in_0 = 0x9; break;
   1753     case 0xa: ai4const_in_0 = 0xa; break;
   1754     case 0xb: ai4const_in_0 = 0xb; break;
   1755     case 0xc: ai4const_in_0 = 0xc; break;
   1756     case 0xd: ai4const_in_0 = 0xd; break;
   1757     case 0xe: ai4const_in_0 = 0xe; break;
   1758     default: ai4const_in_0 = 0xf; break;
   1759     }
   1760   *valp = ai4const_in_0;
   1761   return 0;
   1762 }
   1763 
   1764 static int
   1765 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
   1766 {
   1767   unsigned b4const_out_0;
   1768   unsigned b4const_in_0;
   1769   b4const_in_0 = *valp & 0xf;
   1770   b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
   1771   *valp = b4const_out_0;
   1772   return 0;
   1773 }
   1774 
   1775 static int
   1776 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
   1777 {
   1778   unsigned b4const_in_0;
   1779   unsigned b4const_out_0;
   1780   b4const_out_0 = *valp;
   1781   switch (b4const_out_0)
   1782     {
   1783     case 0xffffffff: b4const_in_0 = 0; break;
   1784     case 0x1: b4const_in_0 = 0x1; break;
   1785     case 0x2: b4const_in_0 = 0x2; break;
   1786     case 0x3: b4const_in_0 = 0x3; break;
   1787     case 0x4: b4const_in_0 = 0x4; break;
   1788     case 0x5: b4const_in_0 = 0x5; break;
   1789     case 0x6: b4const_in_0 = 0x6; break;
   1790     case 0x7: b4const_in_0 = 0x7; break;
   1791     case 0x8: b4const_in_0 = 0x8; break;
   1792     case 0xa: b4const_in_0 = 0x9; break;
   1793     case 0xc: b4const_in_0 = 0xa; break;
   1794     case 0x10: b4const_in_0 = 0xb; break;
   1795     case 0x20: b4const_in_0 = 0xc; break;
   1796     case 0x40: b4const_in_0 = 0xd; break;
   1797     case 0x80: b4const_in_0 = 0xe; break;
   1798     default: b4const_in_0 = 0xf; break;
   1799     }
   1800   *valp = b4const_in_0;
   1801   return 0;
   1802 }
   1803 
   1804 static int
   1805 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
   1806 {
   1807   unsigned b4constu_out_0;
   1808   unsigned b4constu_in_0;
   1809   b4constu_in_0 = *valp & 0xf;
   1810   b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
   1811   *valp = b4constu_out_0;
   1812   return 0;
   1813 }
   1814 
   1815 static int
   1816 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
   1817 {
   1818   unsigned b4constu_in_0;
   1819   unsigned b4constu_out_0;
   1820   b4constu_out_0 = *valp;
   1821   switch (b4constu_out_0)
   1822     {
   1823     case 0x8000: b4constu_in_0 = 0; break;
   1824     case 0x10000: b4constu_in_0 = 0x1; break;
   1825     case 0x2: b4constu_in_0 = 0x2; break;
   1826     case 0x3: b4constu_in_0 = 0x3; break;
   1827     case 0x4: b4constu_in_0 = 0x4; break;
   1828     case 0x5: b4constu_in_0 = 0x5; break;
   1829     case 0x6: b4constu_in_0 = 0x6; break;
   1830     case 0x7: b4constu_in_0 = 0x7; break;
   1831     case 0x8: b4constu_in_0 = 0x8; break;
   1832     case 0xa: b4constu_in_0 = 0x9; break;
   1833     case 0xc: b4constu_in_0 = 0xa; break;
   1834     case 0x10: b4constu_in_0 = 0xb; break;
   1835     case 0x20: b4constu_in_0 = 0xc; break;
   1836     case 0x40: b4constu_in_0 = 0xd; break;
   1837     case 0x80: b4constu_in_0 = 0xe; break;
   1838     default: b4constu_in_0 = 0xf; break;
   1839     }
   1840   *valp = b4constu_in_0;
   1841   return 0;
   1842 }
   1843 
   1844 static int
   1845 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
   1846 {
   1847   unsigned uimm8_out_0;
   1848   unsigned uimm8_in_0;
   1849   uimm8_in_0 = *valp & 0xff;
   1850   uimm8_out_0 = uimm8_in_0;
   1851   *valp = uimm8_out_0;
   1852   return 0;
   1853 }
   1854 
   1855 static int
   1856 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
   1857 {
   1858   unsigned uimm8_in_0;
   1859   unsigned uimm8_out_0;
   1860   uimm8_out_0 = *valp;
   1861   uimm8_in_0 = (uimm8_out_0 & 0xff);
   1862   *valp = uimm8_in_0;
   1863   return 0;
   1864 }
   1865 
   1866 static int
   1867 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
   1868 {
   1869   unsigned uimm8x2_out_0;
   1870   unsigned uimm8x2_in_0;
   1871   uimm8x2_in_0 = *valp & 0xff;
   1872   uimm8x2_out_0 = uimm8x2_in_0 << 1;
   1873   *valp = uimm8x2_out_0;
   1874   return 0;
   1875 }
   1876 
   1877 static int
   1878 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
   1879 {
   1880   unsigned uimm8x2_in_0;
   1881   unsigned uimm8x2_out_0;
   1882   uimm8x2_out_0 = *valp;
   1883   uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
   1884   *valp = uimm8x2_in_0;
   1885   return 0;
   1886 }
   1887 
   1888 static int
   1889 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
   1890 {
   1891   unsigned uimm8x4_out_0;
   1892   unsigned uimm8x4_in_0;
   1893   uimm8x4_in_0 = *valp & 0xff;
   1894   uimm8x4_out_0 = uimm8x4_in_0 << 2;
   1895   *valp = uimm8x4_out_0;
   1896   return 0;
   1897 }
   1898 
   1899 static int
   1900 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
   1901 {
   1902   unsigned uimm8x4_in_0;
   1903   unsigned uimm8x4_out_0;
   1904   uimm8x4_out_0 = *valp;
   1905   uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
   1906   *valp = uimm8x4_in_0;
   1907   return 0;
   1908 }
   1909 
   1910 static int
   1911 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
   1912 {
   1913   unsigned uimm4x16_out_0;
   1914   unsigned uimm4x16_in_0;
   1915   uimm4x16_in_0 = *valp & 0xf;
   1916   uimm4x16_out_0 = uimm4x16_in_0 << 4;
   1917   *valp = uimm4x16_out_0;
   1918   return 0;
   1919 }
   1920 
   1921 static int
   1922 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
   1923 {
   1924   unsigned uimm4x16_in_0;
   1925   unsigned uimm4x16_out_0;
   1926   uimm4x16_out_0 = *valp;
   1927   uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
   1928   *valp = uimm4x16_in_0;
   1929   return 0;
   1930 }
   1931 
   1932 static int
   1933 OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
   1934 {
   1935   unsigned uimmrx4_out_0;
   1936   unsigned uimmrx4_in_0;
   1937   uimmrx4_in_0 = *valp & 0xf;
   1938   uimmrx4_out_0 = uimmrx4_in_0 << 2;
   1939   *valp = uimmrx4_out_0;
   1940   return 0;
   1941 }
   1942 
   1943 static int
   1944 OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
   1945 {
   1946   unsigned uimmrx4_in_0;
   1947   unsigned uimmrx4_out_0;
   1948   uimmrx4_out_0 = *valp;
   1949   uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
   1950   *valp = uimmrx4_in_0;
   1951   return 0;
   1952 }
   1953 
   1954 static int
   1955 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
   1956 {
   1957   unsigned simm8_out_0;
   1958   unsigned simm8_in_0;
   1959   simm8_in_0 = *valp & 0xff;
   1960   simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
   1961   *valp = simm8_out_0;
   1962   return 0;
   1963 }
   1964 
   1965 static int
   1966 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
   1967 {
   1968   unsigned simm8_in_0;
   1969   unsigned simm8_out_0;
   1970   simm8_out_0 = *valp;
   1971   simm8_in_0 = (simm8_out_0 & 0xff);
   1972   *valp = simm8_in_0;
   1973   return 0;
   1974 }
   1975 
   1976 static int
   1977 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
   1978 {
   1979   unsigned simm8x256_out_0;
   1980   unsigned simm8x256_in_0;
   1981   simm8x256_in_0 = *valp & 0xff;
   1982   simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
   1983   *valp = simm8x256_out_0;
   1984   return 0;
   1985 }
   1986 
   1987 static int
   1988 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
   1989 {
   1990   unsigned simm8x256_in_0;
   1991   unsigned simm8x256_out_0;
   1992   simm8x256_out_0 = *valp;
   1993   simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
   1994   *valp = simm8x256_in_0;
   1995   return 0;
   1996 }
   1997 
   1998 static int
   1999 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
   2000 {
   2001   unsigned simm12b_out_0;
   2002   unsigned simm12b_in_0;
   2003   simm12b_in_0 = *valp & 0xfff;
   2004   simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
   2005   *valp = simm12b_out_0;
   2006   return 0;
   2007 }
   2008 
   2009 static int
   2010 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
   2011 {
   2012   unsigned simm12b_in_0;
   2013   unsigned simm12b_out_0;
   2014   simm12b_out_0 = *valp;
   2015   simm12b_in_0 = (simm12b_out_0 & 0xfff);
   2016   *valp = simm12b_in_0;
   2017   return 0;
   2018 }
   2019 
   2020 static int
   2021 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
   2022 {
   2023   unsigned msalp32_out_0;
   2024   unsigned msalp32_in_0;
   2025   msalp32_in_0 = *valp & 0x1f;
   2026   msalp32_out_0 = 0x20 - msalp32_in_0;
   2027   *valp = msalp32_out_0;
   2028   return 0;
   2029 }
   2030 
   2031 static int
   2032 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
   2033 {
   2034   unsigned msalp32_in_0;
   2035   unsigned msalp32_out_0;
   2036   msalp32_out_0 = *valp;
   2037   msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
   2038   *valp = msalp32_in_0;
   2039   return 0;
   2040 }
   2041 
   2042 static int
   2043 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
   2044 {
   2045   unsigned op2p1_out_0;
   2046   unsigned op2p1_in_0;
   2047   op2p1_in_0 = *valp & 0xf;
   2048   op2p1_out_0 = op2p1_in_0 + 0x1;
   2049   *valp = op2p1_out_0;
   2050   return 0;
   2051 }
   2052 
   2053 static int
   2054 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
   2055 {
   2056   unsigned op2p1_in_0;
   2057   unsigned op2p1_out_0;
   2058   op2p1_out_0 = *valp;
   2059   op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
   2060   *valp = op2p1_in_0;
   2061   return 0;
   2062 }
   2063 
   2064 static int
   2065 OperandSem_opnd_sem_label8_decode (uint32 *valp)
   2066 {
   2067   unsigned label8_out_0;
   2068   unsigned label8_in_0;
   2069   label8_in_0 = *valp & 0xff;
   2070   label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
   2071   *valp = label8_out_0;
   2072   return 0;
   2073 }
   2074 
   2075 static int
   2076 OperandSem_opnd_sem_label8_encode (uint32 *valp)
   2077 {
   2078   unsigned label8_in_0;
   2079   unsigned label8_out_0;
   2080   label8_out_0 = *valp;
   2081   label8_in_0 = (label8_out_0 - 0x4) & 0xff;
   2082   *valp = label8_in_0;
   2083   return 0;
   2084 }
   2085 
   2086 static int
   2087 OperandSem_opnd_sem_label12_decode (uint32 *valp)
   2088 {
   2089   unsigned label12_out_0;
   2090   unsigned label12_in_0;
   2091   label12_in_0 = *valp & 0xfff;
   2092   label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
   2093   *valp = label12_out_0;
   2094   return 0;
   2095 }
   2096 
   2097 static int
   2098 OperandSem_opnd_sem_label12_encode (uint32 *valp)
   2099 {
   2100   unsigned label12_in_0;
   2101   unsigned label12_out_0;
   2102   label12_out_0 = *valp;
   2103   label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
   2104   *valp = label12_in_0;
   2105   return 0;
   2106 }
   2107 
   2108 static int
   2109 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
   2110 {
   2111   unsigned soffset_out_0;
   2112   unsigned soffset_in_0;
   2113   soffset_in_0 = *valp & 0x3ffff;
   2114   soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
   2115   *valp = soffset_out_0;
   2116   return 0;
   2117 }
   2118 
   2119 static int
   2120 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
   2121 {
   2122   unsigned soffset_in_0;
   2123   unsigned soffset_out_0;
   2124   soffset_out_0 = *valp;
   2125   soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
   2126   *valp = soffset_in_0;
   2127   return 0;
   2128 }
   2129 
   2130 static int
   2131 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
   2132 {
   2133   unsigned uimm16x4_out_0;
   2134   unsigned uimm16x4_in_0;
   2135   uimm16x4_in_0 = *valp & 0xffff;
   2136   uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
   2137   *valp = uimm16x4_out_0;
   2138   return 0;
   2139 }
   2140 
   2141 static int
   2142 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
   2143 {
   2144   unsigned uimm16x4_in_0;
   2145   unsigned uimm16x4_out_0;
   2146   uimm16x4_out_0 = *valp;
   2147   uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
   2148   *valp = uimm16x4_in_0;
   2149   return 0;
   2150 }
   2151 
   2152 static int
   2153 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
   2154 {
   2155   unsigned bbi_out_0;
   2156   unsigned bbi_in_0;
   2157   bbi_in_0 = *valp & 0x1f;
   2158   bbi_out_0 = (0 << 5) | bbi_in_0;
   2159   *valp = bbi_out_0;
   2160   return 0;
   2161 }
   2162 
   2163 static int
   2164 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
   2165 {
   2166   unsigned bbi_in_0;
   2167   unsigned bbi_out_0;
   2168   bbi_out_0 = *valp;
   2169   bbi_in_0 = (bbi_out_0 & 0x1f);
   2170   *valp = bbi_in_0;
   2171   return 0;
   2172 }
   2173 
   2174 static int
   2175 OperandSem_opnd_sem_s_decode (uint32 *valp)
   2176 {
   2177   unsigned s_out_0;
   2178   unsigned s_in_0;
   2179   s_in_0 = *valp & 0xf;
   2180   s_out_0 = (0 << 4) | s_in_0;
   2181   *valp = s_out_0;
   2182   return 0;
   2183 }
   2184 
   2185 static int
   2186 OperandSem_opnd_sem_s_encode (uint32 *valp)
   2187 {
   2188   unsigned s_in_0;
   2189   unsigned s_out_0;
   2190   s_out_0 = *valp;
   2191   s_in_0 = (s_out_0 & 0xf);
   2192   *valp = s_in_0;
   2193   return 0;
   2194 }
   2195 
   2196 static int
   2197 OperandSem_opnd_sem_immt_decode (uint32 *valp)
   2198 {
   2199   unsigned immt_out_0;
   2200   unsigned immt_in_0;
   2201   immt_in_0 = *valp & 0xf;
   2202   immt_out_0 = immt_in_0;
   2203   *valp = immt_out_0;
   2204   return 0;
   2205 }
   2206 
   2207 static int
   2208 OperandSem_opnd_sem_immt_encode (uint32 *valp)
   2209 {
   2210   unsigned immt_in_0;
   2211   unsigned immt_out_0;
   2212   immt_out_0 = *valp;
   2213   immt_in_0 = immt_out_0 & 0xf;
   2214   *valp = immt_in_0;
   2215   return 0;
   2216 }
   2217 
   2218 static int
   2219 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
   2220 {
   2221   unsigned tp7_out_0;
   2222   unsigned tp7_in_0;
   2223   tp7_in_0 = *valp & 0xf;
   2224   tp7_out_0 = tp7_in_0 + 0x7;
   2225   *valp = tp7_out_0;
   2226   return 0;
   2227 }
   2228 
   2229 static int
   2230 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
   2231 {
   2232   unsigned tp7_in_0;
   2233   unsigned tp7_out_0;
   2234   tp7_out_0 = *valp;
   2235   tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
   2236   *valp = tp7_in_0;
   2237   return 0;
   2238 }
   2239 
   2240 static int
   2241 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
   2242 {
   2243   unsigned xt_wbr15_label_out_0;
   2244   unsigned xt_wbr15_label_in_0;
   2245   xt_wbr15_label_in_0 = *valp & 0x7fff;
   2246   xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
   2247   *valp = xt_wbr15_label_out_0;
   2248   return 0;
   2249 }
   2250 
   2251 static int
   2252 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
   2253 {
   2254   unsigned xt_wbr15_label_in_0;
   2255   unsigned xt_wbr15_label_out_0;
   2256   xt_wbr15_label_out_0 = *valp;
   2257   xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
   2258   *valp = xt_wbr15_label_in_0;
   2259   return 0;
   2260 }
   2261 
   2262 static int
   2263 OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
   2264 {
   2265   unsigned xt_wbr18_label_out_0;
   2266   unsigned xt_wbr18_label_in_0;
   2267   xt_wbr18_label_in_0 = *valp & 0x3ffff;
   2268   xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
   2269   *valp = xt_wbr18_label_out_0;
   2270   return 0;
   2271 }
   2272 
   2273 static int
   2274 OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
   2275 {
   2276   unsigned xt_wbr18_label_in_0;
   2277   unsigned xt_wbr18_label_out_0;
   2278   xt_wbr18_label_out_0 = *valp;
   2279   xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
   2280   *valp = xt_wbr18_label_in_0;
   2281   return 0;
   2282 }
   2283 
   2284 static int
   2285 OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
   2286 {
   2287   unsigned bitindex_out_0;
   2288   unsigned bitindex_in_0;
   2289   bitindex_in_0 = *valp & 0x1f;
   2290   bitindex_out_0 = (0 << 5) | bitindex_in_0;
   2291   *valp = bitindex_out_0;
   2292   return 0;
   2293 }
   2294 
   2295 static int
   2296 OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
   2297 {
   2298   unsigned bitindex_in_0;
   2299   unsigned bitindex_out_0;
   2300   bitindex_out_0 = *valp;
   2301   bitindex_in_0 = (bitindex_out_0 & 0x1f);
   2302   *valp = bitindex_in_0;
   2303   return 0;
   2304 }
   2305 
   2306 static int
   2307 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
   2308 {
   2309   *valp -= (pc & ~0x3);
   2310   return 0;
   2311 }
   2312 
   2313 static int
   2314 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
   2315 {
   2316   *valp += (pc & ~0x3);
   2317   return 0;
   2318 }
   2319 
   2320 static int
   2321 Operand_uimm6_ator (uint32 *valp, uint32 pc)
   2322 {
   2323   *valp -= pc;
   2324   return 0;
   2325 }
   2326 
   2327 static int
   2328 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
   2329 {
   2330   *valp += pc;
   2331   return 0;
   2332 }
   2333 
   2334 static int
   2335 Operand_label8_ator (uint32 *valp, uint32 pc)
   2336 {
   2337   *valp -= pc;
   2338   return 0;
   2339 }
   2340 
   2341 static int
   2342 Operand_label8_rtoa (uint32 *valp, uint32 pc)
   2343 {
   2344   *valp += pc;
   2345   return 0;
   2346 }
   2347 
   2348 static int
   2349 Operand_label12_ator (uint32 *valp, uint32 pc)
   2350 {
   2351   *valp -= pc;
   2352   return 0;
   2353 }
   2354 
   2355 static int
   2356 Operand_label12_rtoa (uint32 *valp, uint32 pc)
   2357 {
   2358   *valp += pc;
   2359   return 0;
   2360 }
   2361 
   2362 static int
   2363 Operand_soffset_ator (uint32 *valp, uint32 pc)
   2364 {
   2365   *valp -= pc;
   2366   return 0;
   2367 }
   2368 
   2369 static int
   2370 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
   2371 {
   2372   *valp += pc;
   2373   return 0;
   2374 }
   2375 
   2376 static int
   2377 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
   2378 {
   2379   *valp -= ((pc + 3) & ~0x3);
   2380   return 0;
   2381 }
   2382 
   2383 static int
   2384 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
   2385 {
   2386   *valp += ((pc + 3) & ~0x3);
   2387   return 0;
   2388 }
   2389 
   2390 static int
   2391 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
   2392 {
   2393   *valp -= pc;
   2394   return 0;
   2395 }
   2396 
   2397 static int
   2398 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
   2399 {
   2400   *valp += pc;
   2401   return 0;
   2402 }
   2403 
   2404 static int
   2405 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
   2406 {
   2407   *valp -= pc;
   2408   return 0;
   2409 }
   2410 
   2411 static int
   2412 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
   2413 {
   2414   *valp += pc;
   2415   return 0;
   2416 }
   2417 
   2418 static xtensa_operand_internal operands[] = {
   2419   { "soffsetx4", FIELD_offset, -1, 0,
   2420     XTENSA_OPERAND_IS_PCRELATIVE,
   2421     OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
   2422     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
   2423   { "uimm12x8", FIELD_imm12, -1, 0,
   2424     0,
   2425     OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
   2426     0, 0 },
   2427   { "simm4", FIELD_mn, -1, 0,
   2428     0,
   2429     OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
   2430     0, 0 },
   2431   { "arr", FIELD_r, REGFILE_AR, 1,
   2432     XTENSA_OPERAND_IS_REGISTER,
   2433     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   2434     0, 0 },
   2435   { "ars", FIELD_s, REGFILE_AR, 1,
   2436     XTENSA_OPERAND_IS_REGISTER,
   2437     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   2438     0, 0 },
   2439   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
   2440     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2441     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   2442     0, 0 },
   2443   { "art", FIELD_t, REGFILE_AR, 1,
   2444     XTENSA_OPERAND_IS_REGISTER,
   2445     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   2446     0, 0 },
   2447   { "ar0", FIELD__ar0, REGFILE_AR, 1,
   2448     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2449     OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
   2450     0, 0 },
   2451   { "ar4", FIELD__ar4, REGFILE_AR, 1,
   2452     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2453     OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
   2454     0, 0 },
   2455   { "ar8", FIELD__ar8, REGFILE_AR, 1,
   2456     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2457     OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
   2458     0, 0 },
   2459   { "ar12", FIELD__ar12, REGFILE_AR, 1,
   2460     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2461     OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
   2462     0, 0 },
   2463   { "ars_entry", FIELD_s, REGFILE_AR, 1,
   2464     XTENSA_OPERAND_IS_REGISTER,
   2465     OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
   2466     0, 0 },
   2467   { "immrx4", FIELD_r, -1, 0,
   2468     0,
   2469     OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
   2470     0, 0 },
   2471   { "lsi4x4", FIELD_r, -1, 0,
   2472     0,
   2473     OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
   2474     0, 0 },
   2475   { "simm7", FIELD_imm7, -1, 0,
   2476     0,
   2477     OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
   2478     0, 0 },
   2479   { "uimm6", FIELD_imm6, -1, 0,
   2480     XTENSA_OPERAND_IS_PCRELATIVE,
   2481     OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
   2482     Operand_uimm6_ator, Operand_uimm6_rtoa },
   2483   { "ai4const", FIELD_t, -1, 0,
   2484     0,
   2485     OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
   2486     0, 0 },
   2487   { "b4const", FIELD_r, -1, 0,
   2488     0,
   2489     OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
   2490     0, 0 },
   2491   { "b4constu", FIELD_r, -1, 0,
   2492     0,
   2493     OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
   2494     0, 0 },
   2495   { "uimm8", FIELD_imm8, -1, 0,
   2496     0,
   2497     OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
   2498     0, 0 },
   2499   { "uimm8x2", FIELD_imm8, -1, 0,
   2500     0,
   2501     OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
   2502     0, 0 },
   2503   { "uimm8x4", FIELD_imm8, -1, 0,
   2504     0,
   2505     OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
   2506     0, 0 },
   2507   { "uimm4x16", FIELD_op2, -1, 0,
   2508     0,
   2509     OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
   2510     0, 0 },
   2511   { "uimmrx4", FIELD_r, -1, 0,
   2512     0,
   2513     OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
   2514     0, 0 },
   2515   { "simm8", FIELD_imm8, -1, 0,
   2516     0,
   2517     OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
   2518     0, 0 },
   2519   { "simm8x256", FIELD_imm8, -1, 0,
   2520     0,
   2521     OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
   2522     0, 0 },
   2523   { "simm12b", FIELD_imm12b, -1, 0,
   2524     0,
   2525     OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
   2526     0, 0 },
   2527   { "msalp32", FIELD_sal, -1, 0,
   2528     0,
   2529     OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
   2530     0, 0 },
   2531   { "op2p1", FIELD_op2, -1, 0,
   2532     0,
   2533     OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
   2534     0, 0 },
   2535   { "label8", FIELD_imm8, -1, 0,
   2536     XTENSA_OPERAND_IS_PCRELATIVE,
   2537     OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
   2538     Operand_label8_ator, Operand_label8_rtoa },
   2539   { "label12", FIELD_imm12, -1, 0,
   2540     XTENSA_OPERAND_IS_PCRELATIVE,
   2541     OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
   2542     Operand_label12_ator, Operand_label12_rtoa },
   2543   { "soffset", FIELD_offset, -1, 0,
   2544     XTENSA_OPERAND_IS_PCRELATIVE,
   2545     OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
   2546     Operand_soffset_ator, Operand_soffset_rtoa },
   2547   { "uimm16x4", FIELD_imm16, -1, 0,
   2548     XTENSA_OPERAND_IS_PCRELATIVE,
   2549     OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
   2550     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
   2551   { "bbi", FIELD_bbi, -1, 0,
   2552     0,
   2553     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   2554     0, 0 },
   2555   { "sae", FIELD_sae, -1, 0,
   2556     0,
   2557     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   2558     0, 0 },
   2559   { "sas", FIELD_sas, -1, 0,
   2560     0,
   2561     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   2562     0, 0 },
   2563   { "sargt", FIELD_sargt, -1, 0,
   2564     0,
   2565     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   2566     0, 0 },
   2567   { "s", FIELD_s, -1, 0,
   2568     0,
   2569     OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
   2570     0, 0 },
   2571   { "immt", FIELD_t, -1, 0,
   2572     0,
   2573     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
   2574     0, 0 },
   2575   { "imms", FIELD_s, -1, 0,
   2576     0,
   2577     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
   2578     0, 0 },
   2579   { "tp7", FIELD_t, -1, 0,
   2580     0,
   2581     OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
   2582     0, 0 },
   2583   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
   2584     XTENSA_OPERAND_IS_PCRELATIVE,
   2585     OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
   2586     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
   2587   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
   2588     XTENSA_OPERAND_IS_PCRELATIVE,
   2589     OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
   2590     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
   2591   { "bitindex", FIELD_bitindex, -1, 0,
   2592     0,
   2593     OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
   2594     0, 0 },
   2595   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
   2596   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
   2597   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
   2598   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
   2599   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
   2600   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
   2601   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
   2602   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
   2603   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
   2604   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
   2605   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
   2606   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
   2607   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
   2608   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
   2609   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
   2610   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
   2611   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
   2612   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
   2613   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
   2614   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
   2615   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
   2616   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
   2617   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
   2618   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
   2619   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
   2620   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
   2621   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
   2622   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
   2623   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
   2624   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
   2625   { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
   2626   { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
   2627   { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
   2628 };
   2629 
   2630 enum xtensa_operand_id {
   2631   OPERAND_soffsetx4,
   2632   OPERAND_uimm12x8,
   2633   OPERAND_simm4,
   2634   OPERAND_arr,
   2635   OPERAND_ars,
   2636   OPERAND__ars_invisible,
   2637   OPERAND_art,
   2638   OPERAND_ar0,
   2639   OPERAND_ar4,
   2640   OPERAND_ar8,
   2641   OPERAND_ar12,
   2642   OPERAND_ars_entry,
   2643   OPERAND_immrx4,
   2644   OPERAND_lsi4x4,
   2645   OPERAND_simm7,
   2646   OPERAND_uimm6,
   2647   OPERAND_ai4const,
   2648   OPERAND_b4const,
   2649   OPERAND_b4constu,
   2650   OPERAND_uimm8,
   2651   OPERAND_uimm8x2,
   2652   OPERAND_uimm8x4,
   2653   OPERAND_uimm4x16,
   2654   OPERAND_uimmrx4,
   2655   OPERAND_simm8,
   2656   OPERAND_simm8x256,
   2657   OPERAND_simm12b,
   2658   OPERAND_msalp32,
   2659   OPERAND_op2p1,
   2660   OPERAND_label8,
   2661   OPERAND_label12,
   2662   OPERAND_soffset,
   2663   OPERAND_uimm16x4,
   2664   OPERAND_bbi,
   2665   OPERAND_sae,
   2666   OPERAND_sas,
   2667   OPERAND_sargt,
   2668   OPERAND_s,
   2669   OPERAND_immt,
   2670   OPERAND_imms,
   2671   OPERAND_tp7,
   2672   OPERAND_xt_wbr15_label,
   2673   OPERAND_xt_wbr18_label,
   2674   OPERAND_bitindex,
   2675   OPERAND_t,
   2676   OPERAND_bbi4,
   2677   OPERAND_imm12,
   2678   OPERAND_imm8,
   2679   OPERAND_imm12b,
   2680   OPERAND_imm16,
   2681   OPERAND_m,
   2682   OPERAND_n,
   2683   OPERAND_offset,
   2684   OPERAND_op0,
   2685   OPERAND_op1,
   2686   OPERAND_op2,
   2687   OPERAND_r,
   2688   OPERAND_sa4,
   2689   OPERAND_sae4,
   2690   OPERAND_sal,
   2691   OPERAND_sas4,
   2692   OPERAND_sr,
   2693   OPERAND_st,
   2694   OPERAND_thi3,
   2695   OPERAND_imm4,
   2696   OPERAND_mn,
   2697   OPERAND_i,
   2698   OPERAND_imm6lo,
   2699   OPERAND_imm6hi,
   2700   OPERAND_imm7lo,
   2701   OPERAND_imm7hi,
   2702   OPERAND_z,
   2703   OPERAND_imm6,
   2704   OPERAND_imm7,
   2705   OPERAND_xt_wbr15_imm,
   2706   OPERAND_xt_wbr18_imm,
   2707   OPERAND_s3to1
   2708 };
   2709 
   2710 
   2711 /* Iclass table.  */
   2712 
   2713 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
   2714   { { STATE_PSEXCM }, 'o' },
   2715   { { STATE_EPC1 }, 'i' }
   2716 };
   2717 
   2718 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
   2719   { { STATE_DEPC }, 'i' }
   2720 };
   2721 
   2722 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
   2723   { { OPERAND_soffsetx4 }, 'i' },
   2724   { { OPERAND_ar12 }, 'o' }
   2725 };
   2726 
   2727 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
   2728   { { STATE_PSCALLINC }, 'o' }
   2729 };
   2730 
   2731 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
   2732   { { OPERAND_soffsetx4 }, 'i' },
   2733   { { OPERAND_ar8 }, 'o' }
   2734 };
   2735 
   2736 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
   2737   { { STATE_PSCALLINC }, 'o' }
   2738 };
   2739 
   2740 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
   2741   { { OPERAND_soffsetx4 }, 'i' },
   2742   { { OPERAND_ar4 }, 'o' }
   2743 };
   2744 
   2745 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
   2746   { { STATE_PSCALLINC }, 'o' }
   2747 };
   2748 
   2749 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
   2750   { { OPERAND_ars }, 'i' },
   2751   { { OPERAND_ar12 }, 'o' }
   2752 };
   2753 
   2754 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
   2755   { { STATE_PSCALLINC }, 'o' }
   2756 };
   2757 
   2758 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
   2759   { { OPERAND_ars }, 'i' },
   2760   { { OPERAND_ar8 }, 'o' }
   2761 };
   2762 
   2763 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
   2764   { { STATE_PSCALLINC }, 'o' }
   2765 };
   2766 
   2767 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
   2768   { { OPERAND_ars }, 'i' },
   2769   { { OPERAND_ar4 }, 'o' }
   2770 };
   2771 
   2772 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
   2773   { { STATE_PSCALLINC }, 'o' }
   2774 };
   2775 
   2776 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
   2777   { { OPERAND_ars_entry }, 's' },
   2778   { { OPERAND_ars }, 'i' },
   2779   { { OPERAND_uimm12x8 }, 'i' }
   2780 };
   2781 
   2782 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
   2783   { { STATE_PSCALLINC }, 'i' },
   2784   { { STATE_PSEXCM }, 'i' },
   2785   { { STATE_PSWOE }, 'i' },
   2786   { { STATE_WindowBase }, 'm' },
   2787   { { STATE_WindowStart }, 'm' }
   2788 };
   2789 
   2790 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
   2791   { { OPERAND_art }, 'o' },
   2792   { { OPERAND_ars }, 'i' }
   2793 };
   2794 
   2795 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
   2796   { { STATE_WindowBase }, 'i' },
   2797   { { STATE_WindowStart }, 'i' }
   2798 };
   2799 
   2800 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
   2801   { { OPERAND_simm4 }, 'i' }
   2802 };
   2803 
   2804 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
   2805   { { STATE_WindowBase }, 'm' }
   2806 };
   2807 
   2808 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
   2809   { { OPERAND__ars_invisible }, 'i' }
   2810 };
   2811 
   2812 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
   2813   { { STATE_WindowBase }, 'm' },
   2814   { { STATE_WindowStart }, 'm' },
   2815   { { STATE_PSCALLINC }, 'o' },
   2816   { { STATE_PSEXCM }, 'i' },
   2817   { { STATE_PSWOE }, 'i' }
   2818 };
   2819 
   2820 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
   2821   { { STATE_EPC1 }, 'i' },
   2822   { { STATE_PSEXCM }, 'o' },
   2823   { { STATE_WindowBase }, 'm' },
   2824   { { STATE_WindowStart }, 'm' },
   2825   { { STATE_PSOWB }, 'i' }
   2826 };
   2827 
   2828 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
   2829   { { OPERAND_art }, 'o' },
   2830   { { OPERAND_ars }, 'i' },
   2831   { { OPERAND_immrx4 }, 'i' }
   2832 };
   2833 
   2834 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
   2835   { { OPERAND_art }, 'i' },
   2836   { { OPERAND_ars }, 'i' },
   2837   { { OPERAND_immrx4 }, 'i' }
   2838 };
   2839 
   2840 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
   2841   { { OPERAND_art }, 'o' }
   2842 };
   2843 
   2844 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
   2845   { { STATE_WindowBase }, 'i' }
   2846 };
   2847 
   2848 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
   2849   { { OPERAND_art }, 'i' }
   2850 };
   2851 
   2852 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
   2853   { { STATE_WindowBase }, 'o' }
   2854 };
   2855 
   2856 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
   2857   { { OPERAND_art }, 'm' }
   2858 };
   2859 
   2860 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
   2861   { { STATE_WindowBase }, 'm' }
   2862 };
   2863 
   2864 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
   2865   { { OPERAND_art }, 'o' }
   2866 };
   2867 
   2868 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
   2869   { { STATE_WindowStart }, 'i' }
   2870 };
   2871 
   2872 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
   2873   { { OPERAND_art }, 'i' }
   2874 };
   2875 
   2876 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
   2877   { { STATE_WindowStart }, 'o' }
   2878 };
   2879 
   2880 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
   2881   { { OPERAND_art }, 'm' }
   2882 };
   2883 
   2884 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
   2885   { { STATE_WindowStart }, 'm' }
   2886 };
   2887 
   2888 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
   2889   { { OPERAND_arr }, 'o' },
   2890   { { OPERAND_ars }, 'i' },
   2891   { { OPERAND_art }, 'i' }
   2892 };
   2893 
   2894 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
   2895   { { OPERAND_arr }, 'o' },
   2896   { { OPERAND_ars }, 'i' },
   2897   { { OPERAND_ai4const }, 'i' }
   2898 };
   2899 
   2900 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
   2901   { { OPERAND_ars }, 'i' },
   2902   { { OPERAND_uimm6 }, 'i' }
   2903 };
   2904 
   2905 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
   2906   { { OPERAND_art }, 'o' },
   2907   { { OPERAND_ars }, 'i' },
   2908   { { OPERAND_lsi4x4 }, 'i' }
   2909 };
   2910 
   2911 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
   2912   { { OPERAND_art }, 'o' },
   2913   { { OPERAND_ars }, 'i' }
   2914 };
   2915 
   2916 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
   2917   { { OPERAND_ars }, 'o' },
   2918   { { OPERAND_simm7 }, 'i' }
   2919 };
   2920 
   2921 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
   2922   { { OPERAND__ars_invisible }, 'i' }
   2923 };
   2924 
   2925 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
   2926   { { OPERAND_art }, 'i' },
   2927   { { OPERAND_ars }, 'i' },
   2928   { { OPERAND_lsi4x4 }, 'i' }
   2929 };
   2930 
   2931 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
   2932   { { OPERAND_art }, 'o' },
   2933   { { OPERAND_ars }, 'i' },
   2934   { { OPERAND_simm8 }, 'i' }
   2935 };
   2936 
   2937 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
   2938   { { OPERAND_art }, 'o' },
   2939   { { OPERAND_ars }, 'i' },
   2940   { { OPERAND_simm8x256 }, 'i' }
   2941 };
   2942 
   2943 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
   2944   { { OPERAND_arr }, 'o' },
   2945   { { OPERAND_ars }, 'i' },
   2946   { { OPERAND_art }, 'i' }
   2947 };
   2948 
   2949 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
   2950   { { OPERAND_arr }, 'o' },
   2951   { { OPERAND_ars }, 'i' },
   2952   { { OPERAND_art }, 'i' }
   2953 };
   2954 
   2955 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
   2956   { { OPERAND_ars }, 'i' },
   2957   { { OPERAND_b4const }, 'i' },
   2958   { { OPERAND_label8 }, 'i' }
   2959 };
   2960 
   2961 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
   2962   { { OPERAND_ars }, 'i' },
   2963   { { OPERAND_bbi }, 'i' },
   2964   { { OPERAND_label8 }, 'i' }
   2965 };
   2966 
   2967 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
   2968   { { OPERAND_ars }, 'i' },
   2969   { { OPERAND_b4constu }, 'i' },
   2970   { { OPERAND_label8 }, 'i' }
   2971 };
   2972 
   2973 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
   2974   { { OPERAND_ars }, 'i' },
   2975   { { OPERAND_art }, 'i' },
   2976   { { OPERAND_label8 }, 'i' }
   2977 };
   2978 
   2979 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
   2980   { { OPERAND_ars }, 'i' },
   2981   { { OPERAND_label12 }, 'i' }
   2982 };
   2983 
   2984 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
   2985   { { OPERAND_soffsetx4 }, 'i' },
   2986   { { OPERAND_ar0 }, 'o' }
   2987 };
   2988 
   2989 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
   2990   { { OPERAND_ars }, 'i' },
   2991   { { OPERAND_ar0 }, 'o' }
   2992 };
   2993 
   2994 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
   2995   { { OPERAND_arr }, 'o' },
   2996   { { OPERAND_art }, 'i' },
   2997   { { OPERAND_sae }, 'i' },
   2998   { { OPERAND_op2p1 }, 'i' }
   2999 };
   3000 
   3001 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
   3002   { { OPERAND_soffset }, 'i' }
   3003 };
   3004 
   3005 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
   3006   { { OPERAND_ars }, 'i' }
   3007 };
   3008 
   3009 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
   3010   { { OPERAND_art }, 'o' },
   3011   { { OPERAND_ars }, 'i' },
   3012   { { OPERAND_uimm8x2 }, 'i' }
   3013 };
   3014 
   3015 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
   3016   { { OPERAND_art }, 'o' },
   3017   { { OPERAND_ars }, 'i' },
   3018   { { OPERAND_uimm8x2 }, 'i' }
   3019 };
   3020 
   3021 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
   3022   { { OPERAND_art }, 'o' },
   3023   { { OPERAND_ars }, 'i' },
   3024   { { OPERAND_uimm8x4 }, 'i' }
   3025 };
   3026 
   3027 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
   3028   { { OPERAND_art }, 'o' },
   3029   { { OPERAND_uimm16x4 }, 'i' }
   3030 };
   3031 
   3032 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
   3033   { { OPERAND_art }, 'o' },
   3034   { { OPERAND_ars }, 'i' },
   3035   { { OPERAND_uimm8 }, 'i' }
   3036 };
   3037 
   3038 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
   3039   { { OPERAND_art }, 'o' },
   3040   { { OPERAND_simm12b }, 'i' }
   3041 };
   3042 
   3043 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
   3044   { { OPERAND_arr }, 'm' },
   3045   { { OPERAND_ars }, 'i' },
   3046   { { OPERAND_art }, 'i' }
   3047 };
   3048 
   3049 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
   3050   { { OPERAND_arr }, 'o' },
   3051   { { OPERAND_art }, 'i' }
   3052 };
   3053 
   3054 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
   3055   { { OPERAND__ars_invisible }, 'i' }
   3056 };
   3057 
   3058 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
   3059   { { OPERAND_art }, 'i' },
   3060   { { OPERAND_ars }, 'i' },
   3061   { { OPERAND_uimm8x2 }, 'i' }
   3062 };
   3063 
   3064 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
   3065   { { OPERAND_art }, 'i' },
   3066   { { OPERAND_ars }, 'i' },
   3067   { { OPERAND_uimm8x4 }, 'i' }
   3068 };
   3069 
   3070 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
   3071   { { OPERAND_art }, 'i' },
   3072   { { OPERAND_ars }, 'i' },
   3073   { { OPERAND_uimmrx4 }, 'i' }
   3074 };
   3075 
   3076 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
   3077   { { OPERAND_art }, 'i' },
   3078   { { OPERAND_ars }, 'i' },
   3079   { { OPERAND_uimm8 }, 'i' }
   3080 };
   3081 
   3082 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
   3083   { { OPERAND_ars }, 'i' }
   3084 };
   3085 
   3086 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
   3087   { { STATE_SAR }, 'o' }
   3088 };
   3089 
   3090 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
   3091   { { OPERAND_sas }, 'i' }
   3092 };
   3093 
   3094 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
   3095   { { STATE_SAR }, 'o' }
   3096 };
   3097 
   3098 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
   3099   { { OPERAND_arr }, 'o' },
   3100   { { OPERAND_ars }, 'i' }
   3101 };
   3102 
   3103 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
   3104   { { STATE_SAR }, 'i' }
   3105 };
   3106 
   3107 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
   3108   { { OPERAND_arr }, 'o' },
   3109   { { OPERAND_ars }, 'i' },
   3110   { { OPERAND_art }, 'i' }
   3111 };
   3112 
   3113 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
   3114   { { STATE_SAR }, 'i' }
   3115 };
   3116 
   3117 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
   3118   { { OPERAND_arr }, 'o' },
   3119   { { OPERAND_art }, 'i' }
   3120 };
   3121 
   3122 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
   3123   { { STATE_SAR }, 'i' }
   3124 };
   3125 
   3126 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
   3127   { { OPERAND_arr }, 'o' },
   3128   { { OPERAND_ars }, 'i' },
   3129   { { OPERAND_msalp32 }, 'i' }
   3130 };
   3131 
   3132 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
   3133   { { OPERAND_arr }, 'o' },
   3134   { { OPERAND_art }, 'i' },
   3135   { { OPERAND_sargt }, 'i' }
   3136 };
   3137 
   3138 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
   3139   { { OPERAND_arr }, 'o' },
   3140   { { OPERAND_art }, 'i' },
   3141   { { OPERAND_s }, 'i' }
   3142 };
   3143 
   3144 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
   3145   { { STATE_XTSYNC }, 'i' }
   3146 };
   3147 
   3148 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
   3149   { { OPERAND_art }, 'o' },
   3150   { { OPERAND_s }, 'i' }
   3151 };
   3152 
   3153 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
   3154   { { STATE_PSWOE }, 'i' },
   3155   { { STATE_PSCALLINC }, 'i' },
   3156   { { STATE_PSOWB }, 'i' },
   3157   { { STATE_PSUM }, 'i' },
   3158   { { STATE_PSEXCM }, 'i' },
   3159   { { STATE_PSINTLEVEL }, 'm' }
   3160 };
   3161 
   3162 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
   3163   { { OPERAND_art }, 'o' }
   3164 };
   3165 
   3166 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
   3167   { { STATE_SAR }, 'i' }
   3168 };
   3169 
   3170 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
   3171   { { OPERAND_art }, 'i' }
   3172 };
   3173 
   3174 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
   3175   { { STATE_SAR }, 'o' },
   3176   { { STATE_XTSYNC }, 'o' }
   3177 };
   3178 
   3179 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
   3180   { { OPERAND_art }, 'm' }
   3181 };
   3182 
   3183 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
   3184   { { STATE_SAR }, 'm' }
   3185 };
   3186 
   3187 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
   3188   { { OPERAND_art }, 'o' }
   3189 };
   3190 
   3191 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
   3192   { { OPERAND_art }, 'i' }
   3193 };
   3194 
   3195 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
   3196   { { OPERAND_art }, 'm' }
   3197 };
   3198 
   3199 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
   3200   { { OPERAND_art }, 'o' }
   3201 };
   3202 
   3203 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
   3204   { { OPERAND_art }, 'i' }
   3205 };
   3206 
   3207 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
   3208   { { OPERAND_art }, 'm' }
   3209 };
   3210 
   3211 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
   3212   { { OPERAND_art }, 'o' }
   3213 };
   3214 
   3215 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
   3216   { { OPERAND_art }, 'i' }
   3217 };
   3218 
   3219 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
   3220   { { OPERAND_art }, 'o' }
   3221 };
   3222 
   3223 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
   3224   { { OPERAND_art }, 'o' }
   3225 };
   3226 
   3227 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
   3228   { { STATE_PSWOE }, 'i' },
   3229   { { STATE_PSCALLINC }, 'i' },
   3230   { { STATE_PSOWB }, 'i' },
   3231   { { STATE_PSUM }, 'i' },
   3232   { { STATE_PSEXCM }, 'i' },
   3233   { { STATE_PSINTLEVEL }, 'i' }
   3234 };
   3235 
   3236 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
   3237   { { OPERAND_art }, 'i' }
   3238 };
   3239 
   3240 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
   3241   { { STATE_PSWOE }, 'o' },
   3242   { { STATE_PSCALLINC }, 'o' },
   3243   { { STATE_PSOWB }, 'o' },
   3244   { { STATE_PSUM }, 'o' },
   3245   { { STATE_PSEXCM }, 'o' },
   3246   { { STATE_PSINTLEVEL }, 'o' }
   3247 };
   3248 
   3249 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
   3250   { { OPERAND_art }, 'm' }
   3251 };
   3252 
   3253 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
   3254   { { STATE_PSWOE }, 'm' },
   3255   { { STATE_PSCALLINC }, 'm' },
   3256   { { STATE_PSOWB }, 'm' },
   3257   { { STATE_PSUM }, 'm' },
   3258   { { STATE_PSEXCM }, 'm' },
   3259   { { STATE_PSINTLEVEL }, 'm' }
   3260 };
   3261 
   3262 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
   3263   { { OPERAND_art }, 'o' }
   3264 };
   3265 
   3266 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
   3267   { { STATE_EPC1 }, 'i' }
   3268 };
   3269 
   3270 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
   3271   { { OPERAND_art }, 'i' }
   3272 };
   3273 
   3274 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
   3275   { { STATE_EPC1 }, 'o' }
   3276 };
   3277 
   3278 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
   3279   { { OPERAND_art }, 'm' }
   3280 };
   3281 
   3282 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
   3283   { { STATE_EPC1 }, 'm' }
   3284 };
   3285 
   3286 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
   3287   { { OPERAND_art }, 'o' }
   3288 };
   3289 
   3290 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
   3291   { { STATE_EXCSAVE1 }, 'i' }
   3292 };
   3293 
   3294 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
   3295   { { OPERAND_art }, 'i' }
   3296 };
   3297 
   3298 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
   3299   { { STATE_EXCSAVE1 }, 'o' }
   3300 };
   3301 
   3302 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
   3303   { { OPERAND_art }, 'm' }
   3304 };
   3305 
   3306 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
   3307   { { STATE_EXCSAVE1 }, 'm' }
   3308 };
   3309 
   3310 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
   3311   { { OPERAND_art }, 'o' }
   3312 };
   3313 
   3314 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
   3315   { { STATE_EPC2 }, 'i' }
   3316 };
   3317 
   3318 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
   3319   { { OPERAND_art }, 'i' }
   3320 };
   3321 
   3322 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
   3323   { { STATE_EPC2 }, 'o' }
   3324 };
   3325 
   3326 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
   3327   { { OPERAND_art }, 'm' }
   3328 };
   3329 
   3330 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
   3331   { { STATE_EPC2 }, 'm' }
   3332 };
   3333 
   3334 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
   3335   { { OPERAND_art }, 'o' }
   3336 };
   3337 
   3338 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
   3339   { { STATE_EXCSAVE2 }, 'i' }
   3340 };
   3341 
   3342 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
   3343   { { OPERAND_art }, 'i' }
   3344 };
   3345 
   3346 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
   3347   { { STATE_EXCSAVE2 }, 'o' }
   3348 };
   3349 
   3350 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
   3351   { { OPERAND_art }, 'm' }
   3352 };
   3353 
   3354 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
   3355   { { STATE_EXCSAVE2 }, 'm' }
   3356 };
   3357 
   3358 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
   3359   { { OPERAND_art }, 'o' }
   3360 };
   3361 
   3362 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
   3363   { { STATE_EPC3 }, 'i' }
   3364 };
   3365 
   3366 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
   3367   { { OPERAND_art }, 'i' }
   3368 };
   3369 
   3370 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
   3371   { { STATE_EPC3 }, 'o' }
   3372 };
   3373 
   3374 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
   3375   { { OPERAND_art }, 'm' }
   3376 };
   3377 
   3378 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
   3379   { { STATE_EPC3 }, 'm' }
   3380 };
   3381 
   3382 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
   3383   { { OPERAND_art }, 'o' }
   3384 };
   3385 
   3386 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
   3387   { { STATE_EXCSAVE3 }, 'i' }
   3388 };
   3389 
   3390 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
   3391   { { OPERAND_art }, 'i' }
   3392 };
   3393 
   3394 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
   3395   { { STATE_EXCSAVE3 }, 'o' }
   3396 };
   3397 
   3398 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
   3399   { { OPERAND_art }, 'm' }
   3400 };
   3401 
   3402 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
   3403   { { STATE_EXCSAVE3 }, 'm' }
   3404 };
   3405 
   3406 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
   3407   { { OPERAND_art }, 'o' }
   3408 };
   3409 
   3410 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
   3411   { { STATE_EPC4 }, 'i' }
   3412 };
   3413 
   3414 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
   3415   { { OPERAND_art }, 'i' }
   3416 };
   3417 
   3418 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
   3419   { { STATE_EPC4 }, 'o' }
   3420 };
   3421 
   3422 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
   3423   { { OPERAND_art }, 'm' }
   3424 };
   3425 
   3426 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
   3427   { { STATE_EPC4 }, 'm' }
   3428 };
   3429 
   3430 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
   3431   { { OPERAND_art }, 'o' }
   3432 };
   3433 
   3434 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
   3435   { { STATE_EXCSAVE4 }, 'i' }
   3436 };
   3437 
   3438 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
   3439   { { OPERAND_art }, 'i' }
   3440 };
   3441 
   3442 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
   3443   { { STATE_EXCSAVE4 }, 'o' }
   3444 };
   3445 
   3446 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
   3447   { { OPERAND_art }, 'm' }
   3448 };
   3449 
   3450 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
   3451   { { STATE_EXCSAVE4 }, 'm' }
   3452 };
   3453 
   3454 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
   3455   { { OPERAND_art }, 'o' }
   3456 };
   3457 
   3458 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
   3459   { { STATE_EPC5 }, 'i' }
   3460 };
   3461 
   3462 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
   3463   { { OPERAND_art }, 'i' }
   3464 };
   3465 
   3466 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
   3467   { { STATE_EPC5 }, 'o' }
   3468 };
   3469 
   3470 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
   3471   { { OPERAND_art }, 'm' }
   3472 };
   3473 
   3474 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
   3475   { { STATE_EPC5 }, 'm' }
   3476 };
   3477 
   3478 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
   3479   { { OPERAND_art }, 'o' }
   3480 };
   3481 
   3482 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
   3483   { { STATE_EXCSAVE5 }, 'i' }
   3484 };
   3485 
   3486 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
   3487   { { OPERAND_art }, 'i' }
   3488 };
   3489 
   3490 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
   3491   { { STATE_EXCSAVE5 }, 'o' }
   3492 };
   3493 
   3494 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
   3495   { { OPERAND_art }, 'm' }
   3496 };
   3497 
   3498 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
   3499   { { STATE_EXCSAVE5 }, 'm' }
   3500 };
   3501 
   3502 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
   3503   { { OPERAND_art }, 'o' }
   3504 };
   3505 
   3506 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
   3507   { { STATE_EPC6 }, 'i' }
   3508 };
   3509 
   3510 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
   3511   { { OPERAND_art }, 'i' }
   3512 };
   3513 
   3514 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
   3515   { { STATE_EPC6 }, 'o' }
   3516 };
   3517 
   3518 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
   3519   { { OPERAND_art }, 'm' }
   3520 };
   3521 
   3522 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
   3523   { { STATE_EPC6 }, 'm' }
   3524 };
   3525 
   3526 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
   3527   { { OPERAND_art }, 'o' }
   3528 };
   3529 
   3530 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
   3531   { { STATE_EXCSAVE6 }, 'i' }
   3532 };
   3533 
   3534 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
   3535   { { OPERAND_art }, 'i' }
   3536 };
   3537 
   3538 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
   3539   { { STATE_EXCSAVE6 }, 'o' }
   3540 };
   3541 
   3542 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
   3543   { { OPERAND_art }, 'm' }
   3544 };
   3545 
   3546 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
   3547   { { STATE_EXCSAVE6 }, 'm' }
   3548 };
   3549 
   3550 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
   3551   { { OPERAND_art }, 'o' }
   3552 };
   3553 
   3554 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
   3555   { { STATE_EPC7 }, 'i' }
   3556 };
   3557 
   3558 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
   3559   { { OPERAND_art }, 'i' }
   3560 };
   3561 
   3562 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
   3563   { { STATE_EPC7 }, 'o' }
   3564 };
   3565 
   3566 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
   3567   { { OPERAND_art }, 'm' }
   3568 };
   3569 
   3570 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
   3571   { { STATE_EPC7 }, 'm' }
   3572 };
   3573 
   3574 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
   3575   { { OPERAND_art }, 'o' }
   3576 };
   3577 
   3578 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
   3579   { { STATE_EXCSAVE7 }, 'i' }
   3580 };
   3581 
   3582 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
   3583   { { OPERAND_art }, 'i' }
   3584 };
   3585 
   3586 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
   3587   { { STATE_EXCSAVE7 }, 'o' }
   3588 };
   3589 
   3590 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
   3591   { { OPERAND_art }, 'm' }
   3592 };
   3593 
   3594 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
   3595   { { STATE_EXCSAVE7 }, 'm' }
   3596 };
   3597 
   3598 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
   3599   { { OPERAND_art }, 'o' }
   3600 };
   3601 
   3602 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
   3603   { { STATE_EPS2 }, 'i' }
   3604 };
   3605 
   3606 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
   3607   { { OPERAND_art }, 'i' }
   3608 };
   3609 
   3610 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
   3611   { { STATE_EPS2 }, 'o' }
   3612 };
   3613 
   3614 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
   3615   { { OPERAND_art }, 'm' }
   3616 };
   3617 
   3618 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
   3619   { { STATE_EPS2 }, 'm' }
   3620 };
   3621 
   3622 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
   3623   { { OPERAND_art }, 'o' }
   3624 };
   3625 
   3626 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
   3627   { { STATE_EPS3 }, 'i' }
   3628 };
   3629 
   3630 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
   3631   { { OPERAND_art }, 'i' }
   3632 };
   3633 
   3634 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
   3635   { { STATE_EPS3 }, 'o' }
   3636 };
   3637 
   3638 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
   3639   { { OPERAND_art }, 'm' }
   3640 };
   3641 
   3642 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
   3643   { { STATE_EPS3 }, 'm' }
   3644 };
   3645 
   3646 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
   3647   { { OPERAND_art }, 'o' }
   3648 };
   3649 
   3650 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
   3651   { { STATE_EPS4 }, 'i' }
   3652 };
   3653 
   3654 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
   3655   { { OPERAND_art }, 'i' }
   3656 };
   3657 
   3658 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
   3659   { { STATE_EPS4 }, 'o' }
   3660 };
   3661 
   3662 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
   3663   { { OPERAND_art }, 'm' }
   3664 };
   3665 
   3666 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
   3667   { { STATE_EPS4 }, 'm' }
   3668 };
   3669 
   3670 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
   3671   { { OPERAND_art }, 'o' }
   3672 };
   3673 
   3674 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
   3675   { { STATE_EPS5 }, 'i' }
   3676 };
   3677 
   3678 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
   3679   { { OPERAND_art }, 'i' }
   3680 };
   3681 
   3682 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
   3683   { { STATE_EPS5 }, 'o' }
   3684 };
   3685 
   3686 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
   3687   { { OPERAND_art }, 'm' }
   3688 };
   3689 
   3690 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
   3691   { { STATE_EPS5 }, 'm' }
   3692 };
   3693 
   3694 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
   3695   { { OPERAND_art }, 'o' }
   3696 };
   3697 
   3698 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
   3699   { { STATE_EPS6 }, 'i' }
   3700 };
   3701 
   3702 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
   3703   { { OPERAND_art }, 'i' }
   3704 };
   3705 
   3706 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
   3707   { { STATE_EPS6 }, 'o' }
   3708 };
   3709 
   3710 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
   3711   { { OPERAND_art }, 'm' }
   3712 };
   3713 
   3714 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
   3715   { { STATE_EPS6 }, 'm' }
   3716 };
   3717 
   3718 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
   3719   { { OPERAND_art }, 'o' }
   3720 };
   3721 
   3722 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
   3723   { { STATE_EPS7 }, 'i' }
   3724 };
   3725 
   3726 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
   3727   { { OPERAND_art }, 'i' }
   3728 };
   3729 
   3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
   3731   { { STATE_EPS7 }, 'o' }
   3732 };
   3733 
   3734 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
   3735   { { OPERAND_art }, 'm' }
   3736 };
   3737 
   3738 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
   3739   { { STATE_EPS7 }, 'm' }
   3740 };
   3741 
   3742 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
   3743   { { OPERAND_art }, 'o' }
   3744 };
   3745 
   3746 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
   3747   { { STATE_EXCVADDR }, 'i' }
   3748 };
   3749 
   3750 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
   3751   { { OPERAND_art }, 'i' }
   3752 };
   3753 
   3754 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
   3755   { { STATE_EXCVADDR }, 'o' }
   3756 };
   3757 
   3758 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
   3759   { { OPERAND_art }, 'm' }
   3760 };
   3761 
   3762 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
   3763   { { STATE_EXCVADDR }, 'm' }
   3764 };
   3765 
   3766 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
   3767   { { OPERAND_art }, 'o' }
   3768 };
   3769 
   3770 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
   3771   { { STATE_DEPC }, 'i' }
   3772 };
   3773 
   3774 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
   3775   { { OPERAND_art }, 'i' }
   3776 };
   3777 
   3778 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
   3779   { { STATE_DEPC }, 'o' }
   3780 };
   3781 
   3782 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
   3783   { { OPERAND_art }, 'm' }
   3784 };
   3785 
   3786 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
   3787   { { STATE_DEPC }, 'm' }
   3788 };
   3789 
   3790 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
   3791   { { OPERAND_art }, 'o' }
   3792 };
   3793 
   3794 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
   3795   { { STATE_EXCCAUSE }, 'i' },
   3796   { { STATE_XTSYNC }, 'i' }
   3797 };
   3798 
   3799 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
   3800   { { OPERAND_art }, 'i' }
   3801 };
   3802 
   3803 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
   3804   { { STATE_EXCCAUSE }, 'o' }
   3805 };
   3806 
   3807 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
   3808   { { OPERAND_art }, 'm' }
   3809 };
   3810 
   3811 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
   3812   { { STATE_EXCCAUSE }, 'm' }
   3813 };
   3814 
   3815 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
   3816   { { OPERAND_art }, 'o' }
   3817 };
   3818 
   3819 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
   3820   { { STATE_MISC0 }, 'i' }
   3821 };
   3822 
   3823 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
   3824   { { OPERAND_art }, 'i' }
   3825 };
   3826 
   3827 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
   3828   { { STATE_MISC0 }, 'o' }
   3829 };
   3830 
   3831 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
   3832   { { OPERAND_art }, 'm' }
   3833 };
   3834 
   3835 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
   3836   { { STATE_MISC0 }, 'm' }
   3837 };
   3838 
   3839 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
   3840   { { OPERAND_art }, 'o' }
   3841 };
   3842 
   3843 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
   3844   { { STATE_MISC1 }, 'i' }
   3845 };
   3846 
   3847 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
   3848   { { OPERAND_art }, 'i' }
   3849 };
   3850 
   3851 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
   3852   { { STATE_MISC1 }, 'o' }
   3853 };
   3854 
   3855 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
   3856   { { OPERAND_art }, 'm' }
   3857 };
   3858 
   3859 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
   3860   { { STATE_MISC1 }, 'm' }
   3861 };
   3862 
   3863 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
   3864   { { OPERAND_art }, 'o' }
   3865 };
   3866 
   3867 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
   3868   { { OPERAND_art }, 'o' }
   3869 };
   3870 
   3871 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
   3872   { { STATE_VECBASE }, 'i' }
   3873 };
   3874 
   3875 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
   3876   { { OPERAND_art }, 'i' }
   3877 };
   3878 
   3879 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
   3880   { { STATE_VECBASE }, 'o' }
   3881 };
   3882 
   3883 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
   3884   { { OPERAND_art }, 'm' }
   3885 };
   3886 
   3887 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
   3888   { { STATE_VECBASE }, 'm' }
   3889 };
   3890 
   3891 static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
   3892   { { OPERAND_arr }, 'o' },
   3893   { { OPERAND_ars }, 'i' },
   3894   { { OPERAND_art }, 'i' }
   3895 };
   3896 
   3897 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
   3898   { { OPERAND_arr }, 'o' },
   3899   { { OPERAND_ars }, 'i' },
   3900   { { OPERAND_art }, 'i' }
   3901 };
   3902 
   3903 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
   3904   { { OPERAND_arr }, 'o' },
   3905   { { OPERAND_ars }, 'i' },
   3906   { { OPERAND_art }, 'i' }
   3907 };
   3908 
   3909 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
   3910   { { OPERAND_s }, 'i' }
   3911 };
   3912 
   3913 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
   3914   { { STATE_PSWOE }, 'o' },
   3915   { { STATE_PSCALLINC }, 'o' },
   3916   { { STATE_PSOWB }, 'o' },
   3917   { { STATE_PSUM }, 'o' },
   3918   { { STATE_PSEXCM }, 'o' },
   3919   { { STATE_PSINTLEVEL }, 'o' },
   3920   { { STATE_EPC1 }, 'i' },
   3921   { { STATE_EPC2 }, 'i' },
   3922   { { STATE_EPC3 }, 'i' },
   3923   { { STATE_EPC4 }, 'i' },
   3924   { { STATE_EPC5 }, 'i' },
   3925   { { STATE_EPC6 }, 'i' },
   3926   { { STATE_EPC7 }, 'i' },
   3927   { { STATE_EPS2 }, 'i' },
   3928   { { STATE_EPS3 }, 'i' },
   3929   { { STATE_EPS4 }, 'i' },
   3930   { { STATE_EPS5 }, 'i' },
   3931   { { STATE_EPS6 }, 'i' },
   3932   { { STATE_EPS7 }, 'i' },
   3933   { { STATE_InOCDMode }, 'm' }
   3934 };
   3935 
   3936 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
   3937   { { OPERAND_s }, 'i' }
   3938 };
   3939 
   3940 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
   3941   { { STATE_PSINTLEVEL }, 'o' }
   3942 };
   3943 
   3944 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
   3945   { { OPERAND_art }, 'o' }
   3946 };
   3947 
   3948 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
   3949   { { STATE_INTERRUPT }, 'i' }
   3950 };
   3951 
   3952 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
   3953   { { OPERAND_art }, 'i' }
   3954 };
   3955 
   3956 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
   3957   { { STATE_XTSYNC }, 'o' },
   3958   { { STATE_INTERRUPT }, 'm' }
   3959 };
   3960 
   3961 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
   3962   { { OPERAND_art }, 'i' }
   3963 };
   3964 
   3965 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
   3966   { { STATE_XTSYNC }, 'o' },
   3967   { { STATE_INTERRUPT }, 'm' }
   3968 };
   3969 
   3970 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
   3971   { { OPERAND_art }, 'o' }
   3972 };
   3973 
   3974 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
   3975   { { STATE_INTENABLE }, 'i' }
   3976 };
   3977 
   3978 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
   3979   { { OPERAND_art }, 'i' }
   3980 };
   3981 
   3982 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
   3983   { { STATE_INTENABLE }, 'o' }
   3984 };
   3985 
   3986 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
   3987   { { OPERAND_art }, 'm' }
   3988 };
   3989 
   3990 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
   3991   { { STATE_INTENABLE }, 'm' }
   3992 };
   3993 
   3994 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
   3995   { { OPERAND_imms }, 'i' },
   3996   { { OPERAND_immt }, 'i' }
   3997 };
   3998 
   3999 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
   4000   { { STATE_PSEXCM }, 'i' },
   4001   { { STATE_PSINTLEVEL }, 'i' }
   4002 };
   4003 
   4004 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
   4005   { { OPERAND_imms }, 'i' }
   4006 };
   4007 
   4008 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
   4009   { { STATE_PSEXCM }, 'i' },
   4010   { { STATE_PSINTLEVEL }, 'i' }
   4011 };
   4012 
   4013 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
   4014   { { OPERAND_art }, 'o' }
   4015 };
   4016 
   4017 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
   4018   { { STATE_DBREAKA0 }, 'i' }
   4019 };
   4020 
   4021 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
   4022   { { OPERAND_art }, 'i' }
   4023 };
   4024 
   4025 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
   4026   { { STATE_DBREAKA0 }, 'o' },
   4027   { { STATE_XTSYNC }, 'o' }
   4028 };
   4029 
   4030 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
   4031   { { OPERAND_art }, 'm' }
   4032 };
   4033 
   4034 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
   4035   { { STATE_DBREAKA0 }, 'm' },
   4036   { { STATE_XTSYNC }, 'o' }
   4037 };
   4038 
   4039 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
   4040   { { OPERAND_art }, 'o' }
   4041 };
   4042 
   4043 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
   4044   { { STATE_DBREAKC0 }, 'i' }
   4045 };
   4046 
   4047 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
   4048   { { OPERAND_art }, 'i' }
   4049 };
   4050 
   4051 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
   4052   { { STATE_DBREAKC0 }, 'o' },
   4053   { { STATE_XTSYNC }, 'o' }
   4054 };
   4055 
   4056 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
   4057   { { OPERAND_art }, 'm' }
   4058 };
   4059 
   4060 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
   4061   { { STATE_DBREAKC0 }, 'm' },
   4062   { { STATE_XTSYNC }, 'o' }
   4063 };
   4064 
   4065 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
   4066   { { OPERAND_art }, 'o' }
   4067 };
   4068 
   4069 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
   4070   { { STATE_DBREAKA1 }, 'i' }
   4071 };
   4072 
   4073 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
   4074   { { OPERAND_art }, 'i' }
   4075 };
   4076 
   4077 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
   4078   { { STATE_DBREAKA1 }, 'o' },
   4079   { { STATE_XTSYNC }, 'o' }
   4080 };
   4081 
   4082 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
   4083   { { OPERAND_art }, 'm' }
   4084 };
   4085 
   4086 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
   4087   { { STATE_DBREAKA1 }, 'm' },
   4088   { { STATE_XTSYNC }, 'o' }
   4089 };
   4090 
   4091 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
   4092   { { OPERAND_art }, 'o' }
   4093 };
   4094 
   4095 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
   4096   { { STATE_DBREAKC1 }, 'i' }
   4097 };
   4098 
   4099 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
   4100   { { OPERAND_art }, 'i' }
   4101 };
   4102 
   4103 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
   4104   { { STATE_DBREAKC1 }, 'o' },
   4105   { { STATE_XTSYNC }, 'o' }
   4106 };
   4107 
   4108 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
   4109   { { OPERAND_art }, 'm' }
   4110 };
   4111 
   4112 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
   4113   { { STATE_DBREAKC1 }, 'm' },
   4114   { { STATE_XTSYNC }, 'o' }
   4115 };
   4116 
   4117 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
   4118   { { OPERAND_art }, 'o' }
   4119 };
   4120 
   4121 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
   4122   { { STATE_IBREAKA0 }, 'i' }
   4123 };
   4124 
   4125 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
   4126   { { OPERAND_art }, 'i' }
   4127 };
   4128 
   4129 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
   4130   { { STATE_IBREAKA0 }, 'o' }
   4131 };
   4132 
   4133 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
   4134   { { OPERAND_art }, 'm' }
   4135 };
   4136 
   4137 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
   4138   { { STATE_IBREAKA0 }, 'm' }
   4139 };
   4140 
   4141 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
   4142   { { OPERAND_art }, 'o' }
   4143 };
   4144 
   4145 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
   4146   { { STATE_IBREAKA1 }, 'i' }
   4147 };
   4148 
   4149 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
   4150   { { OPERAND_art }, 'i' }
   4151 };
   4152 
   4153 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
   4154   { { STATE_IBREAKA1 }, 'o' }
   4155 };
   4156 
   4157 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
   4158   { { OPERAND_art }, 'm' }
   4159 };
   4160 
   4161 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
   4162   { { STATE_IBREAKA1 }, 'm' }
   4163 };
   4164 
   4165 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
   4166   { { OPERAND_art }, 'o' }
   4167 };
   4168 
   4169 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
   4170   { { STATE_IBREAKENABLE }, 'i' }
   4171 };
   4172 
   4173 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
   4174   { { OPERAND_art }, 'i' }
   4175 };
   4176 
   4177 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
   4178   { { STATE_IBREAKENABLE }, 'o' }
   4179 };
   4180 
   4181 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
   4182   { { OPERAND_art }, 'm' }
   4183 };
   4184 
   4185 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
   4186   { { STATE_IBREAKENABLE }, 'm' }
   4187 };
   4188 
   4189 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
   4190   { { OPERAND_art }, 'o' }
   4191 };
   4192 
   4193 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
   4194   { { STATE_DEBUGCAUSE }, 'i' },
   4195   { { STATE_DBNUM }, 'i' }
   4196 };
   4197 
   4198 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
   4199   { { OPERAND_art }, 'i' }
   4200 };
   4201 
   4202 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
   4203   { { STATE_DEBUGCAUSE }, 'o' },
   4204   { { STATE_DBNUM }, 'o' }
   4205 };
   4206 
   4207 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
   4208   { { OPERAND_art }, 'm' }
   4209 };
   4210 
   4211 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
   4212   { { STATE_DEBUGCAUSE }, 'm' },
   4213   { { STATE_DBNUM }, 'm' }
   4214 };
   4215 
   4216 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
   4217   { { OPERAND_art }, 'o' }
   4218 };
   4219 
   4220 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
   4221   { { STATE_ICOUNT }, 'i' }
   4222 };
   4223 
   4224 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
   4225   { { OPERAND_art }, 'i' }
   4226 };
   4227 
   4228 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
   4229   { { STATE_XTSYNC }, 'o' },
   4230   { { STATE_ICOUNT }, 'o' }
   4231 };
   4232 
   4233 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
   4234   { { OPERAND_art }, 'm' }
   4235 };
   4236 
   4237 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
   4238   { { STATE_XTSYNC }, 'o' },
   4239   { { STATE_ICOUNT }, 'm' }
   4240 };
   4241 
   4242 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
   4243   { { OPERAND_art }, 'o' }
   4244 };
   4245 
   4246 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
   4247   { { STATE_ICOUNTLEVEL }, 'i' }
   4248 };
   4249 
   4250 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
   4251   { { OPERAND_art }, 'i' }
   4252 };
   4253 
   4254 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
   4255   { { STATE_ICOUNTLEVEL }, 'o' }
   4256 };
   4257 
   4258 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
   4259   { { OPERAND_art }, 'm' }
   4260 };
   4261 
   4262 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
   4263   { { STATE_ICOUNTLEVEL }, 'm' }
   4264 };
   4265 
   4266 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
   4267   { { OPERAND_art }, 'o' }
   4268 };
   4269 
   4270 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
   4271   { { STATE_DDR }, 'i' }
   4272 };
   4273 
   4274 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
   4275   { { OPERAND_art }, 'i' }
   4276 };
   4277 
   4278 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
   4279   { { STATE_XTSYNC }, 'o' },
   4280   { { STATE_DDR }, 'o' }
   4281 };
   4282 
   4283 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
   4284   { { OPERAND_art }, 'm' }
   4285 };
   4286 
   4287 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
   4288   { { STATE_XTSYNC }, 'o' },
   4289   { { STATE_DDR }, 'm' }
   4290 };
   4291 
   4292 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
   4293   { { OPERAND_ars }, 'm' }
   4294 };
   4295 
   4296 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
   4297   { { STATE_XTSYNC }, 'o' },
   4298   { { STATE_InOCDMode }, 'i' },
   4299   { { STATE_DDR }, 'o' }
   4300 };
   4301 
   4302 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
   4303   { { OPERAND_ars }, 'm' }
   4304 };
   4305 
   4306 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
   4307   { { STATE_InOCDMode }, 'i' },
   4308   { { STATE_DDR }, 'i' }
   4309 };
   4310 
   4311 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
   4312   { { OPERAND_imms }, 'i' }
   4313 };
   4314 
   4315 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
   4316   { { STATE_InOCDMode }, 'm' },
   4317   { { STATE_EPC6 }, 'i' },
   4318   { { STATE_PSWOE }, 'o' },
   4319   { { STATE_PSCALLINC }, 'o' },
   4320   { { STATE_PSOWB }, 'o' },
   4321   { { STATE_PSUM }, 'o' },
   4322   { { STATE_PSEXCM }, 'o' },
   4323   { { STATE_PSINTLEVEL }, 'o' },
   4324   { { STATE_EPS6 }, 'i' }
   4325 };
   4326 
   4327 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
   4328   { { STATE_InOCDMode }, 'm' }
   4329 };
   4330 
   4331 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
   4332   { { OPERAND_art }, 'i' }
   4333 };
   4334 
   4335 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
   4336   { { STATE_XTSYNC }, 'o' }
   4337 };
   4338 
   4339 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
   4340   { { OPERAND_art }, 'o' }
   4341 };
   4342 
   4343 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
   4344   { { STATE_CCOUNT }, 'i' }
   4345 };
   4346 
   4347 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
   4348   { { OPERAND_art }, 'i' }
   4349 };
   4350 
   4351 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
   4352   { { STATE_XTSYNC }, 'o' },
   4353   { { STATE_CCOUNT }, 'o' }
   4354 };
   4355 
   4356 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
   4357   { { OPERAND_art }, 'm' }
   4358 };
   4359 
   4360 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
   4361   { { STATE_XTSYNC }, 'o' },
   4362   { { STATE_CCOUNT }, 'm' }
   4363 };
   4364 
   4365 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
   4366   { { OPERAND_art }, 'o' }
   4367 };
   4368 
   4369 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
   4370   { { STATE_CCOMPARE0 }, 'i' }
   4371 };
   4372 
   4373 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
   4374   { { OPERAND_art }, 'i' }
   4375 };
   4376 
   4377 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
   4378   { { STATE_CCOMPARE0 }, 'o' },
   4379   { { STATE_INTERRUPT }, 'm' }
   4380 };
   4381 
   4382 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
   4383   { { OPERAND_art }, 'm' }
   4384 };
   4385 
   4386 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
   4387   { { STATE_CCOMPARE0 }, 'm' },
   4388   { { STATE_INTERRUPT }, 'm' }
   4389 };
   4390 
   4391 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
   4392   { { OPERAND_art }, 'o' }
   4393 };
   4394 
   4395 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
   4396   { { STATE_CCOMPARE1 }, 'i' }
   4397 };
   4398 
   4399 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
   4400   { { OPERAND_art }, 'i' }
   4401 };
   4402 
   4403 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
   4404   { { STATE_CCOMPARE1 }, 'o' },
   4405   { { STATE_INTERRUPT }, 'm' }
   4406 };
   4407 
   4408 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
   4409   { { OPERAND_art }, 'm' }
   4410 };
   4411 
   4412 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
   4413   { { STATE_CCOMPARE1 }, 'm' },
   4414   { { STATE_INTERRUPT }, 'm' }
   4415 };
   4416 
   4417 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
   4418   { { OPERAND_art }, 'o' }
   4419 };
   4420 
   4421 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
   4422   { { STATE_CCOMPARE2 }, 'i' }
   4423 };
   4424 
   4425 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
   4426   { { OPERAND_art }, 'i' }
   4427 };
   4428 
   4429 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
   4430   { { STATE_CCOMPARE2 }, 'o' },
   4431   { { STATE_INTERRUPT }, 'm' }
   4432 };
   4433 
   4434 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
   4435   { { OPERAND_art }, 'm' }
   4436 };
   4437 
   4438 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
   4439   { { STATE_CCOMPARE2 }, 'm' },
   4440   { { STATE_INTERRUPT }, 'm' }
   4441 };
   4442 
   4443 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
   4444   { { OPERAND_ars }, 'i' }
   4445 };
   4446 
   4447 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
   4448   { { STATE_XTSYNC }, 'o' }
   4449 };
   4450 
   4451 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
   4452   { { OPERAND_art }, 'o' },
   4453   { { OPERAND_ars }, 'i' }
   4454 };
   4455 
   4456 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
   4457   { { OPERAND_art }, 'i' },
   4458   { { OPERAND_ars }, 'i' }
   4459 };
   4460 
   4461 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
   4462   { { STATE_XTSYNC }, 'o' }
   4463 };
   4464 
   4465 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
   4466   { { OPERAND_ars }, 'i' }
   4467 };
   4468 
   4469 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
   4470   { { OPERAND_art }, 'o' },
   4471   { { OPERAND_ars }, 'i' }
   4472 };
   4473 
   4474 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
   4475   { { OPERAND_art }, 'i' },
   4476   { { OPERAND_ars }, 'i' }
   4477 };
   4478 
   4479 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
   4480   { { OPERAND_arr }, 'o' },
   4481   { { OPERAND_ars }, 'i' },
   4482   { { OPERAND_art }, 'i' }
   4483 };
   4484 
   4485 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
   4486   { { OPERAND_art }, 'o' },
   4487   { { OPERAND_ars }, 'i' }
   4488 };
   4489 
   4490 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
   4491   { { OPERAND_arr }, 'o' },
   4492   { { OPERAND_ars }, 'i' },
   4493   { { OPERAND_tp7 }, 'i' }
   4494 };
   4495 
   4496 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
   4497   { { OPERAND_art }, 'o' },
   4498   { { OPERAND_ars }, 'i' },
   4499   { { OPERAND_uimm8x4 }, 'i' }
   4500 };
   4501 
   4502 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
   4503   { { OPERAND_art }, 'i' },
   4504   { { OPERAND_ars }, 'i' },
   4505   { { OPERAND_uimm8x4 }, 'i' }
   4506 };
   4507 
   4508 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
   4509   { { OPERAND_art }, 'm' },
   4510   { { OPERAND_ars }, 'i' },
   4511   { { OPERAND_uimm8x4 }, 'i' }
   4512 };
   4513 
   4514 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
   4515   { { STATE_SCOMPARE1 }, 'i' },
   4516   { { STATE_XTSYNC }, 'i' },
   4517   { { STATE_SCOMPARE1 }, 'i' }
   4518 };
   4519 
   4520 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
   4521   { { OPERAND_art }, 'o' }
   4522 };
   4523 
   4524 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
   4525   { { STATE_SCOMPARE1 }, 'i' }
   4526 };
   4527 
   4528 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
   4529   { { OPERAND_art }, 'i' }
   4530 };
   4531 
   4532 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
   4533   { { STATE_SCOMPARE1 }, 'o' }
   4534 };
   4535 
   4536 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
   4537   { { OPERAND_art }, 'm' }
   4538 };
   4539 
   4540 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
   4541   { { STATE_SCOMPARE1 }, 'm' }
   4542 };
   4543 
   4544 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
   4545   { { OPERAND_art }, 'o' }
   4546 };
   4547 
   4548 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
   4549   { { STATE_ATOMCTL }, 'i' }
   4550 };
   4551 
   4552 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
   4553   { { OPERAND_art }, 'i' }
   4554 };
   4555 
   4556 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
   4557   { { STATE_ATOMCTL }, 'o' },
   4558   { { STATE_XTSYNC }, 'o' }
   4559 };
   4560 
   4561 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
   4562   { { OPERAND_art }, 'm' }
   4563 };
   4564 
   4565 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
   4566   { { STATE_ATOMCTL }, 'm' },
   4567   { { STATE_XTSYNC }, 'o' }
   4568 };
   4569 
   4570 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
   4571   { { OPERAND_arr }, 'o' },
   4572   { { OPERAND_ars }, 'i' },
   4573   { { OPERAND_art }, 'i' }
   4574 };
   4575 
   4576 static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
   4577   { { OPERAND_art }, 'o' }
   4578 };
   4579 
   4580 static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
   4581   { { OPERAND_art }, 'i' }
   4582 };
   4583 
   4584 static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
   4585   { { OPERAND_art }, 'm' }
   4586 };
   4587 
   4588 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
   4589   { { OPERAND_art }, 'o' },
   4590   { { OPERAND_ars }, 'i' }
   4591 };
   4592 
   4593 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
   4594   { { OPERAND_art }, 'i' },
   4595   { { OPERAND_ars }, 'i' }
   4596 };
   4597 
   4598 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
   4599   { { OPERAND_arr }, 'o' }
   4600 };
   4601 
   4602 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
   4603   { { STATE_EXPSTATE }, 'i' }
   4604 };
   4605 
   4606 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
   4607   { { OPERAND_art }, 'i' }
   4608 };
   4609 
   4610 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
   4611   { { STATE_EXPSTATE }, 'o' }
   4612 };
   4613 
   4614 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
   4615   { { OPERAND_art }, 'o' }
   4616 };
   4617 
   4618 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
   4619   INTERFACE_IMPWIRE
   4620 };
   4621 
   4622 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
   4623   { { OPERAND_bitindex }, 'i' }
   4624 };
   4625 
   4626 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
   4627   { { STATE_EXPSTATE }, 'm' }
   4628 };
   4629 
   4630 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
   4631   { { OPERAND_bitindex }, 'i' }
   4632 };
   4633 
   4634 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
   4635   { { STATE_EXPSTATE }, 'm' }
   4636 };
   4637 
   4638 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
   4639   { { OPERAND_art }, 'i' },
   4640   { { OPERAND_ars }, 'i' }
   4641 };
   4642 
   4643 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
   4644   { { STATE_EXPSTATE }, 'm' }
   4645 };
   4646 
   4647 static xtensa_iclass_internal iclasses[] = {
   4648   { 0, 0 /* xt_iclass_excw */,
   4649     0, 0, 0, 0 },
   4650   { 0, 0 /* xt_iclass_rfe */,
   4651     2, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
   4652   { 0, 0 /* xt_iclass_rfde */,
   4653     1, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
   4654   { 0, 0 /* xt_iclass_syscall */,
   4655     0, 0, 0, 0 },
   4656   { 2, Iclass_xt_iclass_call12_args,
   4657     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
   4658   { 2, Iclass_xt_iclass_call8_args,
   4659     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
   4660   { 2, Iclass_xt_iclass_call4_args,
   4661     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
   4662   { 2, Iclass_xt_iclass_callx12_args,
   4663     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
   4664   { 2, Iclass_xt_iclass_callx8_args,
   4665     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
   4666   { 2, Iclass_xt_iclass_callx4_args,
   4667     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
   4668   { 3, Iclass_xt_iclass_entry_args,
   4669     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
   4670   { 2, Iclass_xt_iclass_movsp_args,
   4671     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
   4672   { 1, Iclass_xt_iclass_rotw_args,
   4673     1, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
   4674   { 1, Iclass_xt_iclass_retw_args,
   4675     5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
   4676   { 0, 0 /* xt_iclass_rfwou */,
   4677     5, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
   4678   { 3, Iclass_xt_iclass_l32e_args,
   4679     0, 0, 0, 0 },
   4680   { 3, Iclass_xt_iclass_s32e_args,
   4681     0, 0, 0, 0 },
   4682   { 1, Iclass_xt_iclass_rsr_windowbase_args,
   4683     1, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
   4684   { 1, Iclass_xt_iclass_wsr_windowbase_args,
   4685     1, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
   4686   { 1, Iclass_xt_iclass_xsr_windowbase_args,
   4687     1, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
   4688   { 1, Iclass_xt_iclass_rsr_windowstart_args,
   4689     1, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
   4690   { 1, Iclass_xt_iclass_wsr_windowstart_args,
   4691     1, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
   4692   { 1, Iclass_xt_iclass_xsr_windowstart_args,
   4693     1, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
   4694   { 3, Iclass_xt_iclass_add_n_args,
   4695     0, 0, 0, 0 },
   4696   { 3, Iclass_xt_iclass_addi_n_args,
   4697     0, 0, 0, 0 },
   4698   { 2, Iclass_xt_iclass_bz6_args,
   4699     0, 0, 0, 0 },
   4700   { 0, 0 /* xt_iclass_ill_n */,
   4701     0, 0, 0, 0 },
   4702   { 3, Iclass_xt_iclass_loadi4_args,
   4703     0, 0, 0, 0 },
   4704   { 2, Iclass_xt_iclass_mov_n_args,
   4705     0, 0, 0, 0 },
   4706   { 2, Iclass_xt_iclass_movi_n_args,
   4707     0, 0, 0, 0 },
   4708   { 0, 0 /* xt_iclass_nopn */,
   4709     0, 0, 0, 0 },
   4710   { 1, Iclass_xt_iclass_retn_args,
   4711     0, 0, 0, 0 },
   4712   { 3, Iclass_xt_iclass_storei4_args,
   4713     0, 0, 0, 0 },
   4714   { 3, Iclass_xt_iclass_addi_args,
   4715     0, 0, 0, 0 },
   4716   { 3, Iclass_xt_iclass_addmi_args,
   4717     0, 0, 0, 0 },
   4718   { 3, Iclass_xt_iclass_addsub_args,
   4719     0, 0, 0, 0 },
   4720   { 3, Iclass_xt_iclass_bit_args,
   4721     0, 0, 0, 0 },
   4722   { 3, Iclass_xt_iclass_bsi8_args,
   4723     0, 0, 0, 0 },
   4724   { 3, Iclass_xt_iclass_bsi8b_args,
   4725     0, 0, 0, 0 },
   4726   { 3, Iclass_xt_iclass_bsi8u_args,
   4727     0, 0, 0, 0 },
   4728   { 3, Iclass_xt_iclass_bst8_args,
   4729     0, 0, 0, 0 },
   4730   { 2, Iclass_xt_iclass_bsz12_args,
   4731     0, 0, 0, 0 },
   4732   { 2, Iclass_xt_iclass_call0_args,
   4733     0, 0, 0, 0 },
   4734   { 2, Iclass_xt_iclass_callx0_args,
   4735     0, 0, 0, 0 },
   4736   { 4, Iclass_xt_iclass_exti_args,
   4737     0, 0, 0, 0 },
   4738   { 0, 0 /* xt_iclass_ill */,
   4739     0, 0, 0, 0 },
   4740   { 1, Iclass_xt_iclass_jump_args,
   4741     0, 0, 0, 0 },
   4742   { 1, Iclass_xt_iclass_jumpx_args,
   4743     0, 0, 0, 0 },
   4744   { 3, Iclass_xt_iclass_l16ui_args,
   4745     0, 0, 0, 0 },
   4746   { 3, Iclass_xt_iclass_l16si_args,
   4747     0, 0, 0, 0 },
   4748   { 3, Iclass_xt_iclass_l32i_args,
   4749     0, 0, 0, 0 },
   4750   { 2, Iclass_xt_iclass_l32r_args,
   4751     0, 0, 0, 0 },
   4752   { 3, Iclass_xt_iclass_l8i_args,
   4753     0, 0, 0, 0 },
   4754   { 2, Iclass_xt_iclass_movi_args,
   4755     0, 0, 0, 0 },
   4756   { 3, Iclass_xt_iclass_movz_args,
   4757     0, 0, 0, 0 },
   4758   { 2, Iclass_xt_iclass_neg_args,
   4759     0, 0, 0, 0 },
   4760   { 0, 0 /* xt_iclass_nop */,
   4761     0, 0, 0, 0 },
   4762   { 1, Iclass_xt_iclass_return_args,
   4763     0, 0, 0, 0 },
   4764   { 0, 0 /* xt_iclass_simcall */,
   4765     0, 0, 0, 0 },
   4766   { 3, Iclass_xt_iclass_s16i_args,
   4767     0, 0, 0, 0 },
   4768   { 3, Iclass_xt_iclass_s32i_args,
   4769     0, 0, 0, 0 },
   4770   { 3, Iclass_xt_iclass_s32nb_args,
   4771     0, 0, 0, 0 },
   4772   { 3, Iclass_xt_iclass_s8i_args,
   4773     0, 0, 0, 0 },
   4774   { 1, Iclass_xt_iclass_sar_args,
   4775     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
   4776   { 1, Iclass_xt_iclass_sari_args,
   4777     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
   4778   { 2, Iclass_xt_iclass_shifts_args,
   4779     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
   4780   { 3, Iclass_xt_iclass_shiftst_args,
   4781     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
   4782   { 2, Iclass_xt_iclass_shiftt_args,
   4783     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
   4784   { 3, Iclass_xt_iclass_slli_args,
   4785     0, 0, 0, 0 },
   4786   { 3, Iclass_xt_iclass_srai_args,
   4787     0, 0, 0, 0 },
   4788   { 3, Iclass_xt_iclass_srli_args,
   4789     0, 0, 0, 0 },
   4790   { 0, 0 /* xt_iclass_memw */,
   4791     0, 0, 0, 0 },
   4792   { 0, 0 /* xt_iclass_extw */,
   4793     0, 0, 0, 0 },
   4794   { 0, 0 /* xt_iclass_isync */,
   4795     0, 0, 0, 0 },
   4796   { 0, 0 /* xt_iclass_sync */,
   4797     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
   4798   { 2, Iclass_xt_iclass_rsil_args,
   4799     6, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
   4800   { 1, Iclass_xt_iclass_rsr_sar_args,
   4801     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
   4802   { 1, Iclass_xt_iclass_wsr_sar_args,
   4803     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
   4804   { 1, Iclass_xt_iclass_xsr_sar_args,
   4805     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
   4806   { 1, Iclass_xt_iclass_rsr_memctl_args,
   4807     0, 0, 0, 0 },
   4808   { 1, Iclass_xt_iclass_wsr_memctl_args,
   4809     0, 0, 0, 0 },
   4810   { 1, Iclass_xt_iclass_xsr_memctl_args,
   4811     0, 0, 0, 0 },
   4812   { 1, Iclass_xt_iclass_rsr_litbase_args,
   4813     0, 0, 0, 0 },
   4814   { 1, Iclass_xt_iclass_wsr_litbase_args,
   4815     0, 0, 0, 0 },
   4816   { 1, Iclass_xt_iclass_xsr_litbase_args,
   4817     0, 0, 0, 0 },
   4818   { 1, Iclass_xt_iclass_rsr_configid0_args,
   4819     0, 0, 0, 0 },
   4820   { 1, Iclass_xt_iclass_wsr_configid0_args,
   4821     0, 0, 0, 0 },
   4822   { 1, Iclass_xt_iclass_rsr_configid1_args,
   4823     0, 0, 0, 0 },
   4824   { 1, Iclass_xt_iclass_rsr_ps_args,
   4825     6, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
   4826   { 1, Iclass_xt_iclass_wsr_ps_args,
   4827     6, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
   4828   { 1, Iclass_xt_iclass_xsr_ps_args,
   4829     6, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
   4830   { 1, Iclass_xt_iclass_rsr_epc1_args,
   4831     1, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
   4832   { 1, Iclass_xt_iclass_wsr_epc1_args,
   4833     1, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
   4834   { 1, Iclass_xt_iclass_xsr_epc1_args,
   4835     1, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
   4836   { 1, Iclass_xt_iclass_rsr_excsave1_args,
   4837     1, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
   4838   { 1, Iclass_xt_iclass_wsr_excsave1_args,
   4839     1, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
   4840   { 1, Iclass_xt_iclass_xsr_excsave1_args,
   4841     1, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
   4842   { 1, Iclass_xt_iclass_rsr_epc2_args,
   4843     1, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
   4844   { 1, Iclass_xt_iclass_wsr_epc2_args,
   4845     1, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
   4846   { 1, Iclass_xt_iclass_xsr_epc2_args,
   4847     1, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
   4848   { 1, Iclass_xt_iclass_rsr_excsave2_args,
   4849     1, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
   4850   { 1, Iclass_xt_iclass_wsr_excsave2_args,
   4851     1, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
   4852   { 1, Iclass_xt_iclass_xsr_excsave2_args,
   4853     1, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
   4854   { 1, Iclass_xt_iclass_rsr_epc3_args,
   4855     1, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
   4856   { 1, Iclass_xt_iclass_wsr_epc3_args,
   4857     1, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
   4858   { 1, Iclass_xt_iclass_xsr_epc3_args,
   4859     1, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
   4860   { 1, Iclass_xt_iclass_rsr_excsave3_args,
   4861     1, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
   4862   { 1, Iclass_xt_iclass_wsr_excsave3_args,
   4863     1, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
   4864   { 1, Iclass_xt_iclass_xsr_excsave3_args,
   4865     1, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
   4866   { 1, Iclass_xt_iclass_rsr_epc4_args,
   4867     1, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
   4868   { 1, Iclass_xt_iclass_wsr_epc4_args,
   4869     1, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
   4870   { 1, Iclass_xt_iclass_xsr_epc4_args,
   4871     1, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
   4872   { 1, Iclass_xt_iclass_rsr_excsave4_args,
   4873     1, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
   4874   { 1, Iclass_xt_iclass_wsr_excsave4_args,
   4875     1, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
   4876   { 1, Iclass_xt_iclass_xsr_excsave4_args,
   4877     1, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
   4878   { 1, Iclass_xt_iclass_rsr_epc5_args,
   4879     1, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
   4880   { 1, Iclass_xt_iclass_wsr_epc5_args,
   4881     1, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
   4882   { 1, Iclass_xt_iclass_xsr_epc5_args,
   4883     1, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
   4884   { 1, Iclass_xt_iclass_rsr_excsave5_args,
   4885     1, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
   4886   { 1, Iclass_xt_iclass_wsr_excsave5_args,
   4887     1, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
   4888   { 1, Iclass_xt_iclass_xsr_excsave5_args,
   4889     1, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
   4890   { 1, Iclass_xt_iclass_rsr_epc6_args,
   4891     1, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
   4892   { 1, Iclass_xt_iclass_wsr_epc6_args,
   4893     1, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
   4894   { 1, Iclass_xt_iclass_xsr_epc6_args,
   4895     1, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
   4896   { 1, Iclass_xt_iclass_rsr_excsave6_args,
   4897     1, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
   4898   { 1, Iclass_xt_iclass_wsr_excsave6_args,
   4899     1, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
   4900   { 1, Iclass_xt_iclass_xsr_excsave6_args,
   4901     1, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
   4902   { 1, Iclass_xt_iclass_rsr_epc7_args,
   4903     1, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
   4904   { 1, Iclass_xt_iclass_wsr_epc7_args,
   4905     1, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
   4906   { 1, Iclass_xt_iclass_xsr_epc7_args,
   4907     1, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
   4908   { 1, Iclass_xt_iclass_rsr_excsave7_args,
   4909     1, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
   4910   { 1, Iclass_xt_iclass_wsr_excsave7_args,
   4911     1, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
   4912   { 1, Iclass_xt_iclass_xsr_excsave7_args,
   4913     1, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
   4914   { 1, Iclass_xt_iclass_rsr_eps2_args,
   4915     1, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
   4916   { 1, Iclass_xt_iclass_wsr_eps2_args,
   4917     1, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
   4918   { 1, Iclass_xt_iclass_xsr_eps2_args,
   4919     1, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
   4920   { 1, Iclass_xt_iclass_rsr_eps3_args,
   4921     1, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
   4922   { 1, Iclass_xt_iclass_wsr_eps3_args,
   4923     1, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
   4924   { 1, Iclass_xt_iclass_xsr_eps3_args,
   4925     1, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
   4926   { 1, Iclass_xt_iclass_rsr_eps4_args,
   4927     1, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
   4928   { 1, Iclass_xt_iclass_wsr_eps4_args,
   4929     1, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
   4930   { 1, Iclass_xt_iclass_xsr_eps4_args,
   4931     1, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
   4932   { 1, Iclass_xt_iclass_rsr_eps5_args,
   4933     1, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
   4934   { 1, Iclass_xt_iclass_wsr_eps5_args,
   4935     1, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
   4936   { 1, Iclass_xt_iclass_xsr_eps5_args,
   4937     1, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
   4938   { 1, Iclass_xt_iclass_rsr_eps6_args,
   4939     1, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
   4940   { 1, Iclass_xt_iclass_wsr_eps6_args,
   4941     1, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
   4942   { 1, Iclass_xt_iclass_xsr_eps6_args,
   4943     1, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
   4944   { 1, Iclass_xt_iclass_rsr_eps7_args,
   4945     1, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
   4946   { 1, Iclass_xt_iclass_wsr_eps7_args,
   4947     1, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
   4948   { 1, Iclass_xt_iclass_xsr_eps7_args,
   4949     1, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
   4950   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
   4951     1, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
   4952   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
   4953     1, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
   4954   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
   4955     1, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
   4956   { 1, Iclass_xt_iclass_rsr_depc_args,
   4957     1, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
   4958   { 1, Iclass_xt_iclass_wsr_depc_args,
   4959     1, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
   4960   { 1, Iclass_xt_iclass_xsr_depc_args,
   4961     1, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
   4962   { 1, Iclass_xt_iclass_rsr_exccause_args,
   4963     2, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
   4964   { 1, Iclass_xt_iclass_wsr_exccause_args,
   4965     1, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
   4966   { 1, Iclass_xt_iclass_xsr_exccause_args,
   4967     1, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
   4968   { 1, Iclass_xt_iclass_rsr_misc0_args,
   4969     1, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
   4970   { 1, Iclass_xt_iclass_wsr_misc0_args,
   4971     1, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
   4972   { 1, Iclass_xt_iclass_xsr_misc0_args,
   4973     1, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
   4974   { 1, Iclass_xt_iclass_rsr_misc1_args,
   4975     1, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
   4976   { 1, Iclass_xt_iclass_wsr_misc1_args,
   4977     1, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
   4978   { 1, Iclass_xt_iclass_xsr_misc1_args,
   4979     1, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
   4980   { 1, Iclass_xt_iclass_rsr_prid_args,
   4981     0, 0, 0, 0 },
   4982   { 1, Iclass_xt_iclass_rsr_vecbase_args,
   4983     1, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
   4984   { 1, Iclass_xt_iclass_wsr_vecbase_args,
   4985     1, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
   4986   { 1, Iclass_xt_iclass_xsr_vecbase_args,
   4987     1, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
   4988   { 3, Iclass_xt_iclass_salt_args,
   4989     0, 0, 0, 0 },
   4990   { 3, Iclass_xt_mul16_args,
   4991     0, 0, 0, 0 },
   4992   { 3, Iclass_xt_mul32_args,
   4993     0, 0, 0, 0 },
   4994   { 1, Iclass_xt_iclass_rfi_args,
   4995     20, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
   4996   { 1, Iclass_xt_iclass_wait_args,
   4997     1, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
   4998   { 1, Iclass_xt_iclass_rsr_interrupt_args,
   4999     1, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
   5000   { 1, Iclass_xt_iclass_wsr_intset_args,
   5001     2, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
   5002   { 1, Iclass_xt_iclass_wsr_intclear_args,
   5003     2, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
   5004   { 1, Iclass_xt_iclass_rsr_intenable_args,
   5005     1, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
   5006   { 1, Iclass_xt_iclass_wsr_intenable_args,
   5007     1, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
   5008   { 1, Iclass_xt_iclass_xsr_intenable_args,
   5009     1, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
   5010   { 2, Iclass_xt_iclass_break_args,
   5011     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
   5012   { 1, Iclass_xt_iclass_break_n_args,
   5013     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
   5014   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
   5015     1, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
   5016   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
   5017     2, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
   5018   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
   5019     2, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
   5020   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
   5021     1, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
   5022   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
   5023     2, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
   5024   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
   5025     2, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
   5026   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
   5027     1, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
   5028   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
   5029     2, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
   5030   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
   5031     2, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
   5032   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
   5033     1, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
   5034   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
   5035     2, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
   5036   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
   5037     2, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
   5038   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
   5039     1, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
   5040   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
   5041     1, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
   5042   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
   5043     1, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
   5044   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
   5045     1, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
   5046   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
   5047     1, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
   5048   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
   5049     1, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
   5050   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
   5051     1, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
   5052   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
   5053     1, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
   5054   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
   5055     1, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
   5056   { 1, Iclass_xt_iclass_rsr_debugcause_args,
   5057     2, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
   5058   { 1, Iclass_xt_iclass_wsr_debugcause_args,
   5059     2, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
   5060   { 1, Iclass_xt_iclass_xsr_debugcause_args,
   5061     2, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
   5062   { 1, Iclass_xt_iclass_rsr_icount_args,
   5063     1, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
   5064   { 1, Iclass_xt_iclass_wsr_icount_args,
   5065     2, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
   5066   { 1, Iclass_xt_iclass_xsr_icount_args,
   5067     2, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
   5068   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
   5069     1, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
   5070   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
   5071     1, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
   5072   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
   5073     1, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
   5074   { 1, Iclass_xt_iclass_rsr_ddr_args,
   5075     1, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
   5076   { 1, Iclass_xt_iclass_wsr_ddr_args,
   5077     2, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
   5078   { 1, Iclass_xt_iclass_xsr_ddr_args,
   5079     2, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
   5080   { 1, Iclass_xt_iclass_lddr32_p_args,
   5081     3, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
   5082   { 1, Iclass_xt_iclass_sddr32_p_args,
   5083     2, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
   5084   { 1, Iclass_xt_iclass_rfdo_args,
   5085     9, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
   5086   { 0, 0 /* xt_iclass_rfdd */,
   5087     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
   5088   { 1, Iclass_xt_iclass_wsr_mmid_args,
   5089     1, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
   5090   { 1, Iclass_xt_iclass_rsr_ccount_args,
   5091     1, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
   5092   { 1, Iclass_xt_iclass_wsr_ccount_args,
   5093     2, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
   5094   { 1, Iclass_xt_iclass_xsr_ccount_args,
   5095     2, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
   5096   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
   5097     1, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
   5098   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
   5099     2, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
   5100   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
   5101     2, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
   5102   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
   5103     1, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
   5104   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
   5105     2, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
   5106   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
   5107     2, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
   5108   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
   5109     1, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
   5110   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
   5111     2, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
   5112   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
   5113     2, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
   5114   { 1, Iclass_xt_iclass_idtlb_args,
   5115     1, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
   5116   { 2, Iclass_xt_iclass_rdtlb_args,
   5117     0, 0, 0, 0 },
   5118   { 2, Iclass_xt_iclass_wdtlb_args,
   5119     1, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
   5120   { 1, Iclass_xt_iclass_iitlb_args,
   5121     0, 0, 0, 0 },
   5122   { 2, Iclass_xt_iclass_ritlb_args,
   5123     0, 0, 0, 0 },
   5124   { 2, Iclass_xt_iclass_witlb_args,
   5125     0, 0, 0, 0 },
   5126   { 3, Iclass_xt_iclass_minmax_args,
   5127     0, 0, 0, 0 },
   5128   { 2, Iclass_xt_iclass_nsa_args,
   5129     0, 0, 0, 0 },
   5130   { 3, Iclass_xt_iclass_sx_args,
   5131     0, 0, 0, 0 },
   5132   { 3, Iclass_xt_iclass_l32ai_args,
   5133     0, 0, 0, 0 },
   5134   { 3, Iclass_xt_iclass_s32ri_args,
   5135     0, 0, 0, 0 },
   5136   { 3, Iclass_xt_iclass_s32c1i_args,
   5137     3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
   5138   { 1, Iclass_xt_iclass_rsr_scompare1_args,
   5139     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
   5140   { 1, Iclass_xt_iclass_wsr_scompare1_args,
   5141     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
   5142   { 1, Iclass_xt_iclass_xsr_scompare1_args,
   5143     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
   5144   { 1, Iclass_xt_iclass_rsr_atomctl_args,
   5145     1, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
   5146   { 1, Iclass_xt_iclass_wsr_atomctl_args,
   5147     2, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
   5148   { 1, Iclass_xt_iclass_xsr_atomctl_args,
   5149     2, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
   5150   { 3, Iclass_xt_iclass_div_args,
   5151     0, 0, 0, 0 },
   5152   { 1, Iclass_xt_iclass_rsr_eraccess_args,
   5153     0, 0, 0, 0 },
   5154   { 1, Iclass_xt_iclass_wsr_eraccess_args,
   5155     0, 0, 0, 0 },
   5156   { 1, Iclass_xt_iclass_xsr_eraccess_args,
   5157     0, 0, 0, 0 },
   5158   { 2, Iclass_xt_iclass_rer_args,
   5159     0, 0, 0, 0 },
   5160   { 2, Iclass_xt_iclass_wer_args,
   5161     0, 0, 0, 0 },
   5162   { 1, Iclass_rur_expstate_args,
   5163     1, Iclass_rur_expstate_stateArgs, 0, 0 },
   5164   { 1, Iclass_wur_expstate_args,
   5165     1, Iclass_wur_expstate_stateArgs, 0, 0 },
   5166   { 1, Iclass_iclass_READ_IMPWIRE_args,
   5167     0, 0, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
   5168   { 1, Iclass_iclass_SETB_EXPSTATE_args,
   5169     1, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
   5170   { 1, Iclass_iclass_CLRB_EXPSTATE_args,
   5171     1, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
   5172   { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
   5173     1, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
   5174 };
   5175 
   5176 enum xtensa_iclass_id {
   5177   ICLASS_xt_iclass_excw,
   5178   ICLASS_xt_iclass_rfe,
   5179   ICLASS_xt_iclass_rfde,
   5180   ICLASS_xt_iclass_syscall,
   5181   ICLASS_xt_iclass_call12,
   5182   ICLASS_xt_iclass_call8,
   5183   ICLASS_xt_iclass_call4,
   5184   ICLASS_xt_iclass_callx12,
   5185   ICLASS_xt_iclass_callx8,
   5186   ICLASS_xt_iclass_callx4,
   5187   ICLASS_xt_iclass_entry,
   5188   ICLASS_xt_iclass_movsp,
   5189   ICLASS_xt_iclass_rotw,
   5190   ICLASS_xt_iclass_retw,
   5191   ICLASS_xt_iclass_rfwou,
   5192   ICLASS_xt_iclass_l32e,
   5193   ICLASS_xt_iclass_s32e,
   5194   ICLASS_xt_iclass_rsr_windowbase,
   5195   ICLASS_xt_iclass_wsr_windowbase,
   5196   ICLASS_xt_iclass_xsr_windowbase,
   5197   ICLASS_xt_iclass_rsr_windowstart,
   5198   ICLASS_xt_iclass_wsr_windowstart,
   5199   ICLASS_xt_iclass_xsr_windowstart,
   5200   ICLASS_xt_iclass_add_n,
   5201   ICLASS_xt_iclass_addi_n,
   5202   ICLASS_xt_iclass_bz6,
   5203   ICLASS_xt_iclass_ill_n,
   5204   ICLASS_xt_iclass_loadi4,
   5205   ICLASS_xt_iclass_mov_n,
   5206   ICLASS_xt_iclass_movi_n,
   5207   ICLASS_xt_iclass_nopn,
   5208   ICLASS_xt_iclass_retn,
   5209   ICLASS_xt_iclass_storei4,
   5210   ICLASS_xt_iclass_addi,
   5211   ICLASS_xt_iclass_addmi,
   5212   ICLASS_xt_iclass_addsub,
   5213   ICLASS_xt_iclass_bit,
   5214   ICLASS_xt_iclass_bsi8,
   5215   ICLASS_xt_iclass_bsi8b,
   5216   ICLASS_xt_iclass_bsi8u,
   5217   ICLASS_xt_iclass_bst8,
   5218   ICLASS_xt_iclass_bsz12,
   5219   ICLASS_xt_iclass_call0,
   5220   ICLASS_xt_iclass_callx0,
   5221   ICLASS_xt_iclass_exti,
   5222   ICLASS_xt_iclass_ill,
   5223   ICLASS_xt_iclass_jump,
   5224   ICLASS_xt_iclass_jumpx,
   5225   ICLASS_xt_iclass_l16ui,
   5226   ICLASS_xt_iclass_l16si,
   5227   ICLASS_xt_iclass_l32i,
   5228   ICLASS_xt_iclass_l32r,
   5229   ICLASS_xt_iclass_l8i,
   5230   ICLASS_xt_iclass_movi,
   5231   ICLASS_xt_iclass_movz,
   5232   ICLASS_xt_iclass_neg,
   5233   ICLASS_xt_iclass_nop,
   5234   ICLASS_xt_iclass_return,
   5235   ICLASS_xt_iclass_simcall,
   5236   ICLASS_xt_iclass_s16i,
   5237   ICLASS_xt_iclass_s32i,
   5238   ICLASS_xt_iclass_s32nb,
   5239   ICLASS_xt_iclass_s8i,
   5240   ICLASS_xt_iclass_sar,
   5241   ICLASS_xt_iclass_sari,
   5242   ICLASS_xt_iclass_shifts,
   5243   ICLASS_xt_iclass_shiftst,
   5244   ICLASS_xt_iclass_shiftt,
   5245   ICLASS_xt_iclass_slli,
   5246   ICLASS_xt_iclass_srai,
   5247   ICLASS_xt_iclass_srli,
   5248   ICLASS_xt_iclass_memw,
   5249   ICLASS_xt_iclass_extw,
   5250   ICLASS_xt_iclass_isync,
   5251   ICLASS_xt_iclass_sync,
   5252   ICLASS_xt_iclass_rsil,
   5253   ICLASS_xt_iclass_rsr_sar,
   5254   ICLASS_xt_iclass_wsr_sar,
   5255   ICLASS_xt_iclass_xsr_sar,
   5256   ICLASS_xt_iclass_rsr_memctl,
   5257   ICLASS_xt_iclass_wsr_memctl,
   5258   ICLASS_xt_iclass_xsr_memctl,
   5259   ICLASS_xt_iclass_rsr_litbase,
   5260   ICLASS_xt_iclass_wsr_litbase,
   5261   ICLASS_xt_iclass_xsr_litbase,
   5262   ICLASS_xt_iclass_rsr_configid0,
   5263   ICLASS_xt_iclass_wsr_configid0,
   5264   ICLASS_xt_iclass_rsr_configid1,
   5265   ICLASS_xt_iclass_rsr_ps,
   5266   ICLASS_xt_iclass_wsr_ps,
   5267   ICLASS_xt_iclass_xsr_ps,
   5268   ICLASS_xt_iclass_rsr_epc1,
   5269   ICLASS_xt_iclass_wsr_epc1,
   5270   ICLASS_xt_iclass_xsr_epc1,
   5271   ICLASS_xt_iclass_rsr_excsave1,
   5272   ICLASS_xt_iclass_wsr_excsave1,
   5273   ICLASS_xt_iclass_xsr_excsave1,
   5274   ICLASS_xt_iclass_rsr_epc2,
   5275   ICLASS_xt_iclass_wsr_epc2,
   5276   ICLASS_xt_iclass_xsr_epc2,
   5277   ICLASS_xt_iclass_rsr_excsave2,
   5278   ICLASS_xt_iclass_wsr_excsave2,
   5279   ICLASS_xt_iclass_xsr_excsave2,
   5280   ICLASS_xt_iclass_rsr_epc3,
   5281   ICLASS_xt_iclass_wsr_epc3,
   5282   ICLASS_xt_iclass_xsr_epc3,
   5283   ICLASS_xt_iclass_rsr_excsave3,
   5284   ICLASS_xt_iclass_wsr_excsave3,
   5285   ICLASS_xt_iclass_xsr_excsave3,
   5286   ICLASS_xt_iclass_rsr_epc4,
   5287   ICLASS_xt_iclass_wsr_epc4,
   5288   ICLASS_xt_iclass_xsr_epc4,
   5289   ICLASS_xt_iclass_rsr_excsave4,
   5290   ICLASS_xt_iclass_wsr_excsave4,
   5291   ICLASS_xt_iclass_xsr_excsave4,
   5292   ICLASS_xt_iclass_rsr_epc5,
   5293   ICLASS_xt_iclass_wsr_epc5,
   5294   ICLASS_xt_iclass_xsr_epc5,
   5295   ICLASS_xt_iclass_rsr_excsave5,
   5296   ICLASS_xt_iclass_wsr_excsave5,
   5297   ICLASS_xt_iclass_xsr_excsave5,
   5298   ICLASS_xt_iclass_rsr_epc6,
   5299   ICLASS_xt_iclass_wsr_epc6,
   5300   ICLASS_xt_iclass_xsr_epc6,
   5301   ICLASS_xt_iclass_rsr_excsave6,
   5302   ICLASS_xt_iclass_wsr_excsave6,
   5303   ICLASS_xt_iclass_xsr_excsave6,
   5304   ICLASS_xt_iclass_rsr_epc7,
   5305   ICLASS_xt_iclass_wsr_epc7,
   5306   ICLASS_xt_iclass_xsr_epc7,
   5307   ICLASS_xt_iclass_rsr_excsave7,
   5308   ICLASS_xt_iclass_wsr_excsave7,
   5309   ICLASS_xt_iclass_xsr_excsave7,
   5310   ICLASS_xt_iclass_rsr_eps2,
   5311   ICLASS_xt_iclass_wsr_eps2,
   5312   ICLASS_xt_iclass_xsr_eps2,
   5313   ICLASS_xt_iclass_rsr_eps3,
   5314   ICLASS_xt_iclass_wsr_eps3,
   5315   ICLASS_xt_iclass_xsr_eps3,
   5316   ICLASS_xt_iclass_rsr_eps4,
   5317   ICLASS_xt_iclass_wsr_eps4,
   5318   ICLASS_xt_iclass_xsr_eps4,
   5319   ICLASS_xt_iclass_rsr_eps5,
   5320   ICLASS_xt_iclass_wsr_eps5,
   5321   ICLASS_xt_iclass_xsr_eps5,
   5322   ICLASS_xt_iclass_rsr_eps6,
   5323   ICLASS_xt_iclass_wsr_eps6,
   5324   ICLASS_xt_iclass_xsr_eps6,
   5325   ICLASS_xt_iclass_rsr_eps7,
   5326   ICLASS_xt_iclass_wsr_eps7,
   5327   ICLASS_xt_iclass_xsr_eps7,
   5328   ICLASS_xt_iclass_rsr_excvaddr,
   5329   ICLASS_xt_iclass_wsr_excvaddr,
   5330   ICLASS_xt_iclass_xsr_excvaddr,
   5331   ICLASS_xt_iclass_rsr_depc,
   5332   ICLASS_xt_iclass_wsr_depc,
   5333   ICLASS_xt_iclass_xsr_depc,
   5334   ICLASS_xt_iclass_rsr_exccause,
   5335   ICLASS_xt_iclass_wsr_exccause,
   5336   ICLASS_xt_iclass_xsr_exccause,
   5337   ICLASS_xt_iclass_rsr_misc0,
   5338   ICLASS_xt_iclass_wsr_misc0,
   5339   ICLASS_xt_iclass_xsr_misc0,
   5340   ICLASS_xt_iclass_rsr_misc1,
   5341   ICLASS_xt_iclass_wsr_misc1,
   5342   ICLASS_xt_iclass_xsr_misc1,
   5343   ICLASS_xt_iclass_rsr_prid,
   5344   ICLASS_xt_iclass_rsr_vecbase,
   5345   ICLASS_xt_iclass_wsr_vecbase,
   5346   ICLASS_xt_iclass_xsr_vecbase,
   5347   ICLASS_xt_iclass_salt,
   5348   ICLASS_xt_mul16,
   5349   ICLASS_xt_mul32,
   5350   ICLASS_xt_iclass_rfi,
   5351   ICLASS_xt_iclass_wait,
   5352   ICLASS_xt_iclass_rsr_interrupt,
   5353   ICLASS_xt_iclass_wsr_intset,
   5354   ICLASS_xt_iclass_wsr_intclear,
   5355   ICLASS_xt_iclass_rsr_intenable,
   5356   ICLASS_xt_iclass_wsr_intenable,
   5357   ICLASS_xt_iclass_xsr_intenable,
   5358   ICLASS_xt_iclass_break,
   5359   ICLASS_xt_iclass_break_n,
   5360   ICLASS_xt_iclass_rsr_dbreaka0,
   5361   ICLASS_xt_iclass_wsr_dbreaka0,
   5362   ICLASS_xt_iclass_xsr_dbreaka0,
   5363   ICLASS_xt_iclass_rsr_dbreakc0,
   5364   ICLASS_xt_iclass_wsr_dbreakc0,
   5365   ICLASS_xt_iclass_xsr_dbreakc0,
   5366   ICLASS_xt_iclass_rsr_dbreaka1,
   5367   ICLASS_xt_iclass_wsr_dbreaka1,
   5368   ICLASS_xt_iclass_xsr_dbreaka1,
   5369   ICLASS_xt_iclass_rsr_dbreakc1,
   5370   ICLASS_xt_iclass_wsr_dbreakc1,
   5371   ICLASS_xt_iclass_xsr_dbreakc1,
   5372   ICLASS_xt_iclass_rsr_ibreaka0,
   5373   ICLASS_xt_iclass_wsr_ibreaka0,
   5374   ICLASS_xt_iclass_xsr_ibreaka0,
   5375   ICLASS_xt_iclass_rsr_ibreaka1,
   5376   ICLASS_xt_iclass_wsr_ibreaka1,
   5377   ICLASS_xt_iclass_xsr_ibreaka1,
   5378   ICLASS_xt_iclass_rsr_ibreakenable,
   5379   ICLASS_xt_iclass_wsr_ibreakenable,
   5380   ICLASS_xt_iclass_xsr_ibreakenable,
   5381   ICLASS_xt_iclass_rsr_debugcause,
   5382   ICLASS_xt_iclass_wsr_debugcause,
   5383   ICLASS_xt_iclass_xsr_debugcause,
   5384   ICLASS_xt_iclass_rsr_icount,
   5385   ICLASS_xt_iclass_wsr_icount,
   5386   ICLASS_xt_iclass_xsr_icount,
   5387   ICLASS_xt_iclass_rsr_icountlevel,
   5388   ICLASS_xt_iclass_wsr_icountlevel,
   5389   ICLASS_xt_iclass_xsr_icountlevel,
   5390   ICLASS_xt_iclass_rsr_ddr,
   5391   ICLASS_xt_iclass_wsr_ddr,
   5392   ICLASS_xt_iclass_xsr_ddr,
   5393   ICLASS_xt_iclass_lddr32_p,
   5394   ICLASS_xt_iclass_sddr32_p,
   5395   ICLASS_xt_iclass_rfdo,
   5396   ICLASS_xt_iclass_rfdd,
   5397   ICLASS_xt_iclass_wsr_mmid,
   5398   ICLASS_xt_iclass_rsr_ccount,
   5399   ICLASS_xt_iclass_wsr_ccount,
   5400   ICLASS_xt_iclass_xsr_ccount,
   5401   ICLASS_xt_iclass_rsr_ccompare0,
   5402   ICLASS_xt_iclass_wsr_ccompare0,
   5403   ICLASS_xt_iclass_xsr_ccompare0,
   5404   ICLASS_xt_iclass_rsr_ccompare1,
   5405   ICLASS_xt_iclass_wsr_ccompare1,
   5406   ICLASS_xt_iclass_xsr_ccompare1,
   5407   ICLASS_xt_iclass_rsr_ccompare2,
   5408   ICLASS_xt_iclass_wsr_ccompare2,
   5409   ICLASS_xt_iclass_xsr_ccompare2,
   5410   ICLASS_xt_iclass_idtlb,
   5411   ICLASS_xt_iclass_rdtlb,
   5412   ICLASS_xt_iclass_wdtlb,
   5413   ICLASS_xt_iclass_iitlb,
   5414   ICLASS_xt_iclass_ritlb,
   5415   ICLASS_xt_iclass_witlb,
   5416   ICLASS_xt_iclass_minmax,
   5417   ICLASS_xt_iclass_nsa,
   5418   ICLASS_xt_iclass_sx,
   5419   ICLASS_xt_iclass_l32ai,
   5420   ICLASS_xt_iclass_s32ri,
   5421   ICLASS_xt_iclass_s32c1i,
   5422   ICLASS_xt_iclass_rsr_scompare1,
   5423   ICLASS_xt_iclass_wsr_scompare1,
   5424   ICLASS_xt_iclass_xsr_scompare1,
   5425   ICLASS_xt_iclass_rsr_atomctl,
   5426   ICLASS_xt_iclass_wsr_atomctl,
   5427   ICLASS_xt_iclass_xsr_atomctl,
   5428   ICLASS_xt_iclass_div,
   5429   ICLASS_xt_iclass_rsr_eraccess,
   5430   ICLASS_xt_iclass_wsr_eraccess,
   5431   ICLASS_xt_iclass_xsr_eraccess,
   5432   ICLASS_xt_iclass_rer,
   5433   ICLASS_xt_iclass_wer,
   5434   ICLASS_rur_expstate,
   5435   ICLASS_wur_expstate,
   5436   ICLASS_iclass_READ_IMPWIRE,
   5437   ICLASS_iclass_SETB_EXPSTATE,
   5438   ICLASS_iclass_CLRB_EXPSTATE,
   5439   ICLASS_iclass_WRMSK_EXPSTATE
   5440 };
   5441 
   5442 
   5443 /*  Opcode encodings.  */
   5444 
   5445 static void
   5446 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5447 {
   5448   slotbuf[0] = 0x2080;
   5449 }
   5450 
   5451 static void
   5452 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5453 {
   5454   slotbuf[0] = 0x3000;
   5455 }
   5456 
   5457 static void
   5458 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5459 {
   5460   slotbuf[0] = 0x3200;
   5461 }
   5462 
   5463 static void
   5464 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5465 {
   5466   slotbuf[0] = 0x5000;
   5467 }
   5468 
   5469 static void
   5470 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5471 {
   5472   slotbuf[0] = 0x35;
   5473 }
   5474 
   5475 static void
   5476 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5477 {
   5478   slotbuf[0] = 0x25;
   5479 }
   5480 
   5481 static void
   5482 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5483 {
   5484   slotbuf[0] = 0x15;
   5485 }
   5486 
   5487 static void
   5488 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5489 {
   5490   slotbuf[0] = 0xf0;
   5491 }
   5492 
   5493 static void
   5494 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5495 {
   5496   slotbuf[0] = 0xe0;
   5497 }
   5498 
   5499 static void
   5500 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5501 {
   5502   slotbuf[0] = 0xd0;
   5503 }
   5504 
   5505 static void
   5506 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5507 {
   5508   slotbuf[0] = 0x36;
   5509 }
   5510 
   5511 static void
   5512 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5513 {
   5514   slotbuf[0] = 0x1000;
   5515 }
   5516 
   5517 static void
   5518 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5519 {
   5520   slotbuf[0] = 0x408000;
   5521 }
   5522 
   5523 static void
   5524 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5525 {
   5526   slotbuf[0] = 0x90;
   5527 }
   5528 
   5529 static void
   5530 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5531 {
   5532   slotbuf[0] = 0xf01d;
   5533 }
   5534 
   5535 static void
   5536 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5537 {
   5538   slotbuf[0] = 0x3400;
   5539 }
   5540 
   5541 static void
   5542 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5543 {
   5544   slotbuf[0] = 0x3500;
   5545 }
   5546 
   5547 static void
   5548 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5549 {
   5550   slotbuf[0] = 0x90000;
   5551 }
   5552 
   5553 static void
   5554 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5555 {
   5556   slotbuf[0] = 0x490000;
   5557 }
   5558 
   5559 static void
   5560 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5561 {
   5562   slotbuf[0] = 0x34800;
   5563 }
   5564 
   5565 static void
   5566 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5567 {
   5568   slotbuf[0] = 0x134800;
   5569 }
   5570 
   5571 static void
   5572 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5573 {
   5574   slotbuf[0] = 0x614800;
   5575 }
   5576 
   5577 static void
   5578 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5579 {
   5580   slotbuf[0] = 0x34900;
   5581 }
   5582 
   5583 static void
   5584 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5585 {
   5586   slotbuf[0] = 0x134900;
   5587 }
   5588 
   5589 static void
   5590 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5591 {
   5592   slotbuf[0] = 0x614900;
   5593 }
   5594 
   5595 static void
   5596 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   5597 {
   5598   slotbuf[0] = 0xa;
   5599 }
   5600 
   5601 static void
   5602 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   5603 {
   5604   slotbuf[0] = 0xb;
   5605 }
   5606 
   5607 static void
   5608 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5609 {
   5610   slotbuf[0] = 0x8c;
   5611 }
   5612 
   5613 static void
   5614 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5615 {
   5616   slotbuf[0] = 0xcc;
   5617 }
   5618 
   5619 static void
   5620 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5621 {
   5622   slotbuf[0] = 0xf06d;
   5623 }
   5624 
   5625 static void
   5626 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   5627 {
   5628   slotbuf[0] = 0x8;
   5629 }
   5630 
   5631 static void
   5632 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5633 {
   5634   slotbuf[0] = 0xd;
   5635 }
   5636 
   5637 static void
   5638 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5639 {
   5640   slotbuf[0] = 0xc;
   5641 }
   5642 
   5643 static void
   5644 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5645 {
   5646   slotbuf[0] = 0xf03d;
   5647 }
   5648 
   5649 static void
   5650 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   5651 {
   5652   slotbuf[0] = 0xf00d;
   5653 }
   5654 
   5655 static void
   5656 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   5657 {
   5658   slotbuf[0] = 0x9;
   5659 }
   5660 
   5661 static void
   5662 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5663 {
   5664   slotbuf[0] = 0xc002;
   5665 }
   5666 
   5667 static void
   5668 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5669 {
   5670   slotbuf[0] = 0xd002;
   5671 }
   5672 
   5673 static void
   5674 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5675 {
   5676   slotbuf[0] = 0x800000;
   5677 }
   5678 
   5679 static void
   5680 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5681 {
   5682   slotbuf[0] = 0xc00000;
   5683 }
   5684 
   5685 static void
   5686 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5687 {
   5688   slotbuf[0] = 0x900000;
   5689 }
   5690 
   5691 static void
   5692 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5693 {
   5694   slotbuf[0] = 0xa00000;
   5695 }
   5696 
   5697 static void
   5698 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5699 {
   5700   slotbuf[0] = 0xb00000;
   5701 }
   5702 
   5703 static void
   5704 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5705 {
   5706   slotbuf[0] = 0xd00000;
   5707 }
   5708 
   5709 static void
   5710 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5711 {
   5712   slotbuf[0] = 0xe00000;
   5713 }
   5714 
   5715 static void
   5716 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5717 {
   5718   slotbuf[0] = 0xf00000;
   5719 }
   5720 
   5721 static void
   5722 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5723 {
   5724   slotbuf[0] = 0x100000;
   5725 }
   5726 
   5727 static void
   5728 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5729 {
   5730   slotbuf[0] = 0x200000;
   5731 }
   5732 
   5733 static void
   5734 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5735 {
   5736   slotbuf[0] = 0x300000;
   5737 }
   5738 
   5739 static void
   5740 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5741 {
   5742   slotbuf[0] = 0x26;
   5743 }
   5744 
   5745 static void
   5746 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5747 {
   5748   slotbuf[0] = 0x66;
   5749 }
   5750 
   5751 static void
   5752 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5753 {
   5754   slotbuf[0] = 0xe6;
   5755 }
   5756 
   5757 static void
   5758 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5759 {
   5760   slotbuf[0] = 0xa6;
   5761 }
   5762 
   5763 static void
   5764 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5765 {
   5766   slotbuf[0] = 0x6007;
   5767 }
   5768 
   5769 static void
   5770 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5771 {
   5772   slotbuf[0] = 0xe007;
   5773 }
   5774 
   5775 static void
   5776 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5777 {
   5778   slotbuf[0] = 0xf6;
   5779 }
   5780 
   5781 static void
   5782 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5783 {
   5784   slotbuf[0] = 0xb6;
   5785 }
   5786 
   5787 static void
   5788 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5789 {
   5790   slotbuf[0] = 0x1007;
   5791 }
   5792 
   5793 static void
   5794 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5795 {
   5796   slotbuf[0] = 0x9007;
   5797 }
   5798 
   5799 static void
   5800 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5801 {
   5802   slotbuf[0] = 0xa007;
   5803 }
   5804 
   5805 static void
   5806 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5807 {
   5808   slotbuf[0] = 0x2007;
   5809 }
   5810 
   5811 static void
   5812 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5813 {
   5814   slotbuf[0] = 0xb007;
   5815 }
   5816 
   5817 static void
   5818 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5819 {
   5820   slotbuf[0] = 0x3007;
   5821 }
   5822 
   5823 static void
   5824 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5825 {
   5826   slotbuf[0] = 0x8007;
   5827 }
   5828 
   5829 static void
   5830 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5831 {
   5832   slotbuf[0] = 0x7;
   5833 }
   5834 
   5835 static void
   5836 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5837 {
   5838   slotbuf[0] = 0x4007;
   5839 }
   5840 
   5841 static void
   5842 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5843 {
   5844   slotbuf[0] = 0xc007;
   5845 }
   5846 
   5847 static void
   5848 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5849 {
   5850   slotbuf[0] = 0x5007;
   5851 }
   5852 
   5853 static void
   5854 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5855 {
   5856   slotbuf[0] = 0xd007;
   5857 }
   5858 
   5859 static void
   5860 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5861 {
   5862   slotbuf[0] = 0x16;
   5863 }
   5864 
   5865 static void
   5866 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5867 {
   5868   slotbuf[0] = 0x56;
   5869 }
   5870 
   5871 static void
   5872 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5873 {
   5874   slotbuf[0] = 0xd6;
   5875 }
   5876 
   5877 static void
   5878 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5879 {
   5880   slotbuf[0] = 0x96;
   5881 }
   5882 
   5883 static void
   5884 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5885 {
   5886   slotbuf[0] = 0x5;
   5887 }
   5888 
   5889 static void
   5890 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5891 {
   5892   slotbuf[0] = 0xc0;
   5893 }
   5894 
   5895 static void
   5896 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5897 {
   5898   slotbuf[0] = 0x40000;
   5899 }
   5900 
   5901 static void
   5902 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5903 {
   5904   slotbuf[0] = 0;
   5905 }
   5906 
   5907 static void
   5908 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5909 {
   5910   slotbuf[0] = 0x6;
   5911 }
   5912 
   5913 static void
   5914 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5915 {
   5916   slotbuf[0] = 0xa0;
   5917 }
   5918 
   5919 static void
   5920 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5921 {
   5922   slotbuf[0] = 0x1002;
   5923 }
   5924 
   5925 static void
   5926 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5927 {
   5928   slotbuf[0] = 0x9002;
   5929 }
   5930 
   5931 static void
   5932 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5933 {
   5934   slotbuf[0] = 0x2002;
   5935 }
   5936 
   5937 static void
   5938 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5939 {
   5940   slotbuf[0] = 0x1;
   5941 }
   5942 
   5943 static void
   5944 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5945 {
   5946   slotbuf[0] = 0x2;
   5947 }
   5948 
   5949 static void
   5950 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5951 {
   5952   slotbuf[0] = 0xa002;
   5953 }
   5954 
   5955 static void
   5956 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5957 {
   5958   slotbuf[0] = 0x830000;
   5959 }
   5960 
   5961 static void
   5962 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5963 {
   5964   slotbuf[0] = 0x930000;
   5965 }
   5966 
   5967 static void
   5968 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5969 {
   5970   slotbuf[0] = 0xa30000;
   5971 }
   5972 
   5973 static void
   5974 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5975 {
   5976   slotbuf[0] = 0xb30000;
   5977 }
   5978 
   5979 static void
   5980 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5981 {
   5982   slotbuf[0] = 0x600000;
   5983 }
   5984 
   5985 static void
   5986 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5987 {
   5988   slotbuf[0] = 0x600100;
   5989 }
   5990 
   5991 static void
   5992 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5993 {
   5994   slotbuf[0] = 0x20f0;
   5995 }
   5996 
   5997 static void
   5998 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
   5999 {
   6000   slotbuf[0] = 0x80;
   6001 }
   6002 
   6003 static void
   6004 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6005 {
   6006   slotbuf[0] = 0x5100;
   6007 }
   6008 
   6009 static void
   6010 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6011 {
   6012   slotbuf[0] = 0x5002;
   6013 }
   6014 
   6015 static void
   6016 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6017 {
   6018   slotbuf[0] = 0x6002;
   6019 }
   6020 
   6021 static void
   6022 Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6023 {
   6024   slotbuf[0] = 0x590000;
   6025 }
   6026 
   6027 static void
   6028 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6029 {
   6030   slotbuf[0] = 0x4002;
   6031 }
   6032 
   6033 static void
   6034 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6035 {
   6036   slotbuf[0] = 0x400000;
   6037 }
   6038 
   6039 static void
   6040 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6041 {
   6042   slotbuf[0] = 0x401000;
   6043 }
   6044 
   6045 static void
   6046 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6047 {
   6048   slotbuf[0] = 0x402000;
   6049 }
   6050 
   6051 static void
   6052 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6053 {
   6054   slotbuf[0] = 0x403000;
   6055 }
   6056 
   6057 static void
   6058 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6059 {
   6060   slotbuf[0] = 0x404000;
   6061 }
   6062 
   6063 static void
   6064 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6065 {
   6066   slotbuf[0] = 0xa10000;
   6067 }
   6068 
   6069 static void
   6070 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6071 {
   6072   slotbuf[0] = 0x810000;
   6073 }
   6074 
   6075 static void
   6076 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6077 {
   6078   slotbuf[0] = 0x910000;
   6079 }
   6080 
   6081 static void
   6082 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6083 {
   6084   slotbuf[0] = 0xb10000;
   6085 }
   6086 
   6087 static void
   6088 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6089 {
   6090   slotbuf[0] = 0x10000;
   6091 }
   6092 
   6093 static void
   6094 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6095 {
   6096   slotbuf[0] = 0x210000;
   6097 }
   6098 
   6099 static void
   6100 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6101 {
   6102   slotbuf[0] = 0x410000;
   6103 }
   6104 
   6105 static void
   6106 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6107 {
   6108   slotbuf[0] = 0x20c0;
   6109 }
   6110 
   6111 static void
   6112 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6113 {
   6114   slotbuf[0] = 0x20d0;
   6115 }
   6116 
   6117 static void
   6118 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6119 {
   6120   slotbuf[0] = 0x2000;
   6121 }
   6122 
   6123 static void
   6124 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6125 {
   6126   slotbuf[0] = 0x2010;
   6127 }
   6128 
   6129 static void
   6130 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6131 {
   6132   slotbuf[0] = 0x2020;
   6133 }
   6134 
   6135 static void
   6136 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6137 {
   6138   slotbuf[0] = 0x2030;
   6139 }
   6140 
   6141 static void
   6142 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6143 {
   6144   slotbuf[0] = 0x6000;
   6145 }
   6146 
   6147 static void
   6148 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6149 {
   6150   slotbuf[0] = 0x30300;
   6151 }
   6152 
   6153 static void
   6154 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6155 {
   6156   slotbuf[0] = 0x130300;
   6157 }
   6158 
   6159 static void
   6160 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6161 {
   6162   slotbuf[0] = 0x610300;
   6163 }
   6164 
   6165 static void
   6166 Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6167 {
   6168   slotbuf[0] = 0x36100;
   6169 }
   6170 
   6171 static void
   6172 Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6173 {
   6174   slotbuf[0] = 0x136100;
   6175 }
   6176 
   6177 static void
   6178 Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6179 {
   6180   slotbuf[0] = 0x616100;
   6181 }
   6182 
   6183 static void
   6184 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6185 {
   6186   slotbuf[0] = 0x30500;
   6187 }
   6188 
   6189 static void
   6190 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6191 {
   6192   slotbuf[0] = 0x130500;
   6193 }
   6194 
   6195 static void
   6196 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6197 {
   6198   slotbuf[0] = 0x610500;
   6199 }
   6200 
   6201 static void
   6202 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6203 {
   6204   slotbuf[0] = 0x3b000;
   6205 }
   6206 
   6207 static void
   6208 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6209 {
   6210   slotbuf[0] = 0x13b000;
   6211 }
   6212 
   6213 static void
   6214 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6215 {
   6216   slotbuf[0] = 0x3d000;
   6217 }
   6218 
   6219 static void
   6220 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6221 {
   6222   slotbuf[0] = 0x3e600;
   6223 }
   6224 
   6225 static void
   6226 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6227 {
   6228   slotbuf[0] = 0x13e600;
   6229 }
   6230 
   6231 static void
   6232 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6233 {
   6234   slotbuf[0] = 0x61e600;
   6235 }
   6236 
   6237 static void
   6238 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6239 {
   6240   slotbuf[0] = 0x3b100;
   6241 }
   6242 
   6243 static void
   6244 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6245 {
   6246   slotbuf[0] = 0x13b100;
   6247 }
   6248 
   6249 static void
   6250 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6251 {
   6252   slotbuf[0] = 0x61b100;
   6253 }
   6254 
   6255 static void
   6256 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6257 {
   6258   slotbuf[0] = 0x3d100;
   6259 }
   6260 
   6261 static void
   6262 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6263 {
   6264   slotbuf[0] = 0x13d100;
   6265 }
   6266 
   6267 static void
   6268 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6269 {
   6270   slotbuf[0] = 0x61d100;
   6271 }
   6272 
   6273 static void
   6274 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6275 {
   6276   slotbuf[0] = 0x3b200;
   6277 }
   6278 
   6279 static void
   6280 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6281 {
   6282   slotbuf[0] = 0x13b200;
   6283 }
   6284 
   6285 static void
   6286 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6287 {
   6288   slotbuf[0] = 0x61b200;
   6289 }
   6290 
   6291 static void
   6292 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6293 {
   6294   slotbuf[0] = 0x3d200;
   6295 }
   6296 
   6297 static void
   6298 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6299 {
   6300   slotbuf[0] = 0x13d200;
   6301 }
   6302 
   6303 static void
   6304 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6305 {
   6306   slotbuf[0] = 0x61d200;
   6307 }
   6308 
   6309 static void
   6310 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6311 {
   6312   slotbuf[0] = 0x3b300;
   6313 }
   6314 
   6315 static void
   6316 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6317 {
   6318   slotbuf[0] = 0x13b300;
   6319 }
   6320 
   6321 static void
   6322 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6323 {
   6324   slotbuf[0] = 0x61b300;
   6325 }
   6326 
   6327 static void
   6328 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6329 {
   6330   slotbuf[0] = 0x3d300;
   6331 }
   6332 
   6333 static void
   6334 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6335 {
   6336   slotbuf[0] = 0x13d300;
   6337 }
   6338 
   6339 static void
   6340 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6341 {
   6342   slotbuf[0] = 0x61d300;
   6343 }
   6344 
   6345 static void
   6346 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6347 {
   6348   slotbuf[0] = 0x3b400;
   6349 }
   6350 
   6351 static void
   6352 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6353 {
   6354   slotbuf[0] = 0x13b400;
   6355 }
   6356 
   6357 static void
   6358 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6359 {
   6360   slotbuf[0] = 0x61b400;
   6361 }
   6362 
   6363 static void
   6364 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6365 {
   6366   slotbuf[0] = 0x3d400;
   6367 }
   6368 
   6369 static void
   6370 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6371 {
   6372   slotbuf[0] = 0x13d400;
   6373 }
   6374 
   6375 static void
   6376 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6377 {
   6378   slotbuf[0] = 0x61d400;
   6379 }
   6380 
   6381 static void
   6382 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6383 {
   6384   slotbuf[0] = 0x3b500;
   6385 }
   6386 
   6387 static void
   6388 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6389 {
   6390   slotbuf[0] = 0x13b500;
   6391 }
   6392 
   6393 static void
   6394 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6395 {
   6396   slotbuf[0] = 0x61b500;
   6397 }
   6398 
   6399 static void
   6400 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6401 {
   6402   slotbuf[0] = 0x3d500;
   6403 }
   6404 
   6405 static void
   6406 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6407 {
   6408   slotbuf[0] = 0x13d500;
   6409 }
   6410 
   6411 static void
   6412 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6413 {
   6414   slotbuf[0] = 0x61d500;
   6415 }
   6416 
   6417 static void
   6418 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6419 {
   6420   slotbuf[0] = 0x3b600;
   6421 }
   6422 
   6423 static void
   6424 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6425 {
   6426   slotbuf[0] = 0x13b600;
   6427 }
   6428 
   6429 static void
   6430 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6431 {
   6432   slotbuf[0] = 0x61b600;
   6433 }
   6434 
   6435 static void
   6436 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6437 {
   6438   slotbuf[0] = 0x3d600;
   6439 }
   6440 
   6441 static void
   6442 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6443 {
   6444   slotbuf[0] = 0x13d600;
   6445 }
   6446 
   6447 static void
   6448 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6449 {
   6450   slotbuf[0] = 0x61d600;
   6451 }
   6452 
   6453 static void
   6454 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6455 {
   6456   slotbuf[0] = 0x3b700;
   6457 }
   6458 
   6459 static void
   6460 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6461 {
   6462   slotbuf[0] = 0x13b700;
   6463 }
   6464 
   6465 static void
   6466 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6467 {
   6468   slotbuf[0] = 0x61b700;
   6469 }
   6470 
   6471 static void
   6472 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6473 {
   6474   slotbuf[0] = 0x3d700;
   6475 }
   6476 
   6477 static void
   6478 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6479 {
   6480   slotbuf[0] = 0x13d700;
   6481 }
   6482 
   6483 static void
   6484 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6485 {
   6486   slotbuf[0] = 0x61d700;
   6487 }
   6488 
   6489 static void
   6490 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6491 {
   6492   slotbuf[0] = 0x3c200;
   6493 }
   6494 
   6495 static void
   6496 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6497 {
   6498   slotbuf[0] = 0x13c200;
   6499 }
   6500 
   6501 static void
   6502 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6503 {
   6504   slotbuf[0] = 0x61c200;
   6505 }
   6506 
   6507 static void
   6508 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6509 {
   6510   slotbuf[0] = 0x3c300;
   6511 }
   6512 
   6513 static void
   6514 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6515 {
   6516   slotbuf[0] = 0x13c300;
   6517 }
   6518 
   6519 static void
   6520 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6521 {
   6522   slotbuf[0] = 0x61c300;
   6523 }
   6524 
   6525 static void
   6526 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6527 {
   6528   slotbuf[0] = 0x3c400;
   6529 }
   6530 
   6531 static void
   6532 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6533 {
   6534   slotbuf[0] = 0x13c400;
   6535 }
   6536 
   6537 static void
   6538 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6539 {
   6540   slotbuf[0] = 0x61c400;
   6541 }
   6542 
   6543 static void
   6544 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6545 {
   6546   slotbuf[0] = 0x3c500;
   6547 }
   6548 
   6549 static void
   6550 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6551 {
   6552   slotbuf[0] = 0x13c500;
   6553 }
   6554 
   6555 static void
   6556 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6557 {
   6558   slotbuf[0] = 0x61c500;
   6559 }
   6560 
   6561 static void
   6562 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6563 {
   6564   slotbuf[0] = 0x3c600;
   6565 }
   6566 
   6567 static void
   6568 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6569 {
   6570   slotbuf[0] = 0x13c600;
   6571 }
   6572 
   6573 static void
   6574 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6575 {
   6576   slotbuf[0] = 0x61c600;
   6577 }
   6578 
   6579 static void
   6580 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6581 {
   6582   slotbuf[0] = 0x3c700;
   6583 }
   6584 
   6585 static void
   6586 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6587 {
   6588   slotbuf[0] = 0x13c700;
   6589 }
   6590 
   6591 static void
   6592 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6593 {
   6594   slotbuf[0] = 0x61c700;
   6595 }
   6596 
   6597 static void
   6598 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6599 {
   6600   slotbuf[0] = 0x3ee00;
   6601 }
   6602 
   6603 static void
   6604 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6605 {
   6606   slotbuf[0] = 0x13ee00;
   6607 }
   6608 
   6609 static void
   6610 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6611 {
   6612   slotbuf[0] = 0x61ee00;
   6613 }
   6614 
   6615 static void
   6616 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6617 {
   6618   slotbuf[0] = 0x3c000;
   6619 }
   6620 
   6621 static void
   6622 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6623 {
   6624   slotbuf[0] = 0x13c000;
   6625 }
   6626 
   6627 static void
   6628 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6629 {
   6630   slotbuf[0] = 0x61c000;
   6631 }
   6632 
   6633 static void
   6634 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6635 {
   6636   slotbuf[0] = 0x3e800;
   6637 }
   6638 
   6639 static void
   6640 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6641 {
   6642   slotbuf[0] = 0x13e800;
   6643 }
   6644 
   6645 static void
   6646 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6647 {
   6648   slotbuf[0] = 0x61e800;
   6649 }
   6650 
   6651 static void
   6652 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6653 {
   6654   slotbuf[0] = 0x3f400;
   6655 }
   6656 
   6657 static void
   6658 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6659 {
   6660   slotbuf[0] = 0x13f400;
   6661 }
   6662 
   6663 static void
   6664 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6665 {
   6666   slotbuf[0] = 0x61f400;
   6667 }
   6668 
   6669 static void
   6670 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6671 {
   6672   slotbuf[0] = 0x3f500;
   6673 }
   6674 
   6675 static void
   6676 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6677 {
   6678   slotbuf[0] = 0x13f500;
   6679 }
   6680 
   6681 static void
   6682 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6683 {
   6684   slotbuf[0] = 0x61f500;
   6685 }
   6686 
   6687 static void
   6688 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6689 {
   6690   slotbuf[0] = 0x3eb00;
   6691 }
   6692 
   6693 static void
   6694 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6695 {
   6696   slotbuf[0] = 0x3e700;
   6697 }
   6698 
   6699 static void
   6700 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6701 {
   6702   slotbuf[0] = 0x13e700;
   6703 }
   6704 
   6705 static void
   6706 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6707 {
   6708   slotbuf[0] = 0x61e700;
   6709 }
   6710 
   6711 static void
   6712 Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6713 {
   6714   slotbuf[0] = 0x720000;
   6715 }
   6716 
   6717 static void
   6718 Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6719 {
   6720   slotbuf[0] = 0x620000;
   6721 }
   6722 
   6723 static void
   6724 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6725 {
   6726   slotbuf[0] = 0xc10000;
   6727 }
   6728 
   6729 static void
   6730 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6731 {
   6732   slotbuf[0] = 0xd10000;
   6733 }
   6734 
   6735 static void
   6736 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6737 {
   6738   slotbuf[0] = 0x820000;
   6739 }
   6740 
   6741 static void
   6742 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6743 {
   6744   slotbuf[0] = 0x3010;
   6745 }
   6746 
   6747 static void
   6748 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6749 {
   6750   slotbuf[0] = 0x7000;
   6751 }
   6752 
   6753 static void
   6754 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6755 {
   6756   slotbuf[0] = 0x3e200;
   6757 }
   6758 
   6759 static void
   6760 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6761 {
   6762   slotbuf[0] = 0x13e200;
   6763 }
   6764 
   6765 static void
   6766 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6767 {
   6768   slotbuf[0] = 0x13e300;
   6769 }
   6770 
   6771 static void
   6772 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6773 {
   6774   slotbuf[0] = 0x3e400;
   6775 }
   6776 
   6777 static void
   6778 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6779 {
   6780   slotbuf[0] = 0x13e400;
   6781 }
   6782 
   6783 static void
   6784 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6785 {
   6786   slotbuf[0] = 0x61e400;
   6787 }
   6788 
   6789 static void
   6790 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6791 {
   6792   slotbuf[0] = 0x4000;
   6793 }
   6794 
   6795 static void
   6796 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   6797 {
   6798   slotbuf[0] = 0xf02d;
   6799 }
   6800 
   6801 static void
   6802 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6803 {
   6804   slotbuf[0] = 0x39000;
   6805 }
   6806 
   6807 static void
   6808 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6809 {
   6810   slotbuf[0] = 0x139000;
   6811 }
   6812 
   6813 static void
   6814 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6815 {
   6816   slotbuf[0] = 0x619000;
   6817 }
   6818 
   6819 static void
   6820 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6821 {
   6822   slotbuf[0] = 0x3a000;
   6823 }
   6824 
   6825 static void
   6826 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6827 {
   6828   slotbuf[0] = 0x13a000;
   6829 }
   6830 
   6831 static void
   6832 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6833 {
   6834   slotbuf[0] = 0x61a000;
   6835 }
   6836 
   6837 static void
   6838 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6839 {
   6840   slotbuf[0] = 0x39100;
   6841 }
   6842 
   6843 static void
   6844 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6845 {
   6846   slotbuf[0] = 0x139100;
   6847 }
   6848 
   6849 static void
   6850 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6851 {
   6852   slotbuf[0] = 0x619100;
   6853 }
   6854 
   6855 static void
   6856 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6857 {
   6858   slotbuf[0] = 0x3a100;
   6859 }
   6860 
   6861 static void
   6862 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6863 {
   6864   slotbuf[0] = 0x13a100;
   6865 }
   6866 
   6867 static void
   6868 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6869 {
   6870   slotbuf[0] = 0x61a100;
   6871 }
   6872 
   6873 static void
   6874 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6875 {
   6876   slotbuf[0] = 0x38000;
   6877 }
   6878 
   6879 static void
   6880 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6881 {
   6882   slotbuf[0] = 0x138000;
   6883 }
   6884 
   6885 static void
   6886 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6887 {
   6888   slotbuf[0] = 0x618000;
   6889 }
   6890 
   6891 static void
   6892 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6893 {
   6894   slotbuf[0] = 0x38100;
   6895 }
   6896 
   6897 static void
   6898 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6899 {
   6900   slotbuf[0] = 0x138100;
   6901 }
   6902 
   6903 static void
   6904 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6905 {
   6906   slotbuf[0] = 0x618100;
   6907 }
   6908 
   6909 static void
   6910 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6911 {
   6912   slotbuf[0] = 0x36000;
   6913 }
   6914 
   6915 static void
   6916 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6917 {
   6918   slotbuf[0] = 0x136000;
   6919 }
   6920 
   6921 static void
   6922 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6923 {
   6924   slotbuf[0] = 0x616000;
   6925 }
   6926 
   6927 static void
   6928 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6929 {
   6930   slotbuf[0] = 0x3e900;
   6931 }
   6932 
   6933 static void
   6934 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6935 {
   6936   slotbuf[0] = 0x13e900;
   6937 }
   6938 
   6939 static void
   6940 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6941 {
   6942   slotbuf[0] = 0x61e900;
   6943 }
   6944 
   6945 static void
   6946 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6947 {
   6948   slotbuf[0] = 0x3ec00;
   6949 }
   6950 
   6951 static void
   6952 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6953 {
   6954   slotbuf[0] = 0x13ec00;
   6955 }
   6956 
   6957 static void
   6958 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6959 {
   6960   slotbuf[0] = 0x61ec00;
   6961 }
   6962 
   6963 static void
   6964 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6965 {
   6966   slotbuf[0] = 0x3ed00;
   6967 }
   6968 
   6969 static void
   6970 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6971 {
   6972   slotbuf[0] = 0x13ed00;
   6973 }
   6974 
   6975 static void
   6976 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6977 {
   6978   slotbuf[0] = 0x61ed00;
   6979 }
   6980 
   6981 static void
   6982 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6983 {
   6984   slotbuf[0] = 0x36800;
   6985 }
   6986 
   6987 static void
   6988 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6989 {
   6990   slotbuf[0] = 0x136800;
   6991 }
   6992 
   6993 static void
   6994 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6995 {
   6996   slotbuf[0] = 0x616800;
   6997 }
   6998 
   6999 static void
   7000 Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7001 {
   7002   slotbuf[0] = 0x70e0;
   7003 }
   7004 
   7005 static void
   7006 Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7007 {
   7008   slotbuf[0] = 0x70f0;
   7009 }
   7010 
   7011 static void
   7012 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7013 {
   7014   slotbuf[0] = 0xf1e000;
   7015 }
   7016 
   7017 static void
   7018 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7019 {
   7020   slotbuf[0] = 0xf1e010;
   7021 }
   7022 
   7023 static void
   7024 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7025 {
   7026   slotbuf[0] = 0x135900;
   7027 }
   7028 
   7029 static void
   7030 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7031 {
   7032   slotbuf[0] = 0x3ea00;
   7033 }
   7034 
   7035 static void
   7036 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7037 {
   7038   slotbuf[0] = 0x13ea00;
   7039 }
   7040 
   7041 static void
   7042 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7043 {
   7044   slotbuf[0] = 0x61ea00;
   7045 }
   7046 
   7047 static void
   7048 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7049 {
   7050   slotbuf[0] = 0x3f000;
   7051 }
   7052 
   7053 static void
   7054 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7055 {
   7056   slotbuf[0] = 0x13f000;
   7057 }
   7058 
   7059 static void
   7060 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7061 {
   7062   slotbuf[0] = 0x61f000;
   7063 }
   7064 
   7065 static void
   7066 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7067 {
   7068   slotbuf[0] = 0x3f100;
   7069 }
   7070 
   7071 static void
   7072 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7073 {
   7074   slotbuf[0] = 0x13f100;
   7075 }
   7076 
   7077 static void
   7078 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7079 {
   7080   slotbuf[0] = 0x61f100;
   7081 }
   7082 
   7083 static void
   7084 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7085 {
   7086   slotbuf[0] = 0x3f200;
   7087 }
   7088 
   7089 static void
   7090 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7091 {
   7092   slotbuf[0] = 0x13f200;
   7093 }
   7094 
   7095 static void
   7096 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7097 {
   7098   slotbuf[0] = 0x61f200;
   7099 }
   7100 
   7101 static void
   7102 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7103 {
   7104   slotbuf[0] = 0x50c000;
   7105 }
   7106 
   7107 static void
   7108 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7109 {
   7110   slotbuf[0] = 0x50d000;
   7111 }
   7112 
   7113 static void
   7114 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7115 {
   7116   slotbuf[0] = 0x50b000;
   7117 }
   7118 
   7119 static void
   7120 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7121 {
   7122   slotbuf[0] = 0x50f000;
   7123 }
   7124 
   7125 static void
   7126 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7127 {
   7128   slotbuf[0] = 0x50e000;
   7129 }
   7130 
   7131 static void
   7132 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7133 {
   7134   slotbuf[0] = 0x504000;
   7135 }
   7136 
   7137 static void
   7138 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7139 {
   7140   slotbuf[0] = 0x505000;
   7141 }
   7142 
   7143 static void
   7144 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7145 {
   7146   slotbuf[0] = 0x503000;
   7147 }
   7148 
   7149 static void
   7150 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7151 {
   7152   slotbuf[0] = 0x507000;
   7153 }
   7154 
   7155 static void
   7156 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7157 {
   7158   slotbuf[0] = 0x506000;
   7159 }
   7160 
   7161 static void
   7162 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7163 {
   7164   slotbuf[0] = 0x430000;
   7165 }
   7166 
   7167 static void
   7168 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7169 {
   7170   slotbuf[0] = 0x530000;
   7171 }
   7172 
   7173 static void
   7174 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7175 {
   7176   slotbuf[0] = 0x630000;
   7177 }
   7178 
   7179 static void
   7180 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7181 {
   7182   slotbuf[0] = 0x730000;
   7183 }
   7184 
   7185 static void
   7186 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7187 {
   7188   slotbuf[0] = 0x40e000;
   7189 }
   7190 
   7191 static void
   7192 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7193 {
   7194   slotbuf[0] = 0x40f000;
   7195 }
   7196 
   7197 static void
   7198 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7199 {
   7200   slotbuf[0] = 0x230000;
   7201 }
   7202 
   7203 static void
   7204 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7205 {
   7206   slotbuf[0] = 0xb002;
   7207 }
   7208 
   7209 static void
   7210 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7211 {
   7212   slotbuf[0] = 0xf002;
   7213 }
   7214 
   7215 static void
   7216 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7217 {
   7218   slotbuf[0] = 0xe002;
   7219 }
   7220 
   7221 static void
   7222 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7223 {
   7224   slotbuf[0] = 0x30c00;
   7225 }
   7226 
   7227 static void
   7228 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7229 {
   7230   slotbuf[0] = 0x130c00;
   7231 }
   7232 
   7233 static void
   7234 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7235 {
   7236   slotbuf[0] = 0x610c00;
   7237 }
   7238 
   7239 static void
   7240 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7241 {
   7242   slotbuf[0] = 0x36300;
   7243 }
   7244 
   7245 static void
   7246 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7247 {
   7248   slotbuf[0] = 0x136300;
   7249 }
   7250 
   7251 static void
   7252 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7253 {
   7254   slotbuf[0] = 0x616300;
   7255 }
   7256 
   7257 static void
   7258 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7259 {
   7260   slotbuf[0] = 0xc20000;
   7261 }
   7262 
   7263 static void
   7264 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7265 {
   7266   slotbuf[0] = 0xd20000;
   7267 }
   7268 
   7269 static void
   7270 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7271 {
   7272   slotbuf[0] = 0xe20000;
   7273 }
   7274 
   7275 static void
   7276 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7277 {
   7278   slotbuf[0] = 0xf20000;
   7279 }
   7280 
   7281 static void
   7282 Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7283 {
   7284   slotbuf[0] = 0x35f00;
   7285 }
   7286 
   7287 static void
   7288 Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7289 {
   7290   slotbuf[0] = 0x135f00;
   7291 }
   7292 
   7293 static void
   7294 Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7295 {
   7296   slotbuf[0] = 0x615f00;
   7297 }
   7298 
   7299 static void
   7300 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7301 {
   7302   slotbuf[0] = 0x406000;
   7303 }
   7304 
   7305 static void
   7306 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7307 {
   7308   slotbuf[0] = 0x407000;
   7309 }
   7310 
   7311 static void
   7312 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7313 {
   7314   slotbuf[0] = 0xe30e60;
   7315 }
   7316 
   7317 static void
   7318 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7319 {
   7320   slotbuf[0] = 0xf3e600;
   7321 }
   7322 
   7323 static void
   7324 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7325 {
   7326   slotbuf[0] = 0xe0000;
   7327 }
   7328 
   7329 static void
   7330 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7331 {
   7332   slotbuf[0] = 0xe1000;
   7333 }
   7334 
   7335 static void
   7336 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7337 {
   7338   slotbuf[0] = 0xe1200;
   7339 }
   7340 
   7341 static void
   7342 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7343 {
   7344   slotbuf[0] = 0xe2000;
   7345 }
   7346 
   7347 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
   7348   Opcode_excw_Slot_inst_encode, 0, 0
   7349 };
   7350 
   7351 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
   7352   Opcode_rfe_Slot_inst_encode, 0, 0
   7353 };
   7354 
   7355 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
   7356   Opcode_rfde_Slot_inst_encode, 0, 0
   7357 };
   7358 
   7359 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
   7360   Opcode_syscall_Slot_inst_encode, 0, 0
   7361 };
   7362 
   7363 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
   7364   Opcode_call12_Slot_inst_encode, 0, 0
   7365 };
   7366 
   7367 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
   7368   Opcode_call8_Slot_inst_encode, 0, 0
   7369 };
   7370 
   7371 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
   7372   Opcode_call4_Slot_inst_encode, 0, 0
   7373 };
   7374 
   7375 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
   7376   Opcode_callx12_Slot_inst_encode, 0, 0
   7377 };
   7378 
   7379 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
   7380   Opcode_callx8_Slot_inst_encode, 0, 0
   7381 };
   7382 
   7383 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
   7384   Opcode_callx4_Slot_inst_encode, 0, 0
   7385 };
   7386 
   7387 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
   7388   Opcode_entry_Slot_inst_encode, 0, 0
   7389 };
   7390 
   7391 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
   7392   Opcode_movsp_Slot_inst_encode, 0, 0
   7393 };
   7394 
   7395 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
   7396   Opcode_rotw_Slot_inst_encode, 0, 0
   7397 };
   7398 
   7399 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
   7400   Opcode_retw_Slot_inst_encode, 0, 0
   7401 };
   7402 
   7403 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
   7404   0, 0, Opcode_retw_n_Slot_inst16b_encode
   7405 };
   7406 
   7407 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
   7408   Opcode_rfwo_Slot_inst_encode, 0, 0
   7409 };
   7410 
   7411 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
   7412   Opcode_rfwu_Slot_inst_encode, 0, 0
   7413 };
   7414 
   7415 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
   7416   Opcode_l32e_Slot_inst_encode, 0, 0
   7417 };
   7418 
   7419 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
   7420   Opcode_s32e_Slot_inst_encode, 0, 0
   7421 };
   7422 
   7423 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
   7424   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
   7425 };
   7426 
   7427 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
   7428   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
   7429 };
   7430 
   7431 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
   7432   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
   7433 };
   7434 
   7435 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
   7436   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
   7437 };
   7438 
   7439 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
   7440   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
   7441 };
   7442 
   7443 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
   7444   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
   7445 };
   7446 
   7447 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
   7448   0, Opcode_add_n_Slot_inst16a_encode, 0
   7449 };
   7450 
   7451 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
   7452   0, Opcode_addi_n_Slot_inst16a_encode, 0
   7453 };
   7454 
   7455 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
   7456   0, 0, Opcode_beqz_n_Slot_inst16b_encode
   7457 };
   7458 
   7459 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
   7460   0, 0, Opcode_bnez_n_Slot_inst16b_encode
   7461 };
   7462 
   7463 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
   7464   0, 0, Opcode_ill_n_Slot_inst16b_encode
   7465 };
   7466 
   7467 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
   7468   0, Opcode_l32i_n_Slot_inst16a_encode, 0
   7469 };
   7470 
   7471 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
   7472   0, 0, Opcode_mov_n_Slot_inst16b_encode
   7473 };
   7474 
   7475 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
   7476   0, 0, Opcode_movi_n_Slot_inst16b_encode
   7477 };
   7478 
   7479 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
   7480   0, 0, Opcode_nop_n_Slot_inst16b_encode
   7481 };
   7482 
   7483 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
   7484   0, 0, Opcode_ret_n_Slot_inst16b_encode
   7485 };
   7486 
   7487 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
   7488   0, Opcode_s32i_n_Slot_inst16a_encode, 0
   7489 };
   7490 
   7491 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
   7492   Opcode_addi_Slot_inst_encode, 0, 0
   7493 };
   7494 
   7495 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
   7496   Opcode_addmi_Slot_inst_encode, 0, 0
   7497 };
   7498 
   7499 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
   7500   Opcode_add_Slot_inst_encode, 0, 0
   7501 };
   7502 
   7503 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
   7504   Opcode_sub_Slot_inst_encode, 0, 0
   7505 };
   7506 
   7507 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
   7508   Opcode_addx2_Slot_inst_encode, 0, 0
   7509 };
   7510 
   7511 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
   7512   Opcode_addx4_Slot_inst_encode, 0, 0
   7513 };
   7514 
   7515 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
   7516   Opcode_addx8_Slot_inst_encode, 0, 0
   7517 };
   7518 
   7519 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
   7520   Opcode_subx2_Slot_inst_encode, 0, 0
   7521 };
   7522 
   7523 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
   7524   Opcode_subx4_Slot_inst_encode, 0, 0
   7525 };
   7526 
   7527 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
   7528   Opcode_subx8_Slot_inst_encode, 0, 0
   7529 };
   7530 
   7531 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
   7532   Opcode_and_Slot_inst_encode, 0, 0
   7533 };
   7534 
   7535 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
   7536   Opcode_or_Slot_inst_encode, 0, 0
   7537 };
   7538 
   7539 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
   7540   Opcode_xor_Slot_inst_encode, 0, 0
   7541 };
   7542 
   7543 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
   7544   Opcode_beqi_Slot_inst_encode, 0, 0
   7545 };
   7546 
   7547 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
   7548   Opcode_bnei_Slot_inst_encode, 0, 0
   7549 };
   7550 
   7551 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
   7552   Opcode_bgei_Slot_inst_encode, 0, 0
   7553 };
   7554 
   7555 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
   7556   Opcode_blti_Slot_inst_encode, 0, 0
   7557 };
   7558 
   7559 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
   7560   Opcode_bbci_Slot_inst_encode, 0, 0
   7561 };
   7562 
   7563 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
   7564   Opcode_bbsi_Slot_inst_encode, 0, 0
   7565 };
   7566 
   7567 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
   7568   Opcode_bgeui_Slot_inst_encode, 0, 0
   7569 };
   7570 
   7571 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
   7572   Opcode_bltui_Slot_inst_encode, 0, 0
   7573 };
   7574 
   7575 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
   7576   Opcode_beq_Slot_inst_encode, 0, 0
   7577 };
   7578 
   7579 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
   7580   Opcode_bne_Slot_inst_encode, 0, 0
   7581 };
   7582 
   7583 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
   7584   Opcode_bge_Slot_inst_encode, 0, 0
   7585 };
   7586 
   7587 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
   7588   Opcode_blt_Slot_inst_encode, 0, 0
   7589 };
   7590 
   7591 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
   7592   Opcode_bgeu_Slot_inst_encode, 0, 0
   7593 };
   7594 
   7595 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
   7596   Opcode_bltu_Slot_inst_encode, 0, 0
   7597 };
   7598 
   7599 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
   7600   Opcode_bany_Slot_inst_encode, 0, 0
   7601 };
   7602 
   7603 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
   7604   Opcode_bnone_Slot_inst_encode, 0, 0
   7605 };
   7606 
   7607 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
   7608   Opcode_ball_Slot_inst_encode, 0, 0
   7609 };
   7610 
   7611 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
   7612   Opcode_bnall_Slot_inst_encode, 0, 0
   7613 };
   7614 
   7615 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
   7616   Opcode_bbc_Slot_inst_encode, 0, 0
   7617 };
   7618 
   7619 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
   7620   Opcode_bbs_Slot_inst_encode, 0, 0
   7621 };
   7622 
   7623 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
   7624   Opcode_beqz_Slot_inst_encode, 0, 0
   7625 };
   7626 
   7627 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
   7628   Opcode_bnez_Slot_inst_encode, 0, 0
   7629 };
   7630 
   7631 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
   7632   Opcode_bgez_Slot_inst_encode, 0, 0
   7633 };
   7634 
   7635 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
   7636   Opcode_bltz_Slot_inst_encode, 0, 0
   7637 };
   7638 
   7639 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
   7640   Opcode_call0_Slot_inst_encode, 0, 0
   7641 };
   7642 
   7643 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
   7644   Opcode_callx0_Slot_inst_encode, 0, 0
   7645 };
   7646 
   7647 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
   7648   Opcode_extui_Slot_inst_encode, 0, 0
   7649 };
   7650 
   7651 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
   7652   Opcode_ill_Slot_inst_encode, 0, 0
   7653 };
   7654 
   7655 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
   7656   Opcode_j_Slot_inst_encode, 0, 0
   7657 };
   7658 
   7659 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
   7660   Opcode_jx_Slot_inst_encode, 0, 0
   7661 };
   7662 
   7663 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
   7664   Opcode_l16ui_Slot_inst_encode, 0, 0
   7665 };
   7666 
   7667 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
   7668   Opcode_l16si_Slot_inst_encode, 0, 0
   7669 };
   7670 
   7671 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
   7672   Opcode_l32i_Slot_inst_encode, 0, 0
   7673 };
   7674 
   7675 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
   7676   Opcode_l32r_Slot_inst_encode, 0, 0
   7677 };
   7678 
   7679 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
   7680   Opcode_l8ui_Slot_inst_encode, 0, 0
   7681 };
   7682 
   7683 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
   7684   Opcode_movi_Slot_inst_encode, 0, 0
   7685 };
   7686 
   7687 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
   7688   Opcode_moveqz_Slot_inst_encode, 0, 0
   7689 };
   7690 
   7691 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
   7692   Opcode_movnez_Slot_inst_encode, 0, 0
   7693 };
   7694 
   7695 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
   7696   Opcode_movltz_Slot_inst_encode, 0, 0
   7697 };
   7698 
   7699 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
   7700   Opcode_movgez_Slot_inst_encode, 0, 0
   7701 };
   7702 
   7703 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
   7704   Opcode_neg_Slot_inst_encode, 0, 0
   7705 };
   7706 
   7707 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
   7708   Opcode_abs_Slot_inst_encode, 0, 0
   7709 };
   7710 
   7711 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
   7712   Opcode_nop_Slot_inst_encode, 0, 0
   7713 };
   7714 
   7715 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
   7716   Opcode_ret_Slot_inst_encode, 0, 0
   7717 };
   7718 
   7719 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
   7720   Opcode_simcall_Slot_inst_encode, 0, 0
   7721 };
   7722 
   7723 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
   7724   Opcode_s16i_Slot_inst_encode, 0, 0
   7725 };
   7726 
   7727 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
   7728   Opcode_s32i_Slot_inst_encode, 0, 0
   7729 };
   7730 
   7731 static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
   7732   Opcode_s32nb_Slot_inst_encode, 0, 0
   7733 };
   7734 
   7735 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
   7736   Opcode_s8i_Slot_inst_encode, 0, 0
   7737 };
   7738 
   7739 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
   7740   Opcode_ssr_Slot_inst_encode, 0, 0
   7741 };
   7742 
   7743 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
   7744   Opcode_ssl_Slot_inst_encode, 0, 0
   7745 };
   7746 
   7747 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
   7748   Opcode_ssa8l_Slot_inst_encode, 0, 0
   7749 };
   7750 
   7751 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
   7752   Opcode_ssa8b_Slot_inst_encode, 0, 0
   7753 };
   7754 
   7755 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
   7756   Opcode_ssai_Slot_inst_encode, 0, 0
   7757 };
   7758 
   7759 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
   7760   Opcode_sll_Slot_inst_encode, 0, 0
   7761 };
   7762 
   7763 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
   7764   Opcode_src_Slot_inst_encode, 0, 0
   7765 };
   7766 
   7767 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
   7768   Opcode_srl_Slot_inst_encode, 0, 0
   7769 };
   7770 
   7771 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
   7772   Opcode_sra_Slot_inst_encode, 0, 0
   7773 };
   7774 
   7775 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
   7776   Opcode_slli_Slot_inst_encode, 0, 0
   7777 };
   7778 
   7779 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
   7780   Opcode_srai_Slot_inst_encode, 0, 0
   7781 };
   7782 
   7783 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
   7784   Opcode_srli_Slot_inst_encode, 0, 0
   7785 };
   7786 
   7787 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
   7788   Opcode_memw_Slot_inst_encode, 0, 0
   7789 };
   7790 
   7791 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
   7792   Opcode_extw_Slot_inst_encode, 0, 0
   7793 };
   7794 
   7795 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
   7796   Opcode_isync_Slot_inst_encode, 0, 0
   7797 };
   7798 
   7799 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
   7800   Opcode_rsync_Slot_inst_encode, 0, 0
   7801 };
   7802 
   7803 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
   7804   Opcode_esync_Slot_inst_encode, 0, 0
   7805 };
   7806 
   7807 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
   7808   Opcode_dsync_Slot_inst_encode, 0, 0
   7809 };
   7810 
   7811 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
   7812   Opcode_rsil_Slot_inst_encode, 0, 0
   7813 };
   7814 
   7815 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
   7816   Opcode_rsr_sar_Slot_inst_encode, 0, 0
   7817 };
   7818 
   7819 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
   7820   Opcode_wsr_sar_Slot_inst_encode, 0, 0
   7821 };
   7822 
   7823 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
   7824   Opcode_xsr_sar_Slot_inst_encode, 0, 0
   7825 };
   7826 
   7827 static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
   7828   Opcode_rsr_memctl_Slot_inst_encode, 0, 0
   7829 };
   7830 
   7831 static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
   7832   Opcode_wsr_memctl_Slot_inst_encode, 0, 0
   7833 };
   7834 
   7835 static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
   7836   Opcode_xsr_memctl_Slot_inst_encode, 0, 0
   7837 };
   7838 
   7839 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
   7840   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
   7841 };
   7842 
   7843 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
   7844   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
   7845 };
   7846 
   7847 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
   7848   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
   7849 };
   7850 
   7851 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
   7852   Opcode_rsr_configid0_Slot_inst_encode, 0, 0
   7853 };
   7854 
   7855 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
   7856   Opcode_wsr_configid0_Slot_inst_encode, 0, 0
   7857 };
   7858 
   7859 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
   7860   Opcode_rsr_configid1_Slot_inst_encode, 0, 0
   7861 };
   7862 
   7863 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
   7864   Opcode_rsr_ps_Slot_inst_encode, 0, 0
   7865 };
   7866 
   7867 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
   7868   Opcode_wsr_ps_Slot_inst_encode, 0, 0
   7869 };
   7870 
   7871 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
   7872   Opcode_xsr_ps_Slot_inst_encode, 0, 0
   7873 };
   7874 
   7875 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
   7876   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
   7877 };
   7878 
   7879 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
   7880   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
   7881 };
   7882 
   7883 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
   7884   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
   7885 };
   7886 
   7887 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
   7888   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
   7889 };
   7890 
   7891 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
   7892   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
   7893 };
   7894 
   7895 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
   7896   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
   7897 };
   7898 
   7899 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
   7900   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
   7901 };
   7902 
   7903 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
   7904   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
   7905 };
   7906 
   7907 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
   7908   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
   7909 };
   7910 
   7911 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
   7912   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
   7913 };
   7914 
   7915 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
   7916   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
   7917 };
   7918 
   7919 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
   7920   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
   7921 };
   7922 
   7923 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
   7924   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
   7925 };
   7926 
   7927 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
   7928   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
   7929 };
   7930 
   7931 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
   7932   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
   7933 };
   7934 
   7935 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
   7936   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
   7937 };
   7938 
   7939 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
   7940   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
   7941 };
   7942 
   7943 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
   7944   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
   7945 };
   7946 
   7947 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
   7948   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
   7949 };
   7950 
   7951 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
   7952   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
   7953 };
   7954 
   7955 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
   7956   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
   7957 };
   7958 
   7959 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
   7960   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
   7961 };
   7962 
   7963 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
   7964   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
   7965 };
   7966 
   7967 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
   7968   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
   7969 };
   7970 
   7971 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
   7972   Opcode_rsr_epc5_Slot_inst_encode, 0, 0
   7973 };
   7974 
   7975 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
   7976   Opcode_wsr_epc5_Slot_inst_encode, 0, 0
   7977 };
   7978 
   7979 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
   7980   Opcode_xsr_epc5_Slot_inst_encode, 0, 0
   7981 };
   7982 
   7983 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
   7984   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
   7985 };
   7986 
   7987 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
   7988   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
   7989 };
   7990 
   7991 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
   7992   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
   7993 };
   7994 
   7995 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
   7996   Opcode_rsr_epc6_Slot_inst_encode, 0, 0
   7997 };
   7998 
   7999 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
   8000   Opcode_wsr_epc6_Slot_inst_encode, 0, 0
   8001 };
   8002 
   8003 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
   8004   Opcode_xsr_epc6_Slot_inst_encode, 0, 0
   8005 };
   8006 
   8007 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
   8008   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
   8009 };
   8010 
   8011 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
   8012   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
   8013 };
   8014 
   8015 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
   8016   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
   8017 };
   8018 
   8019 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
   8020   Opcode_rsr_epc7_Slot_inst_encode, 0, 0
   8021 };
   8022 
   8023 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
   8024   Opcode_wsr_epc7_Slot_inst_encode, 0, 0
   8025 };
   8026 
   8027 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
   8028   Opcode_xsr_epc7_Slot_inst_encode, 0, 0
   8029 };
   8030 
   8031 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
   8032   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
   8033 };
   8034 
   8035 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
   8036   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
   8037 };
   8038 
   8039 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
   8040   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
   8041 };
   8042 
   8043 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
   8044   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
   8045 };
   8046 
   8047 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
   8048   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
   8049 };
   8050 
   8051 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
   8052   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
   8053 };
   8054 
   8055 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
   8056   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
   8057 };
   8058 
   8059 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
   8060   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
   8061 };
   8062 
   8063 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
   8064   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
   8065 };
   8066 
   8067 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
   8068   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
   8069 };
   8070 
   8071 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
   8072   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
   8073 };
   8074 
   8075 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
   8076   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
   8077 };
   8078 
   8079 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
   8080   Opcode_rsr_eps5_Slot_inst_encode, 0, 0
   8081 };
   8082 
   8083 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
   8084   Opcode_wsr_eps5_Slot_inst_encode, 0, 0
   8085 };
   8086 
   8087 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
   8088   Opcode_xsr_eps5_Slot_inst_encode, 0, 0
   8089 };
   8090 
   8091 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
   8092   Opcode_rsr_eps6_Slot_inst_encode, 0, 0
   8093 };
   8094 
   8095 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
   8096   Opcode_wsr_eps6_Slot_inst_encode, 0, 0
   8097 };
   8098 
   8099 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
   8100   Opcode_xsr_eps6_Slot_inst_encode, 0, 0
   8101 };
   8102 
   8103 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
   8104   Opcode_rsr_eps7_Slot_inst_encode, 0, 0
   8105 };
   8106 
   8107 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
   8108   Opcode_wsr_eps7_Slot_inst_encode, 0, 0
   8109 };
   8110 
   8111 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
   8112   Opcode_xsr_eps7_Slot_inst_encode, 0, 0
   8113 };
   8114 
   8115 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
   8116   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
   8117 };
   8118 
   8119 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
   8120   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
   8121 };
   8122 
   8123 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
   8124   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
   8125 };
   8126 
   8127 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
   8128   Opcode_rsr_depc_Slot_inst_encode, 0, 0
   8129 };
   8130 
   8131 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
   8132   Opcode_wsr_depc_Slot_inst_encode, 0, 0
   8133 };
   8134 
   8135 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
   8136   Opcode_xsr_depc_Slot_inst_encode, 0, 0
   8137 };
   8138 
   8139 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
   8140   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
   8141 };
   8142 
   8143 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
   8144   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
   8145 };
   8146 
   8147 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
   8148   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
   8149 };
   8150 
   8151 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
   8152   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
   8153 };
   8154 
   8155 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
   8156   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
   8157 };
   8158 
   8159 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
   8160   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
   8161 };
   8162 
   8163 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
   8164   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
   8165 };
   8166 
   8167 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
   8168   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
   8169 };
   8170 
   8171 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
   8172   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
   8173 };
   8174 
   8175 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
   8176   Opcode_rsr_prid_Slot_inst_encode, 0, 0
   8177 };
   8178 
   8179 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
   8180   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
   8181 };
   8182 
   8183 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
   8184   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
   8185 };
   8186 
   8187 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
   8188   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
   8189 };
   8190 
   8191 static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
   8192   Opcode_salt_Slot_inst_encode, 0, 0
   8193 };
   8194 
   8195 static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
   8196   Opcode_saltu_Slot_inst_encode, 0, 0
   8197 };
   8198 
   8199 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
   8200   Opcode_mul16u_Slot_inst_encode, 0, 0
   8201 };
   8202 
   8203 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
   8204   Opcode_mul16s_Slot_inst_encode, 0, 0
   8205 };
   8206 
   8207 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
   8208   Opcode_mull_Slot_inst_encode, 0, 0
   8209 };
   8210 
   8211 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
   8212   Opcode_rfi_Slot_inst_encode, 0, 0
   8213 };
   8214 
   8215 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
   8216   Opcode_waiti_Slot_inst_encode, 0, 0
   8217 };
   8218 
   8219 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
   8220   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
   8221 };
   8222 
   8223 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
   8224   Opcode_wsr_intset_Slot_inst_encode, 0, 0
   8225 };
   8226 
   8227 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
   8228   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
   8229 };
   8230 
   8231 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
   8232   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
   8233 };
   8234 
   8235 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
   8236   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
   8237 };
   8238 
   8239 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
   8240   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
   8241 };
   8242 
   8243 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
   8244   Opcode_break_Slot_inst_encode, 0, 0
   8245 };
   8246 
   8247 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
   8248   0, 0, Opcode_break_n_Slot_inst16b_encode
   8249 };
   8250 
   8251 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
   8252   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
   8253 };
   8254 
   8255 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
   8256   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
   8257 };
   8258 
   8259 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
   8260   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
   8261 };
   8262 
   8263 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
   8264   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
   8265 };
   8266 
   8267 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
   8268   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
   8269 };
   8270 
   8271 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
   8272   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
   8273 };
   8274 
   8275 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
   8276   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
   8277 };
   8278 
   8279 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
   8280   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
   8281 };
   8282 
   8283 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
   8284   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
   8285 };
   8286 
   8287 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
   8288   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
   8289 };
   8290 
   8291 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
   8292   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
   8293 };
   8294 
   8295 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
   8296   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
   8297 };
   8298 
   8299 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
   8300   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
   8301 };
   8302 
   8303 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
   8304   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
   8305 };
   8306 
   8307 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
   8308   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
   8309 };
   8310 
   8311 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
   8312   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
   8313 };
   8314 
   8315 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
   8316   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
   8317 };
   8318 
   8319 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
   8320   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
   8321 };
   8322 
   8323 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
   8324   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
   8325 };
   8326 
   8327 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
   8328   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
   8329 };
   8330 
   8331 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
   8332   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
   8333 };
   8334 
   8335 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
   8336   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
   8337 };
   8338 
   8339 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
   8340   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
   8341 };
   8342 
   8343 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
   8344   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
   8345 };
   8346 
   8347 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
   8348   Opcode_rsr_icount_Slot_inst_encode, 0, 0
   8349 };
   8350 
   8351 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
   8352   Opcode_wsr_icount_Slot_inst_encode, 0, 0
   8353 };
   8354 
   8355 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
   8356   Opcode_xsr_icount_Slot_inst_encode, 0, 0
   8357 };
   8358 
   8359 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
   8360   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
   8361 };
   8362 
   8363 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
   8364   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
   8365 };
   8366 
   8367 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
   8368   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
   8369 };
   8370 
   8371 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
   8372   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
   8373 };
   8374 
   8375 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
   8376   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
   8377 };
   8378 
   8379 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
   8380   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
   8381 };
   8382 
   8383 static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
   8384   Opcode_lddr32_p_Slot_inst_encode, 0, 0
   8385 };
   8386 
   8387 static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
   8388   Opcode_sddr32_p_Slot_inst_encode, 0, 0
   8389 };
   8390 
   8391 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
   8392   Opcode_rfdo_Slot_inst_encode, 0, 0
   8393 };
   8394 
   8395 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
   8396   Opcode_rfdd_Slot_inst_encode, 0, 0
   8397 };
   8398 
   8399 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
   8400   Opcode_wsr_mmid_Slot_inst_encode, 0, 0
   8401 };
   8402 
   8403 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
   8404   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
   8405 };
   8406 
   8407 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
   8408   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
   8409 };
   8410 
   8411 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
   8412   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
   8413 };
   8414 
   8415 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
   8416   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
   8417 };
   8418 
   8419 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
   8420   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
   8421 };
   8422 
   8423 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
   8424   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
   8425 };
   8426 
   8427 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
   8428   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
   8429 };
   8430 
   8431 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
   8432   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
   8433 };
   8434 
   8435 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
   8436   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
   8437 };
   8438 
   8439 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
   8440   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
   8441 };
   8442 
   8443 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
   8444   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
   8445 };
   8446 
   8447 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
   8448   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
   8449 };
   8450 
   8451 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
   8452   Opcode_idtlb_Slot_inst_encode, 0, 0
   8453 };
   8454 
   8455 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
   8456   Opcode_pdtlb_Slot_inst_encode, 0, 0
   8457 };
   8458 
   8459 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
   8460   Opcode_rdtlb0_Slot_inst_encode, 0, 0
   8461 };
   8462 
   8463 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
   8464   Opcode_rdtlb1_Slot_inst_encode, 0, 0
   8465 };
   8466 
   8467 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
   8468   Opcode_wdtlb_Slot_inst_encode, 0, 0
   8469 };
   8470 
   8471 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
   8472   Opcode_iitlb_Slot_inst_encode, 0, 0
   8473 };
   8474 
   8475 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
   8476   Opcode_pitlb_Slot_inst_encode, 0, 0
   8477 };
   8478 
   8479 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
   8480   Opcode_ritlb0_Slot_inst_encode, 0, 0
   8481 };
   8482 
   8483 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
   8484   Opcode_ritlb1_Slot_inst_encode, 0, 0
   8485 };
   8486 
   8487 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
   8488   Opcode_witlb_Slot_inst_encode, 0, 0
   8489 };
   8490 
   8491 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
   8492   Opcode_min_Slot_inst_encode, 0, 0
   8493 };
   8494 
   8495 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
   8496   Opcode_max_Slot_inst_encode, 0, 0
   8497 };
   8498 
   8499 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
   8500   Opcode_minu_Slot_inst_encode, 0, 0
   8501 };
   8502 
   8503 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
   8504   Opcode_maxu_Slot_inst_encode, 0, 0
   8505 };
   8506 
   8507 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
   8508   Opcode_nsa_Slot_inst_encode, 0, 0
   8509 };
   8510 
   8511 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
   8512   Opcode_nsau_Slot_inst_encode, 0, 0
   8513 };
   8514 
   8515 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
   8516   Opcode_sext_Slot_inst_encode, 0, 0
   8517 };
   8518 
   8519 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
   8520   Opcode_l32ai_Slot_inst_encode, 0, 0
   8521 };
   8522 
   8523 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
   8524   Opcode_s32ri_Slot_inst_encode, 0, 0
   8525 };
   8526 
   8527 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
   8528   Opcode_s32c1i_Slot_inst_encode, 0, 0
   8529 };
   8530 
   8531 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
   8532   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
   8533 };
   8534 
   8535 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
   8536   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
   8537 };
   8538 
   8539 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
   8540   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
   8541 };
   8542 
   8543 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
   8544   Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
   8545 };
   8546 
   8547 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
   8548   Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
   8549 };
   8550 
   8551 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
   8552   Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
   8553 };
   8554 
   8555 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
   8556   Opcode_quou_Slot_inst_encode, 0, 0
   8557 };
   8558 
   8559 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
   8560   Opcode_quos_Slot_inst_encode, 0, 0
   8561 };
   8562 
   8563 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
   8564   Opcode_remu_Slot_inst_encode, 0, 0
   8565 };
   8566 
   8567 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
   8568   Opcode_rems_Slot_inst_encode, 0, 0
   8569 };
   8570 
   8571 static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
   8572   Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
   8573 };
   8574 
   8575 static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
   8576   Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
   8577 };
   8578 
   8579 static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
   8580   Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
   8581 };
   8582 
   8583 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
   8584   Opcode_rer_Slot_inst_encode, 0, 0
   8585 };
   8586 
   8587 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
   8588   Opcode_wer_Slot_inst_encode, 0, 0
   8589 };
   8590 
   8591 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
   8592   Opcode_rur_expstate_Slot_inst_encode, 0, 0
   8593 };
   8594 
   8595 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
   8596   Opcode_wur_expstate_Slot_inst_encode, 0, 0
   8597 };
   8598 
   8599 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
   8600   Opcode_read_impwire_Slot_inst_encode, 0, 0
   8601 };
   8602 
   8603 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
   8604   Opcode_setb_expstate_Slot_inst_encode, 0, 0
   8605 };
   8606 
   8607 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
   8608   Opcode_clrb_expstate_Slot_inst_encode, 0, 0
   8609 };
   8610 
   8611 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
   8612   Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
   8613 };
   8614 
   8615 
   8616 
   8617 
   8618 
   8619 /* Opcode table.  */
   8620 
   8621 static xtensa_opcode_internal opcodes[] = {
   8622   { "excw", ICLASS_xt_iclass_excw,
   8623     0,
   8624     Opcode_excw_encode_fns, 0, 0 },
   8625   { "rfe", ICLASS_xt_iclass_rfe,
   8626     XTENSA_OPCODE_IS_JUMP,
   8627     Opcode_rfe_encode_fns, 0, 0 },
   8628   { "rfde", ICLASS_xt_iclass_rfde,
   8629     XTENSA_OPCODE_IS_JUMP,
   8630     Opcode_rfde_encode_fns, 0, 0 },
   8631   { "syscall", ICLASS_xt_iclass_syscall,
   8632     0,
   8633     Opcode_syscall_encode_fns, 0, 0 },
   8634   { "call12", ICLASS_xt_iclass_call12,
   8635     XTENSA_OPCODE_IS_CALL,
   8636     Opcode_call12_encode_fns, 0, 0 },
   8637   { "call8", ICLASS_xt_iclass_call8,
   8638     XTENSA_OPCODE_IS_CALL,
   8639     Opcode_call8_encode_fns, 0, 0 },
   8640   { "call4", ICLASS_xt_iclass_call4,
   8641     XTENSA_OPCODE_IS_CALL,
   8642     Opcode_call4_encode_fns, 0, 0 },
   8643   { "callx12", ICLASS_xt_iclass_callx12,
   8644     XTENSA_OPCODE_IS_CALL,
   8645     Opcode_callx12_encode_fns, 0, 0 },
   8646   { "callx8", ICLASS_xt_iclass_callx8,
   8647     XTENSA_OPCODE_IS_CALL,
   8648     Opcode_callx8_encode_fns, 0, 0 },
   8649   { "callx4", ICLASS_xt_iclass_callx4,
   8650     XTENSA_OPCODE_IS_CALL,
   8651     Opcode_callx4_encode_fns, 0, 0 },
   8652   { "entry", ICLASS_xt_iclass_entry,
   8653     0,
   8654     Opcode_entry_encode_fns, 0, 0 },
   8655   { "movsp", ICLASS_xt_iclass_movsp,
   8656     0,
   8657     Opcode_movsp_encode_fns, 0, 0 },
   8658   { "rotw", ICLASS_xt_iclass_rotw,
   8659     0,
   8660     Opcode_rotw_encode_fns, 0, 0 },
   8661   { "retw", ICLASS_xt_iclass_retw,
   8662     XTENSA_OPCODE_IS_JUMP,
   8663     Opcode_retw_encode_fns, 0, 0 },
   8664   { "retw.n", ICLASS_xt_iclass_retw,
   8665     XTENSA_OPCODE_IS_JUMP,
   8666     Opcode_retw_n_encode_fns, 0, 0 },
   8667   { "rfwo", ICLASS_xt_iclass_rfwou,
   8668     XTENSA_OPCODE_IS_JUMP,
   8669     Opcode_rfwo_encode_fns, 0, 0 },
   8670   { "rfwu", ICLASS_xt_iclass_rfwou,
   8671     XTENSA_OPCODE_IS_JUMP,
   8672     Opcode_rfwu_encode_fns, 0, 0 },
   8673   { "l32e", ICLASS_xt_iclass_l32e,
   8674     0,
   8675     Opcode_l32e_encode_fns, 0, 0 },
   8676   { "s32e", ICLASS_xt_iclass_s32e,
   8677     0,
   8678     Opcode_s32e_encode_fns, 0, 0 },
   8679   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
   8680     0,
   8681     Opcode_rsr_windowbase_encode_fns, 0, 0 },
   8682   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
   8683     0,
   8684     Opcode_wsr_windowbase_encode_fns, 0, 0 },
   8685   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
   8686     0,
   8687     Opcode_xsr_windowbase_encode_fns, 0, 0 },
   8688   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
   8689     0,
   8690     Opcode_rsr_windowstart_encode_fns, 0, 0 },
   8691   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
   8692     0,
   8693     Opcode_wsr_windowstart_encode_fns, 0, 0 },
   8694   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
   8695     0,
   8696     Opcode_xsr_windowstart_encode_fns, 0, 0 },
   8697   { "add.n", ICLASS_xt_iclass_add_n,
   8698     0,
   8699     Opcode_add_n_encode_fns, 0, 0 },
   8700   { "addi.n", ICLASS_xt_iclass_addi_n,
   8701     0,
   8702     Opcode_addi_n_encode_fns, 0, 0 },
   8703   { "beqz.n", ICLASS_xt_iclass_bz6,
   8704     XTENSA_OPCODE_IS_BRANCH,
   8705     Opcode_beqz_n_encode_fns, 0, 0 },
   8706   { "bnez.n", ICLASS_xt_iclass_bz6,
   8707     XTENSA_OPCODE_IS_BRANCH,
   8708     Opcode_bnez_n_encode_fns, 0, 0 },
   8709   { "ill.n", ICLASS_xt_iclass_ill_n,
   8710     0,
   8711     Opcode_ill_n_encode_fns, 0, 0 },
   8712   { "l32i.n", ICLASS_xt_iclass_loadi4,
   8713     0,
   8714     Opcode_l32i_n_encode_fns, 0, 0 },
   8715   { "mov.n", ICLASS_xt_iclass_mov_n,
   8716     0,
   8717     Opcode_mov_n_encode_fns, 0, 0 },
   8718   { "movi.n", ICLASS_xt_iclass_movi_n,
   8719     0,
   8720     Opcode_movi_n_encode_fns, 0, 0 },
   8721   { "nop.n", ICLASS_xt_iclass_nopn,
   8722     0,
   8723     Opcode_nop_n_encode_fns, 0, 0 },
   8724   { "ret.n", ICLASS_xt_iclass_retn,
   8725     XTENSA_OPCODE_IS_JUMP,
   8726     Opcode_ret_n_encode_fns, 0, 0 },
   8727   { "s32i.n", ICLASS_xt_iclass_storei4,
   8728     0,
   8729     Opcode_s32i_n_encode_fns, 0, 0 },
   8730   { "addi", ICLASS_xt_iclass_addi,
   8731     0,
   8732     Opcode_addi_encode_fns, 0, 0 },
   8733   { "addmi", ICLASS_xt_iclass_addmi,
   8734     0,
   8735     Opcode_addmi_encode_fns, 0, 0 },
   8736   { "add", ICLASS_xt_iclass_addsub,
   8737     0,
   8738     Opcode_add_encode_fns, 0, 0 },
   8739   { "sub", ICLASS_xt_iclass_addsub,
   8740     0,
   8741     Opcode_sub_encode_fns, 0, 0 },
   8742   { "addx2", ICLASS_xt_iclass_addsub,
   8743     0,
   8744     Opcode_addx2_encode_fns, 0, 0 },
   8745   { "addx4", ICLASS_xt_iclass_addsub,
   8746     0,
   8747     Opcode_addx4_encode_fns, 0, 0 },
   8748   { "addx8", ICLASS_xt_iclass_addsub,
   8749     0,
   8750     Opcode_addx8_encode_fns, 0, 0 },
   8751   { "subx2", ICLASS_xt_iclass_addsub,
   8752     0,
   8753     Opcode_subx2_encode_fns, 0, 0 },
   8754   { "subx4", ICLASS_xt_iclass_addsub,
   8755     0,
   8756     Opcode_subx4_encode_fns, 0, 0 },
   8757   { "subx8", ICLASS_xt_iclass_addsub,
   8758     0,
   8759     Opcode_subx8_encode_fns, 0, 0 },
   8760   { "and", ICLASS_xt_iclass_bit,
   8761     0,
   8762     Opcode_and_encode_fns, 0, 0 },
   8763   { "or", ICLASS_xt_iclass_bit,
   8764     0,
   8765     Opcode_or_encode_fns, 0, 0 },
   8766   { "xor", ICLASS_xt_iclass_bit,
   8767     0,
   8768     Opcode_xor_encode_fns, 0, 0 },
   8769   { "beqi", ICLASS_xt_iclass_bsi8,
   8770     XTENSA_OPCODE_IS_BRANCH,
   8771     Opcode_beqi_encode_fns, 0, 0 },
   8772   { "bnei", ICLASS_xt_iclass_bsi8,
   8773     XTENSA_OPCODE_IS_BRANCH,
   8774     Opcode_bnei_encode_fns, 0, 0 },
   8775   { "bgei", ICLASS_xt_iclass_bsi8,
   8776     XTENSA_OPCODE_IS_BRANCH,
   8777     Opcode_bgei_encode_fns, 0, 0 },
   8778   { "blti", ICLASS_xt_iclass_bsi8,
   8779     XTENSA_OPCODE_IS_BRANCH,
   8780     Opcode_blti_encode_fns, 0, 0 },
   8781   { "bbci", ICLASS_xt_iclass_bsi8b,
   8782     XTENSA_OPCODE_IS_BRANCH,
   8783     Opcode_bbci_encode_fns, 0, 0 },
   8784   { "bbsi", ICLASS_xt_iclass_bsi8b,
   8785     XTENSA_OPCODE_IS_BRANCH,
   8786     Opcode_bbsi_encode_fns, 0, 0 },
   8787   { "bgeui", ICLASS_xt_iclass_bsi8u,
   8788     XTENSA_OPCODE_IS_BRANCH,
   8789     Opcode_bgeui_encode_fns, 0, 0 },
   8790   { "bltui", ICLASS_xt_iclass_bsi8u,
   8791     XTENSA_OPCODE_IS_BRANCH,
   8792     Opcode_bltui_encode_fns, 0, 0 },
   8793   { "beq", ICLASS_xt_iclass_bst8,
   8794     XTENSA_OPCODE_IS_BRANCH,
   8795     Opcode_beq_encode_fns, 0, 0 },
   8796   { "bne", ICLASS_xt_iclass_bst8,
   8797     XTENSA_OPCODE_IS_BRANCH,
   8798     Opcode_bne_encode_fns, 0, 0 },
   8799   { "bge", ICLASS_xt_iclass_bst8,
   8800     XTENSA_OPCODE_IS_BRANCH,
   8801     Opcode_bge_encode_fns, 0, 0 },
   8802   { "blt", ICLASS_xt_iclass_bst8,
   8803     XTENSA_OPCODE_IS_BRANCH,
   8804     Opcode_blt_encode_fns, 0, 0 },
   8805   { "bgeu", ICLASS_xt_iclass_bst8,
   8806     XTENSA_OPCODE_IS_BRANCH,
   8807     Opcode_bgeu_encode_fns, 0, 0 },
   8808   { "bltu", ICLASS_xt_iclass_bst8,
   8809     XTENSA_OPCODE_IS_BRANCH,
   8810     Opcode_bltu_encode_fns, 0, 0 },
   8811   { "bany", ICLASS_xt_iclass_bst8,
   8812     XTENSA_OPCODE_IS_BRANCH,
   8813     Opcode_bany_encode_fns, 0, 0 },
   8814   { "bnone", ICLASS_xt_iclass_bst8,
   8815     XTENSA_OPCODE_IS_BRANCH,
   8816     Opcode_bnone_encode_fns, 0, 0 },
   8817   { "ball", ICLASS_xt_iclass_bst8,
   8818     XTENSA_OPCODE_IS_BRANCH,
   8819     Opcode_ball_encode_fns, 0, 0 },
   8820   { "bnall", ICLASS_xt_iclass_bst8,
   8821     XTENSA_OPCODE_IS_BRANCH,
   8822     Opcode_bnall_encode_fns, 0, 0 },
   8823   { "bbc", ICLASS_xt_iclass_bst8,
   8824     XTENSA_OPCODE_IS_BRANCH,
   8825     Opcode_bbc_encode_fns, 0, 0 },
   8826   { "bbs", ICLASS_xt_iclass_bst8,
   8827     XTENSA_OPCODE_IS_BRANCH,
   8828     Opcode_bbs_encode_fns, 0, 0 },
   8829   { "beqz", ICLASS_xt_iclass_bsz12,
   8830     XTENSA_OPCODE_IS_BRANCH,
   8831     Opcode_beqz_encode_fns, 0, 0 },
   8832   { "bnez", ICLASS_xt_iclass_bsz12,
   8833     XTENSA_OPCODE_IS_BRANCH,
   8834     Opcode_bnez_encode_fns, 0, 0 },
   8835   { "bgez", ICLASS_xt_iclass_bsz12,
   8836     XTENSA_OPCODE_IS_BRANCH,
   8837     Opcode_bgez_encode_fns, 0, 0 },
   8838   { "bltz", ICLASS_xt_iclass_bsz12,
   8839     XTENSA_OPCODE_IS_BRANCH,
   8840     Opcode_bltz_encode_fns, 0, 0 },
   8841   { "call0", ICLASS_xt_iclass_call0,
   8842     XTENSA_OPCODE_IS_CALL,
   8843     Opcode_call0_encode_fns, 0, 0 },
   8844   { "callx0", ICLASS_xt_iclass_callx0,
   8845     XTENSA_OPCODE_IS_CALL,
   8846     Opcode_callx0_encode_fns, 0, 0 },
   8847   { "extui", ICLASS_xt_iclass_exti,
   8848     0,
   8849     Opcode_extui_encode_fns, 0, 0 },
   8850   { "ill", ICLASS_xt_iclass_ill,
   8851     0,
   8852     Opcode_ill_encode_fns, 0, 0 },
   8853   { "j", ICLASS_xt_iclass_jump,
   8854     XTENSA_OPCODE_IS_JUMP,
   8855     Opcode_j_encode_fns, 0, 0 },
   8856   { "jx", ICLASS_xt_iclass_jumpx,
   8857     XTENSA_OPCODE_IS_JUMP,
   8858     Opcode_jx_encode_fns, 0, 0 },
   8859   { "l16ui", ICLASS_xt_iclass_l16ui,
   8860     0,
   8861     Opcode_l16ui_encode_fns, 0, 0 },
   8862   { "l16si", ICLASS_xt_iclass_l16si,
   8863     0,
   8864     Opcode_l16si_encode_fns, 0, 0 },
   8865   { "l32i", ICLASS_xt_iclass_l32i,
   8866     0,
   8867     Opcode_l32i_encode_fns, 0, 0 },
   8868   { "l32r", ICLASS_xt_iclass_l32r,
   8869     0,
   8870     Opcode_l32r_encode_fns, 0, 0 },
   8871   { "l8ui", ICLASS_xt_iclass_l8i,
   8872     0,
   8873     Opcode_l8ui_encode_fns, 0, 0 },
   8874   { "movi", ICLASS_xt_iclass_movi,
   8875     0,
   8876     Opcode_movi_encode_fns, 0, 0 },
   8877   { "moveqz", ICLASS_xt_iclass_movz,
   8878     0,
   8879     Opcode_moveqz_encode_fns, 0, 0 },
   8880   { "movnez", ICLASS_xt_iclass_movz,
   8881     0,
   8882     Opcode_movnez_encode_fns, 0, 0 },
   8883   { "movltz", ICLASS_xt_iclass_movz,
   8884     0,
   8885     Opcode_movltz_encode_fns, 0, 0 },
   8886   { "movgez", ICLASS_xt_iclass_movz,
   8887     0,
   8888     Opcode_movgez_encode_fns, 0, 0 },
   8889   { "neg", ICLASS_xt_iclass_neg,
   8890     0,
   8891     Opcode_neg_encode_fns, 0, 0 },
   8892   { "abs", ICLASS_xt_iclass_neg,
   8893     0,
   8894     Opcode_abs_encode_fns, 0, 0 },
   8895   { "nop", ICLASS_xt_iclass_nop,
   8896     0,
   8897     Opcode_nop_encode_fns, 0, 0 },
   8898   { "ret", ICLASS_xt_iclass_return,
   8899     XTENSA_OPCODE_IS_JUMP,
   8900     Opcode_ret_encode_fns, 0, 0 },
   8901   { "simcall", ICLASS_xt_iclass_simcall,
   8902     0,
   8903     Opcode_simcall_encode_fns, 0, 0 },
   8904   { "s16i", ICLASS_xt_iclass_s16i,
   8905     0,
   8906     Opcode_s16i_encode_fns, 0, 0 },
   8907   { "s32i", ICLASS_xt_iclass_s32i,
   8908     0,
   8909     Opcode_s32i_encode_fns, 0, 0 },
   8910   { "s32nb", ICLASS_xt_iclass_s32nb,
   8911     0,
   8912     Opcode_s32nb_encode_fns, 0, 0 },
   8913   { "s8i", ICLASS_xt_iclass_s8i,
   8914     0,
   8915     Opcode_s8i_encode_fns, 0, 0 },
   8916   { "ssr", ICLASS_xt_iclass_sar,
   8917     0,
   8918     Opcode_ssr_encode_fns, 0, 0 },
   8919   { "ssl", ICLASS_xt_iclass_sar,
   8920     0,
   8921     Opcode_ssl_encode_fns, 0, 0 },
   8922   { "ssa8l", ICLASS_xt_iclass_sar,
   8923     0,
   8924     Opcode_ssa8l_encode_fns, 0, 0 },
   8925   { "ssa8b", ICLASS_xt_iclass_sar,
   8926     0,
   8927     Opcode_ssa8b_encode_fns, 0, 0 },
   8928   { "ssai", ICLASS_xt_iclass_sari,
   8929     0,
   8930     Opcode_ssai_encode_fns, 0, 0 },
   8931   { "sll", ICLASS_xt_iclass_shifts,
   8932     0,
   8933     Opcode_sll_encode_fns, 0, 0 },
   8934   { "src", ICLASS_xt_iclass_shiftst,
   8935     0,
   8936     Opcode_src_encode_fns, 0, 0 },
   8937   { "srl", ICLASS_xt_iclass_shiftt,
   8938     0,
   8939     Opcode_srl_encode_fns, 0, 0 },
   8940   { "sra", ICLASS_xt_iclass_shiftt,
   8941     0,
   8942     Opcode_sra_encode_fns, 0, 0 },
   8943   { "slli", ICLASS_xt_iclass_slli,
   8944     0,
   8945     Opcode_slli_encode_fns, 0, 0 },
   8946   { "srai", ICLASS_xt_iclass_srai,
   8947     0,
   8948     Opcode_srai_encode_fns, 0, 0 },
   8949   { "srli", ICLASS_xt_iclass_srli,
   8950     0,
   8951     Opcode_srli_encode_fns, 0, 0 },
   8952   { "memw", ICLASS_xt_iclass_memw,
   8953     0,
   8954     Opcode_memw_encode_fns, 0, 0 },
   8955   { "extw", ICLASS_xt_iclass_extw,
   8956     0,
   8957     Opcode_extw_encode_fns, 0, 0 },
   8958   { "isync", ICLASS_xt_iclass_isync,
   8959     0,
   8960     Opcode_isync_encode_fns, 0, 0 },
   8961   { "rsync", ICLASS_xt_iclass_sync,
   8962     0,
   8963     Opcode_rsync_encode_fns, 0, 0 },
   8964   { "esync", ICLASS_xt_iclass_sync,
   8965     0,
   8966     Opcode_esync_encode_fns, 0, 0 },
   8967   { "dsync", ICLASS_xt_iclass_sync,
   8968     0,
   8969     Opcode_dsync_encode_fns, 0, 0 },
   8970   { "rsil", ICLASS_xt_iclass_rsil,
   8971     0,
   8972     Opcode_rsil_encode_fns, 0, 0 },
   8973   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
   8974     0,
   8975     Opcode_rsr_sar_encode_fns, 0, 0 },
   8976   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
   8977     0,
   8978     Opcode_wsr_sar_encode_fns, 0, 0 },
   8979   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
   8980     0,
   8981     Opcode_xsr_sar_encode_fns, 0, 0 },
   8982   { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
   8983     0,
   8984     Opcode_rsr_memctl_encode_fns, 0, 0 },
   8985   { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
   8986     0,
   8987     Opcode_wsr_memctl_encode_fns, 0, 0 },
   8988   { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
   8989     0,
   8990     Opcode_xsr_memctl_encode_fns, 0, 0 },
   8991   { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
   8992     0,
   8993     Opcode_rsr_litbase_encode_fns, 0, 0 },
   8994   { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
   8995     0,
   8996     Opcode_wsr_litbase_encode_fns, 0, 0 },
   8997   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
   8998     0,
   8999     Opcode_xsr_litbase_encode_fns, 0, 0 },
   9000   { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
   9001     0,
   9002     Opcode_rsr_configid0_encode_fns, 0, 0 },
   9003   { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
   9004     0,
   9005     Opcode_wsr_configid0_encode_fns, 0, 0 },
   9006   { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
   9007     0,
   9008     Opcode_rsr_configid1_encode_fns, 0, 0 },
   9009   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
   9010     0,
   9011     Opcode_rsr_ps_encode_fns, 0, 0 },
   9012   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
   9013     0,
   9014     Opcode_wsr_ps_encode_fns, 0, 0 },
   9015   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
   9016     0,
   9017     Opcode_xsr_ps_encode_fns, 0, 0 },
   9018   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
   9019     0,
   9020     Opcode_rsr_epc1_encode_fns, 0, 0 },
   9021   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
   9022     0,
   9023     Opcode_wsr_epc1_encode_fns, 0, 0 },
   9024   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
   9025     0,
   9026     Opcode_xsr_epc1_encode_fns, 0, 0 },
   9027   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
   9028     0,
   9029     Opcode_rsr_excsave1_encode_fns, 0, 0 },
   9030   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
   9031     0,
   9032     Opcode_wsr_excsave1_encode_fns, 0, 0 },
   9033   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
   9034     0,
   9035     Opcode_xsr_excsave1_encode_fns, 0, 0 },
   9036   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
   9037     0,
   9038     Opcode_rsr_epc2_encode_fns, 0, 0 },
   9039   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
   9040     0,
   9041     Opcode_wsr_epc2_encode_fns, 0, 0 },
   9042   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
   9043     0,
   9044     Opcode_xsr_epc2_encode_fns, 0, 0 },
   9045   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
   9046     0,
   9047     Opcode_rsr_excsave2_encode_fns, 0, 0 },
   9048   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
   9049     0,
   9050     Opcode_wsr_excsave2_encode_fns, 0, 0 },
   9051   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
   9052     0,
   9053     Opcode_xsr_excsave2_encode_fns, 0, 0 },
   9054   { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
   9055     0,
   9056     Opcode_rsr_epc3_encode_fns, 0, 0 },
   9057   { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
   9058     0,
   9059     Opcode_wsr_epc3_encode_fns, 0, 0 },
   9060   { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
   9061     0,
   9062     Opcode_xsr_epc3_encode_fns, 0, 0 },
   9063   { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
   9064     0,
   9065     Opcode_rsr_excsave3_encode_fns, 0, 0 },
   9066   { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
   9067     0,
   9068     Opcode_wsr_excsave3_encode_fns, 0, 0 },
   9069   { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
   9070     0,
   9071     Opcode_xsr_excsave3_encode_fns, 0, 0 },
   9072   { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
   9073     0,
   9074     Opcode_rsr_epc4_encode_fns, 0, 0 },
   9075   { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
   9076     0,
   9077     Opcode_wsr_epc4_encode_fns, 0, 0 },
   9078   { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
   9079     0,
   9080     Opcode_xsr_epc4_encode_fns, 0, 0 },
   9081   { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
   9082     0,
   9083     Opcode_rsr_excsave4_encode_fns, 0, 0 },
   9084   { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
   9085     0,
   9086     Opcode_wsr_excsave4_encode_fns, 0, 0 },
   9087   { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
   9088     0,
   9089     Opcode_xsr_excsave4_encode_fns, 0, 0 },
   9090   { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
   9091     0,
   9092     Opcode_rsr_epc5_encode_fns, 0, 0 },
   9093   { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
   9094     0,
   9095     Opcode_wsr_epc5_encode_fns, 0, 0 },
   9096   { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
   9097     0,
   9098     Opcode_xsr_epc5_encode_fns, 0, 0 },
   9099   { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
   9100     0,
   9101     Opcode_rsr_excsave5_encode_fns, 0, 0 },
   9102   { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
   9103     0,
   9104     Opcode_wsr_excsave5_encode_fns, 0, 0 },
   9105   { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
   9106     0,
   9107     Opcode_xsr_excsave5_encode_fns, 0, 0 },
   9108   { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
   9109     0,
   9110     Opcode_rsr_epc6_encode_fns, 0, 0 },
   9111   { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
   9112     0,
   9113     Opcode_wsr_epc6_encode_fns, 0, 0 },
   9114   { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
   9115     0,
   9116     Opcode_xsr_epc6_encode_fns, 0, 0 },
   9117   { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
   9118     0,
   9119     Opcode_rsr_excsave6_encode_fns, 0, 0 },
   9120   { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
   9121     0,
   9122     Opcode_wsr_excsave6_encode_fns, 0, 0 },
   9123   { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
   9124     0,
   9125     Opcode_xsr_excsave6_encode_fns, 0, 0 },
   9126   { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
   9127     0,
   9128     Opcode_rsr_epc7_encode_fns, 0, 0 },
   9129   { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
   9130     0,
   9131     Opcode_wsr_epc7_encode_fns, 0, 0 },
   9132   { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
   9133     0,
   9134     Opcode_xsr_epc7_encode_fns, 0, 0 },
   9135   { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
   9136     0,
   9137     Opcode_rsr_excsave7_encode_fns, 0, 0 },
   9138   { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
   9139     0,
   9140     Opcode_wsr_excsave7_encode_fns, 0, 0 },
   9141   { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
   9142     0,
   9143     Opcode_xsr_excsave7_encode_fns, 0, 0 },
   9144   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
   9145     0,
   9146     Opcode_rsr_eps2_encode_fns, 0, 0 },
   9147   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
   9148     0,
   9149     Opcode_wsr_eps2_encode_fns, 0, 0 },
   9150   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
   9151     0,
   9152     Opcode_xsr_eps2_encode_fns, 0, 0 },
   9153   { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
   9154     0,
   9155     Opcode_rsr_eps3_encode_fns, 0, 0 },
   9156   { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
   9157     0,
   9158     Opcode_wsr_eps3_encode_fns, 0, 0 },
   9159   { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
   9160     0,
   9161     Opcode_xsr_eps3_encode_fns, 0, 0 },
   9162   { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
   9163     0,
   9164     Opcode_rsr_eps4_encode_fns, 0, 0 },
   9165   { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
   9166     0,
   9167     Opcode_wsr_eps4_encode_fns, 0, 0 },
   9168   { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
   9169     0,
   9170     Opcode_xsr_eps4_encode_fns, 0, 0 },
   9171   { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
   9172     0,
   9173     Opcode_rsr_eps5_encode_fns, 0, 0 },
   9174   { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
   9175     0,
   9176     Opcode_wsr_eps5_encode_fns, 0, 0 },
   9177   { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
   9178     0,
   9179     Opcode_xsr_eps5_encode_fns, 0, 0 },
   9180   { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
   9181     0,
   9182     Opcode_rsr_eps6_encode_fns, 0, 0 },
   9183   { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
   9184     0,
   9185     Opcode_wsr_eps6_encode_fns, 0, 0 },
   9186   { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
   9187     0,
   9188     Opcode_xsr_eps6_encode_fns, 0, 0 },
   9189   { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
   9190     0,
   9191     Opcode_rsr_eps7_encode_fns, 0, 0 },
   9192   { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
   9193     0,
   9194     Opcode_wsr_eps7_encode_fns, 0, 0 },
   9195   { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
   9196     0,
   9197     Opcode_xsr_eps7_encode_fns, 0, 0 },
   9198   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
   9199     0,
   9200     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
   9201   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
   9202     0,
   9203     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
   9204   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
   9205     0,
   9206     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
   9207   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
   9208     0,
   9209     Opcode_rsr_depc_encode_fns, 0, 0 },
   9210   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
   9211     0,
   9212     Opcode_wsr_depc_encode_fns, 0, 0 },
   9213   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
   9214     0,
   9215     Opcode_xsr_depc_encode_fns, 0, 0 },
   9216   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
   9217     0,
   9218     Opcode_rsr_exccause_encode_fns, 0, 0 },
   9219   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
   9220     0,
   9221     Opcode_wsr_exccause_encode_fns, 0, 0 },
   9222   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
   9223     0,
   9224     Opcode_xsr_exccause_encode_fns, 0, 0 },
   9225   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
   9226     0,
   9227     Opcode_rsr_misc0_encode_fns, 0, 0 },
   9228   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
   9229     0,
   9230     Opcode_wsr_misc0_encode_fns, 0, 0 },
   9231   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
   9232     0,
   9233     Opcode_xsr_misc0_encode_fns, 0, 0 },
   9234   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
   9235     0,
   9236     Opcode_rsr_misc1_encode_fns, 0, 0 },
   9237   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
   9238     0,
   9239     Opcode_wsr_misc1_encode_fns, 0, 0 },
   9240   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
   9241     0,
   9242     Opcode_xsr_misc1_encode_fns, 0, 0 },
   9243   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
   9244     0,
   9245     Opcode_rsr_prid_encode_fns, 0, 0 },
   9246   { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
   9247     0,
   9248     Opcode_rsr_vecbase_encode_fns, 0, 0 },
   9249   { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
   9250     0,
   9251     Opcode_wsr_vecbase_encode_fns, 0, 0 },
   9252   { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
   9253     0,
   9254     Opcode_xsr_vecbase_encode_fns, 0, 0 },
   9255   { "salt", ICLASS_xt_iclass_salt,
   9256     0,
   9257     Opcode_salt_encode_fns, 0, 0 },
   9258   { "saltu", ICLASS_xt_iclass_salt,
   9259     0,
   9260     Opcode_saltu_encode_fns, 0, 0 },
   9261   { "mul16u", ICLASS_xt_mul16,
   9262     0,
   9263     Opcode_mul16u_encode_fns, 0, 0 },
   9264   { "mul16s", ICLASS_xt_mul16,
   9265     0,
   9266     Opcode_mul16s_encode_fns, 0, 0 },
   9267   { "mull", ICLASS_xt_mul32,
   9268     0,
   9269     Opcode_mull_encode_fns, 0, 0 },
   9270   { "rfi", ICLASS_xt_iclass_rfi,
   9271     XTENSA_OPCODE_IS_JUMP,
   9272     Opcode_rfi_encode_fns, 0, 0 },
   9273   { "waiti", ICLASS_xt_iclass_wait,
   9274     0,
   9275     Opcode_waiti_encode_fns, 0, 0 },
   9276   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
   9277     0,
   9278     Opcode_rsr_interrupt_encode_fns, 0, 0 },
   9279   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
   9280     0,
   9281     Opcode_wsr_intset_encode_fns, 0, 0 },
   9282   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
   9283     0,
   9284     Opcode_wsr_intclear_encode_fns, 0, 0 },
   9285   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
   9286     0,
   9287     Opcode_rsr_intenable_encode_fns, 0, 0 },
   9288   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
   9289     0,
   9290     Opcode_wsr_intenable_encode_fns, 0, 0 },
   9291   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
   9292     0,
   9293     Opcode_xsr_intenable_encode_fns, 0, 0 },
   9294   { "break", ICLASS_xt_iclass_break,
   9295     0,
   9296     Opcode_break_encode_fns, 0, 0 },
   9297   { "break.n", ICLASS_xt_iclass_break_n,
   9298     0,
   9299     Opcode_break_n_encode_fns, 0, 0 },
   9300   { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
   9301     0,
   9302     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
   9303   { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
   9304     0,
   9305     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
   9306   { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
   9307     0,
   9308     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
   9309   { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
   9310     0,
   9311     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
   9312   { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
   9313     0,
   9314     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
   9315   { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
   9316     0,
   9317     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
   9318   { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
   9319     0,
   9320     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
   9321   { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
   9322     0,
   9323     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
   9324   { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
   9325     0,
   9326     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
   9327   { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
   9328     0,
   9329     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
   9330   { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
   9331     0,
   9332     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
   9333   { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
   9334     0,
   9335     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
   9336   { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
   9337     0,
   9338     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
   9339   { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
   9340     0,
   9341     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
   9342   { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
   9343     0,
   9344     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
   9345   { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
   9346     0,
   9347     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
   9348   { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
   9349     0,
   9350     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
   9351   { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
   9352     0,
   9353     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
   9354   { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
   9355     0,
   9356     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
   9357   { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
   9358     0,
   9359     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
   9360   { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
   9361     0,
   9362     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
   9363   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
   9364     0,
   9365     Opcode_rsr_debugcause_encode_fns, 0, 0 },
   9366   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
   9367     0,
   9368     Opcode_wsr_debugcause_encode_fns, 0, 0 },
   9369   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
   9370     0,
   9371     Opcode_xsr_debugcause_encode_fns, 0, 0 },
   9372   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
   9373     0,
   9374     Opcode_rsr_icount_encode_fns, 0, 0 },
   9375   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
   9376     0,
   9377     Opcode_wsr_icount_encode_fns, 0, 0 },
   9378   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
   9379     0,
   9380     Opcode_xsr_icount_encode_fns, 0, 0 },
   9381   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
   9382     0,
   9383     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
   9384   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
   9385     0,
   9386     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
   9387   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
   9388     0,
   9389     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
   9390   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
   9391     0,
   9392     Opcode_rsr_ddr_encode_fns, 0, 0 },
   9393   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
   9394     0,
   9395     Opcode_wsr_ddr_encode_fns, 0, 0 },
   9396   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
   9397     0,
   9398     Opcode_xsr_ddr_encode_fns, 0, 0 },
   9399   { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
   9400     0,
   9401     Opcode_lddr32_p_encode_fns, 0, 0 },
   9402   { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
   9403     0,
   9404     Opcode_sddr32_p_encode_fns, 0, 0 },
   9405   { "rfdo", ICLASS_xt_iclass_rfdo,
   9406     XTENSA_OPCODE_IS_JUMP,
   9407     Opcode_rfdo_encode_fns, 0, 0 },
   9408   { "rfdd", ICLASS_xt_iclass_rfdd,
   9409     XTENSA_OPCODE_IS_JUMP,
   9410     Opcode_rfdd_encode_fns, 0, 0 },
   9411   { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
   9412     0,
   9413     Opcode_wsr_mmid_encode_fns, 0, 0 },
   9414   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
   9415     0,
   9416     Opcode_rsr_ccount_encode_fns, 0, 0 },
   9417   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
   9418     0,
   9419     Opcode_wsr_ccount_encode_fns, 0, 0 },
   9420   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
   9421     0,
   9422     Opcode_xsr_ccount_encode_fns, 0, 0 },
   9423   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
   9424     0,
   9425     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
   9426   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
   9427     0,
   9428     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
   9429   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
   9430     0,
   9431     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
   9432   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
   9433     0,
   9434     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
   9435   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
   9436     0,
   9437     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
   9438   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
   9439     0,
   9440     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
   9441   { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
   9442     0,
   9443     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
   9444   { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
   9445     0,
   9446     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
   9447   { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
   9448     0,
   9449     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
   9450   { "idtlb", ICLASS_xt_iclass_idtlb,
   9451     0,
   9452     Opcode_idtlb_encode_fns, 0, 0 },
   9453   { "pdtlb", ICLASS_xt_iclass_rdtlb,
   9454     0,
   9455     Opcode_pdtlb_encode_fns, 0, 0 },
   9456   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
   9457     0,
   9458     Opcode_rdtlb0_encode_fns, 0, 0 },
   9459   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
   9460     0,
   9461     Opcode_rdtlb1_encode_fns, 0, 0 },
   9462   { "wdtlb", ICLASS_xt_iclass_wdtlb,
   9463     0,
   9464     Opcode_wdtlb_encode_fns, 0, 0 },
   9465   { "iitlb", ICLASS_xt_iclass_iitlb,
   9466     0,
   9467     Opcode_iitlb_encode_fns, 0, 0 },
   9468   { "pitlb", ICLASS_xt_iclass_ritlb,
   9469     0,
   9470     Opcode_pitlb_encode_fns, 0, 0 },
   9471   { "ritlb0", ICLASS_xt_iclass_ritlb,
   9472     0,
   9473     Opcode_ritlb0_encode_fns, 0, 0 },
   9474   { "ritlb1", ICLASS_xt_iclass_ritlb,
   9475     0,
   9476     Opcode_ritlb1_encode_fns, 0, 0 },
   9477   { "witlb", ICLASS_xt_iclass_witlb,
   9478     0,
   9479     Opcode_witlb_encode_fns, 0, 0 },
   9480   { "min", ICLASS_xt_iclass_minmax,
   9481     0,
   9482     Opcode_min_encode_fns, 0, 0 },
   9483   { "max", ICLASS_xt_iclass_minmax,
   9484     0,
   9485     Opcode_max_encode_fns, 0, 0 },
   9486   { "minu", ICLASS_xt_iclass_minmax,
   9487     0,
   9488     Opcode_minu_encode_fns, 0, 0 },
   9489   { "maxu", ICLASS_xt_iclass_minmax,
   9490     0,
   9491     Opcode_maxu_encode_fns, 0, 0 },
   9492   { "nsa", ICLASS_xt_iclass_nsa,
   9493     0,
   9494     Opcode_nsa_encode_fns, 0, 0 },
   9495   { "nsau", ICLASS_xt_iclass_nsa,
   9496     0,
   9497     Opcode_nsau_encode_fns, 0, 0 },
   9498   { "sext", ICLASS_xt_iclass_sx,
   9499     0,
   9500     Opcode_sext_encode_fns, 0, 0 },
   9501   { "l32ai", ICLASS_xt_iclass_l32ai,
   9502     0,
   9503     Opcode_l32ai_encode_fns, 0, 0 },
   9504   { "s32ri", ICLASS_xt_iclass_s32ri,
   9505     0,
   9506     Opcode_s32ri_encode_fns, 0, 0 },
   9507   { "s32c1i", ICLASS_xt_iclass_s32c1i,
   9508     0,
   9509     Opcode_s32c1i_encode_fns, 0, 0 },
   9510   { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
   9511     0,
   9512     Opcode_rsr_scompare1_encode_fns, 0, 0 },
   9513   { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
   9514     0,
   9515     Opcode_wsr_scompare1_encode_fns, 0, 0 },
   9516   { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
   9517     0,
   9518     Opcode_xsr_scompare1_encode_fns, 0, 0 },
   9519   { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
   9520     0,
   9521     Opcode_rsr_atomctl_encode_fns, 0, 0 },
   9522   { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
   9523     0,
   9524     Opcode_wsr_atomctl_encode_fns, 0, 0 },
   9525   { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
   9526     0,
   9527     Opcode_xsr_atomctl_encode_fns, 0, 0 },
   9528   { "quou", ICLASS_xt_iclass_div,
   9529     0,
   9530     Opcode_quou_encode_fns, 0, 0 },
   9531   { "quos", ICLASS_xt_iclass_div,
   9532     0,
   9533     Opcode_quos_encode_fns, 0, 0 },
   9534   { "remu", ICLASS_xt_iclass_div,
   9535     0,
   9536     Opcode_remu_encode_fns, 0, 0 },
   9537   { "rems", ICLASS_xt_iclass_div,
   9538     0,
   9539     Opcode_rems_encode_fns, 0, 0 },
   9540   { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
   9541     0,
   9542     Opcode_rsr_eraccess_encode_fns, 0, 0 },
   9543   { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
   9544     0,
   9545     Opcode_wsr_eraccess_encode_fns, 0, 0 },
   9546   { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
   9547     0,
   9548     Opcode_xsr_eraccess_encode_fns, 0, 0 },
   9549   { "rer", ICLASS_xt_iclass_rer,
   9550     0,
   9551     Opcode_rer_encode_fns, 0, 0 },
   9552   { "wer", ICLASS_xt_iclass_wer,
   9553     0,
   9554     Opcode_wer_encode_fns, 0, 0 },
   9555   { "rur.expstate", ICLASS_rur_expstate,
   9556     0,
   9557     Opcode_rur_expstate_encode_fns, 0, 0 },
   9558   { "wur.expstate", ICLASS_wur_expstate,
   9559     0,
   9560     Opcode_wur_expstate_encode_fns, 0, 0 },
   9561   { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
   9562     0,
   9563     Opcode_read_impwire_encode_fns, 0, 0 },
   9564   { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
   9565     0,
   9566     Opcode_setb_expstate_encode_fns, 0, 0 },
   9567   { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
   9568     0,
   9569     Opcode_clrb_expstate_encode_fns, 0, 0 },
   9570   { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
   9571     0,
   9572     Opcode_wrmsk_expstate_encode_fns, 0, 0 }
   9573 };
   9574 
   9575 enum xtensa_opcode_id {
   9576   OPCODE_EXCW,
   9577   OPCODE_RFE,
   9578   OPCODE_RFDE,
   9579   OPCODE_SYSCALL,
   9580   OPCODE_CALL12,
   9581   OPCODE_CALL8,
   9582   OPCODE_CALL4,
   9583   OPCODE_CALLX12,
   9584   OPCODE_CALLX8,
   9585   OPCODE_CALLX4,
   9586   OPCODE_ENTRY,
   9587   OPCODE_MOVSP,
   9588   OPCODE_ROTW,
   9589   OPCODE_RETW,
   9590   OPCODE_RETW_N,
   9591   OPCODE_RFWO,
   9592   OPCODE_RFWU,
   9593   OPCODE_L32E,
   9594   OPCODE_S32E,
   9595   OPCODE_RSR_WINDOWBASE,
   9596   OPCODE_WSR_WINDOWBASE,
   9597   OPCODE_XSR_WINDOWBASE,
   9598   OPCODE_RSR_WINDOWSTART,
   9599   OPCODE_WSR_WINDOWSTART,
   9600   OPCODE_XSR_WINDOWSTART,
   9601   OPCODE_ADD_N,
   9602   OPCODE_ADDI_N,
   9603   OPCODE_BEQZ_N,
   9604   OPCODE_BNEZ_N,
   9605   OPCODE_ILL_N,
   9606   OPCODE_L32I_N,
   9607   OPCODE_MOV_N,
   9608   OPCODE_MOVI_N,
   9609   OPCODE_NOP_N,
   9610   OPCODE_RET_N,
   9611   OPCODE_S32I_N,
   9612   OPCODE_ADDI,
   9613   OPCODE_ADDMI,
   9614   OPCODE_ADD,
   9615   OPCODE_SUB,
   9616   OPCODE_ADDX2,
   9617   OPCODE_ADDX4,
   9618   OPCODE_ADDX8,
   9619   OPCODE_SUBX2,
   9620   OPCODE_SUBX4,
   9621   OPCODE_SUBX8,
   9622   OPCODE_AND,
   9623   OPCODE_OR,
   9624   OPCODE_XOR,
   9625   OPCODE_BEQI,
   9626   OPCODE_BNEI,
   9627   OPCODE_BGEI,
   9628   OPCODE_BLTI,
   9629   OPCODE_BBCI,
   9630   OPCODE_BBSI,
   9631   OPCODE_BGEUI,
   9632   OPCODE_BLTUI,
   9633   OPCODE_BEQ,
   9634   OPCODE_BNE,
   9635   OPCODE_BGE,
   9636   OPCODE_BLT,
   9637   OPCODE_BGEU,
   9638   OPCODE_BLTU,
   9639   OPCODE_BANY,
   9640   OPCODE_BNONE,
   9641   OPCODE_BALL,
   9642   OPCODE_BNALL,
   9643   OPCODE_BBC,
   9644   OPCODE_BBS,
   9645   OPCODE_BEQZ,
   9646   OPCODE_BNEZ,
   9647   OPCODE_BGEZ,
   9648   OPCODE_BLTZ,
   9649   OPCODE_CALL0,
   9650   OPCODE_CALLX0,
   9651   OPCODE_EXTUI,
   9652   OPCODE_ILL,
   9653   OPCODE_J,
   9654   OPCODE_JX,
   9655   OPCODE_L16UI,
   9656   OPCODE_L16SI,
   9657   OPCODE_L32I,
   9658   OPCODE_L32R,
   9659   OPCODE_L8UI,
   9660   OPCODE_MOVI,
   9661   OPCODE_MOVEQZ,
   9662   OPCODE_MOVNEZ,
   9663   OPCODE_MOVLTZ,
   9664   OPCODE_MOVGEZ,
   9665   OPCODE_NEG,
   9666   OPCODE_ABS,
   9667   OPCODE_NOP,
   9668   OPCODE_RET,
   9669   OPCODE_SIMCALL,
   9670   OPCODE_S16I,
   9671   OPCODE_S32I,
   9672   OPCODE_S32NB,
   9673   OPCODE_S8I,
   9674   OPCODE_SSR,
   9675   OPCODE_SSL,
   9676   OPCODE_SSA8L,
   9677   OPCODE_SSA8B,
   9678   OPCODE_SSAI,
   9679   OPCODE_SLL,
   9680   OPCODE_SRC,
   9681   OPCODE_SRL,
   9682   OPCODE_SRA,
   9683   OPCODE_SLLI,
   9684   OPCODE_SRAI,
   9685   OPCODE_SRLI,
   9686   OPCODE_MEMW,
   9687   OPCODE_EXTW,
   9688   OPCODE_ISYNC,
   9689   OPCODE_RSYNC,
   9690   OPCODE_ESYNC,
   9691   OPCODE_DSYNC,
   9692   OPCODE_RSIL,
   9693   OPCODE_RSR_SAR,
   9694   OPCODE_WSR_SAR,
   9695   OPCODE_XSR_SAR,
   9696   OPCODE_RSR_MEMCTL,
   9697   OPCODE_WSR_MEMCTL,
   9698   OPCODE_XSR_MEMCTL,
   9699   OPCODE_RSR_LITBASE,
   9700   OPCODE_WSR_LITBASE,
   9701   OPCODE_XSR_LITBASE,
   9702   OPCODE_RSR_CONFIGID0,
   9703   OPCODE_WSR_CONFIGID0,
   9704   OPCODE_RSR_CONFIGID1,
   9705   OPCODE_RSR_PS,
   9706   OPCODE_WSR_PS,
   9707   OPCODE_XSR_PS,
   9708   OPCODE_RSR_EPC1,
   9709   OPCODE_WSR_EPC1,
   9710   OPCODE_XSR_EPC1,
   9711   OPCODE_RSR_EXCSAVE1,
   9712   OPCODE_WSR_EXCSAVE1,
   9713   OPCODE_XSR_EXCSAVE1,
   9714   OPCODE_RSR_EPC2,
   9715   OPCODE_WSR_EPC2,
   9716   OPCODE_XSR_EPC2,
   9717   OPCODE_RSR_EXCSAVE2,
   9718   OPCODE_WSR_EXCSAVE2,
   9719   OPCODE_XSR_EXCSAVE2,
   9720   OPCODE_RSR_EPC3,
   9721   OPCODE_WSR_EPC3,
   9722   OPCODE_XSR_EPC3,
   9723   OPCODE_RSR_EXCSAVE3,
   9724   OPCODE_WSR_EXCSAVE3,
   9725   OPCODE_XSR_EXCSAVE3,
   9726   OPCODE_RSR_EPC4,
   9727   OPCODE_WSR_EPC4,
   9728   OPCODE_XSR_EPC4,
   9729   OPCODE_RSR_EXCSAVE4,
   9730   OPCODE_WSR_EXCSAVE4,
   9731   OPCODE_XSR_EXCSAVE4,
   9732   OPCODE_RSR_EPC5,
   9733   OPCODE_WSR_EPC5,
   9734   OPCODE_XSR_EPC5,
   9735   OPCODE_RSR_EXCSAVE5,
   9736   OPCODE_WSR_EXCSAVE5,
   9737   OPCODE_XSR_EXCSAVE5,
   9738   OPCODE_RSR_EPC6,
   9739   OPCODE_WSR_EPC6,
   9740   OPCODE_XSR_EPC6,
   9741   OPCODE_RSR_EXCSAVE6,
   9742   OPCODE_WSR_EXCSAVE6,
   9743   OPCODE_XSR_EXCSAVE6,
   9744   OPCODE_RSR_EPC7,
   9745   OPCODE_WSR_EPC7,
   9746   OPCODE_XSR_EPC7,
   9747   OPCODE_RSR_EXCSAVE7,
   9748   OPCODE_WSR_EXCSAVE7,
   9749   OPCODE_XSR_EXCSAVE7,
   9750   OPCODE_RSR_EPS2,
   9751   OPCODE_WSR_EPS2,
   9752   OPCODE_XSR_EPS2,
   9753   OPCODE_RSR_EPS3,
   9754   OPCODE_WSR_EPS3,
   9755   OPCODE_XSR_EPS3,
   9756   OPCODE_RSR_EPS4,
   9757   OPCODE_WSR_EPS4,
   9758   OPCODE_XSR_EPS4,
   9759   OPCODE_RSR_EPS5,
   9760   OPCODE_WSR_EPS5,
   9761   OPCODE_XSR_EPS5,
   9762   OPCODE_RSR_EPS6,
   9763   OPCODE_WSR_EPS6,
   9764   OPCODE_XSR_EPS6,
   9765   OPCODE_RSR_EPS7,
   9766   OPCODE_WSR_EPS7,
   9767   OPCODE_XSR_EPS7,
   9768   OPCODE_RSR_EXCVADDR,
   9769   OPCODE_WSR_EXCVADDR,
   9770   OPCODE_XSR_EXCVADDR,
   9771   OPCODE_RSR_DEPC,
   9772   OPCODE_WSR_DEPC,
   9773   OPCODE_XSR_DEPC,
   9774   OPCODE_RSR_EXCCAUSE,
   9775   OPCODE_WSR_EXCCAUSE,
   9776   OPCODE_XSR_EXCCAUSE,
   9777   OPCODE_RSR_MISC0,
   9778   OPCODE_WSR_MISC0,
   9779   OPCODE_XSR_MISC0,
   9780   OPCODE_RSR_MISC1,
   9781   OPCODE_WSR_MISC1,
   9782   OPCODE_XSR_MISC1,
   9783   OPCODE_RSR_PRID,
   9784   OPCODE_RSR_VECBASE,
   9785   OPCODE_WSR_VECBASE,
   9786   OPCODE_XSR_VECBASE,
   9787   OPCODE_SALT,
   9788   OPCODE_SALTU,
   9789   OPCODE_MUL16U,
   9790   OPCODE_MUL16S,
   9791   OPCODE_MULL,
   9792   OPCODE_RFI,
   9793   OPCODE_WAITI,
   9794   OPCODE_RSR_INTERRUPT,
   9795   OPCODE_WSR_INTSET,
   9796   OPCODE_WSR_INTCLEAR,
   9797   OPCODE_RSR_INTENABLE,
   9798   OPCODE_WSR_INTENABLE,
   9799   OPCODE_XSR_INTENABLE,
   9800   OPCODE_BREAK,
   9801   OPCODE_BREAK_N,
   9802   OPCODE_RSR_DBREAKA0,
   9803   OPCODE_WSR_DBREAKA0,
   9804   OPCODE_XSR_DBREAKA0,
   9805   OPCODE_RSR_DBREAKC0,
   9806   OPCODE_WSR_DBREAKC0,
   9807   OPCODE_XSR_DBREAKC0,
   9808   OPCODE_RSR_DBREAKA1,
   9809   OPCODE_WSR_DBREAKA1,
   9810   OPCODE_XSR_DBREAKA1,
   9811   OPCODE_RSR_DBREAKC1,
   9812   OPCODE_WSR_DBREAKC1,
   9813   OPCODE_XSR_DBREAKC1,
   9814   OPCODE_RSR_IBREAKA0,
   9815   OPCODE_WSR_IBREAKA0,
   9816   OPCODE_XSR_IBREAKA0,
   9817   OPCODE_RSR_IBREAKA1,
   9818   OPCODE_WSR_IBREAKA1,
   9819   OPCODE_XSR_IBREAKA1,
   9820   OPCODE_RSR_IBREAKENABLE,
   9821   OPCODE_WSR_IBREAKENABLE,
   9822   OPCODE_XSR_IBREAKENABLE,
   9823   OPCODE_RSR_DEBUGCAUSE,
   9824   OPCODE_WSR_DEBUGCAUSE,
   9825   OPCODE_XSR_DEBUGCAUSE,
   9826   OPCODE_RSR_ICOUNT,
   9827   OPCODE_WSR_ICOUNT,
   9828   OPCODE_XSR_ICOUNT,
   9829   OPCODE_RSR_ICOUNTLEVEL,
   9830   OPCODE_WSR_ICOUNTLEVEL,
   9831   OPCODE_XSR_ICOUNTLEVEL,
   9832   OPCODE_RSR_DDR,
   9833   OPCODE_WSR_DDR,
   9834   OPCODE_XSR_DDR,
   9835   OPCODE_LDDR32_P,
   9836   OPCODE_SDDR32_P,
   9837   OPCODE_RFDO,
   9838   OPCODE_RFDD,
   9839   OPCODE_WSR_MMID,
   9840   OPCODE_RSR_CCOUNT,
   9841   OPCODE_WSR_CCOUNT,
   9842   OPCODE_XSR_CCOUNT,
   9843   OPCODE_RSR_CCOMPARE0,
   9844   OPCODE_WSR_CCOMPARE0,
   9845   OPCODE_XSR_CCOMPARE0,
   9846   OPCODE_RSR_CCOMPARE1,
   9847   OPCODE_WSR_CCOMPARE1,
   9848   OPCODE_XSR_CCOMPARE1,
   9849   OPCODE_RSR_CCOMPARE2,
   9850   OPCODE_WSR_CCOMPARE2,
   9851   OPCODE_XSR_CCOMPARE2,
   9852   OPCODE_IDTLB,
   9853   OPCODE_PDTLB,
   9854   OPCODE_RDTLB0,
   9855   OPCODE_RDTLB1,
   9856   OPCODE_WDTLB,
   9857   OPCODE_IITLB,
   9858   OPCODE_PITLB,
   9859   OPCODE_RITLB0,
   9860   OPCODE_RITLB1,
   9861   OPCODE_WITLB,
   9862   OPCODE_MIN,
   9863   OPCODE_MAX,
   9864   OPCODE_MINU,
   9865   OPCODE_MAXU,
   9866   OPCODE_NSA,
   9867   OPCODE_NSAU,
   9868   OPCODE_SEXT,
   9869   OPCODE_L32AI,
   9870   OPCODE_S32RI,
   9871   OPCODE_S32C1I,
   9872   OPCODE_RSR_SCOMPARE1,
   9873   OPCODE_WSR_SCOMPARE1,
   9874   OPCODE_XSR_SCOMPARE1,
   9875   OPCODE_RSR_ATOMCTL,
   9876   OPCODE_WSR_ATOMCTL,
   9877   OPCODE_XSR_ATOMCTL,
   9878   OPCODE_QUOU,
   9879   OPCODE_QUOS,
   9880   OPCODE_REMU,
   9881   OPCODE_REMS,
   9882   OPCODE_RSR_ERACCESS,
   9883   OPCODE_WSR_ERACCESS,
   9884   OPCODE_XSR_ERACCESS,
   9885   OPCODE_RER,
   9886   OPCODE_WER,
   9887   OPCODE_RUR_EXPSTATE,
   9888   OPCODE_WUR_EXPSTATE,
   9889   OPCODE_READ_IMPWIRE,
   9890   OPCODE_SETB_EXPSTATE,
   9891   OPCODE_CLRB_EXPSTATE,
   9892   OPCODE_WRMSK_EXPSTATE
   9893 };
   9894 
   9895 
   9896 /* Slot-specific opcode decode functions.  */
   9897 
   9898 static int
   9899 Slot_inst_decode (const xtensa_insnbuf insn)
   9900 {
   9901   if (Field_op0_Slot_inst_get (insn) == 0)
   9902     {
   9903       if (Field_op1_Slot_inst_get (insn) == 0)
   9904 	{
   9905 	  if (Field_op2_Slot_inst_get (insn) == 0)
   9906 	    {
   9907 	      if (Field_r_Slot_inst_get (insn) == 0)
   9908 		{
   9909 		  if (Field_m_Slot_inst_get (insn) == 0 &&
   9910 		      Field_s_Slot_inst_get (insn) == 0 &&
   9911 		      Field_n_Slot_inst_get (insn) == 0)
   9912 		    return OPCODE_ILL;
   9913 		  if (Field_m_Slot_inst_get (insn) == 2)
   9914 		    {
   9915 		      if (Field_n_Slot_inst_get (insn) == 0)
   9916 			return OPCODE_RET;
   9917 		      if (Field_n_Slot_inst_get (insn) == 1)
   9918 			return OPCODE_RETW;
   9919 		      if (Field_n_Slot_inst_get (insn) == 2)
   9920 			return OPCODE_JX;
   9921 		    }
   9922 		  if (Field_m_Slot_inst_get (insn) == 3)
   9923 		    {
   9924 		      if (Field_n_Slot_inst_get (insn) == 0)
   9925 			return OPCODE_CALLX0;
   9926 		      if (Field_n_Slot_inst_get (insn) == 1)
   9927 			return OPCODE_CALLX4;
   9928 		      if (Field_n_Slot_inst_get (insn) == 2)
   9929 			return OPCODE_CALLX8;
   9930 		      if (Field_n_Slot_inst_get (insn) == 3)
   9931 			return OPCODE_CALLX12;
   9932 		    }
   9933 		}
   9934 	      if (Field_r_Slot_inst_get (insn) == 1)
   9935 		return OPCODE_MOVSP;
   9936 	      if (Field_r_Slot_inst_get (insn) == 2)
   9937 		{
   9938 		  if (Field_s_Slot_inst_get (insn) == 0)
   9939 		    {
   9940 		      if (Field_t_Slot_inst_get (insn) == 0)
   9941 			return OPCODE_ISYNC;
   9942 		      if (Field_t_Slot_inst_get (insn) == 1)
   9943 			return OPCODE_RSYNC;
   9944 		      if (Field_t_Slot_inst_get (insn) == 2)
   9945 			return OPCODE_ESYNC;
   9946 		      if (Field_t_Slot_inst_get (insn) == 3)
   9947 			return OPCODE_DSYNC;
   9948 		      if (Field_t_Slot_inst_get (insn) == 8)
   9949 			return OPCODE_EXCW;
   9950 		      if (Field_t_Slot_inst_get (insn) == 12)
   9951 			return OPCODE_MEMW;
   9952 		      if (Field_t_Slot_inst_get (insn) == 13)
   9953 			return OPCODE_EXTW;
   9954 		      if (Field_t_Slot_inst_get (insn) == 15)
   9955 			return OPCODE_NOP;
   9956 		    }
   9957 		}
   9958 	      if (Field_r_Slot_inst_get (insn) == 3)
   9959 		{
   9960 		  if (Field_t_Slot_inst_get (insn) == 0)
   9961 		    {
   9962 		      if (Field_s_Slot_inst_get (insn) == 0)
   9963 			return OPCODE_RFE;
   9964 		      if (Field_s_Slot_inst_get (insn) == 2)
   9965 			return OPCODE_RFDE;
   9966 		      if (Field_s_Slot_inst_get (insn) == 4)
   9967 			return OPCODE_RFWO;
   9968 		      if (Field_s_Slot_inst_get (insn) == 5)
   9969 			return OPCODE_RFWU;
   9970 		    }
   9971 		  if (Field_t_Slot_inst_get (insn) == 1)
   9972 		    return OPCODE_RFI;
   9973 		}
   9974 	      if (Field_r_Slot_inst_get (insn) == 4)
   9975 		return OPCODE_BREAK;
   9976 	      if (Field_r_Slot_inst_get (insn) == 5)
   9977 		{
   9978 		  if (Field_s_Slot_inst_get (insn) == 0 &&
   9979 		      Field_t_Slot_inst_get (insn) == 0)
   9980 		    return OPCODE_SYSCALL;
   9981 		  if (Field_s_Slot_inst_get (insn) == 1 &&
   9982 		      Field_t_Slot_inst_get (insn) == 0)
   9983 		    return OPCODE_SIMCALL;
   9984 		}
   9985 	      if (Field_r_Slot_inst_get (insn) == 6)
   9986 		return OPCODE_RSIL;
   9987 	      if (Field_r_Slot_inst_get (insn) == 7 &&
   9988 		  Field_t_Slot_inst_get (insn) == 0)
   9989 		return OPCODE_WAITI;
   9990 	      if (Field_r_Slot_inst_get (insn) == 7)
   9991 		{
   9992 		  if (Field_t_Slot_inst_get (insn) == 14)
   9993 		    return OPCODE_LDDR32_P;
   9994 		  if (Field_t_Slot_inst_get (insn) == 15)
   9995 		    return OPCODE_SDDR32_P;
   9996 		}
   9997 	    }
   9998 	  if (Field_op2_Slot_inst_get (insn) == 1)
   9999 	    return OPCODE_AND;
  10000 	  if (Field_op2_Slot_inst_get (insn) == 2)
  10001 	    return OPCODE_OR;
  10002 	  if (Field_op2_Slot_inst_get (insn) == 3)
  10003 	    return OPCODE_XOR;
  10004 	  if (Field_op2_Slot_inst_get (insn) == 4)
  10005 	    {
  10006 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  10007 		  Field_t_Slot_inst_get (insn) == 0)
  10008 		return OPCODE_SSR;
  10009 	      if (Field_r_Slot_inst_get (insn) == 1 &&
  10010 		  Field_t_Slot_inst_get (insn) == 0)
  10011 		return OPCODE_SSL;
  10012 	      if (Field_r_Slot_inst_get (insn) == 2 &&
  10013 		  Field_t_Slot_inst_get (insn) == 0)
  10014 		return OPCODE_SSA8L;
  10015 	      if (Field_r_Slot_inst_get (insn) == 3 &&
  10016 		  Field_t_Slot_inst_get (insn) == 0)
  10017 		return OPCODE_SSA8B;
  10018 	      if (Field_r_Slot_inst_get (insn) == 4 &&
  10019 		  Field_thi3_Slot_inst_get (insn) == 0)
  10020 		return OPCODE_SSAI;
  10021 	      if (Field_r_Slot_inst_get (insn) == 6)
  10022 		return OPCODE_RER;
  10023 	      if (Field_r_Slot_inst_get (insn) == 7)
  10024 		return OPCODE_WER;
  10025 	      if (Field_r_Slot_inst_get (insn) == 8 &&
  10026 		  Field_s_Slot_inst_get (insn) == 0)
  10027 		return OPCODE_ROTW;
  10028 	      if (Field_r_Slot_inst_get (insn) == 14)
  10029 		return OPCODE_NSA;
  10030 	      if (Field_r_Slot_inst_get (insn) == 15)
  10031 		return OPCODE_NSAU;
  10032 	    }
  10033 	  if (Field_op2_Slot_inst_get (insn) == 5)
  10034 	    {
  10035 	      if (Field_r_Slot_inst_get (insn) == 3)
  10036 		return OPCODE_RITLB0;
  10037 	      if (Field_r_Slot_inst_get (insn) == 4 &&
  10038 		  Field_t_Slot_inst_get (insn) == 0)
  10039 		return OPCODE_IITLB;
  10040 	      if (Field_r_Slot_inst_get (insn) == 5)
  10041 		return OPCODE_PITLB;
  10042 	      if (Field_r_Slot_inst_get (insn) == 6)
  10043 		return OPCODE_WITLB;
  10044 	      if (Field_r_Slot_inst_get (insn) == 7)
  10045 		return OPCODE_RITLB1;
  10046 	      if (Field_r_Slot_inst_get (insn) == 11)
  10047 		return OPCODE_RDTLB0;
  10048 	      if (Field_r_Slot_inst_get (insn) == 12 &&
  10049 		  Field_t_Slot_inst_get (insn) == 0)
  10050 		return OPCODE_IDTLB;
  10051 	      if (Field_r_Slot_inst_get (insn) == 13)
  10052 		return OPCODE_PDTLB;
  10053 	      if (Field_r_Slot_inst_get (insn) == 14)
  10054 		return OPCODE_WDTLB;
  10055 	      if (Field_r_Slot_inst_get (insn) == 15)
  10056 		return OPCODE_RDTLB1;
  10057 	    }
  10058 	  if (Field_op2_Slot_inst_get (insn) == 6)
  10059 	    {
  10060 	      if (Field_s_Slot_inst_get (insn) == 0)
  10061 		return OPCODE_NEG;
  10062 	      if (Field_s_Slot_inst_get (insn) == 1)
  10063 		return OPCODE_ABS;
  10064 	    }
  10065 	  if (Field_op2_Slot_inst_get (insn) == 8)
  10066 	    return OPCODE_ADD;
  10067 	  if (Field_op2_Slot_inst_get (insn) == 9)
  10068 	    return OPCODE_ADDX2;
  10069 	  if (Field_op2_Slot_inst_get (insn) == 10)
  10070 	    return OPCODE_ADDX4;
  10071 	  if (Field_op2_Slot_inst_get (insn) == 11)
  10072 	    return OPCODE_ADDX8;
  10073 	  if (Field_op2_Slot_inst_get (insn) == 12)
  10074 	    return OPCODE_SUB;
  10075 	  if (Field_op2_Slot_inst_get (insn) == 13)
  10076 	    return OPCODE_SUBX2;
  10077 	  if (Field_op2_Slot_inst_get (insn) == 14)
  10078 	    return OPCODE_SUBX4;
  10079 	  if (Field_op2_Slot_inst_get (insn) == 15)
  10080 	    return OPCODE_SUBX8;
  10081 	}
  10082       if (Field_op1_Slot_inst_get (insn) == 1)
  10083 	{
  10084 	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
  10085 	       Field_op2_Slot_inst_get (insn) == 1))
  10086 	    return OPCODE_SLLI;
  10087 	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
  10088 	       Field_op2_Slot_inst_get (insn) == 3))
  10089 	    return OPCODE_SRAI;
  10090 	  if (Field_op2_Slot_inst_get (insn) == 4)
  10091 	    return OPCODE_SRLI;
  10092 	  if (Field_op2_Slot_inst_get (insn) == 6)
  10093 	    {
  10094 	      if (Field_sr_Slot_inst_get (insn) == 3)
  10095 		return OPCODE_XSR_SAR;
  10096 	      if (Field_sr_Slot_inst_get (insn) == 5)
  10097 		return OPCODE_XSR_LITBASE;
  10098 	      if (Field_sr_Slot_inst_get (insn) == 12)
  10099 		return OPCODE_XSR_SCOMPARE1;
  10100 	      if (Field_sr_Slot_inst_get (insn) == 72)
  10101 		return OPCODE_XSR_WINDOWBASE;
  10102 	      if (Field_sr_Slot_inst_get (insn) == 73)
  10103 		return OPCODE_XSR_WINDOWSTART;
  10104 	      if (Field_sr_Slot_inst_get (insn) == 95)
  10105 		return OPCODE_XSR_ERACCESS;
  10106 	      if (Field_sr_Slot_inst_get (insn) == 96)
  10107 		return OPCODE_XSR_IBREAKENABLE;
  10108 	      if (Field_sr_Slot_inst_get (insn) == 97)
  10109 		return OPCODE_XSR_MEMCTL;
  10110 	      if (Field_sr_Slot_inst_get (insn) == 99)
  10111 		return OPCODE_XSR_ATOMCTL;
  10112 	      if (Field_sr_Slot_inst_get (insn) == 104)
  10113 		return OPCODE_XSR_DDR;
  10114 	      if (Field_sr_Slot_inst_get (insn) == 128)
  10115 		return OPCODE_XSR_IBREAKA0;
  10116 	      if (Field_sr_Slot_inst_get (insn) == 129)
  10117 		return OPCODE_XSR_IBREAKA1;
  10118 	      if (Field_sr_Slot_inst_get (insn) == 144)
  10119 		return OPCODE_XSR_DBREAKA0;
  10120 	      if (Field_sr_Slot_inst_get (insn) == 145)
  10121 		return OPCODE_XSR_DBREAKA1;
  10122 	      if (Field_sr_Slot_inst_get (insn) == 160)
  10123 		return OPCODE_XSR_DBREAKC0;
  10124 	      if (Field_sr_Slot_inst_get (insn) == 161)
  10125 		return OPCODE_XSR_DBREAKC1;
  10126 	      if (Field_sr_Slot_inst_get (insn) == 177)
  10127 		return OPCODE_XSR_EPC1;
  10128 	      if (Field_sr_Slot_inst_get (insn) == 178)
  10129 		return OPCODE_XSR_EPC2;
  10130 	      if (Field_sr_Slot_inst_get (insn) == 179)
  10131 		return OPCODE_XSR_EPC3;
  10132 	      if (Field_sr_Slot_inst_get (insn) == 180)
  10133 		return OPCODE_XSR_EPC4;
  10134 	      if (Field_sr_Slot_inst_get (insn) == 181)
  10135 		return OPCODE_XSR_EPC5;
  10136 	      if (Field_sr_Slot_inst_get (insn) == 182)
  10137 		return OPCODE_XSR_EPC6;
  10138 	      if (Field_sr_Slot_inst_get (insn) == 183)
  10139 		return OPCODE_XSR_EPC7;
  10140 	      if (Field_sr_Slot_inst_get (insn) == 192)
  10141 		return OPCODE_XSR_DEPC;
  10142 	      if (Field_sr_Slot_inst_get (insn) == 194)
  10143 		return OPCODE_XSR_EPS2;
  10144 	      if (Field_sr_Slot_inst_get (insn) == 195)
  10145 		return OPCODE_XSR_EPS3;
  10146 	      if (Field_sr_Slot_inst_get (insn) == 196)
  10147 		return OPCODE_XSR_EPS4;
  10148 	      if (Field_sr_Slot_inst_get (insn) == 197)
  10149 		return OPCODE_XSR_EPS5;
  10150 	      if (Field_sr_Slot_inst_get (insn) == 198)
  10151 		return OPCODE_XSR_EPS6;
  10152 	      if (Field_sr_Slot_inst_get (insn) == 199)
  10153 		return OPCODE_XSR_EPS7;
  10154 	      if (Field_sr_Slot_inst_get (insn) == 209)
  10155 		return OPCODE_XSR_EXCSAVE1;
  10156 	      if (Field_sr_Slot_inst_get (insn) == 210)
  10157 		return OPCODE_XSR_EXCSAVE2;
  10158 	      if (Field_sr_Slot_inst_get (insn) == 211)
  10159 		return OPCODE_XSR_EXCSAVE3;
  10160 	      if (Field_sr_Slot_inst_get (insn) == 212)
  10161 		return OPCODE_XSR_EXCSAVE4;
  10162 	      if (Field_sr_Slot_inst_get (insn) == 213)
  10163 		return OPCODE_XSR_EXCSAVE5;
  10164 	      if (Field_sr_Slot_inst_get (insn) == 214)
  10165 		return OPCODE_XSR_EXCSAVE6;
  10166 	      if (Field_sr_Slot_inst_get (insn) == 215)
  10167 		return OPCODE_XSR_EXCSAVE7;
  10168 	      if (Field_sr_Slot_inst_get (insn) == 228)
  10169 		return OPCODE_XSR_INTENABLE;
  10170 	      if (Field_sr_Slot_inst_get (insn) == 230)
  10171 		return OPCODE_XSR_PS;
  10172 	      if (Field_sr_Slot_inst_get (insn) == 231)
  10173 		return OPCODE_XSR_VECBASE;
  10174 	      if (Field_sr_Slot_inst_get (insn) == 232)
  10175 		return OPCODE_XSR_EXCCAUSE;
  10176 	      if (Field_sr_Slot_inst_get (insn) == 233)
  10177 		return OPCODE_XSR_DEBUGCAUSE;
  10178 	      if (Field_sr_Slot_inst_get (insn) == 234)
  10179 		return OPCODE_XSR_CCOUNT;
  10180 	      if (Field_sr_Slot_inst_get (insn) == 236)
  10181 		return OPCODE_XSR_ICOUNT;
  10182 	      if (Field_sr_Slot_inst_get (insn) == 237)
  10183 		return OPCODE_XSR_ICOUNTLEVEL;
  10184 	      if (Field_sr_Slot_inst_get (insn) == 238)
  10185 		return OPCODE_XSR_EXCVADDR;
  10186 	      if (Field_sr_Slot_inst_get (insn) == 240)
  10187 		return OPCODE_XSR_CCOMPARE0;
  10188 	      if (Field_sr_Slot_inst_get (insn) == 241)
  10189 		return OPCODE_XSR_CCOMPARE1;
  10190 	      if (Field_sr_Slot_inst_get (insn) == 242)
  10191 		return OPCODE_XSR_CCOMPARE2;
  10192 	      if (Field_sr_Slot_inst_get (insn) == 244)
  10193 		return OPCODE_XSR_MISC0;
  10194 	      if (Field_sr_Slot_inst_get (insn) == 245)
  10195 		return OPCODE_XSR_MISC1;
  10196 	    }
  10197 	  if (Field_op2_Slot_inst_get (insn) == 8)
  10198 	    return OPCODE_SRC;
  10199 	  if (Field_op2_Slot_inst_get (insn) == 9 &&
  10200 	      Field_s_Slot_inst_get (insn) == 0)
  10201 	    return OPCODE_SRL;
  10202 	  if (Field_op2_Slot_inst_get (insn) == 10 &&
  10203 	      Field_t_Slot_inst_get (insn) == 0)
  10204 	    return OPCODE_SLL;
  10205 	  if (Field_op2_Slot_inst_get (insn) == 11 &&
  10206 	      Field_s_Slot_inst_get (insn) == 0)
  10207 	    return OPCODE_SRA;
  10208 	  if (Field_op2_Slot_inst_get (insn) == 12)
  10209 	    return OPCODE_MUL16U;
  10210 	  if (Field_op2_Slot_inst_get (insn) == 13)
  10211 	    return OPCODE_MUL16S;
  10212 	  if (Field_op2_Slot_inst_get (insn) == 15)
  10213 	    {
  10214 	      if (Field_r_Slot_inst_get (insn) == 14 &&
  10215 		  Field_t_Slot_inst_get (insn) == 0)
  10216 		return OPCODE_RFDO;
  10217 	      if (Field_r_Slot_inst_get (insn) == 14 &&
  10218 		  Field_t_Slot_inst_get (insn) == 1)
  10219 		return OPCODE_RFDD;
  10220 	    }
  10221 	}
  10222       if (Field_op1_Slot_inst_get (insn) == 2)
  10223 	{
  10224 	  if (Field_op2_Slot_inst_get (insn) == 6)
  10225 	    return OPCODE_SALTU;
  10226 	  if (Field_op2_Slot_inst_get (insn) == 7)
  10227 	    return OPCODE_SALT;
  10228 	  if (Field_op2_Slot_inst_get (insn) == 8)
  10229 	    return OPCODE_MULL;
  10230 	  if (Field_op2_Slot_inst_get (insn) == 12)
  10231 	    return OPCODE_QUOU;
  10232 	  if (Field_op2_Slot_inst_get (insn) == 13)
  10233 	    return OPCODE_QUOS;
  10234 	  if (Field_op2_Slot_inst_get (insn) == 14)
  10235 	    return OPCODE_REMU;
  10236 	  if (Field_op2_Slot_inst_get (insn) == 15)
  10237 	    return OPCODE_REMS;
  10238 	}
  10239       if (Field_op1_Slot_inst_get (insn) == 3)
  10240 	{
  10241 	  if (Field_op2_Slot_inst_get (insn) == 0)
  10242 	    {
  10243 	      if (Field_sr_Slot_inst_get (insn) == 3)
  10244 		return OPCODE_RSR_SAR;
  10245 	      if (Field_sr_Slot_inst_get (insn) == 5)
  10246 		return OPCODE_RSR_LITBASE;
  10247 	      if (Field_sr_Slot_inst_get (insn) == 12)
  10248 		return OPCODE_RSR_SCOMPARE1;
  10249 	      if (Field_sr_Slot_inst_get (insn) == 72)
  10250 		return OPCODE_RSR_WINDOWBASE;
  10251 	      if (Field_sr_Slot_inst_get (insn) == 73)
  10252 		return OPCODE_RSR_WINDOWSTART;
  10253 	      if (Field_sr_Slot_inst_get (insn) == 95)
  10254 		return OPCODE_RSR_ERACCESS;
  10255 	      if (Field_sr_Slot_inst_get (insn) == 96)
  10256 		return OPCODE_RSR_IBREAKENABLE;
  10257 	      if (Field_sr_Slot_inst_get (insn) == 97)
  10258 		return OPCODE_RSR_MEMCTL;
  10259 	      if (Field_sr_Slot_inst_get (insn) == 99)
  10260 		return OPCODE_RSR_ATOMCTL;
  10261 	      if (Field_sr_Slot_inst_get (insn) == 104)
  10262 		return OPCODE_RSR_DDR;
  10263 	      if (Field_sr_Slot_inst_get (insn) == 128)
  10264 		return OPCODE_RSR_IBREAKA0;
  10265 	      if (Field_sr_Slot_inst_get (insn) == 129)
  10266 		return OPCODE_RSR_IBREAKA1;
  10267 	      if (Field_sr_Slot_inst_get (insn) == 144)
  10268 		return OPCODE_RSR_DBREAKA0;
  10269 	      if (Field_sr_Slot_inst_get (insn) == 145)
  10270 		return OPCODE_RSR_DBREAKA1;
  10271 	      if (Field_sr_Slot_inst_get (insn) == 160)
  10272 		return OPCODE_RSR_DBREAKC0;
  10273 	      if (Field_sr_Slot_inst_get (insn) == 161)
  10274 		return OPCODE_RSR_DBREAKC1;
  10275 	      if (Field_sr_Slot_inst_get (insn) == 176)
  10276 		return OPCODE_RSR_CONFIGID0;
  10277 	      if (Field_sr_Slot_inst_get (insn) == 177)
  10278 		return OPCODE_RSR_EPC1;
  10279 	      if (Field_sr_Slot_inst_get (insn) == 178)
  10280 		return OPCODE_RSR_EPC2;
  10281 	      if (Field_sr_Slot_inst_get (insn) == 179)
  10282 		return OPCODE_RSR_EPC3;
  10283 	      if (Field_sr_Slot_inst_get (insn) == 180)
  10284 		return OPCODE_RSR_EPC4;
  10285 	      if (Field_sr_Slot_inst_get (insn) == 181)
  10286 		return OPCODE_RSR_EPC5;
  10287 	      if (Field_sr_Slot_inst_get (insn) == 182)
  10288 		return OPCODE_RSR_EPC6;
  10289 	      if (Field_sr_Slot_inst_get (insn) == 183)
  10290 		return OPCODE_RSR_EPC7;
  10291 	      if (Field_sr_Slot_inst_get (insn) == 192)
  10292 		return OPCODE_RSR_DEPC;
  10293 	      if (Field_sr_Slot_inst_get (insn) == 194)
  10294 		return OPCODE_RSR_EPS2;
  10295 	      if (Field_sr_Slot_inst_get (insn) == 195)
  10296 		return OPCODE_RSR_EPS3;
  10297 	      if (Field_sr_Slot_inst_get (insn) == 196)
  10298 		return OPCODE_RSR_EPS4;
  10299 	      if (Field_sr_Slot_inst_get (insn) == 197)
  10300 		return OPCODE_RSR_EPS5;
  10301 	      if (Field_sr_Slot_inst_get (insn) == 198)
  10302 		return OPCODE_RSR_EPS6;
  10303 	      if (Field_sr_Slot_inst_get (insn) == 199)
  10304 		return OPCODE_RSR_EPS7;
  10305 	      if (Field_sr_Slot_inst_get (insn) == 208)
  10306 		return OPCODE_RSR_CONFIGID1;
  10307 	      if (Field_sr_Slot_inst_get (insn) == 209)
  10308 		return OPCODE_RSR_EXCSAVE1;
  10309 	      if (Field_sr_Slot_inst_get (insn) == 210)
  10310 		return OPCODE_RSR_EXCSAVE2;
  10311 	      if (Field_sr_Slot_inst_get (insn) == 211)
  10312 		return OPCODE_RSR_EXCSAVE3;
  10313 	      if (Field_sr_Slot_inst_get (insn) == 212)
  10314 		return OPCODE_RSR_EXCSAVE4;
  10315 	      if (Field_sr_Slot_inst_get (insn) == 213)
  10316 		return OPCODE_RSR_EXCSAVE5;
  10317 	      if (Field_sr_Slot_inst_get (insn) == 214)
  10318 		return OPCODE_RSR_EXCSAVE6;
  10319 	      if (Field_sr_Slot_inst_get (insn) == 215)
  10320 		return OPCODE_RSR_EXCSAVE7;
  10321 	      if (Field_sr_Slot_inst_get (insn) == 226)
  10322 		return OPCODE_RSR_INTERRUPT;
  10323 	      if (Field_sr_Slot_inst_get (insn) == 228)
  10324 		return OPCODE_RSR_INTENABLE;
  10325 	      if (Field_sr_Slot_inst_get (insn) == 230)
  10326 		return OPCODE_RSR_PS;
  10327 	      if (Field_sr_Slot_inst_get (insn) == 231)
  10328 		return OPCODE_RSR_VECBASE;
  10329 	      if (Field_sr_Slot_inst_get (insn) == 232)
  10330 		return OPCODE_RSR_EXCCAUSE;
  10331 	      if (Field_sr_Slot_inst_get (insn) == 233)
  10332 		return OPCODE_RSR_DEBUGCAUSE;
  10333 	      if (Field_sr_Slot_inst_get (insn) == 234)
  10334 		return OPCODE_RSR_CCOUNT;
  10335 	      if (Field_sr_Slot_inst_get (insn) == 235)
  10336 		return OPCODE_RSR_PRID;
  10337 	      if (Field_sr_Slot_inst_get (insn) == 236)
  10338 		return OPCODE_RSR_ICOUNT;
  10339 	      if (Field_sr_Slot_inst_get (insn) == 237)
  10340 		return OPCODE_RSR_ICOUNTLEVEL;
  10341 	      if (Field_sr_Slot_inst_get (insn) == 238)
  10342 		return OPCODE_RSR_EXCVADDR;
  10343 	      if (Field_sr_Slot_inst_get (insn) == 240)
  10344 		return OPCODE_RSR_CCOMPARE0;
  10345 	      if (Field_sr_Slot_inst_get (insn) == 241)
  10346 		return OPCODE_RSR_CCOMPARE1;
  10347 	      if (Field_sr_Slot_inst_get (insn) == 242)
  10348 		return OPCODE_RSR_CCOMPARE2;
  10349 	      if (Field_sr_Slot_inst_get (insn) == 244)
  10350 		return OPCODE_RSR_MISC0;
  10351 	      if (Field_sr_Slot_inst_get (insn) == 245)
  10352 		return OPCODE_RSR_MISC1;
  10353 	    }
  10354 	  if (Field_op2_Slot_inst_get (insn) == 1)
  10355 	    {
  10356 	      if (Field_sr_Slot_inst_get (insn) == 3)
  10357 		return OPCODE_WSR_SAR;
  10358 	      if (Field_sr_Slot_inst_get (insn) == 5)
  10359 		return OPCODE_WSR_LITBASE;
  10360 	      if (Field_sr_Slot_inst_get (insn) == 12)
  10361 		return OPCODE_WSR_SCOMPARE1;
  10362 	      if (Field_sr_Slot_inst_get (insn) == 72)
  10363 		return OPCODE_WSR_WINDOWBASE;
  10364 	      if (Field_sr_Slot_inst_get (insn) == 73)
  10365 		return OPCODE_WSR_WINDOWSTART;
  10366 	      if (Field_sr_Slot_inst_get (insn) == 89)
  10367 		return OPCODE_WSR_MMID;
  10368 	      if (Field_sr_Slot_inst_get (insn) == 95)
  10369 		return OPCODE_WSR_ERACCESS;
  10370 	      if (Field_sr_Slot_inst_get (insn) == 96)
  10371 		return OPCODE_WSR_IBREAKENABLE;
  10372 	      if (Field_sr_Slot_inst_get (insn) == 97)
  10373 		return OPCODE_WSR_MEMCTL;
  10374 	      if (Field_sr_Slot_inst_get (insn) == 99)
  10375 		return OPCODE_WSR_ATOMCTL;
  10376 	      if (Field_sr_Slot_inst_get (insn) == 104)
  10377 		return OPCODE_WSR_DDR;
  10378 	      if (Field_sr_Slot_inst_get (insn) == 128)
  10379 		return OPCODE_WSR_IBREAKA0;
  10380 	      if (Field_sr_Slot_inst_get (insn) == 129)
  10381 		return OPCODE_WSR_IBREAKA1;
  10382 	      if (Field_sr_Slot_inst_get (insn) == 144)
  10383 		return OPCODE_WSR_DBREAKA0;
  10384 	      if (Field_sr_Slot_inst_get (insn) == 145)
  10385 		return OPCODE_WSR_DBREAKA1;
  10386 	      if (Field_sr_Slot_inst_get (insn) == 160)
  10387 		return OPCODE_WSR_DBREAKC0;
  10388 	      if (Field_sr_Slot_inst_get (insn) == 161)
  10389 		return OPCODE_WSR_DBREAKC1;
  10390 	      if (Field_sr_Slot_inst_get (insn) == 176)
  10391 		return OPCODE_WSR_CONFIGID0;
  10392 	      if (Field_sr_Slot_inst_get (insn) == 177)
  10393 		return OPCODE_WSR_EPC1;
  10394 	      if (Field_sr_Slot_inst_get (insn) == 178)
  10395 		return OPCODE_WSR_EPC2;
  10396 	      if (Field_sr_Slot_inst_get (insn) == 179)
  10397 		return OPCODE_WSR_EPC3;
  10398 	      if (Field_sr_Slot_inst_get (insn) == 180)
  10399 		return OPCODE_WSR_EPC4;
  10400 	      if (Field_sr_Slot_inst_get (insn) == 181)
  10401 		return OPCODE_WSR_EPC5;
  10402 	      if (Field_sr_Slot_inst_get (insn) == 182)
  10403 		return OPCODE_WSR_EPC6;
  10404 	      if (Field_sr_Slot_inst_get (insn) == 183)
  10405 		return OPCODE_WSR_EPC7;
  10406 	      if (Field_sr_Slot_inst_get (insn) == 192)
  10407 		return OPCODE_WSR_DEPC;
  10408 	      if (Field_sr_Slot_inst_get (insn) == 194)
  10409 		return OPCODE_WSR_EPS2;
  10410 	      if (Field_sr_Slot_inst_get (insn) == 195)
  10411 		return OPCODE_WSR_EPS3;
  10412 	      if (Field_sr_Slot_inst_get (insn) == 196)
  10413 		return OPCODE_WSR_EPS4;
  10414 	      if (Field_sr_Slot_inst_get (insn) == 197)
  10415 		return OPCODE_WSR_EPS5;
  10416 	      if (Field_sr_Slot_inst_get (insn) == 198)
  10417 		return OPCODE_WSR_EPS6;
  10418 	      if (Field_sr_Slot_inst_get (insn) == 199)
  10419 		return OPCODE_WSR_EPS7;
  10420 	      if (Field_sr_Slot_inst_get (insn) == 209)
  10421 		return OPCODE_WSR_EXCSAVE1;
  10422 	      if (Field_sr_Slot_inst_get (insn) == 210)
  10423 		return OPCODE_WSR_EXCSAVE2;
  10424 	      if (Field_sr_Slot_inst_get (insn) == 211)
  10425 		return OPCODE_WSR_EXCSAVE3;
  10426 	      if (Field_sr_Slot_inst_get (insn) == 212)
  10427 		return OPCODE_WSR_EXCSAVE4;
  10428 	      if (Field_sr_Slot_inst_get (insn) == 213)
  10429 		return OPCODE_WSR_EXCSAVE5;
  10430 	      if (Field_sr_Slot_inst_get (insn) == 214)
  10431 		return OPCODE_WSR_EXCSAVE6;
  10432 	      if (Field_sr_Slot_inst_get (insn) == 215)
  10433 		return OPCODE_WSR_EXCSAVE7;
  10434 	      if (Field_sr_Slot_inst_get (insn) == 226)
  10435 		return OPCODE_WSR_INTSET;
  10436 	      if (Field_sr_Slot_inst_get (insn) == 227)
  10437 		return OPCODE_WSR_INTCLEAR;
  10438 	      if (Field_sr_Slot_inst_get (insn) == 228)
  10439 		return OPCODE_WSR_INTENABLE;
  10440 	      if (Field_sr_Slot_inst_get (insn) == 230)
  10441 		return OPCODE_WSR_PS;
  10442 	      if (Field_sr_Slot_inst_get (insn) == 231)
  10443 		return OPCODE_WSR_VECBASE;
  10444 	      if (Field_sr_Slot_inst_get (insn) == 232)
  10445 		return OPCODE_WSR_EXCCAUSE;
  10446 	      if (Field_sr_Slot_inst_get (insn) == 233)
  10447 		return OPCODE_WSR_DEBUGCAUSE;
  10448 	      if (Field_sr_Slot_inst_get (insn) == 234)
  10449 		return OPCODE_WSR_CCOUNT;
  10450 	      if (Field_sr_Slot_inst_get (insn) == 236)
  10451 		return OPCODE_WSR_ICOUNT;
  10452 	      if (Field_sr_Slot_inst_get (insn) == 237)
  10453 		return OPCODE_WSR_ICOUNTLEVEL;
  10454 	      if (Field_sr_Slot_inst_get (insn) == 238)
  10455 		return OPCODE_WSR_EXCVADDR;
  10456 	      if (Field_sr_Slot_inst_get (insn) == 240)
  10457 		return OPCODE_WSR_CCOMPARE0;
  10458 	      if (Field_sr_Slot_inst_get (insn) == 241)
  10459 		return OPCODE_WSR_CCOMPARE1;
  10460 	      if (Field_sr_Slot_inst_get (insn) == 242)
  10461 		return OPCODE_WSR_CCOMPARE2;
  10462 	      if (Field_sr_Slot_inst_get (insn) == 244)
  10463 		return OPCODE_WSR_MISC0;
  10464 	      if (Field_sr_Slot_inst_get (insn) == 245)
  10465 		return OPCODE_WSR_MISC1;
  10466 	    }
  10467 	  if (Field_op2_Slot_inst_get (insn) == 2)
  10468 	    return OPCODE_SEXT;
  10469 	  if (Field_op2_Slot_inst_get (insn) == 4)
  10470 	    return OPCODE_MIN;
  10471 	  if (Field_op2_Slot_inst_get (insn) == 5)
  10472 	    return OPCODE_MAX;
  10473 	  if (Field_op2_Slot_inst_get (insn) == 6)
  10474 	    return OPCODE_MINU;
  10475 	  if (Field_op2_Slot_inst_get (insn) == 7)
  10476 	    return OPCODE_MAXU;
  10477 	  if (Field_op2_Slot_inst_get (insn) == 8)
  10478 	    return OPCODE_MOVEQZ;
  10479 	  if (Field_op2_Slot_inst_get (insn) == 9)
  10480 	    return OPCODE_MOVNEZ;
  10481 	  if (Field_op2_Slot_inst_get (insn) == 10)
  10482 	    return OPCODE_MOVLTZ;
  10483 	  if (Field_op2_Slot_inst_get (insn) == 11)
  10484 	    return OPCODE_MOVGEZ;
  10485 	  if (Field_op2_Slot_inst_get (insn) == 14)
  10486 	    {
  10487 	      if (Field_st_Slot_inst_get (insn) == 230)
  10488 		return OPCODE_RUR_EXPSTATE;
  10489 	    }
  10490 	  if (Field_op2_Slot_inst_get (insn) == 15)
  10491 	    {
  10492 	      if (Field_sr_Slot_inst_get (insn) == 230)
  10493 		return OPCODE_WUR_EXPSTATE;
  10494 	    }
  10495 	}
  10496       if ((Field_op1_Slot_inst_get (insn) == 4 ||
  10497 	   Field_op1_Slot_inst_get (insn) == 5))
  10498 	return OPCODE_EXTUI;
  10499       if (Field_op1_Slot_inst_get (insn) == 9)
  10500 	{
  10501 	  if (Field_op2_Slot_inst_get (insn) == 0)
  10502 	    return OPCODE_L32E;
  10503 	  if (Field_op2_Slot_inst_get (insn) == 4)
  10504 	    return OPCODE_S32E;
  10505 	  if (Field_op2_Slot_inst_get (insn) == 5)
  10506 	    return OPCODE_S32NB;
  10507 	}
  10508       if (Field_r_Slot_inst_get (insn) == 0 &&
  10509 	  Field_s_Slot_inst_get (insn) == 0 &&
  10510 	  Field_op2_Slot_inst_get (insn) == 0 &&
  10511 	  Field_op1_Slot_inst_get (insn) == 14)
  10512 	return OPCODE_READ_IMPWIRE;
  10513       if (Field_r_Slot_inst_get (insn) == 1 &&
  10514 	  Field_s3to1_Slot_inst_get (insn) == 0 &&
  10515 	  Field_op2_Slot_inst_get (insn) == 0 &&
  10516 	  Field_op1_Slot_inst_get (insn) == 14)
  10517 	return OPCODE_SETB_EXPSTATE;
  10518       if (Field_r_Slot_inst_get (insn) == 1 &&
  10519 	  Field_s3to1_Slot_inst_get (insn) == 1 &&
  10520 	  Field_op2_Slot_inst_get (insn) == 0 &&
  10521 	  Field_op1_Slot_inst_get (insn) == 14)
  10522 	return OPCODE_CLRB_EXPSTATE;
  10523       if (Field_r_Slot_inst_get (insn) == 2 &&
  10524 	  Field_op2_Slot_inst_get (insn) == 0 &&
  10525 	  Field_op1_Slot_inst_get (insn) == 14)
  10526 	return OPCODE_WRMSK_EXPSTATE;
  10527     }
  10528   if (Field_op0_Slot_inst_get (insn) == 1)
  10529     return OPCODE_L32R;
  10530   if (Field_op0_Slot_inst_get (insn) == 2)
  10531     {
  10532       if (Field_r_Slot_inst_get (insn) == 0)
  10533 	return OPCODE_L8UI;
  10534       if (Field_r_Slot_inst_get (insn) == 1)
  10535 	return OPCODE_L16UI;
  10536       if (Field_r_Slot_inst_get (insn) == 2)
  10537 	return OPCODE_L32I;
  10538       if (Field_r_Slot_inst_get (insn) == 4)
  10539 	return OPCODE_S8I;
  10540       if (Field_r_Slot_inst_get (insn) == 5)
  10541 	return OPCODE_S16I;
  10542       if (Field_r_Slot_inst_get (insn) == 6)
  10543 	return OPCODE_S32I;
  10544       if (Field_r_Slot_inst_get (insn) == 9)
  10545 	return OPCODE_L16SI;
  10546       if (Field_r_Slot_inst_get (insn) == 10)
  10547 	return OPCODE_MOVI;
  10548       if (Field_r_Slot_inst_get (insn) == 11)
  10549 	return OPCODE_L32AI;
  10550       if (Field_r_Slot_inst_get (insn) == 12)
  10551 	return OPCODE_ADDI;
  10552       if (Field_r_Slot_inst_get (insn) == 13)
  10553 	return OPCODE_ADDMI;
  10554       if (Field_r_Slot_inst_get (insn) == 14)
  10555 	return OPCODE_S32C1I;
  10556       if (Field_r_Slot_inst_get (insn) == 15)
  10557 	return OPCODE_S32RI;
  10558     }
  10559   if (Field_op0_Slot_inst_get (insn) == 5)
  10560     {
  10561       if (Field_n_Slot_inst_get (insn) == 0)
  10562 	return OPCODE_CALL0;
  10563       if (Field_n_Slot_inst_get (insn) == 1)
  10564 	return OPCODE_CALL4;
  10565       if (Field_n_Slot_inst_get (insn) == 2)
  10566 	return OPCODE_CALL8;
  10567       if (Field_n_Slot_inst_get (insn) == 3)
  10568 	return OPCODE_CALL12;
  10569     }
  10570   if (Field_op0_Slot_inst_get (insn) == 6)
  10571     {
  10572       if (Field_n_Slot_inst_get (insn) == 0)
  10573 	return OPCODE_J;
  10574       if (Field_n_Slot_inst_get (insn) == 1)
  10575 	{
  10576 	  if (Field_m_Slot_inst_get (insn) == 0)
  10577 	    return OPCODE_BEQZ;
  10578 	  if (Field_m_Slot_inst_get (insn) == 1)
  10579 	    return OPCODE_BNEZ;
  10580 	  if (Field_m_Slot_inst_get (insn) == 2)
  10581 	    return OPCODE_BLTZ;
  10582 	  if (Field_m_Slot_inst_get (insn) == 3)
  10583 	    return OPCODE_BGEZ;
  10584 	}
  10585       if (Field_n_Slot_inst_get (insn) == 2)
  10586 	{
  10587 	  if (Field_m_Slot_inst_get (insn) == 0)
  10588 	    return OPCODE_BEQI;
  10589 	  if (Field_m_Slot_inst_get (insn) == 1)
  10590 	    return OPCODE_BNEI;
  10591 	  if (Field_m_Slot_inst_get (insn) == 2)
  10592 	    return OPCODE_BLTI;
  10593 	  if (Field_m_Slot_inst_get (insn) == 3)
  10594 	    return OPCODE_BGEI;
  10595 	}
  10596       if (Field_n_Slot_inst_get (insn) == 3)
  10597 	{
  10598 	  if (Field_m_Slot_inst_get (insn) == 0)
  10599 	    return OPCODE_ENTRY;
  10600 	  if (Field_m_Slot_inst_get (insn) == 2)
  10601 	    return OPCODE_BLTUI;
  10602 	  if (Field_m_Slot_inst_get (insn) == 3)
  10603 	    return OPCODE_BGEUI;
  10604 	}
  10605     }
  10606   if (Field_op0_Slot_inst_get (insn) == 7)
  10607     {
  10608       if (Field_r_Slot_inst_get (insn) == 0)
  10609 	return OPCODE_BNONE;
  10610       if (Field_r_Slot_inst_get (insn) == 1)
  10611 	return OPCODE_BEQ;
  10612       if (Field_r_Slot_inst_get (insn) == 2)
  10613 	return OPCODE_BLT;
  10614       if (Field_r_Slot_inst_get (insn) == 3)
  10615 	return OPCODE_BLTU;
  10616       if (Field_r_Slot_inst_get (insn) == 4)
  10617 	return OPCODE_BALL;
  10618       if (Field_r_Slot_inst_get (insn) == 5)
  10619 	return OPCODE_BBC;
  10620       if ((Field_r_Slot_inst_get (insn) == 6 ||
  10621 	   Field_r_Slot_inst_get (insn) == 7))
  10622 	return OPCODE_BBCI;
  10623       if (Field_r_Slot_inst_get (insn) == 8)
  10624 	return OPCODE_BANY;
  10625       if (Field_r_Slot_inst_get (insn) == 9)
  10626 	return OPCODE_BNE;
  10627       if (Field_r_Slot_inst_get (insn) == 10)
  10628 	return OPCODE_BGE;
  10629       if (Field_r_Slot_inst_get (insn) == 11)
  10630 	return OPCODE_BGEU;
  10631       if (Field_r_Slot_inst_get (insn) == 12)
  10632 	return OPCODE_BNALL;
  10633       if (Field_r_Slot_inst_get (insn) == 13)
  10634 	return OPCODE_BBS;
  10635       if ((Field_r_Slot_inst_get (insn) == 14 ||
  10636 	   Field_r_Slot_inst_get (insn) == 15))
  10637 	return OPCODE_BBSI;
  10638     }
  10639   return XTENSA_UNDEFINED;
  10640 }
  10641 
  10642 static int
  10643 Slot_inst16b_decode (const xtensa_insnbuf insn)
  10644 {
  10645   if (Field_op0_Slot_inst16b_get (insn) == 12)
  10646     {
  10647       if (Field_i_Slot_inst16b_get (insn) == 0)
  10648 	return OPCODE_MOVI_N;
  10649       if (Field_i_Slot_inst16b_get (insn) == 1)
  10650 	{
  10651 	  if (Field_z_Slot_inst16b_get (insn) == 0)
  10652 	    return OPCODE_BEQZ_N;
  10653 	  if (Field_z_Slot_inst16b_get (insn) == 1)
  10654 	    return OPCODE_BNEZ_N;
  10655 	}
  10656     }
  10657   if (Field_op0_Slot_inst16b_get (insn) == 13)
  10658     {
  10659       if (Field_r_Slot_inst16b_get (insn) == 0)
  10660 	return OPCODE_MOV_N;
  10661       if (Field_r_Slot_inst16b_get (insn) == 15)
  10662 	{
  10663 	  if (Field_t_Slot_inst16b_get (insn) == 0)
  10664 	    return OPCODE_RET_N;
  10665 	  if (Field_t_Slot_inst16b_get (insn) == 1)
  10666 	    return OPCODE_RETW_N;
  10667 	  if (Field_t_Slot_inst16b_get (insn) == 2)
  10668 	    return OPCODE_BREAK_N;
  10669 	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
  10670 	      Field_s_Slot_inst16b_get (insn) == 0)
  10671 	    return OPCODE_NOP_N;
  10672 	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
  10673 	      Field_s_Slot_inst16b_get (insn) == 0)
  10674 	    return OPCODE_ILL_N;
  10675 	}
  10676     }
  10677   return XTENSA_UNDEFINED;
  10678 }
  10679 
  10680 static int
  10681 Slot_inst16a_decode (const xtensa_insnbuf insn)
  10682 {
  10683   if (Field_op0_Slot_inst16a_get (insn) == 8)
  10684     return OPCODE_L32I_N;
  10685   if (Field_op0_Slot_inst16a_get (insn) == 9)
  10686     return OPCODE_S32I_N;
  10687   if (Field_op0_Slot_inst16a_get (insn) == 10)
  10688     return OPCODE_ADD_N;
  10689   if (Field_op0_Slot_inst16a_get (insn) == 11)
  10690     return OPCODE_ADDI_N;
  10691   return XTENSA_UNDEFINED;
  10692 }
  10693 
  10694 
  10695 /* Instruction slots.  */
  10696 
  10697 static void
  10698 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
  10699 			    xtensa_insnbuf slotbuf)
  10700 {
  10701   slotbuf[0] = (insn[0] & 0xffffff);
  10702 }
  10703 
  10704 static void
  10705 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
  10706 			    const xtensa_insnbuf slotbuf)
  10707 {
  10708   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
  10709 }
  10710 
  10711 static void
  10712 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
  10713 				xtensa_insnbuf slotbuf)
  10714 {
  10715   slotbuf[0] = (insn[0] & 0xffff);
  10716 }
  10717 
  10718 static void
  10719 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
  10720 				const xtensa_insnbuf slotbuf)
  10721 {
  10722   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  10723 }
  10724 
  10725 static void
  10726 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
  10727 				xtensa_insnbuf slotbuf)
  10728 {
  10729   slotbuf[0] = (insn[0] & 0xffff);
  10730 }
  10731 
  10732 static void
  10733 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
  10734 				const xtensa_insnbuf slotbuf)
  10735 {
  10736   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  10737 }
  10738 
  10739 static xtensa_get_field_fn
  10740 Slot_inst_get_field_fns[] = {
  10741   Field_t_Slot_inst_get,
  10742   Field_bbi4_Slot_inst_get,
  10743   Field_bbi_Slot_inst_get,
  10744   Field_imm12_Slot_inst_get,
  10745   Field_imm8_Slot_inst_get,
  10746   Field_s_Slot_inst_get,
  10747   Field_imm12b_Slot_inst_get,
  10748   Field_imm16_Slot_inst_get,
  10749   Field_m_Slot_inst_get,
  10750   Field_n_Slot_inst_get,
  10751   Field_offset_Slot_inst_get,
  10752   Field_op0_Slot_inst_get,
  10753   Field_op1_Slot_inst_get,
  10754   Field_op2_Slot_inst_get,
  10755   Field_r_Slot_inst_get,
  10756   Field_sa4_Slot_inst_get,
  10757   Field_sae4_Slot_inst_get,
  10758   Field_sae_Slot_inst_get,
  10759   Field_sal_Slot_inst_get,
  10760   Field_sargt_Slot_inst_get,
  10761   Field_sas4_Slot_inst_get,
  10762   Field_sas_Slot_inst_get,
  10763   Field_sr_Slot_inst_get,
  10764   Field_st_Slot_inst_get,
  10765   Field_thi3_Slot_inst_get,
  10766   Field_imm4_Slot_inst_get,
  10767   Field_mn_Slot_inst_get,
  10768   0,
  10769   0,
  10770   0,
  10771   0,
  10772   0,
  10773   0,
  10774   0,
  10775   0,
  10776   Field_xt_wbr15_imm_Slot_inst_get,
  10777   Field_xt_wbr18_imm_Slot_inst_get,
  10778   Field_bitindex_Slot_inst_get,
  10779   Field_s3to1_Slot_inst_get,
  10780   Implicit_Field_ar0_get,
  10781   Implicit_Field_ar4_get,
  10782   Implicit_Field_ar8_get,
  10783   Implicit_Field_ar12_get
  10784 };
  10785 
  10786 static xtensa_set_field_fn
  10787 Slot_inst_set_field_fns[] = {
  10788   Field_t_Slot_inst_set,
  10789   Field_bbi4_Slot_inst_set,
  10790   Field_bbi_Slot_inst_set,
  10791   Field_imm12_Slot_inst_set,
  10792   Field_imm8_Slot_inst_set,
  10793   Field_s_Slot_inst_set,
  10794   Field_imm12b_Slot_inst_set,
  10795   Field_imm16_Slot_inst_set,
  10796   Field_m_Slot_inst_set,
  10797   Field_n_Slot_inst_set,
  10798   Field_offset_Slot_inst_set,
  10799   Field_op0_Slot_inst_set,
  10800   Field_op1_Slot_inst_set,
  10801   Field_op2_Slot_inst_set,
  10802   Field_r_Slot_inst_set,
  10803   Field_sa4_Slot_inst_set,
  10804   Field_sae4_Slot_inst_set,
  10805   Field_sae_Slot_inst_set,
  10806   Field_sal_Slot_inst_set,
  10807   Field_sargt_Slot_inst_set,
  10808   Field_sas4_Slot_inst_set,
  10809   Field_sas_Slot_inst_set,
  10810   Field_sr_Slot_inst_set,
  10811   Field_st_Slot_inst_set,
  10812   Field_thi3_Slot_inst_set,
  10813   Field_imm4_Slot_inst_set,
  10814   Field_mn_Slot_inst_set,
  10815   0,
  10816   0,
  10817   0,
  10818   0,
  10819   0,
  10820   0,
  10821   0,
  10822   0,
  10823   Field_xt_wbr15_imm_Slot_inst_set,
  10824   Field_xt_wbr18_imm_Slot_inst_set,
  10825   Field_bitindex_Slot_inst_set,
  10826   Field_s3to1_Slot_inst_set,
  10827   Implicit_Field_set,
  10828   Implicit_Field_set,
  10829   Implicit_Field_set,
  10830   Implicit_Field_set
  10831 };
  10832 
  10833 static xtensa_get_field_fn
  10834 Slot_inst16a_get_field_fns[] = {
  10835   Field_t_Slot_inst16a_get,
  10836   0,
  10837   0,
  10838   0,
  10839   0,
  10840   Field_s_Slot_inst16a_get,
  10841   0,
  10842   0,
  10843   0,
  10844   0,
  10845   0,
  10846   Field_op0_Slot_inst16a_get,
  10847   0,
  10848   0,
  10849   Field_r_Slot_inst16a_get,
  10850   0,
  10851   0,
  10852   0,
  10853   0,
  10854   0,
  10855   0,
  10856   0,
  10857   Field_sr_Slot_inst16a_get,
  10858   Field_st_Slot_inst16a_get,
  10859   0,
  10860   Field_imm4_Slot_inst16a_get,
  10861   0,
  10862   Field_i_Slot_inst16a_get,
  10863   Field_imm6lo_Slot_inst16a_get,
  10864   Field_imm6hi_Slot_inst16a_get,
  10865   Field_imm7lo_Slot_inst16a_get,
  10866   Field_imm7hi_Slot_inst16a_get,
  10867   Field_z_Slot_inst16a_get,
  10868   Field_imm6_Slot_inst16a_get,
  10869   Field_imm7_Slot_inst16a_get,
  10870   0,
  10871   0,
  10872   Field_bitindex_Slot_inst16a_get,
  10873   Field_s3to1_Slot_inst16a_get,
  10874   Implicit_Field_ar0_get,
  10875   Implicit_Field_ar4_get,
  10876   Implicit_Field_ar8_get,
  10877   Implicit_Field_ar12_get
  10878 };
  10879 
  10880 static xtensa_set_field_fn
  10881 Slot_inst16a_set_field_fns[] = {
  10882   Field_t_Slot_inst16a_set,
  10883   0,
  10884   0,
  10885   0,
  10886   0,
  10887   Field_s_Slot_inst16a_set,
  10888   0,
  10889   0,
  10890   0,
  10891   0,
  10892   0,
  10893   Field_op0_Slot_inst16a_set,
  10894   0,
  10895   0,
  10896   Field_r_Slot_inst16a_set,
  10897   0,
  10898   0,
  10899   0,
  10900   0,
  10901   0,
  10902   0,
  10903   0,
  10904   Field_sr_Slot_inst16a_set,
  10905   Field_st_Slot_inst16a_set,
  10906   0,
  10907   Field_imm4_Slot_inst16a_set,
  10908   0,
  10909   Field_i_Slot_inst16a_set,
  10910   Field_imm6lo_Slot_inst16a_set,
  10911   Field_imm6hi_Slot_inst16a_set,
  10912   Field_imm7lo_Slot_inst16a_set,
  10913   Field_imm7hi_Slot_inst16a_set,
  10914   Field_z_Slot_inst16a_set,
  10915   Field_imm6_Slot_inst16a_set,
  10916   Field_imm7_Slot_inst16a_set,
  10917   0,
  10918   0,
  10919   Field_bitindex_Slot_inst16a_set,
  10920   Field_s3to1_Slot_inst16a_set,
  10921   Implicit_Field_set,
  10922   Implicit_Field_set,
  10923   Implicit_Field_set,
  10924   Implicit_Field_set
  10925 };
  10926 
  10927 static xtensa_get_field_fn
  10928 Slot_inst16b_get_field_fns[] = {
  10929   Field_t_Slot_inst16b_get,
  10930   0,
  10931   0,
  10932   0,
  10933   0,
  10934   Field_s_Slot_inst16b_get,
  10935   0,
  10936   0,
  10937   0,
  10938   0,
  10939   0,
  10940   Field_op0_Slot_inst16b_get,
  10941   0,
  10942   0,
  10943   Field_r_Slot_inst16b_get,
  10944   0,
  10945   0,
  10946   0,
  10947   0,
  10948   0,
  10949   0,
  10950   0,
  10951   Field_sr_Slot_inst16b_get,
  10952   Field_st_Slot_inst16b_get,
  10953   0,
  10954   Field_imm4_Slot_inst16b_get,
  10955   0,
  10956   Field_i_Slot_inst16b_get,
  10957   Field_imm6lo_Slot_inst16b_get,
  10958   Field_imm6hi_Slot_inst16b_get,
  10959   Field_imm7lo_Slot_inst16b_get,
  10960   Field_imm7hi_Slot_inst16b_get,
  10961   Field_z_Slot_inst16b_get,
  10962   Field_imm6_Slot_inst16b_get,
  10963   Field_imm7_Slot_inst16b_get,
  10964   0,
  10965   0,
  10966   Field_bitindex_Slot_inst16b_get,
  10967   Field_s3to1_Slot_inst16b_get,
  10968   Implicit_Field_ar0_get,
  10969   Implicit_Field_ar4_get,
  10970   Implicit_Field_ar8_get,
  10971   Implicit_Field_ar12_get
  10972 };
  10973 
  10974 static xtensa_set_field_fn
  10975 Slot_inst16b_set_field_fns[] = {
  10976   Field_t_Slot_inst16b_set,
  10977   0,
  10978   0,
  10979   0,
  10980   0,
  10981   Field_s_Slot_inst16b_set,
  10982   0,
  10983   0,
  10984   0,
  10985   0,
  10986   0,
  10987   Field_op0_Slot_inst16b_set,
  10988   0,
  10989   0,
  10990   Field_r_Slot_inst16b_set,
  10991   0,
  10992   0,
  10993   0,
  10994   0,
  10995   0,
  10996   0,
  10997   0,
  10998   Field_sr_Slot_inst16b_set,
  10999   Field_st_Slot_inst16b_set,
  11000   0,
  11001   Field_imm4_Slot_inst16b_set,
  11002   0,
  11003   Field_i_Slot_inst16b_set,
  11004   Field_imm6lo_Slot_inst16b_set,
  11005   Field_imm6hi_Slot_inst16b_set,
  11006   Field_imm7lo_Slot_inst16b_set,
  11007   Field_imm7hi_Slot_inst16b_set,
  11008   Field_z_Slot_inst16b_set,
  11009   Field_imm6_Slot_inst16b_set,
  11010   Field_imm7_Slot_inst16b_set,
  11011   0,
  11012   0,
  11013   Field_bitindex_Slot_inst16b_set,
  11014   Field_s3to1_Slot_inst16b_set,
  11015   Implicit_Field_set,
  11016   Implicit_Field_set,
  11017   Implicit_Field_set,
  11018   Implicit_Field_set
  11019 };
  11020 
  11021 static xtensa_slot_internal slots[] = {
  11022   { "Inst", "x24", 0,
  11023     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
  11024     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
  11025     Slot_inst_decode, "nop" },
  11026   { "Inst16a", "x16a", 0,
  11027     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
  11028     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
  11029     Slot_inst16a_decode, "" },
  11030   { "Inst16b", "x16b", 0,
  11031     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
  11032     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
  11033     Slot_inst16b_decode, "nop.n" }
  11034 };
  11035 
  11036 
  11037 /* Instruction formats.  */
  11038 
  11039 static void
  11040 Format_x24_encode (xtensa_insnbuf insn)
  11041 {
  11042   insn[0] = 0;
  11043 }
  11044 
  11045 static void
  11046 Format_x16a_encode (xtensa_insnbuf insn)
  11047 {
  11048   insn[0] = 0x8;
  11049 }
  11050 
  11051 static void
  11052 Format_x16b_encode (xtensa_insnbuf insn)
  11053 {
  11054   insn[0] = 0xc;
  11055 }
  11056 
  11057 static int Format_x24_slots[] = { 0 };
  11058 
  11059 static int Format_x16a_slots[] = { 1 };
  11060 
  11061 static int Format_x16b_slots[] = { 2 };
  11062 
  11063 static xtensa_format_internal formats[] = {
  11064   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
  11065   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
  11066   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
  11067 };
  11068 
  11069 
  11070 static int
  11071 format_decoder (const xtensa_insnbuf insn)
  11072 {
  11073   if ((insn[0] & 0x8) == 0)
  11074     return 0; /* x24 */
  11075   if ((insn[0] & 0xc) == 0x8)
  11076     return 1; /* x16a */
  11077   if ((insn[0] & 0xe) == 0xc)
  11078     return 2; /* x16b */
  11079   return -1;
  11080 }
  11081 
  11082 static int length_table[256] = {
  11083   3,
  11084   3,
  11085   3,
  11086   3,
  11087   3,
  11088   3,
  11089   3,
  11090   3,
  11091   2,
  11092   2,
  11093   2,
  11094   2,
  11095   2,
  11096   2,
  11097   -1,
  11098   -1,
  11099   3,
  11100   3,
  11101   3,
  11102   3,
  11103   3,
  11104   3,
  11105   3,
  11106   3,
  11107   2,
  11108   2,
  11109   2,
  11110   2,
  11111   2,
  11112   2,
  11113   -1,
  11114   -1,
  11115   3,
  11116   3,
  11117   3,
  11118   3,
  11119   3,
  11120   3,
  11121   3,
  11122   3,
  11123   2,
  11124   2,
  11125   2,
  11126   2,
  11127   2,
  11128   2,
  11129   -1,
  11130   -1,
  11131   3,
  11132   3,
  11133   3,
  11134   3,
  11135   3,
  11136   3,
  11137   3,
  11138   3,
  11139   2,
  11140   2,
  11141   2,
  11142   2,
  11143   2,
  11144   2,
  11145   -1,
  11146   -1,
  11147   3,
  11148   3,
  11149   3,
  11150   3,
  11151   3,
  11152   3,
  11153   3,
  11154   3,
  11155   2,
  11156   2,
  11157   2,
  11158   2,
  11159   2,
  11160   2,
  11161   -1,
  11162   -1,
  11163   3,
  11164   3,
  11165   3,
  11166   3,
  11167   3,
  11168   3,
  11169   3,
  11170   3,
  11171   2,
  11172   2,
  11173   2,
  11174   2,
  11175   2,
  11176   2,
  11177   -1,
  11178   -1,
  11179   3,
  11180   3,
  11181   3,
  11182   3,
  11183   3,
  11184   3,
  11185   3,
  11186   3,
  11187   2,
  11188   2,
  11189   2,
  11190   2,
  11191   2,
  11192   2,
  11193   -1,
  11194   -1,
  11195   3,
  11196   3,
  11197   3,
  11198   3,
  11199   3,
  11200   3,
  11201   3,
  11202   3,
  11203   2,
  11204   2,
  11205   2,
  11206   2,
  11207   2,
  11208   2,
  11209   -1,
  11210   -1,
  11211   3,
  11212   3,
  11213   3,
  11214   3,
  11215   3,
  11216   3,
  11217   3,
  11218   3,
  11219   2,
  11220   2,
  11221   2,
  11222   2,
  11223   2,
  11224   2,
  11225   -1,
  11226   -1,
  11227   3,
  11228   3,
  11229   3,
  11230   3,
  11231   3,
  11232   3,
  11233   3,
  11234   3,
  11235   2,
  11236   2,
  11237   2,
  11238   2,
  11239   2,
  11240   2,
  11241   -1,
  11242   -1,
  11243   3,
  11244   3,
  11245   3,
  11246   3,
  11247   3,
  11248   3,
  11249   3,
  11250   3,
  11251   2,
  11252   2,
  11253   2,
  11254   2,
  11255   2,
  11256   2,
  11257   -1,
  11258   -1,
  11259   3,
  11260   3,
  11261   3,
  11262   3,
  11263   3,
  11264   3,
  11265   3,
  11266   3,
  11267   2,
  11268   2,
  11269   2,
  11270   2,
  11271   2,
  11272   2,
  11273   -1,
  11274   -1,
  11275   3,
  11276   3,
  11277   3,
  11278   3,
  11279   3,
  11280   3,
  11281   3,
  11282   3,
  11283   2,
  11284   2,
  11285   2,
  11286   2,
  11287   2,
  11288   2,
  11289   -1,
  11290   -1,
  11291   3,
  11292   3,
  11293   3,
  11294   3,
  11295   3,
  11296   3,
  11297   3,
  11298   3,
  11299   2,
  11300   2,
  11301   2,
  11302   2,
  11303   2,
  11304   2,
  11305   -1,
  11306   -1,
  11307   3,
  11308   3,
  11309   3,
  11310   3,
  11311   3,
  11312   3,
  11313   3,
  11314   3,
  11315   2,
  11316   2,
  11317   2,
  11318   2,
  11319   2,
  11320   2,
  11321   -1,
  11322   -1,
  11323   3,
  11324   3,
  11325   3,
  11326   3,
  11327   3,
  11328   3,
  11329   3,
  11330   3,
  11331   2,
  11332   2,
  11333   2,
  11334   2,
  11335   2,
  11336   2,
  11337   -1,
  11338   -1
  11339 };
  11340 
  11341 static int
  11342 length_decoder (const unsigned char *insn)
  11343 {
  11344   int l = insn[0];
  11345   return length_table[l];
  11346 }
  11347 
  11348 
  11349 /* Top-level ISA structure.  */
  11350 
  11351 xtensa_isa_internal xtensa_modules = {
  11352   0 /* little-endian */,
  11353   3 /* insn_size */, 0,
  11354   3, formats, format_decoder, length_decoder,
  11355   3, slots,
  11356   43 /* num_fields */,
  11357   77, operands,
  11358   263, iclasses,
  11359   317, opcodes, 0,
  11360   1, regfiles,
  11361   NUM_STATES, states, 0,
  11362   NUM_SYSREGS, sysregs, 0,
  11363   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
  11364   1, interfaces, 0,
  11365   0, funcUnits, 0
  11366 };
	qemu FORK: QEMU emulator
	git clone https://git.neptards.moe/neptards/qemu.git
	Log \| Files \| Refs \| Submodules \| LICENSE