xtensa-modules.c.inc - qemu - FORK: QEMU emulator

xtensa-modules.c.inc (502470B)
      1 /* Xtensa configuration-specific ISA information.
      2 
      3    Copyright (c) 2003-2020 Tensilica Inc.
      4 
      5    Permission is hereby granted, free of charge, to any person obtaining
      6    a copy of this software and associated documentation files (the
      7    "Software"), to deal in the Software without restriction, including
      8    without limitation the rights to use, copy, modify, merge, publish,
      9    distribute, sublicense, and/or sell copies of the Software, and to
     10    permit persons to whom the Software is furnished to do so, subject to
     11    the following conditions:
     12 
     13    The above copyright notice and this permission notice shall be included
     14    in all copies or substantial portions of the Software.
     15 
     16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     17    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     18    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
     19    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
     20    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     21    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     22    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
     23 
     24 #include "xtensa-isa.h"
     25 #include "xtensa-isa-internal.h"
     26 
     27 
     28 /* Sysregs.  */
     29 
     30 static xtensa_sysreg_internal sysregs[] = {
     31   { "LBEG", 0, 0 },
     32   { "LEND", 1, 0 },
     33   { "LCOUNT", 2, 0 },
     34   { "BR", 4, 0 },
     35   { "ACCLO", 16, 0 },
     36   { "ACCHI", 17, 0 },
     37   { "M0", 32, 0 },
     38   { "M1", 33, 0 },
     39   { "M2", 34, 0 },
     40   { "M3", 35, 0 },
     41   { "PTEVADDR", 83, 0 },
     42   { "MMID", 89, 0 },
     43   { "DDR", 104, 0 },
     44   { "CONFIGID0", 176, 0 },
     45   { "CONFIGID1", 208, 0 },
     46   { "INTERRUPT", 226, 0 },
     47   { "INTCLEAR", 227, 0 },
     48   { "CCOUNT", 234, 0 },
     49   { "PRID", 235, 0 },
     50   { "ICOUNT", 236, 0 },
     51   { "CCOMPARE0", 240, 0 },
     52   { "CCOMPARE1", 241, 0 },
     53   { "CCOMPARE2", 242, 0 },
     54   { "VECBASE", 231, 0 },
     55   { "EPC1", 177, 0 },
     56   { "EPC2", 178, 0 },
     57   { "EPC3", 179, 0 },
     58   { "EPC4", 180, 0 },
     59   { "EPC5", 181, 0 },
     60   { "EPC6", 182, 0 },
     61   { "EPC7", 183, 0 },
     62   { "EXCSAVE1", 209, 0 },
     63   { "EXCSAVE2", 210, 0 },
     64   { "EXCSAVE3", 211, 0 },
     65   { "EXCSAVE4", 212, 0 },
     66   { "EXCSAVE5", 213, 0 },
     67   { "EXCSAVE6", 214, 0 },
     68   { "EXCSAVE7", 215, 0 },
     69   { "EPS2", 194, 0 },
     70   { "EPS3", 195, 0 },
     71   { "EPS4", 196, 0 },
     72   { "EPS5", 197, 0 },
     73   { "EPS6", 198, 0 },
     74   { "EPS7", 199, 0 },
     75   { "EXCCAUSE", 232, 0 },
     76   { "DEPC", 192, 0 },
     77   { "EXCVADDR", 238, 0 },
     78   { "WINDOWBASE", 72, 0 },
     79   { "WINDOWSTART", 73, 0 },
     80   { "SAR", 3, 0 },
     81   { "PS", 230, 0 },
     82   { "MISC0", 244, 0 },
     83   { "MISC1", 245, 0 },
     84   { "INTENABLE", 228, 0 },
     85   { "DBREAKA0", 144, 0 },
     86   { "DBREAKC0", 160, 0 },
     87   { "DBREAKA1", 145, 0 },
     88   { "DBREAKC1", 161, 0 },
     89   { "IBREAKA0", 128, 0 },
     90   { "IBREAKA1", 129, 0 },
     91   { "IBREAKENABLE", 96, 0 },
     92   { "ICOUNTLEVEL", 237, 0 },
     93   { "DEBUGCAUSE", 233, 0 },
     94   { "RASID", 90, 0 },
     95   { "ITLBCFG", 91, 0 },
     96   { "DTLBCFG", 92, 0 },
     97   { "CPENABLE", 224, 0 },
     98   { "SCOMPARE1", 12, 0 },
     99   { "ATOMCTL", 99, 0 },
    100   { "ERACCESS", 95, 0 },
    101   { "THREADPTR", 231, 1 },
    102   { "FCR", 232, 1 },
    103   { "FSR", 233, 1 },
    104   { "EXPSTATE", 230, 1 }
    105 };
    106 
    107 #define NUM_SYSREGS 74
    108 #define MAX_SPECIAL_REG 245
    109 #define MAX_USER_REG 233
    110 
    111 
    112 /* Processor states.  */
    113 
    114 static xtensa_state_internal states[] = {
    115   { "LCOUNT", 32, 0 },
    116   { "PC", 32, 0 },
    117   { "ICOUNT", 32, 0 },
    118   { "DDR", 32, 0 },
    119   { "INTERRUPT", 22, 0 },
    120   { "CCOUNT", 32, 0 },
    121   { "XTSYNC", 1, 0 },
    122   { "VECBASE", 22, 0 },
    123   { "EPC1", 32, 0 },
    124   { "EPC2", 32, 0 },
    125   { "EPC3", 32, 0 },
    126   { "EPC4", 32, 0 },
    127   { "EPC5", 32, 0 },
    128   { "EPC6", 32, 0 },
    129   { "EPC7", 32, 0 },
    130   { "EXCSAVE1", 32, 0 },
    131   { "EXCSAVE2", 32, 0 },
    132   { "EXCSAVE3", 32, 0 },
    133   { "EXCSAVE4", 32, 0 },
    134   { "EXCSAVE5", 32, 0 },
    135   { "EXCSAVE6", 32, 0 },
    136   { "EXCSAVE7", 32, 0 },
    137   { "EPS2", 15, 0 },
    138   { "EPS3", 15, 0 },
    139   { "EPS4", 15, 0 },
    140   { "EPS5", 15, 0 },
    141   { "EPS6", 15, 0 },
    142   { "EPS7", 15, 0 },
    143   { "EXCCAUSE", 6, 0 },
    144   { "PSINTLEVEL", 4, 0 },
    145   { "PSUM", 1, 0 },
    146   { "PSWOE", 1, 0 },
    147   { "PSRING", 2, 0 },
    148   { "PSEXCM", 1, 0 },
    149   { "DEPC", 32, 0 },
    150   { "EXCVADDR", 32, 0 },
    151   { "WindowBase", 3, 0 },
    152   { "WindowStart", 8, 0 },
    153   { "PSCALLINC", 2, 0 },
    154   { "PSOWB", 4, 0 },
    155   { "LBEG", 32, 0 },
    156   { "LEND", 32, 0 },
    157   { "SAR", 6, 0 },
    158   { "THREADPTR", 32, 0 },
    159   { "MISC0", 32, 0 },
    160   { "MISC1", 32, 0 },
    161   { "ACC", 40, 0 },
    162   { "InOCDMode", 1, 0 },
    163   { "INTENABLE", 22, 0 },
    164   { "DBREAKA0", 32, 0 },
    165   { "DBREAKC0", 8, 0 },
    166   { "DBREAKA1", 32, 0 },
    167   { "DBREAKC1", 8, 0 },
    168   { "IBREAKA0", 32, 0 },
    169   { "IBREAKA1", 32, 0 },
    170   { "IBREAKENABLE", 2, 0 },
    171   { "ICOUNTLEVEL", 4, 0 },
    172   { "DEBUGCAUSE", 6, 0 },
    173   { "DBNUM", 4, 0 },
    174   { "CCOMPARE0", 32, 0 },
    175   { "CCOMPARE1", 32, 0 },
    176   { "CCOMPARE2", 32, 0 },
    177   { "ASID3", 8, 0 },
    178   { "ASID2", 8, 0 },
    179   { "ASID1", 8, 0 },
    180   { "INSTPGSZID6", 1, 0 },
    181   { "INSTPGSZID5", 1, 0 },
    182   { "INSTPGSZID4", 2, 0 },
    183   { "DATAPGSZID6", 1, 0 },
    184   { "DATAPGSZID5", 1, 0 },
    185   { "DATAPGSZID4", 2, 0 },
    186   { "PTBASE", 10, 0 },
    187   { "CPENABLE", 8, 0 },
    188   { "SCOMPARE1", 32, 0 },
    189   { "ATOMCTL", 6, 0 },
    190   { "ERACCESS", 16, 0 },
    191   { "RoundMode", 2, 0 },
    192   { "InvalidEnable", 1, 0 },
    193   { "DivZeroEnable", 1, 0 },
    194   { "OverflowEnable", 1, 0 },
    195   { "UnderflowEnable", 1, 0 },
    196   { "InexactEnable", 1, 0 },
    197   { "InvalidFlag", 1, XTENSA_STATE_IS_SHARED_OR },
    198   { "DivZeroFlag", 1, XTENSA_STATE_IS_SHARED_OR },
    199   { "OverflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
    200   { "UnderflowFlag", 1, XTENSA_STATE_IS_SHARED_OR },
    201   { "InexactFlag", 1, XTENSA_STATE_IS_SHARED_OR },
    202   { "FPreserved20", 20, 0 },
    203   { "FPreserved20a", 20, 0 },
    204   { "FPreserved5", 5, 0 },
    205   { "FPreserved7", 7, 0 },
    206   { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
    207 };
    208 
    209 #define NUM_STATES 92
    210 
    211 enum xtensa_state_id {
    212   STATE_LCOUNT,
    213   STATE_PC,
    214   STATE_ICOUNT,
    215   STATE_DDR,
    216   STATE_INTERRUPT,
    217   STATE_CCOUNT,
    218   STATE_XTSYNC,
    219   STATE_VECBASE,
    220   STATE_EPC1,
    221   STATE_EPC2,
    222   STATE_EPC3,
    223   STATE_EPC4,
    224   STATE_EPC5,
    225   STATE_EPC6,
    226   STATE_EPC7,
    227   STATE_EXCSAVE1,
    228   STATE_EXCSAVE2,
    229   STATE_EXCSAVE3,
    230   STATE_EXCSAVE4,
    231   STATE_EXCSAVE5,
    232   STATE_EXCSAVE6,
    233   STATE_EXCSAVE7,
    234   STATE_EPS2,
    235   STATE_EPS3,
    236   STATE_EPS4,
    237   STATE_EPS5,
    238   STATE_EPS6,
    239   STATE_EPS7,
    240   STATE_EXCCAUSE,
    241   STATE_PSINTLEVEL,
    242   STATE_PSUM,
    243   STATE_PSWOE,
    244   STATE_PSRING,
    245   STATE_PSEXCM,
    246   STATE_DEPC,
    247   STATE_EXCVADDR,
    248   STATE_WindowBase,
    249   STATE_WindowStart,
    250   STATE_PSCALLINC,
    251   STATE_PSOWB,
    252   STATE_LBEG,
    253   STATE_LEND,
    254   STATE_SAR,
    255   STATE_THREADPTR,
    256   STATE_MISC0,
    257   STATE_MISC1,
    258   STATE_ACC,
    259   STATE_InOCDMode,
    260   STATE_INTENABLE,
    261   STATE_DBREAKA0,
    262   STATE_DBREAKC0,
    263   STATE_DBREAKA1,
    264   STATE_DBREAKC1,
    265   STATE_IBREAKA0,
    266   STATE_IBREAKA1,
    267   STATE_IBREAKENABLE,
    268   STATE_ICOUNTLEVEL,
    269   STATE_DEBUGCAUSE,
    270   STATE_DBNUM,
    271   STATE_CCOMPARE0,
    272   STATE_CCOMPARE1,
    273   STATE_CCOMPARE2,
    274   STATE_ASID3,
    275   STATE_ASID2,
    276   STATE_ASID1,
    277   STATE_INSTPGSZID6,
    278   STATE_INSTPGSZID5,
    279   STATE_INSTPGSZID4,
    280   STATE_DATAPGSZID6,
    281   STATE_DATAPGSZID5,
    282   STATE_DATAPGSZID4,
    283   STATE_PTBASE,
    284   STATE_CPENABLE,
    285   STATE_SCOMPARE1,
    286   STATE_ATOMCTL,
    287   STATE_ERACCESS,
    288   STATE_RoundMode,
    289   STATE_InvalidEnable,
    290   STATE_DivZeroEnable,
    291   STATE_OverflowEnable,
    292   STATE_UnderflowEnable,
    293   STATE_InexactEnable,
    294   STATE_InvalidFlag,
    295   STATE_DivZeroFlag,
    296   STATE_OverflowFlag,
    297   STATE_UnderflowFlag,
    298   STATE_InexactFlag,
    299   STATE_FPreserved20,
    300   STATE_FPreserved20a,
    301   STATE_FPreserved5,
    302   STATE_FPreserved7,
    303   STATE_EXPSTATE
    304 };
    305 
    306 
    307 /* Field definitions.  */
    308 
    309 static unsigned
    310 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
    311 {
    312   unsigned tie_t = 0;
    313   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    314   return tie_t;
    315 }
    316 
    317 static void
    318 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    319 {
    320   uint32 tie_t;
    321   tie_t = (val << 28) >> 28;
    322   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    323 }
    324 
    325 static unsigned
    326 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
    327 {
    328   unsigned tie_t = 0;
    329   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    330   return tie_t;
    331 }
    332 
    333 static void
    334 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    335 {
    336   uint32 tie_t;
    337   tie_t = (val << 28) >> 28;
    338   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    339 }
    340 
    341 static unsigned
    342 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
    343 {
    344   unsigned tie_t = 0;
    345   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    346   return tie_t;
    347 }
    348 
    349 static void
    350 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    351 {
    352   uint32 tie_t;
    353   tie_t = (val << 28) >> 28;
    354   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    355 }
    356 
    357 static unsigned
    358 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
    359 {
    360   unsigned tie_t = 0;
    361   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
    362   return tie_t;
    363 }
    364 
    365 static void
    366 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    367 {
    368   uint32 tie_t;
    369   tie_t = (val << 28) >> 28;
    370   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
    371 }
    372 
    373 static unsigned
    374 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
    375 {
    376   unsigned tie_t = 0;
    377   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
    378   return tie_t;
    379 }
    380 
    381 static void
    382 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    383 {
    384   uint32 tie_t;
    385   tie_t = (val << 28) >> 28;
    386   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
    387 }
    388 
    389 static unsigned
    390 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
    391 {
    392   unsigned tie_t = 0;
    393   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    394   return tie_t;
    395 }
    396 
    397 static void
    398 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    399 {
    400   uint32 tie_t;
    401   tie_t = (val << 28) >> 28;
    402   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    403 }
    404 
    405 static unsigned
    406 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
    407 {
    408   unsigned tie_t = 0;
    409   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    410   return tie_t;
    411 }
    412 
    413 static void
    414 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    415 {
    416   uint32 tie_t;
    417   tie_t = (val << 30) >> 30;
    418   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    419 }
    420 
    421 static unsigned
    422 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
    423 {
    424   unsigned tie_t = 0;
    425   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
    426   return tie_t;
    427 }
    428 
    429 static void
    430 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    431 {
    432   uint32 tie_t;
    433   tie_t = (val << 30) >> 30;
    434   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
    435 }
    436 
    437 static unsigned
    438 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
    439 {
    440   unsigned tie_t = 0;
    441   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    442   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    443   return tie_t;
    444 }
    445 
    446 static void
    447 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    448 {
    449   uint32 tie_t;
    450   tie_t = (val << 28) >> 28;
    451   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    452   tie_t = (val << 24) >> 28;
    453   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    454 }
    455 
    456 static unsigned
    457 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
    458 {
    459   unsigned tie_t = 0;
    460   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    461   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    462   return tie_t;
    463 }
    464 
    465 static void
    466 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    467 {
    468   uint32 tie_t;
    469   tie_t = (val << 28) >> 28;
    470   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    471   tie_t = (val << 24) >> 28;
    472   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    473 }
    474 
    475 static unsigned
    476 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
    477 {
    478   unsigned tie_t = 0;
    479   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
    480   return tie_t;
    481 }
    482 
    483 static void
    484 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    485 {
    486   uint32 tie_t;
    487   tie_t = (val << 29) >> 29;
    488   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
    489 }
    490 
    491 static unsigned
    492 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
    493 {
    494   unsigned tie_t = 0;
    495   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    496   return tie_t;
    497 }
    498 
    499 static void
    500 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    501 {
    502   uint32 tie_t;
    503   tie_t = (val << 31) >> 31;
    504   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    505 }
    506 
    507 static unsigned
    508 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
    509 {
    510   unsigned tie_t = 0;
    511   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    512   return tie_t;
    513 }
    514 
    515 static void
    516 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    517 {
    518   uint32 tie_t;
    519   tie_t = (val << 30) >> 30;
    520   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    521 }
    522 
    523 static unsigned
    524 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
    525 {
    526   unsigned tie_t = 0;
    527   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
    528   return tie_t;
    529 }
    530 
    531 static void
    532 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    533 {
    534   uint32 tie_t;
    535   tie_t = (val << 30) >> 30;
    536   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
    537 }
    538 
    539 static unsigned
    540 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
    541 {
    542   unsigned tie_t = 0;
    543   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
    544   return tie_t;
    545 }
    546 
    547 static void
    548 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    549 {
    550   uint32 tie_t;
    551   tie_t = (val << 31) >> 31;
    552   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
    553 }
    554 
    555 static unsigned
    556 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
    557 {
    558   unsigned tie_t = 0;
    559   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
    560   return tie_t;
    561 }
    562 
    563 static void
    564 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    565 {
    566   uint32 tie_t;
    567   tie_t = (val << 30) >> 30;
    568   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
    569 }
    570 
    571 static unsigned
    572 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
    573 {
    574   unsigned tie_t = 0;
    575   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
    576   return tie_t;
    577 }
    578 
    579 static void
    580 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    581 {
    582   uint32 tie_t;
    583   tie_t = (val << 29) >> 29;
    584   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
    585 }
    586 
    587 static unsigned
    588 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
    589 {
    590   unsigned tie_t = 0;
    591   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    592   return tie_t;
    593 }
    594 
    595 static void
    596 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    597 {
    598   uint32 tie_t;
    599   tie_t = (val << 28) >> 28;
    600   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    601 }
    602 
    603 static unsigned
    604 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
    605 {
    606   unsigned tie_t = 0;
    607   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    608   return tie_t;
    609 }
    610 
    611 static void
    612 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    613 {
    614   uint32 tie_t;
    615   tie_t = (val << 28) >> 28;
    616   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    617 }
    618 
    619 static unsigned
    620 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
    621 {
    622   unsigned tie_t = 0;
    623   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    624   return tie_t;
    625 }
    626 
    627 static void
    628 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    629 {
    630   uint32 tie_t;
    631   tie_t = (val << 28) >> 28;
    632   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    633 }
    634 
    635 static unsigned
    636 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
    637 {
    638   unsigned tie_t = 0;
    639   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    640   return tie_t;
    641 }
    642 
    643 static void
    644 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    645 {
    646   uint32 tie_t;
    647   tie_t = (val << 28) >> 28;
    648   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    649 }
    650 
    651 static unsigned
    652 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
    653 {
    654   unsigned tie_t = 0;
    655   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
    656   return tie_t;
    657 }
    658 
    659 static void
    660 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    661 {
    662   uint32 tie_t;
    663   tie_t = (val << 31) >> 31;
    664   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
    665 }
    666 
    667 static unsigned
    668 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
    669 {
    670   unsigned tie_t = 0;
    671   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    672   return tie_t;
    673 }
    674 
    675 static void
    676 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    677 {
    678   uint32 tie_t;
    679   tie_t = (val << 31) >> 31;
    680   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    681 }
    682 
    683 static unsigned
    684 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
    685 {
    686   unsigned tie_t = 0;
    687   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    688   return tie_t;
    689 }
    690 
    691 static void
    692 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    693 {
    694   uint32 tie_t;
    695   tie_t = (val << 28) >> 28;
    696   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    697 }
    698 
    699 static unsigned
    700 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
    701 {
    702   unsigned tie_t = 0;
    703   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    704   return tie_t;
    705 }
    706 
    707 static void
    708 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    709 {
    710   uint32 tie_t;
    711   tie_t = (val << 28) >> 28;
    712   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    713 }
    714 
    715 static unsigned
    716 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
    717 {
    718   unsigned tie_t = 0;
    719   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    720   return tie_t;
    721 }
    722 
    723 static void
    724 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    725 {
    726   uint32 tie_t;
    727   tie_t = (val << 31) >> 31;
    728   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    729 }
    730 
    731 static unsigned
    732 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
    733 {
    734   unsigned tie_t = 0;
    735   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    736   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    737   return tie_t;
    738 }
    739 
    740 static void
    741 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    742 {
    743   uint32 tie_t;
    744   tie_t = (val << 28) >> 28;
    745   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    746   tie_t = (val << 27) >> 31;
    747   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    748 }
    749 
    750 static unsigned
    751 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
    752 {
    753   unsigned tie_t = 0;
    754   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
    755   return tie_t;
    756 }
    757 
    758 static void
    759 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    760 {
    761   uint32 tie_t;
    762   tie_t = (val << 20) >> 20;
    763   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
    764 }
    765 
    766 static unsigned
    767 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
    768 {
    769   unsigned tie_t = 0;
    770   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    771   return tie_t;
    772 }
    773 
    774 static void
    775 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    776 {
    777   uint32 tie_t;
    778   tie_t = (val << 24) >> 24;
    779   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    780 }
    781 
    782 static unsigned
    783 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
    784 {
    785   unsigned tie_t = 0;
    786   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    787   return tie_t;
    788 }
    789 
    790 static void
    791 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    792 {
    793   uint32 tie_t;
    794   tie_t = (val << 28) >> 28;
    795   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    796 }
    797 
    798 static unsigned
    799 Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
    800 {
    801   unsigned tie_t = 0;
    802   tie_t = (tie_t << 1) | ((insn[0] << 20) >> 31);
    803   return tie_t;
    804 }
    805 
    806 static void
    807 Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    808 {
    809   uint32 tie_t;
    810   tie_t = (val << 31) >> 31;
    811   insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
    812 }
    813 
    814 static unsigned
    815 Field_imms8_Slot_inst_get (const xtensa_insnbuf insn)
    816 {
    817   unsigned tie_t = 0;
    818   tie_t = (tie_t << 3) | ((insn[0] << 21) >> 29);
    819   return tie_t;
    820 }
    821 
    822 static void
    823 Field_imms8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    824 {
    825   uint32 tie_t;
    826   tie_t = (val << 29) >> 29;
    827   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
    828 }
    829 
    830 static unsigned
    831 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
    832 {
    833   unsigned tie_t = 0;
    834   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    835   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    836   return tie_t;
    837 }
    838 
    839 static void
    840 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    841 {
    842   uint32 tie_t;
    843   tie_t = (val << 24) >> 24;
    844   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    845   tie_t = (val << 20) >> 28;
    846   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    847 }
    848 
    849 static unsigned
    850 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
    851 {
    852   unsigned tie_t = 0;
    853   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
    854   return tie_t;
    855 }
    856 
    857 static void
    858 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    859 {
    860   uint32 tie_t;
    861   tie_t = (val << 16) >> 16;
    862   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
    863 }
    864 
    865 static unsigned
    866 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
    867 {
    868   unsigned tie_t = 0;
    869   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
    870   return tie_t;
    871 }
    872 
    873 static void
    874 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    875 {
    876   uint32 tie_t;
    877   tie_t = (val << 14) >> 14;
    878   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
    879 }
    880 
    881 static unsigned
    882 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
    883 {
    884   unsigned tie_t = 0;
    885   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    886   return tie_t;
    887 }
    888 
    889 static void
    890 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    891 {
    892   uint32 tie_t;
    893   tie_t = (val << 28) >> 28;
    894   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    895 }
    896 
    897 static unsigned
    898 Field_r_disp_Slot_inst_get (const xtensa_insnbuf insn)
    899 {
    900   unsigned tie_t = 0;
    901   tie_t = (tie_t << 3) | ((insn[0] << 17) >> 29);
    902   return tie_t;
    903 }
    904 
    905 static void
    906 Field_r_disp_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    907 {
    908   uint32 tie_t;
    909   tie_t = (val << 29) >> 29;
    910   insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
    911 }
    912 
    913 static unsigned
    914 Field_r_3_Slot_inst_get (const xtensa_insnbuf insn)
    915 {
    916   unsigned tie_t = 0;
    917   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
    918   return tie_t;
    919 }
    920 
    921 static void
    922 Field_r_3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    923 {
    924   uint32 tie_t;
    925   tie_t = (val << 31) >> 31;
    926   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
    927 }
    928 
    929 static unsigned
    930 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
    931 {
    932   unsigned tie_t = 0;
    933   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    934   return tie_t;
    935 }
    936 
    937 static void
    938 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    939 {
    940   uint32 tie_t;
    941   tie_t = (val << 31) >> 31;
    942   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    943 }
    944 
    945 static unsigned
    946 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
    947 {
    948   unsigned tie_t = 0;
    949   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    950   return tie_t;
    951 }
    952 
    953 static void
    954 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    955 {
    956   uint32 tie_t;
    957   tie_t = (val << 31) >> 31;
    958   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    959 }
    960 
    961 static unsigned
    962 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
    963 {
    964   unsigned tie_t = 0;
    965   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    966   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    967   return tie_t;
    968 }
    969 
    970 static void
    971 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    972 {
    973   uint32 tie_t;
    974   tie_t = (val << 28) >> 28;
    975   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    976   tie_t = (val << 27) >> 31;
    977   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    978 }
    979 
    980 static unsigned
    981 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
    982 {
    983   unsigned tie_t = 0;
    984   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    985   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    986   return tie_t;
    987 }
    988 
    989 static void
    990 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    991 {
    992   uint32 tie_t;
    993   tie_t = (val << 28) >> 28;
    994   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    995   tie_t = (val << 27) >> 31;
    996   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    997 }
    998 
    999 static unsigned
   1000 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
   1001 {
   1002   unsigned tie_t = 0;
   1003   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
   1004   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
   1005   return tie_t;
   1006 }
   1007 
   1008 static void
   1009 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1010 {
   1011   uint32 tie_t;
   1012   tie_t = (val << 28) >> 28;
   1013   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
   1014   tie_t = (val << 27) >> 31;
   1015   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
   1016 }
   1017 
   1018 static unsigned
   1019 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
   1020 {
   1021   unsigned tie_t = 0;
   1022   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
   1023   return tie_t;
   1024 }
   1025 
   1026 static void
   1027 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1028 {
   1029   uint32 tie_t;
   1030   tie_t = (val << 31) >> 31;
   1031   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
   1032 }
   1033 
   1034 static unsigned
   1035 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
   1036 {
   1037   unsigned tie_t = 0;
   1038   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
   1039   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
   1040   return tie_t;
   1041 }
   1042 
   1043 static void
   1044 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1045 {
   1046   uint32 tie_t;
   1047   tie_t = (val << 28) >> 28;
   1048   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
   1049   tie_t = (val << 27) >> 31;
   1050   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
   1051 }
   1052 
   1053 static unsigned
   1054 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
   1055 {
   1056   unsigned tie_t = 0;
   1057   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1058   return tie_t;
   1059 }
   1060 
   1061 static void
   1062 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1063 {
   1064   uint32 tie_t;
   1065   tie_t = (val << 28) >> 28;
   1066   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1067 }
   1068 
   1069 static unsigned
   1070 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
   1071 {
   1072   unsigned tie_t = 0;
   1073   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
   1074   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1075   return tie_t;
   1076 }
   1077 
   1078 static void
   1079 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1080 {
   1081   uint32 tie_t;
   1082   tie_t = (val << 30) >> 30;
   1083   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1084   tie_t = (val << 28) >> 30;
   1085   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
   1086 }
   1087 
   1088 static unsigned
   1089 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
   1090 {
   1091   unsigned tie_t = 0;
   1092   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
   1093   return tie_t;
   1094 }
   1095 
   1096 static void
   1097 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1098 {
   1099   uint32 tie_t;
   1100   tie_t = (val << 31) >> 31;
   1101   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
   1102 }
   1103 
   1104 static unsigned
   1105 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
   1106 {
   1107   unsigned tie_t = 0;
   1108   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1109   return tie_t;
   1110 }
   1111 
   1112 static void
   1113 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1114 {
   1115   uint32 tie_t;
   1116   tie_t = (val << 28) >> 28;
   1117   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1118 }
   1119 
   1120 static unsigned
   1121 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1122 {
   1123   unsigned tie_t = 0;
   1124   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1125   return tie_t;
   1126 }
   1127 
   1128 static void
   1129 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1130 {
   1131   uint32 tie_t;
   1132   tie_t = (val << 28) >> 28;
   1133   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1134 }
   1135 
   1136 static unsigned
   1137 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1138 {
   1139   unsigned tie_t = 0;
   1140   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1141   return tie_t;
   1142 }
   1143 
   1144 static void
   1145 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1146 {
   1147   uint32 tie_t;
   1148   tie_t = (val << 30) >> 30;
   1149   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1150 }
   1151 
   1152 static unsigned
   1153 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1154 {
   1155   unsigned tie_t = 0;
   1156   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1157   return tie_t;
   1158 }
   1159 
   1160 static void
   1161 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1162 {
   1163   uint32 tie_t;
   1164   tie_t = (val << 30) >> 30;
   1165   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1166 }
   1167 
   1168 static unsigned
   1169 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
   1170 {
   1171   unsigned tie_t = 0;
   1172   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1173   return tie_t;
   1174 }
   1175 
   1176 static void
   1177 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1178 {
   1179   uint32 tie_t;
   1180   tie_t = (val << 28) >> 28;
   1181   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1182 }
   1183 
   1184 static unsigned
   1185 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1186 {
   1187   unsigned tie_t = 0;
   1188   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1189   return tie_t;
   1190 }
   1191 
   1192 static void
   1193 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1194 {
   1195   uint32 tie_t;
   1196   tie_t = (val << 28) >> 28;
   1197   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1198 }
   1199 
   1200 static unsigned
   1201 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1202 {
   1203   unsigned tie_t = 0;
   1204   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1205   return tie_t;
   1206 }
   1207 
   1208 static void
   1209 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1210 {
   1211   uint32 tie_t;
   1212   tie_t = (val << 29) >> 29;
   1213   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1214 }
   1215 
   1216 static unsigned
   1217 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1218 {
   1219   unsigned tie_t = 0;
   1220   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1221   return tie_t;
   1222 }
   1223 
   1224 static void
   1225 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1226 {
   1227   uint32 tie_t;
   1228   tie_t = (val << 29) >> 29;
   1229   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1230 }
   1231 
   1232 static unsigned
   1233 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
   1234 {
   1235   unsigned tie_t = 0;
   1236   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1237   return tie_t;
   1238 }
   1239 
   1240 static void
   1241 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1242 {
   1243   uint32 tie_t;
   1244   tie_t = (val << 31) >> 31;
   1245   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1246 }
   1247 
   1248 static unsigned
   1249 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
   1250 {
   1251   unsigned tie_t = 0;
   1252   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1253   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1254   return tie_t;
   1255 }
   1256 
   1257 static void
   1258 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1259 {
   1260   uint32 tie_t;
   1261   tie_t = (val << 28) >> 28;
   1262   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1263   tie_t = (val << 26) >> 30;
   1264   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1265 }
   1266 
   1267 static unsigned
   1268 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
   1269 {
   1270   unsigned tie_t = 0;
   1271   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1272   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1273   return tie_t;
   1274 }
   1275 
   1276 static void
   1277 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1278 {
   1279   uint32 tie_t;
   1280   tie_t = (val << 28) >> 28;
   1281   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1282   tie_t = (val << 25) >> 29;
   1283   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1284 }
   1285 
   1286 static unsigned
   1287 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
   1288 {
   1289   unsigned tie_t = 0;
   1290   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
   1291   return tie_t;
   1292 }
   1293 
   1294 static void
   1295 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1296 {
   1297   uint32 tie_t;
   1298   tie_t = (val << 31) >> 31;
   1299   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
   1300 }
   1301 
   1302 static unsigned
   1303 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
   1304 {
   1305   unsigned tie_t = 0;
   1306   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1307   return tie_t;
   1308 }
   1309 
   1310 static void
   1311 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1312 {
   1313   uint32 tie_t;
   1314   tie_t = (val << 31) >> 31;
   1315   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1316 }
   1317 
   1318 static unsigned
   1319 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
   1320 {
   1321   unsigned tie_t = 0;
   1322   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1323   return tie_t;
   1324 }
   1325 
   1326 static void
   1327 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1328 {
   1329   uint32 tie_t;
   1330   tie_t = (val << 31) >> 31;
   1331   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1332 }
   1333 
   1334 static unsigned
   1335 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
   1336 {
   1337   unsigned tie_t = 0;
   1338   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
   1339   return tie_t;
   1340 }
   1341 
   1342 static void
   1343 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1344 {
   1345   uint32 tie_t;
   1346   tie_t = (val << 31) >> 31;
   1347   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
   1348 }
   1349 
   1350 static unsigned
   1351 Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
   1352 {
   1353   unsigned tie_t = 0;
   1354   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
   1355   return tie_t;
   1356 }
   1357 
   1358 static void
   1359 Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1360 {
   1361   uint32 tie_t;
   1362   tie_t = (val << 29) >> 29;
   1363   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
   1364 }
   1365 
   1366 static unsigned
   1367 Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
   1368 {
   1369   unsigned tie_t = 0;
   1370   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
   1371   return tie_t;
   1372 }
   1373 
   1374 static void
   1375 Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1376 {
   1377   uint32 tie_t;
   1378   tie_t = (val << 29) >> 29;
   1379   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
   1380 }
   1381 
   1382 static unsigned
   1383 Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
   1384 {
   1385   unsigned tie_t = 0;
   1386   tie_t = (tie_t << 3) | ((insn[0] << 16) >> 29);
   1387   return tie_t;
   1388 }
   1389 
   1390 static void
   1391 Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1392 {
   1393   uint32 tie_t;
   1394   tie_t = (val << 29) >> 29;
   1395   insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
   1396 }
   1397 
   1398 static unsigned
   1399 Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
   1400 {
   1401   unsigned tie_t = 0;
   1402   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
   1403   return tie_t;
   1404 }
   1405 
   1406 static void
   1407 Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1408 {
   1409   uint32 tie_t;
   1410   tie_t = (val << 30) >> 30;
   1411   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
   1412 }
   1413 
   1414 static unsigned
   1415 Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
   1416 {
   1417   unsigned tie_t = 0;
   1418   tie_t = (tie_t << 2) | ((insn[0] << 20) >> 30);
   1419   return tie_t;
   1420 }
   1421 
   1422 static void
   1423 Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1424 {
   1425   uint32 tie_t;
   1426   tie_t = (val << 30) >> 30;
   1427   insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
   1428 }
   1429 
   1430 static unsigned
   1431 Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
   1432 {
   1433   unsigned tie_t = 0;
   1434   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
   1435   return tie_t;
   1436 }
   1437 
   1438 static void
   1439 Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1440 {
   1441   uint32 tie_t;
   1442   tie_t = (val << 30) >> 30;
   1443   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
   1444 }
   1445 
   1446 static unsigned
   1447 Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
   1448 {
   1449   unsigned tie_t = 0;
   1450   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
   1451   return tie_t;
   1452 }
   1453 
   1454 static void
   1455 Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1456 {
   1457   uint32 tie_t;
   1458   tie_t = (val << 31) >> 31;
   1459   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
   1460 }
   1461 
   1462 static unsigned
   1463 Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
   1464 {
   1465   unsigned tie_t = 0;
   1466   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
   1467   return tie_t;
   1468 }
   1469 
   1470 static void
   1471 Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1472 {
   1473   uint32 tie_t;
   1474   tie_t = (val << 31) >> 31;
   1475   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
   1476 }
   1477 
   1478 static unsigned
   1479 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1480 {
   1481   unsigned tie_t = 0;
   1482   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
   1483   return tie_t;
   1484 }
   1485 
   1486 static void
   1487 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1488 {
   1489   uint32 tie_t;
   1490   tie_t = (val << 17) >> 17;
   1491   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
   1492 }
   1493 
   1494 static unsigned
   1495 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1496 {
   1497   unsigned tie_t = 0;
   1498   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
   1499   return tie_t;
   1500 }
   1501 
   1502 static void
   1503 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1504 {
   1505   uint32 tie_t;
   1506   tie_t = (val << 14) >> 14;
   1507   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
   1508 }
   1509 
   1510 static unsigned
   1511 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
   1512 {
   1513   unsigned tie_t = 0;
   1514   tie_t = (tie_t << 5) | ((insn[0] << 23) >> 27);
   1515   return tie_t;
   1516 }
   1517 
   1518 static void
   1519 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1520 {
   1521   uint32 tie_t;
   1522   tie_t = (val << 27) >> 27;
   1523   insn[0] = (insn[0] & ~0x1f0) | (tie_t << 4);
   1524 }
   1525 
   1526 static void
   1527 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
   1528 		    uint32 val ATTRIBUTE_UNUSED)
   1529 {
   1530   /* Do nothing.  */
   1531 }
   1532 
   1533 static unsigned
   1534 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1535 {
   1536   return 0;
   1537 }
   1538 
   1539 static unsigned
   1540 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1541 {
   1542   return 4;
   1543 }
   1544 
   1545 static unsigned
   1546 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1547 {
   1548   return 8;
   1549 }
   1550 
   1551 static unsigned
   1552 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1553 {
   1554   return 12;
   1555 }
   1556 
   1557 static unsigned
   1558 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1559 {
   1560   return 0;
   1561 }
   1562 
   1563 static unsigned
   1564 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1565 {
   1566   return 1;
   1567 }
   1568 
   1569 static unsigned
   1570 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1571 {
   1572   return 2;
   1573 }
   1574 
   1575 static unsigned
   1576 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1577 {
   1578   return 3;
   1579 }
   1580 
   1581 static unsigned
   1582 Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1583 {
   1584   return 0;
   1585 }
   1586 
   1587 static unsigned
   1588 Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1589 {
   1590   return 0;
   1591 }
   1592 
   1593 static unsigned
   1594 Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1595 {
   1596   return 0;
   1597 }
   1598 
   1599 static unsigned
   1600 Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1601 {
   1602   return 0;
   1603 }
   1604 
   1605 enum xtensa_field_id {
   1606   FIELD_t,
   1607   FIELD_bbi4,
   1608   FIELD_bbi,
   1609   FIELD_imm12,
   1610   FIELD_imm8,
   1611   FIELD_s,
   1612   FIELD_s8,
   1613   FIELD_imms8,
   1614   FIELD_imm12b,
   1615   FIELD_imm16,
   1616   FIELD_m,
   1617   FIELD_n,
   1618   FIELD_offset,
   1619   FIELD_op0,
   1620   FIELD_op1,
   1621   FIELD_op2,
   1622   FIELD_r,
   1623   FIELD_r_disp,
   1624   FIELD_r_3,
   1625   FIELD_sa4,
   1626   FIELD_sae4,
   1627   FIELD_sae,
   1628   FIELD_sal,
   1629   FIELD_sargt,
   1630   FIELD_sas4,
   1631   FIELD_sas,
   1632   FIELD_sr,
   1633   FIELD_st,
   1634   FIELD_thi3,
   1635   FIELD_imm4,
   1636   FIELD_mn,
   1637   FIELD_i,
   1638   FIELD_imm6lo,
   1639   FIELD_imm6hi,
   1640   FIELD_imm7lo,
   1641   FIELD_imm7hi,
   1642   FIELD_z,
   1643   FIELD_imm6,
   1644   FIELD_imm7,
   1645   FIELD_r3,
   1646   FIELD_rbit2,
   1647   FIELD_rhi,
   1648   FIELD_t3,
   1649   FIELD_tbit2,
   1650   FIELD_tlo,
   1651   FIELD_w,
   1652   FIELD_y,
   1653   FIELD_x,
   1654   FIELD_t2,
   1655   FIELD_s2,
   1656   FIELD_r2,
   1657   FIELD_t4,
   1658   FIELD_s4,
   1659   FIELD_r4,
   1660   FIELD_t8,
   1661   FIELD_r8,
   1662   FIELD_xt_wbr15_imm,
   1663   FIELD_xt_wbr18_imm,
   1664   FIELD_bitindex,
   1665   FIELD_s3to1,
   1666   FIELD__ar0,
   1667   FIELD__ar4,
   1668   FIELD__ar8,
   1669   FIELD__ar12,
   1670   FIELD__mr0,
   1671   FIELD__mr1,
   1672   FIELD__mr2,
   1673   FIELD__mr3,
   1674   FIELD__bt16,
   1675   FIELD__bs16,
   1676   FIELD__br16,
   1677   FIELD__brall
   1678 };
   1679 
   1680 
   1681 /* Functional units.  */
   1682 
   1683 static xtensa_funcUnit_internal funcUnits[] = {
   1684   {"XT_LOADSTORE_UNIT", 1}
   1685 };
   1686 
   1687 enum xtensa_funcUnit_id {
   1688   FUNCUNIT_XT_LOADSTORE_UNIT
   1689 };
   1690 
   1691 
   1692 /* Register files.  */
   1693 
   1694 enum xtensa_regfile_id {
   1695   REGFILE_AR,
   1696   REGFILE_MR,
   1697   REGFILE_BR,
   1698   REGFILE_FR,
   1699   REGFILE_BR2,
   1700   REGFILE_BR4,
   1701   REGFILE_BR8,
   1702   REGFILE_BR16
   1703 };
   1704 
   1705 static xtensa_regfile_internal regfiles[] = {
   1706   { "AR", "a", REGFILE_AR, 32, 32 },
   1707   { "MR", "m", REGFILE_MR, 32, 4 },
   1708   { "BR", "b", REGFILE_BR, 1, 16 },
   1709   { "FR", "f", REGFILE_FR, 64, 16 },
   1710   { "BR2", "b", REGFILE_BR, 2, 8 },
   1711   { "BR4", "b", REGFILE_BR, 4, 4 },
   1712   { "BR8", "b", REGFILE_BR, 8, 2 },
   1713   { "BR16", "b", REGFILE_BR, 16, 1 }
   1714 };
   1715 
   1716 
   1717 /* Interfaces.  */
   1718 
   1719 static xtensa_interface_internal interfaces[] = {
   1720   { "IMPWIRE", 32, 0, 0, 'i' }
   1721 };
   1722 
   1723 enum xtensa_interface_id {
   1724   INTERFACE_IMPWIRE
   1725 };
   1726 
   1727 
   1728 /* Constant tables.  */
   1729 
   1730 /* constant table ai4c */
   1731 static const unsigned CONST_TBL_ai4c_0[] = {
   1732   0xffffffff,
   1733   0x1,
   1734   0x2,
   1735   0x3,
   1736   0x4,
   1737   0x5,
   1738   0x6,
   1739   0x7,
   1740   0x8,
   1741   0x9,
   1742   0xa,
   1743   0xb,
   1744   0xc,
   1745   0xd,
   1746   0xe,
   1747   0xf,
   1748   0
   1749 };
   1750 
   1751 /* constant table b4c */
   1752 static const unsigned CONST_TBL_b4c_0[] = {
   1753   0xffffffff,
   1754   0x1,
   1755   0x2,
   1756   0x3,
   1757   0x4,
   1758   0x5,
   1759   0x6,
   1760   0x7,
   1761   0x8,
   1762   0xa,
   1763   0xc,
   1764   0x10,
   1765   0x20,
   1766   0x40,
   1767   0x80,
   1768   0x100,
   1769   0
   1770 };
   1771 
   1772 /* constant table b4cu */
   1773 static const unsigned CONST_TBL_b4cu_0[] = {
   1774   0x8000,
   1775   0x10000,
   1776   0x2,
   1777   0x3,
   1778   0x4,
   1779   0x5,
   1780   0x6,
   1781   0x7,
   1782   0x8,
   1783   0xa,
   1784   0xc,
   1785   0x10,
   1786   0x20,
   1787   0x40,
   1788   0x80,
   1789   0x100,
   1790   0
   1791 };
   1792 
   1793 /* constant table RECIP_Data8 */
   1794 static const unsigned CONST_TBL_RECIP_Data8_0[] = {
   1795   0xff & 0xff,
   1796   0xfd & 0xff,
   1797   0xfb & 0xff,
   1798   0xf9 & 0xff,
   1799   0xf7 & 0xff,
   1800   0xf5 & 0xff,
   1801   0xf4 & 0xff,
   1802   0xf2 & 0xff,
   1803   0xf0 & 0xff,
   1804   0xee & 0xff,
   1805   0xed & 0xff,
   1806   0xeb & 0xff,
   1807   0xe9 & 0xff,
   1808   0xe8 & 0xff,
   1809   0xe6 & 0xff,
   1810   0xe4 & 0xff,
   1811   0xe3 & 0xff,
   1812   0xe1 & 0xff,
   1813   0xe0 & 0xff,
   1814   0xde & 0xff,
   1815   0xdd & 0xff,
   1816   0xdb & 0xff,
   1817   0xda & 0xff,
   1818   0xd8 & 0xff,
   1819   0xd7 & 0xff,
   1820   0xd5 & 0xff,
   1821   0xd4 & 0xff,
   1822   0xd3 & 0xff,
   1823   0xd1 & 0xff,
   1824   0xd0 & 0xff,
   1825   0xcf & 0xff,
   1826   0xcd & 0xff,
   1827   0xcc & 0xff,
   1828   0xcb & 0xff,
   1829   0xca & 0xff,
   1830   0xc8 & 0xff,
   1831   0xc7 & 0xff,
   1832   0xc6 & 0xff,
   1833   0xc5 & 0xff,
   1834   0xc4 & 0xff,
   1835   0xc2 & 0xff,
   1836   0xc1 & 0xff,
   1837   0xc0 & 0xff,
   1838   0xbf & 0xff,
   1839   0xbe & 0xff,
   1840   0xbd & 0xff,
   1841   0xbc & 0xff,
   1842   0xbb & 0xff,
   1843   0xba & 0xff,
   1844   0xb9 & 0xff,
   1845   0xb8 & 0xff,
   1846   0xb7 & 0xff,
   1847   0xb6 & 0xff,
   1848   0xb5 & 0xff,
   1849   0xb4 & 0xff,
   1850   0xb3 & 0xff,
   1851   0xb2 & 0xff,
   1852   0xb1 & 0xff,
   1853   0xb0 & 0xff,
   1854   0xaf & 0xff,
   1855   0xae & 0xff,
   1856   0xad & 0xff,
   1857   0xac & 0xff,
   1858   0xab & 0xff,
   1859   0xaa & 0xff,
   1860   0xa9 & 0xff,
   1861   0xa8 & 0xff,
   1862   0xa8 & 0xff,
   1863   0xa7 & 0xff,
   1864   0xa6 & 0xff,
   1865   0xa5 & 0xff,
   1866   0xa4 & 0xff,
   1867   0xa3 & 0xff,
   1868   0xa3 & 0xff,
   1869   0xa2 & 0xff,
   1870   0xa1 & 0xff,
   1871   0xa0 & 0xff,
   1872   0x9f & 0xff,
   1873   0x9f & 0xff,
   1874   0x9e & 0xff,
   1875   0x9d & 0xff,
   1876   0x9c & 0xff,
   1877   0x9c & 0xff,
   1878   0x9b & 0xff,
   1879   0x9a & 0xff,
   1880   0x99 & 0xff,
   1881   0x99 & 0xff,
   1882   0x98 & 0xff,
   1883   0x97 & 0xff,
   1884   0x97 & 0xff,
   1885   0x96 & 0xff,
   1886   0x95 & 0xff,
   1887   0x95 & 0xff,
   1888   0x94 & 0xff,
   1889   0x93 & 0xff,
   1890   0x93 & 0xff,
   1891   0x92 & 0xff,
   1892   0x91 & 0xff,
   1893   0x91 & 0xff,
   1894   0x90 & 0xff,
   1895   0x8f & 0xff,
   1896   0x8f & 0xff,
   1897   0x8e & 0xff,
   1898   0x8e & 0xff,
   1899   0x8d & 0xff,
   1900   0x8c & 0xff,
   1901   0x8c & 0xff,
   1902   0x8b & 0xff,
   1903   0x8b & 0xff,
   1904   0x8a & 0xff,
   1905   0x89 & 0xff,
   1906   0x89 & 0xff,
   1907   0x88 & 0xff,
   1908   0x88 & 0xff,
   1909   0x87 & 0xff,
   1910   0x87 & 0xff,
   1911   0x86 & 0xff,
   1912   0x85 & 0xff,
   1913   0x85 & 0xff,
   1914   0x84 & 0xff,
   1915   0x84 & 0xff,
   1916   0x83 & 0xff,
   1917   0x83 & 0xff,
   1918   0x82 & 0xff,
   1919   0x82 & 0xff,
   1920   0x81 & 0xff,
   1921   0x81 & 0xff,
   1922   0x81 & 0xff,
   1923   0
   1924 };
   1925 
   1926 /* constant table RSQRT_Data8 */
   1927 static const unsigned CONST_TBL_RSQRT_Data8_0[] = {
   1928   0xb4 & 0xff,
   1929   0xb3 & 0xff,
   1930   0xb2 & 0xff,
   1931   0xb0 & 0xff,
   1932   0xaf & 0xff,
   1933   0xae & 0xff,
   1934   0xac & 0xff,
   1935   0xab & 0xff,
   1936   0xaa & 0xff,
   1937   0xa9 & 0xff,
   1938   0xa8 & 0xff,
   1939   0xa7 & 0xff,
   1940   0xa6 & 0xff,
   1941   0xa5 & 0xff,
   1942   0xa3 & 0xff,
   1943   0xa2 & 0xff,
   1944   0xa1 & 0xff,
   1945   0xa0 & 0xff,
   1946   0x9f & 0xff,
   1947   0x9e & 0xff,
   1948   0x9e & 0xff,
   1949   0x9d & 0xff,
   1950   0x9c & 0xff,
   1951   0x9b & 0xff,
   1952   0x9a & 0xff,
   1953   0x99 & 0xff,
   1954   0x98 & 0xff,
   1955   0x97 & 0xff,
   1956   0x97 & 0xff,
   1957   0x96 & 0xff,
   1958   0x95 & 0xff,
   1959   0x94 & 0xff,
   1960   0x93 & 0xff,
   1961   0x93 & 0xff,
   1962   0x92 & 0xff,
   1963   0x91 & 0xff,
   1964   0x90 & 0xff,
   1965   0x90 & 0xff,
   1966   0x8f & 0xff,
   1967   0x8e & 0xff,
   1968   0x8e & 0xff,
   1969   0x8d & 0xff,
   1970   0x8c & 0xff,
   1971   0x8c & 0xff,
   1972   0x8b & 0xff,
   1973   0x8a & 0xff,
   1974   0x8a & 0xff,
   1975   0x89 & 0xff,
   1976   0x89 & 0xff,
   1977   0x88 & 0xff,
   1978   0x87 & 0xff,
   1979   0x87 & 0xff,
   1980   0x86 & 0xff,
   1981   0x86 & 0xff,
   1982   0x85 & 0xff,
   1983   0x84 & 0xff,
   1984   0x84 & 0xff,
   1985   0x83 & 0xff,
   1986   0x83 & 0xff,
   1987   0x82 & 0xff,
   1988   0x82 & 0xff,
   1989   0x81 & 0xff,
   1990   0x81 & 0xff,
   1991   0x80 & 0xff,
   1992   0xff & 0xff,
   1993   0xfd & 0xff,
   1994   0xfb & 0xff,
   1995   0xf9 & 0xff,
   1996   0xf7 & 0xff,
   1997   0xf6 & 0xff,
   1998   0xf4 & 0xff,
   1999   0xf2 & 0xff,
   2000   0xf1 & 0xff,
   2001   0xef & 0xff,
   2002   0xed & 0xff,
   2003   0xec & 0xff,
   2004   0xea & 0xff,
   2005   0xe9 & 0xff,
   2006   0xe7 & 0xff,
   2007   0xe6 & 0xff,
   2008   0xe4 & 0xff,
   2009   0xe3 & 0xff,
   2010   0xe1 & 0xff,
   2011   0xe0 & 0xff,
   2012   0xdf & 0xff,
   2013   0xdd & 0xff,
   2014   0xdc & 0xff,
   2015   0xdb & 0xff,
   2016   0xda & 0xff,
   2017   0xd8 & 0xff,
   2018   0xd7 & 0xff,
   2019   0xd6 & 0xff,
   2020   0xd5 & 0xff,
   2021   0xd4 & 0xff,
   2022   0xd3 & 0xff,
   2023   0xd2 & 0xff,
   2024   0xd0 & 0xff,
   2025   0xcf & 0xff,
   2026   0xce & 0xff,
   2027   0xcd & 0xff,
   2028   0xcc & 0xff,
   2029   0xcb & 0xff,
   2030   0xca & 0xff,
   2031   0xc9 & 0xff,
   2032   0xc8 & 0xff,
   2033   0xc7 & 0xff,
   2034   0xc6 & 0xff,
   2035   0xc6 & 0xff,
   2036   0xc5 & 0xff,
   2037   0xc4 & 0xff,
   2038   0xc3 & 0xff,
   2039   0xc2 & 0xff,
   2040   0xc1 & 0xff,
   2041   0xc0 & 0xff,
   2042   0xbf & 0xff,
   2043   0xbf & 0xff,
   2044   0xbe & 0xff,
   2045   0xbd & 0xff,
   2046   0xbc & 0xff,
   2047   0xbb & 0xff,
   2048   0xbb & 0xff,
   2049   0xba & 0xff,
   2050   0xb9 & 0xff,
   2051   0xb8 & 0xff,
   2052   0xb8 & 0xff,
   2053   0xb7 & 0xff,
   2054   0xb6 & 0xff,
   2055   0xb5 & 0xff,
   2056   0
   2057 };
   2058 
   2059 /* constant table RECIP_Data10_2 */
   2060 static const unsigned CONST_TBL_RECIP_Data10_2_0[] = {
   2061   0x3fc & 0x3ff,
   2062   0x3f4 & 0x3ff,
   2063   0x3ec & 0x3ff,
   2064   0x3e5 & 0x3ff,
   2065   0x3dd & 0x3ff,
   2066   0x3d6 & 0x3ff,
   2067   0x3cf & 0x3ff,
   2068   0x3c7 & 0x3ff,
   2069   0x3c0 & 0x3ff,
   2070   0x3b9 & 0x3ff,
   2071   0x3b2 & 0x3ff,
   2072   0x3ac & 0x3ff,
   2073   0x3a5 & 0x3ff,
   2074   0x39e & 0x3ff,
   2075   0x398 & 0x3ff,
   2076   0x391 & 0x3ff,
   2077   0x38b & 0x3ff,
   2078   0x385 & 0x3ff,
   2079   0x37f & 0x3ff,
   2080   0x378 & 0x3ff,
   2081   0x373 & 0x3ff,
   2082   0x36c & 0x3ff,
   2083   0x367 & 0x3ff,
   2084   0x361 & 0x3ff,
   2085   0x35c & 0x3ff,
   2086   0x356 & 0x3ff,
   2087   0x350 & 0x3ff,
   2088   0x34b & 0x3ff,
   2089   0x345 & 0x3ff,
   2090   0x340 & 0x3ff,
   2091   0x33b & 0x3ff,
   2092   0x335 & 0x3ff,
   2093   0x330 & 0x3ff,
   2094   0x32c & 0x3ff,
   2095   0x327 & 0x3ff,
   2096   0x322 & 0x3ff,
   2097   0x31c & 0x3ff,
   2098   0x318 & 0x3ff,
   2099   0x314 & 0x3ff,
   2100   0x30e & 0x3ff,
   2101   0x30a & 0x3ff,
   2102   0x306 & 0x3ff,
   2103   0x300 & 0x3ff,
   2104   0x2fc & 0x3ff,
   2105   0x2f8 & 0x3ff,
   2106   0x2f4 & 0x3ff,
   2107   0x2f0 & 0x3ff,
   2108   0x2ea & 0x3ff,
   2109   0x2e6 & 0x3ff,
   2110   0x2e2 & 0x3ff,
   2111   0x2de & 0x3ff,
   2112   0x2da & 0x3ff,
   2113   0x2d6 & 0x3ff,
   2114   0x2d2 & 0x3ff,
   2115   0x2ce & 0x3ff,
   2116   0x2ca & 0x3ff,
   2117   0x2c6 & 0x3ff,
   2118   0x2c2 & 0x3ff,
   2119   0x2be & 0x3ff,
   2120   0x2ba & 0x3ff,
   2121   0x2b8 & 0x3ff,
   2122   0x2b4 & 0x3ff,
   2123   0x2b0 & 0x3ff,
   2124   0x2ac & 0x3ff,
   2125   0x2a8 & 0x3ff,
   2126   0x2a6 & 0x3ff,
   2127   0x2a2 & 0x3ff,
   2128   0x29e & 0x3ff,
   2129   0x29c & 0x3ff,
   2130   0x298 & 0x3ff,
   2131   0x294 & 0x3ff,
   2132   0x290 & 0x3ff,
   2133   0x28e & 0x3ff,
   2134   0x28a & 0x3ff,
   2135   0x288 & 0x3ff,
   2136   0x284 & 0x3ff,
   2137   0x280 & 0x3ff,
   2138   0x27e & 0x3ff,
   2139   0x27a & 0x3ff,
   2140   0x278 & 0x3ff,
   2141   0x274 & 0x3ff,
   2142   0x272 & 0x3ff,
   2143   0x26e & 0x3ff,
   2144   0x26c & 0x3ff,
   2145   0x268 & 0x3ff,
   2146   0x266 & 0x3ff,
   2147   0x264 & 0x3ff,
   2148   0x260 & 0x3ff,
   2149   0x25e & 0x3ff,
   2150   0x25a & 0x3ff,
   2151   0x258 & 0x3ff,
   2152   0x254 & 0x3ff,
   2153   0x252 & 0x3ff,
   2154   0x250 & 0x3ff,
   2155   0x24c & 0x3ff,
   2156   0x24a & 0x3ff,
   2157   0x248 & 0x3ff,
   2158   0x246 & 0x3ff,
   2159   0x242 & 0x3ff,
   2160   0x240 & 0x3ff,
   2161   0x23e & 0x3ff,
   2162   0x23c & 0x3ff,
   2163   0x238 & 0x3ff,
   2164   0x236 & 0x3ff,
   2165   0x234 & 0x3ff,
   2166   0x232 & 0x3ff,
   2167   0x230 & 0x3ff,
   2168   0x22c & 0x3ff,
   2169   0x22a & 0x3ff,
   2170   0x228 & 0x3ff,
   2171   0x226 & 0x3ff,
   2172   0x224 & 0x3ff,
   2173   0x220 & 0x3ff,
   2174   0x21e & 0x3ff,
   2175   0x21c & 0x3ff,
   2176   0x21a & 0x3ff,
   2177   0x218 & 0x3ff,
   2178   0x216 & 0x3ff,
   2179   0x214 & 0x3ff,
   2180   0x212 & 0x3ff,
   2181   0x210 & 0x3ff,
   2182   0x20e & 0x3ff,
   2183   0x20c & 0x3ff,
   2184   0x208 & 0x3ff,
   2185   0x208 & 0x3ff,
   2186   0x204 & 0x3ff,
   2187   0x204 & 0x3ff,
   2188   0x201 & 0x3ff,
   2189   0
   2190 };
   2191 
   2192 /* constant table RSQRT_10b_256 */
   2193 static const unsigned CONST_TBL_RSQRT_10b_256_0[] = {
   2194   0x1a5 & 0x3ff,
   2195   0x1a0 & 0x3ff,
   2196   0x19a & 0x3ff,
   2197   0x195 & 0x3ff,
   2198   0x18f & 0x3ff,
   2199   0x18a & 0x3ff,
   2200   0x185 & 0x3ff,
   2201   0x180 & 0x3ff,
   2202   0x17a & 0x3ff,
   2203   0x175 & 0x3ff,
   2204   0x170 & 0x3ff,
   2205   0x16b & 0x3ff,
   2206   0x166 & 0x3ff,
   2207   0x161 & 0x3ff,
   2208   0x15d & 0x3ff,
   2209   0x158 & 0x3ff,
   2210   0x153 & 0x3ff,
   2211   0x14e & 0x3ff,
   2212   0x14a & 0x3ff,
   2213   0x145 & 0x3ff,
   2214   0x140 & 0x3ff,
   2215   0x13c & 0x3ff,
   2216   0x138 & 0x3ff,
   2217   0x133 & 0x3ff,
   2218   0x12f & 0x3ff,
   2219   0x12a & 0x3ff,
   2220   0x126 & 0x3ff,
   2221   0x122 & 0x3ff,
   2222   0x11e & 0x3ff,
   2223   0x11a & 0x3ff,
   2224   0x115 & 0x3ff,
   2225   0x111 & 0x3ff,
   2226   0x10d & 0x3ff,
   2227   0x109 & 0x3ff,
   2228   0x105 & 0x3ff,
   2229   0x101 & 0x3ff,
   2230   0xfd & 0x3ff,
   2231   0xfa & 0x3ff,
   2232   0xf6 & 0x3ff,
   2233   0xf2 & 0x3ff,
   2234   0xee & 0x3ff,
   2235   0xea & 0x3ff,
   2236   0xe7 & 0x3ff,
   2237   0xe3 & 0x3ff,
   2238   0xdf & 0x3ff,
   2239   0xdc & 0x3ff,
   2240   0xd8 & 0x3ff,
   2241   0xd5 & 0x3ff,
   2242   0xd1 & 0x3ff,
   2243   0xce & 0x3ff,
   2244   0xca & 0x3ff,
   2245   0xc7 & 0x3ff,
   2246   0xc3 & 0x3ff,
   2247   0xc0 & 0x3ff,
   2248   0xbd & 0x3ff,
   2249   0xb9 & 0x3ff,
   2250   0xb6 & 0x3ff,
   2251   0xb3 & 0x3ff,
   2252   0xb0 & 0x3ff,
   2253   0xad & 0x3ff,
   2254   0xa9 & 0x3ff,
   2255   0xa6 & 0x3ff,
   2256   0xa3 & 0x3ff,
   2257   0xa0 & 0x3ff,
   2258   0x9d & 0x3ff,
   2259   0x9a & 0x3ff,
   2260   0x97 & 0x3ff,
   2261   0x94 & 0x3ff,
   2262   0x91 & 0x3ff,
   2263   0x8e & 0x3ff,
   2264   0x8b & 0x3ff,
   2265   0x88 & 0x3ff,
   2266   0x85 & 0x3ff,
   2267   0x82 & 0x3ff,
   2268   0x7f & 0x3ff,
   2269   0x7d & 0x3ff,
   2270   0x7a & 0x3ff,
   2271   0x77 & 0x3ff,
   2272   0x74 & 0x3ff,
   2273   0x71 & 0x3ff,
   2274   0x6f & 0x3ff,
   2275   0x6c & 0x3ff,
   2276   0x69 & 0x3ff,
   2277   0x67 & 0x3ff,
   2278   0x64 & 0x3ff,
   2279   0x61 & 0x3ff,
   2280   0x5f & 0x3ff,
   2281   0x5c & 0x3ff,
   2282   0x5a & 0x3ff,
   2283   0x57 & 0x3ff,
   2284   0x54 & 0x3ff,
   2285   0x52 & 0x3ff,
   2286   0x4f & 0x3ff,
   2287   0x4d & 0x3ff,
   2288   0x4a & 0x3ff,
   2289   0x48 & 0x3ff,
   2290   0x45 & 0x3ff,
   2291   0x43 & 0x3ff,
   2292   0x41 & 0x3ff,
   2293   0x3e & 0x3ff,
   2294   0x3c & 0x3ff,
   2295   0x3a & 0x3ff,
   2296   0x37 & 0x3ff,
   2297   0x35 & 0x3ff,
   2298   0x33 & 0x3ff,
   2299   0x30 & 0x3ff,
   2300   0x2e & 0x3ff,
   2301   0x2c & 0x3ff,
   2302   0x29 & 0x3ff,
   2303   0x27 & 0x3ff,
   2304   0x25 & 0x3ff,
   2305   0x23 & 0x3ff,
   2306   0x20 & 0x3ff,
   2307   0x1e & 0x3ff,
   2308   0x1c & 0x3ff,
   2309   0x1a & 0x3ff,
   2310   0x18 & 0x3ff,
   2311   0x16 & 0x3ff,
   2312   0x14 & 0x3ff,
   2313   0x11 & 0x3ff,
   2314   0xf & 0x3ff,
   2315   0xd & 0x3ff,
   2316   0xb & 0x3ff,
   2317   0x9 & 0x3ff,
   2318   0x7 & 0x3ff,
   2319   0x5 & 0x3ff,
   2320   0x3 & 0x3ff,
   2321   0x1 & 0x3ff,
   2322   0x3fc & 0x3ff,
   2323   0x3f4 & 0x3ff,
   2324   0x3ec & 0x3ff,
   2325   0x3e5 & 0x3ff,
   2326   0x3dd & 0x3ff,
   2327   0x3d5 & 0x3ff,
   2328   0x3ce & 0x3ff,
   2329   0x3c7 & 0x3ff,
   2330   0x3bf & 0x3ff,
   2331   0x3b8 & 0x3ff,
   2332   0x3b1 & 0x3ff,
   2333   0x3aa & 0x3ff,
   2334   0x3a3 & 0x3ff,
   2335   0x39c & 0x3ff,
   2336   0x395 & 0x3ff,
   2337   0x38e & 0x3ff,
   2338   0x388 & 0x3ff,
   2339   0x381 & 0x3ff,
   2340   0x37a & 0x3ff,
   2341   0x374 & 0x3ff,
   2342   0x36d & 0x3ff,
   2343   0x367 & 0x3ff,
   2344   0x361 & 0x3ff,
   2345   0x35a & 0x3ff,
   2346   0x354 & 0x3ff,
   2347   0x34e & 0x3ff,
   2348   0x348 & 0x3ff,
   2349   0x342 & 0x3ff,
   2350   0x33c & 0x3ff,
   2351   0x336 & 0x3ff,
   2352   0x330 & 0x3ff,
   2353   0x32b & 0x3ff,
   2354   0x325 & 0x3ff,
   2355   0x31f & 0x3ff,
   2356   0x31a & 0x3ff,
   2357   0x314 & 0x3ff,
   2358   0x30f & 0x3ff,
   2359   0x309 & 0x3ff,
   2360   0x304 & 0x3ff,
   2361   0x2fe & 0x3ff,
   2362   0x2f9 & 0x3ff,
   2363   0x2f4 & 0x3ff,
   2364   0x2ee & 0x3ff,
   2365   0x2e9 & 0x3ff,
   2366   0x2e4 & 0x3ff,
   2367   0x2df & 0x3ff,
   2368   0x2da & 0x3ff,
   2369   0x2d5 & 0x3ff,
   2370   0x2d0 & 0x3ff,
   2371   0x2cb & 0x3ff,
   2372   0x2c6 & 0x3ff,
   2373   0x2c1 & 0x3ff,
   2374   0x2bd & 0x3ff,
   2375   0x2b8 & 0x3ff,
   2376   0x2b3 & 0x3ff,
   2377   0x2ae & 0x3ff,
   2378   0x2aa & 0x3ff,
   2379   0x2a5 & 0x3ff,
   2380   0x2a1 & 0x3ff,
   2381   0x29c & 0x3ff,
   2382   0x298 & 0x3ff,
   2383   0x293 & 0x3ff,
   2384   0x28f & 0x3ff,
   2385   0x28a & 0x3ff,
   2386   0x286 & 0x3ff,
   2387   0x282 & 0x3ff,
   2388   0x27d & 0x3ff,
   2389   0x279 & 0x3ff,
   2390   0x275 & 0x3ff,
   2391   0x271 & 0x3ff,
   2392   0x26d & 0x3ff,
   2393   0x268 & 0x3ff,
   2394   0x264 & 0x3ff,
   2395   0x260 & 0x3ff,
   2396   0x25c & 0x3ff,
   2397   0x258 & 0x3ff,
   2398   0x254 & 0x3ff,
   2399   0x250 & 0x3ff,
   2400   0x24c & 0x3ff,
   2401   0x249 & 0x3ff,
   2402   0x245 & 0x3ff,
   2403   0x241 & 0x3ff,
   2404   0x23d & 0x3ff,
   2405   0x239 & 0x3ff,
   2406   0x235 & 0x3ff,
   2407   0x232 & 0x3ff,
   2408   0x22e & 0x3ff,
   2409   0x22a & 0x3ff,
   2410   0x227 & 0x3ff,
   2411   0x223 & 0x3ff,
   2412   0x220 & 0x3ff,
   2413   0x21c & 0x3ff,
   2414   0x218 & 0x3ff,
   2415   0x215 & 0x3ff,
   2416   0x211 & 0x3ff,
   2417   0x20e & 0x3ff,
   2418   0x20a & 0x3ff,
   2419   0x207 & 0x3ff,
   2420   0x204 & 0x3ff,
   2421   0x200 & 0x3ff,
   2422   0x1fd & 0x3ff,
   2423   0x1f9 & 0x3ff,
   2424   0x1f6 & 0x3ff,
   2425   0x1f3 & 0x3ff,
   2426   0x1f0 & 0x3ff,
   2427   0x1ec & 0x3ff,
   2428   0x1e9 & 0x3ff,
   2429   0x1e6 & 0x3ff,
   2430   0x1e3 & 0x3ff,
   2431   0x1df & 0x3ff,
   2432   0x1dc & 0x3ff,
   2433   0x1d9 & 0x3ff,
   2434   0x1d6 & 0x3ff,
   2435   0x1d3 & 0x3ff,
   2436   0x1d0 & 0x3ff,
   2437   0x1cd & 0x3ff,
   2438   0x1ca & 0x3ff,
   2439   0x1c7 & 0x3ff,
   2440   0x1c4 & 0x3ff,
   2441   0x1c1 & 0x3ff,
   2442   0x1be & 0x3ff,
   2443   0x1bb & 0x3ff,
   2444   0x1b8 & 0x3ff,
   2445   0x1b5 & 0x3ff,
   2446   0x1b2 & 0x3ff,
   2447   0x1af & 0x3ff,
   2448   0x1ac & 0x3ff,
   2449   0x1aa & 0x3ff,
   2450   0
   2451 };
   2452 
   2453 /* constant table RECIP_10b_256 */
   2454 static const unsigned CONST_TBL_RECIP_10b_256_0[] = {
   2455   0x3fc & 0x3ff,
   2456   0x3f4 & 0x3ff,
   2457   0x3ec & 0x3ff,
   2458   0x3e4 & 0x3ff,
   2459   0x3dd & 0x3ff,
   2460   0x3d5 & 0x3ff,
   2461   0x3cd & 0x3ff,
   2462   0x3c6 & 0x3ff,
   2463   0x3be & 0x3ff,
   2464   0x3b7 & 0x3ff,
   2465   0x3af & 0x3ff,
   2466   0x3a8 & 0x3ff,
   2467   0x3a1 & 0x3ff,
   2468   0x399 & 0x3ff,
   2469   0x392 & 0x3ff,
   2470   0x38b & 0x3ff,
   2471   0x384 & 0x3ff,
   2472   0x37d & 0x3ff,
   2473   0x376 & 0x3ff,
   2474   0x36f & 0x3ff,
   2475   0x368 & 0x3ff,
   2476   0x361 & 0x3ff,
   2477   0x35b & 0x3ff,
   2478   0x354 & 0x3ff,
   2479   0x34d & 0x3ff,
   2480   0x346 & 0x3ff,
   2481   0x340 & 0x3ff,
   2482   0x339 & 0x3ff,
   2483   0x333 & 0x3ff,
   2484   0x32c & 0x3ff,
   2485   0x326 & 0x3ff,
   2486   0x320 & 0x3ff,
   2487   0x319 & 0x3ff,
   2488   0x313 & 0x3ff,
   2489   0x30d & 0x3ff,
   2490   0x307 & 0x3ff,
   2491   0x300 & 0x3ff,
   2492   0x2fa & 0x3ff,
   2493   0x2f4 & 0x3ff,
   2494   0x2ee & 0x3ff,
   2495   0x2e8 & 0x3ff,
   2496   0x2e2 & 0x3ff,
   2497   0x2dc & 0x3ff,
   2498   0x2d7 & 0x3ff,
   2499   0x2d1 & 0x3ff,
   2500   0x2cb & 0x3ff,
   2501   0x2c5 & 0x3ff,
   2502   0x2bf & 0x3ff,
   2503   0x2ba & 0x3ff,
   2504   0x2b4 & 0x3ff,
   2505   0x2af & 0x3ff,
   2506   0x2a9 & 0x3ff,
   2507   0x2a3 & 0x3ff,
   2508   0x29e & 0x3ff,
   2509   0x299 & 0x3ff,
   2510   0x293 & 0x3ff,
   2511   0x28e & 0x3ff,
   2512   0x288 & 0x3ff,
   2513   0x283 & 0x3ff,
   2514   0x27e & 0x3ff,
   2515   0x279 & 0x3ff,
   2516   0x273 & 0x3ff,
   2517   0x26e & 0x3ff,
   2518   0x269 & 0x3ff,
   2519   0x264 & 0x3ff,
   2520   0x25f & 0x3ff,
   2521   0x25a & 0x3ff,
   2522   0x255 & 0x3ff,
   2523   0x250 & 0x3ff,
   2524   0x24b & 0x3ff,
   2525   0x246 & 0x3ff,
   2526   0x241 & 0x3ff,
   2527   0x23c & 0x3ff,
   2528   0x237 & 0x3ff,
   2529   0x232 & 0x3ff,
   2530   0x22e & 0x3ff,
   2531   0x229 & 0x3ff,
   2532   0x224 & 0x3ff,
   2533   0x21f & 0x3ff,
   2534   0x21b & 0x3ff,
   2535   0x216 & 0x3ff,
   2536   0x211 & 0x3ff,
   2537   0x20d & 0x3ff,
   2538   0x208 & 0x3ff,
   2539   0x204 & 0x3ff,
   2540   0x1ff & 0x3ff,
   2541   0x1fb & 0x3ff,
   2542   0x1f6 & 0x3ff,
   2543   0x1f2 & 0x3ff,
   2544   0x1ed & 0x3ff,
   2545   0x1e9 & 0x3ff,
   2546   0x1e5 & 0x3ff,
   2547   0x1e0 & 0x3ff,
   2548   0x1dc & 0x3ff,
   2549   0x1d8 & 0x3ff,
   2550   0x1d4 & 0x3ff,
   2551   0x1cf & 0x3ff,
   2552   0x1cb & 0x3ff,
   2553   0x1c7 & 0x3ff,
   2554   0x1c3 & 0x3ff,
   2555   0x1bf & 0x3ff,
   2556   0x1bb & 0x3ff,
   2557   0x1b6 & 0x3ff,
   2558   0x1b2 & 0x3ff,
   2559   0x1ae & 0x3ff,
   2560   0x1aa & 0x3ff,
   2561   0x1a6 & 0x3ff,
   2562   0x1a2 & 0x3ff,
   2563   0x19e & 0x3ff,
   2564   0x19a & 0x3ff,
   2565   0x197 & 0x3ff,
   2566   0x193 & 0x3ff,
   2567   0x18f & 0x3ff,
   2568   0x18b & 0x3ff,
   2569   0x187 & 0x3ff,
   2570   0x183 & 0x3ff,
   2571   0x17f & 0x3ff,
   2572   0x17c & 0x3ff,
   2573   0x178 & 0x3ff,
   2574   0x174 & 0x3ff,
   2575   0x171 & 0x3ff,
   2576   0x16d & 0x3ff,
   2577   0x169 & 0x3ff,
   2578   0x166 & 0x3ff,
   2579   0x162 & 0x3ff,
   2580   0x15e & 0x3ff,
   2581   0x15b & 0x3ff,
   2582   0x157 & 0x3ff,
   2583   0x154 & 0x3ff,
   2584   0x150 & 0x3ff,
   2585   0x14d & 0x3ff,
   2586   0x149 & 0x3ff,
   2587   0x146 & 0x3ff,
   2588   0x142 & 0x3ff,
   2589   0x13f & 0x3ff,
   2590   0x13b & 0x3ff,
   2591   0x138 & 0x3ff,
   2592   0x134 & 0x3ff,
   2593   0x131 & 0x3ff,
   2594   0x12e & 0x3ff,
   2595   0x12a & 0x3ff,
   2596   0x127 & 0x3ff,
   2597   0x124 & 0x3ff,
   2598   0x120 & 0x3ff,
   2599   0x11d & 0x3ff,
   2600   0x11a & 0x3ff,
   2601   0x117 & 0x3ff,
   2602   0x113 & 0x3ff,
   2603   0x110 & 0x3ff,
   2604   0x10d & 0x3ff,
   2605   0x10a & 0x3ff,
   2606   0x107 & 0x3ff,
   2607   0x103 & 0x3ff,
   2608   0x100 & 0x3ff,
   2609   0xfd & 0x3ff,
   2610   0xfa & 0x3ff,
   2611   0xf7 & 0x3ff,
   2612   0xf4 & 0x3ff,
   2613   0xf1 & 0x3ff,
   2614   0xee & 0x3ff,
   2615   0xeb & 0x3ff,
   2616   0xe8 & 0x3ff,
   2617   0xe5 & 0x3ff,
   2618   0xe2 & 0x3ff,
   2619   0xdf & 0x3ff,
   2620   0xdc & 0x3ff,
   2621   0xd9 & 0x3ff,
   2622   0xd6 & 0x3ff,
   2623   0xd3 & 0x3ff,
   2624   0xd0 & 0x3ff,
   2625   0xcd & 0x3ff,
   2626   0xca & 0x3ff,
   2627   0xc8 & 0x3ff,
   2628   0xc5 & 0x3ff,
   2629   0xc2 & 0x3ff,
   2630   0xbf & 0x3ff,
   2631   0xbc & 0x3ff,
   2632   0xb9 & 0x3ff,
   2633   0xb7 & 0x3ff,
   2634   0xb4 & 0x3ff,
   2635   0xb1 & 0x3ff,
   2636   0xae & 0x3ff,
   2637   0xac & 0x3ff,
   2638   0xa9 & 0x3ff,
   2639   0xa6 & 0x3ff,
   2640   0xa4 & 0x3ff,
   2641   0xa1 & 0x3ff,
   2642   0x9e & 0x3ff,
   2643   0x9c & 0x3ff,
   2644   0x99 & 0x3ff,
   2645   0x96 & 0x3ff,
   2646   0x94 & 0x3ff,
   2647   0x91 & 0x3ff,
   2648   0x8e & 0x3ff,
   2649   0x8c & 0x3ff,
   2650   0x89 & 0x3ff,
   2651   0x87 & 0x3ff,
   2652   0x84 & 0x3ff,
   2653   0x82 & 0x3ff,
   2654   0x7f & 0x3ff,
   2655   0x7c & 0x3ff,
   2656   0x7a & 0x3ff,
   2657   0x77 & 0x3ff,
   2658   0x75 & 0x3ff,
   2659   0x73 & 0x3ff,
   2660   0x70 & 0x3ff,
   2661   0x6e & 0x3ff,
   2662   0x6b & 0x3ff,
   2663   0x69 & 0x3ff,
   2664   0x66 & 0x3ff,
   2665   0x64 & 0x3ff,
   2666   0x61 & 0x3ff,
   2667   0x5f & 0x3ff,
   2668   0x5d & 0x3ff,
   2669   0x5a & 0x3ff,
   2670   0x58 & 0x3ff,
   2671   0x56 & 0x3ff,
   2672   0x53 & 0x3ff,
   2673   0x51 & 0x3ff,
   2674   0x4f & 0x3ff,
   2675   0x4c & 0x3ff,
   2676   0x4a & 0x3ff,
   2677   0x48 & 0x3ff,
   2678   0x45 & 0x3ff,
   2679   0x43 & 0x3ff,
   2680   0x41 & 0x3ff,
   2681   0x3f & 0x3ff,
   2682   0x3c & 0x3ff,
   2683   0x3a & 0x3ff,
   2684   0x38 & 0x3ff,
   2685   0x36 & 0x3ff,
   2686   0x33 & 0x3ff,
   2687   0x31 & 0x3ff,
   2688   0x2f & 0x3ff,
   2689   0x2d & 0x3ff,
   2690   0x2b & 0x3ff,
   2691   0x29 & 0x3ff,
   2692   0x26 & 0x3ff,
   2693   0x24 & 0x3ff,
   2694   0x22 & 0x3ff,
   2695   0x20 & 0x3ff,
   2696   0x1e & 0x3ff,
   2697   0x1c & 0x3ff,
   2698   0x1a & 0x3ff,
   2699   0x18 & 0x3ff,
   2700   0x15 & 0x3ff,
   2701   0x13 & 0x3ff,
   2702   0x11 & 0x3ff,
   2703   0xf & 0x3ff,
   2704   0xd & 0x3ff,
   2705   0xb & 0x3ff,
   2706   0x9 & 0x3ff,
   2707   0x7 & 0x3ff,
   2708   0x5 & 0x3ff,
   2709   0x3 & 0x3ff,
   2710   0x1 & 0x3ff,
   2711   0
   2712 };
   2713 
   2714 
   2715 /* Instruction operands.  */
   2716 
   2717 static int
   2718 OperandSem_opnd_sem_MR_0_decode (uint32 *valp)
   2719 {
   2720   *valp += 2;
   2721   return 0;
   2722 }
   2723 
   2724 static int
   2725 OperandSem_opnd_sem_MR_0_encode (uint32 *valp)
   2726 {
   2727   int error;
   2728   error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
   2729   *valp = *valp & 1;
   2730   return error;
   2731 }
   2732 
   2733 static int
   2734 OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
   2735 {
   2736   unsigned soffsetx4_out_0;
   2737   unsigned soffsetx4_in_0;
   2738   soffsetx4_in_0 = *valp & 0x3ffff;
   2739   soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
   2740   *valp = soffsetx4_out_0;
   2741   return 0;
   2742 }
   2743 
   2744 static int
   2745 OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
   2746 {
   2747   unsigned soffsetx4_in_0;
   2748   unsigned soffsetx4_out_0;
   2749   soffsetx4_out_0 = *valp;
   2750   soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
   2751   *valp = soffsetx4_in_0;
   2752   return 0;
   2753 }
   2754 
   2755 static int
   2756 OperandSem_opnd_sem_immr_decode (uint32 *valp)
   2757 {
   2758   unsigned immr_out_0;
   2759   unsigned immr_in_0;
   2760   immr_in_0 = *valp & 0xf;
   2761   immr_out_0 = immr_in_0;
   2762   *valp = immr_out_0;
   2763   return 0;
   2764 }
   2765 
   2766 static int
   2767 OperandSem_opnd_sem_immr_encode (uint32 *valp)
   2768 {
   2769   unsigned immr_in_0;
   2770   unsigned immr_out_0;
   2771   immr_out_0 = *valp;
   2772   immr_in_0 = (immr_out_0 & 0xf);
   2773   *valp = immr_in_0;
   2774   return 0;
   2775 }
   2776 
   2777 static int
   2778 OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
   2779 {
   2780   unsigned uimm12x8_out_0;
   2781   unsigned uimm12x8_in_0;
   2782   uimm12x8_in_0 = *valp & 0xfff;
   2783   uimm12x8_out_0 = uimm12x8_in_0 << 3;
   2784   *valp = uimm12x8_out_0;
   2785   return 0;
   2786 }
   2787 
   2788 static int
   2789 OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
   2790 {
   2791   unsigned uimm12x8_in_0;
   2792   unsigned uimm12x8_out_0;
   2793   uimm12x8_out_0 = *valp;
   2794   uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
   2795   *valp = uimm12x8_in_0;
   2796   return 0;
   2797 }
   2798 
   2799 static int
   2800 OperandSem_opnd_sem_simm4_decode (uint32 *valp)
   2801 {
   2802   unsigned simm4_out_0;
   2803   unsigned simm4_in_0;
   2804   simm4_in_0 = *valp & 0xf;
   2805   simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
   2806   *valp = simm4_out_0;
   2807   return 0;
   2808 }
   2809 
   2810 static int
   2811 OperandSem_opnd_sem_simm4_encode (uint32 *valp)
   2812 {
   2813   unsigned simm4_in_0;
   2814   unsigned simm4_out_0;
   2815   simm4_out_0 = *valp;
   2816   simm4_in_0 = (simm4_out_0 & 0xf);
   2817   *valp = simm4_in_0;
   2818   return 0;
   2819 }
   2820 
   2821 static int
   2822 OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2823 {
   2824   return 0;
   2825 }
   2826 
   2827 static int
   2828 OperandSem_opnd_sem_AR_encode (uint32 *valp)
   2829 {
   2830   int error;
   2831   error = (*valp >= 32);
   2832   return error;
   2833 }
   2834 
   2835 static int
   2836 OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2837 {
   2838   return 0;
   2839 }
   2840 
   2841 static int
   2842 OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
   2843 {
   2844   int error;
   2845   error = (*valp >= 32);
   2846   return error;
   2847 }
   2848 
   2849 static int
   2850 OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2851 {
   2852   return 0;
   2853 }
   2854 
   2855 static int
   2856 OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
   2857 {
   2858   int error;
   2859   error = (*valp >= 32);
   2860   return error;
   2861 }
   2862 
   2863 static int
   2864 OperandSem_opnd_sem_AR_8_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2865 {
   2866   return 0;
   2867 }
   2868 
   2869 static int
   2870 OperandSem_opnd_sem_AR_8_encode (uint32 *valp)
   2871 {
   2872   int error;
   2873   error = (*valp >= 32);
   2874   return error;
   2875 }
   2876 
   2877 static int
   2878 OperandSem_opnd_sem_AR_12_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2879 {
   2880   return 0;
   2881 }
   2882 
   2883 static int
   2884 OperandSem_opnd_sem_AR_12_encode (uint32 *valp)
   2885 {
   2886   int error;
   2887   error = (*valp >= 32);
   2888   return error;
   2889 }
   2890 
   2891 static int
   2892 OperandSem_opnd_sem_AR_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2893 {
   2894   return 0;
   2895 }
   2896 
   2897 static int
   2898 OperandSem_opnd_sem_AR_entry_encode (uint32 *valp)
   2899 {
   2900   int error;
   2901   error = (*valp >= 32);
   2902   return error;
   2903 }
   2904 
   2905 static int
   2906 OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
   2907 {
   2908   unsigned immrx4_out_0;
   2909   unsigned immrx4_in_0;
   2910   immrx4_in_0 = *valp & 0xf;
   2911   immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
   2912   *valp = immrx4_out_0;
   2913   return 0;
   2914 }
   2915 
   2916 static int
   2917 OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
   2918 {
   2919   unsigned immrx4_in_0;
   2920   unsigned immrx4_out_0;
   2921   immrx4_out_0 = *valp;
   2922   immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
   2923   *valp = immrx4_in_0;
   2924   return 0;
   2925 }
   2926 
   2927 static int
   2928 OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
   2929 {
   2930   unsigned lsi4x4_out_0;
   2931   unsigned lsi4x4_in_0;
   2932   lsi4x4_in_0 = *valp & 0xf;
   2933   lsi4x4_out_0 = lsi4x4_in_0 << 2;
   2934   *valp = lsi4x4_out_0;
   2935   return 0;
   2936 }
   2937 
   2938 static int
   2939 OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
   2940 {
   2941   unsigned lsi4x4_in_0;
   2942   unsigned lsi4x4_out_0;
   2943   lsi4x4_out_0 = *valp;
   2944   lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
   2945   *valp = lsi4x4_in_0;
   2946   return 0;
   2947 }
   2948 
   2949 static int
   2950 OperandSem_opnd_sem_simm7_decode (uint32 *valp)
   2951 {
   2952   unsigned simm7_out_0;
   2953   unsigned simm7_in_0;
   2954   simm7_in_0 = *valp & 0x7f;
   2955   simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
   2956   *valp = simm7_out_0;
   2957   return 0;
   2958 }
   2959 
   2960 static int
   2961 OperandSem_opnd_sem_simm7_encode (uint32 *valp)
   2962 {
   2963   unsigned simm7_in_0;
   2964   unsigned simm7_out_0;
   2965   simm7_out_0 = *valp;
   2966   simm7_in_0 = (simm7_out_0 & 0x7f);
   2967   *valp = simm7_in_0;
   2968   return 0;
   2969 }
   2970 
   2971 static int
   2972 OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
   2973 {
   2974   unsigned uimm6_out_0;
   2975   unsigned uimm6_in_0;
   2976   uimm6_in_0 = *valp & 0x3f;
   2977   uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
   2978   *valp = uimm6_out_0;
   2979   return 0;
   2980 }
   2981 
   2982 static int
   2983 OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
   2984 {
   2985   unsigned uimm6_in_0;
   2986   unsigned uimm6_out_0;
   2987   uimm6_out_0 = *valp;
   2988   uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
   2989   *valp = uimm6_in_0;
   2990   return 0;
   2991 }
   2992 
   2993 static int
   2994 OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
   2995 {
   2996   unsigned ai4const_out_0;
   2997   unsigned ai4const_in_0;
   2998   ai4const_in_0 = *valp & 0xf;
   2999   ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
   3000   *valp = ai4const_out_0;
   3001   return 0;
   3002 }
   3003 
   3004 static int
   3005 OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
   3006 {
   3007   unsigned ai4const_in_0;
   3008   unsigned ai4const_out_0;
   3009   ai4const_out_0 = *valp;
   3010   switch (ai4const_out_0)
   3011     {
   3012     case 0xffffffff: ai4const_in_0 = 0; break;
   3013     case 0x1: ai4const_in_0 = 0x1; break;
   3014     case 0x2: ai4const_in_0 = 0x2; break;
   3015     case 0x3: ai4const_in_0 = 0x3; break;
   3016     case 0x4: ai4const_in_0 = 0x4; break;
   3017     case 0x5: ai4const_in_0 = 0x5; break;
   3018     case 0x6: ai4const_in_0 = 0x6; break;
   3019     case 0x7: ai4const_in_0 = 0x7; break;
   3020     case 0x8: ai4const_in_0 = 0x8; break;
   3021     case 0x9: ai4const_in_0 = 0x9; break;
   3022     case 0xa: ai4const_in_0 = 0xa; break;
   3023     case 0xb: ai4const_in_0 = 0xb; break;
   3024     case 0xc: ai4const_in_0 = 0xc; break;
   3025     case 0xd: ai4const_in_0 = 0xd; break;
   3026     case 0xe: ai4const_in_0 = 0xe; break;
   3027     default: ai4const_in_0 = 0xf; break;
   3028     }
   3029   *valp = ai4const_in_0;
   3030   return 0;
   3031 }
   3032 
   3033 static int
   3034 OperandSem_opnd_sem_b4const_decode (uint32 *valp)
   3035 {
   3036   unsigned b4const_out_0;
   3037   unsigned b4const_in_0;
   3038   b4const_in_0 = *valp & 0xf;
   3039   b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
   3040   *valp = b4const_out_0;
   3041   return 0;
   3042 }
   3043 
   3044 static int
   3045 OperandSem_opnd_sem_b4const_encode (uint32 *valp)
   3046 {
   3047   unsigned b4const_in_0;
   3048   unsigned b4const_out_0;
   3049   b4const_out_0 = *valp;
   3050   switch (b4const_out_0)
   3051     {
   3052     case 0xffffffff: b4const_in_0 = 0; break;
   3053     case 0x1: b4const_in_0 = 0x1; break;
   3054     case 0x2: b4const_in_0 = 0x2; break;
   3055     case 0x3: b4const_in_0 = 0x3; break;
   3056     case 0x4: b4const_in_0 = 0x4; break;
   3057     case 0x5: b4const_in_0 = 0x5; break;
   3058     case 0x6: b4const_in_0 = 0x6; break;
   3059     case 0x7: b4const_in_0 = 0x7; break;
   3060     case 0x8: b4const_in_0 = 0x8; break;
   3061     case 0xa: b4const_in_0 = 0x9; break;
   3062     case 0xc: b4const_in_0 = 0xa; break;
   3063     case 0x10: b4const_in_0 = 0xb; break;
   3064     case 0x20: b4const_in_0 = 0xc; break;
   3065     case 0x40: b4const_in_0 = 0xd; break;
   3066     case 0x80: b4const_in_0 = 0xe; break;
   3067     default: b4const_in_0 = 0xf; break;
   3068     }
   3069   *valp = b4const_in_0;
   3070   return 0;
   3071 }
   3072 
   3073 static int
   3074 OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
   3075 {
   3076   unsigned b4constu_out_0;
   3077   unsigned b4constu_in_0;
   3078   b4constu_in_0 = *valp & 0xf;
   3079   b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
   3080   *valp = b4constu_out_0;
   3081   return 0;
   3082 }
   3083 
   3084 static int
   3085 OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
   3086 {
   3087   unsigned b4constu_in_0;
   3088   unsigned b4constu_out_0;
   3089   b4constu_out_0 = *valp;
   3090   switch (b4constu_out_0)
   3091     {
   3092     case 0x8000: b4constu_in_0 = 0; break;
   3093     case 0x10000: b4constu_in_0 = 0x1; break;
   3094     case 0x2: b4constu_in_0 = 0x2; break;
   3095     case 0x3: b4constu_in_0 = 0x3; break;
   3096     case 0x4: b4constu_in_0 = 0x4; break;
   3097     case 0x5: b4constu_in_0 = 0x5; break;
   3098     case 0x6: b4constu_in_0 = 0x6; break;
   3099     case 0x7: b4constu_in_0 = 0x7; break;
   3100     case 0x8: b4constu_in_0 = 0x8; break;
   3101     case 0xa: b4constu_in_0 = 0x9; break;
   3102     case 0xc: b4constu_in_0 = 0xa; break;
   3103     case 0x10: b4constu_in_0 = 0xb; break;
   3104     case 0x20: b4constu_in_0 = 0xc; break;
   3105     case 0x40: b4constu_in_0 = 0xd; break;
   3106     case 0x80: b4constu_in_0 = 0xe; break;
   3107     default: b4constu_in_0 = 0xf; break;
   3108     }
   3109   *valp = b4constu_in_0;
   3110   return 0;
   3111 }
   3112 
   3113 static int
   3114 OperandSem_opnd_sem_immt_decode (uint32 *valp)
   3115 {
   3116   unsigned immt_out_0;
   3117   unsigned immt_in_0;
   3118   immt_in_0 = *valp & 0xf;
   3119   immt_out_0 = immt_in_0;
   3120   *valp = immt_out_0;
   3121   return 0;
   3122 }
   3123 
   3124 static int
   3125 OperandSem_opnd_sem_immt_encode (uint32 *valp)
   3126 {
   3127   unsigned immt_in_0;
   3128   unsigned immt_out_0;
   3129   immt_out_0 = *valp;
   3130   immt_in_0 = immt_out_0 & 0xf;
   3131   *valp = immt_in_0;
   3132   return 0;
   3133 }
   3134 
   3135 static int
   3136 OperandSem_opnd_sem_uimms8_decode (uint32 *valp)
   3137 {
   3138   unsigned uimms8_out_0;
   3139   unsigned uimms8_in_0;
   3140   uimms8_in_0 = *valp & 0x7;
   3141   uimms8_out_0 = uimms8_in_0;
   3142   *valp = uimms8_out_0;
   3143   return 0;
   3144 }
   3145 
   3146 static int
   3147 OperandSem_opnd_sem_uimms8_encode (uint32 *valp)
   3148 {
   3149   unsigned uimms8_in_0;
   3150   unsigned uimms8_out_0;
   3151   uimms8_out_0 = *valp;
   3152   uimms8_in_0 = uimms8_out_0 & 0x7;
   3153   *valp = uimms8_in_0;
   3154   return 0;
   3155 }
   3156 
   3157 static int
   3158 OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
   3159 {
   3160   unsigned uimm8_out_0;
   3161   unsigned uimm8_in_0;
   3162   uimm8_in_0 = *valp & 0xff;
   3163   uimm8_out_0 = uimm8_in_0;
   3164   *valp = uimm8_out_0;
   3165   return 0;
   3166 }
   3167 
   3168 static int
   3169 OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
   3170 {
   3171   unsigned uimm8_in_0;
   3172   unsigned uimm8_out_0;
   3173   uimm8_out_0 = *valp;
   3174   uimm8_in_0 = (uimm8_out_0 & 0xff);
   3175   *valp = uimm8_in_0;
   3176   return 0;
   3177 }
   3178 
   3179 static int
   3180 OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
   3181 {
   3182   unsigned uimm8x2_out_0;
   3183   unsigned uimm8x2_in_0;
   3184   uimm8x2_in_0 = *valp & 0xff;
   3185   uimm8x2_out_0 = uimm8x2_in_0 << 1;
   3186   *valp = uimm8x2_out_0;
   3187   return 0;
   3188 }
   3189 
   3190 static int
   3191 OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
   3192 {
   3193   unsigned uimm8x2_in_0;
   3194   unsigned uimm8x2_out_0;
   3195   uimm8x2_out_0 = *valp;
   3196   uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
   3197   *valp = uimm8x2_in_0;
   3198   return 0;
   3199 }
   3200 
   3201 static int
   3202 OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
   3203 {
   3204   unsigned uimm8x4_out_0;
   3205   unsigned uimm8x4_in_0;
   3206   uimm8x4_in_0 = *valp & 0xff;
   3207   uimm8x4_out_0 = uimm8x4_in_0 << 2;
   3208   *valp = uimm8x4_out_0;
   3209   return 0;
   3210 }
   3211 
   3212 static int
   3213 OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
   3214 {
   3215   unsigned uimm8x4_in_0;
   3216   unsigned uimm8x4_out_0;
   3217   uimm8x4_out_0 = *valp;
   3218   uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
   3219   *valp = uimm8x4_in_0;
   3220   return 0;
   3221 }
   3222 
   3223 static int
   3224 OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
   3225 {
   3226   unsigned uimm4x16_out_0;
   3227   unsigned uimm4x16_in_0;
   3228   uimm4x16_in_0 = *valp & 0xf;
   3229   uimm4x16_out_0 = uimm4x16_in_0 << 4;
   3230   *valp = uimm4x16_out_0;
   3231   return 0;
   3232 }
   3233 
   3234 static int
   3235 OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
   3236 {
   3237   unsigned uimm4x16_in_0;
   3238   unsigned uimm4x16_out_0;
   3239   uimm4x16_out_0 = *valp;
   3240   uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
   3241   *valp = uimm4x16_in_0;
   3242   return 0;
   3243 }
   3244 
   3245 static int
   3246 OperandSem_opnd_sem_uimmrx4_decode (uint32 *valp)
   3247 {
   3248   unsigned uimmrx4_out_0;
   3249   unsigned uimmrx4_in_0;
   3250   uimmrx4_in_0 = *valp & 0xf;
   3251   uimmrx4_out_0 = uimmrx4_in_0 << 2;
   3252   *valp = uimmrx4_out_0;
   3253   return 0;
   3254 }
   3255 
   3256 static int
   3257 OperandSem_opnd_sem_uimmrx4_encode (uint32 *valp)
   3258 {
   3259   unsigned uimmrx4_in_0;
   3260   unsigned uimmrx4_out_0;
   3261   uimmrx4_out_0 = *valp;
   3262   uimmrx4_in_0 = ((uimmrx4_out_0 >> 2) & 0xf);
   3263   *valp = uimmrx4_in_0;
   3264   return 0;
   3265 }
   3266 
   3267 static int
   3268 OperandSem_opnd_sem_simm8_decode (uint32 *valp)
   3269 {
   3270   unsigned simm8_out_0;
   3271   unsigned simm8_in_0;
   3272   simm8_in_0 = *valp & 0xff;
   3273   simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
   3274   *valp = simm8_out_0;
   3275   return 0;
   3276 }
   3277 
   3278 static int
   3279 OperandSem_opnd_sem_simm8_encode (uint32 *valp)
   3280 {
   3281   unsigned simm8_in_0;
   3282   unsigned simm8_out_0;
   3283   simm8_out_0 = *valp;
   3284   simm8_in_0 = (simm8_out_0 & 0xff);
   3285   *valp = simm8_in_0;
   3286   return 0;
   3287 }
   3288 
   3289 static int
   3290 OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
   3291 {
   3292   unsigned simm8x256_out_0;
   3293   unsigned simm8x256_in_0;
   3294   simm8x256_in_0 = *valp & 0xff;
   3295   simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
   3296   *valp = simm8x256_out_0;
   3297   return 0;
   3298 }
   3299 
   3300 static int
   3301 OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
   3302 {
   3303   unsigned simm8x256_in_0;
   3304   unsigned simm8x256_out_0;
   3305   simm8x256_out_0 = *valp;
   3306   simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
   3307   *valp = simm8x256_in_0;
   3308   return 0;
   3309 }
   3310 
   3311 static int
   3312 OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
   3313 {
   3314   unsigned simm12b_out_0;
   3315   unsigned simm12b_in_0;
   3316   simm12b_in_0 = *valp & 0xfff;
   3317   simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
   3318   *valp = simm12b_out_0;
   3319   return 0;
   3320 }
   3321 
   3322 static int
   3323 OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
   3324 {
   3325   unsigned simm12b_in_0;
   3326   unsigned simm12b_out_0;
   3327   simm12b_out_0 = *valp;
   3328   simm12b_in_0 = (simm12b_out_0 & 0xfff);
   3329   *valp = simm12b_in_0;
   3330   return 0;
   3331 }
   3332 
   3333 static int
   3334 OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
   3335 {
   3336   unsigned msalp32_out_0;
   3337   unsigned msalp32_in_0;
   3338   msalp32_in_0 = *valp & 0x1f;
   3339   msalp32_out_0 = 0x20 - msalp32_in_0;
   3340   *valp = msalp32_out_0;
   3341   return 0;
   3342 }
   3343 
   3344 static int
   3345 OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
   3346 {
   3347   unsigned msalp32_in_0;
   3348   unsigned msalp32_out_0;
   3349   msalp32_out_0 = *valp;
   3350   msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
   3351   *valp = msalp32_in_0;
   3352   return 0;
   3353 }
   3354 
   3355 static int
   3356 OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
   3357 {
   3358   unsigned op2p1_out_0;
   3359   unsigned op2p1_in_0;
   3360   op2p1_in_0 = *valp & 0xf;
   3361   op2p1_out_0 = op2p1_in_0 + 0x1;
   3362   *valp = op2p1_out_0;
   3363   return 0;
   3364 }
   3365 
   3366 static int
   3367 OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
   3368 {
   3369   unsigned op2p1_in_0;
   3370   unsigned op2p1_out_0;
   3371   op2p1_out_0 = *valp;
   3372   op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
   3373   *valp = op2p1_in_0;
   3374   return 0;
   3375 }
   3376 
   3377 static int
   3378 OperandSem_opnd_sem_label8_decode (uint32 *valp)
   3379 {
   3380   unsigned label8_out_0;
   3381   unsigned label8_in_0;
   3382   label8_in_0 = *valp & 0xff;
   3383   label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
   3384   *valp = label8_out_0;
   3385   return 0;
   3386 }
   3387 
   3388 static int
   3389 OperandSem_opnd_sem_label8_encode (uint32 *valp)
   3390 {
   3391   unsigned label8_in_0;
   3392   unsigned label8_out_0;
   3393   label8_out_0 = *valp;
   3394   label8_in_0 = (label8_out_0 - 0x4) & 0xff;
   3395   *valp = label8_in_0;
   3396   return 0;
   3397 }
   3398 
   3399 static int
   3400 OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
   3401 {
   3402   unsigned ulabel8_out_0;
   3403   unsigned ulabel8_in_0;
   3404   ulabel8_in_0 = *valp & 0xff;
   3405   ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
   3406   *valp = ulabel8_out_0;
   3407   return 0;
   3408 }
   3409 
   3410 static int
   3411 OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
   3412 {
   3413   unsigned ulabel8_in_0;
   3414   unsigned ulabel8_out_0;
   3415   ulabel8_out_0 = *valp;
   3416   ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
   3417   *valp = ulabel8_in_0;
   3418   return 0;
   3419 }
   3420 
   3421 static int
   3422 OperandSem_opnd_sem_label12_decode (uint32 *valp)
   3423 {
   3424   unsigned label12_out_0;
   3425   unsigned label12_in_0;
   3426   label12_in_0 = *valp & 0xfff;
   3427   label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
   3428   *valp = label12_out_0;
   3429   return 0;
   3430 }
   3431 
   3432 static int
   3433 OperandSem_opnd_sem_label12_encode (uint32 *valp)
   3434 {
   3435   unsigned label12_in_0;
   3436   unsigned label12_out_0;
   3437   label12_out_0 = *valp;
   3438   label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
   3439   *valp = label12_in_0;
   3440   return 0;
   3441 }
   3442 
   3443 static int
   3444 OperandSem_opnd_sem_soffset_decode (uint32 *valp)
   3445 {
   3446   unsigned soffset_out_0;
   3447   unsigned soffset_in_0;
   3448   soffset_in_0 = *valp & 0x3ffff;
   3449   soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
   3450   *valp = soffset_out_0;
   3451   return 0;
   3452 }
   3453 
   3454 static int
   3455 OperandSem_opnd_sem_soffset_encode (uint32 *valp)
   3456 {
   3457   unsigned soffset_in_0;
   3458   unsigned soffset_out_0;
   3459   soffset_out_0 = *valp;
   3460   soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
   3461   *valp = soffset_in_0;
   3462   return 0;
   3463 }
   3464 
   3465 static int
   3466 OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
   3467 {
   3468   unsigned uimm16x4_out_0;
   3469   unsigned uimm16x4_in_0;
   3470   uimm16x4_in_0 = *valp & 0xffff;
   3471   uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
   3472   *valp = uimm16x4_out_0;
   3473   return 0;
   3474 }
   3475 
   3476 static int
   3477 OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
   3478 {
   3479   unsigned uimm16x4_in_0;
   3480   unsigned uimm16x4_out_0;
   3481   uimm16x4_out_0 = *valp;
   3482   uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
   3483   *valp = uimm16x4_in_0;
   3484   return 0;
   3485 }
   3486 
   3487 static int
   3488 OperandSem_opnd_sem_MR_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3489 {
   3490   return 0;
   3491 }
   3492 
   3493 static int
   3494 OperandSem_opnd_sem_MR_encode (uint32 *valp)
   3495 {
   3496   int error;
   3497   error = (*valp >= 4);
   3498   return error;
   3499 }
   3500 
   3501 static int
   3502 OperandSem_opnd_sem_MR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3503 {
   3504   return 0;
   3505 }
   3506 
   3507 static int
   3508 OperandSem_opnd_sem_MR_1_encode (uint32 *valp)
   3509 {
   3510   int error;
   3511   error = (*valp >= 4);
   3512   return error;
   3513 }
   3514 
   3515 static int
   3516 OperandSem_opnd_sem_MR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3517 {
   3518   return 0;
   3519 }
   3520 
   3521 static int
   3522 OperandSem_opnd_sem_MR_2_encode (uint32 *valp)
   3523 {
   3524   int error;
   3525   error = (*valp >= 4);
   3526   return error;
   3527 }
   3528 
   3529 static int
   3530 OperandSem_opnd_sem_MR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3531 {
   3532   return 0;
   3533 }
   3534 
   3535 static int
   3536 OperandSem_opnd_sem_MR_3_encode (uint32 *valp)
   3537 {
   3538   int error;
   3539   error = (*valp >= 4);
   3540   return error;
   3541 }
   3542 
   3543 static int
   3544 OperandSem_opnd_sem_MR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3545 {
   3546   return 0;
   3547 }
   3548 
   3549 static int
   3550 OperandSem_opnd_sem_MR_4_encode (uint32 *valp)
   3551 {
   3552   int error;
   3553   error = (*valp >= 4);
   3554   return error;
   3555 }
   3556 
   3557 static int
   3558 OperandSem_opnd_sem_MR_5_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3559 {
   3560   return 0;
   3561 }
   3562 
   3563 static int
   3564 OperandSem_opnd_sem_MR_5_encode (uint32 *valp)
   3565 {
   3566   int error;
   3567   error = (*valp >= 4);
   3568   return error;
   3569 }
   3570 
   3571 static int
   3572 OperandSem_opnd_sem_imms_decode (uint32 *valp)
   3573 {
   3574   unsigned imms_out_0;
   3575   unsigned imms_in_0;
   3576   imms_in_0 = *valp & 0xf;
   3577   imms_out_0 = imms_in_0;
   3578   *valp = imms_out_0;
   3579   return 0;
   3580 }
   3581 
   3582 static int
   3583 OperandSem_opnd_sem_imms_encode (uint32 *valp)
   3584 {
   3585   unsigned imms_in_0;
   3586   unsigned imms_out_0;
   3587   imms_out_0 = *valp;
   3588   imms_in_0 = imms_out_0 & 0xf;
   3589   *valp = imms_in_0;
   3590   return 0;
   3591 }
   3592 
   3593 static int
   3594 OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3595 {
   3596   return 0;
   3597 }
   3598 
   3599 static int
   3600 OperandSem_opnd_sem_BR_encode (uint32 *valp)
   3601 {
   3602   int error;
   3603   error = (*valp >= 16);
   3604   return error;
   3605 }
   3606 
   3607 static int
   3608 OperandSem_opnd_sem_BR2_decode (uint32 *valp)
   3609 {
   3610   *valp = *valp << 1;
   3611   return 0;
   3612 }
   3613 
   3614 static int
   3615 OperandSem_opnd_sem_BR2_encode (uint32 *valp)
   3616 {
   3617   int error;
   3618   error = (*valp >= 16) || ((*valp & 1) != 0);
   3619   *valp = *valp >> 1;
   3620   return error;
   3621 }
   3622 
   3623 static int
   3624 OperandSem_opnd_sem_BR4_decode (uint32 *valp)
   3625 {
   3626   *valp = *valp << 2;
   3627   return 0;
   3628 }
   3629 
   3630 static int
   3631 OperandSem_opnd_sem_BR4_encode (uint32 *valp)
   3632 {
   3633   int error;
   3634   error = (*valp >= 16) || ((*valp & 3) != 0);
   3635   *valp = *valp >> 2;
   3636   return error;
   3637 }
   3638 
   3639 static int
   3640 OperandSem_opnd_sem_BR8_decode (uint32 *valp)
   3641 {
   3642   *valp = *valp << 3;
   3643   return 0;
   3644 }
   3645 
   3646 static int
   3647 OperandSem_opnd_sem_BR8_encode (uint32 *valp)
   3648 {
   3649   int error;
   3650   error = (*valp >= 16) || ((*valp & 7) != 0);
   3651   *valp = *valp >> 3;
   3652   return error;
   3653 }
   3654 
   3655 static int
   3656 OperandSem_opnd_sem_BR16_decode (uint32 *valp)
   3657 {
   3658   *valp = *valp << 4;
   3659   return 0;
   3660 }
   3661 
   3662 static int
   3663 OperandSem_opnd_sem_BR16_encode (uint32 *valp)
   3664 {
   3665   int error;
   3666   error = (*valp >= 16) || ((*valp & 15) != 0);
   3667   *valp = *valp >> 4;
   3668   return error;
   3669 }
   3670 
   3671 static int
   3672 OperandSem_opnd_sem_tp7_decode (uint32 *valp)
   3673 {
   3674   unsigned tp7_out_0;
   3675   unsigned tp7_in_0;
   3676   tp7_in_0 = *valp & 0xf;
   3677   tp7_out_0 = tp7_in_0 + 0x7;
   3678   *valp = tp7_out_0;
   3679   return 0;
   3680 }
   3681 
   3682 static int
   3683 OperandSem_opnd_sem_tp7_encode (uint32 *valp)
   3684 {
   3685   unsigned tp7_in_0;
   3686   unsigned tp7_out_0;
   3687   tp7_out_0 = *valp;
   3688   tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
   3689   *valp = tp7_in_0;
   3690   return 0;
   3691 }
   3692 
   3693 static int
   3694 OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
   3695 {
   3696   unsigned xt_wbr15_label_out_0;
   3697   unsigned xt_wbr15_label_in_0;
   3698   xt_wbr15_label_in_0 = *valp & 0x7fff;
   3699   xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
   3700   *valp = xt_wbr15_label_out_0;
   3701   return 0;
   3702 }
   3703 
   3704 static int
   3705 OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
   3706 {
   3707   unsigned xt_wbr15_label_in_0;
   3708   unsigned xt_wbr15_label_out_0;
   3709   xt_wbr15_label_out_0 = *valp;
   3710   xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
   3711   *valp = xt_wbr15_label_in_0;
   3712   return 0;
   3713 }
   3714 
   3715 static int
   3716 OperandSem_opnd_sem_xt_wbr18_label_decode (uint32 *valp)
   3717 {
   3718   unsigned xt_wbr18_label_out_0;
   3719   unsigned xt_wbr18_label_in_0;
   3720   xt_wbr18_label_in_0 = *valp & 0x3ffff;
   3721   xt_wbr18_label_out_0 = 0x4 + (((int) xt_wbr18_label_in_0 << 14) >> 14);
   3722   *valp = xt_wbr18_label_out_0;
   3723   return 0;
   3724 }
   3725 
   3726 static int
   3727 OperandSem_opnd_sem_xt_wbr18_label_encode (uint32 *valp)
   3728 {
   3729   unsigned xt_wbr18_label_in_0;
   3730   unsigned xt_wbr18_label_out_0;
   3731   xt_wbr18_label_out_0 = *valp;
   3732   xt_wbr18_label_in_0 = (xt_wbr18_label_out_0 - 0x4) & 0x3ffff;
   3733   *valp = xt_wbr18_label_in_0;
   3734   return 0;
   3735 }
   3736 
   3737 static int
   3738 OperandSem_opnd_sem_FR_decode (uint32 *valp ATTRIBUTE_UNUSED)
   3739 {
   3740   return 0;
   3741 }
   3742 
   3743 static int
   3744 OperandSem_opnd_sem_FR_encode (uint32 *valp)
   3745 {
   3746   int error;
   3747   error = (*valp >= 16);
   3748   return error;
   3749 }
   3750 
   3751 static int
   3752 OperandSem_opnd_sem_imm_t_decode (uint32 *valp)
   3753 {
   3754   unsigned imm_t_out_0;
   3755   unsigned imm_t_in_0;
   3756   imm_t_in_0 = *valp & 0xf;
   3757   imm_t_out_0 = (0 << 4) | imm_t_in_0;
   3758   *valp = imm_t_out_0;
   3759   return 0;
   3760 }
   3761 
   3762 static int
   3763 OperandSem_opnd_sem_imm_t_encode (uint32 *valp)
   3764 {
   3765   unsigned imm_t_in_0;
   3766   unsigned imm_t_out_0;
   3767   imm_t_out_0 = *valp;
   3768   imm_t_in_0 = (imm_t_out_0 & 0xf);
   3769   *valp = imm_t_in_0;
   3770   return 0;
   3771 }
   3772 
   3773 static int
   3774 OperandSem_opnd_sem_imm8x4_decode (uint32 *valp)
   3775 {
   3776   unsigned imm8x4_out_0;
   3777   unsigned imm8x4_in_0;
   3778   imm8x4_in_0 = *valp & 0xff;
   3779   imm8x4_out_0 = (0 << 10) | (imm8x4_in_0 << 2) | 0;
   3780   *valp = imm8x4_out_0;
   3781   return 0;
   3782 }
   3783 
   3784 static int
   3785 OperandSem_opnd_sem_imm8x4_encode (uint32 *valp)
   3786 {
   3787   unsigned imm8x4_in_0;
   3788   unsigned imm8x4_out_0;
   3789   imm8x4_out_0 = *valp;
   3790   imm8x4_in_0 = ((imm8x4_out_0 >> 2) & 0xff);
   3791   *valp = imm8x4_in_0;
   3792   return 0;
   3793 }
   3794 
   3795 static int
   3796 OperandSem_opnd_sem_imm8x8_decode (uint32 *valp)
   3797 {
   3798   unsigned imm8x8_out_0;
   3799   unsigned imm8x8_in_0;
   3800   imm8x8_in_0 = *valp & 0xff;
   3801   imm8x8_out_0 = (0 << 11) | (imm8x8_in_0 << 3) | 0;
   3802   *valp = imm8x8_out_0;
   3803   return 0;
   3804 }
   3805 
   3806 static int
   3807 OperandSem_opnd_sem_imm8x8_encode (uint32 *valp)
   3808 {
   3809   unsigned imm8x8_in_0;
   3810   unsigned imm8x8_out_0;
   3811   imm8x8_out_0 = *valp;
   3812   imm8x8_in_0 = ((imm8x8_out_0 >> 3) & 0xff);
   3813   *valp = imm8x8_in_0;
   3814   return 0;
   3815 }
   3816 
   3817 static int
   3818 OperandSem_opnd_sem_bbi_decode (uint32 *valp)
   3819 {
   3820   unsigned bbi_out_0;
   3821   unsigned bbi_in_0;
   3822   bbi_in_0 = *valp & 0x1f;
   3823   bbi_out_0 = (0 << 5) | bbi_in_0;
   3824   *valp = bbi_out_0;
   3825   return 0;
   3826 }
   3827 
   3828 static int
   3829 OperandSem_opnd_sem_bbi_encode (uint32 *valp)
   3830 {
   3831   unsigned bbi_in_0;
   3832   unsigned bbi_out_0;
   3833   bbi_out_0 = *valp;
   3834   bbi_in_0 = (bbi_out_0 & 0x1f);
   3835   *valp = bbi_in_0;
   3836   return 0;
   3837 }
   3838 
   3839 static int
   3840 OperandSem_opnd_sem_s_decode (uint32 *valp)
   3841 {
   3842   unsigned s_out_0;
   3843   unsigned s_in_0;
   3844   s_in_0 = *valp & 0xf;
   3845   s_out_0 = (0 << 4) | s_in_0;
   3846   *valp = s_out_0;
   3847   return 0;
   3848 }
   3849 
   3850 static int
   3851 OperandSem_opnd_sem_s_encode (uint32 *valp)
   3852 {
   3853   unsigned s_in_0;
   3854   unsigned s_out_0;
   3855   s_out_0 = *valp;
   3856   s_in_0 = (s_out_0 & 0xf);
   3857   *valp = s_in_0;
   3858   return 0;
   3859 }
   3860 
   3861 static int
   3862 OperandSem_opnd_sem_bitindex_decode (uint32 *valp)
   3863 {
   3864   unsigned bitindex_out_0;
   3865   unsigned bitindex_in_0;
   3866   bitindex_in_0 = *valp & 0x1f;
   3867   bitindex_out_0 = (0 << 5) | bitindex_in_0;
   3868   *valp = bitindex_out_0;
   3869   return 0;
   3870 }
   3871 
   3872 static int
   3873 OperandSem_opnd_sem_bitindex_encode (uint32 *valp)
   3874 {
   3875   unsigned bitindex_in_0;
   3876   unsigned bitindex_out_0;
   3877   bitindex_out_0 = *valp;
   3878   bitindex_in_0 = (bitindex_out_0 & 0x1f);
   3879   *valp = bitindex_in_0;
   3880   return 0;
   3881 }
   3882 
   3883 static int
   3884 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
   3885 {
   3886   *valp -= (pc & ~0x3);
   3887   return 0;
   3888 }
   3889 
   3890 static int
   3891 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
   3892 {
   3893   *valp += (pc & ~0x3);
   3894   return 0;
   3895 }
   3896 
   3897 static int
   3898 Operand_uimm6_ator (uint32 *valp, uint32 pc)
   3899 {
   3900   *valp -= pc;
   3901   return 0;
   3902 }
   3903 
   3904 static int
   3905 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
   3906 {
   3907   *valp += pc;
   3908   return 0;
   3909 }
   3910 
   3911 static int
   3912 Operand_label8_ator (uint32 *valp, uint32 pc)
   3913 {
   3914   *valp -= pc;
   3915   return 0;
   3916 }
   3917 
   3918 static int
   3919 Operand_label8_rtoa (uint32 *valp, uint32 pc)
   3920 {
   3921   *valp += pc;
   3922   return 0;
   3923 }
   3924 
   3925 static int
   3926 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
   3927 {
   3928   *valp -= pc;
   3929   return 0;
   3930 }
   3931 
   3932 static int
   3933 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
   3934 {
   3935   *valp += pc;
   3936   return 0;
   3937 }
   3938 
   3939 static int
   3940 Operand_label12_ator (uint32 *valp, uint32 pc)
   3941 {
   3942   *valp -= pc;
   3943   return 0;
   3944 }
   3945 
   3946 static int
   3947 Operand_label12_rtoa (uint32 *valp, uint32 pc)
   3948 {
   3949   *valp += pc;
   3950   return 0;
   3951 }
   3952 
   3953 static int
   3954 Operand_soffset_ator (uint32 *valp, uint32 pc)
   3955 {
   3956   *valp -= pc;
   3957   return 0;
   3958 }
   3959 
   3960 static int
   3961 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
   3962 {
   3963   *valp += pc;
   3964   return 0;
   3965 }
   3966 
   3967 static int
   3968 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
   3969 {
   3970   *valp -= ((pc + 3) & ~0x3);
   3971   return 0;
   3972 }
   3973 
   3974 static int
   3975 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
   3976 {
   3977   *valp += ((pc + 3) & ~0x3);
   3978   return 0;
   3979 }
   3980 
   3981 static int
   3982 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
   3983 {
   3984   *valp -= pc;
   3985   return 0;
   3986 }
   3987 
   3988 static int
   3989 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
   3990 {
   3991   *valp += pc;
   3992   return 0;
   3993 }
   3994 
   3995 static int
   3996 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
   3997 {
   3998   *valp -= pc;
   3999   return 0;
   4000 }
   4001 
   4002 static int
   4003 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
   4004 {
   4005   *valp += pc;
   4006   return 0;
   4007 }
   4008 
   4009 static xtensa_operand_internal operands[] = {
   4010   { "soffsetx4", FIELD_offset, -1, 0,
   4011     XTENSA_OPERAND_IS_PCRELATIVE,
   4012     OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
   4013     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
   4014   { "immr", FIELD_r, -1, 0,
   4015     0,
   4016     OperandSem_opnd_sem_immr_encode, OperandSem_opnd_sem_immr_decode,
   4017     0, 0 },
   4018   { "uimm12x8", FIELD_imm12, -1, 0,
   4019     0,
   4020     OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
   4021     0, 0 },
   4022   { "simm4", FIELD_mn, -1, 0,
   4023     0,
   4024     OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
   4025     0, 0 },
   4026   { "arr", FIELD_r, REGFILE_AR, 1,
   4027     XTENSA_OPERAND_IS_REGISTER,
   4028     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   4029     0, 0 },
   4030   { "ars", FIELD_s, REGFILE_AR, 1,
   4031     XTENSA_OPERAND_IS_REGISTER,
   4032     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   4033     0, 0 },
   4034   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
   4035     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4036     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   4037     0, 0 },
   4038   { "art", FIELD_t, REGFILE_AR, 1,
   4039     XTENSA_OPERAND_IS_REGISTER,
   4040     OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
   4041     0, 0 },
   4042   { "ar0", FIELD__ar0, REGFILE_AR, 1,
   4043     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4044     OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
   4045     0, 0 },
   4046   { "ar4", FIELD__ar4, REGFILE_AR, 1,
   4047     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4048     OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
   4049     0, 0 },
   4050   { "ar8", FIELD__ar8, REGFILE_AR, 1,
   4051     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4052     OperandSem_opnd_sem_AR_8_encode, OperandSem_opnd_sem_AR_8_decode,
   4053     0, 0 },
   4054   { "ar12", FIELD__ar12, REGFILE_AR, 1,
   4055     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4056     OperandSem_opnd_sem_AR_12_encode, OperandSem_opnd_sem_AR_12_decode,
   4057     0, 0 },
   4058   { "ars_entry", FIELD_s, REGFILE_AR, 1,
   4059     XTENSA_OPERAND_IS_REGISTER,
   4060     OperandSem_opnd_sem_AR_entry_encode, OperandSem_opnd_sem_AR_entry_decode,
   4061     0, 0 },
   4062   { "immrx4", FIELD_r, -1, 0,
   4063     0,
   4064     OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
   4065     0, 0 },
   4066   { "lsi4x4", FIELD_r, -1, 0,
   4067     0,
   4068     OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
   4069     0, 0 },
   4070   { "simm7", FIELD_imm7, -1, 0,
   4071     0,
   4072     OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
   4073     0, 0 },
   4074   { "uimm6", FIELD_imm6, -1, 0,
   4075     XTENSA_OPERAND_IS_PCRELATIVE,
   4076     OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
   4077     Operand_uimm6_ator, Operand_uimm6_rtoa },
   4078   { "ai4const", FIELD_t, -1, 0,
   4079     0,
   4080     OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
   4081     0, 0 },
   4082   { "b4const", FIELD_r, -1, 0,
   4083     0,
   4084     OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
   4085     0, 0 },
   4086   { "b4constu", FIELD_r, -1, 0,
   4087     0,
   4088     OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
   4089     0, 0 },
   4090   { "immt", FIELD_t, -1, 0,
   4091     0,
   4092     OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
   4093     0, 0 },
   4094   { "uimms8", FIELD_imms8, -1, 0,
   4095     0,
   4096     OperandSem_opnd_sem_uimms8_encode, OperandSem_opnd_sem_uimms8_decode,
   4097     0, 0 },
   4098   { "uimm8", FIELD_imm8, -1, 0,
   4099     0,
   4100     OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
   4101     0, 0 },
   4102   { "uimm8x2", FIELD_imm8, -1, 0,
   4103     0,
   4104     OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
   4105     0, 0 },
   4106   { "uimm8x4", FIELD_imm8, -1, 0,
   4107     0,
   4108     OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
   4109     0, 0 },
   4110   { "uimm4x16", FIELD_op2, -1, 0,
   4111     0,
   4112     OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
   4113     0, 0 },
   4114   { "uimmrx4", FIELD_r, -1, 0,
   4115     0,
   4116     OperandSem_opnd_sem_uimmrx4_encode, OperandSem_opnd_sem_uimmrx4_decode,
   4117     0, 0 },
   4118   { "simm8", FIELD_imm8, -1, 0,
   4119     0,
   4120     OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
   4121     0, 0 },
   4122   { "simm8x256", FIELD_imm8, -1, 0,
   4123     0,
   4124     OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
   4125     0, 0 },
   4126   { "simm12b", FIELD_imm12b, -1, 0,
   4127     0,
   4128     OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
   4129     0, 0 },
   4130   { "msalp32", FIELD_sal, -1, 0,
   4131     0,
   4132     OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
   4133     0, 0 },
   4134   { "op2p1", FIELD_op2, -1, 0,
   4135     0,
   4136     OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
   4137     0, 0 },
   4138   { "label8", FIELD_imm8, -1, 0,
   4139     XTENSA_OPERAND_IS_PCRELATIVE,
   4140     OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
   4141     Operand_label8_ator, Operand_label8_rtoa },
   4142   { "ulabel8", FIELD_imm8, -1, 0,
   4143     XTENSA_OPERAND_IS_PCRELATIVE,
   4144     OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
   4145     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
   4146   { "label12", FIELD_imm12, -1, 0,
   4147     XTENSA_OPERAND_IS_PCRELATIVE,
   4148     OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
   4149     Operand_label12_ator, Operand_label12_rtoa },
   4150   { "soffset", FIELD_offset, -1, 0,
   4151     XTENSA_OPERAND_IS_PCRELATIVE,
   4152     OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
   4153     Operand_soffset_ator, Operand_soffset_rtoa },
   4154   { "uimm16x4", FIELD_imm16, -1, 0,
   4155     XTENSA_OPERAND_IS_PCRELATIVE,
   4156     OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
   4157     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
   4158   { "mx", FIELD_x, REGFILE_MR, 1,
   4159     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
   4160     OperandSem_opnd_sem_MR_encode, OperandSem_opnd_sem_MR_decode,
   4161     0, 0 },
   4162   { "my", FIELD_y, REGFILE_MR, 1,
   4163     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
   4164     OperandSem_opnd_sem_MR_0_encode, OperandSem_opnd_sem_MR_0_decode,
   4165     0, 0 },
   4166   { "mw", FIELD_w, REGFILE_MR, 1,
   4167     XTENSA_OPERAND_IS_REGISTER,
   4168     OperandSem_opnd_sem_MR_1_encode, OperandSem_opnd_sem_MR_1_decode,
   4169     0, 0 },
   4170   { "mr0", FIELD__mr0, REGFILE_MR, 1,
   4171     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4172     OperandSem_opnd_sem_MR_2_encode, OperandSem_opnd_sem_MR_2_decode,
   4173     0, 0 },
   4174   { "mr1", FIELD__mr1, REGFILE_MR, 1,
   4175     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4176     OperandSem_opnd_sem_MR_3_encode, OperandSem_opnd_sem_MR_3_decode,
   4177     0, 0 },
   4178   { "mr2", FIELD__mr2, REGFILE_MR, 1,
   4179     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4180     OperandSem_opnd_sem_MR_4_encode, OperandSem_opnd_sem_MR_4_decode,
   4181     0, 0 },
   4182   { "mr3", FIELD__mr3, REGFILE_MR, 1,
   4183     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4184     OperandSem_opnd_sem_MR_5_encode, OperandSem_opnd_sem_MR_5_decode,
   4185     0, 0 },
   4186   { "imms", FIELD_s, -1, 0,
   4187     0,
   4188     OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode,
   4189     0, 0 },
   4190   { "imms1", FIELD_s, -1, 0,
   4191     0,
   4192     OperandSem_opnd_sem_imms_encode, OperandSem_opnd_sem_imms_decode,
   4193     0, 0 },
   4194   { "bt", FIELD_t, REGFILE_BR, 1,
   4195     XTENSA_OPERAND_IS_REGISTER,
   4196     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
   4197     0, 0 },
   4198   { "bs", FIELD_s, REGFILE_BR, 1,
   4199     XTENSA_OPERAND_IS_REGISTER,
   4200     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
   4201     0, 0 },
   4202   { "br", FIELD_r, REGFILE_BR, 1,
   4203     XTENSA_OPERAND_IS_REGISTER,
   4204     OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
   4205     0, 0 },
   4206   { "bt2", FIELD_t2, REGFILE_BR, 2,
   4207     XTENSA_OPERAND_IS_REGISTER,
   4208     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
   4209     0, 0 },
   4210   { "bs2", FIELD_s2, REGFILE_BR, 2,
   4211     XTENSA_OPERAND_IS_REGISTER,
   4212     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
   4213     0, 0 },
   4214   { "br2", FIELD_r2, REGFILE_BR, 2,
   4215     XTENSA_OPERAND_IS_REGISTER,
   4216     OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
   4217     0, 0 },
   4218   { "bt4", FIELD_t4, REGFILE_BR, 4,
   4219     XTENSA_OPERAND_IS_REGISTER,
   4220     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
   4221     0, 0 },
   4222   { "bs4", FIELD_s4, REGFILE_BR, 4,
   4223     XTENSA_OPERAND_IS_REGISTER,
   4224     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
   4225     0, 0 },
   4226   { "br4", FIELD_r4, REGFILE_BR, 4,
   4227     XTENSA_OPERAND_IS_REGISTER,
   4228     OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
   4229     0, 0 },
   4230   { "bt8", FIELD_t8, REGFILE_BR, 8,
   4231     XTENSA_OPERAND_IS_REGISTER,
   4232     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
   4233     0, 0 },
   4234   { "bs8", FIELD_s8, REGFILE_BR, 8,
   4235     XTENSA_OPERAND_IS_REGISTER,
   4236     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
   4237     0, 0 },
   4238   { "br8", FIELD_r8, REGFILE_BR, 8,
   4239     XTENSA_OPERAND_IS_REGISTER,
   4240     OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
   4241     0, 0 },
   4242   { "bt16", FIELD__bt16, REGFILE_BR, 16,
   4243     XTENSA_OPERAND_IS_REGISTER,
   4244     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
   4245     0, 0 },
   4246   { "bs16", FIELD__bs16, REGFILE_BR, 16,
   4247     XTENSA_OPERAND_IS_REGISTER,
   4248     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
   4249     0, 0 },
   4250   { "br16", FIELD__br16, REGFILE_BR, 16,
   4251     XTENSA_OPERAND_IS_REGISTER,
   4252     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
   4253     0, 0 },
   4254   { "brall", FIELD__brall, REGFILE_BR, 16,
   4255     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   4256     OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
   4257     0, 0 },
   4258   { "tp7", FIELD_t, -1, 0,
   4259     0,
   4260     OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
   4261     0, 0 },
   4262   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
   4263     XTENSA_OPERAND_IS_PCRELATIVE,
   4264     OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
   4265     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
   4266   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
   4267     XTENSA_OPERAND_IS_PCRELATIVE,
   4268     OperandSem_opnd_sem_xt_wbr18_label_encode, OperandSem_opnd_sem_xt_wbr18_label_decode,
   4269     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
   4270   { "frr", FIELD_r, REGFILE_FR, 1,
   4271     XTENSA_OPERAND_IS_REGISTER,
   4272     OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
   4273     0, 0 },
   4274   { "frs", FIELD_s, REGFILE_FR, 1,
   4275     XTENSA_OPERAND_IS_REGISTER,
   4276     OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
   4277     0, 0 },
   4278   { "frt", FIELD_t, REGFILE_FR, 1,
   4279     XTENSA_OPERAND_IS_REGISTER,
   4280     OperandSem_opnd_sem_FR_encode, OperandSem_opnd_sem_FR_decode,
   4281     0, 0 },
   4282   { "imm_t", FIELD_t, -1, 0,
   4283     0,
   4284     OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
   4285     0, 0 },
   4286   { "imm_s", FIELD_s, -1, 0,
   4287     0,
   4288     OperandSem_opnd_sem_imm_t_encode, OperandSem_opnd_sem_imm_t_decode,
   4289     0, 0 },
   4290   { "imm8x4", FIELD_imm8, -1, 0,
   4291     0,
   4292     OperandSem_opnd_sem_imm8x4_encode, OperandSem_opnd_sem_imm8x4_decode,
   4293     0, 0 },
   4294   { "imm8x8", FIELD_imm8, -1, 0,
   4295     0,
   4296     OperandSem_opnd_sem_imm8x8_encode, OperandSem_opnd_sem_imm8x8_decode,
   4297     0, 0 },
   4298   { "bbi", FIELD_bbi, -1, 0,
   4299     0,
   4300     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   4301     0, 0 },
   4302   { "sae", FIELD_sae, -1, 0,
   4303     0,
   4304     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   4305     0, 0 },
   4306   { "sas", FIELD_sas, -1, 0,
   4307     0,
   4308     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   4309     0, 0 },
   4310   { "sargt", FIELD_sargt, -1, 0,
   4311     0,
   4312     OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
   4313     0, 0 },
   4314   { "s", FIELD_s, -1, 0,
   4315     0,
   4316     OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
   4317     0, 0 },
   4318   { "bitindex", FIELD_bitindex, -1, 0,
   4319     0,
   4320     OperandSem_opnd_sem_bitindex_encode, OperandSem_opnd_sem_bitindex_decode,
   4321     0, 0 },
   4322   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
   4323   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
   4324   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
   4325   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
   4326   { "s8", FIELD_s8, -1, 0, 0, 0, 0, 0, 0 },
   4327   { "imms8", FIELD_imms8, -1, 0, 0, 0, 0, 0, 0 },
   4328   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
   4329   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
   4330   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
   4331   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
   4332   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
   4333   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
   4334   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
   4335   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
   4336   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
   4337   { "r_disp", FIELD_r_disp, -1, 0, 0, 0, 0, 0, 0 },
   4338   { "r_3", FIELD_r_3, -1, 0, 0, 0, 0, 0, 0 },
   4339   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
   4340   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
   4341   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
   4342   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
   4343   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
   4344   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
   4345   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
   4346   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
   4347   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
   4348   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
   4349   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
   4350   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
   4351   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
   4352   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
   4353   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
   4354   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
   4355   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
   4356   { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
   4357   { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
   4358   { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
   4359   { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
   4360   { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
   4361   { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
   4362   { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
   4363   { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
   4364   { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
   4365   { "t2", FIELD_t2, -1, 0, 0, 0, 0, 0, 0 },
   4366   { "s2", FIELD_s2, -1, 0, 0, 0, 0, 0, 0 },
   4367   { "r2", FIELD_r2, -1, 0, 0, 0, 0, 0, 0 },
   4368   { "t4", FIELD_t4, -1, 0, 0, 0, 0, 0, 0 },
   4369   { "s4", FIELD_s4, -1, 0, 0, 0, 0, 0, 0 },
   4370   { "r4", FIELD_r4, -1, 0, 0, 0, 0, 0, 0 },
   4371   { "t8", FIELD_t8, -1, 0, 0, 0, 0, 0, 0 },
   4372   { "r8", FIELD_r8, -1, 0, 0, 0, 0, 0, 0 },
   4373   { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
   4374   { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
   4375   { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
   4376 };
   4377 
   4378 enum xtensa_operand_id {
   4379   OPERAND_soffsetx4,
   4380   OPERAND_immr,
   4381   OPERAND_uimm12x8,
   4382   OPERAND_simm4,
   4383   OPERAND_arr,
   4384   OPERAND_ars,
   4385   OPERAND__ars_invisible,
   4386   OPERAND_art,
   4387   OPERAND_ar0,
   4388   OPERAND_ar4,
   4389   OPERAND_ar8,
   4390   OPERAND_ar12,
   4391   OPERAND_ars_entry,
   4392   OPERAND_immrx4,
   4393   OPERAND_lsi4x4,
   4394   OPERAND_simm7,
   4395   OPERAND_uimm6,
   4396   OPERAND_ai4const,
   4397   OPERAND_b4const,
   4398   OPERAND_b4constu,
   4399   OPERAND_immt,
   4400   OPERAND_uimms8,
   4401   OPERAND_uimm8,
   4402   OPERAND_uimm8x2,
   4403   OPERAND_uimm8x4,
   4404   OPERAND_uimm4x16,
   4405   OPERAND_uimmrx4,
   4406   OPERAND_simm8,
   4407   OPERAND_simm8x256,
   4408   OPERAND_simm12b,
   4409   OPERAND_msalp32,
   4410   OPERAND_op2p1,
   4411   OPERAND_label8,
   4412   OPERAND_ulabel8,
   4413   OPERAND_label12,
   4414   OPERAND_soffset,
   4415   OPERAND_uimm16x4,
   4416   OPERAND_mx,
   4417   OPERAND_my,
   4418   OPERAND_mw,
   4419   OPERAND_mr0,
   4420   OPERAND_mr1,
   4421   OPERAND_mr2,
   4422   OPERAND_mr3,
   4423   OPERAND_imms,
   4424   OPERAND_imms1,
   4425   OPERAND_bt,
   4426   OPERAND_bs,
   4427   OPERAND_br,
   4428   OPERAND_bt2,
   4429   OPERAND_bs2,
   4430   OPERAND_br2,
   4431   OPERAND_bt4,
   4432   OPERAND_bs4,
   4433   OPERAND_br4,
   4434   OPERAND_bt8,
   4435   OPERAND_bs8,
   4436   OPERAND_br8,
   4437   OPERAND_bt16,
   4438   OPERAND_bs16,
   4439   OPERAND_br16,
   4440   OPERAND_brall,
   4441   OPERAND_tp7,
   4442   OPERAND_xt_wbr15_label,
   4443   OPERAND_xt_wbr18_label,
   4444   OPERAND_frr,
   4445   OPERAND_frs,
   4446   OPERAND_frt,
   4447   OPERAND_imm_t,
   4448   OPERAND_imm_s,
   4449   OPERAND_imm8x4,
   4450   OPERAND_imm8x8,
   4451   OPERAND_bbi,
   4452   OPERAND_sae,
   4453   OPERAND_sas,
   4454   OPERAND_sargt,
   4455   OPERAND_s,
   4456   OPERAND_bitindex,
   4457   OPERAND_t,
   4458   OPERAND_bbi4,
   4459   OPERAND_imm12,
   4460   OPERAND_imm8,
   4461   OPERAND_s8,
   4462   OPERAND_imms8,
   4463   OPERAND_imm12b,
   4464   OPERAND_imm16,
   4465   OPERAND_m,
   4466   OPERAND_n,
   4467   OPERAND_offset,
   4468   OPERAND_op0,
   4469   OPERAND_op1,
   4470   OPERAND_op2,
   4471   OPERAND_r,
   4472   OPERAND_r_disp,
   4473   OPERAND_r_3,
   4474   OPERAND_sa4,
   4475   OPERAND_sae4,
   4476   OPERAND_sal,
   4477   OPERAND_sas4,
   4478   OPERAND_sr,
   4479   OPERAND_st,
   4480   OPERAND_thi3,
   4481   OPERAND_imm4,
   4482   OPERAND_mn,
   4483   OPERAND_i,
   4484   OPERAND_imm6lo,
   4485   OPERAND_imm6hi,
   4486   OPERAND_imm7lo,
   4487   OPERAND_imm7hi,
   4488   OPERAND_z,
   4489   OPERAND_imm6,
   4490   OPERAND_imm7,
   4491   OPERAND_r3,
   4492   OPERAND_rbit2,
   4493   OPERAND_rhi,
   4494   OPERAND_t3,
   4495   OPERAND_tbit2,
   4496   OPERAND_tlo,
   4497   OPERAND_w,
   4498   OPERAND_y,
   4499   OPERAND_x,
   4500   OPERAND_t2,
   4501   OPERAND_s2,
   4502   OPERAND_r2,
   4503   OPERAND_t4,
   4504   OPERAND_s4,
   4505   OPERAND_r4,
   4506   OPERAND_t8,
   4507   OPERAND_r8,
   4508   OPERAND_xt_wbr15_imm,
   4509   OPERAND_xt_wbr18_imm,
   4510   OPERAND_s3to1
   4511 };
   4512 
   4513 
   4514 /* Iclass table.  */
   4515 
   4516 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
   4517   { { STATE_PSRING }, 'i' },
   4518   { { STATE_PSEXCM }, 'm' },
   4519   { { STATE_EPC1 }, 'i' }
   4520 };
   4521 
   4522 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
   4523   { { STATE_PSEXCM }, 'i' },
   4524   { { STATE_PSRING }, 'i' },
   4525   { { STATE_DEPC }, 'i' }
   4526 };
   4527 
   4528 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
   4529   { { OPERAND_soffsetx4 }, 'i' },
   4530   { { OPERAND_ar12 }, 'o' }
   4531 };
   4532 
   4533 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
   4534   { { STATE_PSCALLINC }, 'o' }
   4535 };
   4536 
   4537 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
   4538   { { OPERAND_soffsetx4 }, 'i' },
   4539   { { OPERAND_ar8 }, 'o' }
   4540 };
   4541 
   4542 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
   4543   { { STATE_PSCALLINC }, 'o' }
   4544 };
   4545 
   4546 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
   4547   { { OPERAND_soffsetx4 }, 'i' },
   4548   { { OPERAND_ar4 }, 'o' }
   4549 };
   4550 
   4551 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
   4552   { { STATE_PSCALLINC }, 'o' }
   4553 };
   4554 
   4555 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
   4556   { { OPERAND_ars }, 'i' },
   4557   { { OPERAND_ar12 }, 'o' }
   4558 };
   4559 
   4560 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
   4561   { { STATE_PSCALLINC }, 'o' }
   4562 };
   4563 
   4564 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
   4565   { { OPERAND_ars }, 'i' },
   4566   { { OPERAND_ar8 }, 'o' }
   4567 };
   4568 
   4569 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
   4570   { { STATE_PSCALLINC }, 'o' }
   4571 };
   4572 
   4573 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
   4574   { { OPERAND_ars }, 'i' },
   4575   { { OPERAND_ar4 }, 'o' }
   4576 };
   4577 
   4578 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
   4579   { { STATE_PSCALLINC }, 'o' }
   4580 };
   4581 
   4582 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
   4583   { { OPERAND_ars_entry }, 's' },
   4584   { { OPERAND_ars }, 'i' },
   4585   { { OPERAND_uimm12x8 }, 'i' }
   4586 };
   4587 
   4588 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
   4589   { { STATE_PSCALLINC }, 'i' },
   4590   { { STATE_PSEXCM }, 'i' },
   4591   { { STATE_PSWOE }, 'i' },
   4592   { { STATE_WindowBase }, 'm' },
   4593   { { STATE_WindowStart }, 'm' }
   4594 };
   4595 
   4596 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
   4597   { { OPERAND_art }, 'o' },
   4598   { { OPERAND_ars }, 'i' }
   4599 };
   4600 
   4601 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
   4602   { { STATE_WindowBase }, 'i' },
   4603   { { STATE_WindowStart }, 'i' }
   4604 };
   4605 
   4606 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
   4607   { { OPERAND_simm4 }, 'i' }
   4608 };
   4609 
   4610 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
   4611   { { STATE_PSEXCM }, 'i' },
   4612   { { STATE_PSRING }, 'i' },
   4613   { { STATE_WindowBase }, 'm' }
   4614 };
   4615 
   4616 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
   4617   { { OPERAND__ars_invisible }, 'i' }
   4618 };
   4619 
   4620 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
   4621   { { STATE_WindowBase }, 'm' },
   4622   { { STATE_WindowStart }, 'm' },
   4623   { { STATE_PSCALLINC }, 'o' },
   4624   { { STATE_PSEXCM }, 'i' },
   4625   { { STATE_PSWOE }, 'i' }
   4626 };
   4627 
   4628 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
   4629   { { STATE_EPC1 }, 'i' },
   4630   { { STATE_PSEXCM }, 'm' },
   4631   { { STATE_PSRING }, 'i' },
   4632   { { STATE_WindowBase }, 'm' },
   4633   { { STATE_WindowStart }, 'm' },
   4634   { { STATE_PSOWB }, 'i' }
   4635 };
   4636 
   4637 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
   4638   { { OPERAND_art }, 'o' },
   4639   { { OPERAND_ars }, 'i' },
   4640   { { OPERAND_immrx4 }, 'i' }
   4641 };
   4642 
   4643 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
   4644   { { STATE_PSEXCM }, 'i' },
   4645   { { STATE_PSRING }, 'i' }
   4646 };
   4647 
   4648 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
   4649   { { OPERAND_art }, 'i' },
   4650   { { OPERAND_ars }, 'i' },
   4651   { { OPERAND_immrx4 }, 'i' }
   4652 };
   4653 
   4654 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
   4655   { { STATE_PSEXCM }, 'i' },
   4656   { { STATE_PSRING }, 'i' }
   4657 };
   4658 
   4659 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
   4660   { { OPERAND_art }, 'o' }
   4661 };
   4662 
   4663 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
   4664   { { STATE_PSEXCM }, 'i' },
   4665   { { STATE_PSRING }, 'i' },
   4666   { { STATE_WindowBase }, 'i' }
   4667 };
   4668 
   4669 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
   4670   { { OPERAND_art }, 'i' }
   4671 };
   4672 
   4673 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
   4674   { { STATE_PSEXCM }, 'i' },
   4675   { { STATE_PSRING }, 'i' },
   4676   { { STATE_WindowBase }, 'o' }
   4677 };
   4678 
   4679 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
   4680   { { OPERAND_art }, 'm' }
   4681 };
   4682 
   4683 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
   4684   { { STATE_PSEXCM }, 'i' },
   4685   { { STATE_PSRING }, 'i' },
   4686   { { STATE_WindowBase }, 'm' }
   4687 };
   4688 
   4689 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
   4690   { { OPERAND_art }, 'o' }
   4691 };
   4692 
   4693 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
   4694   { { STATE_PSEXCM }, 'i' },
   4695   { { STATE_PSRING }, 'i' },
   4696   { { STATE_WindowStart }, 'i' }
   4697 };
   4698 
   4699 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
   4700   { { OPERAND_art }, 'i' }
   4701 };
   4702 
   4703 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
   4704   { { STATE_PSEXCM }, 'i' },
   4705   { { STATE_PSRING }, 'i' },
   4706   { { STATE_WindowStart }, 'o' }
   4707 };
   4708 
   4709 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
   4710   { { OPERAND_art }, 'm' }
   4711 };
   4712 
   4713 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
   4714   { { STATE_PSEXCM }, 'i' },
   4715   { { STATE_PSRING }, 'i' },
   4716   { { STATE_WindowStart }, 'm' }
   4717 };
   4718 
   4719 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
   4720   { { OPERAND_arr }, 'o' },
   4721   { { OPERAND_ars }, 'i' },
   4722   { { OPERAND_art }, 'i' }
   4723 };
   4724 
   4725 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
   4726   { { OPERAND_arr }, 'o' },
   4727   { { OPERAND_ars }, 'i' },
   4728   { { OPERAND_ai4const }, 'i' }
   4729 };
   4730 
   4731 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
   4732   { { OPERAND_ars }, 'i' },
   4733   { { OPERAND_uimm6 }, 'i' }
   4734 };
   4735 
   4736 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
   4737   { { OPERAND_art }, 'o' },
   4738   { { OPERAND_ars }, 'i' },
   4739   { { OPERAND_lsi4x4 }, 'i' }
   4740 };
   4741 
   4742 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
   4743   { { OPERAND_art }, 'o' },
   4744   { { OPERAND_ars }, 'i' }
   4745 };
   4746 
   4747 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
   4748   { { OPERAND_ars }, 'o' },
   4749   { { OPERAND_simm7 }, 'i' }
   4750 };
   4751 
   4752 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
   4753   { { OPERAND__ars_invisible }, 'i' }
   4754 };
   4755 
   4756 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
   4757   { { OPERAND_art }, 'i' },
   4758   { { OPERAND_ars }, 'i' },
   4759   { { OPERAND_lsi4x4 }, 'i' }
   4760 };
   4761 
   4762 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
   4763   { { OPERAND_arr }, 'o' }
   4764 };
   4765 
   4766 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
   4767   { { STATE_THREADPTR }, 'i' }
   4768 };
   4769 
   4770 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
   4771   { { OPERAND_art }, 'i' }
   4772 };
   4773 
   4774 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
   4775   { { STATE_THREADPTR }, 'o' }
   4776 };
   4777 
   4778 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
   4779   { { OPERAND_art }, 'o' },
   4780   { { OPERAND_ars }, 'i' },
   4781   { { OPERAND_simm8 }, 'i' }
   4782 };
   4783 
   4784 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
   4785   { { OPERAND_art }, 'o' },
   4786   { { OPERAND_ars }, 'i' },
   4787   { { OPERAND_simm8x256 }, 'i' }
   4788 };
   4789 
   4790 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
   4791   { { OPERAND_arr }, 'o' },
   4792   { { OPERAND_ars }, 'i' },
   4793   { { OPERAND_art }, 'i' }
   4794 };
   4795 
   4796 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
   4797   { { OPERAND_arr }, 'o' },
   4798   { { OPERAND_ars }, 'i' },
   4799   { { OPERAND_art }, 'i' }
   4800 };
   4801 
   4802 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
   4803   { { OPERAND_ars }, 'i' },
   4804   { { OPERAND_b4const }, 'i' },
   4805   { { OPERAND_label8 }, 'i' }
   4806 };
   4807 
   4808 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
   4809   { { OPERAND_ars }, 'i' },
   4810   { { OPERAND_bbi }, 'i' },
   4811   { { OPERAND_label8 }, 'i' }
   4812 };
   4813 
   4814 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
   4815   { { OPERAND_ars }, 'i' },
   4816   { { OPERAND_b4constu }, 'i' },
   4817   { { OPERAND_label8 }, 'i' }
   4818 };
   4819 
   4820 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
   4821   { { OPERAND_ars }, 'i' },
   4822   { { OPERAND_art }, 'i' },
   4823   { { OPERAND_label8 }, 'i' }
   4824 };
   4825 
   4826 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
   4827   { { OPERAND_ars }, 'i' },
   4828   { { OPERAND_label12 }, 'i' }
   4829 };
   4830 
   4831 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
   4832   { { OPERAND_soffsetx4 }, 'i' },
   4833   { { OPERAND_ar0 }, 'o' }
   4834 };
   4835 
   4836 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
   4837   { { OPERAND_ars }, 'i' },
   4838   { { OPERAND_ar0 }, 'o' }
   4839 };
   4840 
   4841 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
   4842   { { OPERAND_arr }, 'o' },
   4843   { { OPERAND_art }, 'i' },
   4844   { { OPERAND_sae }, 'i' },
   4845   { { OPERAND_op2p1 }, 'i' }
   4846 };
   4847 
   4848 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
   4849   { { OPERAND_soffset }, 'i' }
   4850 };
   4851 
   4852 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
   4853   { { OPERAND_ars }, 'i' }
   4854 };
   4855 
   4856 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
   4857   { { OPERAND_art }, 'o' },
   4858   { { OPERAND_ars }, 'i' },
   4859   { { OPERAND_uimm8x2 }, 'i' }
   4860 };
   4861 
   4862 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
   4863   { { OPERAND_art }, 'o' },
   4864   { { OPERAND_ars }, 'i' },
   4865   { { OPERAND_uimm8x2 }, 'i' }
   4866 };
   4867 
   4868 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
   4869   { { OPERAND_art }, 'o' },
   4870   { { OPERAND_ars }, 'i' },
   4871   { { OPERAND_uimm8x4 }, 'i' }
   4872 };
   4873 
   4874 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
   4875   { { OPERAND_art }, 'o' },
   4876   { { OPERAND_uimm16x4 }, 'i' }
   4877 };
   4878 
   4879 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
   4880   { { OPERAND_art }, 'o' },
   4881   { { OPERAND_ars }, 'i' },
   4882   { { OPERAND_uimm8 }, 'i' }
   4883 };
   4884 
   4885 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
   4886   { { OPERAND_ars }, 'i' },
   4887   { { OPERAND_ulabel8 }, 'i' }
   4888 };
   4889 
   4890 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
   4891   { { STATE_LBEG }, 'o' },
   4892   { { STATE_LEND }, 'o' },
   4893   { { STATE_LCOUNT }, 'o' }
   4894 };
   4895 
   4896 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
   4897   { { OPERAND_ars }, 'i' },
   4898   { { OPERAND_ulabel8 }, 'i' }
   4899 };
   4900 
   4901 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
   4902   { { STATE_LBEG }, 'o' },
   4903   { { STATE_LEND }, 'o' },
   4904   { { STATE_LCOUNT }, 'o' }
   4905 };
   4906 
   4907 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
   4908   { { OPERAND_art }, 'o' },
   4909   { { OPERAND_simm12b }, 'i' }
   4910 };
   4911 
   4912 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
   4913   { { OPERAND_arr }, 'm' },
   4914   { { OPERAND_ars }, 'i' },
   4915   { { OPERAND_art }, 'i' }
   4916 };
   4917 
   4918 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
   4919   { { OPERAND_arr }, 'o' },
   4920   { { OPERAND_art }, 'i' }
   4921 };
   4922 
   4923 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
   4924   { { OPERAND__ars_invisible }, 'i' }
   4925 };
   4926 
   4927 static xtensa_arg_internal Iclass_xt_iclass_simcall_args[] = {
   4928   { { OPERAND_immt }, 'i' }
   4929 };
   4930 
   4931 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
   4932   { { OPERAND_art }, 'i' },
   4933   { { OPERAND_ars }, 'i' },
   4934   { { OPERAND_uimm8x2 }, 'i' }
   4935 };
   4936 
   4937 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
   4938   { { OPERAND_art }, 'i' },
   4939   { { OPERAND_ars }, 'i' },
   4940   { { OPERAND_uimm8x4 }, 'i' }
   4941 };
   4942 
   4943 static xtensa_arg_internal Iclass_xt_iclass_s32nb_args[] = {
   4944   { { OPERAND_art }, 'i' },
   4945   { { OPERAND_ars }, 'i' },
   4946   { { OPERAND_uimmrx4 }, 'i' }
   4947 };
   4948 
   4949 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
   4950   { { OPERAND_art }, 'i' },
   4951   { { OPERAND_ars }, 'i' },
   4952   { { OPERAND_uimm8 }, 'i' }
   4953 };
   4954 
   4955 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
   4956   { { OPERAND_ars }, 'i' }
   4957 };
   4958 
   4959 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
   4960   { { STATE_SAR }, 'o' }
   4961 };
   4962 
   4963 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
   4964   { { OPERAND_sas }, 'i' }
   4965 };
   4966 
   4967 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
   4968   { { STATE_SAR }, 'o' }
   4969 };
   4970 
   4971 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
   4972   { { OPERAND_arr }, 'o' },
   4973   { { OPERAND_ars }, 'i' }
   4974 };
   4975 
   4976 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
   4977   { { STATE_SAR }, 'i' }
   4978 };
   4979 
   4980 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
   4981   { { OPERAND_arr }, 'o' },
   4982   { { OPERAND_ars }, 'i' },
   4983   { { OPERAND_art }, 'i' }
   4984 };
   4985 
   4986 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
   4987   { { STATE_SAR }, 'i' }
   4988 };
   4989 
   4990 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
   4991   { { OPERAND_arr }, 'o' },
   4992   { { OPERAND_art }, 'i' }
   4993 };
   4994 
   4995 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
   4996   { { STATE_SAR }, 'i' }
   4997 };
   4998 
   4999 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
   5000   { { OPERAND_arr }, 'o' },
   5001   { { OPERAND_ars }, 'i' },
   5002   { { OPERAND_msalp32 }, 'i' }
   5003 };
   5004 
   5005 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
   5006   { { OPERAND_arr }, 'o' },
   5007   { { OPERAND_art }, 'i' },
   5008   { { OPERAND_sargt }, 'i' }
   5009 };
   5010 
   5011 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
   5012   { { OPERAND_arr }, 'o' },
   5013   { { OPERAND_art }, 'i' },
   5014   { { OPERAND_s }, 'i' }
   5015 };
   5016 
   5017 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
   5018   { { STATE_XTSYNC }, 'i' }
   5019 };
   5020 
   5021 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
   5022   { { OPERAND_art }, 'o' },
   5023   { { OPERAND_s }, 'i' }
   5024 };
   5025 
   5026 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
   5027   { { STATE_PSWOE }, 'i' },
   5028   { { STATE_PSCALLINC }, 'i' },
   5029   { { STATE_PSOWB }, 'i' },
   5030   { { STATE_PSRING }, 'i' },
   5031   { { STATE_PSUM }, 'i' },
   5032   { { STATE_PSEXCM }, 'i' },
   5033   { { STATE_PSINTLEVEL }, 'm' }
   5034 };
   5035 
   5036 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
   5037   { { OPERAND_art }, 'o' }
   5038 };
   5039 
   5040 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
   5041   { { STATE_LEND }, 'i' }
   5042 };
   5043 
   5044 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
   5045   { { OPERAND_art }, 'i' }
   5046 };
   5047 
   5048 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
   5049   { { STATE_LEND }, 'o' }
   5050 };
   5051 
   5052 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
   5053   { { OPERAND_art }, 'm' }
   5054 };
   5055 
   5056 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
   5057   { { STATE_LEND }, 'm' }
   5058 };
   5059 
   5060 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
   5061   { { OPERAND_art }, 'o' }
   5062 };
   5063 
   5064 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
   5065   { { STATE_LCOUNT }, 'i' }
   5066 };
   5067 
   5068 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
   5069   { { OPERAND_art }, 'i' }
   5070 };
   5071 
   5072 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
   5073   { { STATE_XTSYNC }, 'o' },
   5074   { { STATE_LCOUNT }, 'o' }
   5075 };
   5076 
   5077 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
   5078   { { OPERAND_art }, 'm' }
   5079 };
   5080 
   5081 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
   5082   { { STATE_XTSYNC }, 'o' },
   5083   { { STATE_LCOUNT }, 'm' }
   5084 };
   5085 
   5086 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
   5087   { { OPERAND_art }, 'o' }
   5088 };
   5089 
   5090 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
   5091   { { STATE_LBEG }, 'i' }
   5092 };
   5093 
   5094 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
   5095   { { OPERAND_art }, 'i' }
   5096 };
   5097 
   5098 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
   5099   { { STATE_LBEG }, 'o' }
   5100 };
   5101 
   5102 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
   5103   { { OPERAND_art }, 'm' }
   5104 };
   5105 
   5106 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
   5107   { { STATE_LBEG }, 'm' }
   5108 };
   5109 
   5110 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
   5111   { { OPERAND_art }, 'o' }
   5112 };
   5113 
   5114 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
   5115   { { STATE_SAR }, 'i' }
   5116 };
   5117 
   5118 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
   5119   { { OPERAND_art }, 'i' }
   5120 };
   5121 
   5122 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
   5123   { { STATE_SAR }, 'o' },
   5124   { { STATE_XTSYNC }, 'o' }
   5125 };
   5126 
   5127 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
   5128   { { OPERAND_art }, 'm' }
   5129 };
   5130 
   5131 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
   5132   { { STATE_SAR }, 'm' }
   5133 };
   5134 
   5135 static xtensa_arg_internal Iclass_xt_iclass_rsr_memctl_args[] = {
   5136   { { OPERAND_art }, 'o' }
   5137 };
   5138 
   5139 static xtensa_arg_internal Iclass_xt_iclass_wsr_memctl_args[] = {
   5140   { { OPERAND_art }, 'i' }
   5141 };
   5142 
   5143 static xtensa_arg_internal Iclass_xt_iclass_xsr_memctl_args[] = {
   5144   { { OPERAND_art }, 'm' }
   5145 };
   5146 
   5147 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
   5148   { { OPERAND_art }, 'o' }
   5149 };
   5150 
   5151 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
   5152   { { STATE_PSEXCM }, 'i' },
   5153   { { STATE_PSRING }, 'i' }
   5154 };
   5155 
   5156 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
   5157   { { OPERAND_art }, 'i' }
   5158 };
   5159 
   5160 static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
   5161   { { STATE_PSEXCM }, 'i' },
   5162   { { STATE_PSRING }, 'i' }
   5163 };
   5164 
   5165 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
   5166   { { OPERAND_art }, 'o' }
   5167 };
   5168 
   5169 static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
   5170   { { STATE_PSEXCM }, 'i' },
   5171   { { STATE_PSRING }, 'i' }
   5172 };
   5173 
   5174 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
   5175   { { OPERAND_art }, 'o' }
   5176 };
   5177 
   5178 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
   5179   { { STATE_PSWOE }, 'i' },
   5180   { { STATE_PSCALLINC }, 'i' },
   5181   { { STATE_PSOWB }, 'i' },
   5182   { { STATE_PSRING }, 'i' },
   5183   { { STATE_PSUM }, 'i' },
   5184   { { STATE_PSEXCM }, 'i' },
   5185   { { STATE_PSINTLEVEL }, 'i' }
   5186 };
   5187 
   5188 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
   5189   { { OPERAND_art }, 'i' }
   5190 };
   5191 
   5192 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
   5193   { { STATE_PSWOE }, 'o' },
   5194   { { STATE_PSCALLINC }, 'o' },
   5195   { { STATE_PSOWB }, 'o' },
   5196   { { STATE_PSRING }, 'm' },
   5197   { { STATE_PSUM }, 'o' },
   5198   { { STATE_PSEXCM }, 'm' },
   5199   { { STATE_PSINTLEVEL }, 'o' }
   5200 };
   5201 
   5202 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
   5203   { { OPERAND_art }, 'm' }
   5204 };
   5205 
   5206 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
   5207   { { STATE_PSWOE }, 'm' },
   5208   { { STATE_PSCALLINC }, 'm' },
   5209   { { STATE_PSOWB }, 'm' },
   5210   { { STATE_PSRING }, 'm' },
   5211   { { STATE_PSUM }, 'm' },
   5212   { { STATE_PSEXCM }, 'm' },
   5213   { { STATE_PSINTLEVEL }, 'm' }
   5214 };
   5215 
   5216 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
   5217   { { OPERAND_art }, 'o' }
   5218 };
   5219 
   5220 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
   5221   { { STATE_PSEXCM }, 'i' },
   5222   { { STATE_PSRING }, 'i' },
   5223   { { STATE_EPC1 }, 'i' }
   5224 };
   5225 
   5226 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
   5227   { { OPERAND_art }, 'i' }
   5228 };
   5229 
   5230 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
   5231   { { STATE_PSEXCM }, 'i' },
   5232   { { STATE_PSRING }, 'i' },
   5233   { { STATE_EPC1 }, 'o' }
   5234 };
   5235 
   5236 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
   5237   { { OPERAND_art }, 'm' }
   5238 };
   5239 
   5240 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
   5241   { { STATE_PSEXCM }, 'i' },
   5242   { { STATE_PSRING }, 'i' },
   5243   { { STATE_EPC1 }, 'm' }
   5244 };
   5245 
   5246 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
   5247   { { OPERAND_art }, 'o' }
   5248 };
   5249 
   5250 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
   5251   { { STATE_PSEXCM }, 'i' },
   5252   { { STATE_PSRING }, 'i' },
   5253   { { STATE_EXCSAVE1 }, 'i' }
   5254 };
   5255 
   5256 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
   5257   { { OPERAND_art }, 'i' }
   5258 };
   5259 
   5260 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
   5261   { { STATE_PSEXCM }, 'i' },
   5262   { { STATE_PSRING }, 'i' },
   5263   { { STATE_EXCSAVE1 }, 'o' }
   5264 };
   5265 
   5266 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
   5267   { { OPERAND_art }, 'm' }
   5268 };
   5269 
   5270 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
   5271   { { STATE_PSEXCM }, 'i' },
   5272   { { STATE_PSRING }, 'i' },
   5273   { { STATE_EXCSAVE1 }, 'm' }
   5274 };
   5275 
   5276 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
   5277   { { OPERAND_art }, 'o' }
   5278 };
   5279 
   5280 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
   5281   { { STATE_PSEXCM }, 'i' },
   5282   { { STATE_PSRING }, 'i' },
   5283   { { STATE_EPC2 }, 'i' }
   5284 };
   5285 
   5286 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
   5287   { { OPERAND_art }, 'i' }
   5288 };
   5289 
   5290 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
   5291   { { STATE_PSEXCM }, 'i' },
   5292   { { STATE_PSRING }, 'i' },
   5293   { { STATE_EPC2 }, 'o' }
   5294 };
   5295 
   5296 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
   5297   { { OPERAND_art }, 'm' }
   5298 };
   5299 
   5300 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
   5301   { { STATE_PSEXCM }, 'i' },
   5302   { { STATE_PSRING }, 'i' },
   5303   { { STATE_EPC2 }, 'm' }
   5304 };
   5305 
   5306 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
   5307   { { OPERAND_art }, 'o' }
   5308 };
   5309 
   5310 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
   5311   { { STATE_PSEXCM }, 'i' },
   5312   { { STATE_PSRING }, 'i' },
   5313   { { STATE_EXCSAVE2 }, 'i' }
   5314 };
   5315 
   5316 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
   5317   { { OPERAND_art }, 'i' }
   5318 };
   5319 
   5320 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
   5321   { { STATE_PSEXCM }, 'i' },
   5322   { { STATE_PSRING }, 'i' },
   5323   { { STATE_EXCSAVE2 }, 'o' }
   5324 };
   5325 
   5326 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
   5327   { { OPERAND_art }, 'm' }
   5328 };
   5329 
   5330 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
   5331   { { STATE_PSEXCM }, 'i' },
   5332   { { STATE_PSRING }, 'i' },
   5333   { { STATE_EXCSAVE2 }, 'm' }
   5334 };
   5335 
   5336 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
   5337   { { OPERAND_art }, 'o' }
   5338 };
   5339 
   5340 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
   5341   { { STATE_PSEXCM }, 'i' },
   5342   { { STATE_PSRING }, 'i' },
   5343   { { STATE_EPC3 }, 'i' }
   5344 };
   5345 
   5346 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
   5347   { { OPERAND_art }, 'i' }
   5348 };
   5349 
   5350 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
   5351   { { STATE_PSEXCM }, 'i' },
   5352   { { STATE_PSRING }, 'i' },
   5353   { { STATE_EPC3 }, 'o' }
   5354 };
   5355 
   5356 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
   5357   { { OPERAND_art }, 'm' }
   5358 };
   5359 
   5360 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
   5361   { { STATE_PSEXCM }, 'i' },
   5362   { { STATE_PSRING }, 'i' },
   5363   { { STATE_EPC3 }, 'm' }
   5364 };
   5365 
   5366 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
   5367   { { OPERAND_art }, 'o' }
   5368 };
   5369 
   5370 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
   5371   { { STATE_PSEXCM }, 'i' },
   5372   { { STATE_PSRING }, 'i' },
   5373   { { STATE_EXCSAVE3 }, 'i' }
   5374 };
   5375 
   5376 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
   5377   { { OPERAND_art }, 'i' }
   5378 };
   5379 
   5380 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
   5381   { { STATE_PSEXCM }, 'i' },
   5382   { { STATE_PSRING }, 'i' },
   5383   { { STATE_EXCSAVE3 }, 'o' }
   5384 };
   5385 
   5386 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
   5387   { { OPERAND_art }, 'm' }
   5388 };
   5389 
   5390 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
   5391   { { STATE_PSEXCM }, 'i' },
   5392   { { STATE_PSRING }, 'i' },
   5393   { { STATE_EXCSAVE3 }, 'm' }
   5394 };
   5395 
   5396 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
   5397   { { OPERAND_art }, 'o' }
   5398 };
   5399 
   5400 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
   5401   { { STATE_PSEXCM }, 'i' },
   5402   { { STATE_PSRING }, 'i' },
   5403   { { STATE_EPC4 }, 'i' }
   5404 };
   5405 
   5406 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
   5407   { { OPERAND_art }, 'i' }
   5408 };
   5409 
   5410 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
   5411   { { STATE_PSEXCM }, 'i' },
   5412   { { STATE_PSRING }, 'i' },
   5413   { { STATE_EPC4 }, 'o' }
   5414 };
   5415 
   5416 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
   5417   { { OPERAND_art }, 'm' }
   5418 };
   5419 
   5420 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
   5421   { { STATE_PSEXCM }, 'i' },
   5422   { { STATE_PSRING }, 'i' },
   5423   { { STATE_EPC4 }, 'm' }
   5424 };
   5425 
   5426 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
   5427   { { OPERAND_art }, 'o' }
   5428 };
   5429 
   5430 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
   5431   { { STATE_PSEXCM }, 'i' },
   5432   { { STATE_PSRING }, 'i' },
   5433   { { STATE_EXCSAVE4 }, 'i' }
   5434 };
   5435 
   5436 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
   5437   { { OPERAND_art }, 'i' }
   5438 };
   5439 
   5440 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
   5441   { { STATE_PSEXCM }, 'i' },
   5442   { { STATE_PSRING }, 'i' },
   5443   { { STATE_EXCSAVE4 }, 'o' }
   5444 };
   5445 
   5446 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
   5447   { { OPERAND_art }, 'm' }
   5448 };
   5449 
   5450 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
   5451   { { STATE_PSEXCM }, 'i' },
   5452   { { STATE_PSRING }, 'i' },
   5453   { { STATE_EXCSAVE4 }, 'm' }
   5454 };
   5455 
   5456 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
   5457   { { OPERAND_art }, 'o' }
   5458 };
   5459 
   5460 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
   5461   { { STATE_PSEXCM }, 'i' },
   5462   { { STATE_PSRING }, 'i' },
   5463   { { STATE_EPC5 }, 'i' }
   5464 };
   5465 
   5466 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
   5467   { { OPERAND_art }, 'i' }
   5468 };
   5469 
   5470 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
   5471   { { STATE_PSEXCM }, 'i' },
   5472   { { STATE_PSRING }, 'i' },
   5473   { { STATE_EPC5 }, 'o' }
   5474 };
   5475 
   5476 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
   5477   { { OPERAND_art }, 'm' }
   5478 };
   5479 
   5480 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
   5481   { { STATE_PSEXCM }, 'i' },
   5482   { { STATE_PSRING }, 'i' },
   5483   { { STATE_EPC5 }, 'm' }
   5484 };
   5485 
   5486 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
   5487   { { OPERAND_art }, 'o' }
   5488 };
   5489 
   5490 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
   5491   { { STATE_PSEXCM }, 'i' },
   5492   { { STATE_PSRING }, 'i' },
   5493   { { STATE_EXCSAVE5 }, 'i' }
   5494 };
   5495 
   5496 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
   5497   { { OPERAND_art }, 'i' }
   5498 };
   5499 
   5500 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
   5501   { { STATE_PSEXCM }, 'i' },
   5502   { { STATE_PSRING }, 'i' },
   5503   { { STATE_EXCSAVE5 }, 'o' }
   5504 };
   5505 
   5506 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
   5507   { { OPERAND_art }, 'm' }
   5508 };
   5509 
   5510 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
   5511   { { STATE_PSEXCM }, 'i' },
   5512   { { STATE_PSRING }, 'i' },
   5513   { { STATE_EXCSAVE5 }, 'm' }
   5514 };
   5515 
   5516 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
   5517   { { OPERAND_art }, 'o' }
   5518 };
   5519 
   5520 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
   5521   { { STATE_PSEXCM }, 'i' },
   5522   { { STATE_PSRING }, 'i' },
   5523   { { STATE_EPC6 }, 'i' }
   5524 };
   5525 
   5526 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
   5527   { { OPERAND_art }, 'i' }
   5528 };
   5529 
   5530 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
   5531   { { STATE_PSEXCM }, 'i' },
   5532   { { STATE_PSRING }, 'i' },
   5533   { { STATE_EPC6 }, 'o' }
   5534 };
   5535 
   5536 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
   5537   { { OPERAND_art }, 'm' }
   5538 };
   5539 
   5540 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
   5541   { { STATE_PSEXCM }, 'i' },
   5542   { { STATE_PSRING }, 'i' },
   5543   { { STATE_EPC6 }, 'm' }
   5544 };
   5545 
   5546 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
   5547   { { OPERAND_art }, 'o' }
   5548 };
   5549 
   5550 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
   5551   { { STATE_PSEXCM }, 'i' },
   5552   { { STATE_PSRING }, 'i' },
   5553   { { STATE_EXCSAVE6 }, 'i' }
   5554 };
   5555 
   5556 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
   5557   { { OPERAND_art }, 'i' }
   5558 };
   5559 
   5560 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
   5561   { { STATE_PSEXCM }, 'i' },
   5562   { { STATE_PSRING }, 'i' },
   5563   { { STATE_EXCSAVE6 }, 'o' }
   5564 };
   5565 
   5566 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
   5567   { { OPERAND_art }, 'm' }
   5568 };
   5569 
   5570 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
   5571   { { STATE_PSEXCM }, 'i' },
   5572   { { STATE_PSRING }, 'i' },
   5573   { { STATE_EXCSAVE6 }, 'm' }
   5574 };
   5575 
   5576 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
   5577   { { OPERAND_art }, 'o' }
   5578 };
   5579 
   5580 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
   5581   { { STATE_PSEXCM }, 'i' },
   5582   { { STATE_PSRING }, 'i' },
   5583   { { STATE_EPC7 }, 'i' }
   5584 };
   5585 
   5586 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
   5587   { { OPERAND_art }, 'i' }
   5588 };
   5589 
   5590 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
   5591   { { STATE_PSEXCM }, 'i' },
   5592   { { STATE_PSRING }, 'i' },
   5593   { { STATE_EPC7 }, 'o' }
   5594 };
   5595 
   5596 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
   5597   { { OPERAND_art }, 'm' }
   5598 };
   5599 
   5600 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
   5601   { { STATE_PSEXCM }, 'i' },
   5602   { { STATE_PSRING }, 'i' },
   5603   { { STATE_EPC7 }, 'm' }
   5604 };
   5605 
   5606 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
   5607   { { OPERAND_art }, 'o' }
   5608 };
   5609 
   5610 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
   5611   { { STATE_PSEXCM }, 'i' },
   5612   { { STATE_PSRING }, 'i' },
   5613   { { STATE_EXCSAVE7 }, 'i' }
   5614 };
   5615 
   5616 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
   5617   { { OPERAND_art }, 'i' }
   5618 };
   5619 
   5620 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
   5621   { { STATE_PSEXCM }, 'i' },
   5622   { { STATE_PSRING }, 'i' },
   5623   { { STATE_EXCSAVE7 }, 'o' }
   5624 };
   5625 
   5626 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
   5627   { { OPERAND_art }, 'm' }
   5628 };
   5629 
   5630 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
   5631   { { STATE_PSEXCM }, 'i' },
   5632   { { STATE_PSRING }, 'i' },
   5633   { { STATE_EXCSAVE7 }, 'm' }
   5634 };
   5635 
   5636 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
   5637   { { OPERAND_art }, 'o' }
   5638 };
   5639 
   5640 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
   5641   { { STATE_PSEXCM }, 'i' },
   5642   { { STATE_PSRING }, 'i' },
   5643   { { STATE_EPS2 }, 'i' }
   5644 };
   5645 
   5646 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
   5647   { { OPERAND_art }, 'i' }
   5648 };
   5649 
   5650 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
   5651   { { STATE_PSEXCM }, 'i' },
   5652   { { STATE_PSRING }, 'i' },
   5653   { { STATE_EPS2 }, 'o' }
   5654 };
   5655 
   5656 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
   5657   { { OPERAND_art }, 'm' }
   5658 };
   5659 
   5660 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
   5661   { { STATE_PSEXCM }, 'i' },
   5662   { { STATE_PSRING }, 'i' },
   5663   { { STATE_EPS2 }, 'm' }
   5664 };
   5665 
   5666 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
   5667   { { OPERAND_art }, 'o' }
   5668 };
   5669 
   5670 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
   5671   { { STATE_PSEXCM }, 'i' },
   5672   { { STATE_PSRING }, 'i' },
   5673   { { STATE_EPS3 }, 'i' }
   5674 };
   5675 
   5676 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
   5677   { { OPERAND_art }, 'i' }
   5678 };
   5679 
   5680 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
   5681   { { STATE_PSEXCM }, 'i' },
   5682   { { STATE_PSRING }, 'i' },
   5683   { { STATE_EPS3 }, 'o' }
   5684 };
   5685 
   5686 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
   5687   { { OPERAND_art }, 'm' }
   5688 };
   5689 
   5690 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
   5691   { { STATE_PSEXCM }, 'i' },
   5692   { { STATE_PSRING }, 'i' },
   5693   { { STATE_EPS3 }, 'm' }
   5694 };
   5695 
   5696 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
   5697   { { OPERAND_art }, 'o' }
   5698 };
   5699 
   5700 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
   5701   { { STATE_PSEXCM }, 'i' },
   5702   { { STATE_PSRING }, 'i' },
   5703   { { STATE_EPS4 }, 'i' }
   5704 };
   5705 
   5706 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
   5707   { { OPERAND_art }, 'i' }
   5708 };
   5709 
   5710 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
   5711   { { STATE_PSEXCM }, 'i' },
   5712   { { STATE_PSRING }, 'i' },
   5713   { { STATE_EPS4 }, 'o' }
   5714 };
   5715 
   5716 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
   5717   { { OPERAND_art }, 'm' }
   5718 };
   5719 
   5720 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
   5721   { { STATE_PSEXCM }, 'i' },
   5722   { { STATE_PSRING }, 'i' },
   5723   { { STATE_EPS4 }, 'm' }
   5724 };
   5725 
   5726 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
   5727   { { OPERAND_art }, 'o' }
   5728 };
   5729 
   5730 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
   5731   { { STATE_PSEXCM }, 'i' },
   5732   { { STATE_PSRING }, 'i' },
   5733   { { STATE_EPS5 }, 'i' }
   5734 };
   5735 
   5736 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
   5737   { { OPERAND_art }, 'i' }
   5738 };
   5739 
   5740 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
   5741   { { STATE_PSEXCM }, 'i' },
   5742   { { STATE_PSRING }, 'i' },
   5743   { { STATE_EPS5 }, 'o' }
   5744 };
   5745 
   5746 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
   5747   { { OPERAND_art }, 'm' }
   5748 };
   5749 
   5750 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
   5751   { { STATE_PSEXCM }, 'i' },
   5752   { { STATE_PSRING }, 'i' },
   5753   { { STATE_EPS5 }, 'm' }
   5754 };
   5755 
   5756 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
   5757   { { OPERAND_art }, 'o' }
   5758 };
   5759 
   5760 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
   5761   { { STATE_PSEXCM }, 'i' },
   5762   { { STATE_PSRING }, 'i' },
   5763   { { STATE_EPS6 }, 'i' }
   5764 };
   5765 
   5766 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
   5767   { { OPERAND_art }, 'i' }
   5768 };
   5769 
   5770 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
   5771   { { STATE_PSEXCM }, 'i' },
   5772   { { STATE_PSRING }, 'i' },
   5773   { { STATE_EPS6 }, 'o' }
   5774 };
   5775 
   5776 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
   5777   { { OPERAND_art }, 'm' }
   5778 };
   5779 
   5780 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
   5781   { { STATE_PSEXCM }, 'i' },
   5782   { { STATE_PSRING }, 'i' },
   5783   { { STATE_EPS6 }, 'm' }
   5784 };
   5785 
   5786 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
   5787   { { OPERAND_art }, 'o' }
   5788 };
   5789 
   5790 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
   5791   { { STATE_PSEXCM }, 'i' },
   5792   { { STATE_PSRING }, 'i' },
   5793   { { STATE_EPS7 }, 'i' }
   5794 };
   5795 
   5796 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
   5797   { { OPERAND_art }, 'i' }
   5798 };
   5799 
   5800 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
   5801   { { STATE_PSEXCM }, 'i' },
   5802   { { STATE_PSRING }, 'i' },
   5803   { { STATE_EPS7 }, 'o' }
   5804 };
   5805 
   5806 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
   5807   { { OPERAND_art }, 'm' }
   5808 };
   5809 
   5810 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
   5811   { { STATE_PSEXCM }, 'i' },
   5812   { { STATE_PSRING }, 'i' },
   5813   { { STATE_EPS7 }, 'm' }
   5814 };
   5815 
   5816 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
   5817   { { OPERAND_art }, 'o' }
   5818 };
   5819 
   5820 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
   5821   { { STATE_PSEXCM }, 'i' },
   5822   { { STATE_PSRING }, 'i' },
   5823   { { STATE_EXCVADDR }, 'i' }
   5824 };
   5825 
   5826 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
   5827   { { OPERAND_art }, 'i' }
   5828 };
   5829 
   5830 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
   5831   { { STATE_PSEXCM }, 'i' },
   5832   { { STATE_PSRING }, 'i' },
   5833   { { STATE_EXCVADDR }, 'o' }
   5834 };
   5835 
   5836 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
   5837   { { OPERAND_art }, 'm' }
   5838 };
   5839 
   5840 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
   5841   { { STATE_PSEXCM }, 'i' },
   5842   { { STATE_PSRING }, 'i' },
   5843   { { STATE_EXCVADDR }, 'm' }
   5844 };
   5845 
   5846 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
   5847   { { OPERAND_art }, 'o' }
   5848 };
   5849 
   5850 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
   5851   { { STATE_PSEXCM }, 'i' },
   5852   { { STATE_PSRING }, 'i' },
   5853   { { STATE_DEPC }, 'i' }
   5854 };
   5855 
   5856 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
   5857   { { OPERAND_art }, 'i' }
   5858 };
   5859 
   5860 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
   5861   { { STATE_PSEXCM }, 'i' },
   5862   { { STATE_PSRING }, 'i' },
   5863   { { STATE_DEPC }, 'o' }
   5864 };
   5865 
   5866 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
   5867   { { OPERAND_art }, 'm' }
   5868 };
   5869 
   5870 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
   5871   { { STATE_PSEXCM }, 'i' },
   5872   { { STATE_PSRING }, 'i' },
   5873   { { STATE_DEPC }, 'm' }
   5874 };
   5875 
   5876 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
   5877   { { OPERAND_art }, 'o' }
   5878 };
   5879 
   5880 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
   5881   { { STATE_PSEXCM }, 'i' },
   5882   { { STATE_PSRING }, 'i' },
   5883   { { STATE_EXCCAUSE }, 'i' },
   5884   { { STATE_XTSYNC }, 'i' }
   5885 };
   5886 
   5887 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
   5888   { { OPERAND_art }, 'i' }
   5889 };
   5890 
   5891 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
   5892   { { STATE_PSEXCM }, 'i' },
   5893   { { STATE_PSRING }, 'i' },
   5894   { { STATE_EXCCAUSE }, 'o' }
   5895 };
   5896 
   5897 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
   5898   { { OPERAND_art }, 'm' }
   5899 };
   5900 
   5901 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
   5902   { { STATE_PSEXCM }, 'i' },
   5903   { { STATE_PSRING }, 'i' },
   5904   { { STATE_EXCCAUSE }, 'm' }
   5905 };
   5906 
   5907 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
   5908   { { OPERAND_art }, 'o' }
   5909 };
   5910 
   5911 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
   5912   { { STATE_PSEXCM }, 'i' },
   5913   { { STATE_PSRING }, 'i' },
   5914   { { STATE_MISC0 }, 'i' }
   5915 };
   5916 
   5917 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
   5918   { { OPERAND_art }, 'i' }
   5919 };
   5920 
   5921 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
   5922   { { STATE_PSEXCM }, 'i' },
   5923   { { STATE_PSRING }, 'i' },
   5924   { { STATE_MISC0 }, 'o' }
   5925 };
   5926 
   5927 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
   5928   { { OPERAND_art }, 'm' }
   5929 };
   5930 
   5931 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
   5932   { { STATE_PSEXCM }, 'i' },
   5933   { { STATE_PSRING }, 'i' },
   5934   { { STATE_MISC0 }, 'm' }
   5935 };
   5936 
   5937 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
   5938   { { OPERAND_art }, 'o' }
   5939 };
   5940 
   5941 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
   5942   { { STATE_PSEXCM }, 'i' },
   5943   { { STATE_PSRING }, 'i' },
   5944   { { STATE_MISC1 }, 'i' }
   5945 };
   5946 
   5947 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
   5948   { { OPERAND_art }, 'i' }
   5949 };
   5950 
   5951 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
   5952   { { STATE_PSEXCM }, 'i' },
   5953   { { STATE_PSRING }, 'i' },
   5954   { { STATE_MISC1 }, 'o' }
   5955 };
   5956 
   5957 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
   5958   { { OPERAND_art }, 'm' }
   5959 };
   5960 
   5961 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
   5962   { { STATE_PSEXCM }, 'i' },
   5963   { { STATE_PSRING }, 'i' },
   5964   { { STATE_MISC1 }, 'm' }
   5965 };
   5966 
   5967 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
   5968   { { OPERAND_art }, 'o' }
   5969 };
   5970 
   5971 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
   5972   { { STATE_PSEXCM }, 'i' },
   5973   { { STATE_PSRING }, 'i' }
   5974 };
   5975 
   5976 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
   5977   { { OPERAND_art }, 'o' }
   5978 };
   5979 
   5980 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
   5981   { { STATE_PSEXCM }, 'i' },
   5982   { { STATE_PSRING }, 'i' },
   5983   { { STATE_VECBASE }, 'i' }
   5984 };
   5985 
   5986 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
   5987   { { OPERAND_art }, 'i' }
   5988 };
   5989 
   5990 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
   5991   { { STATE_PSEXCM }, 'i' },
   5992   { { STATE_PSRING }, 'i' },
   5993   { { STATE_VECBASE }, 'o' }
   5994 };
   5995 
   5996 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
   5997   { { OPERAND_art }, 'm' }
   5998 };
   5999 
   6000 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
   6001   { { STATE_PSEXCM }, 'i' },
   6002   { { STATE_PSRING }, 'i' },
   6003   { { STATE_VECBASE }, 'm' }
   6004 };
   6005 
   6006 static xtensa_arg_internal Iclass_xt_iclass_salt_args[] = {
   6007   { { OPERAND_arr }, 'o' },
   6008   { { OPERAND_ars }, 'i' },
   6009   { { OPERAND_art }, 'i' }
   6010 };
   6011 
   6012 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
   6013   { { OPERAND_arr }, 'o' },
   6014   { { OPERAND_ars }, 'i' },
   6015   { { OPERAND_art }, 'i' }
   6016 };
   6017 
   6018 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
   6019   { { OPERAND_arr }, 'o' },
   6020   { { OPERAND_ars }, 'i' },
   6021   { { OPERAND_art }, 'i' }
   6022 };
   6023 
   6024 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
   6025   { { OPERAND_ars }, 'i' },
   6026   { { OPERAND_art }, 'i' }
   6027 };
   6028 
   6029 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
   6030   { { STATE_ACC }, 'o' }
   6031 };
   6032 
   6033 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
   6034   { { OPERAND_ars }, 'i' },
   6035   { { OPERAND_my }, 'i' }
   6036 };
   6037 
   6038 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
   6039   { { STATE_ACC }, 'o' }
   6040 };
   6041 
   6042 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
   6043   { { OPERAND_mx }, 'i' },
   6044   { { OPERAND_art }, 'i' }
   6045 };
   6046 
   6047 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
   6048   { { STATE_ACC }, 'o' }
   6049 };
   6050 
   6051 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
   6052   { { OPERAND_mx }, 'i' },
   6053   { { OPERAND_my }, 'i' }
   6054 };
   6055 
   6056 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
   6057   { { STATE_ACC }, 'o' }
   6058 };
   6059 
   6060 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
   6061   { { OPERAND_ars }, 'i' },
   6062   { { OPERAND_art }, 'i' }
   6063 };
   6064 
   6065 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
   6066   { { STATE_ACC }, 'm' }
   6067 };
   6068 
   6069 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
   6070   { { OPERAND_ars }, 'i' },
   6071   { { OPERAND_my }, 'i' }
   6072 };
   6073 
   6074 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
   6075   { { STATE_ACC }, 'm' }
   6076 };
   6077 
   6078 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
   6079   { { OPERAND_mx }, 'i' },
   6080   { { OPERAND_art }, 'i' }
   6081 };
   6082 
   6083 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
   6084   { { STATE_ACC }, 'm' }
   6085 };
   6086 
   6087 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
   6088   { { OPERAND_mx }, 'i' },
   6089   { { OPERAND_my }, 'i' }
   6090 };
   6091 
   6092 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
   6093   { { STATE_ACC }, 'm' }
   6094 };
   6095 
   6096 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
   6097   { { OPERAND_mw }, 'o' },
   6098   { { OPERAND_ars }, 'm' },
   6099   { { OPERAND_mx }, 'i' },
   6100   { { OPERAND_art }, 'i' }
   6101 };
   6102 
   6103 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
   6104   { { STATE_ACC }, 'm' }
   6105 };
   6106 
   6107 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
   6108   { { OPERAND_mw }, 'o' },
   6109   { { OPERAND_ars }, 'm' },
   6110   { { OPERAND_mx }, 'i' },
   6111   { { OPERAND_my }, 'i' }
   6112 };
   6113 
   6114 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
   6115   { { STATE_ACC }, 'm' }
   6116 };
   6117 
   6118 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
   6119   { { OPERAND_mw }, 'o' },
   6120   { { OPERAND_ars }, 'm' }
   6121 };
   6122 
   6123 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
   6124   { { OPERAND_art }, 'o' },
   6125   { { OPERAND_mr0 }, 'i' }
   6126 };
   6127 
   6128 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
   6129   { { OPERAND_art }, 'i' },
   6130   { { OPERAND_mr0 }, 'o' }
   6131 };
   6132 
   6133 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
   6134   { { OPERAND_art }, 'm' },
   6135   { { OPERAND_mr0 }, 'm' }
   6136 };
   6137 
   6138 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
   6139   { { OPERAND_art }, 'o' },
   6140   { { OPERAND_mr1 }, 'i' }
   6141 };
   6142 
   6143 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
   6144   { { OPERAND_art }, 'i' },
   6145   { { OPERAND_mr1 }, 'o' }
   6146 };
   6147 
   6148 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
   6149   { { OPERAND_art }, 'm' },
   6150   { { OPERAND_mr1 }, 'm' }
   6151 };
   6152 
   6153 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
   6154   { { OPERAND_art }, 'o' },
   6155   { { OPERAND_mr2 }, 'i' }
   6156 };
   6157 
   6158 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
   6159   { { OPERAND_art }, 'i' },
   6160   { { OPERAND_mr2 }, 'o' }
   6161 };
   6162 
   6163 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
   6164   { { OPERAND_art }, 'm' },
   6165   { { OPERAND_mr2 }, 'm' }
   6166 };
   6167 
   6168 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
   6169   { { OPERAND_art }, 'o' },
   6170   { { OPERAND_mr3 }, 'i' }
   6171 };
   6172 
   6173 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
   6174   { { OPERAND_art }, 'i' },
   6175   { { OPERAND_mr3 }, 'o' }
   6176 };
   6177 
   6178 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
   6179   { { OPERAND_art }, 'm' },
   6180   { { OPERAND_mr3 }, 'm' }
   6181 };
   6182 
   6183 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
   6184   { { OPERAND_art }, 'o' }
   6185 };
   6186 
   6187 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
   6188   { { STATE_ACC }, 'i' }
   6189 };
   6190 
   6191 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
   6192   { { OPERAND_art }, 'i' }
   6193 };
   6194 
   6195 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
   6196   { { STATE_ACC }, 'm' }
   6197 };
   6198 
   6199 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
   6200   { { OPERAND_art }, 'm' }
   6201 };
   6202 
   6203 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
   6204   { { STATE_ACC }, 'm' }
   6205 };
   6206 
   6207 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
   6208   { { OPERAND_art }, 'o' }
   6209 };
   6210 
   6211 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
   6212   { { STATE_ACC }, 'i' }
   6213 };
   6214 
   6215 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
   6216   { { OPERAND_art }, 'i' }
   6217 };
   6218 
   6219 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
   6220   { { STATE_ACC }, 'm' }
   6221 };
   6222 
   6223 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
   6224   { { OPERAND_art }, 'm' }
   6225 };
   6226 
   6227 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
   6228   { { STATE_ACC }, 'm' }
   6229 };
   6230 
   6231 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
   6232   { { OPERAND_s }, 'i' }
   6233 };
   6234 
   6235 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
   6236   { { STATE_PSWOE }, 'o' },
   6237   { { STATE_PSCALLINC }, 'o' },
   6238   { { STATE_PSOWB }, 'o' },
   6239   { { STATE_PSRING }, 'm' },
   6240   { { STATE_PSUM }, 'o' },
   6241   { { STATE_PSEXCM }, 'm' },
   6242   { { STATE_PSINTLEVEL }, 'o' },
   6243   { { STATE_EPC1 }, 'i' },
   6244   { { STATE_EPC2 }, 'i' },
   6245   { { STATE_EPC3 }, 'i' },
   6246   { { STATE_EPC4 }, 'i' },
   6247   { { STATE_EPC5 }, 'i' },
   6248   { { STATE_EPC6 }, 'i' },
   6249   { { STATE_EPC7 }, 'i' },
   6250   { { STATE_EPS2 }, 'i' },
   6251   { { STATE_EPS3 }, 'i' },
   6252   { { STATE_EPS4 }, 'i' },
   6253   { { STATE_EPS5 }, 'i' },
   6254   { { STATE_EPS6 }, 'i' },
   6255   { { STATE_EPS7 }, 'i' },
   6256   { { STATE_InOCDMode }, 'm' }
   6257 };
   6258 
   6259 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
   6260   { { OPERAND_s }, 'i' }
   6261 };
   6262 
   6263 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
   6264   { { STATE_PSEXCM }, 'i' },
   6265   { { STATE_PSRING }, 'i' },
   6266   { { STATE_PSINTLEVEL }, 'o' }
   6267 };
   6268 
   6269 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
   6270   { { OPERAND_art }, 'o' }
   6271 };
   6272 
   6273 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
   6274   { { STATE_PSEXCM }, 'i' },
   6275   { { STATE_PSRING }, 'i' },
   6276   { { STATE_INTERRUPT }, 'i' }
   6277 };
   6278 
   6279 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
   6280   { { OPERAND_art }, 'i' }
   6281 };
   6282 
   6283 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
   6284   { { STATE_PSEXCM }, 'i' },
   6285   { { STATE_PSRING }, 'i' },
   6286   { { STATE_XTSYNC }, 'o' },
   6287   { { STATE_INTERRUPT }, 'm' }
   6288 };
   6289 
   6290 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
   6291   { { OPERAND_art }, 'i' }
   6292 };
   6293 
   6294 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
   6295   { { STATE_PSEXCM }, 'i' },
   6296   { { STATE_PSRING }, 'i' },
   6297   { { STATE_XTSYNC }, 'o' },
   6298   { { STATE_INTERRUPT }, 'm' }
   6299 };
   6300 
   6301 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
   6302   { { OPERAND_art }, 'o' }
   6303 };
   6304 
   6305 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
   6306   { { STATE_PSEXCM }, 'i' },
   6307   { { STATE_PSRING }, 'i' },
   6308   { { STATE_INTENABLE }, 'i' }
   6309 };
   6310 
   6311 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
   6312   { { OPERAND_art }, 'i' }
   6313 };
   6314 
   6315 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
   6316   { { STATE_PSEXCM }, 'i' },
   6317   { { STATE_PSRING }, 'i' },
   6318   { { STATE_INTENABLE }, 'o' }
   6319 };
   6320 
   6321 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
   6322   { { OPERAND_art }, 'm' }
   6323 };
   6324 
   6325 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
   6326   { { STATE_PSEXCM }, 'i' },
   6327   { { STATE_PSRING }, 'i' },
   6328   { { STATE_INTENABLE }, 'm' }
   6329 };
   6330 
   6331 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
   6332   { { OPERAND_imms }, 'i' },
   6333   { { OPERAND_immt }, 'i' }
   6334 };
   6335 
   6336 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
   6337   { { STATE_PSEXCM }, 'i' },
   6338   { { STATE_PSINTLEVEL }, 'i' }
   6339 };
   6340 
   6341 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
   6342   { { OPERAND_imms }, 'i' }
   6343 };
   6344 
   6345 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
   6346   { { STATE_PSEXCM }, 'i' },
   6347   { { STATE_PSINTLEVEL }, 'i' }
   6348 };
   6349 
   6350 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
   6351   { { OPERAND_art }, 'o' }
   6352 };
   6353 
   6354 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
   6355   { { STATE_PSEXCM }, 'i' },
   6356   { { STATE_PSRING }, 'i' },
   6357   { { STATE_DBREAKA0 }, 'i' }
   6358 };
   6359 
   6360 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
   6361   { { OPERAND_art }, 'i' }
   6362 };
   6363 
   6364 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
   6365   { { STATE_PSEXCM }, 'i' },
   6366   { { STATE_PSRING }, 'i' },
   6367   { { STATE_DBREAKA0 }, 'o' },
   6368   { { STATE_XTSYNC }, 'o' }
   6369 };
   6370 
   6371 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
   6372   { { OPERAND_art }, 'm' }
   6373 };
   6374 
   6375 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
   6376   { { STATE_PSEXCM }, 'i' },
   6377   { { STATE_PSRING }, 'i' },
   6378   { { STATE_DBREAKA0 }, 'm' },
   6379   { { STATE_XTSYNC }, 'o' }
   6380 };
   6381 
   6382 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
   6383   { { OPERAND_art }, 'o' }
   6384 };
   6385 
   6386 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
   6387   { { STATE_PSEXCM }, 'i' },
   6388   { { STATE_PSRING }, 'i' },
   6389   { { STATE_DBREAKC0 }, 'i' }
   6390 };
   6391 
   6392 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
   6393   { { OPERAND_art }, 'i' }
   6394 };
   6395 
   6396 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
   6397   { { STATE_PSEXCM }, 'i' },
   6398   { { STATE_PSRING }, 'i' },
   6399   { { STATE_DBREAKC0 }, 'o' },
   6400   { { STATE_XTSYNC }, 'o' }
   6401 };
   6402 
   6403 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
   6404   { { OPERAND_art }, 'm' }
   6405 };
   6406 
   6407 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
   6408   { { STATE_PSEXCM }, 'i' },
   6409   { { STATE_PSRING }, 'i' },
   6410   { { STATE_DBREAKC0 }, 'm' },
   6411   { { STATE_XTSYNC }, 'o' }
   6412 };
   6413 
   6414 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
   6415   { { OPERAND_art }, 'o' }
   6416 };
   6417 
   6418 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
   6419   { { STATE_PSEXCM }, 'i' },
   6420   { { STATE_PSRING }, 'i' },
   6421   { { STATE_DBREAKA1 }, 'i' }
   6422 };
   6423 
   6424 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
   6425   { { OPERAND_art }, 'i' }
   6426 };
   6427 
   6428 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
   6429   { { STATE_PSEXCM }, 'i' },
   6430   { { STATE_PSRING }, 'i' },
   6431   { { STATE_DBREAKA1 }, 'o' },
   6432   { { STATE_XTSYNC }, 'o' }
   6433 };
   6434 
   6435 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
   6436   { { OPERAND_art }, 'm' }
   6437 };
   6438 
   6439 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
   6440   { { STATE_PSEXCM }, 'i' },
   6441   { { STATE_PSRING }, 'i' },
   6442   { { STATE_DBREAKA1 }, 'm' },
   6443   { { STATE_XTSYNC }, 'o' }
   6444 };
   6445 
   6446 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
   6447   { { OPERAND_art }, 'o' }
   6448 };
   6449 
   6450 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
   6451   { { STATE_PSEXCM }, 'i' },
   6452   { { STATE_PSRING }, 'i' },
   6453   { { STATE_DBREAKC1 }, 'i' }
   6454 };
   6455 
   6456 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
   6457   { { OPERAND_art }, 'i' }
   6458 };
   6459 
   6460 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
   6461   { { STATE_PSEXCM }, 'i' },
   6462   { { STATE_PSRING }, 'i' },
   6463   { { STATE_DBREAKC1 }, 'o' },
   6464   { { STATE_XTSYNC }, 'o' }
   6465 };
   6466 
   6467 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
   6468   { { OPERAND_art }, 'm' }
   6469 };
   6470 
   6471 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
   6472   { { STATE_PSEXCM }, 'i' },
   6473   { { STATE_PSRING }, 'i' },
   6474   { { STATE_DBREAKC1 }, 'm' },
   6475   { { STATE_XTSYNC }, 'o' }
   6476 };
   6477 
   6478 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
   6479   { { OPERAND_art }, 'o' }
   6480 };
   6481 
   6482 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
   6483   { { STATE_PSEXCM }, 'i' },
   6484   { { STATE_PSRING }, 'i' },
   6485   { { STATE_IBREAKA0 }, 'i' }
   6486 };
   6487 
   6488 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
   6489   { { OPERAND_art }, 'i' }
   6490 };
   6491 
   6492 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
   6493   { { STATE_PSEXCM }, 'i' },
   6494   { { STATE_PSRING }, 'i' },
   6495   { { STATE_IBREAKA0 }, 'o' }
   6496 };
   6497 
   6498 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
   6499   { { OPERAND_art }, 'm' }
   6500 };
   6501 
   6502 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
   6503   { { STATE_PSEXCM }, 'i' },
   6504   { { STATE_PSRING }, 'i' },
   6505   { { STATE_IBREAKA0 }, 'm' }
   6506 };
   6507 
   6508 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
   6509   { { OPERAND_art }, 'o' }
   6510 };
   6511 
   6512 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
   6513   { { STATE_PSEXCM }, 'i' },
   6514   { { STATE_PSRING }, 'i' },
   6515   { { STATE_IBREAKA1 }, 'i' }
   6516 };
   6517 
   6518 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
   6519   { { OPERAND_art }, 'i' }
   6520 };
   6521 
   6522 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
   6523   { { STATE_PSEXCM }, 'i' },
   6524   { { STATE_PSRING }, 'i' },
   6525   { { STATE_IBREAKA1 }, 'o' }
   6526 };
   6527 
   6528 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
   6529   { { OPERAND_art }, 'm' }
   6530 };
   6531 
   6532 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
   6533   { { STATE_PSEXCM }, 'i' },
   6534   { { STATE_PSRING }, 'i' },
   6535   { { STATE_IBREAKA1 }, 'm' }
   6536 };
   6537 
   6538 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
   6539   { { OPERAND_art }, 'o' }
   6540 };
   6541 
   6542 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
   6543   { { STATE_PSEXCM }, 'i' },
   6544   { { STATE_PSRING }, 'i' },
   6545   { { STATE_IBREAKENABLE }, 'i' }
   6546 };
   6547 
   6548 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
   6549   { { OPERAND_art }, 'i' }
   6550 };
   6551 
   6552 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
   6553   { { STATE_PSEXCM }, 'i' },
   6554   { { STATE_PSRING }, 'i' },
   6555   { { STATE_IBREAKENABLE }, 'o' }
   6556 };
   6557 
   6558 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
   6559   { { OPERAND_art }, 'm' }
   6560 };
   6561 
   6562 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
   6563   { { STATE_PSEXCM }, 'i' },
   6564   { { STATE_PSRING }, 'i' },
   6565   { { STATE_IBREAKENABLE }, 'm' }
   6566 };
   6567 
   6568 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
   6569   { { OPERAND_art }, 'o' }
   6570 };
   6571 
   6572 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
   6573   { { STATE_PSEXCM }, 'i' },
   6574   { { STATE_PSRING }, 'i' },
   6575   { { STATE_DEBUGCAUSE }, 'i' },
   6576   { { STATE_DBNUM }, 'i' }
   6577 };
   6578 
   6579 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
   6580   { { OPERAND_art }, 'i' }
   6581 };
   6582 
   6583 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
   6584   { { STATE_PSEXCM }, 'i' },
   6585   { { STATE_PSRING }, 'i' },
   6586   { { STATE_DEBUGCAUSE }, 'o' },
   6587   { { STATE_DBNUM }, 'o' }
   6588 };
   6589 
   6590 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
   6591   { { OPERAND_art }, 'm' }
   6592 };
   6593 
   6594 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
   6595   { { STATE_PSEXCM }, 'i' },
   6596   { { STATE_PSRING }, 'i' },
   6597   { { STATE_DEBUGCAUSE }, 'm' },
   6598   { { STATE_DBNUM }, 'm' }
   6599 };
   6600 
   6601 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
   6602   { { OPERAND_art }, 'o' }
   6603 };
   6604 
   6605 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
   6606   { { STATE_PSEXCM }, 'i' },
   6607   { { STATE_PSRING }, 'i' },
   6608   { { STATE_ICOUNT }, 'i' }
   6609 };
   6610 
   6611 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
   6612   { { OPERAND_art }, 'i' }
   6613 };
   6614 
   6615 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
   6616   { { STATE_PSEXCM }, 'i' },
   6617   { { STATE_PSRING }, 'i' },
   6618   { { STATE_XTSYNC }, 'o' },
   6619   { { STATE_ICOUNT }, 'o' }
   6620 };
   6621 
   6622 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
   6623   { { OPERAND_art }, 'm' }
   6624 };
   6625 
   6626 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
   6627   { { STATE_PSEXCM }, 'i' },
   6628   { { STATE_PSRING }, 'i' },
   6629   { { STATE_XTSYNC }, 'o' },
   6630   { { STATE_ICOUNT }, 'm' }
   6631 };
   6632 
   6633 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
   6634   { { OPERAND_art }, 'o' }
   6635 };
   6636 
   6637 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
   6638   { { STATE_PSEXCM }, 'i' },
   6639   { { STATE_PSRING }, 'i' },
   6640   { { STATE_ICOUNTLEVEL }, 'i' }
   6641 };
   6642 
   6643 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
   6644   { { OPERAND_art }, 'i' }
   6645 };
   6646 
   6647 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
   6648   { { STATE_PSEXCM }, 'i' },
   6649   { { STATE_PSRING }, 'i' },
   6650   { { STATE_ICOUNTLEVEL }, 'o' }
   6651 };
   6652 
   6653 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
   6654   { { OPERAND_art }, 'm' }
   6655 };
   6656 
   6657 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
   6658   { { STATE_PSEXCM }, 'i' },
   6659   { { STATE_PSRING }, 'i' },
   6660   { { STATE_ICOUNTLEVEL }, 'm' }
   6661 };
   6662 
   6663 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
   6664   { { OPERAND_art }, 'o' }
   6665 };
   6666 
   6667 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
   6668   { { STATE_PSEXCM }, 'i' },
   6669   { { STATE_PSRING }, 'i' },
   6670   { { STATE_DDR }, 'i' }
   6671 };
   6672 
   6673 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
   6674   { { OPERAND_art }, 'i' }
   6675 };
   6676 
   6677 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
   6678   { { STATE_PSEXCM }, 'i' },
   6679   { { STATE_PSRING }, 'i' },
   6680   { { STATE_XTSYNC }, 'o' },
   6681   { { STATE_DDR }, 'o' }
   6682 };
   6683 
   6684 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
   6685   { { OPERAND_art }, 'm' }
   6686 };
   6687 
   6688 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
   6689   { { STATE_PSEXCM }, 'i' },
   6690   { { STATE_PSRING }, 'i' },
   6691   { { STATE_XTSYNC }, 'o' },
   6692   { { STATE_DDR }, 'm' }
   6693 };
   6694 
   6695 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_args[] = {
   6696   { { OPERAND_ars }, 'm' }
   6697 };
   6698 
   6699 static xtensa_arg_internal Iclass_xt_iclass_lddr32_p_stateArgs[] = {
   6700   { { STATE_PSEXCM }, 'i' },
   6701   { { STATE_PSRING }, 'i' },
   6702   { { STATE_XTSYNC }, 'o' },
   6703   { { STATE_InOCDMode }, 'i' },
   6704   { { STATE_DDR }, 'o' }
   6705 };
   6706 
   6707 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_args[] = {
   6708   { { OPERAND_ars }, 'm' }
   6709 };
   6710 
   6711 static xtensa_arg_internal Iclass_xt_iclass_sddr32_p_stateArgs[] = {
   6712   { { STATE_PSEXCM }, 'i' },
   6713   { { STATE_PSRING }, 'i' },
   6714   { { STATE_InOCDMode }, 'i' },
   6715   { { STATE_DDR }, 'i' }
   6716 };
   6717 
   6718 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
   6719   { { OPERAND_imms }, 'i' }
   6720 };
   6721 
   6722 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
   6723   { { STATE_InOCDMode }, 'm' },
   6724   { { STATE_EPC6 }, 'i' },
   6725   { { STATE_PSWOE }, 'o' },
   6726   { { STATE_PSCALLINC }, 'o' },
   6727   { { STATE_PSOWB }, 'o' },
   6728   { { STATE_PSRING }, 'o' },
   6729   { { STATE_PSUM }, 'o' },
   6730   { { STATE_PSEXCM }, 'o' },
   6731   { { STATE_PSINTLEVEL }, 'o' },
   6732   { { STATE_EPS6 }, 'i' }
   6733 };
   6734 
   6735 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
   6736   { { STATE_InOCDMode }, 'm' },
   6737   { { STATE_VECBASE }, 'i' }
   6738 };
   6739 
   6740 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
   6741   { { OPERAND_art }, 'i' }
   6742 };
   6743 
   6744 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
   6745   { { STATE_PSEXCM }, 'i' },
   6746   { { STATE_PSRING }, 'i' },
   6747   { { STATE_XTSYNC }, 'o' }
   6748 };
   6749 
   6750 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
   6751   { { OPERAND_br }, 'o' },
   6752   { { OPERAND_bs }, 'i' },
   6753   { { OPERAND_bt }, 'i' }
   6754 };
   6755 
   6756 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
   6757   { { OPERAND_bt }, 'o' },
   6758   { { OPERAND_bs4 }, 'i' }
   6759 };
   6760 
   6761 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
   6762   { { OPERAND_bt }, 'o' },
   6763   { { OPERAND_bs8 }, 'i' }
   6764 };
   6765 
   6766 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
   6767   { { OPERAND_bs }, 'i' },
   6768   { { OPERAND_label8 }, 'i' }
   6769 };
   6770 
   6771 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
   6772   { { OPERAND_arr }, 'm' },
   6773   { { OPERAND_ars }, 'i' },
   6774   { { OPERAND_bt }, 'i' }
   6775 };
   6776 
   6777 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
   6778   { { OPERAND_art }, 'o' },
   6779   { { OPERAND_brall }, 'i' }
   6780 };
   6781 
   6782 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
   6783   { { OPERAND_art }, 'i' },
   6784   { { OPERAND_brall }, 'o' }
   6785 };
   6786 
   6787 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
   6788   { { OPERAND_art }, 'm' },
   6789   { { OPERAND_brall }, 'm' }
   6790 };
   6791 
   6792 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
   6793   { { OPERAND_art }, 'o' }
   6794 };
   6795 
   6796 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
   6797   { { STATE_PSEXCM }, 'i' },
   6798   { { STATE_PSRING }, 'i' },
   6799   { { STATE_CCOUNT }, 'i' }
   6800 };
   6801 
   6802 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
   6803   { { OPERAND_art }, 'i' }
   6804 };
   6805 
   6806 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
   6807   { { STATE_PSEXCM }, 'i' },
   6808   { { STATE_PSRING }, 'i' },
   6809   { { STATE_XTSYNC }, 'o' },
   6810   { { STATE_CCOUNT }, 'o' }
   6811 };
   6812 
   6813 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
   6814   { { OPERAND_art }, 'm' }
   6815 };
   6816 
   6817 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
   6818   { { STATE_PSEXCM }, 'i' },
   6819   { { STATE_PSRING }, 'i' },
   6820   { { STATE_XTSYNC }, 'o' },
   6821   { { STATE_CCOUNT }, 'm' }
   6822 };
   6823 
   6824 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
   6825   { { OPERAND_art }, 'o' }
   6826 };
   6827 
   6828 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
   6829   { { STATE_PSEXCM }, 'i' },
   6830   { { STATE_PSRING }, 'i' },
   6831   { { STATE_CCOMPARE0 }, 'i' }
   6832 };
   6833 
   6834 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
   6835   { { OPERAND_art }, 'i' }
   6836 };
   6837 
   6838 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
   6839   { { STATE_PSEXCM }, 'i' },
   6840   { { STATE_PSRING }, 'i' },
   6841   { { STATE_CCOMPARE0 }, 'o' },
   6842   { { STATE_INTERRUPT }, 'm' }
   6843 };
   6844 
   6845 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
   6846   { { OPERAND_art }, 'm' }
   6847 };
   6848 
   6849 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
   6850   { { STATE_PSEXCM }, 'i' },
   6851   { { STATE_PSRING }, 'i' },
   6852   { { STATE_CCOMPARE0 }, 'm' },
   6853   { { STATE_INTERRUPT }, 'm' }
   6854 };
   6855 
   6856 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
   6857   { { OPERAND_art }, 'o' }
   6858 };
   6859 
   6860 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
   6861   { { STATE_PSEXCM }, 'i' },
   6862   { { STATE_PSRING }, 'i' },
   6863   { { STATE_CCOMPARE1 }, 'i' }
   6864 };
   6865 
   6866 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
   6867   { { OPERAND_art }, 'i' }
   6868 };
   6869 
   6870 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
   6871   { { STATE_PSEXCM }, 'i' },
   6872   { { STATE_PSRING }, 'i' },
   6873   { { STATE_CCOMPARE1 }, 'o' },
   6874   { { STATE_INTERRUPT }, 'm' }
   6875 };
   6876 
   6877 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
   6878   { { OPERAND_art }, 'm' }
   6879 };
   6880 
   6881 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
   6882   { { STATE_PSEXCM }, 'i' },
   6883   { { STATE_PSRING }, 'i' },
   6884   { { STATE_CCOMPARE1 }, 'm' },
   6885   { { STATE_INTERRUPT }, 'm' }
   6886 };
   6887 
   6888 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
   6889   { { OPERAND_art }, 'o' }
   6890 };
   6891 
   6892 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
   6893   { { STATE_PSEXCM }, 'i' },
   6894   { { STATE_PSRING }, 'i' },
   6895   { { STATE_CCOMPARE2 }, 'i' }
   6896 };
   6897 
   6898 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
   6899   { { OPERAND_art }, 'i' }
   6900 };
   6901 
   6902 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
   6903   { { STATE_PSEXCM }, 'i' },
   6904   { { STATE_PSRING }, 'i' },
   6905   { { STATE_CCOMPARE2 }, 'o' },
   6906   { { STATE_INTERRUPT }, 'm' }
   6907 };
   6908 
   6909 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
   6910   { { OPERAND_art }, 'm' }
   6911 };
   6912 
   6913 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
   6914   { { STATE_PSEXCM }, 'i' },
   6915   { { STATE_PSRING }, 'i' },
   6916   { { STATE_CCOMPARE2 }, 'm' },
   6917   { { STATE_INTERRUPT }, 'm' }
   6918 };
   6919 
   6920 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
   6921   { { OPERAND_ars }, 'i' },
   6922   { { OPERAND_uimm8x4 }, 'i' }
   6923 };
   6924 
   6925 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
   6926   { { OPERAND_ars }, 'i' },
   6927   { { OPERAND_uimm4x16 }, 'i' }
   6928 };
   6929 
   6930 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
   6931   { { STATE_PSEXCM }, 'i' },
   6932   { { STATE_PSRING }, 'i' }
   6933 };
   6934 
   6935 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
   6936   { { OPERAND_ars }, 'i' },
   6937   { { OPERAND_uimm8x4 }, 'i' }
   6938 };
   6939 
   6940 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
   6941   { { STATE_PSEXCM }, 'i' },
   6942   { { STATE_PSRING }, 'i' }
   6943 };
   6944 
   6945 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
   6946   { { OPERAND_art }, 'o' },
   6947   { { OPERAND_ars }, 'i' }
   6948 };
   6949 
   6950 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
   6951   { { STATE_PSEXCM }, 'i' },
   6952   { { STATE_PSRING }, 'i' }
   6953 };
   6954 
   6955 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
   6956   { { OPERAND_art }, 'i' },
   6957   { { OPERAND_ars }, 'i' }
   6958 };
   6959 
   6960 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
   6961   { { STATE_PSEXCM }, 'i' },
   6962   { { STATE_PSRING }, 'i' }
   6963 };
   6964 
   6965 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
   6966   { { OPERAND_ars }, 'i' },
   6967   { { OPERAND_uimm8x4 }, 'i' }
   6968 };
   6969 
   6970 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_args[] = {
   6971   { { OPERAND_ars }, 'm' }
   6972 };
   6973 
   6974 static xtensa_arg_internal Iclass_xt_iclass_dcache_dyn_stateArgs[] = {
   6975   { { STATE_PSEXCM }, 'i' },
   6976   { { STATE_PSRING }, 'i' }
   6977 };
   6978 
   6979 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
   6980   { { OPERAND_ars }, 'i' },
   6981   { { OPERAND_uimm4x16 }, 'i' }
   6982 };
   6983 
   6984 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
   6985   { { STATE_PSEXCM }, 'i' },
   6986   { { STATE_PSRING }, 'i' }
   6987 };
   6988 
   6989 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
   6990   { { OPERAND_ars }, 'i' },
   6991   { { OPERAND_uimm8x4 }, 'i' }
   6992 };
   6993 
   6994 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
   6995   { { STATE_PSEXCM }, 'i' },
   6996   { { STATE_PSRING }, 'i' }
   6997 };
   6998 
   6999 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
   7000   { { OPERAND_ars }, 'i' },
   7001   { { OPERAND_uimm8x4 }, 'i' }
   7002 };
   7003 
   7004 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
   7005   { { OPERAND_ars }, 'i' },
   7006   { { OPERAND_uimm4x16 }, 'i' }
   7007 };
   7008 
   7009 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
   7010   { { STATE_PSEXCM }, 'i' },
   7011   { { STATE_PSRING }, 'i' }
   7012 };
   7013 
   7014 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
   7015   { { OPERAND_art }, 'i' },
   7016   { { OPERAND_ars }, 'i' }
   7017 };
   7018 
   7019 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
   7020   { { STATE_PSEXCM }, 'i' },
   7021   { { STATE_PSRING }, 'i' }
   7022 };
   7023 
   7024 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
   7025   { { OPERAND_art }, 'o' },
   7026   { { OPERAND_ars }, 'i' }
   7027 };
   7028 
   7029 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
   7030   { { STATE_PSEXCM }, 'i' },
   7031   { { STATE_PSRING }, 'i' }
   7032 };
   7033 
   7034 static xtensa_arg_internal Iclass_xt_iclass_sdcw_args[] = {
   7035   { { OPERAND_art }, 'i' },
   7036   { { OPERAND_ars }, 'i' }
   7037 };
   7038 
   7039 static xtensa_arg_internal Iclass_xt_iclass_sdcw_stateArgs[] = {
   7040   { { STATE_PSEXCM }, 'i' },
   7041   { { STATE_PSRING }, 'i' }
   7042 };
   7043 
   7044 static xtensa_arg_internal Iclass_xt_iclass_ldcw_args[] = {
   7045   { { OPERAND_art }, 'o' },
   7046   { { OPERAND_ars }, 'i' }
   7047 };
   7048 
   7049 static xtensa_arg_internal Iclass_xt_iclass_ldcw_stateArgs[] = {
   7050   { { STATE_PSEXCM }, 'i' },
   7051   { { STATE_PSRING }, 'i' }
   7052 };
   7053 
   7054 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
   7055   { { OPERAND_art }, 'i' }
   7056 };
   7057 
   7058 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
   7059   { { STATE_PSEXCM }, 'i' },
   7060   { { STATE_PSRING }, 'i' },
   7061   { { STATE_PTBASE }, 'o' },
   7062   { { STATE_XTSYNC }, 'o' }
   7063 };
   7064 
   7065 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
   7066   { { OPERAND_art }, 'o' }
   7067 };
   7068 
   7069 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
   7070   { { STATE_PSEXCM }, 'i' },
   7071   { { STATE_PSRING }, 'i' },
   7072   { { STATE_PTBASE }, 'i' },
   7073   { { STATE_EXCVADDR }, 'i' }
   7074 };
   7075 
   7076 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
   7077   { { OPERAND_art }, 'm' }
   7078 };
   7079 
   7080 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
   7081   { { STATE_PSEXCM }, 'i' },
   7082   { { STATE_PSRING }, 'i' },
   7083   { { STATE_PTBASE }, 'm' },
   7084   { { STATE_EXCVADDR }, 'i' },
   7085   { { STATE_XTSYNC }, 'o' }
   7086 };
   7087 
   7088 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
   7089   { { OPERAND_art }, 'o' }
   7090 };
   7091 
   7092 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
   7093   { { STATE_PSEXCM }, 'i' },
   7094   { { STATE_PSRING }, 'i' },
   7095   { { STATE_ASID3 }, 'i' },
   7096   { { STATE_ASID2 }, 'i' },
   7097   { { STATE_ASID1 }, 'i' }
   7098 };
   7099 
   7100 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
   7101   { { OPERAND_art }, 'i' }
   7102 };
   7103 
   7104 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
   7105   { { STATE_XTSYNC }, 'o' },
   7106   { { STATE_PSEXCM }, 'i' },
   7107   { { STATE_PSRING }, 'i' },
   7108   { { STATE_ASID3 }, 'o' },
   7109   { { STATE_ASID2 }, 'o' },
   7110   { { STATE_ASID1 }, 'o' }
   7111 };
   7112 
   7113 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
   7114   { { OPERAND_art }, 'm' }
   7115 };
   7116 
   7117 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
   7118   { { STATE_XTSYNC }, 'o' },
   7119   { { STATE_PSEXCM }, 'i' },
   7120   { { STATE_PSRING }, 'i' },
   7121   { { STATE_ASID3 }, 'm' },
   7122   { { STATE_ASID2 }, 'm' },
   7123   { { STATE_ASID1 }, 'm' }
   7124 };
   7125 
   7126 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
   7127   { { OPERAND_art }, 'o' }
   7128 };
   7129 
   7130 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
   7131   { { STATE_PSEXCM }, 'i' },
   7132   { { STATE_PSRING }, 'i' },
   7133   { { STATE_INSTPGSZID6 }, 'i' },
   7134   { { STATE_INSTPGSZID5 }, 'i' },
   7135   { { STATE_INSTPGSZID4 }, 'i' }
   7136 };
   7137 
   7138 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
   7139   { { OPERAND_art }, 'i' }
   7140 };
   7141 
   7142 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
   7143   { { STATE_XTSYNC }, 'o' },
   7144   { { STATE_PSEXCM }, 'i' },
   7145   { { STATE_PSRING }, 'i' },
   7146   { { STATE_INSTPGSZID6 }, 'o' },
   7147   { { STATE_INSTPGSZID5 }, 'o' },
   7148   { { STATE_INSTPGSZID4 }, 'o' }
   7149 };
   7150 
   7151 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
   7152   { { OPERAND_art }, 'm' }
   7153 };
   7154 
   7155 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
   7156   { { STATE_XTSYNC }, 'o' },
   7157   { { STATE_PSEXCM }, 'i' },
   7158   { { STATE_PSRING }, 'i' },
   7159   { { STATE_INSTPGSZID6 }, 'm' },
   7160   { { STATE_INSTPGSZID5 }, 'm' },
   7161   { { STATE_INSTPGSZID4 }, 'm' }
   7162 };
   7163 
   7164 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
   7165   { { OPERAND_art }, 'o' }
   7166 };
   7167 
   7168 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
   7169   { { STATE_PSEXCM }, 'i' },
   7170   { { STATE_PSRING }, 'i' },
   7171   { { STATE_DATAPGSZID6 }, 'i' },
   7172   { { STATE_DATAPGSZID5 }, 'i' },
   7173   { { STATE_DATAPGSZID4 }, 'i' }
   7174 };
   7175 
   7176 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
   7177   { { OPERAND_art }, 'i' }
   7178 };
   7179 
   7180 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
   7181   { { STATE_XTSYNC }, 'o' },
   7182   { { STATE_PSEXCM }, 'i' },
   7183   { { STATE_PSRING }, 'i' },
   7184   { { STATE_DATAPGSZID6 }, 'o' },
   7185   { { STATE_DATAPGSZID5 }, 'o' },
   7186   { { STATE_DATAPGSZID4 }, 'o' }
   7187 };
   7188 
   7189 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
   7190   { { OPERAND_art }, 'm' }
   7191 };
   7192 
   7193 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
   7194   { { STATE_XTSYNC }, 'o' },
   7195   { { STATE_PSEXCM }, 'i' },
   7196   { { STATE_PSRING }, 'i' },
   7197   { { STATE_DATAPGSZID6 }, 'm' },
   7198   { { STATE_DATAPGSZID5 }, 'm' },
   7199   { { STATE_DATAPGSZID4 }, 'm' }
   7200 };
   7201 
   7202 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
   7203   { { OPERAND_ars }, 'i' }
   7204 };
   7205 
   7206 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
   7207   { { STATE_PSEXCM }, 'i' },
   7208   { { STATE_PSRING }, 'i' },
   7209   { { STATE_XTSYNC }, 'o' }
   7210 };
   7211 
   7212 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
   7213   { { OPERAND_art }, 'o' },
   7214   { { OPERAND_ars }, 'i' }
   7215 };
   7216 
   7217 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
   7218   { { STATE_PSEXCM }, 'i' },
   7219   { { STATE_PSRING }, 'i' }
   7220 };
   7221 
   7222 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
   7223   { { OPERAND_art }, 'i' },
   7224   { { OPERAND_ars }, 'i' }
   7225 };
   7226 
   7227 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
   7228   { { STATE_PSEXCM }, 'i' },
   7229   { { STATE_PSRING }, 'i' },
   7230   { { STATE_XTSYNC }, 'o' }
   7231 };
   7232 
   7233 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
   7234   { { OPERAND_ars }, 'i' }
   7235 };
   7236 
   7237 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
   7238   { { STATE_PSEXCM }, 'i' },
   7239   { { STATE_PSRING }, 'i' }
   7240 };
   7241 
   7242 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
   7243   { { OPERAND_art }, 'o' },
   7244   { { OPERAND_ars }, 'i' }
   7245 };
   7246 
   7247 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
   7248   { { STATE_PSEXCM }, 'i' },
   7249   { { STATE_PSRING }, 'i' }
   7250 };
   7251 
   7252 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
   7253   { { OPERAND_art }, 'i' },
   7254   { { OPERAND_ars }, 'i' }
   7255 };
   7256 
   7257 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
   7258   { { STATE_PSEXCM }, 'i' },
   7259   { { STATE_PSRING }, 'i' }
   7260 };
   7261 
   7262 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
   7263   { { STATE_PTBASE }, 'i' },
   7264   { { STATE_EXCVADDR }, 'i' }
   7265 };
   7266 
   7267 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
   7268   { { STATE_EXCVADDR }, 'i' }
   7269 };
   7270 
   7271 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
   7272   { { STATE_EXCVADDR }, 'i' }
   7273 };
   7274 
   7275 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
   7276   { { OPERAND_art }, 'o' }
   7277 };
   7278 
   7279 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
   7280   { { STATE_PSEXCM }, 'i' },
   7281   { { STATE_PSRING }, 'i' },
   7282   { { STATE_CPENABLE }, 'i' }
   7283 };
   7284 
   7285 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
   7286   { { OPERAND_art }, 'i' }
   7287 };
   7288 
   7289 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
   7290   { { STATE_PSEXCM }, 'i' },
   7291   { { STATE_PSRING }, 'i' },
   7292   { { STATE_CPENABLE }, 'o' }
   7293 };
   7294 
   7295 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
   7296   { { OPERAND_art }, 'm' }
   7297 };
   7298 
   7299 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
   7300   { { STATE_PSEXCM }, 'i' },
   7301   { { STATE_PSRING }, 'i' },
   7302   { { STATE_CPENABLE }, 'm' }
   7303 };
   7304 
   7305 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
   7306   { { OPERAND_arr }, 'o' },
   7307   { { OPERAND_ars }, 'i' },
   7308   { { OPERAND_tp7 }, 'i' }
   7309 };
   7310 
   7311 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
   7312   { { OPERAND_arr }, 'o' },
   7313   { { OPERAND_ars }, 'i' },
   7314   { { OPERAND_art }, 'i' }
   7315 };
   7316 
   7317 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
   7318   { { OPERAND_art }, 'o' },
   7319   { { OPERAND_ars }, 'i' }
   7320 };
   7321 
   7322 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
   7323   { { OPERAND_arr }, 'o' },
   7324   { { OPERAND_ars }, 'i' },
   7325   { { OPERAND_tp7 }, 'i' }
   7326 };
   7327 
   7328 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
   7329   { { OPERAND_art }, 'o' },
   7330   { { OPERAND_ars }, 'i' },
   7331   { { OPERAND_uimm8x4 }, 'i' }
   7332 };
   7333 
   7334 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
   7335   { { OPERAND_art }, 'i' },
   7336   { { OPERAND_ars }, 'i' },
   7337   { { OPERAND_uimm8x4 }, 'i' }
   7338 };
   7339 
   7340 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
   7341   { { OPERAND_art }, 'm' },
   7342   { { OPERAND_ars }, 'i' },
   7343   { { OPERAND_uimm8x4 }, 'i' }
   7344 };
   7345 
   7346 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
   7347   { { STATE_SCOMPARE1 }, 'i' },
   7348   { { STATE_XTSYNC }, 'i' },
   7349   { { STATE_SCOMPARE1 }, 'i' }
   7350 };
   7351 
   7352 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
   7353   { { OPERAND_art }, 'o' }
   7354 };
   7355 
   7356 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
   7357   { { STATE_SCOMPARE1 }, 'i' }
   7358 };
   7359 
   7360 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
   7361   { { OPERAND_art }, 'i' }
   7362 };
   7363 
   7364 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
   7365   { { STATE_SCOMPARE1 }, 'o' }
   7366 };
   7367 
   7368 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
   7369   { { OPERAND_art }, 'm' }
   7370 };
   7371 
   7372 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
   7373   { { STATE_SCOMPARE1 }, 'm' }
   7374 };
   7375 
   7376 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
   7377   { { OPERAND_art }, 'o' }
   7378 };
   7379 
   7380 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
   7381   { { STATE_PSEXCM }, 'i' },
   7382   { { STATE_PSRING }, 'i' },
   7383   { { STATE_ATOMCTL }, 'i' }
   7384 };
   7385 
   7386 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
   7387   { { OPERAND_art }, 'i' }
   7388 };
   7389 
   7390 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
   7391   { { STATE_PSEXCM }, 'i' },
   7392   { { STATE_PSRING }, 'i' },
   7393   { { STATE_ATOMCTL }, 'o' },
   7394   { { STATE_XTSYNC }, 'o' }
   7395 };
   7396 
   7397 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
   7398   { { OPERAND_art }, 'm' }
   7399 };
   7400 
   7401 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
   7402   { { STATE_PSEXCM }, 'i' },
   7403   { { STATE_PSRING }, 'i' },
   7404   { { STATE_ATOMCTL }, 'm' },
   7405   { { STATE_XTSYNC }, 'o' }
   7406 };
   7407 
   7408 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
   7409   { { OPERAND_arr }, 'o' },
   7410   { { OPERAND_ars }, 'i' },
   7411   { { OPERAND_art }, 'i' }
   7412 };
   7413 
   7414 static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_args[] = {
   7415   { { OPERAND_art }, 'o' }
   7416 };
   7417 
   7418 static xtensa_arg_internal Iclass_xt_iclass_rsr_eraccess_stateArgs[] = {
   7419   { { STATE_PSEXCM }, 'i' },
   7420   { { STATE_PSRING }, 'i' },
   7421   { { STATE_ERACCESS }, 'i' }
   7422 };
   7423 
   7424 static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_args[] = {
   7425   { { OPERAND_art }, 'i' }
   7426 };
   7427 
   7428 static xtensa_arg_internal Iclass_xt_iclass_wsr_eraccess_stateArgs[] = {
   7429   { { STATE_PSEXCM }, 'i' },
   7430   { { STATE_PSRING }, 'i' },
   7431   { { STATE_ERACCESS }, 'o' }
   7432 };
   7433 
   7434 static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_args[] = {
   7435   { { OPERAND_art }, 'm' }
   7436 };
   7437 
   7438 static xtensa_arg_internal Iclass_xt_iclass_xsr_eraccess_stateArgs[] = {
   7439   { { STATE_PSEXCM }, 'i' },
   7440   { { STATE_PSRING }, 'i' },
   7441   { { STATE_ERACCESS }, 'm' }
   7442 };
   7443 
   7444 static xtensa_arg_internal Iclass_xt_iclass_rer_args[] = {
   7445   { { OPERAND_art }, 'o' },
   7446   { { OPERAND_ars }, 'i' }
   7447 };
   7448 
   7449 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
   7450   { { STATE_ERACCESS }, 'i' },
   7451   { { STATE_PSEXCM }, 'i' },
   7452   { { STATE_PSRING }, 'i' }
   7453 };
   7454 
   7455 static xtensa_arg_internal Iclass_xt_iclass_wer_args[] = {
   7456   { { OPERAND_art }, 'i' },
   7457   { { OPERAND_ars }, 'i' }
   7458 };
   7459 
   7460 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
   7461   { { STATE_ERACCESS }, 'i' },
   7462   { { STATE_PSEXCM }, 'i' },
   7463   { { STATE_PSRING }, 'i' }
   7464 };
   7465 
   7466 static xtensa_arg_internal Iclass_rur_fcr_args[] = {
   7467   { { OPERAND_arr }, 'o' }
   7468 };
   7469 
   7470 static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
   7471   { { STATE_RoundMode }, 'i' },
   7472   { { STATE_InvalidEnable }, 'i' },
   7473   { { STATE_DivZeroEnable }, 'i' },
   7474   { { STATE_OverflowEnable }, 'i' },
   7475   { { STATE_UnderflowEnable }, 'i' },
   7476   { { STATE_InexactEnable }, 'i' },
   7477   { { STATE_FPreserved20 }, 'i' },
   7478   { { STATE_FPreserved5 }, 'i' },
   7479   { { STATE_CPENABLE }, 'i' }
   7480 };
   7481 
   7482 static xtensa_arg_internal Iclass_wur_fcr_args[] = {
   7483   { { OPERAND_art }, 'i' }
   7484 };
   7485 
   7486 static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
   7487   { { STATE_RoundMode }, 'o' },
   7488   { { STATE_InvalidEnable }, 'o' },
   7489   { { STATE_DivZeroEnable }, 'o' },
   7490   { { STATE_OverflowEnable }, 'o' },
   7491   { { STATE_UnderflowEnable }, 'o' },
   7492   { { STATE_InexactEnable }, 'o' },
   7493   { { STATE_FPreserved20 }, 'o' },
   7494   { { STATE_FPreserved5 }, 'o' },
   7495   { { STATE_CPENABLE }, 'i' }
   7496 };
   7497 
   7498 static xtensa_arg_internal Iclass_rur_fsr_args[] = {
   7499   { { OPERAND_arr }, 'o' }
   7500 };
   7501 
   7502 static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
   7503   { { STATE_InvalidFlag }, 'i' },
   7504   { { STATE_DivZeroFlag }, 'i' },
   7505   { { STATE_OverflowFlag }, 'i' },
   7506   { { STATE_UnderflowFlag }, 'i' },
   7507   { { STATE_InexactFlag }, 'i' },
   7508   { { STATE_FPreserved20a }, 'i' },
   7509   { { STATE_FPreserved7 }, 'i' },
   7510   { { STATE_CPENABLE }, 'i' }
   7511 };
   7512 
   7513 static xtensa_arg_internal Iclass_wur_fsr_args[] = {
   7514   { { OPERAND_art }, 'i' }
   7515 };
   7516 
   7517 static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
   7518   { { STATE_InvalidFlag }, 'o' },
   7519   { { STATE_DivZeroFlag }, 'o' },
   7520   { { STATE_OverflowFlag }, 'o' },
   7521   { { STATE_UnderflowFlag }, 'o' },
   7522   { { STATE_InexactFlag }, 'o' },
   7523   { { STATE_FPreserved20a }, 'o' },
   7524   { { STATE_FPreserved7 }, 'o' },
   7525   { { STATE_CPENABLE }, 'i' }
   7526 };
   7527 
   7528 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
   7529   { { OPERAND_art }, 'o' }
   7530 };
   7531 
   7532 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
   7533   { { STATE_CPENABLE }, 'i' }
   7534 };
   7535 
   7536 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
   7537   INTERFACE_IMPWIRE
   7538 };
   7539 
   7540 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
   7541   { { OPERAND_bitindex }, 'i' }
   7542 };
   7543 
   7544 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
   7545   { { STATE_EXPSTATE }, 'm' },
   7546   { { STATE_CPENABLE }, 'i' }
   7547 };
   7548 
   7549 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
   7550   { { OPERAND_bitindex }, 'i' }
   7551 };
   7552 
   7553 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
   7554   { { STATE_EXPSTATE }, 'm' },
   7555   { { STATE_CPENABLE }, 'i' }
   7556 };
   7557 
   7558 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
   7559   { { OPERAND_art }, 'i' },
   7560   { { OPERAND_ars }, 'i' }
   7561 };
   7562 
   7563 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
   7564   { { STATE_EXPSTATE }, 'm' },
   7565   { { STATE_CPENABLE }, 'i' }
   7566 };
   7567 
   7568 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
   7569   { { OPERAND_arr }, 'o' }
   7570 };
   7571 
   7572 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
   7573   { { STATE_EXPSTATE }, 'i' },
   7574   { { STATE_CPENABLE }, 'i' }
   7575 };
   7576 
   7577 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
   7578   { { OPERAND_art }, 'i' }
   7579 };
   7580 
   7581 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
   7582   { { STATE_EXPSTATE }, 'o' },
   7583   { { STATE_CPENABLE }, 'i' }
   7584 };
   7585 
   7586 static xtensa_arg_internal Iclass_LSI_args[] = {
   7587   { { OPERAND_frt }, 'o' },
   7588   { { OPERAND_ars }, 'i' },
   7589   { { OPERAND_imm8x4 }, 'i' }
   7590 };
   7591 
   7592 static xtensa_arg_internal Iclass_LSI_stateArgs[] = {
   7593   { { STATE_CPENABLE }, 'i' }
   7594 };
   7595 
   7596 static xtensa_arg_internal Iclass_LSIP_args[] = {
   7597   { { OPERAND_frt }, 'o' },
   7598   { { OPERAND_ars }, 'm' },
   7599   { { OPERAND_imm8x4 }, 'i' }
   7600 };
   7601 
   7602 static xtensa_arg_internal Iclass_LSIP_stateArgs[] = {
   7603   { { STATE_CPENABLE }, 'i' }
   7604 };
   7605 
   7606 static xtensa_arg_internal Iclass_LSX_args[] = {
   7607   { { OPERAND_frr }, 'o' },
   7608   { { OPERAND_ars }, 'i' },
   7609   { { OPERAND_art }, 'i' }
   7610 };
   7611 
   7612 static xtensa_arg_internal Iclass_LSX_stateArgs[] = {
   7613   { { STATE_CPENABLE }, 'i' }
   7614 };
   7615 
   7616 static xtensa_arg_internal Iclass_LSXP_args[] = {
   7617   { { OPERAND_frr }, 'o' },
   7618   { { OPERAND_ars }, 'm' },
   7619   { { OPERAND_art }, 'i' }
   7620 };
   7621 
   7622 static xtensa_arg_internal Iclass_LSXP_stateArgs[] = {
   7623   { { STATE_CPENABLE }, 'i' }
   7624 };
   7625 
   7626 static xtensa_arg_internal Iclass_SSI_args[] = {
   7627   { { OPERAND_frt }, 'i' },
   7628   { { OPERAND_ars }, 'i' },
   7629   { { OPERAND_imm8x4 }, 'i' }
   7630 };
   7631 
   7632 static xtensa_arg_internal Iclass_SSI_stateArgs[] = {
   7633   { { STATE_CPENABLE }, 'i' }
   7634 };
   7635 
   7636 static xtensa_arg_internal Iclass_SSIP_args[] = {
   7637   { { OPERAND_frt }, 'i' },
   7638   { { OPERAND_ars }, 'm' },
   7639   { { OPERAND_imm8x4 }, 'i' }
   7640 };
   7641 
   7642 static xtensa_arg_internal Iclass_SSIP_stateArgs[] = {
   7643   { { STATE_CPENABLE }, 'i' }
   7644 };
   7645 
   7646 static xtensa_arg_internal Iclass_SSX_args[] = {
   7647   { { OPERAND_frr }, 'i' },
   7648   { { OPERAND_ars }, 'i' },
   7649   { { OPERAND_art }, 'i' }
   7650 };
   7651 
   7652 static xtensa_arg_internal Iclass_SSX_stateArgs[] = {
   7653   { { STATE_CPENABLE }, 'i' }
   7654 };
   7655 
   7656 static xtensa_arg_internal Iclass_SSXP_args[] = {
   7657   { { OPERAND_frr }, 'i' },
   7658   { { OPERAND_ars }, 'm' },
   7659   { { OPERAND_art }, 'i' }
   7660 };
   7661 
   7662 static xtensa_arg_internal Iclass_SSXP_stateArgs[] = {
   7663   { { STATE_CPENABLE }, 'i' }
   7664 };
   7665 
   7666 static xtensa_arg_internal Iclass_LDI_args[] = {
   7667   { { OPERAND_frt }, 'o' },
   7668   { { OPERAND_ars }, 'i' },
   7669   { { OPERAND_imm8x8 }, 'i' }
   7670 };
   7671 
   7672 static xtensa_arg_internal Iclass_LDI_stateArgs[] = {
   7673   { { STATE_CPENABLE }, 'i' }
   7674 };
   7675 
   7676 static xtensa_arg_internal Iclass_LDIP_args[] = {
   7677   { { OPERAND_frt }, 'o' },
   7678   { { OPERAND_ars }, 'm' },
   7679   { { OPERAND_imm8x8 }, 'i' }
   7680 };
   7681 
   7682 static xtensa_arg_internal Iclass_LDIP_stateArgs[] = {
   7683   { { STATE_CPENABLE }, 'i' }
   7684 };
   7685 
   7686 static xtensa_arg_internal Iclass_LDX_args[] = {
   7687   { { OPERAND_frr }, 'o' },
   7688   { { OPERAND_ars }, 'i' },
   7689   { { OPERAND_art }, 'i' }
   7690 };
   7691 
   7692 static xtensa_arg_internal Iclass_LDX_stateArgs[] = {
   7693   { { STATE_CPENABLE }, 'i' }
   7694 };
   7695 
   7696 static xtensa_arg_internal Iclass_LDXP_args[] = {
   7697   { { OPERAND_frr }, 'o' },
   7698   { { OPERAND_ars }, 'm' },
   7699   { { OPERAND_art }, 'i' }
   7700 };
   7701 
   7702 static xtensa_arg_internal Iclass_LDXP_stateArgs[] = {
   7703   { { STATE_CPENABLE }, 'i' }
   7704 };
   7705 
   7706 static xtensa_arg_internal Iclass_SDI_args[] = {
   7707   { { OPERAND_frt }, 'i' },
   7708   { { OPERAND_ars }, 'i' },
   7709   { { OPERAND_imm8x8 }, 'i' }
   7710 };
   7711 
   7712 static xtensa_arg_internal Iclass_SDI_stateArgs[] = {
   7713   { { STATE_CPENABLE }, 'i' }
   7714 };
   7715 
   7716 static xtensa_arg_internal Iclass_SDIP_args[] = {
   7717   { { OPERAND_frt }, 'i' },
   7718   { { OPERAND_ars }, 'm' },
   7719   { { OPERAND_imm8x8 }, 'i' }
   7720 };
   7721 
   7722 static xtensa_arg_internal Iclass_SDIP_stateArgs[] = {
   7723   { { STATE_CPENABLE }, 'i' }
   7724 };
   7725 
   7726 static xtensa_arg_internal Iclass_SDX_args[] = {
   7727   { { OPERAND_frr }, 'i' },
   7728   { { OPERAND_ars }, 'i' },
   7729   { { OPERAND_art }, 'i' }
   7730 };
   7731 
   7732 static xtensa_arg_internal Iclass_SDX_stateArgs[] = {
   7733   { { STATE_CPENABLE }, 'i' }
   7734 };
   7735 
   7736 static xtensa_arg_internal Iclass_SDXP_args[] = {
   7737   { { OPERAND_frr }, 'i' },
   7738   { { OPERAND_ars }, 'm' },
   7739   { { OPERAND_art }, 'i' }
   7740 };
   7741 
   7742 static xtensa_arg_internal Iclass_SDXP_stateArgs[] = {
   7743   { { STATE_CPENABLE }, 'i' }
   7744 };
   7745 
   7746 static xtensa_arg_internal Iclass_ABS_S_args[] = {
   7747   { { OPERAND_frr }, 'o' },
   7748   { { OPERAND_frs }, 'i' }
   7749 };
   7750 
   7751 static xtensa_arg_internal Iclass_ABS_S_stateArgs[] = {
   7752   { { STATE_CPENABLE }, 'i' }
   7753 };
   7754 
   7755 static xtensa_arg_internal Iclass_NEG_S_args[] = {
   7756   { { OPERAND_frr }, 'o' },
   7757   { { OPERAND_frs }, 'i' }
   7758 };
   7759 
   7760 static xtensa_arg_internal Iclass_NEG_S_stateArgs[] = {
   7761   { { STATE_CPENABLE }, 'i' }
   7762 };
   7763 
   7764 static xtensa_arg_internal Iclass_ABS_D_args[] = {
   7765   { { OPERAND_frr }, 'o' },
   7766   { { OPERAND_frs }, 'i' }
   7767 };
   7768 
   7769 static xtensa_arg_internal Iclass_ABS_D_stateArgs[] = {
   7770   { { STATE_CPENABLE }, 'i' }
   7771 };
   7772 
   7773 static xtensa_arg_internal Iclass_NEG_D_args[] = {
   7774   { { OPERAND_frr }, 'o' },
   7775   { { OPERAND_frs }, 'i' }
   7776 };
   7777 
   7778 static xtensa_arg_internal Iclass_NEG_D_stateArgs[] = {
   7779   { { STATE_CPENABLE }, 'i' }
   7780 };
   7781 
   7782 static xtensa_arg_internal Iclass_MOV_S_args[] = {
   7783   { { OPERAND_frr }, 'o' },
   7784   { { OPERAND_frs }, 'i' }
   7785 };
   7786 
   7787 static xtensa_arg_internal Iclass_MOV_S_stateArgs[] = {
   7788   { { STATE_CPENABLE }, 'i' }
   7789 };
   7790 
   7791 static xtensa_arg_internal Iclass_MOV_D_args[] = {
   7792   { { OPERAND_frr }, 'o' },
   7793   { { OPERAND_frs }, 'i' }
   7794 };
   7795 
   7796 static xtensa_arg_internal Iclass_MOV_D_stateArgs[] = {
   7797   { { STATE_CPENABLE }, 'i' }
   7798 };
   7799 
   7800 static xtensa_arg_internal Iclass_MOVEQZ_S_args[] = {
   7801   { { OPERAND_frr }, 'm' },
   7802   { { OPERAND_frs }, 'i' },
   7803   { { OPERAND_art }, 'i' }
   7804 };
   7805 
   7806 static xtensa_arg_internal Iclass_MOVEQZ_S_stateArgs[] = {
   7807   { { STATE_CPENABLE }, 'i' }
   7808 };
   7809 
   7810 static xtensa_arg_internal Iclass_MOVNEZ_S_args[] = {
   7811   { { OPERAND_frr }, 'm' },
   7812   { { OPERAND_frs }, 'i' },
   7813   { { OPERAND_art }, 'i' }
   7814 };
   7815 
   7816 static xtensa_arg_internal Iclass_MOVNEZ_S_stateArgs[] = {
   7817   { { STATE_CPENABLE }, 'i' }
   7818 };
   7819 
   7820 static xtensa_arg_internal Iclass_MOVLTZ_S_args[] = {
   7821   { { OPERAND_frr }, 'm' },
   7822   { { OPERAND_frs }, 'i' },
   7823   { { OPERAND_art }, 'i' }
   7824 };
   7825 
   7826 static xtensa_arg_internal Iclass_MOVLTZ_S_stateArgs[] = {
   7827   { { STATE_CPENABLE }, 'i' }
   7828 };
   7829 
   7830 static xtensa_arg_internal Iclass_MOVGEZ_S_args[] = {
   7831   { { OPERAND_frr }, 'm' },
   7832   { { OPERAND_frs }, 'i' },
   7833   { { OPERAND_art }, 'i' }
   7834 };
   7835 
   7836 static xtensa_arg_internal Iclass_MOVGEZ_S_stateArgs[] = {
   7837   { { STATE_CPENABLE }, 'i' }
   7838 };
   7839 
   7840 static xtensa_arg_internal Iclass_MOVF_S_args[] = {
   7841   { { OPERAND_frr }, 'm' },
   7842   { { OPERAND_frs }, 'i' },
   7843   { { OPERAND_bt }, 'i' }
   7844 };
   7845 
   7846 static xtensa_arg_internal Iclass_MOVF_S_stateArgs[] = {
   7847   { { STATE_CPENABLE }, 'i' }
   7848 };
   7849 
   7850 static xtensa_arg_internal Iclass_MOVT_S_args[] = {
   7851   { { OPERAND_frr }, 'm' },
   7852   { { OPERAND_frs }, 'i' },
   7853   { { OPERAND_bt }, 'i' }
   7854 };
   7855 
   7856 static xtensa_arg_internal Iclass_MOVT_S_stateArgs[] = {
   7857   { { STATE_CPENABLE }, 'i' }
   7858 };
   7859 
   7860 static xtensa_arg_internal Iclass_WFR_args[] = {
   7861   { { OPERAND_frr }, 'o' },
   7862   { { OPERAND_ars }, 'i' }
   7863 };
   7864 
   7865 static xtensa_arg_internal Iclass_WFR_stateArgs[] = {
   7866   { { STATE_CPENABLE }, 'i' }
   7867 };
   7868 
   7869 static xtensa_arg_internal Iclass_RFR_args[] = {
   7870   { { OPERAND_arr }, 'o' },
   7871   { { OPERAND_frs }, 'i' }
   7872 };
   7873 
   7874 static xtensa_arg_internal Iclass_RFR_stateArgs[] = {
   7875   { { STATE_CPENABLE }, 'i' }
   7876 };
   7877 
   7878 static xtensa_arg_internal Iclass_RFRD_args[] = {
   7879   { { OPERAND_arr }, 'o' },
   7880   { { OPERAND_frs }, 'i' }
   7881 };
   7882 
   7883 static xtensa_arg_internal Iclass_RFRD_stateArgs[] = {
   7884   { { STATE_CPENABLE }, 'i' }
   7885 };
   7886 
   7887 static xtensa_arg_internal Iclass_WFRD_args[] = {
   7888   { { OPERAND_frr }, 'o' },
   7889   { { OPERAND_ars }, 'i' },
   7890   { { OPERAND_art }, 'i' }
   7891 };
   7892 
   7893 static xtensa_arg_internal Iclass_WFRD_stateArgs[] = {
   7894   { { STATE_CPENABLE }, 'i' }
   7895 };
   7896 
   7897 static xtensa_arg_internal Iclass_ROUND_S_args[] = {
   7898   { { OPERAND_arr }, 'o' },
   7899   { { OPERAND_frs }, 'i' },
   7900   { { OPERAND_imm_t }, 'i' }
   7901 };
   7902 
   7903 static xtensa_arg_internal Iclass_ROUND_S_stateArgs[] = {
   7904   { { STATE_InvalidFlag }, 'm' },
   7905   { { STATE_InexactFlag }, 'm' },
   7906   { { STATE_CPENABLE }, 'i' }
   7907 };
   7908 
   7909 static xtensa_arg_internal Iclass_ROUND_D_args[] = {
   7910   { { OPERAND_arr }, 'o' },
   7911   { { OPERAND_frs }, 'i' },
   7912   { { OPERAND_imm_t }, 'i' }
   7913 };
   7914 
   7915 static xtensa_arg_internal Iclass_ROUND_D_stateArgs[] = {
   7916   { { STATE_InvalidFlag }, 'm' },
   7917   { { STATE_InexactFlag }, 'm' },
   7918   { { STATE_CPENABLE }, 'i' }
   7919 };
   7920 
   7921 static xtensa_arg_internal Iclass_CEIL_S_args[] = {
   7922   { { OPERAND_arr }, 'o' },
   7923   { { OPERAND_frs }, 'i' },
   7924   { { OPERAND_imm_t }, 'i' }
   7925 };
   7926 
   7927 static xtensa_arg_internal Iclass_CEIL_S_stateArgs[] = {
   7928   { { STATE_InvalidFlag }, 'm' },
   7929   { { STATE_InexactFlag }, 'm' },
   7930   { { STATE_CPENABLE }, 'i' }
   7931 };
   7932 
   7933 static xtensa_arg_internal Iclass_CEIL_D_args[] = {
   7934   { { OPERAND_arr }, 'o' },
   7935   { { OPERAND_frs }, 'i' },
   7936   { { OPERAND_imm_t }, 'i' }
   7937 };
   7938 
   7939 static xtensa_arg_internal Iclass_CEIL_D_stateArgs[] = {
   7940   { { STATE_InvalidFlag }, 'm' },
   7941   { { STATE_InexactFlag }, 'm' },
   7942   { { STATE_CPENABLE }, 'i' }
   7943 };
   7944 
   7945 static xtensa_arg_internal Iclass_FLOOR_S_args[] = {
   7946   { { OPERAND_arr }, 'o' },
   7947   { { OPERAND_frs }, 'i' },
   7948   { { OPERAND_imm_t }, 'i' }
   7949 };
   7950 
   7951 static xtensa_arg_internal Iclass_FLOOR_S_stateArgs[] = {
   7952   { { STATE_InvalidFlag }, 'm' },
   7953   { { STATE_InexactFlag }, 'm' },
   7954   { { STATE_CPENABLE }, 'i' }
   7955 };
   7956 
   7957 static xtensa_arg_internal Iclass_FLOOR_D_args[] = {
   7958   { { OPERAND_arr }, 'o' },
   7959   { { OPERAND_frs }, 'i' },
   7960   { { OPERAND_imm_t }, 'i' }
   7961 };
   7962 
   7963 static xtensa_arg_internal Iclass_FLOOR_D_stateArgs[] = {
   7964   { { STATE_InvalidFlag }, 'm' },
   7965   { { STATE_InexactFlag }, 'm' },
   7966   { { STATE_CPENABLE }, 'i' }
   7967 };
   7968 
   7969 static xtensa_arg_internal Iclass_TRUNC_S_args[] = {
   7970   { { OPERAND_arr }, 'o' },
   7971   { { OPERAND_frs }, 'i' },
   7972   { { OPERAND_imm_t }, 'i' }
   7973 };
   7974 
   7975 static xtensa_arg_internal Iclass_TRUNC_S_stateArgs[] = {
   7976   { { STATE_InvalidFlag }, 'm' },
   7977   { { STATE_InexactFlag }, 'm' },
   7978   { { STATE_CPENABLE }, 'i' }
   7979 };
   7980 
   7981 static xtensa_arg_internal Iclass_TRUNC_D_args[] = {
   7982   { { OPERAND_arr }, 'o' },
   7983   { { OPERAND_frs }, 'i' },
   7984   { { OPERAND_imm_t }, 'i' }
   7985 };
   7986 
   7987 static xtensa_arg_internal Iclass_TRUNC_D_stateArgs[] = {
   7988   { { STATE_InvalidFlag }, 'm' },
   7989   { { STATE_InexactFlag }, 'm' },
   7990   { { STATE_CPENABLE }, 'i' }
   7991 };
   7992 
   7993 static xtensa_arg_internal Iclass_UTRUNC_S_args[] = {
   7994   { { OPERAND_arr }, 'o' },
   7995   { { OPERAND_frs }, 'i' },
   7996   { { OPERAND_imm_t }, 'i' }
   7997 };
   7998 
   7999 static xtensa_arg_internal Iclass_UTRUNC_S_stateArgs[] = {
   8000   { { STATE_InvalidFlag }, 'm' },
   8001   { { STATE_InexactFlag }, 'm' },
   8002   { { STATE_CPENABLE }, 'i' }
   8003 };
   8004 
   8005 static xtensa_arg_internal Iclass_UTRUNC_D_args[] = {
   8006   { { OPERAND_arr }, 'o' },
   8007   { { OPERAND_frs }, 'i' },
   8008   { { OPERAND_imm_t }, 'i' }
   8009 };
   8010 
   8011 static xtensa_arg_internal Iclass_UTRUNC_D_stateArgs[] = {
   8012   { { STATE_InvalidFlag }, 'm' },
   8013   { { STATE_InexactFlag }, 'm' },
   8014   { { STATE_CPENABLE }, 'i' }
   8015 };
   8016 
   8017 static xtensa_arg_internal Iclass_FLOAT_S_args[] = {
   8018   { { OPERAND_frr }, 'o' },
   8019   { { OPERAND_ars }, 'i' },
   8020   { { OPERAND_imm_t }, 'i' }
   8021 };
   8022 
   8023 static xtensa_arg_internal Iclass_FLOAT_S_stateArgs[] = {
   8024   { { STATE_InexactFlag }, 'm' },
   8025   { { STATE_RoundMode }, 'i' },
   8026   { { STATE_CPENABLE }, 'i' }
   8027 };
   8028 
   8029 static xtensa_arg_internal Iclass_FLOAT_D_args[] = {
   8030   { { OPERAND_frr }, 'o' },
   8031   { { OPERAND_ars }, 'i' },
   8032   { { OPERAND_imm_t }, 'i' }
   8033 };
   8034 
   8035 static xtensa_arg_internal Iclass_FLOAT_D_stateArgs[] = {
   8036   { { STATE_InexactFlag }, 'm' },
   8037   { { STATE_CPENABLE }, 'i' }
   8038 };
   8039 
   8040 static xtensa_arg_internal Iclass_UFLOAT_S_args[] = {
   8041   { { OPERAND_frr }, 'o' },
   8042   { { OPERAND_ars }, 'i' },
   8043   { { OPERAND_imm_t }, 'i' }
   8044 };
   8045 
   8046 static xtensa_arg_internal Iclass_UFLOAT_S_stateArgs[] = {
   8047   { { STATE_InexactFlag }, 'm' },
   8048   { { STATE_RoundMode }, 'i' },
   8049   { { STATE_CPENABLE }, 'i' }
   8050 };
   8051 
   8052 static xtensa_arg_internal Iclass_UFLOAT_D_args[] = {
   8053   { { OPERAND_frr }, 'o' },
   8054   { { OPERAND_ars }, 'i' },
   8055   { { OPERAND_imm_t }, 'i' }
   8056 };
   8057 
   8058 static xtensa_arg_internal Iclass_UFLOAT_D_stateArgs[] = {
   8059   { { STATE_InexactFlag }, 'm' },
   8060   { { STATE_CPENABLE }, 'i' }
   8061 };
   8062 
   8063 static xtensa_arg_internal Iclass_CVTD_S_args[] = {
   8064   { { OPERAND_frr }, 'o' },
   8065   { { OPERAND_frs }, 'i' }
   8066 };
   8067 
   8068 static xtensa_arg_internal Iclass_CVTD_S_stateArgs[] = {
   8069   { { STATE_InvalidFlag }, 'm' },
   8070   { { STATE_CPENABLE }, 'i' }
   8071 };
   8072 
   8073 static xtensa_arg_internal Iclass_CVTS_D_args[] = {
   8074   { { OPERAND_frr }, 'o' },
   8075   { { OPERAND_frs }, 'i' }
   8076 };
   8077 
   8078 static xtensa_arg_internal Iclass_CVTS_D_stateArgs[] = {
   8079   { { STATE_InvalidFlag }, 'm' },
   8080   { { STATE_UnderflowFlag }, 'm' },
   8081   { { STATE_OverflowFlag }, 'm' },
   8082   { { STATE_InexactFlag }, 'm' },
   8083   { { STATE_RoundMode }, 'i' },
   8084   { { STATE_CPENABLE }, 'i' }
   8085 };
   8086 
   8087 static xtensa_arg_internal Iclass_UN_S_args[] = {
   8088   { { OPERAND_br }, 'o' },
   8089   { { OPERAND_frs }, 'i' },
   8090   { { OPERAND_frt }, 'i' }
   8091 };
   8092 
   8093 static xtensa_arg_internal Iclass_UN_S_stateArgs[] = {
   8094   { { STATE_InvalidFlag }, 'm' },
   8095   { { STATE_CPENABLE }, 'i' }
   8096 };
   8097 
   8098 static xtensa_arg_internal Iclass_UN_D_args[] = {
   8099   { { OPERAND_br }, 'o' },
   8100   { { OPERAND_frs }, 'i' },
   8101   { { OPERAND_frt }, 'i' }
   8102 };
   8103 
   8104 static xtensa_arg_internal Iclass_UN_D_stateArgs[] = {
   8105   { { STATE_InvalidFlag }, 'm' },
   8106   { { STATE_CPENABLE }, 'i' }
   8107 };
   8108 
   8109 static xtensa_arg_internal Iclass_ULT_S_args[] = {
   8110   { { OPERAND_br }, 'o' },
   8111   { { OPERAND_frs }, 'i' },
   8112   { { OPERAND_frt }, 'i' }
   8113 };
   8114 
   8115 static xtensa_arg_internal Iclass_ULT_S_stateArgs[] = {
   8116   { { STATE_InvalidFlag }, 'm' },
   8117   { { STATE_CPENABLE }, 'i' }
   8118 };
   8119 
   8120 static xtensa_arg_internal Iclass_ULT_D_args[] = {
   8121   { { OPERAND_br }, 'o' },
   8122   { { OPERAND_frs }, 'i' },
   8123   { { OPERAND_frt }, 'i' }
   8124 };
   8125 
   8126 static xtensa_arg_internal Iclass_ULT_D_stateArgs[] = {
   8127   { { STATE_InvalidFlag }, 'm' },
   8128   { { STATE_CPENABLE }, 'i' }
   8129 };
   8130 
   8131 static xtensa_arg_internal Iclass_ULE_S_args[] = {
   8132   { { OPERAND_br }, 'o' },
   8133   { { OPERAND_frs }, 'i' },
   8134   { { OPERAND_frt }, 'i' }
   8135 };
   8136 
   8137 static xtensa_arg_internal Iclass_ULE_S_stateArgs[] = {
   8138   { { STATE_InvalidFlag }, 'm' },
   8139   { { STATE_CPENABLE }, 'i' }
   8140 };
   8141 
   8142 static xtensa_arg_internal Iclass_ULE_D_args[] = {
   8143   { { OPERAND_br }, 'o' },
   8144   { { OPERAND_frs }, 'i' },
   8145   { { OPERAND_frt }, 'i' }
   8146 };
   8147 
   8148 static xtensa_arg_internal Iclass_ULE_D_stateArgs[] = {
   8149   { { STATE_InvalidFlag }, 'm' },
   8150   { { STATE_CPENABLE }, 'i' }
   8151 };
   8152 
   8153 static xtensa_arg_internal Iclass_UEQ_S_args[] = {
   8154   { { OPERAND_br }, 'o' },
   8155   { { OPERAND_frs }, 'i' },
   8156   { { OPERAND_frt }, 'i' }
   8157 };
   8158 
   8159 static xtensa_arg_internal Iclass_UEQ_S_stateArgs[] = {
   8160   { { STATE_InvalidFlag }, 'm' },
   8161   { { STATE_CPENABLE }, 'i' }
   8162 };
   8163 
   8164 static xtensa_arg_internal Iclass_UEQ_D_args[] = {
   8165   { { OPERAND_br }, 'o' },
   8166   { { OPERAND_frs }, 'i' },
   8167   { { OPERAND_frt }, 'i' }
   8168 };
   8169 
   8170 static xtensa_arg_internal Iclass_UEQ_D_stateArgs[] = {
   8171   { { STATE_InvalidFlag }, 'm' },
   8172   { { STATE_CPENABLE }, 'i' }
   8173 };
   8174 
   8175 static xtensa_arg_internal Iclass_OLT_S_args[] = {
   8176   { { OPERAND_br }, 'o' },
   8177   { { OPERAND_frs }, 'i' },
   8178   { { OPERAND_frt }, 'i' }
   8179 };
   8180 
   8181 static xtensa_arg_internal Iclass_OLT_S_stateArgs[] = {
   8182   { { STATE_InvalidFlag }, 'm' },
   8183   { { STATE_CPENABLE }, 'i' }
   8184 };
   8185 
   8186 static xtensa_arg_internal Iclass_OLT_D_args[] = {
   8187   { { OPERAND_br }, 'o' },
   8188   { { OPERAND_frs }, 'i' },
   8189   { { OPERAND_frt }, 'i' }
   8190 };
   8191 
   8192 static xtensa_arg_internal Iclass_OLT_D_stateArgs[] = {
   8193   { { STATE_InvalidFlag }, 'm' },
   8194   { { STATE_CPENABLE }, 'i' }
   8195 };
   8196 
   8197 static xtensa_arg_internal Iclass_OLE_S_args[] = {
   8198   { { OPERAND_br }, 'o' },
   8199   { { OPERAND_frs }, 'i' },
   8200   { { OPERAND_frt }, 'i' }
   8201 };
   8202 
   8203 static xtensa_arg_internal Iclass_OLE_S_stateArgs[] = {
   8204   { { STATE_InvalidFlag }, 'm' },
   8205   { { STATE_CPENABLE }, 'i' }
   8206 };
   8207 
   8208 static xtensa_arg_internal Iclass_OLE_D_args[] = {
   8209   { { OPERAND_br }, 'o' },
   8210   { { OPERAND_frs }, 'i' },
   8211   { { OPERAND_frt }, 'i' }
   8212 };
   8213 
   8214 static xtensa_arg_internal Iclass_OLE_D_stateArgs[] = {
   8215   { { STATE_InvalidFlag }, 'm' },
   8216   { { STATE_CPENABLE }, 'i' }
   8217 };
   8218 
   8219 static xtensa_arg_internal Iclass_OEQ_S_args[] = {
   8220   { { OPERAND_br }, 'o' },
   8221   { { OPERAND_frs }, 'i' },
   8222   { { OPERAND_frt }, 'i' }
   8223 };
   8224 
   8225 static xtensa_arg_internal Iclass_OEQ_S_stateArgs[] = {
   8226   { { STATE_InvalidFlag }, 'm' },
   8227   { { STATE_CPENABLE }, 'i' }
   8228 };
   8229 
   8230 static xtensa_arg_internal Iclass_OEQ_D_args[] = {
   8231   { { OPERAND_br }, 'o' },
   8232   { { OPERAND_frs }, 'i' },
   8233   { { OPERAND_frt }, 'i' }
   8234 };
   8235 
   8236 static xtensa_arg_internal Iclass_OEQ_D_stateArgs[] = {
   8237   { { STATE_InvalidFlag }, 'm' },
   8238   { { STATE_CPENABLE }, 'i' }
   8239 };
   8240 
   8241 static xtensa_arg_internal Iclass_ADD_S_args[] = {
   8242   { { OPERAND_frr }, 'o' },
   8243   { { OPERAND_frs }, 'i' },
   8244   { { OPERAND_frt }, 'i' }
   8245 };
   8246 
   8247 static xtensa_arg_internal Iclass_ADD_S_stateArgs[] = {
   8248   { { STATE_InvalidFlag }, 'm' },
   8249   { { STATE_OverflowFlag }, 'm' },
   8250   { { STATE_UnderflowFlag }, 'm' },
   8251   { { STATE_InexactFlag }, 'm' },
   8252   { { STATE_RoundMode }, 'i' },
   8253   { { STATE_CPENABLE }, 'i' }
   8254 };
   8255 
   8256 static xtensa_arg_internal Iclass_ADD_D_args[] = {
   8257   { { OPERAND_frr }, 'o' },
   8258   { { OPERAND_frs }, 'i' },
   8259   { { OPERAND_frt }, 'i' }
   8260 };
   8261 
   8262 static xtensa_arg_internal Iclass_ADD_D_stateArgs[] = {
   8263   { { STATE_InvalidFlag }, 'm' },
   8264   { { STATE_OverflowFlag }, 'm' },
   8265   { { STATE_UnderflowFlag }, 'm' },
   8266   { { STATE_InexactFlag }, 'm' },
   8267   { { STATE_RoundMode }, 'i' },
   8268   { { STATE_CPENABLE }, 'i' }
   8269 };
   8270 
   8271 static xtensa_arg_internal Iclass_SUB_S_args[] = {
   8272   { { OPERAND_frr }, 'o' },
   8273   { { OPERAND_frs }, 'i' },
   8274   { { OPERAND_frt }, 'i' }
   8275 };
   8276 
   8277 static xtensa_arg_internal Iclass_SUB_S_stateArgs[] = {
   8278   { { STATE_InvalidFlag }, 'm' },
   8279   { { STATE_OverflowFlag }, 'm' },
   8280   { { STATE_UnderflowFlag }, 'm' },
   8281   { { STATE_InexactFlag }, 'm' },
   8282   { { STATE_RoundMode }, 'i' },
   8283   { { STATE_CPENABLE }, 'i' }
   8284 };
   8285 
   8286 static xtensa_arg_internal Iclass_SUB_D_args[] = {
   8287   { { OPERAND_frr }, 'o' },
   8288   { { OPERAND_frs }, 'i' },
   8289   { { OPERAND_frt }, 'i' }
   8290 };
   8291 
   8292 static xtensa_arg_internal Iclass_SUB_D_stateArgs[] = {
   8293   { { STATE_InvalidFlag }, 'm' },
   8294   { { STATE_OverflowFlag }, 'm' },
   8295   { { STATE_UnderflowFlag }, 'm' },
   8296   { { STATE_InexactFlag }, 'm' },
   8297   { { STATE_RoundMode }, 'i' },
   8298   { { STATE_CPENABLE }, 'i' }
   8299 };
   8300 
   8301 static xtensa_arg_internal Iclass_MUL_S_args[] = {
   8302   { { OPERAND_frr }, 'o' },
   8303   { { OPERAND_frs }, 'i' },
   8304   { { OPERAND_frt }, 'i' }
   8305 };
   8306 
   8307 static xtensa_arg_internal Iclass_MUL_S_stateArgs[] = {
   8308   { { STATE_InvalidFlag }, 'm' },
   8309   { { STATE_OverflowFlag }, 'm' },
   8310   { { STATE_UnderflowFlag }, 'm' },
   8311   { { STATE_InexactFlag }, 'm' },
   8312   { { STATE_RoundMode }, 'i' },
   8313   { { STATE_CPENABLE }, 'i' }
   8314 };
   8315 
   8316 static xtensa_arg_internal Iclass_MUL_D_args[] = {
   8317   { { OPERAND_frr }, 'o' },
   8318   { { OPERAND_frs }, 'i' },
   8319   { { OPERAND_frt }, 'i' }
   8320 };
   8321 
   8322 static xtensa_arg_internal Iclass_MUL_D_stateArgs[] = {
   8323   { { STATE_InvalidFlag }, 'm' },
   8324   { { STATE_OverflowFlag }, 'm' },
   8325   { { STATE_UnderflowFlag }, 'm' },
   8326   { { STATE_InexactFlag }, 'm' },
   8327   { { STATE_RoundMode }, 'i' },
   8328   { { STATE_CPENABLE }, 'i' }
   8329 };
   8330 
   8331 static xtensa_arg_internal Iclass_MADD_S_args[] = {
   8332   { { OPERAND_frr }, 'm' },
   8333   { { OPERAND_frs }, 'i' },
   8334   { { OPERAND_frt }, 'i' }
   8335 };
   8336 
   8337 static xtensa_arg_internal Iclass_MADD_S_stateArgs[] = {
   8338   { { STATE_InvalidFlag }, 'm' },
   8339   { { STATE_OverflowFlag }, 'm' },
   8340   { { STATE_UnderflowFlag }, 'm' },
   8341   { { STATE_InexactFlag }, 'm' },
   8342   { { STATE_RoundMode }, 'i' },
   8343   { { STATE_CPENABLE }, 'i' }
   8344 };
   8345 
   8346 static xtensa_arg_internal Iclass_MADD_D_args[] = {
   8347   { { OPERAND_frr }, 'm' },
   8348   { { OPERAND_frs }, 'i' },
   8349   { { OPERAND_frt }, 'i' }
   8350 };
   8351 
   8352 static xtensa_arg_internal Iclass_MADD_D_stateArgs[] = {
   8353   { { STATE_InvalidFlag }, 'm' },
   8354   { { STATE_OverflowFlag }, 'm' },
   8355   { { STATE_UnderflowFlag }, 'm' },
   8356   { { STATE_InexactFlag }, 'm' },
   8357   { { STATE_RoundMode }, 'i' },
   8358   { { STATE_CPENABLE }, 'i' }
   8359 };
   8360 
   8361 static xtensa_arg_internal Iclass_MSUB_S_args[] = {
   8362   { { OPERAND_frr }, 'm' },
   8363   { { OPERAND_frs }, 'i' },
   8364   { { OPERAND_frt }, 'i' }
   8365 };
   8366 
   8367 static xtensa_arg_internal Iclass_MSUB_S_stateArgs[] = {
   8368   { { STATE_InvalidFlag }, 'm' },
   8369   { { STATE_OverflowFlag }, 'm' },
   8370   { { STATE_UnderflowFlag }, 'm' },
   8371   { { STATE_InexactFlag }, 'm' },
   8372   { { STATE_RoundMode }, 'i' },
   8373   { { STATE_CPENABLE }, 'i' }
   8374 };
   8375 
   8376 static xtensa_arg_internal Iclass_MSUB_D_args[] = {
   8377   { { OPERAND_frr }, 'm' },
   8378   { { OPERAND_frs }, 'i' },
   8379   { { OPERAND_frt }, 'i' }
   8380 };
   8381 
   8382 static xtensa_arg_internal Iclass_MSUB_D_stateArgs[] = {
   8383   { { STATE_InvalidFlag }, 'm' },
   8384   { { STATE_OverflowFlag }, 'm' },
   8385   { { STATE_UnderflowFlag }, 'm' },
   8386   { { STATE_InexactFlag }, 'm' },
   8387   { { STATE_RoundMode }, 'i' },
   8388   { { STATE_CPENABLE }, 'i' }
   8389 };
   8390 
   8391 static xtensa_arg_internal Iclass_SQRT0_S_args[] = {
   8392   { { OPERAND_frr }, 'o' },
   8393   { { OPERAND_frs }, 'i' }
   8394 };
   8395 
   8396 static xtensa_arg_internal Iclass_SQRT0_S_stateArgs[] = {
   8397   { { STATE_CPENABLE }, 'i' }
   8398 };
   8399 
   8400 static xtensa_arg_internal Iclass_SQRT0_D_args[] = {
   8401   { { OPERAND_frr }, 'o' },
   8402   { { OPERAND_frs }, 'i' }
   8403 };
   8404 
   8405 static xtensa_arg_internal Iclass_SQRT0_D_stateArgs[] = {
   8406   { { STATE_CPENABLE }, 'i' }
   8407 };
   8408 
   8409 static xtensa_arg_internal Iclass_DIV0_S_args[] = {
   8410   { { OPERAND_frr }, 'o' },
   8411   { { OPERAND_frs }, 'i' }
   8412 };
   8413 
   8414 static xtensa_arg_internal Iclass_DIV0_S_stateArgs[] = {
   8415   { { STATE_CPENABLE }, 'i' }
   8416 };
   8417 
   8418 static xtensa_arg_internal Iclass_DIV0_D_args[] = {
   8419   { { OPERAND_frr }, 'o' },
   8420   { { OPERAND_frs }, 'i' }
   8421 };
   8422 
   8423 static xtensa_arg_internal Iclass_DIV0_D_stateArgs[] = {
   8424   { { STATE_CPENABLE }, 'i' }
   8425 };
   8426 
   8427 static xtensa_arg_internal Iclass_RECIP0_S_args[] = {
   8428   { { OPERAND_frr }, 'o' },
   8429   { { OPERAND_frs }, 'i' }
   8430 };
   8431 
   8432 static xtensa_arg_internal Iclass_RECIP0_S_stateArgs[] = {
   8433   { { STATE_InvalidFlag }, 'm' },
   8434   { { STATE_DivZeroFlag }, 'm' },
   8435   { { STATE_CPENABLE }, 'i' }
   8436 };
   8437 
   8438 static xtensa_arg_internal Iclass_RECIP0_D_args[] = {
   8439   { { OPERAND_frr }, 'o' },
   8440   { { OPERAND_frs }, 'i' }
   8441 };
   8442 
   8443 static xtensa_arg_internal Iclass_RECIP0_D_stateArgs[] = {
   8444   { { STATE_InvalidFlag }, 'm' },
   8445   { { STATE_DivZeroFlag }, 'm' },
   8446   { { STATE_CPENABLE }, 'i' }
   8447 };
   8448 
   8449 static xtensa_arg_internal Iclass_RSQRT0_S_args[] = {
   8450   { { OPERAND_frr }, 'o' },
   8451   { { OPERAND_frs }, 'i' }
   8452 };
   8453 
   8454 static xtensa_arg_internal Iclass_RSQRT0_S_stateArgs[] = {
   8455   { { STATE_InvalidFlag }, 'm' },
   8456   { { STATE_DivZeroFlag }, 'm' },
   8457   { { STATE_CPENABLE }, 'i' }
   8458 };
   8459 
   8460 static xtensa_arg_internal Iclass_RSQRT0_D_args[] = {
   8461   { { OPERAND_frr }, 'o' },
   8462   { { OPERAND_frs }, 'i' }
   8463 };
   8464 
   8465 static xtensa_arg_internal Iclass_RSQRT0_D_stateArgs[] = {
   8466   { { STATE_InvalidFlag }, 'm' },
   8467   { { STATE_DivZeroFlag }, 'm' },
   8468   { { STATE_CPENABLE }, 'i' }
   8469 };
   8470 
   8471 static xtensa_arg_internal Iclass_MADDN_S_args[] = {
   8472   { { OPERAND_frr }, 'm' },
   8473   { { OPERAND_frs }, 'i' },
   8474   { { OPERAND_frt }, 'i' }
   8475 };
   8476 
   8477 static xtensa_arg_internal Iclass_MADDN_S_stateArgs[] = {
   8478   { { STATE_CPENABLE }, 'i' }
   8479 };
   8480 
   8481 static xtensa_arg_internal Iclass_MADDN_D_args[] = {
   8482   { { OPERAND_frr }, 'm' },
   8483   { { OPERAND_frs }, 'i' },
   8484   { { OPERAND_frt }, 'i' }
   8485 };
   8486 
   8487 static xtensa_arg_internal Iclass_MADDN_D_stateArgs[] = {
   8488   { { STATE_CPENABLE }, 'i' }
   8489 };
   8490 
   8491 static xtensa_arg_internal Iclass_DIVN_S_args[] = {
   8492   { { OPERAND_frr }, 'm' },
   8493   { { OPERAND_frs }, 'i' },
   8494   { { OPERAND_frt }, 'i' }
   8495 };
   8496 
   8497 static xtensa_arg_internal Iclass_DIVN_S_stateArgs[] = {
   8498   { { STATE_OverflowFlag }, 'm' },
   8499   { { STATE_UnderflowFlag }, 'm' },
   8500   { { STATE_InexactFlag }, 'm' },
   8501   { { STATE_RoundMode }, 'i' },
   8502   { { STATE_CPENABLE }, 'i' }
   8503 };
   8504 
   8505 static xtensa_arg_internal Iclass_DIVN_D_args[] = {
   8506   { { OPERAND_frr }, 'm' },
   8507   { { OPERAND_frs }, 'i' },
   8508   { { OPERAND_frt }, 'i' }
   8509 };
   8510 
   8511 static xtensa_arg_internal Iclass_DIVN_D_stateArgs[] = {
   8512   { { STATE_OverflowFlag }, 'm' },
   8513   { { STATE_UnderflowFlag }, 'm' },
   8514   { { STATE_InexactFlag }, 'm' },
   8515   { { STATE_RoundMode }, 'i' },
   8516   { { STATE_CPENABLE }, 'i' }
   8517 };
   8518 
   8519 static xtensa_arg_internal Iclass_CONST_S_args[] = {
   8520   { { OPERAND_frr }, 'o' },
   8521   { { OPERAND_imm_s }, 'i' }
   8522 };
   8523 
   8524 static xtensa_arg_internal Iclass_CONST_S_stateArgs[] = {
   8525   { { STATE_CPENABLE }, 'i' }
   8526 };
   8527 
   8528 static xtensa_arg_internal Iclass_CONST_D_args[] = {
   8529   { { OPERAND_frr }, 'o' },
   8530   { { OPERAND_imm_s }, 'i' }
   8531 };
   8532 
   8533 static xtensa_arg_internal Iclass_CONST_D_stateArgs[] = {
   8534   { { STATE_CPENABLE }, 'i' }
   8535 };
   8536 
   8537 static xtensa_arg_internal Iclass_NEXP01_S_args[] = {
   8538   { { OPERAND_frr }, 'o' },
   8539   { { OPERAND_frs }, 'i' }
   8540 };
   8541 
   8542 static xtensa_arg_internal Iclass_NEXP01_S_stateArgs[] = {
   8543   { { STATE_CPENABLE }, 'i' }
   8544 };
   8545 
   8546 static xtensa_arg_internal Iclass_NEXP01_D_args[] = {
   8547   { { OPERAND_frr }, 'o' },
   8548   { { OPERAND_frs }, 'i' }
   8549 };
   8550 
   8551 static xtensa_arg_internal Iclass_NEXP01_D_stateArgs[] = {
   8552   { { STATE_CPENABLE }, 'i' }
   8553 };
   8554 
   8555 static xtensa_arg_internal Iclass_ADDEXP_S_args[] = {
   8556   { { OPERAND_frr }, 'm' },
   8557   { { OPERAND_frs }, 'i' }
   8558 };
   8559 
   8560 static xtensa_arg_internal Iclass_ADDEXP_S_stateArgs[] = {
   8561   { { STATE_CPENABLE }, 'i' }
   8562 };
   8563 
   8564 static xtensa_arg_internal Iclass_ADDEXP_D_args[] = {
   8565   { { OPERAND_frr }, 'm' },
   8566   { { OPERAND_frs }, 'i' }
   8567 };
   8568 
   8569 static xtensa_arg_internal Iclass_ADDEXP_D_stateArgs[] = {
   8570   { { STATE_CPENABLE }, 'i' }
   8571 };
   8572 
   8573 static xtensa_arg_internal Iclass_ADDEXPM_S_args[] = {
   8574   { { OPERAND_frr }, 'm' },
   8575   { { OPERAND_frs }, 'i' }
   8576 };
   8577 
   8578 static xtensa_arg_internal Iclass_ADDEXPM_S_stateArgs[] = {
   8579   { { STATE_CPENABLE }, 'i' }
   8580 };
   8581 
   8582 static xtensa_arg_internal Iclass_ADDEXPM_D_args[] = {
   8583   { { OPERAND_frr }, 'm' },
   8584   { { OPERAND_frs }, 'i' }
   8585 };
   8586 
   8587 static xtensa_arg_internal Iclass_ADDEXPM_D_stateArgs[] = {
   8588   { { STATE_CPENABLE }, 'i' }
   8589 };
   8590 
   8591 static xtensa_arg_internal Iclass_MKDADJ_S_args[] = {
   8592   { { OPERAND_frr }, 'm' },
   8593   { { OPERAND_frs }, 'i' }
   8594 };
   8595 
   8596 static xtensa_arg_internal Iclass_MKDADJ_S_stateArgs[] = {
   8597   { { STATE_InvalidFlag }, 'm' },
   8598   { { STATE_DivZeroFlag }, 'm' },
   8599   { { STATE_CPENABLE }, 'i' }
   8600 };
   8601 
   8602 static xtensa_arg_internal Iclass_MKDADJ_D_args[] = {
   8603   { { OPERAND_frr }, 'm' },
   8604   { { OPERAND_frs }, 'i' }
   8605 };
   8606 
   8607 static xtensa_arg_internal Iclass_MKDADJ_D_stateArgs[] = {
   8608   { { STATE_InvalidFlag }, 'm' },
   8609   { { STATE_DivZeroFlag }, 'm' },
   8610   { { STATE_CPENABLE }, 'i' }
   8611 };
   8612 
   8613 static xtensa_arg_internal Iclass_MKSADJ_S_args[] = {
   8614   { { OPERAND_frr }, 'o' },
   8615   { { OPERAND_frs }, 'i' }
   8616 };
   8617 
   8618 static xtensa_arg_internal Iclass_MKSADJ_S_stateArgs[] = {
   8619   { { STATE_InvalidFlag }, 'm' },
   8620   { { STATE_CPENABLE }, 'i' }
   8621 };
   8622 
   8623 static xtensa_arg_internal Iclass_MKSADJ_D_args[] = {
   8624   { { OPERAND_frr }, 'o' },
   8625   { { OPERAND_frs }, 'i' }
   8626 };
   8627 
   8628 static xtensa_arg_internal Iclass_MKSADJ_D_stateArgs[] = {
   8629   { { STATE_InvalidFlag }, 'm' },
   8630   { { STATE_CPENABLE }, 'i' }
   8631 };
   8632 
   8633 static xtensa_iclass_internal iclasses[] = {
   8634   { 0, 0 /* xt_iclass_excw */,
   8635     0, 0, 0, 0 },
   8636   { 0, 0 /* xt_iclass_rfe */,
   8637     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
   8638   { 0, 0 /* xt_iclass_rfde */,
   8639     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
   8640   { 0, 0 /* xt_iclass_syscall */,
   8641     0, 0, 0, 0 },
   8642   { 2, Iclass_xt_iclass_call12_args,
   8643     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
   8644   { 2, Iclass_xt_iclass_call8_args,
   8645     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
   8646   { 2, Iclass_xt_iclass_call4_args,
   8647     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
   8648   { 2, Iclass_xt_iclass_callx12_args,
   8649     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
   8650   { 2, Iclass_xt_iclass_callx8_args,
   8651     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
   8652   { 2, Iclass_xt_iclass_callx4_args,
   8653     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
   8654   { 3, Iclass_xt_iclass_entry_args,
   8655     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
   8656   { 2, Iclass_xt_iclass_movsp_args,
   8657     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
   8658   { 1, Iclass_xt_iclass_rotw_args,
   8659     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
   8660   { 1, Iclass_xt_iclass_retw_args,
   8661     5, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
   8662   { 0, 0 /* xt_iclass_rfwou */,
   8663     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
   8664   { 3, Iclass_xt_iclass_l32e_args,
   8665     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
   8666   { 3, Iclass_xt_iclass_s32e_args,
   8667     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
   8668   { 1, Iclass_xt_iclass_rsr_windowbase_args,
   8669     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
   8670   { 1, Iclass_xt_iclass_wsr_windowbase_args,
   8671     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
   8672   { 1, Iclass_xt_iclass_xsr_windowbase_args,
   8673     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
   8674   { 1, Iclass_xt_iclass_rsr_windowstart_args,
   8675     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
   8676   { 1, Iclass_xt_iclass_wsr_windowstart_args,
   8677     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
   8678   { 1, Iclass_xt_iclass_xsr_windowstart_args,
   8679     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
   8680   { 3, Iclass_xt_iclass_add_n_args,
   8681     0, 0, 0, 0 },
   8682   { 3, Iclass_xt_iclass_addi_n_args,
   8683     0, 0, 0, 0 },
   8684   { 2, Iclass_xt_iclass_bz6_args,
   8685     0, 0, 0, 0 },
   8686   { 0, 0 /* xt_iclass_ill_n */,
   8687     0, 0, 0, 0 },
   8688   { 3, Iclass_xt_iclass_loadi4_args,
   8689     0, 0, 0, 0 },
   8690   { 2, Iclass_xt_iclass_mov_n_args,
   8691     0, 0, 0, 0 },
   8692   { 2, Iclass_xt_iclass_movi_n_args,
   8693     0, 0, 0, 0 },
   8694   { 0, 0 /* xt_iclass_nopn */,
   8695     0, 0, 0, 0 },
   8696   { 1, Iclass_xt_iclass_retn_args,
   8697     0, 0, 0, 0 },
   8698   { 3, Iclass_xt_iclass_storei4_args,
   8699     0, 0, 0, 0 },
   8700   { 1, Iclass_rur_threadptr_args,
   8701     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
   8702   { 1, Iclass_wur_threadptr_args,
   8703     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
   8704   { 3, Iclass_xt_iclass_addi_args,
   8705     0, 0, 0, 0 },
   8706   { 3, Iclass_xt_iclass_addmi_args,
   8707     0, 0, 0, 0 },
   8708   { 3, Iclass_xt_iclass_addsub_args,
   8709     0, 0, 0, 0 },
   8710   { 3, Iclass_xt_iclass_bit_args,
   8711     0, 0, 0, 0 },
   8712   { 3, Iclass_xt_iclass_bsi8_args,
   8713     0, 0, 0, 0 },
   8714   { 3, Iclass_xt_iclass_bsi8b_args,
   8715     0, 0, 0, 0 },
   8716   { 3, Iclass_xt_iclass_bsi8u_args,
   8717     0, 0, 0, 0 },
   8718   { 3, Iclass_xt_iclass_bst8_args,
   8719     0, 0, 0, 0 },
   8720   { 2, Iclass_xt_iclass_bsz12_args,
   8721     0, 0, 0, 0 },
   8722   { 2, Iclass_xt_iclass_call0_args,
   8723     0, 0, 0, 0 },
   8724   { 2, Iclass_xt_iclass_callx0_args,
   8725     0, 0, 0, 0 },
   8726   { 4, Iclass_xt_iclass_exti_args,
   8727     0, 0, 0, 0 },
   8728   { 0, 0 /* xt_iclass_ill */,
   8729     0, 0, 0, 0 },
   8730   { 1, Iclass_xt_iclass_jump_args,
   8731     0, 0, 0, 0 },
   8732   { 1, Iclass_xt_iclass_jumpx_args,
   8733     0, 0, 0, 0 },
   8734   { 3, Iclass_xt_iclass_l16ui_args,
   8735     0, 0, 0, 0 },
   8736   { 3, Iclass_xt_iclass_l16si_args,
   8737     0, 0, 0, 0 },
   8738   { 3, Iclass_xt_iclass_l32i_args,
   8739     0, 0, 0, 0 },
   8740   { 2, Iclass_xt_iclass_l32r_args,
   8741     0, 0, 0, 0 },
   8742   { 3, Iclass_xt_iclass_l8i_args,
   8743     0, 0, 0, 0 },
   8744   { 2, Iclass_xt_iclass_loop_args,
   8745     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
   8746   { 2, Iclass_xt_iclass_loopz_args,
   8747     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
   8748   { 2, Iclass_xt_iclass_movi_args,
   8749     0, 0, 0, 0 },
   8750   { 3, Iclass_xt_iclass_movz_args,
   8751     0, 0, 0, 0 },
   8752   { 2, Iclass_xt_iclass_neg_args,
   8753     0, 0, 0, 0 },
   8754   { 0, 0 /* xt_iclass_nop */,
   8755     0, 0, 0, 0 },
   8756   { 1, Iclass_xt_iclass_return_args,
   8757     0, 0, 0, 0 },
   8758   { 1, Iclass_xt_iclass_simcall_args,
   8759     0, 0, 0, 0 },
   8760   { 3, Iclass_xt_iclass_s16i_args,
   8761     0, 0, 0, 0 },
   8762   { 3, Iclass_xt_iclass_s32i_args,
   8763     0, 0, 0, 0 },
   8764   { 3, Iclass_xt_iclass_s32nb_args,
   8765     0, 0, 0, 0 },
   8766   { 3, Iclass_xt_iclass_s8i_args,
   8767     0, 0, 0, 0 },
   8768   { 1, Iclass_xt_iclass_sar_args,
   8769     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
   8770   { 1, Iclass_xt_iclass_sari_args,
   8771     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
   8772   { 2, Iclass_xt_iclass_shifts_args,
   8773     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
   8774   { 3, Iclass_xt_iclass_shiftst_args,
   8775     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
   8776   { 2, Iclass_xt_iclass_shiftt_args,
   8777     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
   8778   { 3, Iclass_xt_iclass_slli_args,
   8779     0, 0, 0, 0 },
   8780   { 3, Iclass_xt_iclass_srai_args,
   8781     0, 0, 0, 0 },
   8782   { 3, Iclass_xt_iclass_srli_args,
   8783     0, 0, 0, 0 },
   8784   { 0, 0 /* xt_iclass_memw */,
   8785     0, 0, 0, 0 },
   8786   { 0, 0 /* xt_iclass_extw */,
   8787     0, 0, 0, 0 },
   8788   { 0, 0 /* xt_iclass_isync */,
   8789     0, 0, 0, 0 },
   8790   { 0, 0 /* xt_iclass_sync */,
   8791     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
   8792   { 2, Iclass_xt_iclass_rsil_args,
   8793     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
   8794   { 1, Iclass_xt_iclass_rsr_lend_args,
   8795     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
   8796   { 1, Iclass_xt_iclass_wsr_lend_args,
   8797     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
   8798   { 1, Iclass_xt_iclass_xsr_lend_args,
   8799     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
   8800   { 1, Iclass_xt_iclass_rsr_lcount_args,
   8801     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
   8802   { 1, Iclass_xt_iclass_wsr_lcount_args,
   8803     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
   8804   { 1, Iclass_xt_iclass_xsr_lcount_args,
   8805     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
   8806   { 1, Iclass_xt_iclass_rsr_lbeg_args,
   8807     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
   8808   { 1, Iclass_xt_iclass_wsr_lbeg_args,
   8809     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
   8810   { 1, Iclass_xt_iclass_xsr_lbeg_args,
   8811     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
   8812   { 1, Iclass_xt_iclass_rsr_sar_args,
   8813     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
   8814   { 1, Iclass_xt_iclass_wsr_sar_args,
   8815     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
   8816   { 1, Iclass_xt_iclass_xsr_sar_args,
   8817     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
   8818   { 1, Iclass_xt_iclass_rsr_memctl_args,
   8819     0, 0, 0, 0 },
   8820   { 1, Iclass_xt_iclass_wsr_memctl_args,
   8821     0, 0, 0, 0 },
   8822   { 1, Iclass_xt_iclass_xsr_memctl_args,
   8823     0, 0, 0, 0 },
   8824   { 1, Iclass_xt_iclass_rsr_configid0_args,
   8825     2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
   8826   { 1, Iclass_xt_iclass_wsr_configid0_args,
   8827     2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
   8828   { 1, Iclass_xt_iclass_rsr_configid1_args,
   8829     2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
   8830   { 1, Iclass_xt_iclass_rsr_ps_args,
   8831     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
   8832   { 1, Iclass_xt_iclass_wsr_ps_args,
   8833     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
   8834   { 1, Iclass_xt_iclass_xsr_ps_args,
   8835     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
   8836   { 1, Iclass_xt_iclass_rsr_epc1_args,
   8837     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
   8838   { 1, Iclass_xt_iclass_wsr_epc1_args,
   8839     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
   8840   { 1, Iclass_xt_iclass_xsr_epc1_args,
   8841     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
   8842   { 1, Iclass_xt_iclass_rsr_excsave1_args,
   8843     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
   8844   { 1, Iclass_xt_iclass_wsr_excsave1_args,
   8845     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
   8846   { 1, Iclass_xt_iclass_xsr_excsave1_args,
   8847     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
   8848   { 1, Iclass_xt_iclass_rsr_epc2_args,
   8849     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
   8850   { 1, Iclass_xt_iclass_wsr_epc2_args,
   8851     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
   8852   { 1, Iclass_xt_iclass_xsr_epc2_args,
   8853     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
   8854   { 1, Iclass_xt_iclass_rsr_excsave2_args,
   8855     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
   8856   { 1, Iclass_xt_iclass_wsr_excsave2_args,
   8857     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
   8858   { 1, Iclass_xt_iclass_xsr_excsave2_args,
   8859     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
   8860   { 1, Iclass_xt_iclass_rsr_epc3_args,
   8861     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
   8862   { 1, Iclass_xt_iclass_wsr_epc3_args,
   8863     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
   8864   { 1, Iclass_xt_iclass_xsr_epc3_args,
   8865     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
   8866   { 1, Iclass_xt_iclass_rsr_excsave3_args,
   8867     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
   8868   { 1, Iclass_xt_iclass_wsr_excsave3_args,
   8869     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
   8870   { 1, Iclass_xt_iclass_xsr_excsave3_args,
   8871     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
   8872   { 1, Iclass_xt_iclass_rsr_epc4_args,
   8873     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
   8874   { 1, Iclass_xt_iclass_wsr_epc4_args,
   8875     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
   8876   { 1, Iclass_xt_iclass_xsr_epc4_args,
   8877     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
   8878   { 1, Iclass_xt_iclass_rsr_excsave4_args,
   8879     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
   8880   { 1, Iclass_xt_iclass_wsr_excsave4_args,
   8881     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
   8882   { 1, Iclass_xt_iclass_xsr_excsave4_args,
   8883     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
   8884   { 1, Iclass_xt_iclass_rsr_epc5_args,
   8885     3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
   8886   { 1, Iclass_xt_iclass_wsr_epc5_args,
   8887     3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
   8888   { 1, Iclass_xt_iclass_xsr_epc5_args,
   8889     3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
   8890   { 1, Iclass_xt_iclass_rsr_excsave5_args,
   8891     3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
   8892   { 1, Iclass_xt_iclass_wsr_excsave5_args,
   8893     3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
   8894   { 1, Iclass_xt_iclass_xsr_excsave5_args,
   8895     3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
   8896   { 1, Iclass_xt_iclass_rsr_epc6_args,
   8897     3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
   8898   { 1, Iclass_xt_iclass_wsr_epc6_args,
   8899     3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
   8900   { 1, Iclass_xt_iclass_xsr_epc6_args,
   8901     3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
   8902   { 1, Iclass_xt_iclass_rsr_excsave6_args,
   8903     3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
   8904   { 1, Iclass_xt_iclass_wsr_excsave6_args,
   8905     3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
   8906   { 1, Iclass_xt_iclass_xsr_excsave6_args,
   8907     3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
   8908   { 1, Iclass_xt_iclass_rsr_epc7_args,
   8909     3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
   8910   { 1, Iclass_xt_iclass_wsr_epc7_args,
   8911     3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
   8912   { 1, Iclass_xt_iclass_xsr_epc7_args,
   8913     3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
   8914   { 1, Iclass_xt_iclass_rsr_excsave7_args,
   8915     3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
   8916   { 1, Iclass_xt_iclass_wsr_excsave7_args,
   8917     3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
   8918   { 1, Iclass_xt_iclass_xsr_excsave7_args,
   8919     3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
   8920   { 1, Iclass_xt_iclass_rsr_eps2_args,
   8921     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
   8922   { 1, Iclass_xt_iclass_wsr_eps2_args,
   8923     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
   8924   { 1, Iclass_xt_iclass_xsr_eps2_args,
   8925     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
   8926   { 1, Iclass_xt_iclass_rsr_eps3_args,
   8927     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
   8928   { 1, Iclass_xt_iclass_wsr_eps3_args,
   8929     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
   8930   { 1, Iclass_xt_iclass_xsr_eps3_args,
   8931     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
   8932   { 1, Iclass_xt_iclass_rsr_eps4_args,
   8933     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
   8934   { 1, Iclass_xt_iclass_wsr_eps4_args,
   8935     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
   8936   { 1, Iclass_xt_iclass_xsr_eps4_args,
   8937     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
   8938   { 1, Iclass_xt_iclass_rsr_eps5_args,
   8939     3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
   8940   { 1, Iclass_xt_iclass_wsr_eps5_args,
   8941     3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
   8942   { 1, Iclass_xt_iclass_xsr_eps5_args,
   8943     3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
   8944   { 1, Iclass_xt_iclass_rsr_eps6_args,
   8945     3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
   8946   { 1, Iclass_xt_iclass_wsr_eps6_args,
   8947     3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
   8948   { 1, Iclass_xt_iclass_xsr_eps6_args,
   8949     3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
   8950   { 1, Iclass_xt_iclass_rsr_eps7_args,
   8951     3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
   8952   { 1, Iclass_xt_iclass_wsr_eps7_args,
   8953     3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
   8954   { 1, Iclass_xt_iclass_xsr_eps7_args,
   8955     3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
   8956   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
   8957     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
   8958   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
   8959     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
   8960   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
   8961     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
   8962   { 1, Iclass_xt_iclass_rsr_depc_args,
   8963     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
   8964   { 1, Iclass_xt_iclass_wsr_depc_args,
   8965     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
   8966   { 1, Iclass_xt_iclass_xsr_depc_args,
   8967     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
   8968   { 1, Iclass_xt_iclass_rsr_exccause_args,
   8969     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
   8970   { 1, Iclass_xt_iclass_wsr_exccause_args,
   8971     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
   8972   { 1, Iclass_xt_iclass_xsr_exccause_args,
   8973     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
   8974   { 1, Iclass_xt_iclass_rsr_misc0_args,
   8975     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
   8976   { 1, Iclass_xt_iclass_wsr_misc0_args,
   8977     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
   8978   { 1, Iclass_xt_iclass_xsr_misc0_args,
   8979     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
   8980   { 1, Iclass_xt_iclass_rsr_misc1_args,
   8981     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
   8982   { 1, Iclass_xt_iclass_wsr_misc1_args,
   8983     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
   8984   { 1, Iclass_xt_iclass_xsr_misc1_args,
   8985     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
   8986   { 1, Iclass_xt_iclass_rsr_prid_args,
   8987     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
   8988   { 1, Iclass_xt_iclass_rsr_vecbase_args,
   8989     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
   8990   { 1, Iclass_xt_iclass_wsr_vecbase_args,
   8991     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
   8992   { 1, Iclass_xt_iclass_xsr_vecbase_args,
   8993     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
   8994   { 3, Iclass_xt_iclass_salt_args,
   8995     0, 0, 0, 0 },
   8996   { 3, Iclass_xt_mul16_args,
   8997     0, 0, 0, 0 },
   8998   { 3, Iclass_xt_mul32_args,
   8999     0, 0, 0, 0 },
   9000   { 2, Iclass_xt_iclass_mac16_aa_args,
   9001     1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
   9002   { 2, Iclass_xt_iclass_mac16_ad_args,
   9003     1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
   9004   { 2, Iclass_xt_iclass_mac16_da_args,
   9005     1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
   9006   { 2, Iclass_xt_iclass_mac16_dd_args,
   9007     1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
   9008   { 2, Iclass_xt_iclass_mac16a_aa_args,
   9009     1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
   9010   { 2, Iclass_xt_iclass_mac16a_ad_args,
   9011     1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
   9012   { 2, Iclass_xt_iclass_mac16a_da_args,
   9013     1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
   9014   { 2, Iclass_xt_iclass_mac16a_dd_args,
   9015     1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
   9016   { 4, Iclass_xt_iclass_mac16al_da_args,
   9017     1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
   9018   { 4, Iclass_xt_iclass_mac16al_dd_args,
   9019     1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
   9020   { 2, Iclass_xt_iclass_mac16_l_args,
   9021     0, 0, 0, 0 },
   9022   { 2, Iclass_xt_iclass_rsr_m0_args,
   9023     0, 0, 0, 0 },
   9024   { 2, Iclass_xt_iclass_wsr_m0_args,
   9025     0, 0, 0, 0 },
   9026   { 2, Iclass_xt_iclass_xsr_m0_args,
   9027     0, 0, 0, 0 },
   9028   { 2, Iclass_xt_iclass_rsr_m1_args,
   9029     0, 0, 0, 0 },
   9030   { 2, Iclass_xt_iclass_wsr_m1_args,
   9031     0, 0, 0, 0 },
   9032   { 2, Iclass_xt_iclass_xsr_m1_args,
   9033     0, 0, 0, 0 },
   9034   { 2, Iclass_xt_iclass_rsr_m2_args,
   9035     0, 0, 0, 0 },
   9036   { 2, Iclass_xt_iclass_wsr_m2_args,
   9037     0, 0, 0, 0 },
   9038   { 2, Iclass_xt_iclass_xsr_m2_args,
   9039     0, 0, 0, 0 },
   9040   { 2, Iclass_xt_iclass_rsr_m3_args,
   9041     0, 0, 0, 0 },
   9042   { 2, Iclass_xt_iclass_wsr_m3_args,
   9043     0, 0, 0, 0 },
   9044   { 2, Iclass_xt_iclass_xsr_m3_args,
   9045     0, 0, 0, 0 },
   9046   { 1, Iclass_xt_iclass_rsr_acclo_args,
   9047     1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
   9048   { 1, Iclass_xt_iclass_wsr_acclo_args,
   9049     1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
   9050   { 1, Iclass_xt_iclass_xsr_acclo_args,
   9051     1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
   9052   { 1, Iclass_xt_iclass_rsr_acchi_args,
   9053     1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
   9054   { 1, Iclass_xt_iclass_wsr_acchi_args,
   9055     1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
   9056   { 1, Iclass_xt_iclass_xsr_acchi_args,
   9057     1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
   9058   { 1, Iclass_xt_iclass_rfi_args,
   9059     21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
   9060   { 1, Iclass_xt_iclass_wait_args,
   9061     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
   9062   { 1, Iclass_xt_iclass_rsr_interrupt_args,
   9063     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
   9064   { 1, Iclass_xt_iclass_wsr_intset_args,
   9065     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
   9066   { 1, Iclass_xt_iclass_wsr_intclear_args,
   9067     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
   9068   { 1, Iclass_xt_iclass_rsr_intenable_args,
   9069     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
   9070   { 1, Iclass_xt_iclass_wsr_intenable_args,
   9071     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
   9072   { 1, Iclass_xt_iclass_xsr_intenable_args,
   9073     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
   9074   { 2, Iclass_xt_iclass_break_args,
   9075     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
   9076   { 1, Iclass_xt_iclass_break_n_args,
   9077     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
   9078   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
   9079     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
   9080   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
   9081     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
   9082   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
   9083     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
   9084   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
   9085     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
   9086   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
   9087     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
   9088   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
   9089     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
   9090   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
   9091     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
   9092   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
   9093     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
   9094   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
   9095     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
   9096   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
   9097     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
   9098   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
   9099     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
   9100   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
   9101     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
   9102   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
   9103     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
   9104   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
   9105     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
   9106   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
   9107     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
   9108   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
   9109     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
   9110   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
   9111     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
   9112   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
   9113     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
   9114   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
   9115     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
   9116   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
   9117     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
   9118   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
   9119     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
   9120   { 1, Iclass_xt_iclass_rsr_debugcause_args,
   9121     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
   9122   { 1, Iclass_xt_iclass_wsr_debugcause_args,
   9123     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
   9124   { 1, Iclass_xt_iclass_xsr_debugcause_args,
   9125     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
   9126   { 1, Iclass_xt_iclass_rsr_icount_args,
   9127     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
   9128   { 1, Iclass_xt_iclass_wsr_icount_args,
   9129     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
   9130   { 1, Iclass_xt_iclass_xsr_icount_args,
   9131     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
   9132   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
   9133     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
   9134   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
   9135     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
   9136   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
   9137     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
   9138   { 1, Iclass_xt_iclass_rsr_ddr_args,
   9139     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
   9140   { 1, Iclass_xt_iclass_wsr_ddr_args,
   9141     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
   9142   { 1, Iclass_xt_iclass_xsr_ddr_args,
   9143     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
   9144   { 1, Iclass_xt_iclass_lddr32_p_args,
   9145     5, Iclass_xt_iclass_lddr32_p_stateArgs, 0, 0 },
   9146   { 1, Iclass_xt_iclass_sddr32_p_args,
   9147     4, Iclass_xt_iclass_sddr32_p_stateArgs, 0, 0 },
   9148   { 1, Iclass_xt_iclass_rfdo_args,
   9149     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
   9150   { 0, 0 /* xt_iclass_rfdd */,
   9151     2, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
   9152   { 1, Iclass_xt_iclass_wsr_mmid_args,
   9153     3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
   9154   { 3, Iclass_xt_iclass_bbool1_args,
   9155     0, 0, 0, 0 },
   9156   { 2, Iclass_xt_iclass_bbool4_args,
   9157     0, 0, 0, 0 },
   9158   { 2, Iclass_xt_iclass_bbool8_args,
   9159     0, 0, 0, 0 },
   9160   { 2, Iclass_xt_iclass_bbranch_args,
   9161     0, 0, 0, 0 },
   9162   { 3, Iclass_xt_iclass_bmove_args,
   9163     0, 0, 0, 0 },
   9164   { 2, Iclass_xt_iclass_RSR_BR_args,
   9165     0, 0, 0, 0 },
   9166   { 2, Iclass_xt_iclass_WSR_BR_args,
   9167     0, 0, 0, 0 },
   9168   { 2, Iclass_xt_iclass_XSR_BR_args,
   9169     0, 0, 0, 0 },
   9170   { 1, Iclass_xt_iclass_rsr_ccount_args,
   9171     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
   9172   { 1, Iclass_xt_iclass_wsr_ccount_args,
   9173     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
   9174   { 1, Iclass_xt_iclass_xsr_ccount_args,
   9175     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
   9176   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
   9177     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
   9178   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
   9179     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
   9180   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
   9181     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
   9182   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
   9183     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
   9184   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
   9185     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
   9186   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
   9187     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
   9188   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
   9189     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
   9190   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
   9191     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
   9192   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
   9193     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
   9194   { 2, Iclass_xt_iclass_icache_args,
   9195     0, 0, 0, 0 },
   9196   { 2, Iclass_xt_iclass_icache_lock_args,
   9197     2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
   9198   { 2, Iclass_xt_iclass_icache_inv_args,
   9199     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
   9200   { 2, Iclass_xt_iclass_licx_args,
   9201     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
   9202   { 2, Iclass_xt_iclass_sicx_args,
   9203     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
   9204   { 2, Iclass_xt_iclass_dcache_args,
   9205     0, 0, 0, 0 },
   9206   { 1, Iclass_xt_iclass_dcache_dyn_args,
   9207     2, Iclass_xt_iclass_dcache_dyn_stateArgs, 0, 0 },
   9208   { 2, Iclass_xt_iclass_dcache_ind_args,
   9209     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
   9210   { 2, Iclass_xt_iclass_dcache_inv_args,
   9211     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
   9212   { 2, Iclass_xt_iclass_dpf_args,
   9213     0, 0, 0, 0 },
   9214   { 2, Iclass_xt_iclass_dcache_lock_args,
   9215     2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
   9216   { 2, Iclass_xt_iclass_sdct_args,
   9217     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
   9218   { 2, Iclass_xt_iclass_ldct_args,
   9219     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
   9220   { 2, Iclass_xt_iclass_sdcw_args,
   9221     2, Iclass_xt_iclass_sdcw_stateArgs, 0, 0 },
   9222   { 2, Iclass_xt_iclass_ldcw_args,
   9223     2, Iclass_xt_iclass_ldcw_stateArgs, 0, 0 },
   9224   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
   9225     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
   9226   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
   9227     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
   9228   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
   9229     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
   9230   { 1, Iclass_xt_iclass_rsr_rasid_args,
   9231     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
   9232   { 1, Iclass_xt_iclass_wsr_rasid_args,
   9233     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
   9234   { 1, Iclass_xt_iclass_xsr_rasid_args,
   9235     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
   9236   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
   9237     5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
   9238   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
   9239     6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
   9240   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
   9241     6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
   9242   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
   9243     5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
   9244   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
   9245     6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
   9246   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
   9247     6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
   9248   { 1, Iclass_xt_iclass_idtlb_args,
   9249     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
   9250   { 2, Iclass_xt_iclass_rdtlb_args,
   9251     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
   9252   { 2, Iclass_xt_iclass_wdtlb_args,
   9253     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
   9254   { 1, Iclass_xt_iclass_iitlb_args,
   9255     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
   9256   { 2, Iclass_xt_iclass_ritlb_args,
   9257     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
   9258   { 2, Iclass_xt_iclass_witlb_args,
   9259     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
   9260   { 0, 0 /* xt_iclass_ldpte */,
   9261     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
   9262   { 0, 0 /* xt_iclass_hwwitlba */,
   9263     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
   9264   { 0, 0 /* xt_iclass_hwwdtlba */,
   9265     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
   9266   { 1, Iclass_xt_iclass_rsr_cpenable_args,
   9267     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
   9268   { 1, Iclass_xt_iclass_wsr_cpenable_args,
   9269     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
   9270   { 1, Iclass_xt_iclass_xsr_cpenable_args,
   9271     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
   9272   { 3, Iclass_xt_iclass_clamp_args,
   9273     0, 0, 0, 0 },
   9274   { 3, Iclass_xt_iclass_minmax_args,
   9275     0, 0, 0, 0 },
   9276   { 2, Iclass_xt_iclass_nsa_args,
   9277     0, 0, 0, 0 },
   9278   { 3, Iclass_xt_iclass_sx_args,
   9279     0, 0, 0, 0 },
   9280   { 3, Iclass_xt_iclass_l32ai_args,
   9281     0, 0, 0, 0 },
   9282   { 3, Iclass_xt_iclass_s32ri_args,
   9283     0, 0, 0, 0 },
   9284   { 3, Iclass_xt_iclass_s32c1i_args,
   9285     3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
   9286   { 1, Iclass_xt_iclass_rsr_scompare1_args,
   9287     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
   9288   { 1, Iclass_xt_iclass_wsr_scompare1_args,
   9289     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
   9290   { 1, Iclass_xt_iclass_xsr_scompare1_args,
   9291     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
   9292   { 1, Iclass_xt_iclass_rsr_atomctl_args,
   9293     3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
   9294   { 1, Iclass_xt_iclass_wsr_atomctl_args,
   9295     4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
   9296   { 1, Iclass_xt_iclass_xsr_atomctl_args,
   9297     4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
   9298   { 3, Iclass_xt_iclass_div_args,
   9299     0, 0, 0, 0 },
   9300   { 1, Iclass_xt_iclass_rsr_eraccess_args,
   9301     3, Iclass_xt_iclass_rsr_eraccess_stateArgs, 0, 0 },
   9302   { 1, Iclass_xt_iclass_wsr_eraccess_args,
   9303     3, Iclass_xt_iclass_wsr_eraccess_stateArgs, 0, 0 },
   9304   { 1, Iclass_xt_iclass_xsr_eraccess_args,
   9305     3, Iclass_xt_iclass_xsr_eraccess_stateArgs, 0, 0 },
   9306   { 2, Iclass_xt_iclass_rer_args,
   9307     3, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
   9308   { 2, Iclass_xt_iclass_wer_args,
   9309     3, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
   9310   { 1, Iclass_rur_fcr_args,
   9311     9, Iclass_rur_fcr_stateArgs, 0, 0 },
   9312   { 1, Iclass_wur_fcr_args,
   9313     9, Iclass_wur_fcr_stateArgs, 0, 0 },
   9314   { 1, Iclass_rur_fsr_args,
   9315     8, Iclass_rur_fsr_stateArgs, 0, 0 },
   9316   { 1, Iclass_wur_fsr_args,
   9317     8, Iclass_wur_fsr_stateArgs, 0, 0 },
   9318   { 1, Iclass_iclass_READ_IMPWIRE_args,
   9319     1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
   9320   { 1, Iclass_iclass_SETB_EXPSTATE_args,
   9321     2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
   9322   { 1, Iclass_iclass_CLRB_EXPSTATE_args,
   9323     2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
   9324   { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
   9325     2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 },
   9326   { 1, Iclass_rur_expstate_args,
   9327     2, Iclass_rur_expstate_stateArgs, 0, 0 },
   9328   { 1, Iclass_wur_expstate_args,
   9329     2, Iclass_wur_expstate_stateArgs, 0, 0 },
   9330   { 3, Iclass_LSI_args,
   9331     1, Iclass_LSI_stateArgs, 0, 0 },
   9332   { 3, Iclass_LSIP_args,
   9333     1, Iclass_LSIP_stateArgs, 0, 0 },
   9334   { 3, Iclass_LSX_args,
   9335     1, Iclass_LSX_stateArgs, 0, 0 },
   9336   { 3, Iclass_LSXP_args,
   9337     1, Iclass_LSXP_stateArgs, 0, 0 },
   9338   { 3, Iclass_SSI_args,
   9339     1, Iclass_SSI_stateArgs, 0, 0 },
   9340   { 3, Iclass_SSIP_args,
   9341     1, Iclass_SSIP_stateArgs, 0, 0 },
   9342   { 3, Iclass_SSX_args,
   9343     1, Iclass_SSX_stateArgs, 0, 0 },
   9344   { 3, Iclass_SSXP_args,
   9345     1, Iclass_SSXP_stateArgs, 0, 0 },
   9346   { 3, Iclass_LDI_args,
   9347     1, Iclass_LDI_stateArgs, 0, 0 },
   9348   { 3, Iclass_LDIP_args,
   9349     1, Iclass_LDIP_stateArgs, 0, 0 },
   9350   { 3, Iclass_LDX_args,
   9351     1, Iclass_LDX_stateArgs, 0, 0 },
   9352   { 3, Iclass_LDXP_args,
   9353     1, Iclass_LDXP_stateArgs, 0, 0 },
   9354   { 3, Iclass_SDI_args,
   9355     1, Iclass_SDI_stateArgs, 0, 0 },
   9356   { 3, Iclass_SDIP_args,
   9357     1, Iclass_SDIP_stateArgs, 0, 0 },
   9358   { 3, Iclass_SDX_args,
   9359     1, Iclass_SDX_stateArgs, 0, 0 },
   9360   { 3, Iclass_SDXP_args,
   9361     1, Iclass_SDXP_stateArgs, 0, 0 },
   9362   { 2, Iclass_ABS_S_args,
   9363     1, Iclass_ABS_S_stateArgs, 0, 0 },
   9364   { 2, Iclass_NEG_S_args,
   9365     1, Iclass_NEG_S_stateArgs, 0, 0 },
   9366   { 2, Iclass_ABS_D_args,
   9367     1, Iclass_ABS_D_stateArgs, 0, 0 },
   9368   { 2, Iclass_NEG_D_args,
   9369     1, Iclass_NEG_D_stateArgs, 0, 0 },
   9370   { 2, Iclass_MOV_S_args,
   9371     1, Iclass_MOV_S_stateArgs, 0, 0 },
   9372   { 2, Iclass_MOV_D_args,
   9373     1, Iclass_MOV_D_stateArgs, 0, 0 },
   9374   { 3, Iclass_MOVEQZ_S_args,
   9375     1, Iclass_MOVEQZ_S_stateArgs, 0, 0 },
   9376   { 3, Iclass_MOVNEZ_S_args,
   9377     1, Iclass_MOVNEZ_S_stateArgs, 0, 0 },
   9378   { 3, Iclass_MOVLTZ_S_args,
   9379     1, Iclass_MOVLTZ_S_stateArgs, 0, 0 },
   9380   { 3, Iclass_MOVGEZ_S_args,
   9381     1, Iclass_MOVGEZ_S_stateArgs, 0, 0 },
   9382   { 3, Iclass_MOVF_S_args,
   9383     1, Iclass_MOVF_S_stateArgs, 0, 0 },
   9384   { 3, Iclass_MOVT_S_args,
   9385     1, Iclass_MOVT_S_stateArgs, 0, 0 },
   9386   { 2, Iclass_WFR_args,
   9387     1, Iclass_WFR_stateArgs, 0, 0 },
   9388   { 2, Iclass_RFR_args,
   9389     1, Iclass_RFR_stateArgs, 0, 0 },
   9390   { 2, Iclass_RFRD_args,
   9391     1, Iclass_RFRD_stateArgs, 0, 0 },
   9392   { 3, Iclass_WFRD_args,
   9393     1, Iclass_WFRD_stateArgs, 0, 0 },
   9394   { 3, Iclass_ROUND_S_args,
   9395     3, Iclass_ROUND_S_stateArgs, 0, 0 },
   9396   { 3, Iclass_ROUND_D_args,
   9397     3, Iclass_ROUND_D_stateArgs, 0, 0 },
   9398   { 3, Iclass_CEIL_S_args,
   9399     3, Iclass_CEIL_S_stateArgs, 0, 0 },
   9400   { 3, Iclass_CEIL_D_args,
   9401     3, Iclass_CEIL_D_stateArgs, 0, 0 },
   9402   { 3, Iclass_FLOOR_S_args,
   9403     3, Iclass_FLOOR_S_stateArgs, 0, 0 },
   9404   { 3, Iclass_FLOOR_D_args,
   9405     3, Iclass_FLOOR_D_stateArgs, 0, 0 },
   9406   { 3, Iclass_TRUNC_S_args,
   9407     3, Iclass_TRUNC_S_stateArgs, 0, 0 },
   9408   { 3, Iclass_TRUNC_D_args,
   9409     3, Iclass_TRUNC_D_stateArgs, 0, 0 },
   9410   { 3, Iclass_UTRUNC_S_args,
   9411     3, Iclass_UTRUNC_S_stateArgs, 0, 0 },
   9412   { 3, Iclass_UTRUNC_D_args,
   9413     3, Iclass_UTRUNC_D_stateArgs, 0, 0 },
   9414   { 3, Iclass_FLOAT_S_args,
   9415     3, Iclass_FLOAT_S_stateArgs, 0, 0 },
   9416   { 3, Iclass_FLOAT_D_args,
   9417     2, Iclass_FLOAT_D_stateArgs, 0, 0 },
   9418   { 3, Iclass_UFLOAT_S_args,
   9419     3, Iclass_UFLOAT_S_stateArgs, 0, 0 },
   9420   { 3, Iclass_UFLOAT_D_args,
   9421     2, Iclass_UFLOAT_D_stateArgs, 0, 0 },
   9422   { 2, Iclass_CVTD_S_args,
   9423     2, Iclass_CVTD_S_stateArgs, 0, 0 },
   9424   { 2, Iclass_CVTS_D_args,
   9425     6, Iclass_CVTS_D_stateArgs, 0, 0 },
   9426   { 3, Iclass_UN_S_args,
   9427     2, Iclass_UN_S_stateArgs, 0, 0 },
   9428   { 3, Iclass_UN_D_args,
   9429     2, Iclass_UN_D_stateArgs, 0, 0 },
   9430   { 3, Iclass_ULT_S_args,
   9431     2, Iclass_ULT_S_stateArgs, 0, 0 },
   9432   { 3, Iclass_ULT_D_args,
   9433     2, Iclass_ULT_D_stateArgs, 0, 0 },
   9434   { 3, Iclass_ULE_S_args,
   9435     2, Iclass_ULE_S_stateArgs, 0, 0 },
   9436   { 3, Iclass_ULE_D_args,
   9437     2, Iclass_ULE_D_stateArgs, 0, 0 },
   9438   { 3, Iclass_UEQ_S_args,
   9439     2, Iclass_UEQ_S_stateArgs, 0, 0 },
   9440   { 3, Iclass_UEQ_D_args,
   9441     2, Iclass_UEQ_D_stateArgs, 0, 0 },
   9442   { 3, Iclass_OLT_S_args,
   9443     2, Iclass_OLT_S_stateArgs, 0, 0 },
   9444   { 3, Iclass_OLT_D_args,
   9445     2, Iclass_OLT_D_stateArgs, 0, 0 },
   9446   { 3, Iclass_OLE_S_args,
   9447     2, Iclass_OLE_S_stateArgs, 0, 0 },
   9448   { 3, Iclass_OLE_D_args,
   9449     2, Iclass_OLE_D_stateArgs, 0, 0 },
   9450   { 3, Iclass_OEQ_S_args,
   9451     2, Iclass_OEQ_S_stateArgs, 0, 0 },
   9452   { 3, Iclass_OEQ_D_args,
   9453     2, Iclass_OEQ_D_stateArgs, 0, 0 },
   9454   { 3, Iclass_ADD_S_args,
   9455     6, Iclass_ADD_S_stateArgs, 0, 0 },
   9456   { 3, Iclass_ADD_D_args,
   9457     6, Iclass_ADD_D_stateArgs, 0, 0 },
   9458   { 3, Iclass_SUB_S_args,
   9459     6, Iclass_SUB_S_stateArgs, 0, 0 },
   9460   { 3, Iclass_SUB_D_args,
   9461     6, Iclass_SUB_D_stateArgs, 0, 0 },
   9462   { 3, Iclass_MUL_S_args,
   9463     6, Iclass_MUL_S_stateArgs, 0, 0 },
   9464   { 3, Iclass_MUL_D_args,
   9465     6, Iclass_MUL_D_stateArgs, 0, 0 },
   9466   { 3, Iclass_MADD_S_args,
   9467     6, Iclass_MADD_S_stateArgs, 0, 0 },
   9468   { 3, Iclass_MADD_D_args,
   9469     6, Iclass_MADD_D_stateArgs, 0, 0 },
   9470   { 3, Iclass_MSUB_S_args,
   9471     6, Iclass_MSUB_S_stateArgs, 0, 0 },
   9472   { 3, Iclass_MSUB_D_args,
   9473     6, Iclass_MSUB_D_stateArgs, 0, 0 },
   9474   { 2, Iclass_SQRT0_S_args,
   9475     1, Iclass_SQRT0_S_stateArgs, 0, 0 },
   9476   { 2, Iclass_SQRT0_D_args,
   9477     1, Iclass_SQRT0_D_stateArgs, 0, 0 },
   9478   { 2, Iclass_DIV0_S_args,
   9479     1, Iclass_DIV0_S_stateArgs, 0, 0 },
   9480   { 2, Iclass_DIV0_D_args,
   9481     1, Iclass_DIV0_D_stateArgs, 0, 0 },
   9482   { 2, Iclass_RECIP0_S_args,
   9483     3, Iclass_RECIP0_S_stateArgs, 0, 0 },
   9484   { 2, Iclass_RECIP0_D_args,
   9485     3, Iclass_RECIP0_D_stateArgs, 0, 0 },
   9486   { 2, Iclass_RSQRT0_S_args,
   9487     3, Iclass_RSQRT0_S_stateArgs, 0, 0 },
   9488   { 2, Iclass_RSQRT0_D_args,
   9489     3, Iclass_RSQRT0_D_stateArgs, 0, 0 },
   9490   { 3, Iclass_MADDN_S_args,
   9491     1, Iclass_MADDN_S_stateArgs, 0, 0 },
   9492   { 3, Iclass_MADDN_D_args,
   9493     1, Iclass_MADDN_D_stateArgs, 0, 0 },
   9494   { 3, Iclass_DIVN_S_args,
   9495     5, Iclass_DIVN_S_stateArgs, 0, 0 },
   9496   { 3, Iclass_DIVN_D_args,
   9497     5, Iclass_DIVN_D_stateArgs, 0, 0 },
   9498   { 2, Iclass_CONST_S_args,
   9499     1, Iclass_CONST_S_stateArgs, 0, 0 },
   9500   { 2, Iclass_CONST_D_args,
   9501     1, Iclass_CONST_D_stateArgs, 0, 0 },
   9502   { 2, Iclass_NEXP01_S_args,
   9503     1, Iclass_NEXP01_S_stateArgs, 0, 0 },
   9504   { 2, Iclass_NEXP01_D_args,
   9505     1, Iclass_NEXP01_D_stateArgs, 0, 0 },
   9506   { 2, Iclass_ADDEXP_S_args,
   9507     1, Iclass_ADDEXP_S_stateArgs, 0, 0 },
   9508   { 2, Iclass_ADDEXP_D_args,
   9509     1, Iclass_ADDEXP_D_stateArgs, 0, 0 },
   9510   { 2, Iclass_ADDEXPM_S_args,
   9511     1, Iclass_ADDEXPM_S_stateArgs, 0, 0 },
   9512   { 2, Iclass_ADDEXPM_D_args,
   9513     1, Iclass_ADDEXPM_D_stateArgs, 0, 0 },
   9514   { 2, Iclass_MKDADJ_S_args,
   9515     3, Iclass_MKDADJ_S_stateArgs, 0, 0 },
   9516   { 2, Iclass_MKDADJ_D_args,
   9517     3, Iclass_MKDADJ_D_stateArgs, 0, 0 },
   9518   { 2, Iclass_MKSADJ_S_args,
   9519     2, Iclass_MKSADJ_S_stateArgs, 0, 0 },
   9520   { 2, Iclass_MKSADJ_D_args,
   9521     2, Iclass_MKSADJ_D_stateArgs, 0, 0 }
   9522 };
   9523 
   9524 enum xtensa_iclass_id {
   9525   ICLASS_xt_iclass_excw,
   9526   ICLASS_xt_iclass_rfe,
   9527   ICLASS_xt_iclass_rfde,
   9528   ICLASS_xt_iclass_syscall,
   9529   ICLASS_xt_iclass_call12,
   9530   ICLASS_xt_iclass_call8,
   9531   ICLASS_xt_iclass_call4,
   9532   ICLASS_xt_iclass_callx12,
   9533   ICLASS_xt_iclass_callx8,
   9534   ICLASS_xt_iclass_callx4,
   9535   ICLASS_xt_iclass_entry,
   9536   ICLASS_xt_iclass_movsp,
   9537   ICLASS_xt_iclass_rotw,
   9538   ICLASS_xt_iclass_retw,
   9539   ICLASS_xt_iclass_rfwou,
   9540   ICLASS_xt_iclass_l32e,
   9541   ICLASS_xt_iclass_s32e,
   9542   ICLASS_xt_iclass_rsr_windowbase,
   9543   ICLASS_xt_iclass_wsr_windowbase,
   9544   ICLASS_xt_iclass_xsr_windowbase,
   9545   ICLASS_xt_iclass_rsr_windowstart,
   9546   ICLASS_xt_iclass_wsr_windowstart,
   9547   ICLASS_xt_iclass_xsr_windowstart,
   9548   ICLASS_xt_iclass_add_n,
   9549   ICLASS_xt_iclass_addi_n,
   9550   ICLASS_xt_iclass_bz6,
   9551   ICLASS_xt_iclass_ill_n,
   9552   ICLASS_xt_iclass_loadi4,
   9553   ICLASS_xt_iclass_mov_n,
   9554   ICLASS_xt_iclass_movi_n,
   9555   ICLASS_xt_iclass_nopn,
   9556   ICLASS_xt_iclass_retn,
   9557   ICLASS_xt_iclass_storei4,
   9558   ICLASS_rur_threadptr,
   9559   ICLASS_wur_threadptr,
   9560   ICLASS_xt_iclass_addi,
   9561   ICLASS_xt_iclass_addmi,
   9562   ICLASS_xt_iclass_addsub,
   9563   ICLASS_xt_iclass_bit,
   9564   ICLASS_xt_iclass_bsi8,
   9565   ICLASS_xt_iclass_bsi8b,
   9566   ICLASS_xt_iclass_bsi8u,
   9567   ICLASS_xt_iclass_bst8,
   9568   ICLASS_xt_iclass_bsz12,
   9569   ICLASS_xt_iclass_call0,
   9570   ICLASS_xt_iclass_callx0,
   9571   ICLASS_xt_iclass_exti,
   9572   ICLASS_xt_iclass_ill,
   9573   ICLASS_xt_iclass_jump,
   9574   ICLASS_xt_iclass_jumpx,
   9575   ICLASS_xt_iclass_l16ui,
   9576   ICLASS_xt_iclass_l16si,
   9577   ICLASS_xt_iclass_l32i,
   9578   ICLASS_xt_iclass_l32r,
   9579   ICLASS_xt_iclass_l8i,
   9580   ICLASS_xt_iclass_loop,
   9581   ICLASS_xt_iclass_loopz,
   9582   ICLASS_xt_iclass_movi,
   9583   ICLASS_xt_iclass_movz,
   9584   ICLASS_xt_iclass_neg,
   9585   ICLASS_xt_iclass_nop,
   9586   ICLASS_xt_iclass_return,
   9587   ICLASS_xt_iclass_simcall,
   9588   ICLASS_xt_iclass_s16i,
   9589   ICLASS_xt_iclass_s32i,
   9590   ICLASS_xt_iclass_s32nb,
   9591   ICLASS_xt_iclass_s8i,
   9592   ICLASS_xt_iclass_sar,
   9593   ICLASS_xt_iclass_sari,
   9594   ICLASS_xt_iclass_shifts,
   9595   ICLASS_xt_iclass_shiftst,
   9596   ICLASS_xt_iclass_shiftt,
   9597   ICLASS_xt_iclass_slli,
   9598   ICLASS_xt_iclass_srai,
   9599   ICLASS_xt_iclass_srli,
   9600   ICLASS_xt_iclass_memw,
   9601   ICLASS_xt_iclass_extw,
   9602   ICLASS_xt_iclass_isync,
   9603   ICLASS_xt_iclass_sync,
   9604   ICLASS_xt_iclass_rsil,
   9605   ICLASS_xt_iclass_rsr_lend,
   9606   ICLASS_xt_iclass_wsr_lend,
   9607   ICLASS_xt_iclass_xsr_lend,
   9608   ICLASS_xt_iclass_rsr_lcount,
   9609   ICLASS_xt_iclass_wsr_lcount,
   9610   ICLASS_xt_iclass_xsr_lcount,
   9611   ICLASS_xt_iclass_rsr_lbeg,
   9612   ICLASS_xt_iclass_wsr_lbeg,
   9613   ICLASS_xt_iclass_xsr_lbeg,
   9614   ICLASS_xt_iclass_rsr_sar,
   9615   ICLASS_xt_iclass_wsr_sar,
   9616   ICLASS_xt_iclass_xsr_sar,
   9617   ICLASS_xt_iclass_rsr_memctl,
   9618   ICLASS_xt_iclass_wsr_memctl,
   9619   ICLASS_xt_iclass_xsr_memctl,
   9620   ICLASS_xt_iclass_rsr_configid0,
   9621   ICLASS_xt_iclass_wsr_configid0,
   9622   ICLASS_xt_iclass_rsr_configid1,
   9623   ICLASS_xt_iclass_rsr_ps,
   9624   ICLASS_xt_iclass_wsr_ps,
   9625   ICLASS_xt_iclass_xsr_ps,
   9626   ICLASS_xt_iclass_rsr_epc1,
   9627   ICLASS_xt_iclass_wsr_epc1,
   9628   ICLASS_xt_iclass_xsr_epc1,
   9629   ICLASS_xt_iclass_rsr_excsave1,
   9630   ICLASS_xt_iclass_wsr_excsave1,
   9631   ICLASS_xt_iclass_xsr_excsave1,
   9632   ICLASS_xt_iclass_rsr_epc2,
   9633   ICLASS_xt_iclass_wsr_epc2,
   9634   ICLASS_xt_iclass_xsr_epc2,
   9635   ICLASS_xt_iclass_rsr_excsave2,
   9636   ICLASS_xt_iclass_wsr_excsave2,
   9637   ICLASS_xt_iclass_xsr_excsave2,
   9638   ICLASS_xt_iclass_rsr_epc3,
   9639   ICLASS_xt_iclass_wsr_epc3,
   9640   ICLASS_xt_iclass_xsr_epc3,
   9641   ICLASS_xt_iclass_rsr_excsave3,
   9642   ICLASS_xt_iclass_wsr_excsave3,
   9643   ICLASS_xt_iclass_xsr_excsave3,
   9644   ICLASS_xt_iclass_rsr_epc4,
   9645   ICLASS_xt_iclass_wsr_epc4,
   9646   ICLASS_xt_iclass_xsr_epc4,
   9647   ICLASS_xt_iclass_rsr_excsave4,
   9648   ICLASS_xt_iclass_wsr_excsave4,
   9649   ICLASS_xt_iclass_xsr_excsave4,
   9650   ICLASS_xt_iclass_rsr_epc5,
   9651   ICLASS_xt_iclass_wsr_epc5,
   9652   ICLASS_xt_iclass_xsr_epc5,
   9653   ICLASS_xt_iclass_rsr_excsave5,
   9654   ICLASS_xt_iclass_wsr_excsave5,
   9655   ICLASS_xt_iclass_xsr_excsave5,
   9656   ICLASS_xt_iclass_rsr_epc6,
   9657   ICLASS_xt_iclass_wsr_epc6,
   9658   ICLASS_xt_iclass_xsr_epc6,
   9659   ICLASS_xt_iclass_rsr_excsave6,
   9660   ICLASS_xt_iclass_wsr_excsave6,
   9661   ICLASS_xt_iclass_xsr_excsave6,
   9662   ICLASS_xt_iclass_rsr_epc7,
   9663   ICLASS_xt_iclass_wsr_epc7,
   9664   ICLASS_xt_iclass_xsr_epc7,
   9665   ICLASS_xt_iclass_rsr_excsave7,
   9666   ICLASS_xt_iclass_wsr_excsave7,
   9667   ICLASS_xt_iclass_xsr_excsave7,
   9668   ICLASS_xt_iclass_rsr_eps2,
   9669   ICLASS_xt_iclass_wsr_eps2,
   9670   ICLASS_xt_iclass_xsr_eps2,
   9671   ICLASS_xt_iclass_rsr_eps3,
   9672   ICLASS_xt_iclass_wsr_eps3,
   9673   ICLASS_xt_iclass_xsr_eps3,
   9674   ICLASS_xt_iclass_rsr_eps4,
   9675   ICLASS_xt_iclass_wsr_eps4,
   9676   ICLASS_xt_iclass_xsr_eps4,
   9677   ICLASS_xt_iclass_rsr_eps5,
   9678   ICLASS_xt_iclass_wsr_eps5,
   9679   ICLASS_xt_iclass_xsr_eps5,
   9680   ICLASS_xt_iclass_rsr_eps6,
   9681   ICLASS_xt_iclass_wsr_eps6,
   9682   ICLASS_xt_iclass_xsr_eps6,
   9683   ICLASS_xt_iclass_rsr_eps7,
   9684   ICLASS_xt_iclass_wsr_eps7,
   9685   ICLASS_xt_iclass_xsr_eps7,
   9686   ICLASS_xt_iclass_rsr_excvaddr,
   9687   ICLASS_xt_iclass_wsr_excvaddr,
   9688   ICLASS_xt_iclass_xsr_excvaddr,
   9689   ICLASS_xt_iclass_rsr_depc,
   9690   ICLASS_xt_iclass_wsr_depc,
   9691   ICLASS_xt_iclass_xsr_depc,
   9692   ICLASS_xt_iclass_rsr_exccause,
   9693   ICLASS_xt_iclass_wsr_exccause,
   9694   ICLASS_xt_iclass_xsr_exccause,
   9695   ICLASS_xt_iclass_rsr_misc0,
   9696   ICLASS_xt_iclass_wsr_misc0,
   9697   ICLASS_xt_iclass_xsr_misc0,
   9698   ICLASS_xt_iclass_rsr_misc1,
   9699   ICLASS_xt_iclass_wsr_misc1,
   9700   ICLASS_xt_iclass_xsr_misc1,
   9701   ICLASS_xt_iclass_rsr_prid,
   9702   ICLASS_xt_iclass_rsr_vecbase,
   9703   ICLASS_xt_iclass_wsr_vecbase,
   9704   ICLASS_xt_iclass_xsr_vecbase,
   9705   ICLASS_xt_iclass_salt,
   9706   ICLASS_xt_mul16,
   9707   ICLASS_xt_mul32,
   9708   ICLASS_xt_iclass_mac16_aa,
   9709   ICLASS_xt_iclass_mac16_ad,
   9710   ICLASS_xt_iclass_mac16_da,
   9711   ICLASS_xt_iclass_mac16_dd,
   9712   ICLASS_xt_iclass_mac16a_aa,
   9713   ICLASS_xt_iclass_mac16a_ad,
   9714   ICLASS_xt_iclass_mac16a_da,
   9715   ICLASS_xt_iclass_mac16a_dd,
   9716   ICLASS_xt_iclass_mac16al_da,
   9717   ICLASS_xt_iclass_mac16al_dd,
   9718   ICLASS_xt_iclass_mac16_l,
   9719   ICLASS_xt_iclass_rsr_m0,
   9720   ICLASS_xt_iclass_wsr_m0,
   9721   ICLASS_xt_iclass_xsr_m0,
   9722   ICLASS_xt_iclass_rsr_m1,
   9723   ICLASS_xt_iclass_wsr_m1,
   9724   ICLASS_xt_iclass_xsr_m1,
   9725   ICLASS_xt_iclass_rsr_m2,
   9726   ICLASS_xt_iclass_wsr_m2,
   9727   ICLASS_xt_iclass_xsr_m2,
   9728   ICLASS_xt_iclass_rsr_m3,
   9729   ICLASS_xt_iclass_wsr_m3,
   9730   ICLASS_xt_iclass_xsr_m3,
   9731   ICLASS_xt_iclass_rsr_acclo,
   9732   ICLASS_xt_iclass_wsr_acclo,
   9733   ICLASS_xt_iclass_xsr_acclo,
   9734   ICLASS_xt_iclass_rsr_acchi,
   9735   ICLASS_xt_iclass_wsr_acchi,
   9736   ICLASS_xt_iclass_xsr_acchi,
   9737   ICLASS_xt_iclass_rfi,
   9738   ICLASS_xt_iclass_wait,
   9739   ICLASS_xt_iclass_rsr_interrupt,
   9740   ICLASS_xt_iclass_wsr_intset,
   9741   ICLASS_xt_iclass_wsr_intclear,
   9742   ICLASS_xt_iclass_rsr_intenable,
   9743   ICLASS_xt_iclass_wsr_intenable,
   9744   ICLASS_xt_iclass_xsr_intenable,
   9745   ICLASS_xt_iclass_break,
   9746   ICLASS_xt_iclass_break_n,
   9747   ICLASS_xt_iclass_rsr_dbreaka0,
   9748   ICLASS_xt_iclass_wsr_dbreaka0,
   9749   ICLASS_xt_iclass_xsr_dbreaka0,
   9750   ICLASS_xt_iclass_rsr_dbreakc0,
   9751   ICLASS_xt_iclass_wsr_dbreakc0,
   9752   ICLASS_xt_iclass_xsr_dbreakc0,
   9753   ICLASS_xt_iclass_rsr_dbreaka1,
   9754   ICLASS_xt_iclass_wsr_dbreaka1,
   9755   ICLASS_xt_iclass_xsr_dbreaka1,
   9756   ICLASS_xt_iclass_rsr_dbreakc1,
   9757   ICLASS_xt_iclass_wsr_dbreakc1,
   9758   ICLASS_xt_iclass_xsr_dbreakc1,
   9759   ICLASS_xt_iclass_rsr_ibreaka0,
   9760   ICLASS_xt_iclass_wsr_ibreaka0,
   9761   ICLASS_xt_iclass_xsr_ibreaka0,
   9762   ICLASS_xt_iclass_rsr_ibreaka1,
   9763   ICLASS_xt_iclass_wsr_ibreaka1,
   9764   ICLASS_xt_iclass_xsr_ibreaka1,
   9765   ICLASS_xt_iclass_rsr_ibreakenable,
   9766   ICLASS_xt_iclass_wsr_ibreakenable,
   9767   ICLASS_xt_iclass_xsr_ibreakenable,
   9768   ICLASS_xt_iclass_rsr_debugcause,
   9769   ICLASS_xt_iclass_wsr_debugcause,
   9770   ICLASS_xt_iclass_xsr_debugcause,
   9771   ICLASS_xt_iclass_rsr_icount,
   9772   ICLASS_xt_iclass_wsr_icount,
   9773   ICLASS_xt_iclass_xsr_icount,
   9774   ICLASS_xt_iclass_rsr_icountlevel,
   9775   ICLASS_xt_iclass_wsr_icountlevel,
   9776   ICLASS_xt_iclass_xsr_icountlevel,
   9777   ICLASS_xt_iclass_rsr_ddr,
   9778   ICLASS_xt_iclass_wsr_ddr,
   9779   ICLASS_xt_iclass_xsr_ddr,
   9780   ICLASS_xt_iclass_lddr32_p,
   9781   ICLASS_xt_iclass_sddr32_p,
   9782   ICLASS_xt_iclass_rfdo,
   9783   ICLASS_xt_iclass_rfdd,
   9784   ICLASS_xt_iclass_wsr_mmid,
   9785   ICLASS_xt_iclass_bbool1,
   9786   ICLASS_xt_iclass_bbool4,
   9787   ICLASS_xt_iclass_bbool8,
   9788   ICLASS_xt_iclass_bbranch,
   9789   ICLASS_xt_iclass_bmove,
   9790   ICLASS_xt_iclass_RSR_BR,
   9791   ICLASS_xt_iclass_WSR_BR,
   9792   ICLASS_xt_iclass_XSR_BR,
   9793   ICLASS_xt_iclass_rsr_ccount,
   9794   ICLASS_xt_iclass_wsr_ccount,
   9795   ICLASS_xt_iclass_xsr_ccount,
   9796   ICLASS_xt_iclass_rsr_ccompare0,
   9797   ICLASS_xt_iclass_wsr_ccompare0,
   9798   ICLASS_xt_iclass_xsr_ccompare0,
   9799   ICLASS_xt_iclass_rsr_ccompare1,
   9800   ICLASS_xt_iclass_wsr_ccompare1,
   9801   ICLASS_xt_iclass_xsr_ccompare1,
   9802   ICLASS_xt_iclass_rsr_ccompare2,
   9803   ICLASS_xt_iclass_wsr_ccompare2,
   9804   ICLASS_xt_iclass_xsr_ccompare2,
   9805   ICLASS_xt_iclass_icache,
   9806   ICLASS_xt_iclass_icache_lock,
   9807   ICLASS_xt_iclass_icache_inv,
   9808   ICLASS_xt_iclass_licx,
   9809   ICLASS_xt_iclass_sicx,
   9810   ICLASS_xt_iclass_dcache,
   9811   ICLASS_xt_iclass_dcache_dyn,
   9812   ICLASS_xt_iclass_dcache_ind,
   9813   ICLASS_xt_iclass_dcache_inv,
   9814   ICLASS_xt_iclass_dpf,
   9815   ICLASS_xt_iclass_dcache_lock,
   9816   ICLASS_xt_iclass_sdct,
   9817   ICLASS_xt_iclass_ldct,
   9818   ICLASS_xt_iclass_sdcw,
   9819   ICLASS_xt_iclass_ldcw,
   9820   ICLASS_xt_iclass_wsr_ptevaddr,
   9821   ICLASS_xt_iclass_rsr_ptevaddr,
   9822   ICLASS_xt_iclass_xsr_ptevaddr,
   9823   ICLASS_xt_iclass_rsr_rasid,
   9824   ICLASS_xt_iclass_wsr_rasid,
   9825   ICLASS_xt_iclass_xsr_rasid,
   9826   ICLASS_xt_iclass_rsr_itlbcfg,
   9827   ICLASS_xt_iclass_wsr_itlbcfg,
   9828   ICLASS_xt_iclass_xsr_itlbcfg,
   9829   ICLASS_xt_iclass_rsr_dtlbcfg,
   9830   ICLASS_xt_iclass_wsr_dtlbcfg,
   9831   ICLASS_xt_iclass_xsr_dtlbcfg,
   9832   ICLASS_xt_iclass_idtlb,
   9833   ICLASS_xt_iclass_rdtlb,
   9834   ICLASS_xt_iclass_wdtlb,
   9835   ICLASS_xt_iclass_iitlb,
   9836   ICLASS_xt_iclass_ritlb,
   9837   ICLASS_xt_iclass_witlb,
   9838   ICLASS_xt_iclass_ldpte,
   9839   ICLASS_xt_iclass_hwwitlba,
   9840   ICLASS_xt_iclass_hwwdtlba,
   9841   ICLASS_xt_iclass_rsr_cpenable,
   9842   ICLASS_xt_iclass_wsr_cpenable,
   9843   ICLASS_xt_iclass_xsr_cpenable,
   9844   ICLASS_xt_iclass_clamp,
   9845   ICLASS_xt_iclass_minmax,
   9846   ICLASS_xt_iclass_nsa,
   9847   ICLASS_xt_iclass_sx,
   9848   ICLASS_xt_iclass_l32ai,
   9849   ICLASS_xt_iclass_s32ri,
   9850   ICLASS_xt_iclass_s32c1i,
   9851   ICLASS_xt_iclass_rsr_scompare1,
   9852   ICLASS_xt_iclass_wsr_scompare1,
   9853   ICLASS_xt_iclass_xsr_scompare1,
   9854   ICLASS_xt_iclass_rsr_atomctl,
   9855   ICLASS_xt_iclass_wsr_atomctl,
   9856   ICLASS_xt_iclass_xsr_atomctl,
   9857   ICLASS_xt_iclass_div,
   9858   ICLASS_xt_iclass_rsr_eraccess,
   9859   ICLASS_xt_iclass_wsr_eraccess,
   9860   ICLASS_xt_iclass_xsr_eraccess,
   9861   ICLASS_xt_iclass_rer,
   9862   ICLASS_xt_iclass_wer,
   9863   ICLASS_rur_fcr,
   9864   ICLASS_wur_fcr,
   9865   ICLASS_rur_fsr,
   9866   ICLASS_wur_fsr,
   9867   ICLASS_iclass_READ_IMPWIRE,
   9868   ICLASS_iclass_SETB_EXPSTATE,
   9869   ICLASS_iclass_CLRB_EXPSTATE,
   9870   ICLASS_iclass_WRMSK_EXPSTATE,
   9871   ICLASS_rur_expstate,
   9872   ICLASS_wur_expstate,
   9873   ICLASS_LSI,
   9874   ICLASS_LSIP,
   9875   ICLASS_LSX,
   9876   ICLASS_LSXP,
   9877   ICLASS_SSI,
   9878   ICLASS_SSIP,
   9879   ICLASS_SSX,
   9880   ICLASS_SSXP,
   9881   ICLASS_LDI,
   9882   ICLASS_LDIP,
   9883   ICLASS_LDX,
   9884   ICLASS_LDXP,
   9885   ICLASS_SDI,
   9886   ICLASS_SDIP,
   9887   ICLASS_SDX,
   9888   ICLASS_SDXP,
   9889   ICLASS_ABS_S,
   9890   ICLASS_NEG_S,
   9891   ICLASS_ABS_D,
   9892   ICLASS_NEG_D,
   9893   ICLASS_MOV_S,
   9894   ICLASS_MOV_D,
   9895   ICLASS_MOVEQZ_S,
   9896   ICLASS_MOVNEZ_S,
   9897   ICLASS_MOVLTZ_S,
   9898   ICLASS_MOVGEZ_S,
   9899   ICLASS_MOVF_S,
   9900   ICLASS_MOVT_S,
   9901   ICLASS_WFR,
   9902   ICLASS_RFR,
   9903   ICLASS_RFRD,
   9904   ICLASS_WFRD,
   9905   ICLASS_ROUND_S,
   9906   ICLASS_ROUND_D,
   9907   ICLASS_CEIL_S,
   9908   ICLASS_CEIL_D,
   9909   ICLASS_FLOOR_S,
   9910   ICLASS_FLOOR_D,
   9911   ICLASS_TRUNC_S,
   9912   ICLASS_TRUNC_D,
   9913   ICLASS_UTRUNC_S,
   9914   ICLASS_UTRUNC_D,
   9915   ICLASS_FLOAT_S,
   9916   ICLASS_FLOAT_D,
   9917   ICLASS_UFLOAT_S,
   9918   ICLASS_UFLOAT_D,
   9919   ICLASS_CVTD_S,
   9920   ICLASS_CVTS_D,
   9921   ICLASS_UN_S,
   9922   ICLASS_UN_D,
   9923   ICLASS_ULT_S,
   9924   ICLASS_ULT_D,
   9925   ICLASS_ULE_S,
   9926   ICLASS_ULE_D,
   9927   ICLASS_UEQ_S,
   9928   ICLASS_UEQ_D,
   9929   ICLASS_OLT_S,
   9930   ICLASS_OLT_D,
   9931   ICLASS_OLE_S,
   9932   ICLASS_OLE_D,
   9933   ICLASS_OEQ_S,
   9934   ICLASS_OEQ_D,
   9935   ICLASS_ADD_S,
   9936   ICLASS_ADD_D,
   9937   ICLASS_SUB_S,
   9938   ICLASS_SUB_D,
   9939   ICLASS_MUL_S,
   9940   ICLASS_MUL_D,
   9941   ICLASS_MADD_S,
   9942   ICLASS_MADD_D,
   9943   ICLASS_MSUB_S,
   9944   ICLASS_MSUB_D,
   9945   ICLASS_SQRT0_S,
   9946   ICLASS_SQRT0_D,
   9947   ICLASS_DIV0_S,
   9948   ICLASS_DIV0_D,
   9949   ICLASS_RECIP0_S,
   9950   ICLASS_RECIP0_D,
   9951   ICLASS_RSQRT0_S,
   9952   ICLASS_RSQRT0_D,
   9953   ICLASS_MADDN_S,
   9954   ICLASS_MADDN_D,
   9955   ICLASS_DIVN_S,
   9956   ICLASS_DIVN_D,
   9957   ICLASS_CONST_S,
   9958   ICLASS_CONST_D,
   9959   ICLASS_NEXP01_S,
   9960   ICLASS_NEXP01_D,
   9961   ICLASS_ADDEXP_S,
   9962   ICLASS_ADDEXP_D,
   9963   ICLASS_ADDEXPM_S,
   9964   ICLASS_ADDEXPM_D,
   9965   ICLASS_MKDADJ_S,
   9966   ICLASS_MKDADJ_D,
   9967   ICLASS_MKSADJ_S,
   9968   ICLASS_MKSADJ_D
   9969 };
   9970 
   9971 
   9972 /*  Opcode encodings.  */
   9973 
   9974 static void
   9975 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9976 {
   9977   slotbuf[0] = 0x2080;
   9978 }
   9979 
   9980 static void
   9981 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9982 {
   9983   slotbuf[0] = 0x3000;
   9984 }
   9985 
   9986 static void
   9987 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9988 {
   9989   slotbuf[0] = 0x3200;
   9990 }
   9991 
   9992 static void
   9993 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9994 {
   9995   slotbuf[0] = 0x5000;
   9996 }
   9997 
   9998 static void
   9999 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10000 {
  10001   slotbuf[0] = 0x35;
  10002 }
  10003 
  10004 static void
  10005 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10006 {
  10007   slotbuf[0] = 0x25;
  10008 }
  10009 
  10010 static void
  10011 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10012 {
  10013   slotbuf[0] = 0x15;
  10014 }
  10015 
  10016 static void
  10017 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10018 {
  10019   slotbuf[0] = 0xf0;
  10020 }
  10021 
  10022 static void
  10023 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10024 {
  10025   slotbuf[0] = 0xe0;
  10026 }
  10027 
  10028 static void
  10029 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10030 {
  10031   slotbuf[0] = 0xd0;
  10032 }
  10033 
  10034 static void
  10035 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10036 {
  10037   slotbuf[0] = 0x36;
  10038 }
  10039 
  10040 static void
  10041 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10042 {
  10043   slotbuf[0] = 0x1000;
  10044 }
  10045 
  10046 static void
  10047 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10048 {
  10049   slotbuf[0] = 0x408000;
  10050 }
  10051 
  10052 static void
  10053 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10054 {
  10055   slotbuf[0] = 0x90;
  10056 }
  10057 
  10058 static void
  10059 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10060 {
  10061   slotbuf[0] = 0xf01d;
  10062 }
  10063 
  10064 static void
  10065 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10066 {
  10067   slotbuf[0] = 0x3400;
  10068 }
  10069 
  10070 static void
  10071 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10072 {
  10073   slotbuf[0] = 0x3500;
  10074 }
  10075 
  10076 static void
  10077 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10078 {
  10079   slotbuf[0] = 0x90000;
  10080 }
  10081 
  10082 static void
  10083 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10084 {
  10085   slotbuf[0] = 0x490000;
  10086 }
  10087 
  10088 static void
  10089 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10090 {
  10091   slotbuf[0] = 0x34800;
  10092 }
  10093 
  10094 static void
  10095 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10096 {
  10097   slotbuf[0] = 0x134800;
  10098 }
  10099 
  10100 static void
  10101 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10102 {
  10103   slotbuf[0] = 0x614800;
  10104 }
  10105 
  10106 static void
  10107 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10108 {
  10109   slotbuf[0] = 0x34900;
  10110 }
  10111 
  10112 static void
  10113 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10114 {
  10115   slotbuf[0] = 0x134900;
  10116 }
  10117 
  10118 static void
  10119 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10120 {
  10121   slotbuf[0] = 0x614900;
  10122 }
  10123 
  10124 static void
  10125 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  10126 {
  10127   slotbuf[0] = 0xa;
  10128 }
  10129 
  10130 static void
  10131 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  10132 {
  10133   slotbuf[0] = 0xb;
  10134 }
  10135 
  10136 static void
  10137 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10138 {
  10139   slotbuf[0] = 0x8c;
  10140 }
  10141 
  10142 static void
  10143 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10144 {
  10145   slotbuf[0] = 0xcc;
  10146 }
  10147 
  10148 static void
  10149 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10150 {
  10151   slotbuf[0] = 0xf06d;
  10152 }
  10153 
  10154 static void
  10155 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  10156 {
  10157   slotbuf[0] = 0x8;
  10158 }
  10159 
  10160 static void
  10161 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10162 {
  10163   slotbuf[0] = 0xd;
  10164 }
  10165 
  10166 static void
  10167 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10168 {
  10169   slotbuf[0] = 0xc;
  10170 }
  10171 
  10172 static void
  10173 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10174 {
  10175   slotbuf[0] = 0xf03d;
  10176 }
  10177 
  10178 static void
  10179 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  10180 {
  10181   slotbuf[0] = 0xf00d;
  10182 }
  10183 
  10184 static void
  10185 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
  10186 {
  10187   slotbuf[0] = 0x9;
  10188 }
  10189 
  10190 static void
  10191 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10192 {
  10193   slotbuf[0] = 0xe30e70;
  10194 }
  10195 
  10196 static void
  10197 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10198 {
  10199   slotbuf[0] = 0xf3e700;
  10200 }
  10201 
  10202 static void
  10203 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10204 {
  10205   slotbuf[0] = 0xc002;
  10206 }
  10207 
  10208 static void
  10209 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10210 {
  10211   slotbuf[0] = 0xd002;
  10212 }
  10213 
  10214 static void
  10215 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10216 {
  10217   slotbuf[0] = 0x800000;
  10218 }
  10219 
  10220 static void
  10221 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10222 {
  10223   slotbuf[0] = 0x900000;
  10224 }
  10225 
  10226 static void
  10227 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10228 {
  10229   slotbuf[0] = 0xa00000;
  10230 }
  10231 
  10232 static void
  10233 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10234 {
  10235   slotbuf[0] = 0xb00000;
  10236 }
  10237 
  10238 static void
  10239 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10240 {
  10241   slotbuf[0] = 0xc00000;
  10242 }
  10243 
  10244 static void
  10245 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10246 {
  10247   slotbuf[0] = 0xd00000;
  10248 }
  10249 
  10250 static void
  10251 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10252 {
  10253   slotbuf[0] = 0xe00000;
  10254 }
  10255 
  10256 static void
  10257 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10258 {
  10259   slotbuf[0] = 0xf00000;
  10260 }
  10261 
  10262 static void
  10263 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10264 {
  10265   slotbuf[0] = 0x100000;
  10266 }
  10267 
  10268 static void
  10269 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10270 {
  10271   slotbuf[0] = 0x200000;
  10272 }
  10273 
  10274 static void
  10275 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10276 {
  10277   slotbuf[0] = 0x300000;
  10278 }
  10279 
  10280 static void
  10281 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10282 {
  10283   slotbuf[0] = 0x26;
  10284 }
  10285 
  10286 static void
  10287 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10288 {
  10289   slotbuf[0] = 0xe6;
  10290 }
  10291 
  10292 static void
  10293 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10294 {
  10295   slotbuf[0] = 0xa6;
  10296 }
  10297 
  10298 static void
  10299 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10300 {
  10301   slotbuf[0] = 0x66;
  10302 }
  10303 
  10304 static void
  10305 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10306 {
  10307   slotbuf[0] = 0x6007;
  10308 }
  10309 
  10310 static void
  10311 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10312 {
  10313   slotbuf[0] = 0xe007;
  10314 }
  10315 
  10316 static void
  10317 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10318 {
  10319   slotbuf[0] = 0xf6;
  10320 }
  10321 
  10322 static void
  10323 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10324 {
  10325   slotbuf[0] = 0xb6;
  10326 }
  10327 
  10328 static void
  10329 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10330 {
  10331   slotbuf[0] = 0x4007;
  10332 }
  10333 
  10334 static void
  10335 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10336 {
  10337   slotbuf[0] = 0x8007;
  10338 }
  10339 
  10340 static void
  10341 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10342 {
  10343   slotbuf[0] = 0x5007;
  10344 }
  10345 
  10346 static void
  10347 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10348 {
  10349   slotbuf[0] = 0xd007;
  10350 }
  10351 
  10352 static void
  10353 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10354 {
  10355   slotbuf[0] = 0x1007;
  10356 }
  10357 
  10358 static void
  10359 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10360 {
  10361   slotbuf[0] = 0xa007;
  10362 }
  10363 
  10364 static void
  10365 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10366 {
  10367   slotbuf[0] = 0xb007;
  10368 }
  10369 
  10370 static void
  10371 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10372 {
  10373   slotbuf[0] = 0x2007;
  10374 }
  10375 
  10376 static void
  10377 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10378 {
  10379   slotbuf[0] = 0x3007;
  10380 }
  10381 
  10382 static void
  10383 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10384 {
  10385   slotbuf[0] = 0xc007;
  10386 }
  10387 
  10388 static void
  10389 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10390 {
  10391   slotbuf[0] = 0x9007;
  10392 }
  10393 
  10394 static void
  10395 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10396 {
  10397   slotbuf[0] = 0x7;
  10398 }
  10399 
  10400 static void
  10401 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10402 {
  10403   slotbuf[0] = 0x16;
  10404 }
  10405 
  10406 static void
  10407 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10408 {
  10409   slotbuf[0] = 0xd6;
  10410 }
  10411 
  10412 static void
  10413 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10414 {
  10415   slotbuf[0] = 0x96;
  10416 }
  10417 
  10418 static void
  10419 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10420 {
  10421   slotbuf[0] = 0x56;
  10422 }
  10423 
  10424 static void
  10425 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10426 {
  10427   slotbuf[0] = 0x5;
  10428 }
  10429 
  10430 static void
  10431 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10432 {
  10433   slotbuf[0] = 0xc0;
  10434 }
  10435 
  10436 static void
  10437 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10438 {
  10439   slotbuf[0] = 0x40000;
  10440 }
  10441 
  10442 static void
  10443 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10444 {
  10445   slotbuf[0] = 0;
  10446 }
  10447 
  10448 static void
  10449 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10450 {
  10451   slotbuf[0] = 0x6;
  10452 }
  10453 
  10454 static void
  10455 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10456 {
  10457   slotbuf[0] = 0xa0;
  10458 }
  10459 
  10460 static void
  10461 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10462 {
  10463   slotbuf[0] = 0x1002;
  10464 }
  10465 
  10466 static void
  10467 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10468 {
  10469   slotbuf[0] = 0x9002;
  10470 }
  10471 
  10472 static void
  10473 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10474 {
  10475   slotbuf[0] = 0x2002;
  10476 }
  10477 
  10478 static void
  10479 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10480 {
  10481   slotbuf[0] = 0x1;
  10482 }
  10483 
  10484 static void
  10485 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10486 {
  10487   slotbuf[0] = 0x2;
  10488 }
  10489 
  10490 static void
  10491 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10492 {
  10493   slotbuf[0] = 0x8076;
  10494 }
  10495 
  10496 static void
  10497 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10498 {
  10499   slotbuf[0] = 0xa076;
  10500 }
  10501 
  10502 static void
  10503 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10504 {
  10505   slotbuf[0] = 0x9076;
  10506 }
  10507 
  10508 static void
  10509 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10510 {
  10511   slotbuf[0] = 0xa002;
  10512 }
  10513 
  10514 static void
  10515 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10516 {
  10517   slotbuf[0] = 0x830000;
  10518 }
  10519 
  10520 static void
  10521 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10522 {
  10523   slotbuf[0] = 0xb30000;
  10524 }
  10525 
  10526 static void
  10527 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10528 {
  10529   slotbuf[0] = 0xa30000;
  10530 }
  10531 
  10532 static void
  10533 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10534 {
  10535   slotbuf[0] = 0x930000;
  10536 }
  10537 
  10538 static void
  10539 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10540 {
  10541   slotbuf[0] = 0x600100;
  10542 }
  10543 
  10544 static void
  10545 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10546 {
  10547   slotbuf[0] = 0x600000;
  10548 }
  10549 
  10550 static void
  10551 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10552 {
  10553   slotbuf[0] = 0x20f0;
  10554 }
  10555 
  10556 static void
  10557 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10558 {
  10559   slotbuf[0] = 0x80;
  10560 }
  10561 
  10562 static void
  10563 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10564 {
  10565   slotbuf[0] = 0x5100;
  10566 }
  10567 
  10568 static void
  10569 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10570 {
  10571   slotbuf[0] = 0x5002;
  10572 }
  10573 
  10574 static void
  10575 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10576 {
  10577   slotbuf[0] = 0x6002;
  10578 }
  10579 
  10580 static void
  10581 Opcode_s32nb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10582 {
  10583   slotbuf[0] = 0x590000;
  10584 }
  10585 
  10586 static void
  10587 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10588 {
  10589   slotbuf[0] = 0x4002;
  10590 }
  10591 
  10592 static void
  10593 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10594 {
  10595   slotbuf[0] = 0x403000;
  10596 }
  10597 
  10598 static void
  10599 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10600 {
  10601   slotbuf[0] = 0x402000;
  10602 }
  10603 
  10604 static void
  10605 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10606 {
  10607   slotbuf[0] = 0x401000;
  10608 }
  10609 
  10610 static void
  10611 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10612 {
  10613   slotbuf[0] = 0x400000;
  10614 }
  10615 
  10616 static void
  10617 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10618 {
  10619   slotbuf[0] = 0x404000;
  10620 }
  10621 
  10622 static void
  10623 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10624 {
  10625   slotbuf[0] = 0xa10000;
  10626 }
  10627 
  10628 static void
  10629 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10630 {
  10631   slotbuf[0] = 0x810000;
  10632 }
  10633 
  10634 static void
  10635 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10636 {
  10637   slotbuf[0] = 0xb10000;
  10638 }
  10639 
  10640 static void
  10641 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10642 {
  10643   slotbuf[0] = 0x910000;
  10644 }
  10645 
  10646 static void
  10647 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10648 {
  10649   slotbuf[0] = 0x10000;
  10650 }
  10651 
  10652 static void
  10653 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10654 {
  10655   slotbuf[0] = 0x210000;
  10656 }
  10657 
  10658 static void
  10659 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10660 {
  10661   slotbuf[0] = 0x410000;
  10662 }
  10663 
  10664 static void
  10665 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10666 {
  10667   slotbuf[0] = 0x20c0;
  10668 }
  10669 
  10670 static void
  10671 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10672 {
  10673   slotbuf[0] = 0x20d0;
  10674 }
  10675 
  10676 static void
  10677 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10678 {
  10679   slotbuf[0] = 0x2000;
  10680 }
  10681 
  10682 static void
  10683 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10684 {
  10685   slotbuf[0] = 0x2030;
  10686 }
  10687 
  10688 static void
  10689 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10690 {
  10691   slotbuf[0] = 0x2020;
  10692 }
  10693 
  10694 static void
  10695 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10696 {
  10697   slotbuf[0] = 0x2010;
  10698 }
  10699 
  10700 static void
  10701 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10702 {
  10703   slotbuf[0] = 0x6000;
  10704 }
  10705 
  10706 static void
  10707 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10708 {
  10709   slotbuf[0] = 0x30100;
  10710 }
  10711 
  10712 static void
  10713 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10714 {
  10715   slotbuf[0] = 0x130100;
  10716 }
  10717 
  10718 static void
  10719 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10720 {
  10721   slotbuf[0] = 0x610100;
  10722 }
  10723 
  10724 static void
  10725 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10726 {
  10727   slotbuf[0] = 0x30200;
  10728 }
  10729 
  10730 static void
  10731 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10732 {
  10733   slotbuf[0] = 0x130200;
  10734 }
  10735 
  10736 static void
  10737 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10738 {
  10739   slotbuf[0] = 0x610200;
  10740 }
  10741 
  10742 static void
  10743 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10744 {
  10745   slotbuf[0] = 0x30000;
  10746 }
  10747 
  10748 static void
  10749 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10750 {
  10751   slotbuf[0] = 0x130000;
  10752 }
  10753 
  10754 static void
  10755 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10756 {
  10757   slotbuf[0] = 0x610000;
  10758 }
  10759 
  10760 static void
  10761 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10762 {
  10763   slotbuf[0] = 0x30300;
  10764 }
  10765 
  10766 static void
  10767 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10768 {
  10769   slotbuf[0] = 0x130300;
  10770 }
  10771 
  10772 static void
  10773 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10774 {
  10775   slotbuf[0] = 0x610300;
  10776 }
  10777 
  10778 static void
  10779 Opcode_rsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10780 {
  10781   slotbuf[0] = 0x36100;
  10782 }
  10783 
  10784 static void
  10785 Opcode_wsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10786 {
  10787   slotbuf[0] = 0x136100;
  10788 }
  10789 
  10790 static void
  10791 Opcode_xsr_memctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10792 {
  10793   slotbuf[0] = 0x616100;
  10794 }
  10795 
  10796 static void
  10797 Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10798 {
  10799   slotbuf[0] = 0x3b000;
  10800 }
  10801 
  10802 static void
  10803 Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10804 {
  10805   slotbuf[0] = 0x13b000;
  10806 }
  10807 
  10808 static void
  10809 Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10810 {
  10811   slotbuf[0] = 0x3d000;
  10812 }
  10813 
  10814 static void
  10815 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10816 {
  10817   slotbuf[0] = 0x3e600;
  10818 }
  10819 
  10820 static void
  10821 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10822 {
  10823   slotbuf[0] = 0x13e600;
  10824 }
  10825 
  10826 static void
  10827 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10828 {
  10829   slotbuf[0] = 0x61e600;
  10830 }
  10831 
  10832 static void
  10833 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10834 {
  10835   slotbuf[0] = 0x3b100;
  10836 }
  10837 
  10838 static void
  10839 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10840 {
  10841   slotbuf[0] = 0x13b100;
  10842 }
  10843 
  10844 static void
  10845 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10846 {
  10847   slotbuf[0] = 0x61b100;
  10848 }
  10849 
  10850 static void
  10851 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10852 {
  10853   slotbuf[0] = 0x3d100;
  10854 }
  10855 
  10856 static void
  10857 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10858 {
  10859   slotbuf[0] = 0x13d100;
  10860 }
  10861 
  10862 static void
  10863 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10864 {
  10865   slotbuf[0] = 0x61d100;
  10866 }
  10867 
  10868 static void
  10869 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10870 {
  10871   slotbuf[0] = 0x3b200;
  10872 }
  10873 
  10874 static void
  10875 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10876 {
  10877   slotbuf[0] = 0x13b200;
  10878 }
  10879 
  10880 static void
  10881 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10882 {
  10883   slotbuf[0] = 0x61b200;
  10884 }
  10885 
  10886 static void
  10887 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10888 {
  10889   slotbuf[0] = 0x3d200;
  10890 }
  10891 
  10892 static void
  10893 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10894 {
  10895   slotbuf[0] = 0x13d200;
  10896 }
  10897 
  10898 static void
  10899 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10900 {
  10901   slotbuf[0] = 0x61d200;
  10902 }
  10903 
  10904 static void
  10905 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10906 {
  10907   slotbuf[0] = 0x3b300;
  10908 }
  10909 
  10910 static void
  10911 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10912 {
  10913   slotbuf[0] = 0x13b300;
  10914 }
  10915 
  10916 static void
  10917 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10918 {
  10919   slotbuf[0] = 0x61b300;
  10920 }
  10921 
  10922 static void
  10923 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10924 {
  10925   slotbuf[0] = 0x3d300;
  10926 }
  10927 
  10928 static void
  10929 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10930 {
  10931   slotbuf[0] = 0x13d300;
  10932 }
  10933 
  10934 static void
  10935 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10936 {
  10937   slotbuf[0] = 0x61d300;
  10938 }
  10939 
  10940 static void
  10941 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10942 {
  10943   slotbuf[0] = 0x3b400;
  10944 }
  10945 
  10946 static void
  10947 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10948 {
  10949   slotbuf[0] = 0x13b400;
  10950 }
  10951 
  10952 static void
  10953 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10954 {
  10955   slotbuf[0] = 0x61b400;
  10956 }
  10957 
  10958 static void
  10959 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10960 {
  10961   slotbuf[0] = 0x3d400;
  10962 }
  10963 
  10964 static void
  10965 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10966 {
  10967   slotbuf[0] = 0x13d400;
  10968 }
  10969 
  10970 static void
  10971 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10972 {
  10973   slotbuf[0] = 0x61d400;
  10974 }
  10975 
  10976 static void
  10977 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10978 {
  10979   slotbuf[0] = 0x3b500;
  10980 }
  10981 
  10982 static void
  10983 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10984 {
  10985   slotbuf[0] = 0x13b500;
  10986 }
  10987 
  10988 static void
  10989 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10990 {
  10991   slotbuf[0] = 0x61b500;
  10992 }
  10993 
  10994 static void
  10995 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  10996 {
  10997   slotbuf[0] = 0x3d500;
  10998 }
  10999 
  11000 static void
  11001 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11002 {
  11003   slotbuf[0] = 0x13d500;
  11004 }
  11005 
  11006 static void
  11007 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11008 {
  11009   slotbuf[0] = 0x61d500;
  11010 }
  11011 
  11012 static void
  11013 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11014 {
  11015   slotbuf[0] = 0x3b600;
  11016 }
  11017 
  11018 static void
  11019 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11020 {
  11021   slotbuf[0] = 0x13b600;
  11022 }
  11023 
  11024 static void
  11025 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11026 {
  11027   slotbuf[0] = 0x61b600;
  11028 }
  11029 
  11030 static void
  11031 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11032 {
  11033   slotbuf[0] = 0x3d600;
  11034 }
  11035 
  11036 static void
  11037 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11038 {
  11039   slotbuf[0] = 0x13d600;
  11040 }
  11041 
  11042 static void
  11043 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11044 {
  11045   slotbuf[0] = 0x61d600;
  11046 }
  11047 
  11048 static void
  11049 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11050 {
  11051   slotbuf[0] = 0x3b700;
  11052 }
  11053 
  11054 static void
  11055 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11056 {
  11057   slotbuf[0] = 0x13b700;
  11058 }
  11059 
  11060 static void
  11061 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11062 {
  11063   slotbuf[0] = 0x61b700;
  11064 }
  11065 
  11066 static void
  11067 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11068 {
  11069   slotbuf[0] = 0x3d700;
  11070 }
  11071 
  11072 static void
  11073 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11074 {
  11075   slotbuf[0] = 0x13d700;
  11076 }
  11077 
  11078 static void
  11079 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11080 {
  11081   slotbuf[0] = 0x61d700;
  11082 }
  11083 
  11084 static void
  11085 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11086 {
  11087   slotbuf[0] = 0x3c200;
  11088 }
  11089 
  11090 static void
  11091 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11092 {
  11093   slotbuf[0] = 0x13c200;
  11094 }
  11095 
  11096 static void
  11097 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11098 {
  11099   slotbuf[0] = 0x61c200;
  11100 }
  11101 
  11102 static void
  11103 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11104 {
  11105   slotbuf[0] = 0x3c300;
  11106 }
  11107 
  11108 static void
  11109 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11110 {
  11111   slotbuf[0] = 0x13c300;
  11112 }
  11113 
  11114 static void
  11115 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11116 {
  11117   slotbuf[0] = 0x61c300;
  11118 }
  11119 
  11120 static void
  11121 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11122 {
  11123   slotbuf[0] = 0x3c400;
  11124 }
  11125 
  11126 static void
  11127 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11128 {
  11129   slotbuf[0] = 0x13c400;
  11130 }
  11131 
  11132 static void
  11133 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11134 {
  11135   slotbuf[0] = 0x61c400;
  11136 }
  11137 
  11138 static void
  11139 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11140 {
  11141   slotbuf[0] = 0x3c500;
  11142 }
  11143 
  11144 static void
  11145 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11146 {
  11147   slotbuf[0] = 0x13c500;
  11148 }
  11149 
  11150 static void
  11151 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11152 {
  11153   slotbuf[0] = 0x61c500;
  11154 }
  11155 
  11156 static void
  11157 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11158 {
  11159   slotbuf[0] = 0x3c600;
  11160 }
  11161 
  11162 static void
  11163 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11164 {
  11165   slotbuf[0] = 0x13c600;
  11166 }
  11167 
  11168 static void
  11169 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11170 {
  11171   slotbuf[0] = 0x61c600;
  11172 }
  11173 
  11174 static void
  11175 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11176 {
  11177   slotbuf[0] = 0x3c700;
  11178 }
  11179 
  11180 static void
  11181 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11182 {
  11183   slotbuf[0] = 0x13c700;
  11184 }
  11185 
  11186 static void
  11187 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11188 {
  11189   slotbuf[0] = 0x61c700;
  11190 }
  11191 
  11192 static void
  11193 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11194 {
  11195   slotbuf[0] = 0x3ee00;
  11196 }
  11197 
  11198 static void
  11199 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11200 {
  11201   slotbuf[0] = 0x13ee00;
  11202 }
  11203 
  11204 static void
  11205 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11206 {
  11207   slotbuf[0] = 0x61ee00;
  11208 }
  11209 
  11210 static void
  11211 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11212 {
  11213   slotbuf[0] = 0x3c000;
  11214 }
  11215 
  11216 static void
  11217 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11218 {
  11219   slotbuf[0] = 0x13c000;
  11220 }
  11221 
  11222 static void
  11223 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11224 {
  11225   slotbuf[0] = 0x61c000;
  11226 }
  11227 
  11228 static void
  11229 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11230 {
  11231   slotbuf[0] = 0x3e800;
  11232 }
  11233 
  11234 static void
  11235 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11236 {
  11237   slotbuf[0] = 0x13e800;
  11238 }
  11239 
  11240 static void
  11241 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11242 {
  11243   slotbuf[0] = 0x61e800;
  11244 }
  11245 
  11246 static void
  11247 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11248 {
  11249   slotbuf[0] = 0x3f400;
  11250 }
  11251 
  11252 static void
  11253 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11254 {
  11255   slotbuf[0] = 0x13f400;
  11256 }
  11257 
  11258 static void
  11259 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11260 {
  11261   slotbuf[0] = 0x61f400;
  11262 }
  11263 
  11264 static void
  11265 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11266 {
  11267   slotbuf[0] = 0x3f500;
  11268 }
  11269 
  11270 static void
  11271 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11272 {
  11273   slotbuf[0] = 0x13f500;
  11274 }
  11275 
  11276 static void
  11277 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11278 {
  11279   slotbuf[0] = 0x61f500;
  11280 }
  11281 
  11282 static void
  11283 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11284 {
  11285   slotbuf[0] = 0x3eb00;
  11286 }
  11287 
  11288 static void
  11289 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11290 {
  11291   slotbuf[0] = 0x3e700;
  11292 }
  11293 
  11294 static void
  11295 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11296 {
  11297   slotbuf[0] = 0x13e700;
  11298 }
  11299 
  11300 static void
  11301 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11302 {
  11303   slotbuf[0] = 0x61e700;
  11304 }
  11305 
  11306 static void
  11307 Opcode_salt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11308 {
  11309   slotbuf[0] = 0x720000;
  11310 }
  11311 
  11312 static void
  11313 Opcode_saltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11314 {
  11315   slotbuf[0] = 0x620000;
  11316 }
  11317 
  11318 static void
  11319 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11320 {
  11321   slotbuf[0] = 0xd10000;
  11322 }
  11323 
  11324 static void
  11325 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11326 {
  11327   slotbuf[0] = 0xc10000;
  11328 }
  11329 
  11330 static void
  11331 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11332 {
  11333   slotbuf[0] = 0x820000;
  11334 }
  11335 
  11336 static void
  11337 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11338 {
  11339   slotbuf[0] = 0x770004;
  11340 }
  11341 
  11342 static void
  11343 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11344 {
  11345   slotbuf[0] = 0x750004;
  11346 }
  11347 
  11348 static void
  11349 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11350 {
  11351   slotbuf[0] = 0x760004;
  11352 }
  11353 
  11354 static void
  11355 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11356 {
  11357   slotbuf[0] = 0x740004;
  11358 }
  11359 
  11360 static void
  11361 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11362 {
  11363   slotbuf[0] = 0x730004;
  11364 }
  11365 
  11366 static void
  11367 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11368 {
  11369   slotbuf[0] = 0x710004;
  11370 }
  11371 
  11372 static void
  11373 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11374 {
  11375   slotbuf[0] = 0x720004;
  11376 }
  11377 
  11378 static void
  11379 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11380 {
  11381   slotbuf[0] = 0x700004;
  11382 }
  11383 
  11384 static void
  11385 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11386 {
  11387   slotbuf[0] = 0x370004;
  11388 }
  11389 
  11390 static void
  11391 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11392 {
  11393   slotbuf[0] = 0x350004;
  11394 }
  11395 
  11396 static void
  11397 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11398 {
  11399   slotbuf[0] = 0x360004;
  11400 }
  11401 
  11402 static void
  11403 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11404 {
  11405   slotbuf[0] = 0x340004;
  11406 }
  11407 
  11408 static void
  11409 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11410 {
  11411   slotbuf[0] = 0x670004;
  11412 }
  11413 
  11414 static void
  11415 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11416 {
  11417   slotbuf[0] = 0x650004;
  11418 }
  11419 
  11420 static void
  11421 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11422 {
  11423   slotbuf[0] = 0x660004;
  11424 }
  11425 
  11426 static void
  11427 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11428 {
  11429   slotbuf[0] = 0x640004;
  11430 }
  11431 
  11432 static void
  11433 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11434 {
  11435   slotbuf[0] = 0x270004;
  11436 }
  11437 
  11438 static void
  11439 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11440 {
  11441   slotbuf[0] = 0x250004;
  11442 }
  11443 
  11444 static void
  11445 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11446 {
  11447   slotbuf[0] = 0x260004;
  11448 }
  11449 
  11450 static void
  11451 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11452 {
  11453   slotbuf[0] = 0x240004;
  11454 }
  11455 
  11456 static void
  11457 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11458 {
  11459   slotbuf[0] = 0x7b0004;
  11460 }
  11461 
  11462 static void
  11463 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11464 {
  11465   slotbuf[0] = 0x790004;
  11466 }
  11467 
  11468 static void
  11469 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11470 {
  11471   slotbuf[0] = 0x7a0004;
  11472 }
  11473 
  11474 static void
  11475 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11476 {
  11477   slotbuf[0] = 0x780004;
  11478 }
  11479 
  11480 static void
  11481 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11482 {
  11483   slotbuf[0] = 0x7f0004;
  11484 }
  11485 
  11486 static void
  11487 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11488 {
  11489   slotbuf[0] = 0x7d0004;
  11490 }
  11491 
  11492 static void
  11493 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11494 {
  11495   slotbuf[0] = 0x7e0004;
  11496 }
  11497 
  11498 static void
  11499 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11500 {
  11501   slotbuf[0] = 0x7c0004;
  11502 }
  11503 
  11504 static void
  11505 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11506 {
  11507   slotbuf[0] = 0x3b0004;
  11508 }
  11509 
  11510 static void
  11511 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11512 {
  11513   slotbuf[0] = 0x390004;
  11514 }
  11515 
  11516 static void
  11517 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11518 {
  11519   slotbuf[0] = 0x3a0004;
  11520 }
  11521 
  11522 static void
  11523 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11524 {
  11525   slotbuf[0] = 0x380004;
  11526 }
  11527 
  11528 static void
  11529 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11530 {
  11531   slotbuf[0] = 0x3f0004;
  11532 }
  11533 
  11534 static void
  11535 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11536 {
  11537   slotbuf[0] = 0x3d0004;
  11538 }
  11539 
  11540 static void
  11541 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11542 {
  11543   slotbuf[0] = 0x3e0004;
  11544 }
  11545 
  11546 static void
  11547 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11548 {
  11549   slotbuf[0] = 0x3c0004;
  11550 }
  11551 
  11552 static void
  11553 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11554 {
  11555   slotbuf[0] = 0x6b0004;
  11556 }
  11557 
  11558 static void
  11559 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11560 {
  11561   slotbuf[0] = 0x690004;
  11562 }
  11563 
  11564 static void
  11565 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11566 {
  11567   slotbuf[0] = 0x6a0004;
  11568 }
  11569 
  11570 static void
  11571 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11572 {
  11573   slotbuf[0] = 0x680004;
  11574 }
  11575 
  11576 static void
  11577 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11578 {
  11579   slotbuf[0] = 0x6f0004;
  11580 }
  11581 
  11582 static void
  11583 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11584 {
  11585   slotbuf[0] = 0x6d0004;
  11586 }
  11587 
  11588 static void
  11589 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11590 {
  11591   slotbuf[0] = 0x6e0004;
  11592 }
  11593 
  11594 static void
  11595 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11596 {
  11597   slotbuf[0] = 0x6c0004;
  11598 }
  11599 
  11600 static void
  11601 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11602 {
  11603   slotbuf[0] = 0x2b0004;
  11604 }
  11605 
  11606 static void
  11607 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11608 {
  11609   slotbuf[0] = 0x290004;
  11610 }
  11611 
  11612 static void
  11613 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11614 {
  11615   slotbuf[0] = 0x2a0004;
  11616 }
  11617 
  11618 static void
  11619 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11620 {
  11621   slotbuf[0] = 0x280004;
  11622 }
  11623 
  11624 static void
  11625 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11626 {
  11627   slotbuf[0] = 0x2f0004;
  11628 }
  11629 
  11630 static void
  11631 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11632 {
  11633   slotbuf[0] = 0x2d0004;
  11634 }
  11635 
  11636 static void
  11637 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11638 {
  11639   slotbuf[0] = 0x2e0004;
  11640 }
  11641 
  11642 static void
  11643 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11644 {
  11645   slotbuf[0] = 0x2c0004;
  11646 }
  11647 
  11648 static void
  11649 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11650 {
  11651   slotbuf[0] = 0x5b0004;
  11652 }
  11653 
  11654 static void
  11655 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11656 {
  11657   slotbuf[0] = 0x4b0004;
  11658 }
  11659 
  11660 static void
  11661 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11662 {
  11663   slotbuf[0] = 0x590004;
  11664 }
  11665 
  11666 static void
  11667 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11668 {
  11669   slotbuf[0] = 0x490004;
  11670 }
  11671 
  11672 static void
  11673 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11674 {
  11675   slotbuf[0] = 0x5a0004;
  11676 }
  11677 
  11678 static void
  11679 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11680 {
  11681   slotbuf[0] = 0x4a0004;
  11682 }
  11683 
  11684 static void
  11685 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11686 {
  11687   slotbuf[0] = 0x580004;
  11688 }
  11689 
  11690 static void
  11691 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11692 {
  11693   slotbuf[0] = 0x480004;
  11694 }
  11695 
  11696 static void
  11697 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11698 {
  11699   slotbuf[0] = 0x1b0004;
  11700 }
  11701 
  11702 static void
  11703 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11704 {
  11705   slotbuf[0] = 0xb0004;
  11706 }
  11707 
  11708 static void
  11709 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11710 {
  11711   slotbuf[0] = 0x190004;
  11712 }
  11713 
  11714 static void
  11715 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11716 {
  11717   slotbuf[0] = 0x90004;
  11718 }
  11719 
  11720 static void
  11721 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11722 {
  11723   slotbuf[0] = 0x1a0004;
  11724 }
  11725 
  11726 static void
  11727 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11728 {
  11729   slotbuf[0] = 0xa0004;
  11730 }
  11731 
  11732 static void
  11733 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11734 {
  11735   slotbuf[0] = 0x180004;
  11736 }
  11737 
  11738 static void
  11739 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11740 {
  11741   slotbuf[0] = 0x80004;
  11742 }
  11743 
  11744 static void
  11745 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11746 {
  11747   slotbuf[0] = 0x900004;
  11748 }
  11749 
  11750 static void
  11751 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11752 {
  11753   slotbuf[0] = 0x800004;
  11754 }
  11755 
  11756 static void
  11757 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11758 {
  11759   slotbuf[0] = 0x32000;
  11760 }
  11761 
  11762 static void
  11763 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11764 {
  11765   slotbuf[0] = 0x132000;
  11766 }
  11767 
  11768 static void
  11769 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11770 {
  11771   slotbuf[0] = 0x612000;
  11772 }
  11773 
  11774 static void
  11775 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11776 {
  11777   slotbuf[0] = 0x32100;
  11778 }
  11779 
  11780 static void
  11781 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11782 {
  11783   slotbuf[0] = 0x132100;
  11784 }
  11785 
  11786 static void
  11787 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11788 {
  11789   slotbuf[0] = 0x612100;
  11790 }
  11791 
  11792 static void
  11793 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11794 {
  11795   slotbuf[0] = 0x32200;
  11796 }
  11797 
  11798 static void
  11799 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11800 {
  11801   slotbuf[0] = 0x132200;
  11802 }
  11803 
  11804 static void
  11805 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11806 {
  11807   slotbuf[0] = 0x612200;
  11808 }
  11809 
  11810 static void
  11811 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11812 {
  11813   slotbuf[0] = 0x32300;
  11814 }
  11815 
  11816 static void
  11817 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11818 {
  11819   slotbuf[0] = 0x132300;
  11820 }
  11821 
  11822 static void
  11823 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11824 {
  11825   slotbuf[0] = 0x612300;
  11826 }
  11827 
  11828 static void
  11829 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11830 {
  11831   slotbuf[0] = 0x31000;
  11832 }
  11833 
  11834 static void
  11835 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11836 {
  11837   slotbuf[0] = 0x131000;
  11838 }
  11839 
  11840 static void
  11841 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11842 {
  11843   slotbuf[0] = 0x611000;
  11844 }
  11845 
  11846 static void
  11847 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11848 {
  11849   slotbuf[0] = 0x31100;
  11850 }
  11851 
  11852 static void
  11853 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11854 {
  11855   slotbuf[0] = 0x131100;
  11856 }
  11857 
  11858 static void
  11859 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11860 {
  11861   slotbuf[0] = 0x611100;
  11862 }
  11863 
  11864 static void
  11865 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11866 {
  11867   slotbuf[0] = 0x3010;
  11868 }
  11869 
  11870 static void
  11871 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11872 {
  11873   slotbuf[0] = 0x7000;
  11874 }
  11875 
  11876 static void
  11877 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11878 {
  11879   slotbuf[0] = 0x3e200;
  11880 }
  11881 
  11882 static void
  11883 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11884 {
  11885   slotbuf[0] = 0x13e200;
  11886 }
  11887 
  11888 static void
  11889 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11890 {
  11891   slotbuf[0] = 0x13e300;
  11892 }
  11893 
  11894 static void
  11895 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11896 {
  11897   slotbuf[0] = 0x3e400;
  11898 }
  11899 
  11900 static void
  11901 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11902 {
  11903   slotbuf[0] = 0x13e400;
  11904 }
  11905 
  11906 static void
  11907 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11908 {
  11909   slotbuf[0] = 0x61e400;
  11910 }
  11911 
  11912 static void
  11913 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11914 {
  11915   slotbuf[0] = 0x4000;
  11916 }
  11917 
  11918 static void
  11919 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
  11920 {
  11921   slotbuf[0] = 0xf02d;
  11922 }
  11923 
  11924 static void
  11925 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11926 {
  11927   slotbuf[0] = 0x39000;
  11928 }
  11929 
  11930 static void
  11931 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11932 {
  11933   slotbuf[0] = 0x139000;
  11934 }
  11935 
  11936 static void
  11937 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11938 {
  11939   slotbuf[0] = 0x619000;
  11940 }
  11941 
  11942 static void
  11943 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11944 {
  11945   slotbuf[0] = 0x3a000;
  11946 }
  11947 
  11948 static void
  11949 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11950 {
  11951   slotbuf[0] = 0x13a000;
  11952 }
  11953 
  11954 static void
  11955 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11956 {
  11957   slotbuf[0] = 0x61a000;
  11958 }
  11959 
  11960 static void
  11961 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11962 {
  11963   slotbuf[0] = 0x39100;
  11964 }
  11965 
  11966 static void
  11967 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11968 {
  11969   slotbuf[0] = 0x139100;
  11970 }
  11971 
  11972 static void
  11973 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11974 {
  11975   slotbuf[0] = 0x619100;
  11976 }
  11977 
  11978 static void
  11979 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11980 {
  11981   slotbuf[0] = 0x3a100;
  11982 }
  11983 
  11984 static void
  11985 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11986 {
  11987   slotbuf[0] = 0x13a100;
  11988 }
  11989 
  11990 static void
  11991 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11992 {
  11993   slotbuf[0] = 0x61a100;
  11994 }
  11995 
  11996 static void
  11997 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  11998 {
  11999   slotbuf[0] = 0x38000;
  12000 }
  12001 
  12002 static void
  12003 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12004 {
  12005   slotbuf[0] = 0x138000;
  12006 }
  12007 
  12008 static void
  12009 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12010 {
  12011   slotbuf[0] = 0x618000;
  12012 }
  12013 
  12014 static void
  12015 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12016 {
  12017   slotbuf[0] = 0x38100;
  12018 }
  12019 
  12020 static void
  12021 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12022 {
  12023   slotbuf[0] = 0x138100;
  12024 }
  12025 
  12026 static void
  12027 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12028 {
  12029   slotbuf[0] = 0x618100;
  12030 }
  12031 
  12032 static void
  12033 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12034 {
  12035   slotbuf[0] = 0x36000;
  12036 }
  12037 
  12038 static void
  12039 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12040 {
  12041   slotbuf[0] = 0x136000;
  12042 }
  12043 
  12044 static void
  12045 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12046 {
  12047   slotbuf[0] = 0x616000;
  12048 }
  12049 
  12050 static void
  12051 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12052 {
  12053   slotbuf[0] = 0x3e900;
  12054 }
  12055 
  12056 static void
  12057 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12058 {
  12059   slotbuf[0] = 0x13e900;
  12060 }
  12061 
  12062 static void
  12063 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12064 {
  12065   slotbuf[0] = 0x61e900;
  12066 }
  12067 
  12068 static void
  12069 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12070 {
  12071   slotbuf[0] = 0x3ec00;
  12072 }
  12073 
  12074 static void
  12075 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12076 {
  12077   slotbuf[0] = 0x13ec00;
  12078 }
  12079 
  12080 static void
  12081 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12082 {
  12083   slotbuf[0] = 0x61ec00;
  12084 }
  12085 
  12086 static void
  12087 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12088 {
  12089   slotbuf[0] = 0x3ed00;
  12090 }
  12091 
  12092 static void
  12093 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12094 {
  12095   slotbuf[0] = 0x13ed00;
  12096 }
  12097 
  12098 static void
  12099 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12100 {
  12101   slotbuf[0] = 0x61ed00;
  12102 }
  12103 
  12104 static void
  12105 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12106 {
  12107   slotbuf[0] = 0x36800;
  12108 }
  12109 
  12110 static void
  12111 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12112 {
  12113   slotbuf[0] = 0x136800;
  12114 }
  12115 
  12116 static void
  12117 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12118 {
  12119   slotbuf[0] = 0x616800;
  12120 }
  12121 
  12122 static void
  12123 Opcode_lddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12124 {
  12125   slotbuf[0] = 0x70e0;
  12126 }
  12127 
  12128 static void
  12129 Opcode_sddr32_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12130 {
  12131   slotbuf[0] = 0x70f0;
  12132 }
  12133 
  12134 static void
  12135 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12136 {
  12137   slotbuf[0] = 0xf1e000;
  12138 }
  12139 
  12140 static void
  12141 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12142 {
  12143   slotbuf[0] = 0xf1e010;
  12144 }
  12145 
  12146 static void
  12147 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12148 {
  12149   slotbuf[0] = 0x135900;
  12150 }
  12151 
  12152 static void
  12153 Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12154 {
  12155   slotbuf[0] = 0x20000;
  12156 }
  12157 
  12158 static void
  12159 Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12160 {
  12161   slotbuf[0] = 0x120000;
  12162 }
  12163 
  12164 static void
  12165 Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12166 {
  12167   slotbuf[0] = 0x220000;
  12168 }
  12169 
  12170 static void
  12171 Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12172 {
  12173   slotbuf[0] = 0x320000;
  12174 }
  12175 
  12176 static void
  12177 Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12178 {
  12179   slotbuf[0] = 0x420000;
  12180 }
  12181 
  12182 static void
  12183 Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12184 {
  12185   slotbuf[0] = 0x9000;
  12186 }
  12187 
  12188 static void
  12189 Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12190 {
  12191   slotbuf[0] = 0x8000;
  12192 }
  12193 
  12194 static void
  12195 Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12196 {
  12197   slotbuf[0] = 0xb000;
  12198 }
  12199 
  12200 static void
  12201 Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12202 {
  12203   slotbuf[0] = 0xa000;
  12204 }
  12205 
  12206 static void
  12207 Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12208 {
  12209   slotbuf[0] = 0x76;
  12210 }
  12211 
  12212 static void
  12213 Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12214 {
  12215   slotbuf[0] = 0x1076;
  12216 }
  12217 
  12218 static void
  12219 Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12220 {
  12221   slotbuf[0] = 0xc30000;
  12222 }
  12223 
  12224 static void
  12225 Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12226 {
  12227   slotbuf[0] = 0xd30000;
  12228 }
  12229 
  12230 static void
  12231 Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12232 {
  12233   slotbuf[0] = 0x30400;
  12234 }
  12235 
  12236 static void
  12237 Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12238 {
  12239   slotbuf[0] = 0x130400;
  12240 }
  12241 
  12242 static void
  12243 Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12244 {
  12245   slotbuf[0] = 0x610400;
  12246 }
  12247 
  12248 static void
  12249 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12250 {
  12251   slotbuf[0] = 0x3ea00;
  12252 }
  12253 
  12254 static void
  12255 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12256 {
  12257   slotbuf[0] = 0x13ea00;
  12258 }
  12259 
  12260 static void
  12261 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12262 {
  12263   slotbuf[0] = 0x61ea00;
  12264 }
  12265 
  12266 static void
  12267 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12268 {
  12269   slotbuf[0] = 0x3f000;
  12270 }
  12271 
  12272 static void
  12273 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12274 {
  12275   slotbuf[0] = 0x13f000;
  12276 }
  12277 
  12278 static void
  12279 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12280 {
  12281   slotbuf[0] = 0x61f000;
  12282 }
  12283 
  12284 static void
  12285 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12286 {
  12287   slotbuf[0] = 0x3f100;
  12288 }
  12289 
  12290 static void
  12291 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12292 {
  12293   slotbuf[0] = 0x13f100;
  12294 }
  12295 
  12296 static void
  12297 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12298 {
  12299   slotbuf[0] = 0x61f100;
  12300 }
  12301 
  12302 static void
  12303 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12304 {
  12305   slotbuf[0] = 0x3f200;
  12306 }
  12307 
  12308 static void
  12309 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12310 {
  12311   slotbuf[0] = 0x13f200;
  12312 }
  12313 
  12314 static void
  12315 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12316 {
  12317   slotbuf[0] = 0x61f200;
  12318 }
  12319 
  12320 static void
  12321 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12322 {
  12323   slotbuf[0] = 0x70e2;
  12324 }
  12325 
  12326 static void
  12327 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12328 {
  12329   slotbuf[0] = 0x70c2;
  12330 }
  12331 
  12332 static void
  12333 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12334 {
  12335   slotbuf[0] = 0x270d2;
  12336 }
  12337 
  12338 static void
  12339 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12340 {
  12341   slotbuf[0] = 0x370d2;
  12342 }
  12343 
  12344 static void
  12345 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12346 {
  12347   slotbuf[0] = 0x70d2;
  12348 }
  12349 
  12350 static void
  12351 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12352 {
  12353   slotbuf[0] = 0x70f2;
  12354 }
  12355 
  12356 static void
  12357 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12358 {
  12359   slotbuf[0] = 0xf10000;
  12360 }
  12361 
  12362 static void
  12363 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12364 {
  12365   slotbuf[0] = 0xf12000;
  12366 }
  12367 
  12368 static void
  12369 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12370 {
  12371   slotbuf[0] = 0xf11000;
  12372 }
  12373 
  12374 static void
  12375 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12376 {
  12377   slotbuf[0] = 0xf13000;
  12378 }
  12379 
  12380 static void
  12381 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12382 {
  12383   slotbuf[0] = 0x7042;
  12384 }
  12385 
  12386 static void
  12387 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12388 {
  12389   slotbuf[0] = 0x7052;
  12390 }
  12391 
  12392 static void
  12393 Opcode_diwbui_p_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12394 {
  12395   slotbuf[0] = 0xf7082;
  12396 }
  12397 
  12398 static void
  12399 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12400 {
  12401   slotbuf[0] = 0x47082;
  12402 }
  12403 
  12404 static void
  12405 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12406 {
  12407   slotbuf[0] = 0x57082;
  12408 }
  12409 
  12410 static void
  12411 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12412 {
  12413   slotbuf[0] = 0x7062;
  12414 }
  12415 
  12416 static void
  12417 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12418 {
  12419   slotbuf[0] = 0x7072;
  12420 }
  12421 
  12422 static void
  12423 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12424 {
  12425   slotbuf[0] = 0x7002;
  12426 }
  12427 
  12428 static void
  12429 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12430 {
  12431   slotbuf[0] = 0x7022;
  12432 }
  12433 
  12434 static void
  12435 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12436 {
  12437   slotbuf[0] = 0x7012;
  12438 }
  12439 
  12440 static void
  12441 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12442 {
  12443   slotbuf[0] = 0x7032;
  12444 }
  12445 
  12446 static void
  12447 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12448 {
  12449   slotbuf[0] = 0x27082;
  12450 }
  12451 
  12452 static void
  12453 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12454 {
  12455   slotbuf[0] = 0x37082;
  12456 }
  12457 
  12458 static void
  12459 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12460 {
  12461   slotbuf[0] = 0x7082;
  12462 }
  12463 
  12464 static void
  12465 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12466 {
  12467   slotbuf[0] = 0xf19000;
  12468 }
  12469 
  12470 static void
  12471 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12472 {
  12473   slotbuf[0] = 0xf18000;
  12474 }
  12475 
  12476 static void
  12477 Opcode_sdcw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12478 {
  12479   slotbuf[0] = 0xf1b000;
  12480 }
  12481 
  12482 static void
  12483 Opcode_ldcw_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12484 {
  12485   slotbuf[0] = 0xf1a000;
  12486 }
  12487 
  12488 static void
  12489 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12490 {
  12491   slotbuf[0] = 0x135300;
  12492 }
  12493 
  12494 static void
  12495 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12496 {
  12497   slotbuf[0] = 0x35300;
  12498 }
  12499 
  12500 static void
  12501 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12502 {
  12503   slotbuf[0] = 0x615300;
  12504 }
  12505 
  12506 static void
  12507 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12508 {
  12509   slotbuf[0] = 0x35a00;
  12510 }
  12511 
  12512 static void
  12513 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12514 {
  12515   slotbuf[0] = 0x135a00;
  12516 }
  12517 
  12518 static void
  12519 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12520 {
  12521   slotbuf[0] = 0x615a00;
  12522 }
  12523 
  12524 static void
  12525 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12526 {
  12527   slotbuf[0] = 0x35b00;
  12528 }
  12529 
  12530 static void
  12531 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12532 {
  12533   slotbuf[0] = 0x135b00;
  12534 }
  12535 
  12536 static void
  12537 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12538 {
  12539   slotbuf[0] = 0x615b00;
  12540 }
  12541 
  12542 static void
  12543 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12544 {
  12545   slotbuf[0] = 0x35c00;
  12546 }
  12547 
  12548 static void
  12549 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12550 {
  12551   slotbuf[0] = 0x135c00;
  12552 }
  12553 
  12554 static void
  12555 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12556 {
  12557   slotbuf[0] = 0x615c00;
  12558 }
  12559 
  12560 static void
  12561 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12562 {
  12563   slotbuf[0] = 0x50c000;
  12564 }
  12565 
  12566 static void
  12567 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12568 {
  12569   slotbuf[0] = 0x50d000;
  12570 }
  12571 
  12572 static void
  12573 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12574 {
  12575   slotbuf[0] = 0x50b000;
  12576 }
  12577 
  12578 static void
  12579 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12580 {
  12581   slotbuf[0] = 0x50f000;
  12582 }
  12583 
  12584 static void
  12585 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12586 {
  12587   slotbuf[0] = 0x50e000;
  12588 }
  12589 
  12590 static void
  12591 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12592 {
  12593   slotbuf[0] = 0x504000;
  12594 }
  12595 
  12596 static void
  12597 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12598 {
  12599   slotbuf[0] = 0x505000;
  12600 }
  12601 
  12602 static void
  12603 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12604 {
  12605   slotbuf[0] = 0x503000;
  12606 }
  12607 
  12608 static void
  12609 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12610 {
  12611   slotbuf[0] = 0x507000;
  12612 }
  12613 
  12614 static void
  12615 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12616 {
  12617   slotbuf[0] = 0x506000;
  12618 }
  12619 
  12620 static void
  12621 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12622 {
  12623   slotbuf[0] = 0xf1f000;
  12624 }
  12625 
  12626 static void
  12627 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12628 {
  12629   slotbuf[0] = 0x501000;
  12630 }
  12631 
  12632 static void
  12633 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12634 {
  12635   slotbuf[0] = 0x509000;
  12636 }
  12637 
  12638 static void
  12639 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12640 {
  12641   slotbuf[0] = 0x3e000;
  12642 }
  12643 
  12644 static void
  12645 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12646 {
  12647   slotbuf[0] = 0x13e000;
  12648 }
  12649 
  12650 static void
  12651 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12652 {
  12653   slotbuf[0] = 0x61e000;
  12654 }
  12655 
  12656 static void
  12657 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12658 {
  12659   slotbuf[0] = 0x330000;
  12660 }
  12661 
  12662 static void
  12663 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12664 {
  12665   slotbuf[0] = 0x530000;
  12666 }
  12667 
  12668 static void
  12669 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12670 {
  12671   slotbuf[0] = 0x730000;
  12672 }
  12673 
  12674 static void
  12675 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12676 {
  12677   slotbuf[0] = 0x430000;
  12678 }
  12679 
  12680 static void
  12681 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12682 {
  12683   slotbuf[0] = 0x630000;
  12684 }
  12685 
  12686 static void
  12687 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12688 {
  12689   slotbuf[0] = 0x40e000;
  12690 }
  12691 
  12692 static void
  12693 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12694 {
  12695   slotbuf[0] = 0x40f000;
  12696 }
  12697 
  12698 static void
  12699 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12700 {
  12701   slotbuf[0] = 0x230000;
  12702 }
  12703 
  12704 static void
  12705 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12706 {
  12707   slotbuf[0] = 0xb002;
  12708 }
  12709 
  12710 static void
  12711 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12712 {
  12713   slotbuf[0] = 0xf002;
  12714 }
  12715 
  12716 static void
  12717 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12718 {
  12719   slotbuf[0] = 0xe002;
  12720 }
  12721 
  12722 static void
  12723 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12724 {
  12725   slotbuf[0] = 0x30c00;
  12726 }
  12727 
  12728 static void
  12729 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12730 {
  12731   slotbuf[0] = 0x130c00;
  12732 }
  12733 
  12734 static void
  12735 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12736 {
  12737   slotbuf[0] = 0x610c00;
  12738 }
  12739 
  12740 static void
  12741 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12742 {
  12743   slotbuf[0] = 0x36300;
  12744 }
  12745 
  12746 static void
  12747 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12748 {
  12749   slotbuf[0] = 0x136300;
  12750 }
  12751 
  12752 static void
  12753 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12754 {
  12755   slotbuf[0] = 0x616300;
  12756 }
  12757 
  12758 static void
  12759 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12760 {
  12761   slotbuf[0] = 0xd20000;
  12762 }
  12763 
  12764 static void
  12765 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12766 {
  12767   slotbuf[0] = 0xc20000;
  12768 }
  12769 
  12770 static void
  12771 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12772 {
  12773   slotbuf[0] = 0xf20000;
  12774 }
  12775 
  12776 static void
  12777 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12778 {
  12779   slotbuf[0] = 0xe20000;
  12780 }
  12781 
  12782 static void
  12783 Opcode_rsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12784 {
  12785   slotbuf[0] = 0x35f00;
  12786 }
  12787 
  12788 static void
  12789 Opcode_wsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12790 {
  12791   slotbuf[0] = 0x135f00;
  12792 }
  12793 
  12794 static void
  12795 Opcode_xsr_eraccess_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12796 {
  12797   slotbuf[0] = 0x615f00;
  12798 }
  12799 
  12800 static void
  12801 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12802 {
  12803   slotbuf[0] = 0x406000;
  12804 }
  12805 
  12806 static void
  12807 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12808 {
  12809   slotbuf[0] = 0x407000;
  12810 }
  12811 
  12812 static void
  12813 Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12814 {
  12815   slotbuf[0] = 0xe30e80;
  12816 }
  12817 
  12818 static void
  12819 Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12820 {
  12821   slotbuf[0] = 0xf3e800;
  12822 }
  12823 
  12824 static void
  12825 Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12826 {
  12827   slotbuf[0] = 0xe30e90;
  12828 }
  12829 
  12830 static void
  12831 Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12832 {
  12833   slotbuf[0] = 0xf3e900;
  12834 }
  12835 
  12836 static void
  12837 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12838 {
  12839   slotbuf[0] = 0xe0000;
  12840 }
  12841 
  12842 static void
  12843 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12844 {
  12845   slotbuf[0] = 0xe1000;
  12846 }
  12847 
  12848 static void
  12849 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12850 {
  12851   slotbuf[0] = 0xe1200;
  12852 }
  12853 
  12854 static void
  12855 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12856 {
  12857   slotbuf[0] = 0xe2000;
  12858 }
  12859 
  12860 static void
  12861 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12862 {
  12863   slotbuf[0] = 0xe30e60;
  12864 }
  12865 
  12866 static void
  12867 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12868 {
  12869   slotbuf[0] = 0xf3e600;
  12870 }
  12871 
  12872 static void
  12873 Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12874 {
  12875   slotbuf[0] = 0x3;
  12876 }
  12877 
  12878 static void
  12879 Opcode_lsip_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12880 {
  12881   slotbuf[0] = 0x8003;
  12882 }
  12883 
  12884 static void
  12885 Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12886 {
  12887   slotbuf[0] = 0x80000;
  12888 }
  12889 
  12890 static void
  12891 Opcode_lsxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12892 {
  12893   slotbuf[0] = 0x180000;
  12894 }
  12895 
  12896 static void
  12897 Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12898 {
  12899   slotbuf[0] = 0x4003;
  12900 }
  12901 
  12902 static void
  12903 Opcode_ssip_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12904 {
  12905   slotbuf[0] = 0xc003;
  12906 }
  12907 
  12908 static void
  12909 Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12910 {
  12911   slotbuf[0] = 0x480000;
  12912 }
  12913 
  12914 static void
  12915 Opcode_ssxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12916 {
  12917   slotbuf[0] = 0x580000;
  12918 }
  12919 
  12920 static void
  12921 Opcode_ldi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12922 {
  12923   slotbuf[0] = 0x1003;
  12924 }
  12925 
  12926 static void
  12927 Opcode_ldip_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12928 {
  12929   slotbuf[0] = 0x9003;
  12930 }
  12931 
  12932 static void
  12933 Opcode_ldx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12934 {
  12935   slotbuf[0] = 0x280000;
  12936 }
  12937 
  12938 static void
  12939 Opcode_ldxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12940 {
  12941   slotbuf[0] = 0x380000;
  12942 }
  12943 
  12944 static void
  12945 Opcode_sdi_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12946 {
  12947   slotbuf[0] = 0x5003;
  12948 }
  12949 
  12950 static void
  12951 Opcode_sdip_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12952 {
  12953   slotbuf[0] = 0xd003;
  12954 }
  12955 
  12956 static void
  12957 Opcode_sdx_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12958 {
  12959   slotbuf[0] = 0x680000;
  12960 }
  12961 
  12962 static void
  12963 Opcode_sdxp_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12964 {
  12965   slotbuf[0] = 0x780000;
  12966 }
  12967 
  12968 static void
  12969 Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12970 {
  12971   slotbuf[0] = 0xfa0010;
  12972 }
  12973 
  12974 static void
  12975 Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12976 {
  12977   slotbuf[0] = 0xfa0060;
  12978 }
  12979 
  12980 static void
  12981 Opcode_abs_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12982 {
  12983   slotbuf[0] = 0xff0010;
  12984 }
  12985 
  12986 static void
  12987 Opcode_neg_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12988 {
  12989   slotbuf[0] = 0xff0060;
  12990 }
  12991 
  12992 static void
  12993 Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  12994 {
  12995   slotbuf[0] = 0xfa0000;
  12996 }
  12997 
  12998 static void
  12999 Opcode_mov_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13000 {
  13001   slotbuf[0] = 0xff0000;
  13002 }
  13003 
  13004 static void
  13005 Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13006 {
  13007   slotbuf[0] = 0x8b0000;
  13008 }
  13009 
  13010 static void
  13011 Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13012 {
  13013   slotbuf[0] = 0x9b0000;
  13014 }
  13015 
  13016 static void
  13017 Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13018 {
  13019   slotbuf[0] = 0xab0000;
  13020 }
  13021 
  13022 static void
  13023 Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13024 {
  13025   slotbuf[0] = 0xbb0000;
  13026 }
  13027 
  13028 static void
  13029 Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13030 {
  13031   slotbuf[0] = 0xcb0000;
  13032 }
  13033 
  13034 static void
  13035 Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13036 {
  13037   slotbuf[0] = 0xdb0000;
  13038 }
  13039 
  13040 static void
  13041 Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13042 {
  13043   slotbuf[0] = 0xfa0050;
  13044 }
  13045 
  13046 static void
  13047 Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13048 {
  13049   slotbuf[0] = 0xfa0040;
  13050 }
  13051 
  13052 static void
  13053 Opcode_rfrd_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13054 {
  13055   slotbuf[0] = 0xff0040;
  13056 }
  13057 
  13058 static void
  13059 Opcode_wfrd_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13060 {
  13061   slotbuf[0] = 0x8e0000;
  13062 }
  13063 
  13064 static void
  13065 Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13066 {
  13067   slotbuf[0] = 0x8a0000;
  13068 }
  13069 
  13070 static void
  13071 Opcode_round_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13072 {
  13073   slotbuf[0] = 0x8f0000;
  13074 }
  13075 
  13076 static void
  13077 Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13078 {
  13079   slotbuf[0] = 0xba0000;
  13080 }
  13081 
  13082 static void
  13083 Opcode_ceil_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13084 {
  13085   slotbuf[0] = 0xbf0000;
  13086 }
  13087 
  13088 static void
  13089 Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13090 {
  13091   slotbuf[0] = 0xaa0000;
  13092 }
  13093 
  13094 static void
  13095 Opcode_floor_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13096 {
  13097   slotbuf[0] = 0xaf0000;
  13098 }
  13099 
  13100 static void
  13101 Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13102 {
  13103   slotbuf[0] = 0x9a0000;
  13104 }
  13105 
  13106 static void
  13107 Opcode_trunc_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13108 {
  13109   slotbuf[0] = 0x9f0000;
  13110 }
  13111 
  13112 static void
  13113 Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13114 {
  13115   slotbuf[0] = 0xea0000;
  13116 }
  13117 
  13118 static void
  13119 Opcode_utrunc_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13120 {
  13121   slotbuf[0] = 0xef0000;
  13122 }
  13123 
  13124 static void
  13125 Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13126 {
  13127   slotbuf[0] = 0xca0000;
  13128 }
  13129 
  13130 static void
  13131 Opcode_float_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13132 {
  13133   slotbuf[0] = 0xcf0000;
  13134 }
  13135 
  13136 static void
  13137 Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13138 {
  13139   slotbuf[0] = 0xda0000;
  13140 }
  13141 
  13142 static void
  13143 Opcode_ufloat_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13144 {
  13145   slotbuf[0] = 0xdf0000;
  13146 }
  13147 
  13148 static void
  13149 Opcode_cvtd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13150 {
  13151   slotbuf[0] = 0xfa0020;
  13152 }
  13153 
  13154 static void
  13155 Opcode_cvts_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13156 {
  13157   slotbuf[0] = 0xff0020;
  13158 }
  13159 
  13160 static void
  13161 Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13162 {
  13163   slotbuf[0] = 0x1b0000;
  13164 }
  13165 
  13166 static void
  13167 Opcode_un_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13168 {
  13169   slotbuf[0] = 0x1e0000;
  13170 }
  13171 
  13172 static void
  13173 Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13174 {
  13175   slotbuf[0] = 0x5b0000;
  13176 }
  13177 
  13178 static void
  13179 Opcode_ult_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13180 {
  13181   slotbuf[0] = 0x5e0000;
  13182 }
  13183 
  13184 static void
  13185 Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13186 {
  13187   slotbuf[0] = 0x7b0000;
  13188 }
  13189 
  13190 static void
  13191 Opcode_ule_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13192 {
  13193   slotbuf[0] = 0x7e0000;
  13194 }
  13195 
  13196 static void
  13197 Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13198 {
  13199   slotbuf[0] = 0x3b0000;
  13200 }
  13201 
  13202 static void
  13203 Opcode_ueq_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13204 {
  13205   slotbuf[0] = 0x3e0000;
  13206 }
  13207 
  13208 static void
  13209 Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13210 {
  13211   slotbuf[0] = 0x4b0000;
  13212 }
  13213 
  13214 static void
  13215 Opcode_olt_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13216 {
  13217   slotbuf[0] = 0x4e0000;
  13218 }
  13219 
  13220 static void
  13221 Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13222 {
  13223   slotbuf[0] = 0x6b0000;
  13224 }
  13225 
  13226 static void
  13227 Opcode_ole_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13228 {
  13229   slotbuf[0] = 0x6e0000;
  13230 }
  13231 
  13232 static void
  13233 Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13234 {
  13235   slotbuf[0] = 0x2b0000;
  13236 }
  13237 
  13238 static void
  13239 Opcode_oeq_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13240 {
  13241   slotbuf[0] = 0x2e0000;
  13242 }
  13243 
  13244 static void
  13245 Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13246 {
  13247   slotbuf[0] = 0xa0000;
  13248 }
  13249 
  13250 static void
  13251 Opcode_add_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13252 {
  13253   slotbuf[0] = 0xf0000;
  13254 }
  13255 
  13256 static void
  13257 Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13258 {
  13259   slotbuf[0] = 0x1a0000;
  13260 }
  13261 
  13262 static void
  13263 Opcode_sub_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13264 {
  13265   slotbuf[0] = 0x1f0000;
  13266 }
  13267 
  13268 static void
  13269 Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13270 {
  13271   slotbuf[0] = 0x2a0000;
  13272 }
  13273 
  13274 static void
  13275 Opcode_mul_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13276 {
  13277   slotbuf[0] = 0x2f0000;
  13278 }
  13279 
  13280 static void
  13281 Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13282 {
  13283   slotbuf[0] = 0x4a0000;
  13284 }
  13285 
  13286 static void
  13287 Opcode_madd_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13288 {
  13289   slotbuf[0] = 0x4f0000;
  13290 }
  13291 
  13292 static void
  13293 Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13294 {
  13295   slotbuf[0] = 0x5a0000;
  13296 }
  13297 
  13298 static void
  13299 Opcode_msub_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13300 {
  13301   slotbuf[0] = 0x5f0000;
  13302 }
  13303 
  13304 static void
  13305 Opcode_sqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13306 {
  13307   slotbuf[0] = 0xfa0090;
  13308 }
  13309 
  13310 static void
  13311 Opcode_sqrt0_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13312 {
  13313   slotbuf[0] = 0xff0090;
  13314 }
  13315 
  13316 static void
  13317 Opcode_div0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13318 {
  13319   slotbuf[0] = 0xfa0070;
  13320 }
  13321 
  13322 static void
  13323 Opcode_div0_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13324 {
  13325   slotbuf[0] = 0xff0070;
  13326 }
  13327 
  13328 static void
  13329 Opcode_recip0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13330 {
  13331   slotbuf[0] = 0xfa0080;
  13332 }
  13333 
  13334 static void
  13335 Opcode_recip0_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13336 {
  13337   slotbuf[0] = 0xff0080;
  13338 }
  13339 
  13340 static void
  13341 Opcode_rsqrt0_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13342 {
  13343   slotbuf[0] = 0xfa00a0;
  13344 }
  13345 
  13346 static void
  13347 Opcode_rsqrt0_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13348 {
  13349   slotbuf[0] = 0xff00a0;
  13350 }
  13351 
  13352 static void
  13353 Opcode_maddn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13354 {
  13355   slotbuf[0] = 0x6a0000;
  13356 }
  13357 
  13358 static void
  13359 Opcode_maddn_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13360 {
  13361   slotbuf[0] = 0x6f0000;
  13362 }
  13363 
  13364 static void
  13365 Opcode_divn_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13366 {
  13367   slotbuf[0] = 0x7a0000;
  13368 }
  13369 
  13370 static void
  13371 Opcode_divn_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13372 {
  13373   slotbuf[0] = 0x7f0000;
  13374 }
  13375 
  13376 static void
  13377 Opcode_const_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13378 {
  13379   slotbuf[0] = 0xfa0030;
  13380 }
  13381 
  13382 static void
  13383 Opcode_const_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13384 {
  13385   slotbuf[0] = 0xff0030;
  13386 }
  13387 
  13388 static void
  13389 Opcode_nexp01_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13390 {
  13391   slotbuf[0] = 0xfa00b0;
  13392 }
  13393 
  13394 static void
  13395 Opcode_nexp01_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13396 {
  13397   slotbuf[0] = 0xff00b0;
  13398 }
  13399 
  13400 static void
  13401 Opcode_addexp_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13402 {
  13403   slotbuf[0] = 0xfa00e0;
  13404 }
  13405 
  13406 static void
  13407 Opcode_addexp_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13408 {
  13409   slotbuf[0] = 0xff00e0;
  13410 }
  13411 
  13412 static void
  13413 Opcode_addexpm_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13414 {
  13415   slotbuf[0] = 0xfa00f0;
  13416 }
  13417 
  13418 static void
  13419 Opcode_addexpm_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13420 {
  13421   slotbuf[0] = 0xff00f0;
  13422 }
  13423 
  13424 static void
  13425 Opcode_mkdadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13426 {
  13427   slotbuf[0] = 0xfa00d0;
  13428 }
  13429 
  13430 static void
  13431 Opcode_mkdadj_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13432 {
  13433   slotbuf[0] = 0xff00d0;
  13434 }
  13435 
  13436 static void
  13437 Opcode_mksadj_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13438 {
  13439   slotbuf[0] = 0xfa00c0;
  13440 }
  13441 
  13442 static void
  13443 Opcode_mksadj_d_Slot_inst_encode (xtensa_insnbuf slotbuf)
  13444 {
  13445   slotbuf[0] = 0xff00c0;
  13446 }
  13447 
  13448 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
  13449   Opcode_excw_Slot_inst_encode, 0, 0
  13450 };
  13451 
  13452 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
  13453   Opcode_rfe_Slot_inst_encode, 0, 0
  13454 };
  13455 
  13456 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
  13457   Opcode_rfde_Slot_inst_encode, 0, 0
  13458 };
  13459 
  13460 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
  13461   Opcode_syscall_Slot_inst_encode, 0, 0
  13462 };
  13463 
  13464 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
  13465   Opcode_call12_Slot_inst_encode, 0, 0
  13466 };
  13467 
  13468 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
  13469   Opcode_call8_Slot_inst_encode, 0, 0
  13470 };
  13471 
  13472 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
  13473   Opcode_call4_Slot_inst_encode, 0, 0
  13474 };
  13475 
  13476 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
  13477   Opcode_callx12_Slot_inst_encode, 0, 0
  13478 };
  13479 
  13480 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
  13481   Opcode_callx8_Slot_inst_encode, 0, 0
  13482 };
  13483 
  13484 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
  13485   Opcode_callx4_Slot_inst_encode, 0, 0
  13486 };
  13487 
  13488 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
  13489   Opcode_entry_Slot_inst_encode, 0, 0
  13490 };
  13491 
  13492 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
  13493   Opcode_movsp_Slot_inst_encode, 0, 0
  13494 };
  13495 
  13496 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
  13497   Opcode_rotw_Slot_inst_encode, 0, 0
  13498 };
  13499 
  13500 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
  13501   Opcode_retw_Slot_inst_encode, 0, 0
  13502 };
  13503 
  13504 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
  13505   0, 0, Opcode_retw_n_Slot_inst16b_encode
  13506 };
  13507 
  13508 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
  13509   Opcode_rfwo_Slot_inst_encode, 0, 0
  13510 };
  13511 
  13512 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
  13513   Opcode_rfwu_Slot_inst_encode, 0, 0
  13514 };
  13515 
  13516 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
  13517   Opcode_l32e_Slot_inst_encode, 0, 0
  13518 };
  13519 
  13520 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
  13521   Opcode_s32e_Slot_inst_encode, 0, 0
  13522 };
  13523 
  13524 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
  13525   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
  13526 };
  13527 
  13528 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
  13529   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
  13530 };
  13531 
  13532 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
  13533   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
  13534 };
  13535 
  13536 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
  13537   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
  13538 };
  13539 
  13540 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
  13541   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
  13542 };
  13543 
  13544 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
  13545   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
  13546 };
  13547 
  13548 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
  13549   0, Opcode_add_n_Slot_inst16a_encode, 0
  13550 };
  13551 
  13552 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
  13553   0, Opcode_addi_n_Slot_inst16a_encode, 0
  13554 };
  13555 
  13556 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
  13557   0, 0, Opcode_beqz_n_Slot_inst16b_encode
  13558 };
  13559 
  13560 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
  13561   0, 0, Opcode_bnez_n_Slot_inst16b_encode
  13562 };
  13563 
  13564 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
  13565   0, 0, Opcode_ill_n_Slot_inst16b_encode
  13566 };
  13567 
  13568 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
  13569   0, Opcode_l32i_n_Slot_inst16a_encode, 0
  13570 };
  13571 
  13572 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
  13573   0, 0, Opcode_mov_n_Slot_inst16b_encode
  13574 };
  13575 
  13576 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
  13577   0, 0, Opcode_movi_n_Slot_inst16b_encode
  13578 };
  13579 
  13580 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
  13581   0, 0, Opcode_nop_n_Slot_inst16b_encode
  13582 };
  13583 
  13584 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
  13585   0, 0, Opcode_ret_n_Slot_inst16b_encode
  13586 };
  13587 
  13588 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
  13589   0, Opcode_s32i_n_Slot_inst16a_encode, 0
  13590 };
  13591 
  13592 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
  13593   Opcode_rur_threadptr_Slot_inst_encode, 0, 0
  13594 };
  13595 
  13596 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
  13597   Opcode_wur_threadptr_Slot_inst_encode, 0, 0
  13598 };
  13599 
  13600 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
  13601   Opcode_addi_Slot_inst_encode, 0, 0
  13602 };
  13603 
  13604 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
  13605   Opcode_addmi_Slot_inst_encode, 0, 0
  13606 };
  13607 
  13608 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
  13609   Opcode_add_Slot_inst_encode, 0, 0
  13610 };
  13611 
  13612 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
  13613   Opcode_addx2_Slot_inst_encode, 0, 0
  13614 };
  13615 
  13616 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
  13617   Opcode_addx4_Slot_inst_encode, 0, 0
  13618 };
  13619 
  13620 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
  13621   Opcode_addx8_Slot_inst_encode, 0, 0
  13622 };
  13623 
  13624 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
  13625   Opcode_sub_Slot_inst_encode, 0, 0
  13626 };
  13627 
  13628 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
  13629   Opcode_subx2_Slot_inst_encode, 0, 0
  13630 };
  13631 
  13632 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
  13633   Opcode_subx4_Slot_inst_encode, 0, 0
  13634 };
  13635 
  13636 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
  13637   Opcode_subx8_Slot_inst_encode, 0, 0
  13638 };
  13639 
  13640 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
  13641   Opcode_and_Slot_inst_encode, 0, 0
  13642 };
  13643 
  13644 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
  13645   Opcode_or_Slot_inst_encode, 0, 0
  13646 };
  13647 
  13648 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
  13649   Opcode_xor_Slot_inst_encode, 0, 0
  13650 };
  13651 
  13652 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
  13653   Opcode_beqi_Slot_inst_encode, 0, 0
  13654 };
  13655 
  13656 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
  13657   Opcode_bgei_Slot_inst_encode, 0, 0
  13658 };
  13659 
  13660 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
  13661   Opcode_blti_Slot_inst_encode, 0, 0
  13662 };
  13663 
  13664 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
  13665   Opcode_bnei_Slot_inst_encode, 0, 0
  13666 };
  13667 
  13668 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
  13669   Opcode_bbci_Slot_inst_encode, 0, 0
  13670 };
  13671 
  13672 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
  13673   Opcode_bbsi_Slot_inst_encode, 0, 0
  13674 };
  13675 
  13676 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
  13677   Opcode_bgeui_Slot_inst_encode, 0, 0
  13678 };
  13679 
  13680 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
  13681   Opcode_bltui_Slot_inst_encode, 0, 0
  13682 };
  13683 
  13684 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
  13685   Opcode_ball_Slot_inst_encode, 0, 0
  13686 };
  13687 
  13688 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
  13689   Opcode_bany_Slot_inst_encode, 0, 0
  13690 };
  13691 
  13692 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
  13693   Opcode_bbc_Slot_inst_encode, 0, 0
  13694 };
  13695 
  13696 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
  13697   Opcode_bbs_Slot_inst_encode, 0, 0
  13698 };
  13699 
  13700 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
  13701   Opcode_beq_Slot_inst_encode, 0, 0
  13702 };
  13703 
  13704 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
  13705   Opcode_bge_Slot_inst_encode, 0, 0
  13706 };
  13707 
  13708 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
  13709   Opcode_bgeu_Slot_inst_encode, 0, 0
  13710 };
  13711 
  13712 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
  13713   Opcode_blt_Slot_inst_encode, 0, 0
  13714 };
  13715 
  13716 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
  13717   Opcode_bltu_Slot_inst_encode, 0, 0
  13718 };
  13719 
  13720 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
  13721   Opcode_bnall_Slot_inst_encode, 0, 0
  13722 };
  13723 
  13724 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
  13725   Opcode_bne_Slot_inst_encode, 0, 0
  13726 };
  13727 
  13728 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
  13729   Opcode_bnone_Slot_inst_encode, 0, 0
  13730 };
  13731 
  13732 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
  13733   Opcode_beqz_Slot_inst_encode, 0, 0
  13734 };
  13735 
  13736 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
  13737   Opcode_bgez_Slot_inst_encode, 0, 0
  13738 };
  13739 
  13740 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
  13741   Opcode_bltz_Slot_inst_encode, 0, 0
  13742 };
  13743 
  13744 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
  13745   Opcode_bnez_Slot_inst_encode, 0, 0
  13746 };
  13747 
  13748 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
  13749   Opcode_call0_Slot_inst_encode, 0, 0
  13750 };
  13751 
  13752 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
  13753   Opcode_callx0_Slot_inst_encode, 0, 0
  13754 };
  13755 
  13756 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
  13757   Opcode_extui_Slot_inst_encode, 0, 0
  13758 };
  13759 
  13760 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
  13761   Opcode_ill_Slot_inst_encode, 0, 0
  13762 };
  13763 
  13764 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
  13765   Opcode_j_Slot_inst_encode, 0, 0
  13766 };
  13767 
  13768 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
  13769   Opcode_jx_Slot_inst_encode, 0, 0
  13770 };
  13771 
  13772 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
  13773   Opcode_l16ui_Slot_inst_encode, 0, 0
  13774 };
  13775 
  13776 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
  13777   Opcode_l16si_Slot_inst_encode, 0, 0
  13778 };
  13779 
  13780 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
  13781   Opcode_l32i_Slot_inst_encode, 0, 0
  13782 };
  13783 
  13784 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
  13785   Opcode_l32r_Slot_inst_encode, 0, 0
  13786 };
  13787 
  13788 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
  13789   Opcode_l8ui_Slot_inst_encode, 0, 0
  13790 };
  13791 
  13792 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
  13793   Opcode_loop_Slot_inst_encode, 0, 0
  13794 };
  13795 
  13796 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
  13797   Opcode_loopgtz_Slot_inst_encode, 0, 0
  13798 };
  13799 
  13800 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
  13801   Opcode_loopnez_Slot_inst_encode, 0, 0
  13802 };
  13803 
  13804 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
  13805   Opcode_movi_Slot_inst_encode, 0, 0
  13806 };
  13807 
  13808 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
  13809   Opcode_moveqz_Slot_inst_encode, 0, 0
  13810 };
  13811 
  13812 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
  13813   Opcode_movgez_Slot_inst_encode, 0, 0
  13814 };
  13815 
  13816 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
  13817   Opcode_movltz_Slot_inst_encode, 0, 0
  13818 };
  13819 
  13820 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
  13821   Opcode_movnez_Slot_inst_encode, 0, 0
  13822 };
  13823 
  13824 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
  13825   Opcode_abs_Slot_inst_encode, 0, 0
  13826 };
  13827 
  13828 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
  13829   Opcode_neg_Slot_inst_encode, 0, 0
  13830 };
  13831 
  13832 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
  13833   Opcode_nop_Slot_inst_encode, 0, 0
  13834 };
  13835 
  13836 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
  13837   Opcode_ret_Slot_inst_encode, 0, 0
  13838 };
  13839 
  13840 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
  13841   Opcode_simcall_Slot_inst_encode, 0, 0
  13842 };
  13843 
  13844 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
  13845   Opcode_s16i_Slot_inst_encode, 0, 0
  13846 };
  13847 
  13848 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
  13849   Opcode_s32i_Slot_inst_encode, 0, 0
  13850 };
  13851 
  13852 static xtensa_opcode_encode_fn Opcode_s32nb_encode_fns[] = {
  13853   Opcode_s32nb_Slot_inst_encode, 0, 0
  13854 };
  13855 
  13856 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
  13857   Opcode_s8i_Slot_inst_encode, 0, 0
  13858 };
  13859 
  13860 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
  13861   Opcode_ssa8b_Slot_inst_encode, 0, 0
  13862 };
  13863 
  13864 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
  13865   Opcode_ssa8l_Slot_inst_encode, 0, 0
  13866 };
  13867 
  13868 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
  13869   Opcode_ssl_Slot_inst_encode, 0, 0
  13870 };
  13871 
  13872 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
  13873   Opcode_ssr_Slot_inst_encode, 0, 0
  13874 };
  13875 
  13876 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
  13877   Opcode_ssai_Slot_inst_encode, 0, 0
  13878 };
  13879 
  13880 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
  13881   Opcode_sll_Slot_inst_encode, 0, 0
  13882 };
  13883 
  13884 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
  13885   Opcode_src_Slot_inst_encode, 0, 0
  13886 };
  13887 
  13888 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
  13889   Opcode_sra_Slot_inst_encode, 0, 0
  13890 };
  13891 
  13892 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
  13893   Opcode_srl_Slot_inst_encode, 0, 0
  13894 };
  13895 
  13896 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
  13897   Opcode_slli_Slot_inst_encode, 0, 0
  13898 };
  13899 
  13900 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
  13901   Opcode_srai_Slot_inst_encode, 0, 0
  13902 };
  13903 
  13904 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
  13905   Opcode_srli_Slot_inst_encode, 0, 0
  13906 };
  13907 
  13908 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
  13909   Opcode_memw_Slot_inst_encode, 0, 0
  13910 };
  13911 
  13912 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
  13913   Opcode_extw_Slot_inst_encode, 0, 0
  13914 };
  13915 
  13916 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
  13917   Opcode_isync_Slot_inst_encode, 0, 0
  13918 };
  13919 
  13920 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
  13921   Opcode_dsync_Slot_inst_encode, 0, 0
  13922 };
  13923 
  13924 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
  13925   Opcode_esync_Slot_inst_encode, 0, 0
  13926 };
  13927 
  13928 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
  13929   Opcode_rsync_Slot_inst_encode, 0, 0
  13930 };
  13931 
  13932 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
  13933   Opcode_rsil_Slot_inst_encode, 0, 0
  13934 };
  13935 
  13936 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
  13937   Opcode_rsr_lend_Slot_inst_encode, 0, 0
  13938 };
  13939 
  13940 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
  13941   Opcode_wsr_lend_Slot_inst_encode, 0, 0
  13942 };
  13943 
  13944 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
  13945   Opcode_xsr_lend_Slot_inst_encode, 0, 0
  13946 };
  13947 
  13948 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
  13949   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
  13950 };
  13951 
  13952 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
  13953   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
  13954 };
  13955 
  13956 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
  13957   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
  13958 };
  13959 
  13960 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
  13961   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
  13962 };
  13963 
  13964 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
  13965   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
  13966 };
  13967 
  13968 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
  13969   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
  13970 };
  13971 
  13972 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
  13973   Opcode_rsr_sar_Slot_inst_encode, 0, 0
  13974 };
  13975 
  13976 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
  13977   Opcode_wsr_sar_Slot_inst_encode, 0, 0
  13978 };
  13979 
  13980 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
  13981   Opcode_xsr_sar_Slot_inst_encode, 0, 0
  13982 };
  13983 
  13984 static xtensa_opcode_encode_fn Opcode_rsr_memctl_encode_fns[] = {
  13985   Opcode_rsr_memctl_Slot_inst_encode, 0, 0
  13986 };
  13987 
  13988 static xtensa_opcode_encode_fn Opcode_wsr_memctl_encode_fns[] = {
  13989   Opcode_wsr_memctl_Slot_inst_encode, 0, 0
  13990 };
  13991 
  13992 static xtensa_opcode_encode_fn Opcode_xsr_memctl_encode_fns[] = {
  13993   Opcode_xsr_memctl_Slot_inst_encode, 0, 0
  13994 };
  13995 
  13996 static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
  13997   Opcode_rsr_configid0_Slot_inst_encode, 0, 0
  13998 };
  13999 
  14000 static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
  14001   Opcode_wsr_configid0_Slot_inst_encode, 0, 0
  14002 };
  14003 
  14004 static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
  14005   Opcode_rsr_configid1_Slot_inst_encode, 0, 0
  14006 };
  14007 
  14008 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
  14009   Opcode_rsr_ps_Slot_inst_encode, 0, 0
  14010 };
  14011 
  14012 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
  14013   Opcode_wsr_ps_Slot_inst_encode, 0, 0
  14014 };
  14015 
  14016 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
  14017   Opcode_xsr_ps_Slot_inst_encode, 0, 0
  14018 };
  14019 
  14020 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
  14021   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
  14022 };
  14023 
  14024 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
  14025   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
  14026 };
  14027 
  14028 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
  14029   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
  14030 };
  14031 
  14032 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
  14033   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
  14034 };
  14035 
  14036 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
  14037   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
  14038 };
  14039 
  14040 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
  14041   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
  14042 };
  14043 
  14044 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
  14045   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
  14046 };
  14047 
  14048 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
  14049   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
  14050 };
  14051 
  14052 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
  14053   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
  14054 };
  14055 
  14056 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
  14057   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
  14058 };
  14059 
  14060 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
  14061   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
  14062 };
  14063 
  14064 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
  14065   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
  14066 };
  14067 
  14068 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
  14069   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
  14070 };
  14071 
  14072 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
  14073   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
  14074 };
  14075 
  14076 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
  14077   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
  14078 };
  14079 
  14080 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
  14081   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
  14082 };
  14083 
  14084 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
  14085   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
  14086 };
  14087 
  14088 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
  14089   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
  14090 };
  14091 
  14092 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
  14093   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
  14094 };
  14095 
  14096 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
  14097   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
  14098 };
  14099 
  14100 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
  14101   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
  14102 };
  14103 
  14104 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
  14105   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
  14106 };
  14107 
  14108 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
  14109   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
  14110 };
  14111 
  14112 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
  14113   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
  14114 };
  14115 
  14116 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
  14117   Opcode_rsr_epc5_Slot_inst_encode, 0, 0
  14118 };
  14119 
  14120 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
  14121   Opcode_wsr_epc5_Slot_inst_encode, 0, 0
  14122 };
  14123 
  14124 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
  14125   Opcode_xsr_epc5_Slot_inst_encode, 0, 0
  14126 };
  14127 
  14128 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
  14129   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
  14130 };
  14131 
  14132 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
  14133   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
  14134 };
  14135 
  14136 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
  14137   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
  14138 };
  14139 
  14140 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
  14141   Opcode_rsr_epc6_Slot_inst_encode, 0, 0
  14142 };
  14143 
  14144 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
  14145   Opcode_wsr_epc6_Slot_inst_encode, 0, 0
  14146 };
  14147 
  14148 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
  14149   Opcode_xsr_epc6_Slot_inst_encode, 0, 0
  14150 };
  14151 
  14152 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
  14153   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
  14154 };
  14155 
  14156 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
  14157   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
  14158 };
  14159 
  14160 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
  14161   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
  14162 };
  14163 
  14164 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
  14165   Opcode_rsr_epc7_Slot_inst_encode, 0, 0
  14166 };
  14167 
  14168 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
  14169   Opcode_wsr_epc7_Slot_inst_encode, 0, 0
  14170 };
  14171 
  14172 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
  14173   Opcode_xsr_epc7_Slot_inst_encode, 0, 0
  14174 };
  14175 
  14176 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
  14177   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
  14178 };
  14179 
  14180 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
  14181   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
  14182 };
  14183 
  14184 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
  14185   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
  14186 };
  14187 
  14188 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
  14189   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
  14190 };
  14191 
  14192 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
  14193   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
  14194 };
  14195 
  14196 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
  14197   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
  14198 };
  14199 
  14200 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
  14201   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
  14202 };
  14203 
  14204 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
  14205   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
  14206 };
  14207 
  14208 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
  14209   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
  14210 };
  14211 
  14212 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
  14213   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
  14214 };
  14215 
  14216 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
  14217   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
  14218 };
  14219 
  14220 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
  14221   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
  14222 };
  14223 
  14224 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
  14225   Opcode_rsr_eps5_Slot_inst_encode, 0, 0
  14226 };
  14227 
  14228 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
  14229   Opcode_wsr_eps5_Slot_inst_encode, 0, 0
  14230 };
  14231 
  14232 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
  14233   Opcode_xsr_eps5_Slot_inst_encode, 0, 0
  14234 };
  14235 
  14236 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
  14237   Opcode_rsr_eps6_Slot_inst_encode, 0, 0
  14238 };
  14239 
  14240 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
  14241   Opcode_wsr_eps6_Slot_inst_encode, 0, 0
  14242 };
  14243 
  14244 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
  14245   Opcode_xsr_eps6_Slot_inst_encode, 0, 0
  14246 };
  14247 
  14248 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
  14249   Opcode_rsr_eps7_Slot_inst_encode, 0, 0
  14250 };
  14251 
  14252 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
  14253   Opcode_wsr_eps7_Slot_inst_encode, 0, 0
  14254 };
  14255 
  14256 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
  14257   Opcode_xsr_eps7_Slot_inst_encode, 0, 0
  14258 };
  14259 
  14260 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
  14261   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
  14262 };
  14263 
  14264 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
  14265   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
  14266 };
  14267 
  14268 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
  14269   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
  14270 };
  14271 
  14272 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
  14273   Opcode_rsr_depc_Slot_inst_encode, 0, 0
  14274 };
  14275 
  14276 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
  14277   Opcode_wsr_depc_Slot_inst_encode, 0, 0
  14278 };
  14279 
  14280 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
  14281   Opcode_xsr_depc_Slot_inst_encode, 0, 0
  14282 };
  14283 
  14284 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
  14285   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
  14286 };
  14287 
  14288 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
  14289   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
  14290 };
  14291 
  14292 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
  14293   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
  14294 };
  14295 
  14296 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
  14297   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
  14298 };
  14299 
  14300 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
  14301   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
  14302 };
  14303 
  14304 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
  14305   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
  14306 };
  14307 
  14308 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
  14309   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
  14310 };
  14311 
  14312 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
  14313   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
  14314 };
  14315 
  14316 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
  14317   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
  14318 };
  14319 
  14320 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
  14321   Opcode_rsr_prid_Slot_inst_encode, 0, 0
  14322 };
  14323 
  14324 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
  14325   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
  14326 };
  14327 
  14328 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
  14329   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
  14330 };
  14331 
  14332 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
  14333   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
  14334 };
  14335 
  14336 static xtensa_opcode_encode_fn Opcode_salt_encode_fns[] = {
  14337   Opcode_salt_Slot_inst_encode, 0, 0
  14338 };
  14339 
  14340 static xtensa_opcode_encode_fn Opcode_saltu_encode_fns[] = {
  14341   Opcode_saltu_Slot_inst_encode, 0, 0
  14342 };
  14343 
  14344 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
  14345   Opcode_mul16s_Slot_inst_encode, 0, 0
  14346 };
  14347 
  14348 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
  14349   Opcode_mul16u_Slot_inst_encode, 0, 0
  14350 };
  14351 
  14352 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
  14353   Opcode_mull_Slot_inst_encode, 0, 0
  14354 };
  14355 
  14356 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
  14357   Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
  14358 };
  14359 
  14360 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
  14361   Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
  14362 };
  14363 
  14364 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
  14365   Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
  14366 };
  14367 
  14368 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
  14369   Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
  14370 };
  14371 
  14372 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
  14373   Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
  14374 };
  14375 
  14376 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
  14377   Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
  14378 };
  14379 
  14380 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
  14381   Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
  14382 };
  14383 
  14384 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
  14385   Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
  14386 };
  14387 
  14388 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
  14389   Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
  14390 };
  14391 
  14392 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
  14393   Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
  14394 };
  14395 
  14396 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
  14397   Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
  14398 };
  14399 
  14400 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
  14401   Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
  14402 };
  14403 
  14404 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
  14405   Opcode_mul_da_hh_Slot_inst_encode, 0, 0
  14406 };
  14407 
  14408 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
  14409   Opcode_mul_da_hl_Slot_inst_encode, 0, 0
  14410 };
  14411 
  14412 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
  14413   Opcode_mul_da_lh_Slot_inst_encode, 0, 0
  14414 };
  14415 
  14416 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
  14417   Opcode_mul_da_ll_Slot_inst_encode, 0, 0
  14418 };
  14419 
  14420 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
  14421   Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
  14422 };
  14423 
  14424 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
  14425   Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
  14426 };
  14427 
  14428 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
  14429   Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
  14430 };
  14431 
  14432 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
  14433   Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
  14434 };
  14435 
  14436 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
  14437   Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
  14438 };
  14439 
  14440 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
  14441   Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
  14442 };
  14443 
  14444 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
  14445   Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
  14446 };
  14447 
  14448 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
  14449   Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
  14450 };
  14451 
  14452 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
  14453   Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
  14454 };
  14455 
  14456 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
  14457   Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
  14458 };
  14459 
  14460 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
  14461   Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
  14462 };
  14463 
  14464 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
  14465   Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
  14466 };
  14467 
  14468 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
  14469   Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
  14470 };
  14471 
  14472 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
  14473   Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
  14474 };
  14475 
  14476 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
  14477   Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
  14478 };
  14479 
  14480 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
  14481   Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
  14482 };
  14483 
  14484 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
  14485   Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
  14486 };
  14487 
  14488 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
  14489   Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
  14490 };
  14491 
  14492 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
  14493   Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
  14494 };
  14495 
  14496 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
  14497   Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
  14498 };
  14499 
  14500 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
  14501   Opcode_mula_da_hh_Slot_inst_encode, 0, 0
  14502 };
  14503 
  14504 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
  14505   Opcode_mula_da_hl_Slot_inst_encode, 0, 0
  14506 };
  14507 
  14508 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
  14509   Opcode_mula_da_lh_Slot_inst_encode, 0, 0
  14510 };
  14511 
  14512 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
  14513   Opcode_mula_da_ll_Slot_inst_encode, 0, 0
  14514 };
  14515 
  14516 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
  14517   Opcode_muls_da_hh_Slot_inst_encode, 0, 0
  14518 };
  14519 
  14520 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
  14521   Opcode_muls_da_hl_Slot_inst_encode, 0, 0
  14522 };
  14523 
  14524 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
  14525   Opcode_muls_da_lh_Slot_inst_encode, 0, 0
  14526 };
  14527 
  14528 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
  14529   Opcode_muls_da_ll_Slot_inst_encode, 0, 0
  14530 };
  14531 
  14532 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
  14533   Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
  14534 };
  14535 
  14536 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
  14537   Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
  14538 };
  14539 
  14540 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
  14541   Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
  14542 };
  14543 
  14544 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
  14545   Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
  14546 };
  14547 
  14548 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
  14549   Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
  14550 };
  14551 
  14552 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
  14553   Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
  14554 };
  14555 
  14556 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
  14557   Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
  14558 };
  14559 
  14560 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
  14561   Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
  14562 };
  14563 
  14564 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
  14565   Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
  14566 };
  14567 
  14568 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
  14569   Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
  14570 };
  14571 
  14572 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
  14573   Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
  14574 };
  14575 
  14576 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
  14577   Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
  14578 };
  14579 
  14580 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
  14581   Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
  14582 };
  14583 
  14584 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
  14585   Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
  14586 };
  14587 
  14588 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
  14589   Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
  14590 };
  14591 
  14592 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
  14593   Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
  14594 };
  14595 
  14596 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
  14597   Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
  14598 };
  14599 
  14600 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
  14601   Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
  14602 };
  14603 
  14604 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
  14605   Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
  14606 };
  14607 
  14608 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
  14609   Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
  14610 };
  14611 
  14612 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
  14613   Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
  14614 };
  14615 
  14616 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
  14617   Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
  14618 };
  14619 
  14620 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
  14621   Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
  14622 };
  14623 
  14624 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
  14625   Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
  14626 };
  14627 
  14628 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
  14629   Opcode_lddec_Slot_inst_encode, 0, 0
  14630 };
  14631 
  14632 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
  14633   Opcode_ldinc_Slot_inst_encode, 0, 0
  14634 };
  14635 
  14636 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
  14637   Opcode_rsr_m0_Slot_inst_encode, 0, 0
  14638 };
  14639 
  14640 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
  14641   Opcode_wsr_m0_Slot_inst_encode, 0, 0
  14642 };
  14643 
  14644 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
  14645   Opcode_xsr_m0_Slot_inst_encode, 0, 0
  14646 };
  14647 
  14648 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
  14649   Opcode_rsr_m1_Slot_inst_encode, 0, 0
  14650 };
  14651 
  14652 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
  14653   Opcode_wsr_m1_Slot_inst_encode, 0, 0
  14654 };
  14655 
  14656 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
  14657   Opcode_xsr_m1_Slot_inst_encode, 0, 0
  14658 };
  14659 
  14660 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
  14661   Opcode_rsr_m2_Slot_inst_encode, 0, 0
  14662 };
  14663 
  14664 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
  14665   Opcode_wsr_m2_Slot_inst_encode, 0, 0
  14666 };
  14667 
  14668 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
  14669   Opcode_xsr_m2_Slot_inst_encode, 0, 0
  14670 };
  14671 
  14672 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
  14673   Opcode_rsr_m3_Slot_inst_encode, 0, 0
  14674 };
  14675 
  14676 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
  14677   Opcode_wsr_m3_Slot_inst_encode, 0, 0
  14678 };
  14679 
  14680 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
  14681   Opcode_xsr_m3_Slot_inst_encode, 0, 0
  14682 };
  14683 
  14684 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
  14685   Opcode_rsr_acclo_Slot_inst_encode, 0, 0
  14686 };
  14687 
  14688 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
  14689   Opcode_wsr_acclo_Slot_inst_encode, 0, 0
  14690 };
  14691 
  14692 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
  14693   Opcode_xsr_acclo_Slot_inst_encode, 0, 0
  14694 };
  14695 
  14696 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
  14697   Opcode_rsr_acchi_Slot_inst_encode, 0, 0
  14698 };
  14699 
  14700 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
  14701   Opcode_wsr_acchi_Slot_inst_encode, 0, 0
  14702 };
  14703 
  14704 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
  14705   Opcode_xsr_acchi_Slot_inst_encode, 0, 0
  14706 };
  14707 
  14708 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
  14709   Opcode_rfi_Slot_inst_encode, 0, 0
  14710 };
  14711 
  14712 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
  14713   Opcode_waiti_Slot_inst_encode, 0, 0
  14714 };
  14715 
  14716 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
  14717   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
  14718 };
  14719 
  14720 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
  14721   Opcode_wsr_intset_Slot_inst_encode, 0, 0
  14722 };
  14723 
  14724 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
  14725   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
  14726 };
  14727 
  14728 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
  14729   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
  14730 };
  14731 
  14732 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
  14733   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
  14734 };
  14735 
  14736 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
  14737   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
  14738 };
  14739 
  14740 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
  14741   Opcode_break_Slot_inst_encode, 0, 0
  14742 };
  14743 
  14744 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
  14745   0, 0, Opcode_break_n_Slot_inst16b_encode
  14746 };
  14747 
  14748 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
  14749   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
  14750 };
  14751 
  14752 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
  14753   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
  14754 };
  14755 
  14756 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
  14757   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
  14758 };
  14759 
  14760 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
  14761   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
  14762 };
  14763 
  14764 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
  14765   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
  14766 };
  14767 
  14768 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
  14769   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
  14770 };
  14771 
  14772 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
  14773   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
  14774 };
  14775 
  14776 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
  14777   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
  14778 };
  14779 
  14780 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
  14781   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
  14782 };
  14783 
  14784 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
  14785   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
  14786 };
  14787 
  14788 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
  14789   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
  14790 };
  14791 
  14792 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
  14793   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
  14794 };
  14795 
  14796 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
  14797   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
  14798 };
  14799 
  14800 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
  14801   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
  14802 };
  14803 
  14804 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
  14805   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
  14806 };
  14807 
  14808 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
  14809   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
  14810 };
  14811 
  14812 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
  14813   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
  14814 };
  14815 
  14816 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
  14817   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
  14818 };
  14819 
  14820 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
  14821   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
  14822 };
  14823 
  14824 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
  14825   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
  14826 };
  14827 
  14828 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
  14829   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
  14830 };
  14831 
  14832 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
  14833   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
  14834 };
  14835 
  14836 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
  14837   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
  14838 };
  14839 
  14840 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
  14841   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
  14842 };
  14843 
  14844 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
  14845   Opcode_rsr_icount_Slot_inst_encode, 0, 0
  14846 };
  14847 
  14848 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
  14849   Opcode_wsr_icount_Slot_inst_encode, 0, 0
  14850 };
  14851 
  14852 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
  14853   Opcode_xsr_icount_Slot_inst_encode, 0, 0
  14854 };
  14855 
  14856 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
  14857   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
  14858 };
  14859 
  14860 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
  14861   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
  14862 };
  14863 
  14864 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
  14865   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
  14866 };
  14867 
  14868 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
  14869   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
  14870 };
  14871 
  14872 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
  14873   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
  14874 };
  14875 
  14876 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
  14877   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
  14878 };
  14879 
  14880 static xtensa_opcode_encode_fn Opcode_lddr32_p_encode_fns[] = {
  14881   Opcode_lddr32_p_Slot_inst_encode, 0, 0
  14882 };
  14883 
  14884 static xtensa_opcode_encode_fn Opcode_sddr32_p_encode_fns[] = {
  14885   Opcode_sddr32_p_Slot_inst_encode, 0, 0
  14886 };
  14887 
  14888 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
  14889   Opcode_rfdo_Slot_inst_encode, 0, 0
  14890 };
  14891 
  14892 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
  14893   Opcode_rfdd_Slot_inst_encode, 0, 0
  14894 };
  14895 
  14896 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
  14897   Opcode_wsr_mmid_Slot_inst_encode, 0, 0
  14898 };
  14899 
  14900 static xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
  14901   Opcode_andb_Slot_inst_encode, 0, 0
  14902 };
  14903 
  14904 static xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
  14905   Opcode_andbc_Slot_inst_encode, 0, 0
  14906 };
  14907 
  14908 static xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
  14909   Opcode_orb_Slot_inst_encode, 0, 0
  14910 };
  14911 
  14912 static xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
  14913   Opcode_orbc_Slot_inst_encode, 0, 0
  14914 };
  14915 
  14916 static xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
  14917   Opcode_xorb_Slot_inst_encode, 0, 0
  14918 };
  14919 
  14920 static xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
  14921   Opcode_all4_Slot_inst_encode, 0, 0
  14922 };
  14923 
  14924 static xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
  14925   Opcode_any4_Slot_inst_encode, 0, 0
  14926 };
  14927 
  14928 static xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
  14929   Opcode_all8_Slot_inst_encode, 0, 0
  14930 };
  14931 
  14932 static xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
  14933   Opcode_any8_Slot_inst_encode, 0, 0
  14934 };
  14935 
  14936 static xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
  14937   Opcode_bf_Slot_inst_encode, 0, 0
  14938 };
  14939 
  14940 static xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
  14941   Opcode_bt_Slot_inst_encode, 0, 0
  14942 };
  14943 
  14944 static xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
  14945   Opcode_movf_Slot_inst_encode, 0, 0
  14946 };
  14947 
  14948 static xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
  14949   Opcode_movt_Slot_inst_encode, 0, 0
  14950 };
  14951 
  14952 static xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
  14953   Opcode_rsr_br_Slot_inst_encode, 0, 0
  14954 };
  14955 
  14956 static xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
  14957   Opcode_wsr_br_Slot_inst_encode, 0, 0
  14958 };
  14959 
  14960 static xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
  14961   Opcode_xsr_br_Slot_inst_encode, 0, 0
  14962 };
  14963 
  14964 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
  14965   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
  14966 };
  14967 
  14968 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
  14969   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
  14970 };
  14971 
  14972 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
  14973   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
  14974 };
  14975 
  14976 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
  14977   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
  14978 };
  14979 
  14980 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
  14981   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
  14982 };
  14983 
  14984 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
  14985   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
  14986 };
  14987 
  14988 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
  14989   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
  14990 };
  14991 
  14992 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
  14993   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
  14994 };
  14995 
  14996 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
  14997   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
  14998 };
  14999 
  15000 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
  15001   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
  15002 };
  15003 
  15004 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
  15005   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
  15006 };
  15007 
  15008 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
  15009   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
  15010 };
  15011 
  15012 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
  15013   Opcode_ihi_Slot_inst_encode, 0, 0
  15014 };
  15015 
  15016 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
  15017   Opcode_ipf_Slot_inst_encode, 0, 0
  15018 };
  15019 
  15020 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
  15021   Opcode_ihu_Slot_inst_encode, 0, 0
  15022 };
  15023 
  15024 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
  15025   Opcode_iiu_Slot_inst_encode, 0, 0
  15026 };
  15027 
  15028 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
  15029   Opcode_ipfl_Slot_inst_encode, 0, 0
  15030 };
  15031 
  15032 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
  15033   Opcode_iii_Slot_inst_encode, 0, 0
  15034 };
  15035 
  15036 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
  15037   Opcode_lict_Slot_inst_encode, 0, 0
  15038 };
  15039 
  15040 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
  15041   Opcode_licw_Slot_inst_encode, 0, 0
  15042 };
  15043 
  15044 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
  15045   Opcode_sict_Slot_inst_encode, 0, 0
  15046 };
  15047 
  15048 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
  15049   Opcode_sicw_Slot_inst_encode, 0, 0
  15050 };
  15051 
  15052 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
  15053   Opcode_dhwb_Slot_inst_encode, 0, 0
  15054 };
  15055 
  15056 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
  15057   Opcode_dhwbi_Slot_inst_encode, 0, 0
  15058 };
  15059 
  15060 static xtensa_opcode_encode_fn Opcode_diwbui_p_encode_fns[] = {
  15061   Opcode_diwbui_p_Slot_inst_encode, 0, 0
  15062 };
  15063 
  15064 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
  15065   Opcode_diwb_Slot_inst_encode, 0, 0
  15066 };
  15067 
  15068 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
  15069   Opcode_diwbi_Slot_inst_encode, 0, 0
  15070 };
  15071 
  15072 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
  15073   Opcode_dhi_Slot_inst_encode, 0, 0
  15074 };
  15075 
  15076 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
  15077   Opcode_dii_Slot_inst_encode, 0, 0
  15078 };
  15079 
  15080 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
  15081   Opcode_dpfr_Slot_inst_encode, 0, 0
  15082 };
  15083 
  15084 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
  15085   Opcode_dpfro_Slot_inst_encode, 0, 0
  15086 };
  15087 
  15088 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
  15089   Opcode_dpfw_Slot_inst_encode, 0, 0
  15090 };
  15091 
  15092 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
  15093   Opcode_dpfwo_Slot_inst_encode, 0, 0
  15094 };
  15095 
  15096 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
  15097   Opcode_dhu_Slot_inst_encode, 0, 0
  15098 };
  15099 
  15100 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
  15101   Opcode_diu_Slot_inst_encode, 0, 0
  15102 };
  15103 
  15104 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
  15105   Opcode_dpfl_Slot_inst_encode, 0, 0
  15106 };
  15107 
  15108 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
  15109   Opcode_sdct_Slot_inst_encode, 0, 0
  15110 };
  15111 
  15112 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
  15113   Opcode_ldct_Slot_inst_encode, 0, 0
  15114 };
  15115 
  15116 static xtensa_opcode_encode_fn Opcode_sdcw_encode_fns[] = {
  15117   Opcode_sdcw_Slot_inst_encode, 0, 0
  15118 };
  15119 
  15120 static xtensa_opcode_encode_fn Opcode_ldcw_encode_fns[] = {
  15121   Opcode_ldcw_Slot_inst_encode, 0, 0
  15122 };
  15123 
  15124 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
  15125   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
  15126 };
  15127 
  15128 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
  15129   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
  15130 };
  15131 
  15132 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
  15133   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
  15134 };
  15135 
  15136 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
  15137   Opcode_rsr_rasid_Slot_inst_encode, 0, 0
  15138 };
  15139 
  15140 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
  15141   Opcode_wsr_rasid_Slot_inst_encode, 0, 0
  15142 };
  15143 
  15144 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
  15145   Opcode_xsr_rasid_Slot_inst_encode, 0, 0
  15146 };
  15147 
  15148 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
  15149   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
  15150 };
  15151 
  15152 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
  15153   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
  15154 };
  15155 
  15156 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
  15157   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
  15158 };
  15159 
  15160 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
  15161   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
  15162 };
  15163 
  15164 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
  15165   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
  15166 };
  15167 
  15168 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
  15169   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
  15170 };
  15171 
  15172 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
  15173   Opcode_idtlb_Slot_inst_encode, 0, 0
  15174 };
  15175 
  15176 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
  15177   Opcode_pdtlb_Slot_inst_encode, 0, 0
  15178 };
  15179 
  15180 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
  15181   Opcode_rdtlb0_Slot_inst_encode, 0, 0
  15182 };
  15183 
  15184 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
  15185   Opcode_rdtlb1_Slot_inst_encode, 0, 0
  15186 };
  15187 
  15188 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
  15189   Opcode_wdtlb_Slot_inst_encode, 0, 0
  15190 };
  15191 
  15192 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
  15193   Opcode_iitlb_Slot_inst_encode, 0, 0
  15194 };
  15195 
  15196 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
  15197   Opcode_pitlb_Slot_inst_encode, 0, 0
  15198 };
  15199 
  15200 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
  15201   Opcode_ritlb0_Slot_inst_encode, 0, 0
  15202 };
  15203 
  15204 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
  15205   Opcode_ritlb1_Slot_inst_encode, 0, 0
  15206 };
  15207 
  15208 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
  15209   Opcode_witlb_Slot_inst_encode, 0, 0
  15210 };
  15211 
  15212 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
  15213   Opcode_ldpte_Slot_inst_encode, 0, 0
  15214 };
  15215 
  15216 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
  15217   Opcode_hwwitlba_Slot_inst_encode, 0, 0
  15218 };
  15219 
  15220 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
  15221   Opcode_hwwdtlba_Slot_inst_encode, 0, 0
  15222 };
  15223 
  15224 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
  15225   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
  15226 };
  15227 
  15228 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
  15229   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
  15230 };
  15231 
  15232 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
  15233   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
  15234 };
  15235 
  15236 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
  15237   Opcode_clamps_Slot_inst_encode, 0, 0
  15238 };
  15239 
  15240 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
  15241   Opcode_max_Slot_inst_encode, 0, 0
  15242 };
  15243 
  15244 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
  15245   Opcode_maxu_Slot_inst_encode, 0, 0
  15246 };
  15247 
  15248 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
  15249   Opcode_min_Slot_inst_encode, 0, 0
  15250 };
  15251 
  15252 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
  15253   Opcode_minu_Slot_inst_encode, 0, 0
  15254 };
  15255 
  15256 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
  15257   Opcode_nsa_Slot_inst_encode, 0, 0
  15258 };
  15259 
  15260 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
  15261   Opcode_nsau_Slot_inst_encode, 0, 0
  15262 };
  15263 
  15264 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
  15265   Opcode_sext_Slot_inst_encode, 0, 0
  15266 };
  15267 
  15268 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
  15269   Opcode_l32ai_Slot_inst_encode, 0, 0
  15270 };
  15271 
  15272 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
  15273   Opcode_s32ri_Slot_inst_encode, 0, 0
  15274 };
  15275 
  15276 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
  15277   Opcode_s32c1i_Slot_inst_encode, 0, 0
  15278 };
  15279 
  15280 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
  15281   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
  15282 };
  15283 
  15284 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
  15285   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
  15286 };
  15287 
  15288 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
  15289   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
  15290 };
  15291 
  15292 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
  15293   Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
  15294 };
  15295 
  15296 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
  15297   Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
  15298 };
  15299 
  15300 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
  15301   Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
  15302 };
  15303 
  15304 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
  15305   Opcode_quos_Slot_inst_encode, 0, 0
  15306 };
  15307 
  15308 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
  15309   Opcode_quou_Slot_inst_encode, 0, 0
  15310 };
  15311 
  15312 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
  15313   Opcode_rems_Slot_inst_encode, 0, 0
  15314 };
  15315 
  15316 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
  15317   Opcode_remu_Slot_inst_encode, 0, 0
  15318 };
  15319 
  15320 static xtensa_opcode_encode_fn Opcode_rsr_eraccess_encode_fns[] = {
  15321   Opcode_rsr_eraccess_Slot_inst_encode, 0, 0
  15322 };
  15323 
  15324 static xtensa_opcode_encode_fn Opcode_wsr_eraccess_encode_fns[] = {
  15325   Opcode_wsr_eraccess_Slot_inst_encode, 0, 0
  15326 };
  15327 
  15328 static xtensa_opcode_encode_fn Opcode_xsr_eraccess_encode_fns[] = {
  15329   Opcode_xsr_eraccess_Slot_inst_encode, 0, 0
  15330 };
  15331 
  15332 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
  15333   Opcode_rer_Slot_inst_encode, 0, 0
  15334 };
  15335 
  15336 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
  15337   Opcode_wer_Slot_inst_encode, 0, 0
  15338 };
  15339 
  15340 static xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
  15341   Opcode_rur_fcr_Slot_inst_encode, 0, 0
  15342 };
  15343 
  15344 static xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
  15345   Opcode_wur_fcr_Slot_inst_encode, 0, 0
  15346 };
  15347 
  15348 static xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
  15349   Opcode_rur_fsr_Slot_inst_encode, 0, 0
  15350 };
  15351 
  15352 static xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
  15353   Opcode_wur_fsr_Slot_inst_encode, 0, 0
  15354 };
  15355 
  15356 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
  15357   Opcode_read_impwire_Slot_inst_encode, 0, 0
  15358 };
  15359 
  15360 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
  15361   Opcode_setb_expstate_Slot_inst_encode, 0, 0
  15362 };
  15363 
  15364 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
  15365   Opcode_clrb_expstate_Slot_inst_encode, 0, 0
  15366 };
  15367 
  15368 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
  15369   Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
  15370 };
  15371 
  15372 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
  15373   Opcode_rur_expstate_Slot_inst_encode, 0, 0
  15374 };
  15375 
  15376 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
  15377   Opcode_wur_expstate_Slot_inst_encode, 0, 0
  15378 };
  15379 
  15380 static xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
  15381   Opcode_lsi_Slot_inst_encode, 0, 0
  15382 };
  15383 
  15384 static xtensa_opcode_encode_fn Opcode_lsip_encode_fns[] = {
  15385   Opcode_lsip_Slot_inst_encode, 0, 0
  15386 };
  15387 
  15388 static xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
  15389   Opcode_lsx_Slot_inst_encode, 0, 0
  15390 };
  15391 
  15392 static xtensa_opcode_encode_fn Opcode_lsxp_encode_fns[] = {
  15393   Opcode_lsxp_Slot_inst_encode, 0, 0
  15394 };
  15395 
  15396 static xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
  15397   Opcode_ssi_Slot_inst_encode, 0, 0
  15398 };
  15399 
  15400 static xtensa_opcode_encode_fn Opcode_ssip_encode_fns[] = {
  15401   Opcode_ssip_Slot_inst_encode, 0, 0
  15402 };
  15403 
  15404 static xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
  15405   Opcode_ssx_Slot_inst_encode, 0, 0
  15406 };
  15407 
  15408 static xtensa_opcode_encode_fn Opcode_ssxp_encode_fns[] = {
  15409   Opcode_ssxp_Slot_inst_encode, 0, 0
  15410 };
  15411 
  15412 static xtensa_opcode_encode_fn Opcode_ldi_encode_fns[] = {
  15413   Opcode_ldi_Slot_inst_encode, 0, 0
  15414 };
  15415 
  15416 static xtensa_opcode_encode_fn Opcode_ldip_encode_fns[] = {
  15417   Opcode_ldip_Slot_inst_encode, 0, 0
  15418 };
  15419 
  15420 static xtensa_opcode_encode_fn Opcode_ldx_encode_fns[] = {
  15421   Opcode_ldx_Slot_inst_encode, 0, 0
  15422 };
  15423 
  15424 static xtensa_opcode_encode_fn Opcode_ldxp_encode_fns[] = {
  15425   Opcode_ldxp_Slot_inst_encode, 0, 0
  15426 };
  15427 
  15428 static xtensa_opcode_encode_fn Opcode_sdi_encode_fns[] = {
  15429   Opcode_sdi_Slot_inst_encode, 0, 0
  15430 };
  15431 
  15432 static xtensa_opcode_encode_fn Opcode_sdip_encode_fns[] = {
  15433   Opcode_sdip_Slot_inst_encode, 0, 0
  15434 };
  15435 
  15436 static xtensa_opcode_encode_fn Opcode_sdx_encode_fns[] = {
  15437   Opcode_sdx_Slot_inst_encode, 0, 0
  15438 };
  15439 
  15440 static xtensa_opcode_encode_fn Opcode_sdxp_encode_fns[] = {
  15441   Opcode_sdxp_Slot_inst_encode, 0, 0
  15442 };
  15443 
  15444 static xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
  15445   Opcode_abs_s_Slot_inst_encode, 0, 0
  15446 };
  15447 
  15448 static xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
  15449   Opcode_neg_s_Slot_inst_encode, 0, 0
  15450 };
  15451 
  15452 static xtensa_opcode_encode_fn Opcode_abs_d_encode_fns[] = {
  15453   Opcode_abs_d_Slot_inst_encode, 0, 0
  15454 };
  15455 
  15456 static xtensa_opcode_encode_fn Opcode_neg_d_encode_fns[] = {
  15457   Opcode_neg_d_Slot_inst_encode, 0, 0
  15458 };
  15459 
  15460 static xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
  15461   Opcode_mov_s_Slot_inst_encode, 0, 0
  15462 };
  15463 
  15464 static xtensa_opcode_encode_fn Opcode_mov_d_encode_fns[] = {
  15465   Opcode_mov_d_Slot_inst_encode, 0, 0
  15466 };
  15467 
  15468 static xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
  15469   Opcode_moveqz_s_Slot_inst_encode, 0, 0
  15470 };
  15471 
  15472 static xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
  15473   Opcode_movnez_s_Slot_inst_encode, 0, 0
  15474 };
  15475 
  15476 static xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
  15477   Opcode_movltz_s_Slot_inst_encode, 0, 0
  15478 };
  15479 
  15480 static xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
  15481   Opcode_movgez_s_Slot_inst_encode, 0, 0
  15482 };
  15483 
  15484 static xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
  15485   Opcode_movf_s_Slot_inst_encode, 0, 0
  15486 };
  15487 
  15488 static xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
  15489   Opcode_movt_s_Slot_inst_encode, 0, 0
  15490 };
  15491 
  15492 static xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
  15493   Opcode_wfr_Slot_inst_encode, 0, 0
  15494 };
  15495 
  15496 static xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
  15497   Opcode_rfr_Slot_inst_encode, 0, 0
  15498 };
  15499 
  15500 static xtensa_opcode_encode_fn Opcode_rfrd_encode_fns[] = {
  15501   Opcode_rfrd_Slot_inst_encode, 0, 0
  15502 };
  15503 
  15504 static xtensa_opcode_encode_fn Opcode_wfrd_encode_fns[] = {
  15505   Opcode_wfrd_Slot_inst_encode, 0, 0
  15506 };
  15507 
  15508 static xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
  15509   Opcode_round_s_Slot_inst_encode, 0, 0
  15510 };
  15511 
  15512 static xtensa_opcode_encode_fn Opcode_round_d_encode_fns[] = {
  15513   Opcode_round_d_Slot_inst_encode, 0, 0
  15514 };
  15515 
  15516 static xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
  15517   Opcode_ceil_s_Slot_inst_encode, 0, 0
  15518 };
  15519 
  15520 static xtensa_opcode_encode_fn Opcode_ceil_d_encode_fns[] = {
  15521   Opcode_ceil_d_Slot_inst_encode, 0, 0
  15522 };
  15523 
  15524 static xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
  15525   Opcode_floor_s_Slot_inst_encode, 0, 0
  15526 };
  15527 
  15528 static xtensa_opcode_encode_fn Opcode_floor_d_encode_fns[] = {
  15529   Opcode_floor_d_Slot_inst_encode, 0, 0
  15530 };
  15531 
  15532 static xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
  15533   Opcode_trunc_s_Slot_inst_encode, 0, 0
  15534 };
  15535 
  15536 static xtensa_opcode_encode_fn Opcode_trunc_d_encode_fns[] = {
  15537   Opcode_trunc_d_Slot_inst_encode, 0, 0
  15538 };
  15539 
  15540 static xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
  15541   Opcode_utrunc_s_Slot_inst_encode, 0, 0
  15542 };
  15543 
  15544 static xtensa_opcode_encode_fn Opcode_utrunc_d_encode_fns[] = {
  15545   Opcode_utrunc_d_Slot_inst_encode, 0, 0
  15546 };
  15547 
  15548 static xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
  15549   Opcode_float_s_Slot_inst_encode, 0, 0
  15550 };
  15551 
  15552 static xtensa_opcode_encode_fn Opcode_float_d_encode_fns[] = {
  15553   Opcode_float_d_Slot_inst_encode, 0, 0
  15554 };
  15555 
  15556 static xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
  15557   Opcode_ufloat_s_Slot_inst_encode, 0, 0
  15558 };
  15559 
  15560 static xtensa_opcode_encode_fn Opcode_ufloat_d_encode_fns[] = {
  15561   Opcode_ufloat_d_Slot_inst_encode, 0, 0
  15562 };
  15563 
  15564 static xtensa_opcode_encode_fn Opcode_cvtd_s_encode_fns[] = {
  15565   Opcode_cvtd_s_Slot_inst_encode, 0, 0
  15566 };
  15567 
  15568 static xtensa_opcode_encode_fn Opcode_cvts_d_encode_fns[] = {
  15569   Opcode_cvts_d_Slot_inst_encode, 0, 0
  15570 };
  15571 
  15572 static xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
  15573   Opcode_un_s_Slot_inst_encode, 0, 0
  15574 };
  15575 
  15576 static xtensa_opcode_encode_fn Opcode_un_d_encode_fns[] = {
  15577   Opcode_un_d_Slot_inst_encode, 0, 0
  15578 };
  15579 
  15580 static xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
  15581   Opcode_ult_s_Slot_inst_encode, 0, 0
  15582 };
  15583 
  15584 static xtensa_opcode_encode_fn Opcode_ult_d_encode_fns[] = {
  15585   Opcode_ult_d_Slot_inst_encode, 0, 0
  15586 };
  15587 
  15588 static xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
  15589   Opcode_ule_s_Slot_inst_encode, 0, 0
  15590 };
  15591 
  15592 static xtensa_opcode_encode_fn Opcode_ule_d_encode_fns[] = {
  15593   Opcode_ule_d_Slot_inst_encode, 0, 0
  15594 };
  15595 
  15596 static xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
  15597   Opcode_ueq_s_Slot_inst_encode, 0, 0
  15598 };
  15599 
  15600 static xtensa_opcode_encode_fn Opcode_ueq_d_encode_fns[] = {
  15601   Opcode_ueq_d_Slot_inst_encode, 0, 0
  15602 };
  15603 
  15604 static xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
  15605   Opcode_olt_s_Slot_inst_encode, 0, 0
  15606 };
  15607 
  15608 static xtensa_opcode_encode_fn Opcode_olt_d_encode_fns[] = {
  15609   Opcode_olt_d_Slot_inst_encode, 0, 0
  15610 };
  15611 
  15612 static xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
  15613   Opcode_ole_s_Slot_inst_encode, 0, 0
  15614 };
  15615 
  15616 static xtensa_opcode_encode_fn Opcode_ole_d_encode_fns[] = {
  15617   Opcode_ole_d_Slot_inst_encode, 0, 0
  15618 };
  15619 
  15620 static xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
  15621   Opcode_oeq_s_Slot_inst_encode, 0, 0
  15622 };
  15623 
  15624 static xtensa_opcode_encode_fn Opcode_oeq_d_encode_fns[] = {
  15625   Opcode_oeq_d_Slot_inst_encode, 0, 0
  15626 };
  15627 
  15628 static xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
  15629   Opcode_add_s_Slot_inst_encode, 0, 0
  15630 };
  15631 
  15632 static xtensa_opcode_encode_fn Opcode_add_d_encode_fns[] = {
  15633   Opcode_add_d_Slot_inst_encode, 0, 0
  15634 };
  15635 
  15636 static xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
  15637   Opcode_sub_s_Slot_inst_encode, 0, 0
  15638 };
  15639 
  15640 static xtensa_opcode_encode_fn Opcode_sub_d_encode_fns[] = {
  15641   Opcode_sub_d_Slot_inst_encode, 0, 0
  15642 };
  15643 
  15644 static xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
  15645   Opcode_mul_s_Slot_inst_encode, 0, 0
  15646 };
  15647 
  15648 static xtensa_opcode_encode_fn Opcode_mul_d_encode_fns[] = {
  15649   Opcode_mul_d_Slot_inst_encode, 0, 0
  15650 };
  15651 
  15652 static xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
  15653   Opcode_madd_s_Slot_inst_encode, 0, 0
  15654 };
  15655 
  15656 static xtensa_opcode_encode_fn Opcode_madd_d_encode_fns[] = {
  15657   Opcode_madd_d_Slot_inst_encode, 0, 0
  15658 };
  15659 
  15660 static xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
  15661   Opcode_msub_s_Slot_inst_encode, 0, 0
  15662 };
  15663 
  15664 static xtensa_opcode_encode_fn Opcode_msub_d_encode_fns[] = {
  15665   Opcode_msub_d_Slot_inst_encode, 0, 0
  15666 };
  15667 
  15668 static xtensa_opcode_encode_fn Opcode_sqrt0_s_encode_fns[] = {
  15669   Opcode_sqrt0_s_Slot_inst_encode, 0, 0
  15670 };
  15671 
  15672 static xtensa_opcode_encode_fn Opcode_sqrt0_d_encode_fns[] = {
  15673   Opcode_sqrt0_d_Slot_inst_encode, 0, 0
  15674 };
  15675 
  15676 static xtensa_opcode_encode_fn Opcode_div0_s_encode_fns[] = {
  15677   Opcode_div0_s_Slot_inst_encode, 0, 0
  15678 };
  15679 
  15680 static xtensa_opcode_encode_fn Opcode_div0_d_encode_fns[] = {
  15681   Opcode_div0_d_Slot_inst_encode, 0, 0
  15682 };
  15683 
  15684 static xtensa_opcode_encode_fn Opcode_recip0_s_encode_fns[] = {
  15685   Opcode_recip0_s_Slot_inst_encode, 0, 0
  15686 };
  15687 
  15688 static xtensa_opcode_encode_fn Opcode_recip0_d_encode_fns[] = {
  15689   Opcode_recip0_d_Slot_inst_encode, 0, 0
  15690 };
  15691 
  15692 static xtensa_opcode_encode_fn Opcode_rsqrt0_s_encode_fns[] = {
  15693   Opcode_rsqrt0_s_Slot_inst_encode, 0, 0
  15694 };
  15695 
  15696 static xtensa_opcode_encode_fn Opcode_rsqrt0_d_encode_fns[] = {
  15697   Opcode_rsqrt0_d_Slot_inst_encode, 0, 0
  15698 };
  15699 
  15700 static xtensa_opcode_encode_fn Opcode_maddn_s_encode_fns[] = {
  15701   Opcode_maddn_s_Slot_inst_encode, 0, 0
  15702 };
  15703 
  15704 static xtensa_opcode_encode_fn Opcode_maddn_d_encode_fns[] = {
  15705   Opcode_maddn_d_Slot_inst_encode, 0, 0
  15706 };
  15707 
  15708 static xtensa_opcode_encode_fn Opcode_divn_s_encode_fns[] = {
  15709   Opcode_divn_s_Slot_inst_encode, 0, 0
  15710 };
  15711 
  15712 static xtensa_opcode_encode_fn Opcode_divn_d_encode_fns[] = {
  15713   Opcode_divn_d_Slot_inst_encode, 0, 0
  15714 };
  15715 
  15716 static xtensa_opcode_encode_fn Opcode_const_s_encode_fns[] = {
  15717   Opcode_const_s_Slot_inst_encode, 0, 0
  15718 };
  15719 
  15720 static xtensa_opcode_encode_fn Opcode_const_d_encode_fns[] = {
  15721   Opcode_const_d_Slot_inst_encode, 0, 0
  15722 };
  15723 
  15724 static xtensa_opcode_encode_fn Opcode_nexp01_s_encode_fns[] = {
  15725   Opcode_nexp01_s_Slot_inst_encode, 0, 0
  15726 };
  15727 
  15728 static xtensa_opcode_encode_fn Opcode_nexp01_d_encode_fns[] = {
  15729   Opcode_nexp01_d_Slot_inst_encode, 0, 0
  15730 };
  15731 
  15732 static xtensa_opcode_encode_fn Opcode_addexp_s_encode_fns[] = {
  15733   Opcode_addexp_s_Slot_inst_encode, 0, 0
  15734 };
  15735 
  15736 static xtensa_opcode_encode_fn Opcode_addexp_d_encode_fns[] = {
  15737   Opcode_addexp_d_Slot_inst_encode, 0, 0
  15738 };
  15739 
  15740 static xtensa_opcode_encode_fn Opcode_addexpm_s_encode_fns[] = {
  15741   Opcode_addexpm_s_Slot_inst_encode, 0, 0
  15742 };
  15743 
  15744 static xtensa_opcode_encode_fn Opcode_addexpm_d_encode_fns[] = {
  15745   Opcode_addexpm_d_Slot_inst_encode, 0, 0
  15746 };
  15747 
  15748 static xtensa_opcode_encode_fn Opcode_mkdadj_s_encode_fns[] = {
  15749   Opcode_mkdadj_s_Slot_inst_encode, 0, 0
  15750 };
  15751 
  15752 static xtensa_opcode_encode_fn Opcode_mkdadj_d_encode_fns[] = {
  15753   Opcode_mkdadj_d_Slot_inst_encode, 0, 0
  15754 };
  15755 
  15756 static xtensa_opcode_encode_fn Opcode_mksadj_s_encode_fns[] = {
  15757   Opcode_mksadj_s_Slot_inst_encode, 0, 0
  15758 };
  15759 
  15760 static xtensa_opcode_encode_fn Opcode_mksadj_d_encode_fns[] = {
  15761   Opcode_mksadj_d_Slot_inst_encode, 0, 0
  15762 };
  15763 
  15764 
  15765 
  15766 
  15767 
  15768 /* Opcode table.  */
  15769 
  15770 static xtensa_funcUnit_use Opcode_l32e_funcUnit_uses[] = {
  15771   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15772 };
  15773 
  15774 static xtensa_funcUnit_use Opcode_s32e_funcUnit_uses[] = {
  15775   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15776 };
  15777 
  15778 static xtensa_funcUnit_use Opcode_l32i_n_funcUnit_uses[] = {
  15779   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15780 };
  15781 
  15782 static xtensa_funcUnit_use Opcode_s32i_n_funcUnit_uses[] = {
  15783   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15784 };
  15785 
  15786 static xtensa_funcUnit_use Opcode_l16ui_funcUnit_uses[] = {
  15787   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15788 };
  15789 
  15790 static xtensa_funcUnit_use Opcode_l16si_funcUnit_uses[] = {
  15791   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15792 };
  15793 
  15794 static xtensa_funcUnit_use Opcode_l32i_funcUnit_uses[] = {
  15795   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15796 };
  15797 
  15798 static xtensa_funcUnit_use Opcode_l32r_funcUnit_uses[] = {
  15799   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15800 };
  15801 
  15802 static xtensa_funcUnit_use Opcode_l8ui_funcUnit_uses[] = {
  15803   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15804 };
  15805 
  15806 static xtensa_funcUnit_use Opcode_s16i_funcUnit_uses[] = {
  15807   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15808 };
  15809 
  15810 static xtensa_funcUnit_use Opcode_s32i_funcUnit_uses[] = {
  15811   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15812 };
  15813 
  15814 static xtensa_funcUnit_use Opcode_s32nb_funcUnit_uses[] = {
  15815   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15816 };
  15817 
  15818 static xtensa_funcUnit_use Opcode_s8i_funcUnit_uses[] = {
  15819   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15820 };
  15821 
  15822 static xtensa_funcUnit_use Opcode_mula_da_hh_lddec_funcUnit_uses[] = {
  15823   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15824 };
  15825 
  15826 static xtensa_funcUnit_use Opcode_mula_da_hh_ldinc_funcUnit_uses[] = {
  15827   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15828 };
  15829 
  15830 static xtensa_funcUnit_use Opcode_mula_da_hl_lddec_funcUnit_uses[] = {
  15831   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15832 };
  15833 
  15834 static xtensa_funcUnit_use Opcode_mula_da_hl_ldinc_funcUnit_uses[] = {
  15835   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15836 };
  15837 
  15838 static xtensa_funcUnit_use Opcode_mula_da_lh_lddec_funcUnit_uses[] = {
  15839   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15840 };
  15841 
  15842 static xtensa_funcUnit_use Opcode_mula_da_lh_ldinc_funcUnit_uses[] = {
  15843   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15844 };
  15845 
  15846 static xtensa_funcUnit_use Opcode_mula_da_ll_lddec_funcUnit_uses[] = {
  15847   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15848 };
  15849 
  15850 static xtensa_funcUnit_use Opcode_mula_da_ll_ldinc_funcUnit_uses[] = {
  15851   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15852 };
  15853 
  15854 static xtensa_funcUnit_use Opcode_mula_dd_hh_lddec_funcUnit_uses[] = {
  15855   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15856 };
  15857 
  15858 static xtensa_funcUnit_use Opcode_mula_dd_hh_ldinc_funcUnit_uses[] = {
  15859   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15860 };
  15861 
  15862 static xtensa_funcUnit_use Opcode_mula_dd_hl_lddec_funcUnit_uses[] = {
  15863   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15864 };
  15865 
  15866 static xtensa_funcUnit_use Opcode_mula_dd_hl_ldinc_funcUnit_uses[] = {
  15867   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15868 };
  15869 
  15870 static xtensa_funcUnit_use Opcode_mula_dd_lh_lddec_funcUnit_uses[] = {
  15871   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15872 };
  15873 
  15874 static xtensa_funcUnit_use Opcode_mula_dd_lh_ldinc_funcUnit_uses[] = {
  15875   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15876 };
  15877 
  15878 static xtensa_funcUnit_use Opcode_mula_dd_ll_lddec_funcUnit_uses[] = {
  15879   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15880 };
  15881 
  15882 static xtensa_funcUnit_use Opcode_mula_dd_ll_ldinc_funcUnit_uses[] = {
  15883   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15884 };
  15885 
  15886 static xtensa_funcUnit_use Opcode_lddec_funcUnit_uses[] = {
  15887   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15888 };
  15889 
  15890 static xtensa_funcUnit_use Opcode_ldinc_funcUnit_uses[] = {
  15891   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15892 };
  15893 
  15894 static xtensa_funcUnit_use Opcode_lddr32_p_funcUnit_uses[] = {
  15895   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15896 };
  15897 
  15898 static xtensa_funcUnit_use Opcode_sddr32_p_funcUnit_uses[] = {
  15899   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15900 };
  15901 
  15902 static xtensa_funcUnit_use Opcode_lict_funcUnit_uses[] = {
  15903   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15904 };
  15905 
  15906 static xtensa_funcUnit_use Opcode_licw_funcUnit_uses[] = {
  15907   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15908 };
  15909 
  15910 static xtensa_funcUnit_use Opcode_sict_funcUnit_uses[] = {
  15911   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15912 };
  15913 
  15914 static xtensa_funcUnit_use Opcode_sicw_funcUnit_uses[] = {
  15915   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15916 };
  15917 
  15918 static xtensa_funcUnit_use Opcode_sdct_funcUnit_uses[] = {
  15919   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15920 };
  15921 
  15922 static xtensa_funcUnit_use Opcode_ldct_funcUnit_uses[] = {
  15923   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15924 };
  15925 
  15926 static xtensa_funcUnit_use Opcode_sdcw_funcUnit_uses[] = {
  15927   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15928 };
  15929 
  15930 static xtensa_funcUnit_use Opcode_ldcw_funcUnit_uses[] = {
  15931   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15932 };
  15933 
  15934 static xtensa_funcUnit_use Opcode_ldpte_funcUnit_uses[] = {
  15935   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15936 };
  15937 
  15938 static xtensa_funcUnit_use Opcode_l32ai_funcUnit_uses[] = {
  15939   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15940 };
  15941 
  15942 static xtensa_funcUnit_use Opcode_s32ri_funcUnit_uses[] = {
  15943   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15944 };
  15945 
  15946 static xtensa_funcUnit_use Opcode_s32c1i_funcUnit_uses[] = {
  15947   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15948 };
  15949 
  15950 static xtensa_funcUnit_use Opcode_lsi_funcUnit_uses[] = {
  15951   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15952 };
  15953 
  15954 static xtensa_funcUnit_use Opcode_lsip_funcUnit_uses[] = {
  15955   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15956 };
  15957 
  15958 static xtensa_funcUnit_use Opcode_lsx_funcUnit_uses[] = {
  15959   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15960 };
  15961 
  15962 static xtensa_funcUnit_use Opcode_lsxp_funcUnit_uses[] = {
  15963   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15964 };
  15965 
  15966 static xtensa_funcUnit_use Opcode_ssi_funcUnit_uses[] = {
  15967   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15968 };
  15969 
  15970 static xtensa_funcUnit_use Opcode_ssip_funcUnit_uses[] = {
  15971   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15972 };
  15973 
  15974 static xtensa_funcUnit_use Opcode_ssx_funcUnit_uses[] = {
  15975   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15976 };
  15977 
  15978 static xtensa_funcUnit_use Opcode_ssxp_funcUnit_uses[] = {
  15979   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15980 };
  15981 
  15982 static xtensa_funcUnit_use Opcode_ldi_funcUnit_uses[] = {
  15983   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15984 };
  15985 
  15986 static xtensa_funcUnit_use Opcode_ldip_funcUnit_uses[] = {
  15987   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15988 };
  15989 
  15990 static xtensa_funcUnit_use Opcode_ldx_funcUnit_uses[] = {
  15991   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15992 };
  15993 
  15994 static xtensa_funcUnit_use Opcode_ldxp_funcUnit_uses[] = {
  15995   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  15996 };
  15997 
  15998 static xtensa_funcUnit_use Opcode_sdi_funcUnit_uses[] = {
  15999   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  16000 };
  16001 
  16002 static xtensa_funcUnit_use Opcode_sdip_funcUnit_uses[] = {
  16003   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  16004 };
  16005 
  16006 static xtensa_funcUnit_use Opcode_sdx_funcUnit_uses[] = {
  16007   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  16008 };
  16009 
  16010 static xtensa_funcUnit_use Opcode_sdxp_funcUnit_uses[] = {
  16011   { FUNCUNIT_XT_LOADSTORE_UNIT, 0 }
  16012 };
  16013 
  16014 static xtensa_opcode_internal opcodes[] = {
  16015   { "excw", ICLASS_xt_iclass_excw,
  16016     0,
  16017     Opcode_excw_encode_fns, 0, 0 },
  16018   { "rfe", ICLASS_xt_iclass_rfe,
  16019     XTENSA_OPCODE_IS_JUMP,
  16020     Opcode_rfe_encode_fns, 0, 0 },
  16021   { "rfde", ICLASS_xt_iclass_rfde,
  16022     XTENSA_OPCODE_IS_JUMP,
  16023     Opcode_rfde_encode_fns, 0, 0 },
  16024   { "syscall", ICLASS_xt_iclass_syscall,
  16025     0,
  16026     Opcode_syscall_encode_fns, 0, 0 },
  16027   { "call12", ICLASS_xt_iclass_call12,
  16028     XTENSA_OPCODE_IS_CALL,
  16029     Opcode_call12_encode_fns, 0, 0 },
  16030   { "call8", ICLASS_xt_iclass_call8,
  16031     XTENSA_OPCODE_IS_CALL,
  16032     Opcode_call8_encode_fns, 0, 0 },
  16033   { "call4", ICLASS_xt_iclass_call4,
  16034     XTENSA_OPCODE_IS_CALL,
  16035     Opcode_call4_encode_fns, 0, 0 },
  16036   { "callx12", ICLASS_xt_iclass_callx12,
  16037     XTENSA_OPCODE_IS_CALL,
  16038     Opcode_callx12_encode_fns, 0, 0 },
  16039   { "callx8", ICLASS_xt_iclass_callx8,
  16040     XTENSA_OPCODE_IS_CALL,
  16041     Opcode_callx8_encode_fns, 0, 0 },
  16042   { "callx4", ICLASS_xt_iclass_callx4,
  16043     XTENSA_OPCODE_IS_CALL,
  16044     Opcode_callx4_encode_fns, 0, 0 },
  16045   { "entry", ICLASS_xt_iclass_entry,
  16046     0,
  16047     Opcode_entry_encode_fns, 0, 0 },
  16048   { "movsp", ICLASS_xt_iclass_movsp,
  16049     0,
  16050     Opcode_movsp_encode_fns, 0, 0 },
  16051   { "rotw", ICLASS_xt_iclass_rotw,
  16052     0,
  16053     Opcode_rotw_encode_fns, 0, 0 },
  16054   { "retw", ICLASS_xt_iclass_retw,
  16055     XTENSA_OPCODE_IS_JUMP,
  16056     Opcode_retw_encode_fns, 0, 0 },
  16057   { "retw.n", ICLASS_xt_iclass_retw,
  16058     XTENSA_OPCODE_IS_JUMP,
  16059     Opcode_retw_n_encode_fns, 0, 0 },
  16060   { "rfwo", ICLASS_xt_iclass_rfwou,
  16061     XTENSA_OPCODE_IS_JUMP,
  16062     Opcode_rfwo_encode_fns, 0, 0 },
  16063   { "rfwu", ICLASS_xt_iclass_rfwou,
  16064     XTENSA_OPCODE_IS_JUMP,
  16065     Opcode_rfwu_encode_fns, 0, 0 },
  16066   { "l32e", ICLASS_xt_iclass_l32e,
  16067     0,
  16068     Opcode_l32e_encode_fns, 1, Opcode_l32e_funcUnit_uses },
  16069   { "s32e", ICLASS_xt_iclass_s32e,
  16070     0,
  16071     Opcode_s32e_encode_fns, 1, Opcode_s32e_funcUnit_uses },
  16072   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
  16073     0,
  16074     Opcode_rsr_windowbase_encode_fns, 0, 0 },
  16075   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
  16076     0,
  16077     Opcode_wsr_windowbase_encode_fns, 0, 0 },
  16078   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
  16079     0,
  16080     Opcode_xsr_windowbase_encode_fns, 0, 0 },
  16081   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
  16082     0,
  16083     Opcode_rsr_windowstart_encode_fns, 0, 0 },
  16084   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
  16085     0,
  16086     Opcode_wsr_windowstart_encode_fns, 0, 0 },
  16087   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
  16088     0,
  16089     Opcode_xsr_windowstart_encode_fns, 0, 0 },
  16090   { "add.n", ICLASS_xt_iclass_add_n,
  16091     0,
  16092     Opcode_add_n_encode_fns, 0, 0 },
  16093   { "addi.n", ICLASS_xt_iclass_addi_n,
  16094     0,
  16095     Opcode_addi_n_encode_fns, 0, 0 },
  16096   { "beqz.n", ICLASS_xt_iclass_bz6,
  16097     XTENSA_OPCODE_IS_BRANCH,
  16098     Opcode_beqz_n_encode_fns, 0, 0 },
  16099   { "bnez.n", ICLASS_xt_iclass_bz6,
  16100     XTENSA_OPCODE_IS_BRANCH,
  16101     Opcode_bnez_n_encode_fns, 0, 0 },
  16102   { "ill.n", ICLASS_xt_iclass_ill_n,
  16103     0,
  16104     Opcode_ill_n_encode_fns, 0, 0 },
  16105   { "l32i.n", ICLASS_xt_iclass_loadi4,
  16106     0,
  16107     Opcode_l32i_n_encode_fns, 1, Opcode_l32i_n_funcUnit_uses },
  16108   { "mov.n", ICLASS_xt_iclass_mov_n,
  16109     0,
  16110     Opcode_mov_n_encode_fns, 0, 0 },
  16111   { "movi.n", ICLASS_xt_iclass_movi_n,
  16112     0,
  16113     Opcode_movi_n_encode_fns, 0, 0 },
  16114   { "nop.n", ICLASS_xt_iclass_nopn,
  16115     0,
  16116     Opcode_nop_n_encode_fns, 0, 0 },
  16117   { "ret.n", ICLASS_xt_iclass_retn,
  16118     XTENSA_OPCODE_IS_JUMP,
  16119     Opcode_ret_n_encode_fns, 0, 0 },
  16120   { "s32i.n", ICLASS_xt_iclass_storei4,
  16121     0,
  16122     Opcode_s32i_n_encode_fns, 1, Opcode_s32i_n_funcUnit_uses },
  16123   { "rur.threadptr", ICLASS_rur_threadptr,
  16124     0,
  16125     Opcode_rur_threadptr_encode_fns, 0, 0 },
  16126   { "wur.threadptr", ICLASS_wur_threadptr,
  16127     0,
  16128     Opcode_wur_threadptr_encode_fns, 0, 0 },
  16129   { "addi", ICLASS_xt_iclass_addi,
  16130     0,
  16131     Opcode_addi_encode_fns, 0, 0 },
  16132   { "addmi", ICLASS_xt_iclass_addmi,
  16133     0,
  16134     Opcode_addmi_encode_fns, 0, 0 },
  16135   { "add", ICLASS_xt_iclass_addsub,
  16136     0,
  16137     Opcode_add_encode_fns, 0, 0 },
  16138   { "addx2", ICLASS_xt_iclass_addsub,
  16139     0,
  16140     Opcode_addx2_encode_fns, 0, 0 },
  16141   { "addx4", ICLASS_xt_iclass_addsub,
  16142     0,
  16143     Opcode_addx4_encode_fns, 0, 0 },
  16144   { "addx8", ICLASS_xt_iclass_addsub,
  16145     0,
  16146     Opcode_addx8_encode_fns, 0, 0 },
  16147   { "sub", ICLASS_xt_iclass_addsub,
  16148     0,
  16149     Opcode_sub_encode_fns, 0, 0 },
  16150   { "subx2", ICLASS_xt_iclass_addsub,
  16151     0,
  16152     Opcode_subx2_encode_fns, 0, 0 },
  16153   { "subx4", ICLASS_xt_iclass_addsub,
  16154     0,
  16155     Opcode_subx4_encode_fns, 0, 0 },
  16156   { "subx8", ICLASS_xt_iclass_addsub,
  16157     0,
  16158     Opcode_subx8_encode_fns, 0, 0 },
  16159   { "and", ICLASS_xt_iclass_bit,
  16160     0,
  16161     Opcode_and_encode_fns, 0, 0 },
  16162   { "or", ICLASS_xt_iclass_bit,
  16163     0,
  16164     Opcode_or_encode_fns, 0, 0 },
  16165   { "xor", ICLASS_xt_iclass_bit,
  16166     0,
  16167     Opcode_xor_encode_fns, 0, 0 },
  16168   { "beqi", ICLASS_xt_iclass_bsi8,
  16169     XTENSA_OPCODE_IS_BRANCH,
  16170     Opcode_beqi_encode_fns, 0, 0 },
  16171   { "bgei", ICLASS_xt_iclass_bsi8,
  16172     XTENSA_OPCODE_IS_BRANCH,
  16173     Opcode_bgei_encode_fns, 0, 0 },
  16174   { "blti", ICLASS_xt_iclass_bsi8,
  16175     XTENSA_OPCODE_IS_BRANCH,
  16176     Opcode_blti_encode_fns, 0, 0 },
  16177   { "bnei", ICLASS_xt_iclass_bsi8,
  16178     XTENSA_OPCODE_IS_BRANCH,
  16179     Opcode_bnei_encode_fns, 0, 0 },
  16180   { "bbci", ICLASS_xt_iclass_bsi8b,
  16181     XTENSA_OPCODE_IS_BRANCH,
  16182     Opcode_bbci_encode_fns, 0, 0 },
  16183   { "bbsi", ICLASS_xt_iclass_bsi8b,
  16184     XTENSA_OPCODE_IS_BRANCH,
  16185     Opcode_bbsi_encode_fns, 0, 0 },
  16186   { "bgeui", ICLASS_xt_iclass_bsi8u,
  16187     XTENSA_OPCODE_IS_BRANCH,
  16188     Opcode_bgeui_encode_fns, 0, 0 },
  16189   { "bltui", ICLASS_xt_iclass_bsi8u,
  16190     XTENSA_OPCODE_IS_BRANCH,
  16191     Opcode_bltui_encode_fns, 0, 0 },
  16192   { "ball", ICLASS_xt_iclass_bst8,
  16193     XTENSA_OPCODE_IS_BRANCH,
  16194     Opcode_ball_encode_fns, 0, 0 },
  16195   { "bany", ICLASS_xt_iclass_bst8,
  16196     XTENSA_OPCODE_IS_BRANCH,
  16197     Opcode_bany_encode_fns, 0, 0 },
  16198   { "bbc", ICLASS_xt_iclass_bst8,
  16199     XTENSA_OPCODE_IS_BRANCH,
  16200     Opcode_bbc_encode_fns, 0, 0 },
  16201   { "bbs", ICLASS_xt_iclass_bst8,
  16202     XTENSA_OPCODE_IS_BRANCH,
  16203     Opcode_bbs_encode_fns, 0, 0 },
  16204   { "beq", ICLASS_xt_iclass_bst8,
  16205     XTENSA_OPCODE_IS_BRANCH,
  16206     Opcode_beq_encode_fns, 0, 0 },
  16207   { "bge", ICLASS_xt_iclass_bst8,
  16208     XTENSA_OPCODE_IS_BRANCH,
  16209     Opcode_bge_encode_fns, 0, 0 },
  16210   { "bgeu", ICLASS_xt_iclass_bst8,
  16211     XTENSA_OPCODE_IS_BRANCH,
  16212     Opcode_bgeu_encode_fns, 0, 0 },
  16213   { "blt", ICLASS_xt_iclass_bst8,
  16214     XTENSA_OPCODE_IS_BRANCH,
  16215     Opcode_blt_encode_fns, 0, 0 },
  16216   { "bltu", ICLASS_xt_iclass_bst8,
  16217     XTENSA_OPCODE_IS_BRANCH,
  16218     Opcode_bltu_encode_fns, 0, 0 },
  16219   { "bnall", ICLASS_xt_iclass_bst8,
  16220     XTENSA_OPCODE_IS_BRANCH,
  16221     Opcode_bnall_encode_fns, 0, 0 },
  16222   { "bne", ICLASS_xt_iclass_bst8,
  16223     XTENSA_OPCODE_IS_BRANCH,
  16224     Opcode_bne_encode_fns, 0, 0 },
  16225   { "bnone", ICLASS_xt_iclass_bst8,
  16226     XTENSA_OPCODE_IS_BRANCH,
  16227     Opcode_bnone_encode_fns, 0, 0 },
  16228   { "beqz", ICLASS_xt_iclass_bsz12,
  16229     XTENSA_OPCODE_IS_BRANCH,
  16230     Opcode_beqz_encode_fns, 0, 0 },
  16231   { "bgez", ICLASS_xt_iclass_bsz12,
  16232     XTENSA_OPCODE_IS_BRANCH,
  16233     Opcode_bgez_encode_fns, 0, 0 },
  16234   { "bltz", ICLASS_xt_iclass_bsz12,
  16235     XTENSA_OPCODE_IS_BRANCH,
  16236     Opcode_bltz_encode_fns, 0, 0 },
  16237   { "bnez", ICLASS_xt_iclass_bsz12,
  16238     XTENSA_OPCODE_IS_BRANCH,
  16239     Opcode_bnez_encode_fns, 0, 0 },
  16240   { "call0", ICLASS_xt_iclass_call0,
  16241     XTENSA_OPCODE_IS_CALL,
  16242     Opcode_call0_encode_fns, 0, 0 },
  16243   { "callx0", ICLASS_xt_iclass_callx0,
  16244     XTENSA_OPCODE_IS_CALL,
  16245     Opcode_callx0_encode_fns, 0, 0 },
  16246   { "extui", ICLASS_xt_iclass_exti,
  16247     0,
  16248     Opcode_extui_encode_fns, 0, 0 },
  16249   { "ill", ICLASS_xt_iclass_ill,
  16250     0,
  16251     Opcode_ill_encode_fns, 0, 0 },
  16252   { "j", ICLASS_xt_iclass_jump,
  16253     XTENSA_OPCODE_IS_JUMP,
  16254     Opcode_j_encode_fns, 0, 0 },
  16255   { "jx", ICLASS_xt_iclass_jumpx,
  16256     XTENSA_OPCODE_IS_JUMP,
  16257     Opcode_jx_encode_fns, 0, 0 },
  16258   { "l16ui", ICLASS_xt_iclass_l16ui,
  16259     0,
  16260     Opcode_l16ui_encode_fns, 1, Opcode_l16ui_funcUnit_uses },
  16261   { "l16si", ICLASS_xt_iclass_l16si,
  16262     0,
  16263     Opcode_l16si_encode_fns, 1, Opcode_l16si_funcUnit_uses },
  16264   { "l32i", ICLASS_xt_iclass_l32i,
  16265     0,
  16266     Opcode_l32i_encode_fns, 1, Opcode_l32i_funcUnit_uses },
  16267   { "l32r", ICLASS_xt_iclass_l32r,
  16268     0,
  16269     Opcode_l32r_encode_fns, 1, Opcode_l32r_funcUnit_uses },
  16270   { "l8ui", ICLASS_xt_iclass_l8i,
  16271     0,
  16272     Opcode_l8ui_encode_fns, 1, Opcode_l8ui_funcUnit_uses },
  16273   { "loop", ICLASS_xt_iclass_loop,
  16274     XTENSA_OPCODE_IS_LOOP,
  16275     Opcode_loop_encode_fns, 0, 0 },
  16276   { "loopgtz", ICLASS_xt_iclass_loopz,
  16277     XTENSA_OPCODE_IS_LOOP,
  16278     Opcode_loopgtz_encode_fns, 0, 0 },
  16279   { "loopnez", ICLASS_xt_iclass_loopz,
  16280     XTENSA_OPCODE_IS_LOOP,
  16281     Opcode_loopnez_encode_fns, 0, 0 },
  16282   { "movi", ICLASS_xt_iclass_movi,
  16283     0,
  16284     Opcode_movi_encode_fns, 0, 0 },
  16285   { "moveqz", ICLASS_xt_iclass_movz,
  16286     0,
  16287     Opcode_moveqz_encode_fns, 0, 0 },
  16288   { "movgez", ICLASS_xt_iclass_movz,
  16289     0,
  16290     Opcode_movgez_encode_fns, 0, 0 },
  16291   { "movltz", ICLASS_xt_iclass_movz,
  16292     0,
  16293     Opcode_movltz_encode_fns, 0, 0 },
  16294   { "movnez", ICLASS_xt_iclass_movz,
  16295     0,
  16296     Opcode_movnez_encode_fns, 0, 0 },
  16297   { "abs", ICLASS_xt_iclass_neg,
  16298     0,
  16299     Opcode_abs_encode_fns, 0, 0 },
  16300   { "neg", ICLASS_xt_iclass_neg,
  16301     0,
  16302     Opcode_neg_encode_fns, 0, 0 },
  16303   { "nop", ICLASS_xt_iclass_nop,
  16304     0,
  16305     Opcode_nop_encode_fns, 0, 0 },
  16306   { "ret", ICLASS_xt_iclass_return,
  16307     XTENSA_OPCODE_IS_JUMP,
  16308     Opcode_ret_encode_fns, 0, 0 },
  16309   { "simcall", ICLASS_xt_iclass_simcall,
  16310     0,
  16311     Opcode_simcall_encode_fns, 0, 0 },
  16312   { "s16i", ICLASS_xt_iclass_s16i,
  16313     0,
  16314     Opcode_s16i_encode_fns, 1, Opcode_s16i_funcUnit_uses },
  16315   { "s32i", ICLASS_xt_iclass_s32i,
  16316     0,
  16317     Opcode_s32i_encode_fns, 1, Opcode_s32i_funcUnit_uses },
  16318   { "s32nb", ICLASS_xt_iclass_s32nb,
  16319     0,
  16320     Opcode_s32nb_encode_fns, 1, Opcode_s32nb_funcUnit_uses },
  16321   { "s8i", ICLASS_xt_iclass_s8i,
  16322     0,
  16323     Opcode_s8i_encode_fns, 1, Opcode_s8i_funcUnit_uses },
  16324   { "ssa8b", ICLASS_xt_iclass_sar,
  16325     0,
  16326     Opcode_ssa8b_encode_fns, 0, 0 },
  16327   { "ssa8l", ICLASS_xt_iclass_sar,
  16328     0,
  16329     Opcode_ssa8l_encode_fns, 0, 0 },
  16330   { "ssl", ICLASS_xt_iclass_sar,
  16331     0,
  16332     Opcode_ssl_encode_fns, 0, 0 },
  16333   { "ssr", ICLASS_xt_iclass_sar,
  16334     0,
  16335     Opcode_ssr_encode_fns, 0, 0 },
  16336   { "ssai", ICLASS_xt_iclass_sari,
  16337     0,
  16338     Opcode_ssai_encode_fns, 0, 0 },
  16339   { "sll", ICLASS_xt_iclass_shifts,
  16340     0,
  16341     Opcode_sll_encode_fns, 0, 0 },
  16342   { "src", ICLASS_xt_iclass_shiftst,
  16343     0,
  16344     Opcode_src_encode_fns, 0, 0 },
  16345   { "sra", ICLASS_xt_iclass_shiftt,
  16346     0,
  16347     Opcode_sra_encode_fns, 0, 0 },
  16348   { "srl", ICLASS_xt_iclass_shiftt,
  16349     0,
  16350     Opcode_srl_encode_fns, 0, 0 },
  16351   { "slli", ICLASS_xt_iclass_slli,
  16352     0,
  16353     Opcode_slli_encode_fns, 0, 0 },
  16354   { "srai", ICLASS_xt_iclass_srai,
  16355     0,
  16356     Opcode_srai_encode_fns, 0, 0 },
  16357   { "srli", ICLASS_xt_iclass_srli,
  16358     0,
  16359     Opcode_srli_encode_fns, 0, 0 },
  16360   { "memw", ICLASS_xt_iclass_memw,
  16361     0,
  16362     Opcode_memw_encode_fns, 0, 0 },
  16363   { "extw", ICLASS_xt_iclass_extw,
  16364     0,
  16365     Opcode_extw_encode_fns, 0, 0 },
  16366   { "isync", ICLASS_xt_iclass_isync,
  16367     0,
  16368     Opcode_isync_encode_fns, 0, 0 },
  16369   { "dsync", ICLASS_xt_iclass_sync,
  16370     0,
  16371     Opcode_dsync_encode_fns, 0, 0 },
  16372   { "esync", ICLASS_xt_iclass_sync,
  16373     0,
  16374     Opcode_esync_encode_fns, 0, 0 },
  16375   { "rsync", ICLASS_xt_iclass_sync,
  16376     0,
  16377     Opcode_rsync_encode_fns, 0, 0 },
  16378   { "rsil", ICLASS_xt_iclass_rsil,
  16379     0,
  16380     Opcode_rsil_encode_fns, 0, 0 },
  16381   { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
  16382     0,
  16383     Opcode_rsr_lend_encode_fns, 0, 0 },
  16384   { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
  16385     0,
  16386     Opcode_wsr_lend_encode_fns, 0, 0 },
  16387   { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
  16388     0,
  16389     Opcode_xsr_lend_encode_fns, 0, 0 },
  16390   { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
  16391     0,
  16392     Opcode_rsr_lcount_encode_fns, 0, 0 },
  16393   { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
  16394     0,
  16395     Opcode_wsr_lcount_encode_fns, 0, 0 },
  16396   { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
  16397     0,
  16398     Opcode_xsr_lcount_encode_fns, 0, 0 },
  16399   { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
  16400     0,
  16401     Opcode_rsr_lbeg_encode_fns, 0, 0 },
  16402   { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
  16403     0,
  16404     Opcode_wsr_lbeg_encode_fns, 0, 0 },
  16405   { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
  16406     0,
  16407     Opcode_xsr_lbeg_encode_fns, 0, 0 },
  16408   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
  16409     0,
  16410     Opcode_rsr_sar_encode_fns, 0, 0 },
  16411   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
  16412     0,
  16413     Opcode_wsr_sar_encode_fns, 0, 0 },
  16414   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
  16415     0,
  16416     Opcode_xsr_sar_encode_fns, 0, 0 },
  16417   { "rsr.memctl", ICLASS_xt_iclass_rsr_memctl,
  16418     0,
  16419     Opcode_rsr_memctl_encode_fns, 0, 0 },
  16420   { "wsr.memctl", ICLASS_xt_iclass_wsr_memctl,
  16421     0,
  16422     Opcode_wsr_memctl_encode_fns, 0, 0 },
  16423   { "xsr.memctl", ICLASS_xt_iclass_xsr_memctl,
  16424     0,
  16425     Opcode_xsr_memctl_encode_fns, 0, 0 },
  16426   { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
  16427     0,
  16428     Opcode_rsr_configid0_encode_fns, 0, 0 },
  16429   { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
  16430     0,
  16431     Opcode_wsr_configid0_encode_fns, 0, 0 },
  16432   { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
  16433     0,
  16434     Opcode_rsr_configid1_encode_fns, 0, 0 },
  16435   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
  16436     0,
  16437     Opcode_rsr_ps_encode_fns, 0, 0 },
  16438   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
  16439     0,
  16440     Opcode_wsr_ps_encode_fns, 0, 0 },
  16441   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
  16442     0,
  16443     Opcode_xsr_ps_encode_fns, 0, 0 },
  16444   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
  16445     0,
  16446     Opcode_rsr_epc1_encode_fns, 0, 0 },
  16447   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
  16448     0,
  16449     Opcode_wsr_epc1_encode_fns, 0, 0 },
  16450   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
  16451     0,
  16452     Opcode_xsr_epc1_encode_fns, 0, 0 },
  16453   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
  16454     0,
  16455     Opcode_rsr_excsave1_encode_fns, 0, 0 },
  16456   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
  16457     0,
  16458     Opcode_wsr_excsave1_encode_fns, 0, 0 },
  16459   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
  16460     0,
  16461     Opcode_xsr_excsave1_encode_fns, 0, 0 },
  16462   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
  16463     0,
  16464     Opcode_rsr_epc2_encode_fns, 0, 0 },
  16465   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
  16466     0,
  16467     Opcode_wsr_epc2_encode_fns, 0, 0 },
  16468   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
  16469     0,
  16470     Opcode_xsr_epc2_encode_fns, 0, 0 },
  16471   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
  16472     0,
  16473     Opcode_rsr_excsave2_encode_fns, 0, 0 },
  16474   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
  16475     0,
  16476     Opcode_wsr_excsave2_encode_fns, 0, 0 },
  16477   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
  16478     0,
  16479     Opcode_xsr_excsave2_encode_fns, 0, 0 },
  16480   { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
  16481     0,
  16482     Opcode_rsr_epc3_encode_fns, 0, 0 },
  16483   { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
  16484     0,
  16485     Opcode_wsr_epc3_encode_fns, 0, 0 },
  16486   { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
  16487     0,
  16488     Opcode_xsr_epc3_encode_fns, 0, 0 },
  16489   { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
  16490     0,
  16491     Opcode_rsr_excsave3_encode_fns, 0, 0 },
  16492   { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
  16493     0,
  16494     Opcode_wsr_excsave3_encode_fns, 0, 0 },
  16495   { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
  16496     0,
  16497     Opcode_xsr_excsave3_encode_fns, 0, 0 },
  16498   { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
  16499     0,
  16500     Opcode_rsr_epc4_encode_fns, 0, 0 },
  16501   { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
  16502     0,
  16503     Opcode_wsr_epc4_encode_fns, 0, 0 },
  16504   { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
  16505     0,
  16506     Opcode_xsr_epc4_encode_fns, 0, 0 },
  16507   { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
  16508     0,
  16509     Opcode_rsr_excsave4_encode_fns, 0, 0 },
  16510   { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
  16511     0,
  16512     Opcode_wsr_excsave4_encode_fns, 0, 0 },
  16513   { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
  16514     0,
  16515     Opcode_xsr_excsave4_encode_fns, 0, 0 },
  16516   { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
  16517     0,
  16518     Opcode_rsr_epc5_encode_fns, 0, 0 },
  16519   { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
  16520     0,
  16521     Opcode_wsr_epc5_encode_fns, 0, 0 },
  16522   { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
  16523     0,
  16524     Opcode_xsr_epc5_encode_fns, 0, 0 },
  16525   { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
  16526     0,
  16527     Opcode_rsr_excsave5_encode_fns, 0, 0 },
  16528   { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
  16529     0,
  16530     Opcode_wsr_excsave5_encode_fns, 0, 0 },
  16531   { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
  16532     0,
  16533     Opcode_xsr_excsave5_encode_fns, 0, 0 },
  16534   { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
  16535     0,
  16536     Opcode_rsr_epc6_encode_fns, 0, 0 },
  16537   { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
  16538     0,
  16539     Opcode_wsr_epc6_encode_fns, 0, 0 },
  16540   { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
  16541     0,
  16542     Opcode_xsr_epc6_encode_fns, 0, 0 },
  16543   { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
  16544     0,
  16545     Opcode_rsr_excsave6_encode_fns, 0, 0 },
  16546   { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
  16547     0,
  16548     Opcode_wsr_excsave6_encode_fns, 0, 0 },
  16549   { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
  16550     0,
  16551     Opcode_xsr_excsave6_encode_fns, 0, 0 },
  16552   { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
  16553     0,
  16554     Opcode_rsr_epc7_encode_fns, 0, 0 },
  16555   { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
  16556     0,
  16557     Opcode_wsr_epc7_encode_fns, 0, 0 },
  16558   { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
  16559     0,
  16560     Opcode_xsr_epc7_encode_fns, 0, 0 },
  16561   { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
  16562     0,
  16563     Opcode_rsr_excsave7_encode_fns, 0, 0 },
  16564   { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
  16565     0,
  16566     Opcode_wsr_excsave7_encode_fns, 0, 0 },
  16567   { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
  16568     0,
  16569     Opcode_xsr_excsave7_encode_fns, 0, 0 },
  16570   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
  16571     0,
  16572     Opcode_rsr_eps2_encode_fns, 0, 0 },
  16573   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
  16574     0,
  16575     Opcode_wsr_eps2_encode_fns, 0, 0 },
  16576   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
  16577     0,
  16578     Opcode_xsr_eps2_encode_fns, 0, 0 },
  16579   { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
  16580     0,
  16581     Opcode_rsr_eps3_encode_fns, 0, 0 },
  16582   { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
  16583     0,
  16584     Opcode_wsr_eps3_encode_fns, 0, 0 },
  16585   { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
  16586     0,
  16587     Opcode_xsr_eps3_encode_fns, 0, 0 },
  16588   { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
  16589     0,
  16590     Opcode_rsr_eps4_encode_fns, 0, 0 },
  16591   { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
  16592     0,
  16593     Opcode_wsr_eps4_encode_fns, 0, 0 },
  16594   { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
  16595     0,
  16596     Opcode_xsr_eps4_encode_fns, 0, 0 },
  16597   { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
  16598     0,
  16599     Opcode_rsr_eps5_encode_fns, 0, 0 },
  16600   { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
  16601     0,
  16602     Opcode_wsr_eps5_encode_fns, 0, 0 },
  16603   { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
  16604     0,
  16605     Opcode_xsr_eps5_encode_fns, 0, 0 },
  16606   { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
  16607     0,
  16608     Opcode_rsr_eps6_encode_fns, 0, 0 },
  16609   { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
  16610     0,
  16611     Opcode_wsr_eps6_encode_fns, 0, 0 },
  16612   { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
  16613     0,
  16614     Opcode_xsr_eps6_encode_fns, 0, 0 },
  16615   { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
  16616     0,
  16617     Opcode_rsr_eps7_encode_fns, 0, 0 },
  16618   { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
  16619     0,
  16620     Opcode_wsr_eps7_encode_fns, 0, 0 },
  16621   { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
  16622     0,
  16623     Opcode_xsr_eps7_encode_fns, 0, 0 },
  16624   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
  16625     0,
  16626     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
  16627   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
  16628     0,
  16629     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
  16630   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
  16631     0,
  16632     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
  16633   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
  16634     0,
  16635     Opcode_rsr_depc_encode_fns, 0, 0 },
  16636   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
  16637     0,
  16638     Opcode_wsr_depc_encode_fns, 0, 0 },
  16639   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
  16640     0,
  16641     Opcode_xsr_depc_encode_fns, 0, 0 },
  16642   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
  16643     0,
  16644     Opcode_rsr_exccause_encode_fns, 0, 0 },
  16645   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
  16646     0,
  16647     Opcode_wsr_exccause_encode_fns, 0, 0 },
  16648   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
  16649     0,
  16650     Opcode_xsr_exccause_encode_fns, 0, 0 },
  16651   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
  16652     0,
  16653     Opcode_rsr_misc0_encode_fns, 0, 0 },
  16654   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
  16655     0,
  16656     Opcode_wsr_misc0_encode_fns, 0, 0 },
  16657   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
  16658     0,
  16659     Opcode_xsr_misc0_encode_fns, 0, 0 },
  16660   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
  16661     0,
  16662     Opcode_rsr_misc1_encode_fns, 0, 0 },
  16663   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
  16664     0,
  16665     Opcode_wsr_misc1_encode_fns, 0, 0 },
  16666   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
  16667     0,
  16668     Opcode_xsr_misc1_encode_fns, 0, 0 },
  16669   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
  16670     0,
  16671     Opcode_rsr_prid_encode_fns, 0, 0 },
  16672   { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
  16673     0,
  16674     Opcode_rsr_vecbase_encode_fns, 0, 0 },
  16675   { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
  16676     0,
  16677     Opcode_wsr_vecbase_encode_fns, 0, 0 },
  16678   { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
  16679     0,
  16680     Opcode_xsr_vecbase_encode_fns, 0, 0 },
  16681   { "salt", ICLASS_xt_iclass_salt,
  16682     0,
  16683     Opcode_salt_encode_fns, 0, 0 },
  16684   { "saltu", ICLASS_xt_iclass_salt,
  16685     0,
  16686     Opcode_saltu_encode_fns, 0, 0 },
  16687   { "mul16s", ICLASS_xt_mul16,
  16688     0,
  16689     Opcode_mul16s_encode_fns, 0, 0 },
  16690   { "mul16u", ICLASS_xt_mul16,
  16691     0,
  16692     Opcode_mul16u_encode_fns, 0, 0 },
  16693   { "mull", ICLASS_xt_mul32,
  16694     0,
  16695     Opcode_mull_encode_fns, 0, 0 },
  16696   { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
  16697     0,
  16698     Opcode_mul_aa_hh_encode_fns, 0, 0 },
  16699   { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
  16700     0,
  16701     Opcode_mul_aa_hl_encode_fns, 0, 0 },
  16702   { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
  16703     0,
  16704     Opcode_mul_aa_lh_encode_fns, 0, 0 },
  16705   { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
  16706     0,
  16707     Opcode_mul_aa_ll_encode_fns, 0, 0 },
  16708   { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
  16709     0,
  16710     Opcode_umul_aa_hh_encode_fns, 0, 0 },
  16711   { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
  16712     0,
  16713     Opcode_umul_aa_hl_encode_fns, 0, 0 },
  16714   { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
  16715     0,
  16716     Opcode_umul_aa_lh_encode_fns, 0, 0 },
  16717   { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
  16718     0,
  16719     Opcode_umul_aa_ll_encode_fns, 0, 0 },
  16720   { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
  16721     0,
  16722     Opcode_mul_ad_hh_encode_fns, 0, 0 },
  16723   { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
  16724     0,
  16725     Opcode_mul_ad_hl_encode_fns, 0, 0 },
  16726   { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
  16727     0,
  16728     Opcode_mul_ad_lh_encode_fns, 0, 0 },
  16729   { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
  16730     0,
  16731     Opcode_mul_ad_ll_encode_fns, 0, 0 },
  16732   { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
  16733     0,
  16734     Opcode_mul_da_hh_encode_fns, 0, 0 },
  16735   { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
  16736     0,
  16737     Opcode_mul_da_hl_encode_fns, 0, 0 },
  16738   { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
  16739     0,
  16740     Opcode_mul_da_lh_encode_fns, 0, 0 },
  16741   { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
  16742     0,
  16743     Opcode_mul_da_ll_encode_fns, 0, 0 },
  16744   { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
  16745     0,
  16746     Opcode_mul_dd_hh_encode_fns, 0, 0 },
  16747   { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
  16748     0,
  16749     Opcode_mul_dd_hl_encode_fns, 0, 0 },
  16750   { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
  16751     0,
  16752     Opcode_mul_dd_lh_encode_fns, 0, 0 },
  16753   { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
  16754     0,
  16755     Opcode_mul_dd_ll_encode_fns, 0, 0 },
  16756   { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
  16757     0,
  16758     Opcode_mula_aa_hh_encode_fns, 0, 0 },
  16759   { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
  16760     0,
  16761     Opcode_mula_aa_hl_encode_fns, 0, 0 },
  16762   { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
  16763     0,
  16764     Opcode_mula_aa_lh_encode_fns, 0, 0 },
  16765   { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
  16766     0,
  16767     Opcode_mula_aa_ll_encode_fns, 0, 0 },
  16768   { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
  16769     0,
  16770     Opcode_muls_aa_hh_encode_fns, 0, 0 },
  16771   { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
  16772     0,
  16773     Opcode_muls_aa_hl_encode_fns, 0, 0 },
  16774   { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
  16775     0,
  16776     Opcode_muls_aa_lh_encode_fns, 0, 0 },
  16777   { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
  16778     0,
  16779     Opcode_muls_aa_ll_encode_fns, 0, 0 },
  16780   { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
  16781     0,
  16782     Opcode_mula_ad_hh_encode_fns, 0, 0 },
  16783   { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
  16784     0,
  16785     Opcode_mula_ad_hl_encode_fns, 0, 0 },
  16786   { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
  16787     0,
  16788     Opcode_mula_ad_lh_encode_fns, 0, 0 },
  16789   { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
  16790     0,
  16791     Opcode_mula_ad_ll_encode_fns, 0, 0 },
  16792   { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
  16793     0,
  16794     Opcode_muls_ad_hh_encode_fns, 0, 0 },
  16795   { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
  16796     0,
  16797     Opcode_muls_ad_hl_encode_fns, 0, 0 },
  16798   { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
  16799     0,
  16800     Opcode_muls_ad_lh_encode_fns, 0, 0 },
  16801   { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
  16802     0,
  16803     Opcode_muls_ad_ll_encode_fns, 0, 0 },
  16804   { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
  16805     0,
  16806     Opcode_mula_da_hh_encode_fns, 0, 0 },
  16807   { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
  16808     0,
  16809     Opcode_mula_da_hl_encode_fns, 0, 0 },
  16810   { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
  16811     0,
  16812     Opcode_mula_da_lh_encode_fns, 0, 0 },
  16813   { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
  16814     0,
  16815     Opcode_mula_da_ll_encode_fns, 0, 0 },
  16816   { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
  16817     0,
  16818     Opcode_muls_da_hh_encode_fns, 0, 0 },
  16819   { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
  16820     0,
  16821     Opcode_muls_da_hl_encode_fns, 0, 0 },
  16822   { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
  16823     0,
  16824     Opcode_muls_da_lh_encode_fns, 0, 0 },
  16825   { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
  16826     0,
  16827     Opcode_muls_da_ll_encode_fns, 0, 0 },
  16828   { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
  16829     0,
  16830     Opcode_mula_dd_hh_encode_fns, 0, 0 },
  16831   { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
  16832     0,
  16833     Opcode_mula_dd_hl_encode_fns, 0, 0 },
  16834   { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
  16835     0,
  16836     Opcode_mula_dd_lh_encode_fns, 0, 0 },
  16837   { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
  16838     0,
  16839     Opcode_mula_dd_ll_encode_fns, 0, 0 },
  16840   { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
  16841     0,
  16842     Opcode_muls_dd_hh_encode_fns, 0, 0 },
  16843   { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
  16844     0,
  16845     Opcode_muls_dd_hl_encode_fns, 0, 0 },
  16846   { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
  16847     0,
  16848     Opcode_muls_dd_lh_encode_fns, 0, 0 },
  16849   { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
  16850     0,
  16851     Opcode_muls_dd_ll_encode_fns, 0, 0 },
  16852   { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
  16853     0,
  16854     Opcode_mula_da_hh_lddec_encode_fns, 1, Opcode_mula_da_hh_lddec_funcUnit_uses },
  16855   { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
  16856     0,
  16857     Opcode_mula_da_hh_ldinc_encode_fns, 1, Opcode_mula_da_hh_ldinc_funcUnit_uses },
  16858   { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
  16859     0,
  16860     Opcode_mula_da_hl_lddec_encode_fns, 1, Opcode_mula_da_hl_lddec_funcUnit_uses },
  16861   { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
  16862     0,
  16863     Opcode_mula_da_hl_ldinc_encode_fns, 1, Opcode_mula_da_hl_ldinc_funcUnit_uses },
  16864   { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
  16865     0,
  16866     Opcode_mula_da_lh_lddec_encode_fns, 1, Opcode_mula_da_lh_lddec_funcUnit_uses },
  16867   { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
  16868     0,
  16869     Opcode_mula_da_lh_ldinc_encode_fns, 1, Opcode_mula_da_lh_ldinc_funcUnit_uses },
  16870   { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
  16871     0,
  16872     Opcode_mula_da_ll_lddec_encode_fns, 1, Opcode_mula_da_ll_lddec_funcUnit_uses },
  16873   { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
  16874     0,
  16875     Opcode_mula_da_ll_ldinc_encode_fns, 1, Opcode_mula_da_ll_ldinc_funcUnit_uses },
  16876   { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
  16877     0,
  16878     Opcode_mula_dd_hh_lddec_encode_fns, 1, Opcode_mula_dd_hh_lddec_funcUnit_uses },
  16879   { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
  16880     0,
  16881     Opcode_mula_dd_hh_ldinc_encode_fns, 1, Opcode_mula_dd_hh_ldinc_funcUnit_uses },
  16882   { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
  16883     0,
  16884     Opcode_mula_dd_hl_lddec_encode_fns, 1, Opcode_mula_dd_hl_lddec_funcUnit_uses },
  16885   { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
  16886     0,
  16887     Opcode_mula_dd_hl_ldinc_encode_fns, 1, Opcode_mula_dd_hl_ldinc_funcUnit_uses },
  16888   { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
  16889     0,
  16890     Opcode_mula_dd_lh_lddec_encode_fns, 1, Opcode_mula_dd_lh_lddec_funcUnit_uses },
  16891   { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
  16892     0,
  16893     Opcode_mula_dd_lh_ldinc_encode_fns, 1, Opcode_mula_dd_lh_ldinc_funcUnit_uses },
  16894   { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
  16895     0,
  16896     Opcode_mula_dd_ll_lddec_encode_fns, 1, Opcode_mula_dd_ll_lddec_funcUnit_uses },
  16897   { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
  16898     0,
  16899     Opcode_mula_dd_ll_ldinc_encode_fns, 1, Opcode_mula_dd_ll_ldinc_funcUnit_uses },
  16900   { "lddec", ICLASS_xt_iclass_mac16_l,
  16901     0,
  16902     Opcode_lddec_encode_fns, 1, Opcode_lddec_funcUnit_uses },
  16903   { "ldinc", ICLASS_xt_iclass_mac16_l,
  16904     0,
  16905     Opcode_ldinc_encode_fns, 1, Opcode_ldinc_funcUnit_uses },
  16906   { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
  16907     0,
  16908     Opcode_rsr_m0_encode_fns, 0, 0 },
  16909   { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
  16910     0,
  16911     Opcode_wsr_m0_encode_fns, 0, 0 },
  16912   { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
  16913     0,
  16914     Opcode_xsr_m0_encode_fns, 0, 0 },
  16915   { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
  16916     0,
  16917     Opcode_rsr_m1_encode_fns, 0, 0 },
  16918   { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
  16919     0,
  16920     Opcode_wsr_m1_encode_fns, 0, 0 },
  16921   { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
  16922     0,
  16923     Opcode_xsr_m1_encode_fns, 0, 0 },
  16924   { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
  16925     0,
  16926     Opcode_rsr_m2_encode_fns, 0, 0 },
  16927   { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
  16928     0,
  16929     Opcode_wsr_m2_encode_fns, 0, 0 },
  16930   { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
  16931     0,
  16932     Opcode_xsr_m2_encode_fns, 0, 0 },
  16933   { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
  16934     0,
  16935     Opcode_rsr_m3_encode_fns, 0, 0 },
  16936   { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
  16937     0,
  16938     Opcode_wsr_m3_encode_fns, 0, 0 },
  16939   { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
  16940     0,
  16941     Opcode_xsr_m3_encode_fns, 0, 0 },
  16942   { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
  16943     0,
  16944     Opcode_rsr_acclo_encode_fns, 0, 0 },
  16945   { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
  16946     0,
  16947     Opcode_wsr_acclo_encode_fns, 0, 0 },
  16948   { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
  16949     0,
  16950     Opcode_xsr_acclo_encode_fns, 0, 0 },
  16951   { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
  16952     0,
  16953     Opcode_rsr_acchi_encode_fns, 0, 0 },
  16954   { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
  16955     0,
  16956     Opcode_wsr_acchi_encode_fns, 0, 0 },
  16957   { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
  16958     0,
  16959     Opcode_xsr_acchi_encode_fns, 0, 0 },
  16960   { "rfi", ICLASS_xt_iclass_rfi,
  16961     XTENSA_OPCODE_IS_JUMP,
  16962     Opcode_rfi_encode_fns, 0, 0 },
  16963   { "waiti", ICLASS_xt_iclass_wait,
  16964     0,
  16965     Opcode_waiti_encode_fns, 0, 0 },
  16966   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
  16967     0,
  16968     Opcode_rsr_interrupt_encode_fns, 0, 0 },
  16969   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
  16970     0,
  16971     Opcode_wsr_intset_encode_fns, 0, 0 },
  16972   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
  16973     0,
  16974     Opcode_wsr_intclear_encode_fns, 0, 0 },
  16975   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
  16976     0,
  16977     Opcode_rsr_intenable_encode_fns, 0, 0 },
  16978   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
  16979     0,
  16980     Opcode_wsr_intenable_encode_fns, 0, 0 },
  16981   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
  16982     0,
  16983     Opcode_xsr_intenable_encode_fns, 0, 0 },
  16984   { "break", ICLASS_xt_iclass_break,
  16985     0,
  16986     Opcode_break_encode_fns, 0, 0 },
  16987   { "break.n", ICLASS_xt_iclass_break_n,
  16988     0,
  16989     Opcode_break_n_encode_fns, 0, 0 },
  16990   { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
  16991     0,
  16992     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
  16993   { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
  16994     0,
  16995     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
  16996   { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
  16997     0,
  16998     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
  16999   { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
  17000     0,
  17001     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
  17002   { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
  17003     0,
  17004     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
  17005   { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
  17006     0,
  17007     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
  17008   { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
  17009     0,
  17010     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
  17011   { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
  17012     0,
  17013     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
  17014   { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
  17015     0,
  17016     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
  17017   { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
  17018     0,
  17019     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
  17020   { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
  17021     0,
  17022     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
  17023   { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
  17024     0,
  17025     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
  17026   { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
  17027     0,
  17028     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
  17029   { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
  17030     0,
  17031     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
  17032   { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
  17033     0,
  17034     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
  17035   { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
  17036     0,
  17037     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
  17038   { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
  17039     0,
  17040     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
  17041   { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
  17042     0,
  17043     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
  17044   { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
  17045     0,
  17046     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
  17047   { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
  17048     0,
  17049     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
  17050   { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
  17051     0,
  17052     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
  17053   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
  17054     0,
  17055     Opcode_rsr_debugcause_encode_fns, 0, 0 },
  17056   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
  17057     0,
  17058     Opcode_wsr_debugcause_encode_fns, 0, 0 },
  17059   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
  17060     0,
  17061     Opcode_xsr_debugcause_encode_fns, 0, 0 },
  17062   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
  17063     0,
  17064     Opcode_rsr_icount_encode_fns, 0, 0 },
  17065   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
  17066     0,
  17067     Opcode_wsr_icount_encode_fns, 0, 0 },
  17068   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
  17069     0,
  17070     Opcode_xsr_icount_encode_fns, 0, 0 },
  17071   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
  17072     0,
  17073     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
  17074   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
  17075     0,
  17076     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
  17077   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
  17078     0,
  17079     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
  17080   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
  17081     0,
  17082     Opcode_rsr_ddr_encode_fns, 0, 0 },
  17083   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
  17084     0,
  17085     Opcode_wsr_ddr_encode_fns, 0, 0 },
  17086   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
  17087     0,
  17088     Opcode_xsr_ddr_encode_fns, 0, 0 },
  17089   { "lddr32.p", ICLASS_xt_iclass_lddr32_p,
  17090     0,
  17091     Opcode_lddr32_p_encode_fns, 1, Opcode_lddr32_p_funcUnit_uses },
  17092   { "sddr32.p", ICLASS_xt_iclass_sddr32_p,
  17093     0,
  17094     Opcode_sddr32_p_encode_fns, 1, Opcode_sddr32_p_funcUnit_uses },
  17095   { "rfdo", ICLASS_xt_iclass_rfdo,
  17096     XTENSA_OPCODE_IS_JUMP,
  17097     Opcode_rfdo_encode_fns, 0, 0 },
  17098   { "rfdd", ICLASS_xt_iclass_rfdd,
  17099     XTENSA_OPCODE_IS_JUMP,
  17100     Opcode_rfdd_encode_fns, 0, 0 },
  17101   { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
  17102     0,
  17103     Opcode_wsr_mmid_encode_fns, 0, 0 },
  17104   { "andb", ICLASS_xt_iclass_bbool1,
  17105     0,
  17106     Opcode_andb_encode_fns, 0, 0 },
  17107   { "andbc", ICLASS_xt_iclass_bbool1,
  17108     0,
  17109     Opcode_andbc_encode_fns, 0, 0 },
  17110   { "orb", ICLASS_xt_iclass_bbool1,
  17111     0,
  17112     Opcode_orb_encode_fns, 0, 0 },
  17113   { "orbc", ICLASS_xt_iclass_bbool1,
  17114     0,
  17115     Opcode_orbc_encode_fns, 0, 0 },
  17116   { "xorb", ICLASS_xt_iclass_bbool1,
  17117     0,
  17118     Opcode_xorb_encode_fns, 0, 0 },
  17119   { "all4", ICLASS_xt_iclass_bbool4,
  17120     0,
  17121     Opcode_all4_encode_fns, 0, 0 },
  17122   { "any4", ICLASS_xt_iclass_bbool4,
  17123     0,
  17124     Opcode_any4_encode_fns, 0, 0 },
  17125   { "all8", ICLASS_xt_iclass_bbool8,
  17126     0,
  17127     Opcode_all8_encode_fns, 0, 0 },
  17128   { "any8", ICLASS_xt_iclass_bbool8,
  17129     0,
  17130     Opcode_any8_encode_fns, 0, 0 },
  17131   { "bf", ICLASS_xt_iclass_bbranch,
  17132     XTENSA_OPCODE_IS_BRANCH,
  17133     Opcode_bf_encode_fns, 0, 0 },
  17134   { "bt", ICLASS_xt_iclass_bbranch,
  17135     XTENSA_OPCODE_IS_BRANCH,
  17136     Opcode_bt_encode_fns, 0, 0 },
  17137   { "movf", ICLASS_xt_iclass_bmove,
  17138     0,
  17139     Opcode_movf_encode_fns, 0, 0 },
  17140   { "movt", ICLASS_xt_iclass_bmove,
  17141     0,
  17142     Opcode_movt_encode_fns, 0, 0 },
  17143   { "rsr.br", ICLASS_xt_iclass_RSR_BR,
  17144     0,
  17145     Opcode_rsr_br_encode_fns, 0, 0 },
  17146   { "wsr.br", ICLASS_xt_iclass_WSR_BR,
  17147     0,
  17148     Opcode_wsr_br_encode_fns, 0, 0 },
  17149   { "xsr.br", ICLASS_xt_iclass_XSR_BR,
  17150     0,
  17151     Opcode_xsr_br_encode_fns, 0, 0 },
  17152   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
  17153     0,
  17154     Opcode_rsr_ccount_encode_fns, 0, 0 },
  17155   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
  17156     0,
  17157     Opcode_wsr_ccount_encode_fns, 0, 0 },
  17158   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
  17159     0,
  17160     Opcode_xsr_ccount_encode_fns, 0, 0 },
  17161   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
  17162     0,
  17163     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
  17164   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
  17165     0,
  17166     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
  17167   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
  17168     0,
  17169     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
  17170   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
  17171     0,
  17172     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
  17173   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
  17174     0,
  17175     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
  17176   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
  17177     0,
  17178     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
  17179   { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
  17180     0,
  17181     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
  17182   { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
  17183     0,
  17184     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
  17185   { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
  17186     0,
  17187     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
  17188   { "ihi", ICLASS_xt_iclass_icache,
  17189     0,
  17190     Opcode_ihi_encode_fns, 0, 0 },
  17191   { "ipf", ICLASS_xt_iclass_icache,
  17192     0,
  17193     Opcode_ipf_encode_fns, 0, 0 },
  17194   { "ihu", ICLASS_xt_iclass_icache_lock,
  17195     0,
  17196     Opcode_ihu_encode_fns, 0, 0 },
  17197   { "iiu", ICLASS_xt_iclass_icache_lock,
  17198     0,
  17199     Opcode_iiu_encode_fns, 0, 0 },
  17200   { "ipfl", ICLASS_xt_iclass_icache_lock,
  17201     0,
  17202     Opcode_ipfl_encode_fns, 0, 0 },
  17203   { "iii", ICLASS_xt_iclass_icache_inv,
  17204     0,
  17205     Opcode_iii_encode_fns, 0, 0 },
  17206   { "lict", ICLASS_xt_iclass_licx,
  17207     0,
  17208     Opcode_lict_encode_fns, 1, Opcode_lict_funcUnit_uses },
  17209   { "licw", ICLASS_xt_iclass_licx,
  17210     0,
  17211     Opcode_licw_encode_fns, 1, Opcode_licw_funcUnit_uses },
  17212   { "sict", ICLASS_xt_iclass_sicx,
  17213     0,
  17214     Opcode_sict_encode_fns, 1, Opcode_sict_funcUnit_uses },
  17215   { "sicw", ICLASS_xt_iclass_sicx,
  17216     0,
  17217     Opcode_sicw_encode_fns, 1, Opcode_sicw_funcUnit_uses },
  17218   { "dhwb", ICLASS_xt_iclass_dcache,
  17219     0,
  17220     Opcode_dhwb_encode_fns, 0, 0 },
  17221   { "dhwbi", ICLASS_xt_iclass_dcache,
  17222     0,
  17223     Opcode_dhwbi_encode_fns, 0, 0 },
  17224   { "diwbui.p", ICLASS_xt_iclass_dcache_dyn,
  17225     0,
  17226     Opcode_diwbui_p_encode_fns, 0, 0 },
  17227   { "diwb", ICLASS_xt_iclass_dcache_ind,
  17228     0,
  17229     Opcode_diwb_encode_fns, 0, 0 },
  17230   { "diwbi", ICLASS_xt_iclass_dcache_ind,
  17231     0,
  17232     Opcode_diwbi_encode_fns, 0, 0 },
  17233   { "dhi", ICLASS_xt_iclass_dcache_inv,
  17234     0,
  17235     Opcode_dhi_encode_fns, 0, 0 },
  17236   { "dii", ICLASS_xt_iclass_dcache_inv,
  17237     0,
  17238     Opcode_dii_encode_fns, 0, 0 },
  17239   { "dpfr", ICLASS_xt_iclass_dpf,
  17240     0,
  17241     Opcode_dpfr_encode_fns, 0, 0 },
  17242   { "dpfro", ICLASS_xt_iclass_dpf,
  17243     0,
  17244     Opcode_dpfro_encode_fns, 0, 0 },
  17245   { "dpfw", ICLASS_xt_iclass_dpf,
  17246     0,
  17247     Opcode_dpfw_encode_fns, 0, 0 },
  17248   { "dpfwo", ICLASS_xt_iclass_dpf,
  17249     0,
  17250     Opcode_dpfwo_encode_fns, 0, 0 },
  17251   { "dhu", ICLASS_xt_iclass_dcache_lock,
  17252     0,
  17253     Opcode_dhu_encode_fns, 0, 0 },
  17254   { "diu", ICLASS_xt_iclass_dcache_lock,
  17255     0,
  17256     Opcode_diu_encode_fns, 0, 0 },
  17257   { "dpfl", ICLASS_xt_iclass_dcache_lock,
  17258     0,
  17259     Opcode_dpfl_encode_fns, 0, 0 },
  17260   { "sdct", ICLASS_xt_iclass_sdct,
  17261     0,
  17262     Opcode_sdct_encode_fns, 1, Opcode_sdct_funcUnit_uses },
  17263   { "ldct", ICLASS_xt_iclass_ldct,
  17264     0,
  17265     Opcode_ldct_encode_fns, 1, Opcode_ldct_funcUnit_uses },
  17266   { "sdcw", ICLASS_xt_iclass_sdcw,
  17267     0,
  17268     Opcode_sdcw_encode_fns, 1, Opcode_sdcw_funcUnit_uses },
  17269   { "ldcw", ICLASS_xt_iclass_ldcw,
  17270     0,
  17271     Opcode_ldcw_encode_fns, 1, Opcode_ldcw_funcUnit_uses },
  17272   { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
  17273     0,
  17274     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
  17275   { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
  17276     0,
  17277     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
  17278   { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
  17279     0,
  17280     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
  17281   { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
  17282     0,
  17283     Opcode_rsr_rasid_encode_fns, 0, 0 },
  17284   { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
  17285     0,
  17286     Opcode_wsr_rasid_encode_fns, 0, 0 },
  17287   { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
  17288     0,
  17289     Opcode_xsr_rasid_encode_fns, 0, 0 },
  17290   { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
  17291     0,
  17292     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
  17293   { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
  17294     0,
  17295     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
  17296   { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
  17297     0,
  17298     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
  17299   { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
  17300     0,
  17301     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
  17302   { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
  17303     0,
  17304     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
  17305   { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
  17306     0,
  17307     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
  17308   { "idtlb", ICLASS_xt_iclass_idtlb,
  17309     0,
  17310     Opcode_idtlb_encode_fns, 0, 0 },
  17311   { "pdtlb", ICLASS_xt_iclass_rdtlb,
  17312     0,
  17313     Opcode_pdtlb_encode_fns, 0, 0 },
  17314   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
  17315     0,
  17316     Opcode_rdtlb0_encode_fns, 0, 0 },
  17317   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
  17318     0,
  17319     Opcode_rdtlb1_encode_fns, 0, 0 },
  17320   { "wdtlb", ICLASS_xt_iclass_wdtlb,
  17321     0,
  17322     Opcode_wdtlb_encode_fns, 0, 0 },
  17323   { "iitlb", ICLASS_xt_iclass_iitlb,
  17324     0,
  17325     Opcode_iitlb_encode_fns, 0, 0 },
  17326   { "pitlb", ICLASS_xt_iclass_ritlb,
  17327     0,
  17328     Opcode_pitlb_encode_fns, 0, 0 },
  17329   { "ritlb0", ICLASS_xt_iclass_ritlb,
  17330     0,
  17331     Opcode_ritlb0_encode_fns, 0, 0 },
  17332   { "ritlb1", ICLASS_xt_iclass_ritlb,
  17333     0,
  17334     Opcode_ritlb1_encode_fns, 0, 0 },
  17335   { "witlb", ICLASS_xt_iclass_witlb,
  17336     0,
  17337     Opcode_witlb_encode_fns, 0, 0 },
  17338   { "ldpte", ICLASS_xt_iclass_ldpte,
  17339     0,
  17340     Opcode_ldpte_encode_fns, 1, Opcode_ldpte_funcUnit_uses },
  17341   { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
  17342     XTENSA_OPCODE_IS_BRANCH,
  17343     Opcode_hwwitlba_encode_fns, 0, 0 },
  17344   { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
  17345     0,
  17346     Opcode_hwwdtlba_encode_fns, 0, 0 },
  17347   { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
  17348     0,
  17349     Opcode_rsr_cpenable_encode_fns, 0, 0 },
  17350   { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
  17351     0,
  17352     Opcode_wsr_cpenable_encode_fns, 0, 0 },
  17353   { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
  17354     0,
  17355     Opcode_xsr_cpenable_encode_fns, 0, 0 },
  17356   { "clamps", ICLASS_xt_iclass_clamp,
  17357     0,
  17358     Opcode_clamps_encode_fns, 0, 0 },
  17359   { "max", ICLASS_xt_iclass_minmax,
  17360     0,
  17361     Opcode_max_encode_fns, 0, 0 },
  17362   { "maxu", ICLASS_xt_iclass_minmax,
  17363     0,
  17364     Opcode_maxu_encode_fns, 0, 0 },
  17365   { "min", ICLASS_xt_iclass_minmax,
  17366     0,
  17367     Opcode_min_encode_fns, 0, 0 },
  17368   { "minu", ICLASS_xt_iclass_minmax,
  17369     0,
  17370     Opcode_minu_encode_fns, 0, 0 },
  17371   { "nsa", ICLASS_xt_iclass_nsa,
  17372     0,
  17373     Opcode_nsa_encode_fns, 0, 0 },
  17374   { "nsau", ICLASS_xt_iclass_nsa,
  17375     0,
  17376     Opcode_nsau_encode_fns, 0, 0 },
  17377   { "sext", ICLASS_xt_iclass_sx,
  17378     0,
  17379     Opcode_sext_encode_fns, 0, 0 },
  17380   { "l32ai", ICLASS_xt_iclass_l32ai,
  17381     0,
  17382     Opcode_l32ai_encode_fns, 1, Opcode_l32ai_funcUnit_uses },
  17383   { "s32ri", ICLASS_xt_iclass_s32ri,
  17384     0,
  17385     Opcode_s32ri_encode_fns, 1, Opcode_s32ri_funcUnit_uses },
  17386   { "s32c1i", ICLASS_xt_iclass_s32c1i,
  17387     0,
  17388     Opcode_s32c1i_encode_fns, 1, Opcode_s32c1i_funcUnit_uses },
  17389   { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
  17390     0,
  17391     Opcode_rsr_scompare1_encode_fns, 0, 0 },
  17392   { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
  17393     0,
  17394     Opcode_wsr_scompare1_encode_fns, 0, 0 },
  17395   { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
  17396     0,
  17397     Opcode_xsr_scompare1_encode_fns, 0, 0 },
  17398   { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
  17399     0,
  17400     Opcode_rsr_atomctl_encode_fns, 0, 0 },
  17401   { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
  17402     0,
  17403     Opcode_wsr_atomctl_encode_fns, 0, 0 },
  17404   { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
  17405     0,
  17406     Opcode_xsr_atomctl_encode_fns, 0, 0 },
  17407   { "quos", ICLASS_xt_iclass_div,
  17408     0,
  17409     Opcode_quos_encode_fns, 0, 0 },
  17410   { "quou", ICLASS_xt_iclass_div,
  17411     0,
  17412     Opcode_quou_encode_fns, 0, 0 },
  17413   { "rems", ICLASS_xt_iclass_div,
  17414     0,
  17415     Opcode_rems_encode_fns, 0, 0 },
  17416   { "remu", ICLASS_xt_iclass_div,
  17417     0,
  17418     Opcode_remu_encode_fns, 0, 0 },
  17419   { "rsr.eraccess", ICLASS_xt_iclass_rsr_eraccess,
  17420     0,
  17421     Opcode_rsr_eraccess_encode_fns, 0, 0 },
  17422   { "wsr.eraccess", ICLASS_xt_iclass_wsr_eraccess,
  17423     0,
  17424     Opcode_wsr_eraccess_encode_fns, 0, 0 },
  17425   { "xsr.eraccess", ICLASS_xt_iclass_xsr_eraccess,
  17426     0,
  17427     Opcode_xsr_eraccess_encode_fns, 0, 0 },
  17428   { "rer", ICLASS_xt_iclass_rer,
  17429     0,
  17430     Opcode_rer_encode_fns, 0, 0 },
  17431   { "wer", ICLASS_xt_iclass_wer,
  17432     0,
  17433     Opcode_wer_encode_fns, 0, 0 },
  17434   { "rur.fcr", ICLASS_rur_fcr,
  17435     0,
  17436     Opcode_rur_fcr_encode_fns, 0, 0 },
  17437   { "wur.fcr", ICLASS_wur_fcr,
  17438     0,
  17439     Opcode_wur_fcr_encode_fns, 0, 0 },
  17440   { "rur.fsr", ICLASS_rur_fsr,
  17441     0,
  17442     Opcode_rur_fsr_encode_fns, 0, 0 },
  17443   { "wur.fsr", ICLASS_wur_fsr,
  17444     0,
  17445     Opcode_wur_fsr_encode_fns, 0, 0 },
  17446   { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
  17447     0,
  17448     Opcode_read_impwire_encode_fns, 0, 0 },
  17449   { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
  17450     0,
  17451     Opcode_setb_expstate_encode_fns, 0, 0 },
  17452   { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
  17453     0,
  17454     Opcode_clrb_expstate_encode_fns, 0, 0 },
  17455   { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
  17456     0,
  17457     Opcode_wrmsk_expstate_encode_fns, 0, 0 },
  17458   { "rur.expstate", ICLASS_rur_expstate,
  17459     0,
  17460     Opcode_rur_expstate_encode_fns, 0, 0 },
  17461   { "wur.expstate", ICLASS_wur_expstate,
  17462     0,
  17463     Opcode_wur_expstate_encode_fns, 0, 0 },
  17464   { "lsi", ICLASS_LSI,
  17465     0,
  17466     Opcode_lsi_encode_fns, 1, Opcode_lsi_funcUnit_uses },
  17467   { "lsip", ICLASS_LSIP,
  17468     0,
  17469     Opcode_lsip_encode_fns, 1, Opcode_lsip_funcUnit_uses },
  17470   { "lsx", ICLASS_LSX,
  17471     0,
  17472     Opcode_lsx_encode_fns, 1, Opcode_lsx_funcUnit_uses },
  17473   { "lsxp", ICLASS_LSXP,
  17474     0,
  17475     Opcode_lsxp_encode_fns, 1, Opcode_lsxp_funcUnit_uses },
  17476   { "ssi", ICLASS_SSI,
  17477     0,
  17478     Opcode_ssi_encode_fns, 1, Opcode_ssi_funcUnit_uses },
  17479   { "ssip", ICLASS_SSIP,
  17480     0,
  17481     Opcode_ssip_encode_fns, 1, Opcode_ssip_funcUnit_uses },
  17482   { "ssx", ICLASS_SSX,
  17483     0,
  17484     Opcode_ssx_encode_fns, 1, Opcode_ssx_funcUnit_uses },
  17485   { "ssxp", ICLASS_SSXP,
  17486     0,
  17487     Opcode_ssxp_encode_fns, 1, Opcode_ssxp_funcUnit_uses },
  17488   { "ldi", ICLASS_LDI,
  17489     0,
  17490     Opcode_ldi_encode_fns, 1, Opcode_ldi_funcUnit_uses },
  17491   { "ldip", ICLASS_LDIP,
  17492     0,
  17493     Opcode_ldip_encode_fns, 1, Opcode_ldip_funcUnit_uses },
  17494   { "ldx", ICLASS_LDX,
  17495     0,
  17496     Opcode_ldx_encode_fns, 1, Opcode_ldx_funcUnit_uses },
  17497   { "ldxp", ICLASS_LDXP,
  17498     0,
  17499     Opcode_ldxp_encode_fns, 1, Opcode_ldxp_funcUnit_uses },
  17500   { "sdi", ICLASS_SDI,
  17501     0,
  17502     Opcode_sdi_encode_fns, 1, Opcode_sdi_funcUnit_uses },
  17503   { "sdip", ICLASS_SDIP,
  17504     0,
  17505     Opcode_sdip_encode_fns, 1, Opcode_sdip_funcUnit_uses },
  17506   { "sdx", ICLASS_SDX,
  17507     0,
  17508     Opcode_sdx_encode_fns, 1, Opcode_sdx_funcUnit_uses },
  17509   { "sdxp", ICLASS_SDXP,
  17510     0,
  17511     Opcode_sdxp_encode_fns, 1, Opcode_sdxp_funcUnit_uses },
  17512   { "abs.s", ICLASS_ABS_S,
  17513     0,
  17514     Opcode_abs_s_encode_fns, 0, 0 },
  17515   { "neg.s", ICLASS_NEG_S,
  17516     0,
  17517     Opcode_neg_s_encode_fns, 0, 0 },
  17518   { "abs.d", ICLASS_ABS_D,
  17519     0,
  17520     Opcode_abs_d_encode_fns, 0, 0 },
  17521   { "neg.d", ICLASS_NEG_D,
  17522     0,
  17523     Opcode_neg_d_encode_fns, 0, 0 },
  17524   { "mov.s", ICLASS_MOV_S,
  17525     0,
  17526     Opcode_mov_s_encode_fns, 0, 0 },
  17527   { "mov.d", ICLASS_MOV_D,
  17528     0,
  17529     Opcode_mov_d_encode_fns, 0, 0 },
  17530   { "moveqz.s", ICLASS_MOVEQZ_S,
  17531     0,
  17532     Opcode_moveqz_s_encode_fns, 0, 0 },
  17533   { "movnez.s", ICLASS_MOVNEZ_S,
  17534     0,
  17535     Opcode_movnez_s_encode_fns, 0, 0 },
  17536   { "movltz.s", ICLASS_MOVLTZ_S,
  17537     0,
  17538     Opcode_movltz_s_encode_fns, 0, 0 },
  17539   { "movgez.s", ICLASS_MOVGEZ_S,
  17540     0,
  17541     Opcode_movgez_s_encode_fns, 0, 0 },
  17542   { "movf.s", ICLASS_MOVF_S,
  17543     0,
  17544     Opcode_movf_s_encode_fns, 0, 0 },
  17545   { "movt.s", ICLASS_MOVT_S,
  17546     0,
  17547     Opcode_movt_s_encode_fns, 0, 0 },
  17548   { "wfr", ICLASS_WFR,
  17549     0,
  17550     Opcode_wfr_encode_fns, 0, 0 },
  17551   { "rfr", ICLASS_RFR,
  17552     0,
  17553     Opcode_rfr_encode_fns, 0, 0 },
  17554   { "rfrd", ICLASS_RFRD,
  17555     0,
  17556     Opcode_rfrd_encode_fns, 0, 0 },
  17557   { "wfrd", ICLASS_WFRD,
  17558     0,
  17559     Opcode_wfrd_encode_fns, 0, 0 },
  17560   { "round.s", ICLASS_ROUND_S,
  17561     0,
  17562     Opcode_round_s_encode_fns, 0, 0 },
  17563   { "round.d", ICLASS_ROUND_D,
  17564     0,
  17565     Opcode_round_d_encode_fns, 0, 0 },
  17566   { "ceil.s", ICLASS_CEIL_S,
  17567     0,
  17568     Opcode_ceil_s_encode_fns, 0, 0 },
  17569   { "ceil.d", ICLASS_CEIL_D,
  17570     0,
  17571     Opcode_ceil_d_encode_fns, 0, 0 },
  17572   { "floor.s", ICLASS_FLOOR_S,
  17573     0,
  17574     Opcode_floor_s_encode_fns, 0, 0 },
  17575   { "floor.d", ICLASS_FLOOR_D,
  17576     0,
  17577     Opcode_floor_d_encode_fns, 0, 0 },
  17578   { "trunc.s", ICLASS_TRUNC_S,
  17579     0,
  17580     Opcode_trunc_s_encode_fns, 0, 0 },
  17581   { "trunc.d", ICLASS_TRUNC_D,
  17582     0,
  17583     Opcode_trunc_d_encode_fns, 0, 0 },
  17584   { "utrunc.s", ICLASS_UTRUNC_S,
  17585     0,
  17586     Opcode_utrunc_s_encode_fns, 0, 0 },
  17587   { "utrunc.d", ICLASS_UTRUNC_D,
  17588     0,
  17589     Opcode_utrunc_d_encode_fns, 0, 0 },
  17590   { "float.s", ICLASS_FLOAT_S,
  17591     0,
  17592     Opcode_float_s_encode_fns, 0, 0 },
  17593   { "float.d", ICLASS_FLOAT_D,
  17594     0,
  17595     Opcode_float_d_encode_fns, 0, 0 },
  17596   { "ufloat.s", ICLASS_UFLOAT_S,
  17597     0,
  17598     Opcode_ufloat_s_encode_fns, 0, 0 },
  17599   { "ufloat.d", ICLASS_UFLOAT_D,
  17600     0,
  17601     Opcode_ufloat_d_encode_fns, 0, 0 },
  17602   { "cvtd.s", ICLASS_CVTD_S,
  17603     0,
  17604     Opcode_cvtd_s_encode_fns, 0, 0 },
  17605   { "cvts.d", ICLASS_CVTS_D,
  17606     0,
  17607     Opcode_cvts_d_encode_fns, 0, 0 },
  17608   { "un.s", ICLASS_UN_S,
  17609     0,
  17610     Opcode_un_s_encode_fns, 0, 0 },
  17611   { "un.d", ICLASS_UN_D,
  17612     0,
  17613     Opcode_un_d_encode_fns, 0, 0 },
  17614   { "ult.s", ICLASS_ULT_S,
  17615     0,
  17616     Opcode_ult_s_encode_fns, 0, 0 },
  17617   { "ult.d", ICLASS_ULT_D,
  17618     0,
  17619     Opcode_ult_d_encode_fns, 0, 0 },
  17620   { "ule.s", ICLASS_ULE_S,
  17621     0,
  17622     Opcode_ule_s_encode_fns, 0, 0 },
  17623   { "ule.d", ICLASS_ULE_D,
  17624     0,
  17625     Opcode_ule_d_encode_fns, 0, 0 },
  17626   { "ueq.s", ICLASS_UEQ_S,
  17627     0,
  17628     Opcode_ueq_s_encode_fns, 0, 0 },
  17629   { "ueq.d", ICLASS_UEQ_D,
  17630     0,
  17631     Opcode_ueq_d_encode_fns, 0, 0 },
  17632   { "olt.s", ICLASS_OLT_S,
  17633     0,
  17634     Opcode_olt_s_encode_fns, 0, 0 },
  17635   { "olt.d", ICLASS_OLT_D,
  17636     0,
  17637     Opcode_olt_d_encode_fns, 0, 0 },
  17638   { "ole.s", ICLASS_OLE_S,
  17639     0,
  17640     Opcode_ole_s_encode_fns, 0, 0 },
  17641   { "ole.d", ICLASS_OLE_D,
  17642     0,
  17643     Opcode_ole_d_encode_fns, 0, 0 },
  17644   { "oeq.s", ICLASS_OEQ_S,
  17645     0,
  17646     Opcode_oeq_s_encode_fns, 0, 0 },
  17647   { "oeq.d", ICLASS_OEQ_D,
  17648     0,
  17649     Opcode_oeq_d_encode_fns, 0, 0 },
  17650   { "add.s", ICLASS_ADD_S,
  17651     0,
  17652     Opcode_add_s_encode_fns, 0, 0 },
  17653   { "add.d", ICLASS_ADD_D,
  17654     0,
  17655     Opcode_add_d_encode_fns, 0, 0 },
  17656   { "sub.s", ICLASS_SUB_S,
  17657     0,
  17658     Opcode_sub_s_encode_fns, 0, 0 },
  17659   { "sub.d", ICLASS_SUB_D,
  17660     0,
  17661     Opcode_sub_d_encode_fns, 0, 0 },
  17662   { "mul.s", ICLASS_MUL_S,
  17663     0,
  17664     Opcode_mul_s_encode_fns, 0, 0 },
  17665   { "mul.d", ICLASS_MUL_D,
  17666     0,
  17667     Opcode_mul_d_encode_fns, 0, 0 },
  17668   { "madd.s", ICLASS_MADD_S,
  17669     0,
  17670     Opcode_madd_s_encode_fns, 0, 0 },
  17671   { "madd.d", ICLASS_MADD_D,
  17672     0,
  17673     Opcode_madd_d_encode_fns, 0, 0 },
  17674   { "msub.s", ICLASS_MSUB_S,
  17675     0,
  17676     Opcode_msub_s_encode_fns, 0, 0 },
  17677   { "msub.d", ICLASS_MSUB_D,
  17678     0,
  17679     Opcode_msub_d_encode_fns, 0, 0 },
  17680   { "sqrt0.s", ICLASS_SQRT0_S,
  17681     0,
  17682     Opcode_sqrt0_s_encode_fns, 0, 0 },
  17683   { "sqrt0.d", ICLASS_SQRT0_D,
  17684     0,
  17685     Opcode_sqrt0_d_encode_fns, 0, 0 },
  17686   { "div0.s", ICLASS_DIV0_S,
  17687     0,
  17688     Opcode_div0_s_encode_fns, 0, 0 },
  17689   { "div0.d", ICLASS_DIV0_D,
  17690     0,
  17691     Opcode_div0_d_encode_fns, 0, 0 },
  17692   { "recip0.s", ICLASS_RECIP0_S,
  17693     0,
  17694     Opcode_recip0_s_encode_fns, 0, 0 },
  17695   { "recip0.d", ICLASS_RECIP0_D,
  17696     0,
  17697     Opcode_recip0_d_encode_fns, 0, 0 },
  17698   { "rsqrt0.s", ICLASS_RSQRT0_S,
  17699     0,
  17700     Opcode_rsqrt0_s_encode_fns, 0, 0 },
  17701   { "rsqrt0.d", ICLASS_RSQRT0_D,
  17702     0,
  17703     Opcode_rsqrt0_d_encode_fns, 0, 0 },
  17704   { "maddn.s", ICLASS_MADDN_S,
  17705     0,
  17706     Opcode_maddn_s_encode_fns, 0, 0 },
  17707   { "maddn.d", ICLASS_MADDN_D,
  17708     0,
  17709     Opcode_maddn_d_encode_fns, 0, 0 },
  17710   { "divn.s", ICLASS_DIVN_S,
  17711     0,
  17712     Opcode_divn_s_encode_fns, 0, 0 },
  17713   { "divn.d", ICLASS_DIVN_D,
  17714     0,
  17715     Opcode_divn_d_encode_fns, 0, 0 },
  17716   { "const.s", ICLASS_CONST_S,
  17717     0,
  17718     Opcode_const_s_encode_fns, 0, 0 },
  17719   { "const.d", ICLASS_CONST_D,
  17720     0,
  17721     Opcode_const_d_encode_fns, 0, 0 },
  17722   { "nexp01.s", ICLASS_NEXP01_S,
  17723     0,
  17724     Opcode_nexp01_s_encode_fns, 0, 0 },
  17725   { "nexp01.d", ICLASS_NEXP01_D,
  17726     0,
  17727     Opcode_nexp01_d_encode_fns, 0, 0 },
  17728   { "addexp.s", ICLASS_ADDEXP_S,
  17729     0,
  17730     Opcode_addexp_s_encode_fns, 0, 0 },
  17731   { "addexp.d", ICLASS_ADDEXP_D,
  17732     0,
  17733     Opcode_addexp_d_encode_fns, 0, 0 },
  17734   { "addexpm.s", ICLASS_ADDEXPM_S,
  17735     0,
  17736     Opcode_addexpm_s_encode_fns, 0, 0 },
  17737   { "addexpm.d", ICLASS_ADDEXPM_D,
  17738     0,
  17739     Opcode_addexpm_d_encode_fns, 0, 0 },
  17740   { "mkdadj.s", ICLASS_MKDADJ_S,
  17741     0,
  17742     Opcode_mkdadj_s_encode_fns, 0, 0 },
  17743   { "mkdadj.d", ICLASS_MKDADJ_D,
  17744     0,
  17745     Opcode_mkdadj_d_encode_fns, 0, 0 },
  17746   { "mksadj.s", ICLASS_MKSADJ_S,
  17747     0,
  17748     Opcode_mksadj_s_encode_fns, 0, 0 },
  17749   { "mksadj.d", ICLASS_MKSADJ_D,
  17750     0,
  17751     Opcode_mksadj_d_encode_fns, 0, 0 }
  17752 };
  17753 
  17754 enum xtensa_opcode_id {
  17755   OPCODE_EXCW,
  17756   OPCODE_RFE,
  17757   OPCODE_RFDE,
  17758   OPCODE_SYSCALL,
  17759   OPCODE_CALL12,
  17760   OPCODE_CALL8,
  17761   OPCODE_CALL4,
  17762   OPCODE_CALLX12,
  17763   OPCODE_CALLX8,
  17764   OPCODE_CALLX4,
  17765   OPCODE_ENTRY,
  17766   OPCODE_MOVSP,
  17767   OPCODE_ROTW,
  17768   OPCODE_RETW,
  17769   OPCODE_RETW_N,
  17770   OPCODE_RFWO,
  17771   OPCODE_RFWU,
  17772   OPCODE_L32E,
  17773   OPCODE_S32E,
  17774   OPCODE_RSR_WINDOWBASE,
  17775   OPCODE_WSR_WINDOWBASE,
  17776   OPCODE_XSR_WINDOWBASE,
  17777   OPCODE_RSR_WINDOWSTART,
  17778   OPCODE_WSR_WINDOWSTART,
  17779   OPCODE_XSR_WINDOWSTART,
  17780   OPCODE_ADD_N,
  17781   OPCODE_ADDI_N,
  17782   OPCODE_BEQZ_N,
  17783   OPCODE_BNEZ_N,
  17784   OPCODE_ILL_N,
  17785   OPCODE_L32I_N,
  17786   OPCODE_MOV_N,
  17787   OPCODE_MOVI_N,
  17788   OPCODE_NOP_N,
  17789   OPCODE_RET_N,
  17790   OPCODE_S32I_N,
  17791   OPCODE_RUR_THREADPTR,
  17792   OPCODE_WUR_THREADPTR,
  17793   OPCODE_ADDI,
  17794   OPCODE_ADDMI,
  17795   OPCODE_ADD,
  17796   OPCODE_ADDX2,
  17797   OPCODE_ADDX4,
  17798   OPCODE_ADDX8,
  17799   OPCODE_SUB,
  17800   OPCODE_SUBX2,
  17801   OPCODE_SUBX4,
  17802   OPCODE_SUBX8,
  17803   OPCODE_AND,
  17804   OPCODE_OR,
  17805   OPCODE_XOR,
  17806   OPCODE_BEQI,
  17807   OPCODE_BGEI,
  17808   OPCODE_BLTI,
  17809   OPCODE_BNEI,
  17810   OPCODE_BBCI,
  17811   OPCODE_BBSI,
  17812   OPCODE_BGEUI,
  17813   OPCODE_BLTUI,
  17814   OPCODE_BALL,
  17815   OPCODE_BANY,
  17816   OPCODE_BBC,
  17817   OPCODE_BBS,
  17818   OPCODE_BEQ,
  17819   OPCODE_BGE,
  17820   OPCODE_BGEU,
  17821   OPCODE_BLT,
  17822   OPCODE_BLTU,
  17823   OPCODE_BNALL,
  17824   OPCODE_BNE,
  17825   OPCODE_BNONE,
  17826   OPCODE_BEQZ,
  17827   OPCODE_BGEZ,
  17828   OPCODE_BLTZ,
  17829   OPCODE_BNEZ,
  17830   OPCODE_CALL0,
  17831   OPCODE_CALLX0,
  17832   OPCODE_EXTUI,
  17833   OPCODE_ILL,
  17834   OPCODE_J,
  17835   OPCODE_JX,
  17836   OPCODE_L16UI,
  17837   OPCODE_L16SI,
  17838   OPCODE_L32I,
  17839   OPCODE_L32R,
  17840   OPCODE_L8UI,
  17841   OPCODE_LOOP,
  17842   OPCODE_LOOPGTZ,
  17843   OPCODE_LOOPNEZ,
  17844   OPCODE_MOVI,
  17845   OPCODE_MOVEQZ,
  17846   OPCODE_MOVGEZ,
  17847   OPCODE_MOVLTZ,
  17848   OPCODE_MOVNEZ,
  17849   OPCODE_ABS,
  17850   OPCODE_NEG,
  17851   OPCODE_NOP,
  17852   OPCODE_RET,
  17853   OPCODE_SIMCALL,
  17854   OPCODE_S16I,
  17855   OPCODE_S32I,
  17856   OPCODE_S32NB,
  17857   OPCODE_S8I,
  17858   OPCODE_SSA8B,
  17859   OPCODE_SSA8L,
  17860   OPCODE_SSL,
  17861   OPCODE_SSR,
  17862   OPCODE_SSAI,
  17863   OPCODE_SLL,
  17864   OPCODE_SRC,
  17865   OPCODE_SRA,
  17866   OPCODE_SRL,
  17867   OPCODE_SLLI,
  17868   OPCODE_SRAI,
  17869   OPCODE_SRLI,
  17870   OPCODE_MEMW,
  17871   OPCODE_EXTW,
  17872   OPCODE_ISYNC,
  17873   OPCODE_DSYNC,
  17874   OPCODE_ESYNC,
  17875   OPCODE_RSYNC,
  17876   OPCODE_RSIL,
  17877   OPCODE_RSR_LEND,
  17878   OPCODE_WSR_LEND,
  17879   OPCODE_XSR_LEND,
  17880   OPCODE_RSR_LCOUNT,
  17881   OPCODE_WSR_LCOUNT,
  17882   OPCODE_XSR_LCOUNT,
  17883   OPCODE_RSR_LBEG,
  17884   OPCODE_WSR_LBEG,
  17885   OPCODE_XSR_LBEG,
  17886   OPCODE_RSR_SAR,
  17887   OPCODE_WSR_SAR,
  17888   OPCODE_XSR_SAR,
  17889   OPCODE_RSR_MEMCTL,
  17890   OPCODE_WSR_MEMCTL,
  17891   OPCODE_XSR_MEMCTL,
  17892   OPCODE_RSR_CONFIGID0,
  17893   OPCODE_WSR_CONFIGID0,
  17894   OPCODE_RSR_CONFIGID1,
  17895   OPCODE_RSR_PS,
  17896   OPCODE_WSR_PS,
  17897   OPCODE_XSR_PS,
  17898   OPCODE_RSR_EPC1,
  17899   OPCODE_WSR_EPC1,
  17900   OPCODE_XSR_EPC1,
  17901   OPCODE_RSR_EXCSAVE1,
  17902   OPCODE_WSR_EXCSAVE1,
  17903   OPCODE_XSR_EXCSAVE1,
  17904   OPCODE_RSR_EPC2,
  17905   OPCODE_WSR_EPC2,
  17906   OPCODE_XSR_EPC2,
  17907   OPCODE_RSR_EXCSAVE2,
  17908   OPCODE_WSR_EXCSAVE2,
  17909   OPCODE_XSR_EXCSAVE2,
  17910   OPCODE_RSR_EPC3,
  17911   OPCODE_WSR_EPC3,
  17912   OPCODE_XSR_EPC3,
  17913   OPCODE_RSR_EXCSAVE3,
  17914   OPCODE_WSR_EXCSAVE3,
  17915   OPCODE_XSR_EXCSAVE3,
  17916   OPCODE_RSR_EPC4,
  17917   OPCODE_WSR_EPC4,
  17918   OPCODE_XSR_EPC4,
  17919   OPCODE_RSR_EXCSAVE4,
  17920   OPCODE_WSR_EXCSAVE4,
  17921   OPCODE_XSR_EXCSAVE4,
  17922   OPCODE_RSR_EPC5,
  17923   OPCODE_WSR_EPC5,
  17924   OPCODE_XSR_EPC5,
  17925   OPCODE_RSR_EXCSAVE5,
  17926   OPCODE_WSR_EXCSAVE5,
  17927   OPCODE_XSR_EXCSAVE5,
  17928   OPCODE_RSR_EPC6,
  17929   OPCODE_WSR_EPC6,
  17930   OPCODE_XSR_EPC6,
  17931   OPCODE_RSR_EXCSAVE6,
  17932   OPCODE_WSR_EXCSAVE6,
  17933   OPCODE_XSR_EXCSAVE6,
  17934   OPCODE_RSR_EPC7,
  17935   OPCODE_WSR_EPC7,
  17936   OPCODE_XSR_EPC7,
  17937   OPCODE_RSR_EXCSAVE7,
  17938   OPCODE_WSR_EXCSAVE7,
  17939   OPCODE_XSR_EXCSAVE7,
  17940   OPCODE_RSR_EPS2,
  17941   OPCODE_WSR_EPS2,
  17942   OPCODE_XSR_EPS2,
  17943   OPCODE_RSR_EPS3,
  17944   OPCODE_WSR_EPS3,
  17945   OPCODE_XSR_EPS3,
  17946   OPCODE_RSR_EPS4,
  17947   OPCODE_WSR_EPS4,
  17948   OPCODE_XSR_EPS4,
  17949   OPCODE_RSR_EPS5,
  17950   OPCODE_WSR_EPS5,
  17951   OPCODE_XSR_EPS5,
  17952   OPCODE_RSR_EPS6,
  17953   OPCODE_WSR_EPS6,
  17954   OPCODE_XSR_EPS6,
  17955   OPCODE_RSR_EPS7,
  17956   OPCODE_WSR_EPS7,
  17957   OPCODE_XSR_EPS7,
  17958   OPCODE_RSR_EXCVADDR,
  17959   OPCODE_WSR_EXCVADDR,
  17960   OPCODE_XSR_EXCVADDR,
  17961   OPCODE_RSR_DEPC,
  17962   OPCODE_WSR_DEPC,
  17963   OPCODE_XSR_DEPC,
  17964   OPCODE_RSR_EXCCAUSE,
  17965   OPCODE_WSR_EXCCAUSE,
  17966   OPCODE_XSR_EXCCAUSE,
  17967   OPCODE_RSR_MISC0,
  17968   OPCODE_WSR_MISC0,
  17969   OPCODE_XSR_MISC0,
  17970   OPCODE_RSR_MISC1,
  17971   OPCODE_WSR_MISC1,
  17972   OPCODE_XSR_MISC1,
  17973   OPCODE_RSR_PRID,
  17974   OPCODE_RSR_VECBASE,
  17975   OPCODE_WSR_VECBASE,
  17976   OPCODE_XSR_VECBASE,
  17977   OPCODE_SALT,
  17978   OPCODE_SALTU,
  17979   OPCODE_MUL16S,
  17980   OPCODE_MUL16U,
  17981   OPCODE_MULL,
  17982   OPCODE_MUL_AA_HH,
  17983   OPCODE_MUL_AA_HL,
  17984   OPCODE_MUL_AA_LH,
  17985   OPCODE_MUL_AA_LL,
  17986   OPCODE_UMUL_AA_HH,
  17987   OPCODE_UMUL_AA_HL,
  17988   OPCODE_UMUL_AA_LH,
  17989   OPCODE_UMUL_AA_LL,
  17990   OPCODE_MUL_AD_HH,
  17991   OPCODE_MUL_AD_HL,
  17992   OPCODE_MUL_AD_LH,
  17993   OPCODE_MUL_AD_LL,
  17994   OPCODE_MUL_DA_HH,
  17995   OPCODE_MUL_DA_HL,
  17996   OPCODE_MUL_DA_LH,
  17997   OPCODE_MUL_DA_LL,
  17998   OPCODE_MUL_DD_HH,
  17999   OPCODE_MUL_DD_HL,
  18000   OPCODE_MUL_DD_LH,
  18001   OPCODE_MUL_DD_LL,
  18002   OPCODE_MULA_AA_HH,
  18003   OPCODE_MULA_AA_HL,
  18004   OPCODE_MULA_AA_LH,
  18005   OPCODE_MULA_AA_LL,
  18006   OPCODE_MULS_AA_HH,
  18007   OPCODE_MULS_AA_HL,
  18008   OPCODE_MULS_AA_LH,
  18009   OPCODE_MULS_AA_LL,
  18010   OPCODE_MULA_AD_HH,
  18011   OPCODE_MULA_AD_HL,
  18012   OPCODE_MULA_AD_LH,
  18013   OPCODE_MULA_AD_LL,
  18014   OPCODE_MULS_AD_HH,
  18015   OPCODE_MULS_AD_HL,
  18016   OPCODE_MULS_AD_LH,
  18017   OPCODE_MULS_AD_LL,
  18018   OPCODE_MULA_DA_HH,
  18019   OPCODE_MULA_DA_HL,
  18020   OPCODE_MULA_DA_LH,
  18021   OPCODE_MULA_DA_LL,
  18022   OPCODE_MULS_DA_HH,
  18023   OPCODE_MULS_DA_HL,
  18024   OPCODE_MULS_DA_LH,
  18025   OPCODE_MULS_DA_LL,
  18026   OPCODE_MULA_DD_HH,
  18027   OPCODE_MULA_DD_HL,
  18028   OPCODE_MULA_DD_LH,
  18029   OPCODE_MULA_DD_LL,
  18030   OPCODE_MULS_DD_HH,
  18031   OPCODE_MULS_DD_HL,
  18032   OPCODE_MULS_DD_LH,
  18033   OPCODE_MULS_DD_LL,
  18034   OPCODE_MULA_DA_HH_LDDEC,
  18035   OPCODE_MULA_DA_HH_LDINC,
  18036   OPCODE_MULA_DA_HL_LDDEC,
  18037   OPCODE_MULA_DA_HL_LDINC,
  18038   OPCODE_MULA_DA_LH_LDDEC,
  18039   OPCODE_MULA_DA_LH_LDINC,
  18040   OPCODE_MULA_DA_LL_LDDEC,
  18041   OPCODE_MULA_DA_LL_LDINC,
  18042   OPCODE_MULA_DD_HH_LDDEC,
  18043   OPCODE_MULA_DD_HH_LDINC,
  18044   OPCODE_MULA_DD_HL_LDDEC,
  18045   OPCODE_MULA_DD_HL_LDINC,
  18046   OPCODE_MULA_DD_LH_LDDEC,
  18047   OPCODE_MULA_DD_LH_LDINC,
  18048   OPCODE_MULA_DD_LL_LDDEC,
  18049   OPCODE_MULA_DD_LL_LDINC,
  18050   OPCODE_LDDEC,
  18051   OPCODE_LDINC,
  18052   OPCODE_RSR_M0,
  18053   OPCODE_WSR_M0,
  18054   OPCODE_XSR_M0,
  18055   OPCODE_RSR_M1,
  18056   OPCODE_WSR_M1,
  18057   OPCODE_XSR_M1,
  18058   OPCODE_RSR_M2,
  18059   OPCODE_WSR_M2,
  18060   OPCODE_XSR_M2,
  18061   OPCODE_RSR_M3,
  18062   OPCODE_WSR_M3,
  18063   OPCODE_XSR_M3,
  18064   OPCODE_RSR_ACCLO,
  18065   OPCODE_WSR_ACCLO,
  18066   OPCODE_XSR_ACCLO,
  18067   OPCODE_RSR_ACCHI,
  18068   OPCODE_WSR_ACCHI,
  18069   OPCODE_XSR_ACCHI,
  18070   OPCODE_RFI,
  18071   OPCODE_WAITI,
  18072   OPCODE_RSR_INTERRUPT,
  18073   OPCODE_WSR_INTSET,
  18074   OPCODE_WSR_INTCLEAR,
  18075   OPCODE_RSR_INTENABLE,
  18076   OPCODE_WSR_INTENABLE,
  18077   OPCODE_XSR_INTENABLE,
  18078   OPCODE_BREAK,
  18079   OPCODE_BREAK_N,
  18080   OPCODE_RSR_DBREAKA0,
  18081   OPCODE_WSR_DBREAKA0,
  18082   OPCODE_XSR_DBREAKA0,
  18083   OPCODE_RSR_DBREAKC0,
  18084   OPCODE_WSR_DBREAKC0,
  18085   OPCODE_XSR_DBREAKC0,
  18086   OPCODE_RSR_DBREAKA1,
  18087   OPCODE_WSR_DBREAKA1,
  18088   OPCODE_XSR_DBREAKA1,
  18089   OPCODE_RSR_DBREAKC1,
  18090   OPCODE_WSR_DBREAKC1,
  18091   OPCODE_XSR_DBREAKC1,
  18092   OPCODE_RSR_IBREAKA0,
  18093   OPCODE_WSR_IBREAKA0,
  18094   OPCODE_XSR_IBREAKA0,
  18095   OPCODE_RSR_IBREAKA1,
  18096   OPCODE_WSR_IBREAKA1,
  18097   OPCODE_XSR_IBREAKA1,
  18098   OPCODE_RSR_IBREAKENABLE,
  18099   OPCODE_WSR_IBREAKENABLE,
  18100   OPCODE_XSR_IBREAKENABLE,
  18101   OPCODE_RSR_DEBUGCAUSE,
  18102   OPCODE_WSR_DEBUGCAUSE,
  18103   OPCODE_XSR_DEBUGCAUSE,
  18104   OPCODE_RSR_ICOUNT,
  18105   OPCODE_WSR_ICOUNT,
  18106   OPCODE_XSR_ICOUNT,
  18107   OPCODE_RSR_ICOUNTLEVEL,
  18108   OPCODE_WSR_ICOUNTLEVEL,
  18109   OPCODE_XSR_ICOUNTLEVEL,
  18110   OPCODE_RSR_DDR,
  18111   OPCODE_WSR_DDR,
  18112   OPCODE_XSR_DDR,
  18113   OPCODE_LDDR32_P,
  18114   OPCODE_SDDR32_P,
  18115   OPCODE_RFDO,
  18116   OPCODE_RFDD,
  18117   OPCODE_WSR_MMID,
  18118   OPCODE_ANDB,
  18119   OPCODE_ANDBC,
  18120   OPCODE_ORB,
  18121   OPCODE_ORBC,
  18122   OPCODE_XORB,
  18123   OPCODE_ALL4,
  18124   OPCODE_ANY4,
  18125   OPCODE_ALL8,
  18126   OPCODE_ANY8,
  18127   OPCODE_BF,
  18128   OPCODE_BT,
  18129   OPCODE_MOVF,
  18130   OPCODE_MOVT,
  18131   OPCODE_RSR_BR,
  18132   OPCODE_WSR_BR,
  18133   OPCODE_XSR_BR,
  18134   OPCODE_RSR_CCOUNT,
  18135   OPCODE_WSR_CCOUNT,
  18136   OPCODE_XSR_CCOUNT,
  18137   OPCODE_RSR_CCOMPARE0,
  18138   OPCODE_WSR_CCOMPARE0,
  18139   OPCODE_XSR_CCOMPARE0,
  18140   OPCODE_RSR_CCOMPARE1,
  18141   OPCODE_WSR_CCOMPARE1,
  18142   OPCODE_XSR_CCOMPARE1,
  18143   OPCODE_RSR_CCOMPARE2,
  18144   OPCODE_WSR_CCOMPARE2,
  18145   OPCODE_XSR_CCOMPARE2,
  18146   OPCODE_IHI,
  18147   OPCODE_IPF,
  18148   OPCODE_IHU,
  18149   OPCODE_IIU,
  18150   OPCODE_IPFL,
  18151   OPCODE_III,
  18152   OPCODE_LICT,
  18153   OPCODE_LICW,
  18154   OPCODE_SICT,
  18155   OPCODE_SICW,
  18156   OPCODE_DHWB,
  18157   OPCODE_DHWBI,
  18158   OPCODE_DIWBUI_P,
  18159   OPCODE_DIWB,
  18160   OPCODE_DIWBI,
  18161   OPCODE_DHI,
  18162   OPCODE_DII,
  18163   OPCODE_DPFR,
  18164   OPCODE_DPFRO,
  18165   OPCODE_DPFW,
  18166   OPCODE_DPFWO,
  18167   OPCODE_DHU,
  18168   OPCODE_DIU,
  18169   OPCODE_DPFL,
  18170   OPCODE_SDCT,
  18171   OPCODE_LDCT,
  18172   OPCODE_SDCW,
  18173   OPCODE_LDCW,
  18174   OPCODE_WSR_PTEVADDR,
  18175   OPCODE_RSR_PTEVADDR,
  18176   OPCODE_XSR_PTEVADDR,
  18177   OPCODE_RSR_RASID,
  18178   OPCODE_WSR_RASID,
  18179   OPCODE_XSR_RASID,
  18180   OPCODE_RSR_ITLBCFG,
  18181   OPCODE_WSR_ITLBCFG,
  18182   OPCODE_XSR_ITLBCFG,
  18183   OPCODE_RSR_DTLBCFG,
  18184   OPCODE_WSR_DTLBCFG,
  18185   OPCODE_XSR_DTLBCFG,
  18186   OPCODE_IDTLB,
  18187   OPCODE_PDTLB,
  18188   OPCODE_RDTLB0,
  18189   OPCODE_RDTLB1,
  18190   OPCODE_WDTLB,
  18191   OPCODE_IITLB,
  18192   OPCODE_PITLB,
  18193   OPCODE_RITLB0,
  18194   OPCODE_RITLB1,
  18195   OPCODE_WITLB,
  18196   OPCODE_LDPTE,
  18197   OPCODE_HWWITLBA,
  18198   OPCODE_HWWDTLBA,
  18199   OPCODE_RSR_CPENABLE,
  18200   OPCODE_WSR_CPENABLE,
  18201   OPCODE_XSR_CPENABLE,
  18202   OPCODE_CLAMPS,
  18203   OPCODE_MAX,
  18204   OPCODE_MAXU,
  18205   OPCODE_MIN,
  18206   OPCODE_MINU,
  18207   OPCODE_NSA,
  18208   OPCODE_NSAU,
  18209   OPCODE_SEXT,
  18210   OPCODE_L32AI,
  18211   OPCODE_S32RI,
  18212   OPCODE_S32C1I,
  18213   OPCODE_RSR_SCOMPARE1,
  18214   OPCODE_WSR_SCOMPARE1,
  18215   OPCODE_XSR_SCOMPARE1,
  18216   OPCODE_RSR_ATOMCTL,
  18217   OPCODE_WSR_ATOMCTL,
  18218   OPCODE_XSR_ATOMCTL,
  18219   OPCODE_QUOS,
  18220   OPCODE_QUOU,
  18221   OPCODE_REMS,
  18222   OPCODE_REMU,
  18223   OPCODE_RSR_ERACCESS,
  18224   OPCODE_WSR_ERACCESS,
  18225   OPCODE_XSR_ERACCESS,
  18226   OPCODE_RER,
  18227   OPCODE_WER,
  18228   OPCODE_RUR_FCR,
  18229   OPCODE_WUR_FCR,
  18230   OPCODE_RUR_FSR,
  18231   OPCODE_WUR_FSR,
  18232   OPCODE_READ_IMPWIRE,
  18233   OPCODE_SETB_EXPSTATE,
  18234   OPCODE_CLRB_EXPSTATE,
  18235   OPCODE_WRMSK_EXPSTATE,
  18236   OPCODE_RUR_EXPSTATE,
  18237   OPCODE_WUR_EXPSTATE,
  18238   OPCODE_LSI,
  18239   OPCODE_LSIP,
  18240   OPCODE_LSX,
  18241   OPCODE_LSXP,
  18242   OPCODE_SSI,
  18243   OPCODE_SSIP,
  18244   OPCODE_SSX,
  18245   OPCODE_SSXP,
  18246   OPCODE_LDI,
  18247   OPCODE_LDIP,
  18248   OPCODE_LDX,
  18249   OPCODE_LDXP,
  18250   OPCODE_SDI,
  18251   OPCODE_SDIP,
  18252   OPCODE_SDX,
  18253   OPCODE_SDXP,
  18254   OPCODE_ABS_S,
  18255   OPCODE_NEG_S,
  18256   OPCODE_ABS_D,
  18257   OPCODE_NEG_D,
  18258   OPCODE_MOV_S,
  18259   OPCODE_MOV_D,
  18260   OPCODE_MOVEQZ_S,
  18261   OPCODE_MOVNEZ_S,
  18262   OPCODE_MOVLTZ_S,
  18263   OPCODE_MOVGEZ_S,
  18264   OPCODE_MOVF_S,
  18265   OPCODE_MOVT_S,
  18266   OPCODE_WFR,
  18267   OPCODE_RFR,
  18268   OPCODE_RFRD,
  18269   OPCODE_WFRD,
  18270   OPCODE_ROUND_S,
  18271   OPCODE_ROUND_D,
  18272   OPCODE_CEIL_S,
  18273   OPCODE_CEIL_D,
  18274   OPCODE_FLOOR_S,
  18275   OPCODE_FLOOR_D,
  18276   OPCODE_TRUNC_S,
  18277   OPCODE_TRUNC_D,
  18278   OPCODE_UTRUNC_S,
  18279   OPCODE_UTRUNC_D,
  18280   OPCODE_FLOAT_S,
  18281   OPCODE_FLOAT_D,
  18282   OPCODE_UFLOAT_S,
  18283   OPCODE_UFLOAT_D,
  18284   OPCODE_CVTD_S,
  18285   OPCODE_CVTS_D,
  18286   OPCODE_UN_S,
  18287   OPCODE_UN_D,
  18288   OPCODE_ULT_S,
  18289   OPCODE_ULT_D,
  18290   OPCODE_ULE_S,
  18291   OPCODE_ULE_D,
  18292   OPCODE_UEQ_S,
  18293   OPCODE_UEQ_D,
  18294   OPCODE_OLT_S,
  18295   OPCODE_OLT_D,
  18296   OPCODE_OLE_S,
  18297   OPCODE_OLE_D,
  18298   OPCODE_OEQ_S,
  18299   OPCODE_OEQ_D,
  18300   OPCODE_ADD_S,
  18301   OPCODE_ADD_D,
  18302   OPCODE_SUB_S,
  18303   OPCODE_SUB_D,
  18304   OPCODE_MUL_S,
  18305   OPCODE_MUL_D,
  18306   OPCODE_MADD_S,
  18307   OPCODE_MADD_D,
  18308   OPCODE_MSUB_S,
  18309   OPCODE_MSUB_D,
  18310   OPCODE_SQRT0_S,
  18311   OPCODE_SQRT0_D,
  18312   OPCODE_DIV0_S,
  18313   OPCODE_DIV0_D,
  18314   OPCODE_RECIP0_S,
  18315   OPCODE_RECIP0_D,
  18316   OPCODE_RSQRT0_S,
  18317   OPCODE_RSQRT0_D,
  18318   OPCODE_MADDN_S,
  18319   OPCODE_MADDN_D,
  18320   OPCODE_DIVN_S,
  18321   OPCODE_DIVN_D,
  18322   OPCODE_CONST_S,
  18323   OPCODE_CONST_D,
  18324   OPCODE_NEXP01_S,
  18325   OPCODE_NEXP01_D,
  18326   OPCODE_ADDEXP_S,
  18327   OPCODE_ADDEXP_D,
  18328   OPCODE_ADDEXPM_S,
  18329   OPCODE_ADDEXPM_D,
  18330   OPCODE_MKDADJ_S,
  18331   OPCODE_MKDADJ_D,
  18332   OPCODE_MKSADJ_S,
  18333   OPCODE_MKSADJ_D
  18334 };
  18335 
  18336 
  18337 /* Slot-specific opcode decode functions.  */
  18338 
  18339 static int
  18340 Slot_inst_decode (const xtensa_insnbuf insn)
  18341 {
  18342   if (Field_op0_Slot_inst_get (insn) == 0)
  18343     {
  18344       if (Field_op1_Slot_inst_get (insn) == 0)
  18345 	{
  18346 	  if (Field_op2_Slot_inst_get (insn) == 0)
  18347 	    {
  18348 	      if (Field_r_Slot_inst_get (insn) == 0)
  18349 		{
  18350 		  if (Field_m_Slot_inst_get (insn) == 0 &&
  18351 		      Field_s_Slot_inst_get (insn) == 0 &&
  18352 		      Field_n_Slot_inst_get (insn) == 0)
  18353 		    return OPCODE_ILL;
  18354 		  if (Field_m_Slot_inst_get (insn) == 2)
  18355 		    {
  18356 		      if (Field_n_Slot_inst_get (insn) == 0)
  18357 			return OPCODE_RET;
  18358 		      if (Field_n_Slot_inst_get (insn) == 1)
  18359 			return OPCODE_RETW;
  18360 		      if (Field_n_Slot_inst_get (insn) == 2)
  18361 			return OPCODE_JX;
  18362 		    }
  18363 		  if (Field_m_Slot_inst_get (insn) == 3)
  18364 		    {
  18365 		      if (Field_n_Slot_inst_get (insn) == 0)
  18366 			return OPCODE_CALLX0;
  18367 		      if (Field_n_Slot_inst_get (insn) == 1)
  18368 			return OPCODE_CALLX4;
  18369 		      if (Field_n_Slot_inst_get (insn) == 2)
  18370 			return OPCODE_CALLX8;
  18371 		      if (Field_n_Slot_inst_get (insn) == 3)
  18372 			return OPCODE_CALLX12;
  18373 		    }
  18374 		}
  18375 	      if (Field_r_Slot_inst_get (insn) == 1)
  18376 		return OPCODE_MOVSP;
  18377 	      if (Field_r_Slot_inst_get (insn) == 2)
  18378 		{
  18379 		  if (Field_s_Slot_inst_get (insn) == 0)
  18380 		    {
  18381 		      if (Field_t_Slot_inst_get (insn) == 0)
  18382 			return OPCODE_ISYNC;
  18383 		      if (Field_t_Slot_inst_get (insn) == 1)
  18384 			return OPCODE_RSYNC;
  18385 		      if (Field_t_Slot_inst_get (insn) == 2)
  18386 			return OPCODE_ESYNC;
  18387 		      if (Field_t_Slot_inst_get (insn) == 3)
  18388 			return OPCODE_DSYNC;
  18389 		      if (Field_t_Slot_inst_get (insn) == 8)
  18390 			return OPCODE_EXCW;
  18391 		      if (Field_t_Slot_inst_get (insn) == 12)
  18392 			return OPCODE_MEMW;
  18393 		      if (Field_t_Slot_inst_get (insn) == 13)
  18394 			return OPCODE_EXTW;
  18395 		      if (Field_t_Slot_inst_get (insn) == 15)
  18396 			return OPCODE_NOP;
  18397 		    }
  18398 		}
  18399 	      if (Field_r_Slot_inst_get (insn) == 3)
  18400 		{
  18401 		  if (Field_t_Slot_inst_get (insn) == 0)
  18402 		    {
  18403 		      if (Field_s_Slot_inst_get (insn) == 0)
  18404 			return OPCODE_RFE;
  18405 		      if (Field_s_Slot_inst_get (insn) == 2)
  18406 			return OPCODE_RFDE;
  18407 		      if (Field_s_Slot_inst_get (insn) == 4)
  18408 			return OPCODE_RFWO;
  18409 		      if (Field_s_Slot_inst_get (insn) == 5)
  18410 			return OPCODE_RFWU;
  18411 		    }
  18412 		  if (Field_t_Slot_inst_get (insn) == 1)
  18413 		    return OPCODE_RFI;
  18414 		}
  18415 	      if (Field_r_Slot_inst_get (insn) == 4)
  18416 		return OPCODE_BREAK;
  18417 	      if (Field_r_Slot_inst_get (insn) == 5)
  18418 		{
  18419 		  if (Field_s_Slot_inst_get (insn) == 0 &&
  18420 		      Field_t_Slot_inst_get (insn) == 0)
  18421 		    return OPCODE_SYSCALL;
  18422 		  if (Field_s_Slot_inst_get (insn) == 1)
  18423 		    return OPCODE_SIMCALL;
  18424 		}
  18425 	      if (Field_r_Slot_inst_get (insn) == 6)
  18426 		return OPCODE_RSIL;
  18427 	      if (Field_r_Slot_inst_get (insn) == 7 &&
  18428 		  Field_t_Slot_inst_get (insn) == 0)
  18429 		return OPCODE_WAITI;
  18430 	      if (Field_r_Slot_inst_get (insn) == 7)
  18431 		{
  18432 		  if (Field_t_Slot_inst_get (insn) == 14)
  18433 		    return OPCODE_LDDR32_P;
  18434 		  if (Field_t_Slot_inst_get (insn) == 15)
  18435 		    return OPCODE_SDDR32_P;
  18436 		}
  18437 	      if (Field_r_Slot_inst_get (insn) == 8)
  18438 		return OPCODE_ANY4;
  18439 	      if (Field_r_Slot_inst_get (insn) == 9)
  18440 		return OPCODE_ALL4;
  18441 	      if (Field_r_Slot_inst_get (insn) == 10)
  18442 		return OPCODE_ANY8;
  18443 	      if (Field_r_Slot_inst_get (insn) == 11)
  18444 		return OPCODE_ALL8;
  18445 	    }
  18446 	  if (Field_op2_Slot_inst_get (insn) == 1)
  18447 	    return OPCODE_AND;
  18448 	  if (Field_op2_Slot_inst_get (insn) == 2)
  18449 	    return OPCODE_OR;
  18450 	  if (Field_op2_Slot_inst_get (insn) == 3)
  18451 	    return OPCODE_XOR;
  18452 	  if (Field_op2_Slot_inst_get (insn) == 4)
  18453 	    {
  18454 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  18455 		  Field_t_Slot_inst_get (insn) == 0)
  18456 		return OPCODE_SSR;
  18457 	      if (Field_r_Slot_inst_get (insn) == 1 &&
  18458 		  Field_t_Slot_inst_get (insn) == 0)
  18459 		return OPCODE_SSL;
  18460 	      if (Field_r_Slot_inst_get (insn) == 2 &&
  18461 		  Field_t_Slot_inst_get (insn) == 0)
  18462 		return OPCODE_SSA8L;
  18463 	      if (Field_r_Slot_inst_get (insn) == 3 &&
  18464 		  Field_t_Slot_inst_get (insn) == 0)
  18465 		return OPCODE_SSA8B;
  18466 	      if (Field_r_Slot_inst_get (insn) == 4 &&
  18467 		  Field_thi3_Slot_inst_get (insn) == 0)
  18468 		return OPCODE_SSAI;
  18469 	      if (Field_r_Slot_inst_get (insn) == 6)
  18470 		return OPCODE_RER;
  18471 	      if (Field_r_Slot_inst_get (insn) == 7)
  18472 		return OPCODE_WER;
  18473 	      if (Field_r_Slot_inst_get (insn) == 8 &&
  18474 		  Field_s_Slot_inst_get (insn) == 0)
  18475 		return OPCODE_ROTW;
  18476 	      if (Field_r_Slot_inst_get (insn) == 14)
  18477 		return OPCODE_NSA;
  18478 	      if (Field_r_Slot_inst_get (insn) == 15)
  18479 		return OPCODE_NSAU;
  18480 	    }
  18481 	  if (Field_op2_Slot_inst_get (insn) == 5)
  18482 	    {
  18483 	      if (Field_r_Slot_inst_get (insn) == 1)
  18484 		return OPCODE_HWWITLBA;
  18485 	      if (Field_r_Slot_inst_get (insn) == 3)
  18486 		return OPCODE_RITLB0;
  18487 	      if (Field_r_Slot_inst_get (insn) == 4 &&
  18488 		  Field_t_Slot_inst_get (insn) == 0)
  18489 		return OPCODE_IITLB;
  18490 	      if (Field_r_Slot_inst_get (insn) == 5)
  18491 		return OPCODE_PITLB;
  18492 	      if (Field_r_Slot_inst_get (insn) == 6)
  18493 		return OPCODE_WITLB;
  18494 	      if (Field_r_Slot_inst_get (insn) == 7)
  18495 		return OPCODE_RITLB1;
  18496 	      if (Field_r_Slot_inst_get (insn) == 9)
  18497 		return OPCODE_HWWDTLBA;
  18498 	      if (Field_r_Slot_inst_get (insn) == 11)
  18499 		return OPCODE_RDTLB0;
  18500 	      if (Field_r_Slot_inst_get (insn) == 12 &&
  18501 		  Field_t_Slot_inst_get (insn) == 0)
  18502 		return OPCODE_IDTLB;
  18503 	      if (Field_r_Slot_inst_get (insn) == 13)
  18504 		return OPCODE_PDTLB;
  18505 	      if (Field_r_Slot_inst_get (insn) == 14)
  18506 		return OPCODE_WDTLB;
  18507 	      if (Field_r_Slot_inst_get (insn) == 15)
  18508 		return OPCODE_RDTLB1;
  18509 	    }
  18510 	  if (Field_op2_Slot_inst_get (insn) == 6)
  18511 	    {
  18512 	      if (Field_s_Slot_inst_get (insn) == 0)
  18513 		return OPCODE_NEG;
  18514 	      if (Field_s_Slot_inst_get (insn) == 1)
  18515 		return OPCODE_ABS;
  18516 	    }
  18517 	  if (Field_op2_Slot_inst_get (insn) == 8)
  18518 	    return OPCODE_ADD;
  18519 	  if (Field_op2_Slot_inst_get (insn) == 9)
  18520 	    return OPCODE_ADDX2;
  18521 	  if (Field_op2_Slot_inst_get (insn) == 10)
  18522 	    return OPCODE_ADDX4;
  18523 	  if (Field_op2_Slot_inst_get (insn) == 11)
  18524 	    return OPCODE_ADDX8;
  18525 	  if (Field_op2_Slot_inst_get (insn) == 12)
  18526 	    return OPCODE_SUB;
  18527 	  if (Field_op2_Slot_inst_get (insn) == 13)
  18528 	    return OPCODE_SUBX2;
  18529 	  if (Field_op2_Slot_inst_get (insn) == 14)
  18530 	    return OPCODE_SUBX4;
  18531 	  if (Field_op2_Slot_inst_get (insn) == 15)
  18532 	    return OPCODE_SUBX8;
  18533 	}
  18534       if (Field_op1_Slot_inst_get (insn) == 1)
  18535 	{
  18536 	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
  18537 	       Field_op2_Slot_inst_get (insn) == 1))
  18538 	    return OPCODE_SLLI;
  18539 	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
  18540 	       Field_op2_Slot_inst_get (insn) == 3))
  18541 	    return OPCODE_SRAI;
  18542 	  if (Field_op2_Slot_inst_get (insn) == 4)
  18543 	    return OPCODE_SRLI;
  18544 	  if (Field_op2_Slot_inst_get (insn) == 6)
  18545 	    {
  18546 	      if (Field_sr_Slot_inst_get (insn) == 0)
  18547 		return OPCODE_XSR_LBEG;
  18548 	      if (Field_sr_Slot_inst_get (insn) == 1)
  18549 		return OPCODE_XSR_LEND;
  18550 	      if (Field_sr_Slot_inst_get (insn) == 2)
  18551 		return OPCODE_XSR_LCOUNT;
  18552 	      if (Field_sr_Slot_inst_get (insn) == 3)
  18553 		return OPCODE_XSR_SAR;
  18554 	      if (Field_sr_Slot_inst_get (insn) == 4)
  18555 		return OPCODE_XSR_BR;
  18556 	      if (Field_sr_Slot_inst_get (insn) == 12)
  18557 		return OPCODE_XSR_SCOMPARE1;
  18558 	      if (Field_sr_Slot_inst_get (insn) == 16)
  18559 		return OPCODE_XSR_ACCLO;
  18560 	      if (Field_sr_Slot_inst_get (insn) == 17)
  18561 		return OPCODE_XSR_ACCHI;
  18562 	      if (Field_sr_Slot_inst_get (insn) == 32)
  18563 		return OPCODE_XSR_M0;
  18564 	      if (Field_sr_Slot_inst_get (insn) == 33)
  18565 		return OPCODE_XSR_M1;
  18566 	      if (Field_sr_Slot_inst_get (insn) == 34)
  18567 		return OPCODE_XSR_M2;
  18568 	      if (Field_sr_Slot_inst_get (insn) == 35)
  18569 		return OPCODE_XSR_M3;
  18570 	      if (Field_sr_Slot_inst_get (insn) == 72)
  18571 		return OPCODE_XSR_WINDOWBASE;
  18572 	      if (Field_sr_Slot_inst_get (insn) == 73)
  18573 		return OPCODE_XSR_WINDOWSTART;
  18574 	      if (Field_sr_Slot_inst_get (insn) == 83)
  18575 		return OPCODE_XSR_PTEVADDR;
  18576 	      if (Field_sr_Slot_inst_get (insn) == 90)
  18577 		return OPCODE_XSR_RASID;
  18578 	      if (Field_sr_Slot_inst_get (insn) == 91)
  18579 		return OPCODE_XSR_ITLBCFG;
  18580 	      if (Field_sr_Slot_inst_get (insn) == 92)
  18581 		return OPCODE_XSR_DTLBCFG;
  18582 	      if (Field_sr_Slot_inst_get (insn) == 95)
  18583 		return OPCODE_XSR_ERACCESS;
  18584 	      if (Field_sr_Slot_inst_get (insn) == 96)
  18585 		return OPCODE_XSR_IBREAKENABLE;
  18586 	      if (Field_sr_Slot_inst_get (insn) == 97)
  18587 		return OPCODE_XSR_MEMCTL;
  18588 	      if (Field_sr_Slot_inst_get (insn) == 99)
  18589 		return OPCODE_XSR_ATOMCTL;
  18590 	      if (Field_sr_Slot_inst_get (insn) == 104)
  18591 		return OPCODE_XSR_DDR;
  18592 	      if (Field_sr_Slot_inst_get (insn) == 128)
  18593 		return OPCODE_XSR_IBREAKA0;
  18594 	      if (Field_sr_Slot_inst_get (insn) == 129)
  18595 		return OPCODE_XSR_IBREAKA1;
  18596 	      if (Field_sr_Slot_inst_get (insn) == 144)
  18597 		return OPCODE_XSR_DBREAKA0;
  18598 	      if (Field_sr_Slot_inst_get (insn) == 145)
  18599 		return OPCODE_XSR_DBREAKA1;
  18600 	      if (Field_sr_Slot_inst_get (insn) == 160)
  18601 		return OPCODE_XSR_DBREAKC0;
  18602 	      if (Field_sr_Slot_inst_get (insn) == 161)
  18603 		return OPCODE_XSR_DBREAKC1;
  18604 	      if (Field_sr_Slot_inst_get (insn) == 177)
  18605 		return OPCODE_XSR_EPC1;
  18606 	      if (Field_sr_Slot_inst_get (insn) == 178)
  18607 		return OPCODE_XSR_EPC2;
  18608 	      if (Field_sr_Slot_inst_get (insn) == 179)
  18609 		return OPCODE_XSR_EPC3;
  18610 	      if (Field_sr_Slot_inst_get (insn) == 180)
  18611 		return OPCODE_XSR_EPC4;
  18612 	      if (Field_sr_Slot_inst_get (insn) == 181)
  18613 		return OPCODE_XSR_EPC5;
  18614 	      if (Field_sr_Slot_inst_get (insn) == 182)
  18615 		return OPCODE_XSR_EPC6;
  18616 	      if (Field_sr_Slot_inst_get (insn) == 183)
  18617 		return OPCODE_XSR_EPC7;
  18618 	      if (Field_sr_Slot_inst_get (insn) == 192)
  18619 		return OPCODE_XSR_DEPC;
  18620 	      if (Field_sr_Slot_inst_get (insn) == 194)
  18621 		return OPCODE_XSR_EPS2;
  18622 	      if (Field_sr_Slot_inst_get (insn) == 195)
  18623 		return OPCODE_XSR_EPS3;
  18624 	      if (Field_sr_Slot_inst_get (insn) == 196)
  18625 		return OPCODE_XSR_EPS4;
  18626 	      if (Field_sr_Slot_inst_get (insn) == 197)
  18627 		return OPCODE_XSR_EPS5;
  18628 	      if (Field_sr_Slot_inst_get (insn) == 198)
  18629 		return OPCODE_XSR_EPS6;
  18630 	      if (Field_sr_Slot_inst_get (insn) == 199)
  18631 		return OPCODE_XSR_EPS7;
  18632 	      if (Field_sr_Slot_inst_get (insn) == 209)
  18633 		return OPCODE_XSR_EXCSAVE1;
  18634 	      if (Field_sr_Slot_inst_get (insn) == 210)
  18635 		return OPCODE_XSR_EXCSAVE2;
  18636 	      if (Field_sr_Slot_inst_get (insn) == 211)
  18637 		return OPCODE_XSR_EXCSAVE3;
  18638 	      if (Field_sr_Slot_inst_get (insn) == 212)
  18639 		return OPCODE_XSR_EXCSAVE4;
  18640 	      if (Field_sr_Slot_inst_get (insn) == 213)
  18641 		return OPCODE_XSR_EXCSAVE5;
  18642 	      if (Field_sr_Slot_inst_get (insn) == 214)
  18643 		return OPCODE_XSR_EXCSAVE6;
  18644 	      if (Field_sr_Slot_inst_get (insn) == 215)
  18645 		return OPCODE_XSR_EXCSAVE7;
  18646 	      if (Field_sr_Slot_inst_get (insn) == 224)
  18647 		return OPCODE_XSR_CPENABLE;
  18648 	      if (Field_sr_Slot_inst_get (insn) == 228)
  18649 		return OPCODE_XSR_INTENABLE;
  18650 	      if (Field_sr_Slot_inst_get (insn) == 230)
  18651 		return OPCODE_XSR_PS;
  18652 	      if (Field_sr_Slot_inst_get (insn) == 231)
  18653 		return OPCODE_XSR_VECBASE;
  18654 	      if (Field_sr_Slot_inst_get (insn) == 232)
  18655 		return OPCODE_XSR_EXCCAUSE;
  18656 	      if (Field_sr_Slot_inst_get (insn) == 233)
  18657 		return OPCODE_XSR_DEBUGCAUSE;
  18658 	      if (Field_sr_Slot_inst_get (insn) == 234)
  18659 		return OPCODE_XSR_CCOUNT;
  18660 	      if (Field_sr_Slot_inst_get (insn) == 236)
  18661 		return OPCODE_XSR_ICOUNT;
  18662 	      if (Field_sr_Slot_inst_get (insn) == 237)
  18663 		return OPCODE_XSR_ICOUNTLEVEL;
  18664 	      if (Field_sr_Slot_inst_get (insn) == 238)
  18665 		return OPCODE_XSR_EXCVADDR;
  18666 	      if (Field_sr_Slot_inst_get (insn) == 240)
  18667 		return OPCODE_XSR_CCOMPARE0;
  18668 	      if (Field_sr_Slot_inst_get (insn) == 241)
  18669 		return OPCODE_XSR_CCOMPARE1;
  18670 	      if (Field_sr_Slot_inst_get (insn) == 242)
  18671 		return OPCODE_XSR_CCOMPARE2;
  18672 	      if (Field_sr_Slot_inst_get (insn) == 244)
  18673 		return OPCODE_XSR_MISC0;
  18674 	      if (Field_sr_Slot_inst_get (insn) == 245)
  18675 		return OPCODE_XSR_MISC1;
  18676 	    }
  18677 	  if (Field_op2_Slot_inst_get (insn) == 8)
  18678 	    return OPCODE_SRC;
  18679 	  if (Field_op2_Slot_inst_get (insn) == 9 &&
  18680 	      Field_s_Slot_inst_get (insn) == 0)
  18681 	    return OPCODE_SRL;
  18682 	  if (Field_op2_Slot_inst_get (insn) == 10 &&
  18683 	      Field_t_Slot_inst_get (insn) == 0)
  18684 	    return OPCODE_SLL;
  18685 	  if (Field_op2_Slot_inst_get (insn) == 11 &&
  18686 	      Field_s_Slot_inst_get (insn) == 0)
  18687 	    return OPCODE_SRA;
  18688 	  if (Field_op2_Slot_inst_get (insn) == 12)
  18689 	    return OPCODE_MUL16U;
  18690 	  if (Field_op2_Slot_inst_get (insn) == 13)
  18691 	    return OPCODE_MUL16S;
  18692 	  if (Field_op2_Slot_inst_get (insn) == 15)
  18693 	    {
  18694 	      if (Field_r_Slot_inst_get (insn) == 0)
  18695 		return OPCODE_LICT;
  18696 	      if (Field_r_Slot_inst_get (insn) == 1)
  18697 		return OPCODE_SICT;
  18698 	      if (Field_r_Slot_inst_get (insn) == 2)
  18699 		return OPCODE_LICW;
  18700 	      if (Field_r_Slot_inst_get (insn) == 3)
  18701 		return OPCODE_SICW;
  18702 	      if (Field_r_Slot_inst_get (insn) == 8)
  18703 		return OPCODE_LDCT;
  18704 	      if (Field_r_Slot_inst_get (insn) == 9)
  18705 		return OPCODE_SDCT;
  18706 	      if (Field_r_Slot_inst_get (insn) == 10)
  18707 		return OPCODE_LDCW;
  18708 	      if (Field_r_Slot_inst_get (insn) == 11)
  18709 		return OPCODE_SDCW;
  18710 	      if (Field_r_Slot_inst_get (insn) == 14 &&
  18711 		  Field_t_Slot_inst_get (insn) == 0)
  18712 		return OPCODE_RFDO;
  18713 	      if (Field_r_Slot_inst_get (insn) == 14 &&
  18714 		  Field_t_Slot_inst_get (insn) == 1)
  18715 		return OPCODE_RFDD;
  18716 	      if (Field_r_Slot_inst_get (insn) == 15)
  18717 		return OPCODE_LDPTE;
  18718 	    }
  18719 	}
  18720       if (Field_op1_Slot_inst_get (insn) == 2)
  18721 	{
  18722 	  if (Field_op2_Slot_inst_get (insn) == 0)
  18723 	    return OPCODE_ANDB;
  18724 	  if (Field_op2_Slot_inst_get (insn) == 1)
  18725 	    return OPCODE_ANDBC;
  18726 	  if (Field_op2_Slot_inst_get (insn) == 2)
  18727 	    return OPCODE_ORB;
  18728 	  if (Field_op2_Slot_inst_get (insn) == 3)
  18729 	    return OPCODE_ORBC;
  18730 	  if (Field_op2_Slot_inst_get (insn) == 4)
  18731 	    return OPCODE_XORB;
  18732 	  if (Field_op2_Slot_inst_get (insn) == 6)
  18733 	    return OPCODE_SALTU;
  18734 	  if (Field_op2_Slot_inst_get (insn) == 7)
  18735 	    return OPCODE_SALT;
  18736 	  if (Field_op2_Slot_inst_get (insn) == 8)
  18737 	    return OPCODE_MULL;
  18738 	  if (Field_op2_Slot_inst_get (insn) == 12)
  18739 	    return OPCODE_QUOU;
  18740 	  if (Field_op2_Slot_inst_get (insn) == 13)
  18741 	    return OPCODE_QUOS;
  18742 	  if (Field_op2_Slot_inst_get (insn) == 14)
  18743 	    return OPCODE_REMU;
  18744 	  if (Field_op2_Slot_inst_get (insn) == 15)
  18745 	    return OPCODE_REMS;
  18746 	}
  18747       if (Field_op1_Slot_inst_get (insn) == 3)
  18748 	{
  18749 	  if (Field_op2_Slot_inst_get (insn) == 0)
  18750 	    {
  18751 	      if (Field_sr_Slot_inst_get (insn) == 0)
  18752 		return OPCODE_RSR_LBEG;
  18753 	      if (Field_sr_Slot_inst_get (insn) == 1)
  18754 		return OPCODE_RSR_LEND;
  18755 	      if (Field_sr_Slot_inst_get (insn) == 2)
  18756 		return OPCODE_RSR_LCOUNT;
  18757 	      if (Field_sr_Slot_inst_get (insn) == 3)
  18758 		return OPCODE_RSR_SAR;
  18759 	      if (Field_sr_Slot_inst_get (insn) == 4)
  18760 		return OPCODE_RSR_BR;
  18761 	      if (Field_sr_Slot_inst_get (insn) == 12)
  18762 		return OPCODE_RSR_SCOMPARE1;
  18763 	      if (Field_sr_Slot_inst_get (insn) == 16)
  18764 		return OPCODE_RSR_ACCLO;
  18765 	      if (Field_sr_Slot_inst_get (insn) == 17)
  18766 		return OPCODE_RSR_ACCHI;
  18767 	      if (Field_sr_Slot_inst_get (insn) == 32)
  18768 		return OPCODE_RSR_M0;
  18769 	      if (Field_sr_Slot_inst_get (insn) == 33)
  18770 		return OPCODE_RSR_M1;
  18771 	      if (Field_sr_Slot_inst_get (insn) == 34)
  18772 		return OPCODE_RSR_M2;
  18773 	      if (Field_sr_Slot_inst_get (insn) == 35)
  18774 		return OPCODE_RSR_M3;
  18775 	      if (Field_sr_Slot_inst_get (insn) == 72)
  18776 		return OPCODE_RSR_WINDOWBASE;
  18777 	      if (Field_sr_Slot_inst_get (insn) == 73)
  18778 		return OPCODE_RSR_WINDOWSTART;
  18779 	      if (Field_sr_Slot_inst_get (insn) == 83)
  18780 		return OPCODE_RSR_PTEVADDR;
  18781 	      if (Field_sr_Slot_inst_get (insn) == 90)
  18782 		return OPCODE_RSR_RASID;
  18783 	      if (Field_sr_Slot_inst_get (insn) == 91)
  18784 		return OPCODE_RSR_ITLBCFG;
  18785 	      if (Field_sr_Slot_inst_get (insn) == 92)
  18786 		return OPCODE_RSR_DTLBCFG;
  18787 	      if (Field_sr_Slot_inst_get (insn) == 95)
  18788 		return OPCODE_RSR_ERACCESS;
  18789 	      if (Field_sr_Slot_inst_get (insn) == 96)
  18790 		return OPCODE_RSR_IBREAKENABLE;
  18791 	      if (Field_sr_Slot_inst_get (insn) == 97)
  18792 		return OPCODE_RSR_MEMCTL;
  18793 	      if (Field_sr_Slot_inst_get (insn) == 99)
  18794 		return OPCODE_RSR_ATOMCTL;
  18795 	      if (Field_sr_Slot_inst_get (insn) == 104)
  18796 		return OPCODE_RSR_DDR;
  18797 	      if (Field_sr_Slot_inst_get (insn) == 128)
  18798 		return OPCODE_RSR_IBREAKA0;
  18799 	      if (Field_sr_Slot_inst_get (insn) == 129)
  18800 		return OPCODE_RSR_IBREAKA1;
  18801 	      if (Field_sr_Slot_inst_get (insn) == 144)
  18802 		return OPCODE_RSR_DBREAKA0;
  18803 	      if (Field_sr_Slot_inst_get (insn) == 145)
  18804 		return OPCODE_RSR_DBREAKA1;
  18805 	      if (Field_sr_Slot_inst_get (insn) == 160)
  18806 		return OPCODE_RSR_DBREAKC0;
  18807 	      if (Field_sr_Slot_inst_get (insn) == 161)
  18808 		return OPCODE_RSR_DBREAKC1;
  18809 	      if (Field_sr_Slot_inst_get (insn) == 176)
  18810 		return OPCODE_RSR_CONFIGID0;
  18811 	      if (Field_sr_Slot_inst_get (insn) == 177)
  18812 		return OPCODE_RSR_EPC1;
  18813 	      if (Field_sr_Slot_inst_get (insn) == 178)
  18814 		return OPCODE_RSR_EPC2;
  18815 	      if (Field_sr_Slot_inst_get (insn) == 179)
  18816 		return OPCODE_RSR_EPC3;
  18817 	      if (Field_sr_Slot_inst_get (insn) == 180)
  18818 		return OPCODE_RSR_EPC4;
  18819 	      if (Field_sr_Slot_inst_get (insn) == 181)
  18820 		return OPCODE_RSR_EPC5;
  18821 	      if (Field_sr_Slot_inst_get (insn) == 182)
  18822 		return OPCODE_RSR_EPC6;
  18823 	      if (Field_sr_Slot_inst_get (insn) == 183)
  18824 		return OPCODE_RSR_EPC7;
  18825 	      if (Field_sr_Slot_inst_get (insn) == 192)
  18826 		return OPCODE_RSR_DEPC;
  18827 	      if (Field_sr_Slot_inst_get (insn) == 194)
  18828 		return OPCODE_RSR_EPS2;
  18829 	      if (Field_sr_Slot_inst_get (insn) == 195)
  18830 		return OPCODE_RSR_EPS3;
  18831 	      if (Field_sr_Slot_inst_get (insn) == 196)
  18832 		return OPCODE_RSR_EPS4;
  18833 	      if (Field_sr_Slot_inst_get (insn) == 197)
  18834 		return OPCODE_RSR_EPS5;
  18835 	      if (Field_sr_Slot_inst_get (insn) == 198)
  18836 		return OPCODE_RSR_EPS6;
  18837 	      if (Field_sr_Slot_inst_get (insn) == 199)
  18838 		return OPCODE_RSR_EPS7;
  18839 	      if (Field_sr_Slot_inst_get (insn) == 208)
  18840 		return OPCODE_RSR_CONFIGID1;
  18841 	      if (Field_sr_Slot_inst_get (insn) == 209)
  18842 		return OPCODE_RSR_EXCSAVE1;
  18843 	      if (Field_sr_Slot_inst_get (insn) == 210)
  18844 		return OPCODE_RSR_EXCSAVE2;
  18845 	      if (Field_sr_Slot_inst_get (insn) == 211)
  18846 		return OPCODE_RSR_EXCSAVE3;
  18847 	      if (Field_sr_Slot_inst_get (insn) == 212)
  18848 		return OPCODE_RSR_EXCSAVE4;
  18849 	      if (Field_sr_Slot_inst_get (insn) == 213)
  18850 		return OPCODE_RSR_EXCSAVE5;
  18851 	      if (Field_sr_Slot_inst_get (insn) == 214)
  18852 		return OPCODE_RSR_EXCSAVE6;
  18853 	      if (Field_sr_Slot_inst_get (insn) == 215)
  18854 		return OPCODE_RSR_EXCSAVE7;
  18855 	      if (Field_sr_Slot_inst_get (insn) == 224)
  18856 		return OPCODE_RSR_CPENABLE;
  18857 	      if (Field_sr_Slot_inst_get (insn) == 226)
  18858 		return OPCODE_RSR_INTERRUPT;
  18859 	      if (Field_sr_Slot_inst_get (insn) == 228)
  18860 		return OPCODE_RSR_INTENABLE;
  18861 	      if (Field_sr_Slot_inst_get (insn) == 230)
  18862 		return OPCODE_RSR_PS;
  18863 	      if (Field_sr_Slot_inst_get (insn) == 231)
  18864 		return OPCODE_RSR_VECBASE;
  18865 	      if (Field_sr_Slot_inst_get (insn) == 232)
  18866 		return OPCODE_RSR_EXCCAUSE;
  18867 	      if (Field_sr_Slot_inst_get (insn) == 233)
  18868 		return OPCODE_RSR_DEBUGCAUSE;
  18869 	      if (Field_sr_Slot_inst_get (insn) == 234)
  18870 		return OPCODE_RSR_CCOUNT;
  18871 	      if (Field_sr_Slot_inst_get (insn) == 235)
  18872 		return OPCODE_RSR_PRID;
  18873 	      if (Field_sr_Slot_inst_get (insn) == 236)
  18874 		return OPCODE_RSR_ICOUNT;
  18875 	      if (Field_sr_Slot_inst_get (insn) == 237)
  18876 		return OPCODE_RSR_ICOUNTLEVEL;
  18877 	      if (Field_sr_Slot_inst_get (insn) == 238)
  18878 		return OPCODE_RSR_EXCVADDR;
  18879 	      if (Field_sr_Slot_inst_get (insn) == 240)
  18880 		return OPCODE_RSR_CCOMPARE0;
  18881 	      if (Field_sr_Slot_inst_get (insn) == 241)
  18882 		return OPCODE_RSR_CCOMPARE1;
  18883 	      if (Field_sr_Slot_inst_get (insn) == 242)
  18884 		return OPCODE_RSR_CCOMPARE2;
  18885 	      if (Field_sr_Slot_inst_get (insn) == 244)
  18886 		return OPCODE_RSR_MISC0;
  18887 	      if (Field_sr_Slot_inst_get (insn) == 245)
  18888 		return OPCODE_RSR_MISC1;
  18889 	    }
  18890 	  if (Field_op2_Slot_inst_get (insn) == 1)
  18891 	    {
  18892 	      if (Field_sr_Slot_inst_get (insn) == 0)
  18893 		return OPCODE_WSR_LBEG;
  18894 	      if (Field_sr_Slot_inst_get (insn) == 1)
  18895 		return OPCODE_WSR_LEND;
  18896 	      if (Field_sr_Slot_inst_get (insn) == 2)
  18897 		return OPCODE_WSR_LCOUNT;
  18898 	      if (Field_sr_Slot_inst_get (insn) == 3)
  18899 		return OPCODE_WSR_SAR;
  18900 	      if (Field_sr_Slot_inst_get (insn) == 4)
  18901 		return OPCODE_WSR_BR;
  18902 	      if (Field_sr_Slot_inst_get (insn) == 12)
  18903 		return OPCODE_WSR_SCOMPARE1;
  18904 	      if (Field_sr_Slot_inst_get (insn) == 16)
  18905 		return OPCODE_WSR_ACCLO;
  18906 	      if (Field_sr_Slot_inst_get (insn) == 17)
  18907 		return OPCODE_WSR_ACCHI;
  18908 	      if (Field_sr_Slot_inst_get (insn) == 32)
  18909 		return OPCODE_WSR_M0;
  18910 	      if (Field_sr_Slot_inst_get (insn) == 33)
  18911 		return OPCODE_WSR_M1;
  18912 	      if (Field_sr_Slot_inst_get (insn) == 34)
  18913 		return OPCODE_WSR_M2;
  18914 	      if (Field_sr_Slot_inst_get (insn) == 35)
  18915 		return OPCODE_WSR_M3;
  18916 	      if (Field_sr_Slot_inst_get (insn) == 72)
  18917 		return OPCODE_WSR_WINDOWBASE;
  18918 	      if (Field_sr_Slot_inst_get (insn) == 73)
  18919 		return OPCODE_WSR_WINDOWSTART;
  18920 	      if (Field_sr_Slot_inst_get (insn) == 83)
  18921 		return OPCODE_WSR_PTEVADDR;
  18922 	      if (Field_sr_Slot_inst_get (insn) == 89)
  18923 		return OPCODE_WSR_MMID;
  18924 	      if (Field_sr_Slot_inst_get (insn) == 90)
  18925 		return OPCODE_WSR_RASID;
  18926 	      if (Field_sr_Slot_inst_get (insn) == 91)
  18927 		return OPCODE_WSR_ITLBCFG;
  18928 	      if (Field_sr_Slot_inst_get (insn) == 92)
  18929 		return OPCODE_WSR_DTLBCFG;
  18930 	      if (Field_sr_Slot_inst_get (insn) == 95)
  18931 		return OPCODE_WSR_ERACCESS;
  18932 	      if (Field_sr_Slot_inst_get (insn) == 96)
  18933 		return OPCODE_WSR_IBREAKENABLE;
  18934 	      if (Field_sr_Slot_inst_get (insn) == 97)
  18935 		return OPCODE_WSR_MEMCTL;
  18936 	      if (Field_sr_Slot_inst_get (insn) == 99)
  18937 		return OPCODE_WSR_ATOMCTL;
  18938 	      if (Field_sr_Slot_inst_get (insn) == 104)
  18939 		return OPCODE_WSR_DDR;
  18940 	      if (Field_sr_Slot_inst_get (insn) == 128)
  18941 		return OPCODE_WSR_IBREAKA0;
  18942 	      if (Field_sr_Slot_inst_get (insn) == 129)
  18943 		return OPCODE_WSR_IBREAKA1;
  18944 	      if (Field_sr_Slot_inst_get (insn) == 144)
  18945 		return OPCODE_WSR_DBREAKA0;
  18946 	      if (Field_sr_Slot_inst_get (insn) == 145)
  18947 		return OPCODE_WSR_DBREAKA1;
  18948 	      if (Field_sr_Slot_inst_get (insn) == 160)
  18949 		return OPCODE_WSR_DBREAKC0;
  18950 	      if (Field_sr_Slot_inst_get (insn) == 161)
  18951 		return OPCODE_WSR_DBREAKC1;
  18952 	      if (Field_sr_Slot_inst_get (insn) == 176)
  18953 		return OPCODE_WSR_CONFIGID0;
  18954 	      if (Field_sr_Slot_inst_get (insn) == 177)
  18955 		return OPCODE_WSR_EPC1;
  18956 	      if (Field_sr_Slot_inst_get (insn) == 178)
  18957 		return OPCODE_WSR_EPC2;
  18958 	      if (Field_sr_Slot_inst_get (insn) == 179)
  18959 		return OPCODE_WSR_EPC3;
  18960 	      if (Field_sr_Slot_inst_get (insn) == 180)
  18961 		return OPCODE_WSR_EPC4;
  18962 	      if (Field_sr_Slot_inst_get (insn) == 181)
  18963 		return OPCODE_WSR_EPC5;
  18964 	      if (Field_sr_Slot_inst_get (insn) == 182)
  18965 		return OPCODE_WSR_EPC6;
  18966 	      if (Field_sr_Slot_inst_get (insn) == 183)
  18967 		return OPCODE_WSR_EPC7;
  18968 	      if (Field_sr_Slot_inst_get (insn) == 192)
  18969 		return OPCODE_WSR_DEPC;
  18970 	      if (Field_sr_Slot_inst_get (insn) == 194)
  18971 		return OPCODE_WSR_EPS2;
  18972 	      if (Field_sr_Slot_inst_get (insn) == 195)
  18973 		return OPCODE_WSR_EPS3;
  18974 	      if (Field_sr_Slot_inst_get (insn) == 196)
  18975 		return OPCODE_WSR_EPS4;
  18976 	      if (Field_sr_Slot_inst_get (insn) == 197)
  18977 		return OPCODE_WSR_EPS5;
  18978 	      if (Field_sr_Slot_inst_get (insn) == 198)
  18979 		return OPCODE_WSR_EPS6;
  18980 	      if (Field_sr_Slot_inst_get (insn) == 199)
  18981 		return OPCODE_WSR_EPS7;
  18982 	      if (Field_sr_Slot_inst_get (insn) == 209)
  18983 		return OPCODE_WSR_EXCSAVE1;
  18984 	      if (Field_sr_Slot_inst_get (insn) == 210)
  18985 		return OPCODE_WSR_EXCSAVE2;
  18986 	      if (Field_sr_Slot_inst_get (insn) == 211)
  18987 		return OPCODE_WSR_EXCSAVE3;
  18988 	      if (Field_sr_Slot_inst_get (insn) == 212)
  18989 		return OPCODE_WSR_EXCSAVE4;
  18990 	      if (Field_sr_Slot_inst_get (insn) == 213)
  18991 		return OPCODE_WSR_EXCSAVE5;
  18992 	      if (Field_sr_Slot_inst_get (insn) == 214)
  18993 		return OPCODE_WSR_EXCSAVE6;
  18994 	      if (Field_sr_Slot_inst_get (insn) == 215)
  18995 		return OPCODE_WSR_EXCSAVE7;
  18996 	      if (Field_sr_Slot_inst_get (insn) == 224)
  18997 		return OPCODE_WSR_CPENABLE;
  18998 	      if (Field_sr_Slot_inst_get (insn) == 226)
  18999 		return OPCODE_WSR_INTSET;
  19000 	      if (Field_sr_Slot_inst_get (insn) == 227)
  19001 		return OPCODE_WSR_INTCLEAR;
  19002 	      if (Field_sr_Slot_inst_get (insn) == 228)
  19003 		return OPCODE_WSR_INTENABLE;
  19004 	      if (Field_sr_Slot_inst_get (insn) == 230)
  19005 		return OPCODE_WSR_PS;
  19006 	      if (Field_sr_Slot_inst_get (insn) == 231)
  19007 		return OPCODE_WSR_VECBASE;
  19008 	      if (Field_sr_Slot_inst_get (insn) == 232)
  19009 		return OPCODE_WSR_EXCCAUSE;
  19010 	      if (Field_sr_Slot_inst_get (insn) == 233)
  19011 		return OPCODE_WSR_DEBUGCAUSE;
  19012 	      if (Field_sr_Slot_inst_get (insn) == 234)
  19013 		return OPCODE_WSR_CCOUNT;
  19014 	      if (Field_sr_Slot_inst_get (insn) == 236)
  19015 		return OPCODE_WSR_ICOUNT;
  19016 	      if (Field_sr_Slot_inst_get (insn) == 237)
  19017 		return OPCODE_WSR_ICOUNTLEVEL;
  19018 	      if (Field_sr_Slot_inst_get (insn) == 238)
  19019 		return OPCODE_WSR_EXCVADDR;
  19020 	      if (Field_sr_Slot_inst_get (insn) == 240)
  19021 		return OPCODE_WSR_CCOMPARE0;
  19022 	      if (Field_sr_Slot_inst_get (insn) == 241)
  19023 		return OPCODE_WSR_CCOMPARE1;
  19024 	      if (Field_sr_Slot_inst_get (insn) == 242)
  19025 		return OPCODE_WSR_CCOMPARE2;
  19026 	      if (Field_sr_Slot_inst_get (insn) == 244)
  19027 		return OPCODE_WSR_MISC0;
  19028 	      if (Field_sr_Slot_inst_get (insn) == 245)
  19029 		return OPCODE_WSR_MISC1;
  19030 	    }
  19031 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19032 	    return OPCODE_SEXT;
  19033 	  if (Field_op2_Slot_inst_get (insn) == 3)
  19034 	    return OPCODE_CLAMPS;
  19035 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19036 	    return OPCODE_MIN;
  19037 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19038 	    return OPCODE_MAX;
  19039 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19040 	    return OPCODE_MINU;
  19041 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19042 	    return OPCODE_MAXU;
  19043 	  if (Field_op2_Slot_inst_get (insn) == 8)
  19044 	    return OPCODE_MOVEQZ;
  19045 	  if (Field_op2_Slot_inst_get (insn) == 9)
  19046 	    return OPCODE_MOVNEZ;
  19047 	  if (Field_op2_Slot_inst_get (insn) == 10)
  19048 	    return OPCODE_MOVLTZ;
  19049 	  if (Field_op2_Slot_inst_get (insn) == 11)
  19050 	    return OPCODE_MOVGEZ;
  19051 	  if (Field_op2_Slot_inst_get (insn) == 12)
  19052 	    return OPCODE_MOVF;
  19053 	  if (Field_op2_Slot_inst_get (insn) == 13)
  19054 	    return OPCODE_MOVT;
  19055 	  if (Field_op2_Slot_inst_get (insn) == 14)
  19056 	    {
  19057 	      if (Field_st_Slot_inst_get (insn) == 230)
  19058 		return OPCODE_RUR_EXPSTATE;
  19059 	      if (Field_st_Slot_inst_get (insn) == 231)
  19060 		return OPCODE_RUR_THREADPTR;
  19061 	      if (Field_st_Slot_inst_get (insn) == 232)
  19062 		return OPCODE_RUR_FCR;
  19063 	      if (Field_st_Slot_inst_get (insn) == 233)
  19064 		return OPCODE_RUR_FSR;
  19065 	    }
  19066 	  if (Field_op2_Slot_inst_get (insn) == 15)
  19067 	    {
  19068 	      if (Field_sr_Slot_inst_get (insn) == 230)
  19069 		return OPCODE_WUR_EXPSTATE;
  19070 	      if (Field_sr_Slot_inst_get (insn) == 231)
  19071 		return OPCODE_WUR_THREADPTR;
  19072 	      if (Field_sr_Slot_inst_get (insn) == 232)
  19073 		return OPCODE_WUR_FCR;
  19074 	      if (Field_sr_Slot_inst_get (insn) == 233)
  19075 		return OPCODE_WUR_FSR;
  19076 	    }
  19077 	}
  19078       if ((Field_op1_Slot_inst_get (insn) == 4 ||
  19079 	   Field_op1_Slot_inst_get (insn) == 5))
  19080 	return OPCODE_EXTUI;
  19081       if (Field_op1_Slot_inst_get (insn) == 8)
  19082 	{
  19083 	  if (Field_op2_Slot_inst_get (insn) == 0)
  19084 	    return OPCODE_LSX;
  19085 	  if (Field_op2_Slot_inst_get (insn) == 1)
  19086 	    return OPCODE_LSXP;
  19087 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19088 	    return OPCODE_LDX;
  19089 	  if (Field_op2_Slot_inst_get (insn) == 3)
  19090 	    return OPCODE_LDXP;
  19091 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19092 	    return OPCODE_SSX;
  19093 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19094 	    return OPCODE_SSXP;
  19095 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19096 	    return OPCODE_SDX;
  19097 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19098 	    return OPCODE_SDXP;
  19099 	}
  19100       if (Field_op1_Slot_inst_get (insn) == 9)
  19101 	{
  19102 	  if (Field_op2_Slot_inst_get (insn) == 0)
  19103 	    return OPCODE_L32E;
  19104 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19105 	    return OPCODE_S32E;
  19106 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19107 	    return OPCODE_S32NB;
  19108 	}
  19109       if (Field_op1_Slot_inst_get (insn) == 10)
  19110 	{
  19111 	  if (Field_op2_Slot_inst_get (insn) == 0)
  19112 	    return OPCODE_ADD_S;
  19113 	  if (Field_op2_Slot_inst_get (insn) == 1)
  19114 	    return OPCODE_SUB_S;
  19115 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19116 	    return OPCODE_MUL_S;
  19117 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19118 	    return OPCODE_MADD_S;
  19119 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19120 	    return OPCODE_MSUB_S;
  19121 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19122 	    return OPCODE_MADDN_S;
  19123 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19124 	    return OPCODE_DIVN_S;
  19125 	  if (Field_op2_Slot_inst_get (insn) == 8)
  19126 	    return OPCODE_ROUND_S;
  19127 	  if (Field_op2_Slot_inst_get (insn) == 9)
  19128 	    return OPCODE_TRUNC_S;
  19129 	  if (Field_op2_Slot_inst_get (insn) == 10)
  19130 	    return OPCODE_FLOOR_S;
  19131 	  if (Field_op2_Slot_inst_get (insn) == 11)
  19132 	    return OPCODE_CEIL_S;
  19133 	  if (Field_op2_Slot_inst_get (insn) == 12)
  19134 	    return OPCODE_FLOAT_S;
  19135 	  if (Field_op2_Slot_inst_get (insn) == 13)
  19136 	    return OPCODE_UFLOAT_S;
  19137 	  if (Field_op2_Slot_inst_get (insn) == 14)
  19138 	    return OPCODE_UTRUNC_S;
  19139 	  if (Field_op2_Slot_inst_get (insn) == 15)
  19140 	    {
  19141 	      if (Field_t_Slot_inst_get (insn) == 0)
  19142 		return OPCODE_MOV_S;
  19143 	      if (Field_t_Slot_inst_get (insn) == 1)
  19144 		return OPCODE_ABS_S;
  19145 	      if (Field_t_Slot_inst_get (insn) == 2)
  19146 		return OPCODE_CVTD_S;
  19147 	      if (Field_t_Slot_inst_get (insn) == 3)
  19148 		return OPCODE_CONST_S;
  19149 	      if (Field_t_Slot_inst_get (insn) == 4)
  19150 		return OPCODE_RFR;
  19151 	      if (Field_t_Slot_inst_get (insn) == 5)
  19152 		return OPCODE_WFR;
  19153 	      if (Field_t_Slot_inst_get (insn) == 6)
  19154 		return OPCODE_NEG_S;
  19155 	      if (Field_t_Slot_inst_get (insn) == 7)
  19156 		return OPCODE_DIV0_S;
  19157 	      if (Field_t_Slot_inst_get (insn) == 8)
  19158 		return OPCODE_RECIP0_S;
  19159 	      if (Field_t_Slot_inst_get (insn) == 9)
  19160 		return OPCODE_SQRT0_S;
  19161 	      if (Field_t_Slot_inst_get (insn) == 10)
  19162 		return OPCODE_RSQRT0_S;
  19163 	      if (Field_t_Slot_inst_get (insn) == 11)
  19164 		return OPCODE_NEXP01_S;
  19165 	      if (Field_t_Slot_inst_get (insn) == 12)
  19166 		return OPCODE_MKSADJ_S;
  19167 	      if (Field_t_Slot_inst_get (insn) == 13)
  19168 		return OPCODE_MKDADJ_S;
  19169 	      if (Field_t_Slot_inst_get (insn) == 14)
  19170 		return OPCODE_ADDEXP_S;
  19171 	      if (Field_t_Slot_inst_get (insn) == 15)
  19172 		return OPCODE_ADDEXPM_S;
  19173 	    }
  19174 	}
  19175       if (Field_op1_Slot_inst_get (insn) == 11)
  19176 	{
  19177 	  if (Field_op2_Slot_inst_get (insn) == 1)
  19178 	    return OPCODE_UN_S;
  19179 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19180 	    return OPCODE_OEQ_S;
  19181 	  if (Field_op2_Slot_inst_get (insn) == 3)
  19182 	    return OPCODE_UEQ_S;
  19183 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19184 	    return OPCODE_OLT_S;
  19185 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19186 	    return OPCODE_ULT_S;
  19187 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19188 	    return OPCODE_OLE_S;
  19189 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19190 	    return OPCODE_ULE_S;
  19191 	  if (Field_op2_Slot_inst_get (insn) == 8)
  19192 	    return OPCODE_MOVEQZ_S;
  19193 	  if (Field_op2_Slot_inst_get (insn) == 9)
  19194 	    return OPCODE_MOVNEZ_S;
  19195 	  if (Field_op2_Slot_inst_get (insn) == 10)
  19196 	    return OPCODE_MOVLTZ_S;
  19197 	  if (Field_op2_Slot_inst_get (insn) == 11)
  19198 	    return OPCODE_MOVGEZ_S;
  19199 	  if (Field_op2_Slot_inst_get (insn) == 12)
  19200 	    return OPCODE_MOVF_S;
  19201 	  if (Field_op2_Slot_inst_get (insn) == 13)
  19202 	    return OPCODE_MOVT_S;
  19203 	}
  19204       if (Field_op1_Slot_inst_get (insn) == 14)
  19205 	{
  19206 	  if (Field_op2_Slot_inst_get (insn) == 1)
  19207 	    return OPCODE_UN_D;
  19208 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19209 	    return OPCODE_OEQ_D;
  19210 	  if (Field_op2_Slot_inst_get (insn) == 3)
  19211 	    return OPCODE_UEQ_D;
  19212 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19213 	    return OPCODE_OLT_D;
  19214 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19215 	    return OPCODE_ULT_D;
  19216 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19217 	    return OPCODE_OLE_D;
  19218 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19219 	    return OPCODE_ULE_D;
  19220 	  if (Field_op2_Slot_inst_get (insn) == 8)
  19221 	    return OPCODE_WFRD;
  19222 	}
  19223       if (Field_op1_Slot_inst_get (insn) == 15)
  19224 	{
  19225 	  if (Field_op2_Slot_inst_get (insn) == 0)
  19226 	    return OPCODE_ADD_D;
  19227 	  if (Field_op2_Slot_inst_get (insn) == 1)
  19228 	    return OPCODE_SUB_D;
  19229 	  if (Field_op2_Slot_inst_get (insn) == 2)
  19230 	    return OPCODE_MUL_D;
  19231 	  if (Field_op2_Slot_inst_get (insn) == 4)
  19232 	    return OPCODE_MADD_D;
  19233 	  if (Field_op2_Slot_inst_get (insn) == 5)
  19234 	    return OPCODE_MSUB_D;
  19235 	  if (Field_op2_Slot_inst_get (insn) == 6)
  19236 	    return OPCODE_MADDN_D;
  19237 	  if (Field_op2_Slot_inst_get (insn) == 7)
  19238 	    return OPCODE_DIVN_D;
  19239 	  if (Field_op2_Slot_inst_get (insn) == 8)
  19240 	    return OPCODE_ROUND_D;
  19241 	  if (Field_op2_Slot_inst_get (insn) == 9)
  19242 	    return OPCODE_TRUNC_D;
  19243 	  if (Field_op2_Slot_inst_get (insn) == 10)
  19244 	    return OPCODE_FLOOR_D;
  19245 	  if (Field_op2_Slot_inst_get (insn) == 11)
  19246 	    return OPCODE_CEIL_D;
  19247 	  if (Field_op2_Slot_inst_get (insn) == 12)
  19248 	    return OPCODE_FLOAT_D;
  19249 	  if (Field_op2_Slot_inst_get (insn) == 13)
  19250 	    return OPCODE_UFLOAT_D;
  19251 	  if (Field_op2_Slot_inst_get (insn) == 14)
  19252 	    return OPCODE_UTRUNC_D;
  19253 	  if (Field_op2_Slot_inst_get (insn) == 15)
  19254 	    {
  19255 	      if (Field_t_Slot_inst_get (insn) == 0)
  19256 		return OPCODE_MOV_D;
  19257 	      if (Field_t_Slot_inst_get (insn) == 1)
  19258 		return OPCODE_ABS_D;
  19259 	      if (Field_t_Slot_inst_get (insn) == 2)
  19260 		return OPCODE_CVTS_D;
  19261 	      if (Field_t_Slot_inst_get (insn) == 3)
  19262 		return OPCODE_CONST_D;
  19263 	      if (Field_t_Slot_inst_get (insn) == 4)
  19264 		return OPCODE_RFRD;
  19265 	      if (Field_t_Slot_inst_get (insn) == 6)
  19266 		return OPCODE_NEG_D;
  19267 	      if (Field_t_Slot_inst_get (insn) == 7)
  19268 		return OPCODE_DIV0_D;
  19269 	      if (Field_t_Slot_inst_get (insn) == 8)
  19270 		return OPCODE_RECIP0_D;
  19271 	      if (Field_t_Slot_inst_get (insn) == 9)
  19272 		return OPCODE_SQRT0_D;
  19273 	      if (Field_t_Slot_inst_get (insn) == 10)
  19274 		return OPCODE_RSQRT0_D;
  19275 	      if (Field_t_Slot_inst_get (insn) == 11)
  19276 		return OPCODE_NEXP01_D;
  19277 	      if (Field_t_Slot_inst_get (insn) == 12)
  19278 		return OPCODE_MKSADJ_D;
  19279 	      if (Field_t_Slot_inst_get (insn) == 13)
  19280 		return OPCODE_MKDADJ_D;
  19281 	      if (Field_t_Slot_inst_get (insn) == 14)
  19282 		return OPCODE_ADDEXP_D;
  19283 	      if (Field_t_Slot_inst_get (insn) == 15)
  19284 		return OPCODE_ADDEXPM_D;
  19285 	    }
  19286 	}
  19287       if (Field_r_Slot_inst_get (insn) == 0 &&
  19288 	  Field_s_Slot_inst_get (insn) == 0 &&
  19289 	  Field_op2_Slot_inst_get (insn) == 0 &&
  19290 	  Field_op1_Slot_inst_get (insn) == 14)
  19291 	return OPCODE_READ_IMPWIRE;
  19292       if (Field_r_Slot_inst_get (insn) == 1 &&
  19293 	  Field_s3to1_Slot_inst_get (insn) == 0 &&
  19294 	  Field_op2_Slot_inst_get (insn) == 0 &&
  19295 	  Field_op1_Slot_inst_get (insn) == 14)
  19296 	return OPCODE_SETB_EXPSTATE;
  19297       if (Field_r_Slot_inst_get (insn) == 1 &&
  19298 	  Field_s3to1_Slot_inst_get (insn) == 1 &&
  19299 	  Field_op2_Slot_inst_get (insn) == 0 &&
  19300 	  Field_op1_Slot_inst_get (insn) == 14)
  19301 	return OPCODE_CLRB_EXPSTATE;
  19302       if (Field_r_Slot_inst_get (insn) == 2 &&
  19303 	  Field_op2_Slot_inst_get (insn) == 0 &&
  19304 	  Field_op1_Slot_inst_get (insn) == 14)
  19305 	return OPCODE_WRMSK_EXPSTATE;
  19306     }
  19307   if (Field_op0_Slot_inst_get (insn) == 1)
  19308     return OPCODE_L32R;
  19309   if (Field_op0_Slot_inst_get (insn) == 2)
  19310     {
  19311       if (Field_r_Slot_inst_get (insn) == 0)
  19312 	return OPCODE_L8UI;
  19313       if (Field_r_Slot_inst_get (insn) == 1)
  19314 	return OPCODE_L16UI;
  19315       if (Field_r_Slot_inst_get (insn) == 2)
  19316 	return OPCODE_L32I;
  19317       if (Field_r_Slot_inst_get (insn) == 4)
  19318 	return OPCODE_S8I;
  19319       if (Field_r_Slot_inst_get (insn) == 5)
  19320 	return OPCODE_S16I;
  19321       if (Field_r_Slot_inst_get (insn) == 6)
  19322 	return OPCODE_S32I;
  19323       if (Field_r_Slot_inst_get (insn) == 7)
  19324 	{
  19325 	  if (Field_t_Slot_inst_get (insn) == 0)
  19326 	    return OPCODE_DPFR;
  19327 	  if (Field_t_Slot_inst_get (insn) == 1)
  19328 	    return OPCODE_DPFW;
  19329 	  if (Field_t_Slot_inst_get (insn) == 2)
  19330 	    return OPCODE_DPFRO;
  19331 	  if (Field_t_Slot_inst_get (insn) == 3)
  19332 	    return OPCODE_DPFWO;
  19333 	  if (Field_t_Slot_inst_get (insn) == 4)
  19334 	    return OPCODE_DHWB;
  19335 	  if (Field_t_Slot_inst_get (insn) == 5)
  19336 	    return OPCODE_DHWBI;
  19337 	  if (Field_t_Slot_inst_get (insn) == 6)
  19338 	    return OPCODE_DHI;
  19339 	  if (Field_t_Slot_inst_get (insn) == 7)
  19340 	    return OPCODE_DII;
  19341 	  if (Field_t_Slot_inst_get (insn) == 8)
  19342 	    {
  19343 	      if (Field_op1_Slot_inst_get (insn) == 0)
  19344 		return OPCODE_DPFL;
  19345 	      if (Field_op1_Slot_inst_get (insn) == 2)
  19346 		return OPCODE_DHU;
  19347 	      if (Field_op1_Slot_inst_get (insn) == 3)
  19348 		return OPCODE_DIU;
  19349 	      if (Field_op1_Slot_inst_get (insn) == 4)
  19350 		return OPCODE_DIWB;
  19351 	      if (Field_op1_Slot_inst_get (insn) == 5)
  19352 		return OPCODE_DIWBI;
  19353 	      if (Field_op1_Slot_inst_get (insn) == 15 &&
  19354 		  Field_op2_Slot_inst_get (insn) == 0)
  19355 		return OPCODE_DIWBUI_P;
  19356 	    }
  19357 	  if (Field_t_Slot_inst_get (insn) == 12)
  19358 	    return OPCODE_IPF;
  19359 	  if (Field_t_Slot_inst_get (insn) == 13)
  19360 	    {
  19361 	      if (Field_op1_Slot_inst_get (insn) == 0)
  19362 		return OPCODE_IPFL;
  19363 	      if (Field_op1_Slot_inst_get (insn) == 2)
  19364 		return OPCODE_IHU;
  19365 	      if (Field_op1_Slot_inst_get (insn) == 3)
  19366 		return OPCODE_IIU;
  19367 	    }
  19368 	  if (Field_t_Slot_inst_get (insn) == 14)
  19369 	    return OPCODE_IHI;
  19370 	  if (Field_t_Slot_inst_get (insn) == 15)
  19371 	    return OPCODE_III;
  19372 	}
  19373       if (Field_r_Slot_inst_get (insn) == 9)
  19374 	return OPCODE_L16SI;
  19375       if (Field_r_Slot_inst_get (insn) == 10)
  19376 	return OPCODE_MOVI;
  19377       if (Field_r_Slot_inst_get (insn) == 11)
  19378 	return OPCODE_L32AI;
  19379       if (Field_r_Slot_inst_get (insn) == 12)
  19380 	return OPCODE_ADDI;
  19381       if (Field_r_Slot_inst_get (insn) == 13)
  19382 	return OPCODE_ADDMI;
  19383       if (Field_r_Slot_inst_get (insn) == 14)
  19384 	return OPCODE_S32C1I;
  19385       if (Field_r_Slot_inst_get (insn) == 15)
  19386 	return OPCODE_S32RI;
  19387     }
  19388   if (Field_op0_Slot_inst_get (insn) == 3)
  19389     {
  19390       if (Field_r_Slot_inst_get (insn) == 0)
  19391 	return OPCODE_LSI;
  19392       if (Field_r_Slot_inst_get (insn) == 1)
  19393 	return OPCODE_LDI;
  19394       if (Field_r_Slot_inst_get (insn) == 4)
  19395 	return OPCODE_SSI;
  19396       if (Field_r_Slot_inst_get (insn) == 5)
  19397 	return OPCODE_SDI;
  19398       if (Field_r_Slot_inst_get (insn) == 8)
  19399 	return OPCODE_LSIP;
  19400       if (Field_r_Slot_inst_get (insn) == 9)
  19401 	return OPCODE_LDIP;
  19402       if (Field_r_Slot_inst_get (insn) == 12)
  19403 	return OPCODE_SSIP;
  19404       if (Field_r_Slot_inst_get (insn) == 13)
  19405 	return OPCODE_SDIP;
  19406     }
  19407   if (Field_op0_Slot_inst_get (insn) == 4)
  19408     {
  19409       if (Field_op2_Slot_inst_get (insn) == 0)
  19410 	{
  19411 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19412 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19413 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19414 	      Field_r3_Slot_inst_get (insn) == 0)
  19415 	    return OPCODE_MULA_DD_LL_LDINC;
  19416 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19417 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19418 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19419 	      Field_r3_Slot_inst_get (insn) == 0)
  19420 	    return OPCODE_MULA_DD_HL_LDINC;
  19421 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19422 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19423 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19424 	      Field_r3_Slot_inst_get (insn) == 0)
  19425 	    return OPCODE_MULA_DD_LH_LDINC;
  19426 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19427 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19428 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19429 	      Field_r3_Slot_inst_get (insn) == 0)
  19430 	    return OPCODE_MULA_DD_HH_LDINC;
  19431 	}
  19432       if (Field_op2_Slot_inst_get (insn) == 1)
  19433 	{
  19434 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19435 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19436 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19437 	      Field_r3_Slot_inst_get (insn) == 0)
  19438 	    return OPCODE_MULA_DD_LL_LDDEC;
  19439 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19440 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19441 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19442 	      Field_r3_Slot_inst_get (insn) == 0)
  19443 	    return OPCODE_MULA_DD_HL_LDDEC;
  19444 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19445 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19446 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19447 	      Field_r3_Slot_inst_get (insn) == 0)
  19448 	    return OPCODE_MULA_DD_LH_LDDEC;
  19449 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19450 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19451 	      Field_tlo_Slot_inst_get (insn) == 0 &&
  19452 	      Field_r3_Slot_inst_get (insn) == 0)
  19453 	    return OPCODE_MULA_DD_HH_LDDEC;
  19454 	}
  19455       if (Field_op2_Slot_inst_get (insn) == 2)
  19456 	{
  19457 	  if (Field_op1_Slot_inst_get (insn) == 4 &&
  19458 	      Field_s_Slot_inst_get (insn) == 0 &&
  19459 	      Field_w_Slot_inst_get (insn) == 0 &&
  19460 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19461 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19462 	      Field_tlo_Slot_inst_get (insn) == 0)
  19463 	    return OPCODE_MUL_DD_LL;
  19464 	  if (Field_op1_Slot_inst_get (insn) == 5 &&
  19465 	      Field_s_Slot_inst_get (insn) == 0 &&
  19466 	      Field_w_Slot_inst_get (insn) == 0 &&
  19467 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19468 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19469 	      Field_tlo_Slot_inst_get (insn) == 0)
  19470 	    return OPCODE_MUL_DD_HL;
  19471 	  if (Field_op1_Slot_inst_get (insn) == 6 &&
  19472 	      Field_s_Slot_inst_get (insn) == 0 &&
  19473 	      Field_w_Slot_inst_get (insn) == 0 &&
  19474 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19475 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19476 	      Field_tlo_Slot_inst_get (insn) == 0)
  19477 	    return OPCODE_MUL_DD_LH;
  19478 	  if (Field_op1_Slot_inst_get (insn) == 7 &&
  19479 	      Field_s_Slot_inst_get (insn) == 0 &&
  19480 	      Field_w_Slot_inst_get (insn) == 0 &&
  19481 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19482 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19483 	      Field_tlo_Slot_inst_get (insn) == 0)
  19484 	    return OPCODE_MUL_DD_HH;
  19485 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19486 	      Field_s_Slot_inst_get (insn) == 0 &&
  19487 	      Field_w_Slot_inst_get (insn) == 0 &&
  19488 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19489 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19490 	      Field_tlo_Slot_inst_get (insn) == 0)
  19491 	    return OPCODE_MULA_DD_LL;
  19492 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19493 	      Field_s_Slot_inst_get (insn) == 0 &&
  19494 	      Field_w_Slot_inst_get (insn) == 0 &&
  19495 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19496 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19497 	      Field_tlo_Slot_inst_get (insn) == 0)
  19498 	    return OPCODE_MULA_DD_HL;
  19499 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19500 	      Field_s_Slot_inst_get (insn) == 0 &&
  19501 	      Field_w_Slot_inst_get (insn) == 0 &&
  19502 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19503 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19504 	      Field_tlo_Slot_inst_get (insn) == 0)
  19505 	    return OPCODE_MULA_DD_LH;
  19506 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19507 	      Field_s_Slot_inst_get (insn) == 0 &&
  19508 	      Field_w_Slot_inst_get (insn) == 0 &&
  19509 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19510 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19511 	      Field_tlo_Slot_inst_get (insn) == 0)
  19512 	    return OPCODE_MULA_DD_HH;
  19513 	  if (Field_op1_Slot_inst_get (insn) == 12 &&
  19514 	      Field_s_Slot_inst_get (insn) == 0 &&
  19515 	      Field_w_Slot_inst_get (insn) == 0 &&
  19516 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19517 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19518 	      Field_tlo_Slot_inst_get (insn) == 0)
  19519 	    return OPCODE_MULS_DD_LL;
  19520 	  if (Field_op1_Slot_inst_get (insn) == 13 &&
  19521 	      Field_s_Slot_inst_get (insn) == 0 &&
  19522 	      Field_w_Slot_inst_get (insn) == 0 &&
  19523 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19524 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19525 	      Field_tlo_Slot_inst_get (insn) == 0)
  19526 	    return OPCODE_MULS_DD_HL;
  19527 	  if (Field_op1_Slot_inst_get (insn) == 14 &&
  19528 	      Field_s_Slot_inst_get (insn) == 0 &&
  19529 	      Field_w_Slot_inst_get (insn) == 0 &&
  19530 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19531 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19532 	      Field_tlo_Slot_inst_get (insn) == 0)
  19533 	    return OPCODE_MULS_DD_LH;
  19534 	  if (Field_op1_Slot_inst_get (insn) == 15 &&
  19535 	      Field_s_Slot_inst_get (insn) == 0 &&
  19536 	      Field_w_Slot_inst_get (insn) == 0 &&
  19537 	      Field_r3_Slot_inst_get (insn) == 0 &&
  19538 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19539 	      Field_tlo_Slot_inst_get (insn) == 0)
  19540 	    return OPCODE_MULS_DD_HH;
  19541 	}
  19542       if (Field_op2_Slot_inst_get (insn) == 3)
  19543 	{
  19544 	  if (Field_op1_Slot_inst_get (insn) == 4 &&
  19545 	      Field_r_Slot_inst_get (insn) == 0 &&
  19546 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19547 	      Field_tlo_Slot_inst_get (insn) == 0)
  19548 	    return OPCODE_MUL_AD_LL;
  19549 	  if (Field_op1_Slot_inst_get (insn) == 5 &&
  19550 	      Field_r_Slot_inst_get (insn) == 0 &&
  19551 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19552 	      Field_tlo_Slot_inst_get (insn) == 0)
  19553 	    return OPCODE_MUL_AD_HL;
  19554 	  if (Field_op1_Slot_inst_get (insn) == 6 &&
  19555 	      Field_r_Slot_inst_get (insn) == 0 &&
  19556 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19557 	      Field_tlo_Slot_inst_get (insn) == 0)
  19558 	    return OPCODE_MUL_AD_LH;
  19559 	  if (Field_op1_Slot_inst_get (insn) == 7 &&
  19560 	      Field_r_Slot_inst_get (insn) == 0 &&
  19561 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19562 	      Field_tlo_Slot_inst_get (insn) == 0)
  19563 	    return OPCODE_MUL_AD_HH;
  19564 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19565 	      Field_r_Slot_inst_get (insn) == 0 &&
  19566 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19567 	      Field_tlo_Slot_inst_get (insn) == 0)
  19568 	    return OPCODE_MULA_AD_LL;
  19569 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19570 	      Field_r_Slot_inst_get (insn) == 0 &&
  19571 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19572 	      Field_tlo_Slot_inst_get (insn) == 0)
  19573 	    return OPCODE_MULA_AD_HL;
  19574 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19575 	      Field_r_Slot_inst_get (insn) == 0 &&
  19576 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19577 	      Field_tlo_Slot_inst_get (insn) == 0)
  19578 	    return OPCODE_MULA_AD_LH;
  19579 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19580 	      Field_r_Slot_inst_get (insn) == 0 &&
  19581 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19582 	      Field_tlo_Slot_inst_get (insn) == 0)
  19583 	    return OPCODE_MULA_AD_HH;
  19584 	  if (Field_op1_Slot_inst_get (insn) == 12 &&
  19585 	      Field_r_Slot_inst_get (insn) == 0 &&
  19586 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19587 	      Field_tlo_Slot_inst_get (insn) == 0)
  19588 	    return OPCODE_MULS_AD_LL;
  19589 	  if (Field_op1_Slot_inst_get (insn) == 13 &&
  19590 	      Field_r_Slot_inst_get (insn) == 0 &&
  19591 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19592 	      Field_tlo_Slot_inst_get (insn) == 0)
  19593 	    return OPCODE_MULS_AD_HL;
  19594 	  if (Field_op1_Slot_inst_get (insn) == 14 &&
  19595 	      Field_r_Slot_inst_get (insn) == 0 &&
  19596 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19597 	      Field_tlo_Slot_inst_get (insn) == 0)
  19598 	    return OPCODE_MULS_AD_LH;
  19599 	  if (Field_op1_Slot_inst_get (insn) == 15 &&
  19600 	      Field_r_Slot_inst_get (insn) == 0 &&
  19601 	      Field_t3_Slot_inst_get (insn) == 0 &&
  19602 	      Field_tlo_Slot_inst_get (insn) == 0)
  19603 	    return OPCODE_MULS_AD_HH;
  19604 	}
  19605       if (Field_op2_Slot_inst_get (insn) == 4)
  19606 	{
  19607 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19608 	      Field_r3_Slot_inst_get (insn) == 0)
  19609 	    return OPCODE_MULA_DA_LL_LDINC;
  19610 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19611 	      Field_r3_Slot_inst_get (insn) == 0)
  19612 	    return OPCODE_MULA_DA_HL_LDINC;
  19613 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19614 	      Field_r3_Slot_inst_get (insn) == 0)
  19615 	    return OPCODE_MULA_DA_LH_LDINC;
  19616 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19617 	      Field_r3_Slot_inst_get (insn) == 0)
  19618 	    return OPCODE_MULA_DA_HH_LDINC;
  19619 	}
  19620       if (Field_op2_Slot_inst_get (insn) == 5)
  19621 	{
  19622 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19623 	      Field_r3_Slot_inst_get (insn) == 0)
  19624 	    return OPCODE_MULA_DA_LL_LDDEC;
  19625 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19626 	      Field_r3_Slot_inst_get (insn) == 0)
  19627 	    return OPCODE_MULA_DA_HL_LDDEC;
  19628 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19629 	      Field_r3_Slot_inst_get (insn) == 0)
  19630 	    return OPCODE_MULA_DA_LH_LDDEC;
  19631 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19632 	      Field_r3_Slot_inst_get (insn) == 0)
  19633 	    return OPCODE_MULA_DA_HH_LDDEC;
  19634 	}
  19635       if (Field_op2_Slot_inst_get (insn) == 6)
  19636 	{
  19637 	  if (Field_op1_Slot_inst_get (insn) == 4 &&
  19638 	      Field_s_Slot_inst_get (insn) == 0 &&
  19639 	      Field_w_Slot_inst_get (insn) == 0 &&
  19640 	      Field_r3_Slot_inst_get (insn) == 0)
  19641 	    return OPCODE_MUL_DA_LL;
  19642 	  if (Field_op1_Slot_inst_get (insn) == 5 &&
  19643 	      Field_s_Slot_inst_get (insn) == 0 &&
  19644 	      Field_w_Slot_inst_get (insn) == 0 &&
  19645 	      Field_r3_Slot_inst_get (insn) == 0)
  19646 	    return OPCODE_MUL_DA_HL;
  19647 	  if (Field_op1_Slot_inst_get (insn) == 6 &&
  19648 	      Field_s_Slot_inst_get (insn) == 0 &&
  19649 	      Field_w_Slot_inst_get (insn) == 0 &&
  19650 	      Field_r3_Slot_inst_get (insn) == 0)
  19651 	    return OPCODE_MUL_DA_LH;
  19652 	  if (Field_op1_Slot_inst_get (insn) == 7 &&
  19653 	      Field_s_Slot_inst_get (insn) == 0 &&
  19654 	      Field_w_Slot_inst_get (insn) == 0 &&
  19655 	      Field_r3_Slot_inst_get (insn) == 0)
  19656 	    return OPCODE_MUL_DA_HH;
  19657 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19658 	      Field_s_Slot_inst_get (insn) == 0 &&
  19659 	      Field_w_Slot_inst_get (insn) == 0 &&
  19660 	      Field_r3_Slot_inst_get (insn) == 0)
  19661 	    return OPCODE_MULA_DA_LL;
  19662 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19663 	      Field_s_Slot_inst_get (insn) == 0 &&
  19664 	      Field_w_Slot_inst_get (insn) == 0 &&
  19665 	      Field_r3_Slot_inst_get (insn) == 0)
  19666 	    return OPCODE_MULA_DA_HL;
  19667 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19668 	      Field_s_Slot_inst_get (insn) == 0 &&
  19669 	      Field_w_Slot_inst_get (insn) == 0 &&
  19670 	      Field_r3_Slot_inst_get (insn) == 0)
  19671 	    return OPCODE_MULA_DA_LH;
  19672 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19673 	      Field_s_Slot_inst_get (insn) == 0 &&
  19674 	      Field_w_Slot_inst_get (insn) == 0 &&
  19675 	      Field_r3_Slot_inst_get (insn) == 0)
  19676 	    return OPCODE_MULA_DA_HH;
  19677 	  if (Field_op1_Slot_inst_get (insn) == 12 &&
  19678 	      Field_s_Slot_inst_get (insn) == 0 &&
  19679 	      Field_w_Slot_inst_get (insn) == 0 &&
  19680 	      Field_r3_Slot_inst_get (insn) == 0)
  19681 	    return OPCODE_MULS_DA_LL;
  19682 	  if (Field_op1_Slot_inst_get (insn) == 13 &&
  19683 	      Field_s_Slot_inst_get (insn) == 0 &&
  19684 	      Field_w_Slot_inst_get (insn) == 0 &&
  19685 	      Field_r3_Slot_inst_get (insn) == 0)
  19686 	    return OPCODE_MULS_DA_HL;
  19687 	  if (Field_op1_Slot_inst_get (insn) == 14 &&
  19688 	      Field_s_Slot_inst_get (insn) == 0 &&
  19689 	      Field_w_Slot_inst_get (insn) == 0 &&
  19690 	      Field_r3_Slot_inst_get (insn) == 0)
  19691 	    return OPCODE_MULS_DA_LH;
  19692 	  if (Field_op1_Slot_inst_get (insn) == 15 &&
  19693 	      Field_s_Slot_inst_get (insn) == 0 &&
  19694 	      Field_w_Slot_inst_get (insn) == 0 &&
  19695 	      Field_r3_Slot_inst_get (insn) == 0)
  19696 	    return OPCODE_MULS_DA_HH;
  19697 	}
  19698       if (Field_op2_Slot_inst_get (insn) == 7)
  19699 	{
  19700 	  if (Field_op1_Slot_inst_get (insn) == 0 &&
  19701 	      Field_r_Slot_inst_get (insn) == 0)
  19702 	    return OPCODE_UMUL_AA_LL;
  19703 	  if (Field_op1_Slot_inst_get (insn) == 1 &&
  19704 	      Field_r_Slot_inst_get (insn) == 0)
  19705 	    return OPCODE_UMUL_AA_HL;
  19706 	  if (Field_op1_Slot_inst_get (insn) == 2 &&
  19707 	      Field_r_Slot_inst_get (insn) == 0)
  19708 	    return OPCODE_UMUL_AA_LH;
  19709 	  if (Field_op1_Slot_inst_get (insn) == 3 &&
  19710 	      Field_r_Slot_inst_get (insn) == 0)
  19711 	    return OPCODE_UMUL_AA_HH;
  19712 	  if (Field_op1_Slot_inst_get (insn) == 4 &&
  19713 	      Field_r_Slot_inst_get (insn) == 0)
  19714 	    return OPCODE_MUL_AA_LL;
  19715 	  if (Field_op1_Slot_inst_get (insn) == 5 &&
  19716 	      Field_r_Slot_inst_get (insn) == 0)
  19717 	    return OPCODE_MUL_AA_HL;
  19718 	  if (Field_op1_Slot_inst_get (insn) == 6 &&
  19719 	      Field_r_Slot_inst_get (insn) == 0)
  19720 	    return OPCODE_MUL_AA_LH;
  19721 	  if (Field_op1_Slot_inst_get (insn) == 7 &&
  19722 	      Field_r_Slot_inst_get (insn) == 0)
  19723 	    return OPCODE_MUL_AA_HH;
  19724 	  if (Field_op1_Slot_inst_get (insn) == 8 &&
  19725 	      Field_r_Slot_inst_get (insn) == 0)
  19726 	    return OPCODE_MULA_AA_LL;
  19727 	  if (Field_op1_Slot_inst_get (insn) == 9 &&
  19728 	      Field_r_Slot_inst_get (insn) == 0)
  19729 	    return OPCODE_MULA_AA_HL;
  19730 	  if (Field_op1_Slot_inst_get (insn) == 10 &&
  19731 	      Field_r_Slot_inst_get (insn) == 0)
  19732 	    return OPCODE_MULA_AA_LH;
  19733 	  if (Field_op1_Slot_inst_get (insn) == 11 &&
  19734 	      Field_r_Slot_inst_get (insn) == 0)
  19735 	    return OPCODE_MULA_AA_HH;
  19736 	  if (Field_op1_Slot_inst_get (insn) == 12 &&
  19737 	      Field_r_Slot_inst_get (insn) == 0)
  19738 	    return OPCODE_MULS_AA_LL;
  19739 	  if (Field_op1_Slot_inst_get (insn) == 13 &&
  19740 	      Field_r_Slot_inst_get (insn) == 0)
  19741 	    return OPCODE_MULS_AA_HL;
  19742 	  if (Field_op1_Slot_inst_get (insn) == 14 &&
  19743 	      Field_r_Slot_inst_get (insn) == 0)
  19744 	    return OPCODE_MULS_AA_LH;
  19745 	  if (Field_op1_Slot_inst_get (insn) == 15 &&
  19746 	      Field_r_Slot_inst_get (insn) == 0)
  19747 	    return OPCODE_MULS_AA_HH;
  19748 	}
  19749       if (Field_op2_Slot_inst_get (insn) == 8)
  19750 	{
  19751 	  if (Field_op1_Slot_inst_get (insn) == 0 &&
  19752 	      Field_t_Slot_inst_get (insn) == 0 &&
  19753 	      Field_rhi_Slot_inst_get (insn) == 0)
  19754 	    return OPCODE_LDINC;
  19755 	}
  19756       if (Field_op2_Slot_inst_get (insn) == 9)
  19757 	{
  19758 	  if (Field_op1_Slot_inst_get (insn) == 0 &&
  19759 	      Field_t_Slot_inst_get (insn) == 0 &&
  19760 	      Field_rhi_Slot_inst_get (insn) == 0)
  19761 	    return OPCODE_LDDEC;
  19762 	}
  19763     }
  19764   if (Field_op0_Slot_inst_get (insn) == 5)
  19765     {
  19766       if (Field_n_Slot_inst_get (insn) == 0)
  19767 	return OPCODE_CALL0;
  19768       if (Field_n_Slot_inst_get (insn) == 1)
  19769 	return OPCODE_CALL4;
  19770       if (Field_n_Slot_inst_get (insn) == 2)
  19771 	return OPCODE_CALL8;
  19772       if (Field_n_Slot_inst_get (insn) == 3)
  19773 	return OPCODE_CALL12;
  19774     }
  19775   if (Field_op0_Slot_inst_get (insn) == 6)
  19776     {
  19777       if (Field_n_Slot_inst_get (insn) == 0)
  19778 	return OPCODE_J;
  19779       if (Field_n_Slot_inst_get (insn) == 1)
  19780 	{
  19781 	  if (Field_m_Slot_inst_get (insn) == 0)
  19782 	    return OPCODE_BEQZ;
  19783 	  if (Field_m_Slot_inst_get (insn) == 1)
  19784 	    return OPCODE_BNEZ;
  19785 	  if (Field_m_Slot_inst_get (insn) == 2)
  19786 	    return OPCODE_BLTZ;
  19787 	  if (Field_m_Slot_inst_get (insn) == 3)
  19788 	    return OPCODE_BGEZ;
  19789 	}
  19790       if (Field_n_Slot_inst_get (insn) == 2)
  19791 	{
  19792 	  if (Field_m_Slot_inst_get (insn) == 0)
  19793 	    return OPCODE_BEQI;
  19794 	  if (Field_m_Slot_inst_get (insn) == 1)
  19795 	    return OPCODE_BNEI;
  19796 	  if (Field_m_Slot_inst_get (insn) == 2)
  19797 	    return OPCODE_BLTI;
  19798 	  if (Field_m_Slot_inst_get (insn) == 3)
  19799 	    return OPCODE_BGEI;
  19800 	}
  19801       if (Field_n_Slot_inst_get (insn) == 3)
  19802 	{
  19803 	  if (Field_m_Slot_inst_get (insn) == 0)
  19804 	    return OPCODE_ENTRY;
  19805 	  if (Field_m_Slot_inst_get (insn) == 1)
  19806 	    {
  19807 	      if (Field_r_Slot_inst_get (insn) == 0)
  19808 		return OPCODE_BF;
  19809 	      if (Field_r_Slot_inst_get (insn) == 1)
  19810 		return OPCODE_BT;
  19811 	      if (Field_r_Slot_inst_get (insn) == 8)
  19812 		return OPCODE_LOOP;
  19813 	      if (Field_r_Slot_inst_get (insn) == 9)
  19814 		return OPCODE_LOOPNEZ;
  19815 	      if (Field_r_Slot_inst_get (insn) == 10)
  19816 		return OPCODE_LOOPGTZ;
  19817 	    }
  19818 	  if (Field_m_Slot_inst_get (insn) == 2)
  19819 	    return OPCODE_BLTUI;
  19820 	  if (Field_m_Slot_inst_get (insn) == 3)
  19821 	    return OPCODE_BGEUI;
  19822 	}
  19823     }
  19824   if (Field_op0_Slot_inst_get (insn) == 7)
  19825     {
  19826       if (Field_r_Slot_inst_get (insn) == 0)
  19827 	return OPCODE_BNONE;
  19828       if (Field_r_Slot_inst_get (insn) == 1)
  19829 	return OPCODE_BEQ;
  19830       if (Field_r_Slot_inst_get (insn) == 2)
  19831 	return OPCODE_BLT;
  19832       if (Field_r_Slot_inst_get (insn) == 3)
  19833 	return OPCODE_BLTU;
  19834       if (Field_r_Slot_inst_get (insn) == 4)
  19835 	return OPCODE_BALL;
  19836       if (Field_r_Slot_inst_get (insn) == 5)
  19837 	return OPCODE_BBC;
  19838       if ((Field_r_Slot_inst_get (insn) == 6 ||
  19839 	   Field_r_Slot_inst_get (insn) == 7))
  19840 	return OPCODE_BBCI;
  19841       if (Field_r_Slot_inst_get (insn) == 8)
  19842 	return OPCODE_BANY;
  19843       if (Field_r_Slot_inst_get (insn) == 9)
  19844 	return OPCODE_BNE;
  19845       if (Field_r_Slot_inst_get (insn) == 10)
  19846 	return OPCODE_BGE;
  19847       if (Field_r_Slot_inst_get (insn) == 11)
  19848 	return OPCODE_BGEU;
  19849       if (Field_r_Slot_inst_get (insn) == 12)
  19850 	return OPCODE_BNALL;
  19851       if (Field_r_Slot_inst_get (insn) == 13)
  19852 	return OPCODE_BBS;
  19853       if ((Field_r_Slot_inst_get (insn) == 14 ||
  19854 	   Field_r_Slot_inst_get (insn) == 15))
  19855 	return OPCODE_BBSI;
  19856     }
  19857   return XTENSA_UNDEFINED;
  19858 }
  19859 
  19860 static int
  19861 Slot_inst16b_decode (const xtensa_insnbuf insn)
  19862 {
  19863   if (Field_op0_Slot_inst16b_get (insn) == 12)
  19864     {
  19865       if (Field_i_Slot_inst16b_get (insn) == 0)
  19866 	return OPCODE_MOVI_N;
  19867       if (Field_i_Slot_inst16b_get (insn) == 1)
  19868 	{
  19869 	  if (Field_z_Slot_inst16b_get (insn) == 0)
  19870 	    return OPCODE_BEQZ_N;
  19871 	  if (Field_z_Slot_inst16b_get (insn) == 1)
  19872 	    return OPCODE_BNEZ_N;
  19873 	}
  19874     }
  19875   if (Field_op0_Slot_inst16b_get (insn) == 13)
  19876     {
  19877       if (Field_r_Slot_inst16b_get (insn) == 0)
  19878 	return OPCODE_MOV_N;
  19879       if (Field_r_Slot_inst16b_get (insn) == 15)
  19880 	{
  19881 	  if (Field_t_Slot_inst16b_get (insn) == 0)
  19882 	    return OPCODE_RET_N;
  19883 	  if (Field_t_Slot_inst16b_get (insn) == 1)
  19884 	    return OPCODE_RETW_N;
  19885 	  if (Field_t_Slot_inst16b_get (insn) == 2)
  19886 	    return OPCODE_BREAK_N;
  19887 	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
  19888 	      Field_s_Slot_inst16b_get (insn) == 0)
  19889 	    return OPCODE_NOP_N;
  19890 	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
  19891 	      Field_s_Slot_inst16b_get (insn) == 0)
  19892 	    return OPCODE_ILL_N;
  19893 	}
  19894     }
  19895   return XTENSA_UNDEFINED;
  19896 }
  19897 
  19898 static int
  19899 Slot_inst16a_decode (const xtensa_insnbuf insn)
  19900 {
  19901   if (Field_op0_Slot_inst16a_get (insn) == 8)
  19902     return OPCODE_L32I_N;
  19903   if (Field_op0_Slot_inst16a_get (insn) == 9)
  19904     return OPCODE_S32I_N;
  19905   if (Field_op0_Slot_inst16a_get (insn) == 10)
  19906     return OPCODE_ADD_N;
  19907   if (Field_op0_Slot_inst16a_get (insn) == 11)
  19908     return OPCODE_ADDI_N;
  19909   return XTENSA_UNDEFINED;
  19910 }
  19911 
  19912 
  19913 /* Instruction slots.  */
  19914 
  19915 static void
  19916 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
  19917 			    xtensa_insnbuf slotbuf)
  19918 {
  19919   slotbuf[0] = (insn[0] & 0xffffff);
  19920 }
  19921 
  19922 static void
  19923 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
  19924 			    const xtensa_insnbuf slotbuf)
  19925 {
  19926   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
  19927 }
  19928 
  19929 static void
  19930 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
  19931 				xtensa_insnbuf slotbuf)
  19932 {
  19933   slotbuf[0] = (insn[0] & 0xffff);
  19934 }
  19935 
  19936 static void
  19937 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
  19938 				const xtensa_insnbuf slotbuf)
  19939 {
  19940   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  19941 }
  19942 
  19943 static void
  19944 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
  19945 				xtensa_insnbuf slotbuf)
  19946 {
  19947   slotbuf[0] = (insn[0] & 0xffff);
  19948 }
  19949 
  19950 static void
  19951 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
  19952 				const xtensa_insnbuf slotbuf)
  19953 {
  19954   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  19955 }
  19956 
  19957 static xtensa_get_field_fn
  19958 Slot_inst_get_field_fns[] = {
  19959   Field_t_Slot_inst_get,
  19960   Field_bbi4_Slot_inst_get,
  19961   Field_bbi_Slot_inst_get,
  19962   Field_imm12_Slot_inst_get,
  19963   Field_imm8_Slot_inst_get,
  19964   Field_s_Slot_inst_get,
  19965   Field_s8_Slot_inst_get,
  19966   Field_imms8_Slot_inst_get,
  19967   Field_imm12b_Slot_inst_get,
  19968   Field_imm16_Slot_inst_get,
  19969   Field_m_Slot_inst_get,
  19970   Field_n_Slot_inst_get,
  19971   Field_offset_Slot_inst_get,
  19972   Field_op0_Slot_inst_get,
  19973   Field_op1_Slot_inst_get,
  19974   Field_op2_Slot_inst_get,
  19975   Field_r_Slot_inst_get,
  19976   Field_r_disp_Slot_inst_get,
  19977   Field_r_3_Slot_inst_get,
  19978   Field_sa4_Slot_inst_get,
  19979   Field_sae4_Slot_inst_get,
  19980   Field_sae_Slot_inst_get,
  19981   Field_sal_Slot_inst_get,
  19982   Field_sargt_Slot_inst_get,
  19983   Field_sas4_Slot_inst_get,
  19984   Field_sas_Slot_inst_get,
  19985   Field_sr_Slot_inst_get,
  19986   Field_st_Slot_inst_get,
  19987   Field_thi3_Slot_inst_get,
  19988   Field_imm4_Slot_inst_get,
  19989   Field_mn_Slot_inst_get,
  19990   0,
  19991   0,
  19992   0,
  19993   0,
  19994   0,
  19995   0,
  19996   0,
  19997   0,
  19998   Field_r3_Slot_inst_get,
  19999   Field_rbit2_Slot_inst_get,
  20000   Field_rhi_Slot_inst_get,
  20001   Field_t3_Slot_inst_get,
  20002   Field_tbit2_Slot_inst_get,
  20003   Field_tlo_Slot_inst_get,
  20004   Field_w_Slot_inst_get,
  20005   Field_y_Slot_inst_get,
  20006   Field_x_Slot_inst_get,
  20007   Field_t2_Slot_inst_get,
  20008   Field_s2_Slot_inst_get,
  20009   Field_r2_Slot_inst_get,
  20010   Field_t4_Slot_inst_get,
  20011   Field_s4_Slot_inst_get,
  20012   Field_r4_Slot_inst_get,
  20013   Field_t8_Slot_inst_get,
  20014   Field_r8_Slot_inst_get,
  20015   Field_xt_wbr15_imm_Slot_inst_get,
  20016   Field_xt_wbr18_imm_Slot_inst_get,
  20017   Field_bitindex_Slot_inst_get,
  20018   Field_s3to1_Slot_inst_get,
  20019   Implicit_Field_ar0_get,
  20020   Implicit_Field_ar4_get,
  20021   Implicit_Field_ar8_get,
  20022   Implicit_Field_ar12_get,
  20023   Implicit_Field_mr0_get,
  20024   Implicit_Field_mr1_get,
  20025   Implicit_Field_mr2_get,
  20026   Implicit_Field_mr3_get,
  20027   Implicit_Field_bt16_get,
  20028   Implicit_Field_bs16_get,
  20029   Implicit_Field_br16_get,
  20030   Implicit_Field_brall_get
  20031 };
  20032 
  20033 static xtensa_set_field_fn
  20034 Slot_inst_set_field_fns[] = {
  20035   Field_t_Slot_inst_set,
  20036   Field_bbi4_Slot_inst_set,
  20037   Field_bbi_Slot_inst_set,
  20038   Field_imm12_Slot_inst_set,
  20039   Field_imm8_Slot_inst_set,
  20040   Field_s_Slot_inst_set,
  20041   Field_s8_Slot_inst_set,
  20042   Field_imms8_Slot_inst_set,
  20043   Field_imm12b_Slot_inst_set,
  20044   Field_imm16_Slot_inst_set,
  20045   Field_m_Slot_inst_set,
  20046   Field_n_Slot_inst_set,
  20047   Field_offset_Slot_inst_set,
  20048   Field_op0_Slot_inst_set,
  20049   Field_op1_Slot_inst_set,
  20050   Field_op2_Slot_inst_set,
  20051   Field_r_Slot_inst_set,
  20052   Field_r_disp_Slot_inst_set,
  20053   Field_r_3_Slot_inst_set,
  20054   Field_sa4_Slot_inst_set,
  20055   Field_sae4_Slot_inst_set,
  20056   Field_sae_Slot_inst_set,
  20057   Field_sal_Slot_inst_set,
  20058   Field_sargt_Slot_inst_set,
  20059   Field_sas4_Slot_inst_set,
  20060   Field_sas_Slot_inst_set,
  20061   Field_sr_Slot_inst_set,
  20062   Field_st_Slot_inst_set,
  20063   Field_thi3_Slot_inst_set,
  20064   Field_imm4_Slot_inst_set,
  20065   Field_mn_Slot_inst_set,
  20066   0,
  20067   0,
  20068   0,
  20069   0,
  20070   0,
  20071   0,
  20072   0,
  20073   0,
  20074   Field_r3_Slot_inst_set,
  20075   Field_rbit2_Slot_inst_set,
  20076   Field_rhi_Slot_inst_set,
  20077   Field_t3_Slot_inst_set,
  20078   Field_tbit2_Slot_inst_set,
  20079   Field_tlo_Slot_inst_set,
  20080   Field_w_Slot_inst_set,
  20081   Field_y_Slot_inst_set,
  20082   Field_x_Slot_inst_set,
  20083   Field_t2_Slot_inst_set,
  20084   Field_s2_Slot_inst_set,
  20085   Field_r2_Slot_inst_set,
  20086   Field_t4_Slot_inst_set,
  20087   Field_s4_Slot_inst_set,
  20088   Field_r4_Slot_inst_set,
  20089   Field_t8_Slot_inst_set,
  20090   Field_r8_Slot_inst_set,
  20091   Field_xt_wbr15_imm_Slot_inst_set,
  20092   Field_xt_wbr18_imm_Slot_inst_set,
  20093   Field_bitindex_Slot_inst_set,
  20094   Field_s3to1_Slot_inst_set,
  20095   Implicit_Field_set,
  20096   Implicit_Field_set,
  20097   Implicit_Field_set,
  20098   Implicit_Field_set,
  20099   Implicit_Field_set,
  20100   Implicit_Field_set,
  20101   Implicit_Field_set,
  20102   Implicit_Field_set,
  20103   Implicit_Field_set,
  20104   Implicit_Field_set,
  20105   Implicit_Field_set,
  20106   Implicit_Field_set
  20107 };
  20108 
  20109 static xtensa_get_field_fn
  20110 Slot_inst16a_get_field_fns[] = {
  20111   Field_t_Slot_inst16a_get,
  20112   0,
  20113   0,
  20114   0,
  20115   0,
  20116   Field_s_Slot_inst16a_get,
  20117   0,
  20118   0,
  20119   0,
  20120   0,
  20121   0,
  20122   0,
  20123   0,
  20124   Field_op0_Slot_inst16a_get,
  20125   0,
  20126   0,
  20127   Field_r_Slot_inst16a_get,
  20128   0,
  20129   0,
  20130   0,
  20131   0,
  20132   0,
  20133   0,
  20134   0,
  20135   0,
  20136   0,
  20137   0,
  20138   0,
  20139   0,
  20140   0,
  20141   0,
  20142   Field_i_Slot_inst16a_get,
  20143   Field_imm6lo_Slot_inst16a_get,
  20144   Field_imm6hi_Slot_inst16a_get,
  20145   Field_imm7lo_Slot_inst16a_get,
  20146   Field_imm7hi_Slot_inst16a_get,
  20147   Field_z_Slot_inst16a_get,
  20148   0,
  20149   0,
  20150   0,
  20151   0,
  20152   0,
  20153   0,
  20154   0,
  20155   0,
  20156   0,
  20157   0,
  20158   0,
  20159   0,
  20160   0,
  20161   0,
  20162   0,
  20163   0,
  20164   0,
  20165   0,
  20166   0,
  20167   0,
  20168   0,
  20169   0,
  20170   0,
  20171   Implicit_Field_ar0_get,
  20172   Implicit_Field_ar4_get,
  20173   Implicit_Field_ar8_get,
  20174   Implicit_Field_ar12_get,
  20175   Implicit_Field_mr0_get,
  20176   Implicit_Field_mr1_get,
  20177   Implicit_Field_mr2_get,
  20178   Implicit_Field_mr3_get,
  20179   Implicit_Field_bt16_get,
  20180   Implicit_Field_bs16_get,
  20181   Implicit_Field_br16_get,
  20182   Implicit_Field_brall_get
  20183 };
  20184 
  20185 static xtensa_set_field_fn
  20186 Slot_inst16a_set_field_fns[] = {
  20187   Field_t_Slot_inst16a_set,
  20188   0,
  20189   0,
  20190   0,
  20191   0,
  20192   Field_s_Slot_inst16a_set,
  20193   0,
  20194   0,
  20195   0,
  20196   0,
  20197   0,
  20198   0,
  20199   0,
  20200   Field_op0_Slot_inst16a_set,
  20201   0,
  20202   0,
  20203   Field_r_Slot_inst16a_set,
  20204   0,
  20205   0,
  20206   0,
  20207   0,
  20208   0,
  20209   0,
  20210   0,
  20211   0,
  20212   0,
  20213   0,
  20214   0,
  20215   0,
  20216   0,
  20217   0,
  20218   Field_i_Slot_inst16a_set,
  20219   Field_imm6lo_Slot_inst16a_set,
  20220   Field_imm6hi_Slot_inst16a_set,
  20221   Field_imm7lo_Slot_inst16a_set,
  20222   Field_imm7hi_Slot_inst16a_set,
  20223   Field_z_Slot_inst16a_set,
  20224   0,
  20225   0,
  20226   0,
  20227   0,
  20228   0,
  20229   0,
  20230   0,
  20231   0,
  20232   0,
  20233   0,
  20234   0,
  20235   0,
  20236   0,
  20237   0,
  20238   0,
  20239   0,
  20240   0,
  20241   0,
  20242   0,
  20243   0,
  20244   0,
  20245   0,
  20246   0,
  20247   Implicit_Field_set,
  20248   Implicit_Field_set,
  20249   Implicit_Field_set,
  20250   Implicit_Field_set,
  20251   Implicit_Field_set,
  20252   Implicit_Field_set,
  20253   Implicit_Field_set,
  20254   Implicit_Field_set,
  20255   Implicit_Field_set,
  20256   Implicit_Field_set,
  20257   Implicit_Field_set,
  20258   Implicit_Field_set
  20259 };
  20260 
  20261 static xtensa_get_field_fn
  20262 Slot_inst16b_get_field_fns[] = {
  20263   Field_t_Slot_inst16b_get,
  20264   0,
  20265   0,
  20266   0,
  20267   0,
  20268   Field_s_Slot_inst16b_get,
  20269   0,
  20270   0,
  20271   0,
  20272   0,
  20273   0,
  20274   0,
  20275   0,
  20276   Field_op0_Slot_inst16b_get,
  20277   0,
  20278   0,
  20279   Field_r_Slot_inst16b_get,
  20280   0,
  20281   0,
  20282   0,
  20283   0,
  20284   0,
  20285   0,
  20286   0,
  20287   0,
  20288   0,
  20289   0,
  20290   0,
  20291   0,
  20292   0,
  20293   0,
  20294   Field_i_Slot_inst16b_get,
  20295   Field_imm6lo_Slot_inst16b_get,
  20296   Field_imm6hi_Slot_inst16b_get,
  20297   Field_imm7lo_Slot_inst16b_get,
  20298   Field_imm7hi_Slot_inst16b_get,
  20299   Field_z_Slot_inst16b_get,
  20300   Field_imm6_Slot_inst16b_get,
  20301   Field_imm7_Slot_inst16b_get,
  20302   0,
  20303   0,
  20304   0,
  20305   0,
  20306   0,
  20307   0,
  20308   0,
  20309   0,
  20310   0,
  20311   0,
  20312   0,
  20313   0,
  20314   0,
  20315   0,
  20316   0,
  20317   0,
  20318   0,
  20319   0,
  20320   0,
  20321   0,
  20322   0,
  20323   Implicit_Field_ar0_get,
  20324   Implicit_Field_ar4_get,
  20325   Implicit_Field_ar8_get,
  20326   Implicit_Field_ar12_get,
  20327   Implicit_Field_mr0_get,
  20328   Implicit_Field_mr1_get,
  20329   Implicit_Field_mr2_get,
  20330   Implicit_Field_mr3_get,
  20331   Implicit_Field_bt16_get,
  20332   Implicit_Field_bs16_get,
  20333   Implicit_Field_br16_get,
  20334   Implicit_Field_brall_get
  20335 };
  20336 
  20337 static xtensa_set_field_fn
  20338 Slot_inst16b_set_field_fns[] = {
  20339   Field_t_Slot_inst16b_set,
  20340   0,
  20341   0,
  20342   0,
  20343   0,
  20344   Field_s_Slot_inst16b_set,
  20345   0,
  20346   0,
  20347   0,
  20348   0,
  20349   0,
  20350   0,
  20351   0,
  20352   Field_op0_Slot_inst16b_set,
  20353   0,
  20354   0,
  20355   Field_r_Slot_inst16b_set,
  20356   0,
  20357   0,
  20358   0,
  20359   0,
  20360   0,
  20361   0,
  20362   0,
  20363   0,
  20364   0,
  20365   0,
  20366   0,
  20367   0,
  20368   0,
  20369   0,
  20370   Field_i_Slot_inst16b_set,
  20371   Field_imm6lo_Slot_inst16b_set,
  20372   Field_imm6hi_Slot_inst16b_set,
  20373   Field_imm7lo_Slot_inst16b_set,
  20374   Field_imm7hi_Slot_inst16b_set,
  20375   Field_z_Slot_inst16b_set,
  20376   Field_imm6_Slot_inst16b_set,
  20377   Field_imm7_Slot_inst16b_set,
  20378   0,
  20379   0,
  20380   0,
  20381   0,
  20382   0,
  20383   0,
  20384   0,
  20385   0,
  20386   0,
  20387   0,
  20388   0,
  20389   0,
  20390   0,
  20391   0,
  20392   0,
  20393   0,
  20394   0,
  20395   0,
  20396   0,
  20397   0,
  20398   0,
  20399   Implicit_Field_set,
  20400   Implicit_Field_set,
  20401   Implicit_Field_set,
  20402   Implicit_Field_set,
  20403   Implicit_Field_set,
  20404   Implicit_Field_set,
  20405   Implicit_Field_set,
  20406   Implicit_Field_set,
  20407   Implicit_Field_set,
  20408   Implicit_Field_set,
  20409   Implicit_Field_set,
  20410   Implicit_Field_set
  20411 };
  20412 
  20413 static xtensa_slot_internal slots[] = {
  20414   { "Inst", "x24", 0,
  20415     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
  20416     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
  20417     Slot_inst_decode, "nop" },
  20418   { "Inst16a", "x16a", 0,
  20419     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
  20420     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
  20421     Slot_inst16a_decode, "" },
  20422   { "Inst16b", "x16b", 0,
  20423     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
  20424     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
  20425     Slot_inst16b_decode, "nop.n" }
  20426 };
  20427 
  20428 
  20429 /* Instruction formats.  */
  20430 
  20431 static void
  20432 Format_x24_encode (xtensa_insnbuf insn)
  20433 {
  20434   insn[0] = 0;
  20435 }
  20436 
  20437 static void
  20438 Format_x16a_encode (xtensa_insnbuf insn)
  20439 {
  20440   insn[0] = 0x8;
  20441 }
  20442 
  20443 static void
  20444 Format_x16b_encode (xtensa_insnbuf insn)
  20445 {
  20446   insn[0] = 0xc;
  20447 }
  20448 
  20449 static int Format_x24_slots[] = { 0 };
  20450 
  20451 static int Format_x16a_slots[] = { 1 };
  20452 
  20453 static int Format_x16b_slots[] = { 2 };
  20454 
  20455 static xtensa_format_internal formats[] = {
  20456   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
  20457   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
  20458   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
  20459 };
  20460 
  20461 
  20462 static int
  20463 format_decoder (const xtensa_insnbuf insn)
  20464 {
  20465   if ((insn[0] & 0x8) == 0)
  20466     return 0; /* x24 */
  20467   if ((insn[0] & 0xc) == 0x8)
  20468     return 1; /* x16a */
  20469   if ((insn[0] & 0xe) == 0xc)
  20470     return 2; /* x16b */
  20471   return -1;
  20472 }
  20473 
  20474 static int length_table[256] = {
  20475   3,
  20476   3,
  20477   3,
  20478   3,
  20479   3,
  20480   3,
  20481   3,
  20482   3,
  20483   2,
  20484   2,
  20485   2,
  20486   2,
  20487   2,
  20488   2,
  20489   -1,
  20490   -1,
  20491   3,
  20492   3,
  20493   3,
  20494   3,
  20495   3,
  20496   3,
  20497   3,
  20498   3,
  20499   2,
  20500   2,
  20501   2,
  20502   2,
  20503   2,
  20504   2,
  20505   -1,
  20506   -1,
  20507   3,
  20508   3,
  20509   3,
  20510   3,
  20511   3,
  20512   3,
  20513   3,
  20514   3,
  20515   2,
  20516   2,
  20517   2,
  20518   2,
  20519   2,
  20520   2,
  20521   -1,
  20522   -1,
  20523   3,
  20524   3,
  20525   3,
  20526   3,
  20527   3,
  20528   3,
  20529   3,
  20530   3,
  20531   2,
  20532   2,
  20533   2,
  20534   2,
  20535   2,
  20536   2,
  20537   -1,
  20538   -1,
  20539   3,
  20540   3,
  20541   3,
  20542   3,
  20543   3,
  20544   3,
  20545   3,
  20546   3,
  20547   2,
  20548   2,
  20549   2,
  20550   2,
  20551   2,
  20552   2,
  20553   -1,
  20554   -1,
  20555   3,
  20556   3,
  20557   3,
  20558   3,
  20559   3,
  20560   3,
  20561   3,
  20562   3,
  20563   2,
  20564   2,
  20565   2,
  20566   2,
  20567   2,
  20568   2,
  20569   -1,
  20570   -1,
  20571   3,
  20572   3,
  20573   3,
  20574   3,
  20575   3,
  20576   3,
  20577   3,
  20578   3,
  20579   2,
  20580   2,
  20581   2,
  20582   2,
  20583   2,
  20584   2,
  20585   -1,
  20586   -1,
  20587   3,
  20588   3,
  20589   3,
  20590   3,
  20591   3,
  20592   3,
  20593   3,
  20594   3,
  20595   2,
  20596   2,
  20597   2,
  20598   2,
  20599   2,
  20600   2,
  20601   -1,
  20602   -1,
  20603   3,
  20604   3,
  20605   3,
  20606   3,
  20607   3,
  20608   3,
  20609   3,
  20610   3,
  20611   2,
  20612   2,
  20613   2,
  20614   2,
  20615   2,
  20616   2,
  20617   -1,
  20618   -1,
  20619   3,
  20620   3,
  20621   3,
  20622   3,
  20623   3,
  20624   3,
  20625   3,
  20626   3,
  20627   2,
  20628   2,
  20629   2,
  20630   2,
  20631   2,
  20632   2,
  20633   -1,
  20634   -1,
  20635   3,
  20636   3,
  20637   3,
  20638   3,
  20639   3,
  20640   3,
  20641   3,
  20642   3,
  20643   2,
  20644   2,
  20645   2,
  20646   2,
  20647   2,
  20648   2,
  20649   -1,
  20650   -1,
  20651   3,
  20652   3,
  20653   3,
  20654   3,
  20655   3,
  20656   3,
  20657   3,
  20658   3,
  20659   2,
  20660   2,
  20661   2,
  20662   2,
  20663   2,
  20664   2,
  20665   -1,
  20666   -1,
  20667   3,
  20668   3,
  20669   3,
  20670   3,
  20671   3,
  20672   3,
  20673   3,
  20674   3,
  20675   2,
  20676   2,
  20677   2,
  20678   2,
  20679   2,
  20680   2,
  20681   -1,
  20682   -1,
  20683   3,
  20684   3,
  20685   3,
  20686   3,
  20687   3,
  20688   3,
  20689   3,
  20690   3,
  20691   2,
  20692   2,
  20693   2,
  20694   2,
  20695   2,
  20696   2,
  20697   -1,
  20698   -1,
  20699   3,
  20700   3,
  20701   3,
  20702   3,
  20703   3,
  20704   3,
  20705   3,
  20706   3,
  20707   2,
  20708   2,
  20709   2,
  20710   2,
  20711   2,
  20712   2,
  20713   -1,
  20714   -1,
  20715   3,
  20716   3,
  20717   3,
  20718   3,
  20719   3,
  20720   3,
  20721   3,
  20722   3,
  20723   2,
  20724   2,
  20725   2,
  20726   2,
  20727   2,
  20728   2,
  20729   -1,
  20730   -1
  20731 };
  20732 
  20733 static int
  20734 length_decoder (const unsigned char *insn)
  20735 {
  20736   int l = insn[0];
  20737   return length_table[l];
  20738 }
  20739 
  20740 
  20741 /* Top-level ISA structure.  */
  20742 
  20743 xtensa_isa_internal xtensa_modules = {
  20744   0 /* little-endian */,
  20745   3 /* insn_size */, 0,
  20746   3, formats, format_decoder, length_decoder,
  20747   3, slots,
  20748   72 /* num_fields */,
  20749   132, operands,
  20750   444, iclasses,
  20751   579, opcodes, 0,
  20752   8, regfiles,
  20753   NUM_STATES, states, 0,
  20754   NUM_SYSREGS, sysregs, 0,
  20755   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
  20756   1, interfaces, 0,
  20757   1, funcUnits, 0
  20758 };
	qemu FORK: QEMU emulator
	git clone https://git.neptards.moe/neptards/qemu.git
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