xtensa-modules.c.inc - qemu - FORK: QEMU emulator

xtensa-modules.c.inc (360822B)
      1 /* Xtensa configuration-specific ISA information.
      2 
      3    Customer ID=4869; Build=0x2cfec; Copyright (c) 2003-2010 Tensilica Inc.
      4 
      5    Permission is hereby granted, free of charge, to any person obtaining
      6    a copy of this software and associated documentation files (the
      7    "Software"), to deal in the Software without restriction, including
      8    without limitation the rights to use, copy, modify, merge, publish,
      9    distribute, sublicense, and/or sell copies of the Software, and to
     10    permit persons to whom the Software is furnished to do so, subject to
     11    the following conditions:
     12 
     13    The above copyright notice and this permission notice shall be included
     14    in all copies or substantial portions of the Software.
     15 
     16    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
     17    EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     18    MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
     19    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
     20    CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     21    TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     22    SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
     23 
     24 #include "qemu/osdep.h"
     25 #include "xtensa-isa.h"
     26 #include "xtensa-isa-internal.h"
     27 
     28 
     29 /* Sysregs.  */
     30 
     31 static xtensa_sysreg_internal sysregs[] = {
     32   { "LBEG", 0, 0 },
     33   { "LEND", 1, 0 },
     34   { "LCOUNT", 2, 0 },
     35   { "ACCLO", 16, 0 },
     36   { "ACCHI", 17, 0 },
     37   { "M0", 32, 0 },
     38   { "M1", 33, 0 },
     39   { "M2", 34, 0 },
     40   { "M3", 35, 0 },
     41   { "PTEVADDR", 83, 0 },
     42   { "MMID", 89, 0 },
     43   { "DDR", 104, 0 },
     44   { "176", 176, 0 },
     45   { "208", 208, 0 },
     46   { "INTERRUPT", 226, 0 },
     47   { "INTCLEAR", 227, 0 },
     48   { "CCOUNT", 234, 0 },
     49   { "PRID", 235, 0 },
     50   { "ICOUNT", 236, 0 },
     51   { "CCOMPARE0", 240, 0 },
     52   { "CCOMPARE1", 241, 0 },
     53   { "CCOMPARE2", 242, 0 },
     54   { "VECBASE", 231, 0 },
     55   { "EPC1", 177, 0 },
     56   { "EPC2", 178, 0 },
     57   { "EPC3", 179, 0 },
     58   { "EPC4", 180, 0 },
     59   { "EPC5", 181, 0 },
     60   { "EPC6", 182, 0 },
     61   { "EPC7", 183, 0 },
     62   { "EXCSAVE1", 209, 0 },
     63   { "EXCSAVE2", 210, 0 },
     64   { "EXCSAVE3", 211, 0 },
     65   { "EXCSAVE4", 212, 0 },
     66   { "EXCSAVE5", 213, 0 },
     67   { "EXCSAVE6", 214, 0 },
     68   { "EXCSAVE7", 215, 0 },
     69   { "EPS2", 194, 0 },
     70   { "EPS3", 195, 0 },
     71   { "EPS4", 196, 0 },
     72   { "EPS5", 197, 0 },
     73   { "EPS6", 198, 0 },
     74   { "EPS7", 199, 0 },
     75   { "EXCCAUSE", 232, 0 },
     76   { "DEPC", 192, 0 },
     77   { "EXCVADDR", 238, 0 },
     78   { "WINDOWBASE", 72, 0 },
     79   { "WINDOWSTART", 73, 0 },
     80   { "SAR", 3, 0 },
     81   { "LITBASE", 5, 0 },
     82   { "PS", 230, 0 },
     83   { "MISC0", 244, 0 },
     84   { "MISC1", 245, 0 },
     85   { "INTENABLE", 228, 0 },
     86   { "DBREAKA0", 144, 0 },
     87   { "DBREAKC0", 160, 0 },
     88   { "DBREAKA1", 145, 0 },
     89   { "DBREAKC1", 161, 0 },
     90   { "IBREAKA0", 128, 0 },
     91   { "IBREAKA1", 129, 0 },
     92   { "IBREAKENABLE", 96, 0 },
     93   { "ICOUNTLEVEL", 237, 0 },
     94   { "DEBUGCAUSE", 233, 0 },
     95   { "RASID", 90, 0 },
     96   { "ITLBCFG", 91, 0 },
     97   { "DTLBCFG", 92, 0 },
     98   { "CPENABLE", 224, 0 },
     99   { "SCOMPARE1", 12, 0 },
    100   { "ATOMCTL", 99, 0 },
    101   { "THREADPTR", 231, 1 },
    102   { "EXPSTATE", 230, 1 }
    103 };
    104 
    105 #define NUM_SYSREGS 71
    106 #define MAX_SPECIAL_REG 245
    107 #define MAX_USER_REG 231
    108 
    109 
    110 /* Processor states.  */
    111 
    112 static xtensa_state_internal states[] = {
    113   { "LCOUNT", 32, 0 },
    114   { "PC", 32, 0 },
    115   { "ICOUNT", 32, 0 },
    116   { "DDR", 32, 0 },
    117   { "INTERRUPT", 22, 0 },
    118   { "CCOUNT", 32, 0 },
    119   { "XTSYNC", 1, 0 },
    120   { "VECBASE", 22, 0 },
    121   { "EPC1", 32, 0 },
    122   { "EPC2", 32, 0 },
    123   { "EPC3", 32, 0 },
    124   { "EPC4", 32, 0 },
    125   { "EPC5", 32, 0 },
    126   { "EPC6", 32, 0 },
    127   { "EPC7", 32, 0 },
    128   { "EXCSAVE1", 32, 0 },
    129   { "EXCSAVE2", 32, 0 },
    130   { "EXCSAVE3", 32, 0 },
    131   { "EXCSAVE4", 32, 0 },
    132   { "EXCSAVE5", 32, 0 },
    133   { "EXCSAVE6", 32, 0 },
    134   { "EXCSAVE7", 32, 0 },
    135   { "EPS2", 15, 0 },
    136   { "EPS3", 15, 0 },
    137   { "EPS4", 15, 0 },
    138   { "EPS5", 15, 0 },
    139   { "EPS6", 15, 0 },
    140   { "EPS7", 15, 0 },
    141   { "EXCCAUSE", 6, 0 },
    142   { "PSINTLEVEL", 4, 0 },
    143   { "PSUM", 1, 0 },
    144   { "PSWOE", 1, 0 },
    145   { "PSRING", 2, 0 },
    146   { "PSEXCM", 1, 0 },
    147   { "DEPC", 32, 0 },
    148   { "EXCVADDR", 32, 0 },
    149   { "WindowBase", 3, 0 },
    150   { "WindowStart", 8, 0 },
    151   { "PSCALLINC", 2, 0 },
    152   { "PSOWB", 4, 0 },
    153   { "LBEG", 32, 0 },
    154   { "LEND", 32, 0 },
    155   { "SAR", 6, 0 },
    156   { "THREADPTR", 32, 0 },
    157   { "LITBADDR", 20, 0 },
    158   { "LITBEN", 1, 0 },
    159   { "MISC0", 32, 0 },
    160   { "MISC1", 32, 0 },
    161   { "ACC", 40, 0 },
    162   { "InOCDMode", 1, 0 },
    163   { "INTENABLE", 22, 0 },
    164   { "DBREAKA0", 32, 0 },
    165   { "DBREAKC0", 8, 0 },
    166   { "DBREAKA1", 32, 0 },
    167   { "DBREAKC1", 8, 0 },
    168   { "IBREAKA0", 32, 0 },
    169   { "IBREAKA1", 32, 0 },
    170   { "IBREAKENABLE", 2, 0 },
    171   { "ICOUNTLEVEL", 4, 0 },
    172   { "DEBUGCAUSE", 6, 0 },
    173   { "DBNUM", 4, 0 },
    174   { "CCOMPARE0", 32, 0 },
    175   { "CCOMPARE1", 32, 0 },
    176   { "CCOMPARE2", 32, 0 },
    177   { "ASID3", 8, 0 },
    178   { "ASID2", 8, 0 },
    179   { "ASID1", 8, 0 },
    180   { "INSTPGSZID6", 1, 0 },
    181   { "INSTPGSZID5", 1, 0 },
    182   { "INSTPGSZID4", 2, 0 },
    183   { "DATAPGSZID6", 1, 0 },
    184   { "DATAPGSZID5", 1, 0 },
    185   { "DATAPGSZID4", 2, 0 },
    186   { "PTBASE", 10, 0 },
    187   { "CPENABLE", 8, 0 },
    188   { "SCOMPARE1", 32, 0 },
    189   { "ATOMCTL", 6, 0 },
    190   { "EXPSTATE", 32, XTENSA_STATE_IS_EXPORTED }
    191 };
    192 
    193 #define NUM_STATES 78
    194 
    195 enum xtensa_state_id {
    196   STATE_LCOUNT,
    197   STATE_PC,
    198   STATE_ICOUNT,
    199   STATE_DDR,
    200   STATE_INTERRUPT,
    201   STATE_CCOUNT,
    202   STATE_XTSYNC,
    203   STATE_VECBASE,
    204   STATE_EPC1,
    205   STATE_EPC2,
    206   STATE_EPC3,
    207   STATE_EPC4,
    208   STATE_EPC5,
    209   STATE_EPC6,
    210   STATE_EPC7,
    211   STATE_EXCSAVE1,
    212   STATE_EXCSAVE2,
    213   STATE_EXCSAVE3,
    214   STATE_EXCSAVE4,
    215   STATE_EXCSAVE5,
    216   STATE_EXCSAVE6,
    217   STATE_EXCSAVE7,
    218   STATE_EPS2,
    219   STATE_EPS3,
    220   STATE_EPS4,
    221   STATE_EPS5,
    222   STATE_EPS6,
    223   STATE_EPS7,
    224   STATE_EXCCAUSE,
    225   STATE_PSINTLEVEL,
    226   STATE_PSUM,
    227   STATE_PSWOE,
    228   STATE_PSRING,
    229   STATE_PSEXCM,
    230   STATE_DEPC,
    231   STATE_EXCVADDR,
    232   STATE_WindowBase,
    233   STATE_WindowStart,
    234   STATE_PSCALLINC,
    235   STATE_PSOWB,
    236   STATE_LBEG,
    237   STATE_LEND,
    238   STATE_SAR,
    239   STATE_THREADPTR,
    240   STATE_LITBADDR,
    241   STATE_LITBEN,
    242   STATE_MISC0,
    243   STATE_MISC1,
    244   STATE_ACC,
    245   STATE_InOCDMode,
    246   STATE_INTENABLE,
    247   STATE_DBREAKA0,
    248   STATE_DBREAKC0,
    249   STATE_DBREAKA1,
    250   STATE_DBREAKC1,
    251   STATE_IBREAKA0,
    252   STATE_IBREAKA1,
    253   STATE_IBREAKENABLE,
    254   STATE_ICOUNTLEVEL,
    255   STATE_DEBUGCAUSE,
    256   STATE_DBNUM,
    257   STATE_CCOMPARE0,
    258   STATE_CCOMPARE1,
    259   STATE_CCOMPARE2,
    260   STATE_ASID3,
    261   STATE_ASID2,
    262   STATE_ASID1,
    263   STATE_INSTPGSZID6,
    264   STATE_INSTPGSZID5,
    265   STATE_INSTPGSZID4,
    266   STATE_DATAPGSZID6,
    267   STATE_DATAPGSZID5,
    268   STATE_DATAPGSZID4,
    269   STATE_PTBASE,
    270   STATE_CPENABLE,
    271   STATE_SCOMPARE1,
    272   STATE_ATOMCTL,
    273   STATE_EXPSTATE
    274 };
    275 
    276 
    277 /* Field definitions.  */
    278 
    279 static unsigned
    280 Field_t_Slot_inst_get (const xtensa_insnbuf insn)
    281 {
    282   unsigned tie_t = 0;
    283   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    284   return tie_t;
    285 }
    286 
    287 static void
    288 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    289 {
    290   uint32 tie_t;
    291   tie_t = (val << 28) >> 28;
    292   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    293 }
    294 
    295 static unsigned
    296 Field_s_Slot_inst_get (const xtensa_insnbuf insn)
    297 {
    298   unsigned tie_t = 0;
    299   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    300   return tie_t;
    301 }
    302 
    303 static void
    304 Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    305 {
    306   uint32 tie_t;
    307   tie_t = (val << 28) >> 28;
    308   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    309 }
    310 
    311 static unsigned
    312 Field_r_Slot_inst_get (const xtensa_insnbuf insn)
    313 {
    314   unsigned tie_t = 0;
    315   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    316   return tie_t;
    317 }
    318 
    319 static void
    320 Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    321 {
    322   uint32 tie_t;
    323   tie_t = (val << 28) >> 28;
    324   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    325 }
    326 
    327 static unsigned
    328 Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
    329 {
    330   unsigned tie_t = 0;
    331   tie_t = (tie_t << 4) | ((insn[0] << 8) >> 28);
    332   return tie_t;
    333 }
    334 
    335 static void
    336 Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    337 {
    338   uint32 tie_t;
    339   tie_t = (val << 28) >> 28;
    340   insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
    341 }
    342 
    343 static unsigned
    344 Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
    345 {
    346   unsigned tie_t = 0;
    347   tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
    348   return tie_t;
    349 }
    350 
    351 static void
    352 Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    353 {
    354   uint32 tie_t;
    355   tie_t = (val << 28) >> 28;
    356   insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
    357 }
    358 
    359 static unsigned
    360 Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
    361 {
    362   unsigned tie_t = 0;
    363   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    364   return tie_t;
    365 }
    366 
    367 static void
    368 Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    369 {
    370   uint32 tie_t;
    371   tie_t = (val << 28) >> 28;
    372   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    373 }
    374 
    375 static unsigned
    376 Field_n_Slot_inst_get (const xtensa_insnbuf insn)
    377 {
    378   unsigned tie_t = 0;
    379   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    380   return tie_t;
    381 }
    382 
    383 static void
    384 Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    385 {
    386   uint32 tie_t;
    387   tie_t = (val << 30) >> 30;
    388   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    389 }
    390 
    391 static unsigned
    392 Field_m_Slot_inst_get (const xtensa_insnbuf insn)
    393 {
    394   unsigned tie_t = 0;
    395   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
    396   return tie_t;
    397 }
    398 
    399 static void
    400 Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    401 {
    402   uint32 tie_t;
    403   tie_t = (val << 30) >> 30;
    404   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
    405 }
    406 
    407 static unsigned
    408 Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
    409 {
    410   unsigned tie_t = 0;
    411   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    412   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    413   return tie_t;
    414 }
    415 
    416 static void
    417 Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    418 {
    419   uint32 tie_t;
    420   tie_t = (val << 28) >> 28;
    421   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    422   tie_t = (val << 24) >> 28;
    423   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    424 }
    425 
    426 static unsigned
    427 Field_st_Slot_inst_get (const xtensa_insnbuf insn)
    428 {
    429   unsigned tie_t = 0;
    430   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    431   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    432   return tie_t;
    433 }
    434 
    435 static void
    436 Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    437 {
    438   uint32 tie_t;
    439   tie_t = (val << 28) >> 28;
    440   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    441   tie_t = (val << 24) >> 28;
    442   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    443 }
    444 
    445 static unsigned
    446 Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
    447 {
    448   unsigned tie_t = 0;
    449   tie_t = (tie_t << 3) | ((insn[0] << 24) >> 29);
    450   return tie_t;
    451 }
    452 
    453 static void
    454 Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    455 {
    456   uint32 tie_t;
    457   tie_t = (val << 29) >> 29;
    458   insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
    459 }
    460 
    461 static unsigned
    462 Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
    463 {
    464   unsigned tie_t = 0;
    465   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    466   return tie_t;
    467 }
    468 
    469 static void
    470 Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    471 {
    472   uint32 tie_t;
    473   tie_t = (val << 31) >> 31;
    474   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    475 }
    476 
    477 static unsigned
    478 Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
    479 {
    480   unsigned tie_t = 0;
    481   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
    482   return tie_t;
    483 }
    484 
    485 static void
    486 Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    487 {
    488   uint32 tie_t;
    489   tie_t = (val << 30) >> 30;
    490   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
    491 }
    492 
    493 static unsigned
    494 Field_w_Slot_inst_get (const xtensa_insnbuf insn)
    495 {
    496   unsigned tie_t = 0;
    497   tie_t = (tie_t << 2) | ((insn[0] << 18) >> 30);
    498   return tie_t;
    499 }
    500 
    501 static void
    502 Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    503 {
    504   uint32 tie_t;
    505   tie_t = (val << 30) >> 30;
    506   insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
    507 }
    508 
    509 static unsigned
    510 Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
    511 {
    512   unsigned tie_t = 0;
    513   tie_t = (tie_t << 1) | ((insn[0] << 16) >> 31);
    514   return tie_t;
    515 }
    516 
    517 static void
    518 Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    519 {
    520   uint32 tie_t;
    521   tie_t = (val << 31) >> 31;
    522   insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
    523 }
    524 
    525 static unsigned
    526 Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
    527 {
    528   unsigned tie_t = 0;
    529   tie_t = (tie_t << 2) | ((insn[0] << 16) >> 30);
    530   return tie_t;
    531 }
    532 
    533 static void
    534 Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    535 {
    536   uint32 tie_t;
    537   tie_t = (val << 30) >> 30;
    538   insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
    539 }
    540 
    541 static unsigned
    542 Field_s3to1_Slot_inst_get (const xtensa_insnbuf insn)
    543 {
    544   unsigned tie_t = 0;
    545   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
    546   return tie_t;
    547 }
    548 
    549 static void
    550 Field_s3to1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    551 {
    552   uint32 tie_t;
    553   tie_t = (val << 29) >> 29;
    554   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
    555 }
    556 
    557 static unsigned
    558 Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
    559 {
    560   unsigned tie_t = 0;
    561   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    562   return tie_t;
    563 }
    564 
    565 static void
    566 Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    567 {
    568   uint32 tie_t;
    569   tie_t = (val << 28) >> 28;
    570   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    571 }
    572 
    573 static unsigned
    574 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
    575 {
    576   unsigned tie_t = 0;
    577   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    578   return tie_t;
    579 }
    580 
    581 static void
    582 Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    583 {
    584   uint32 tie_t;
    585   tie_t = (val << 28) >> 28;
    586   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    587 }
    588 
    589 static unsigned
    590 Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
    591 {
    592   unsigned tie_t = 0;
    593   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    594   return tie_t;
    595 }
    596 
    597 static void
    598 Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    599 {
    600   uint32 tie_t;
    601   tie_t = (val << 28) >> 28;
    602   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    603 }
    604 
    605 static unsigned
    606 Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
    607 {
    608   unsigned tie_t = 0;
    609   tie_t = (tie_t << 4) | ((insn[0] << 28) >> 28);
    610   return tie_t;
    611 }
    612 
    613 static void
    614 Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    615 {
    616   uint32 tie_t;
    617   tie_t = (val << 28) >> 28;
    618   insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
    619 }
    620 
    621 static unsigned
    622 Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
    623 {
    624   unsigned tie_t = 0;
    625   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
    626   return tie_t;
    627 }
    628 
    629 static void
    630 Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    631 {
    632   uint32 tie_t;
    633   tie_t = (val << 31) >> 31;
    634   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
    635 }
    636 
    637 static unsigned
    638 Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
    639 {
    640   unsigned tie_t = 0;
    641   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
    642   return tie_t;
    643 }
    644 
    645 static void
    646 Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    647 {
    648   uint32 tie_t;
    649   tie_t = (val << 31) >> 31;
    650   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
    651 }
    652 
    653 static unsigned
    654 Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
    655 {
    656   unsigned tie_t = 0;
    657   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    658   return tie_t;
    659 }
    660 
    661 static void
    662 Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    663 {
    664   uint32 tie_t;
    665   tie_t = (val << 28) >> 28;
    666   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    667 }
    668 
    669 static unsigned
    670 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
    671 {
    672   unsigned tie_t = 0;
    673   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    674   return tie_t;
    675 }
    676 
    677 static void
    678 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    679 {
    680   uint32 tie_t;
    681   tie_t = (val << 28) >> 28;
    682   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    683 }
    684 
    685 static unsigned
    686 Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
    687 {
    688   unsigned tie_t = 0;
    689   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    690   return tie_t;
    691 }
    692 
    693 static void
    694 Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    695 {
    696   uint32 tie_t;
    697   tie_t = (val << 31) >> 31;
    698   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    699 }
    700 
    701 static unsigned
    702 Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
    703 {
    704   unsigned tie_t = 0;
    705   tie_t = (tie_t << 1) | ((insn[0] << 19) >> 31);
    706   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    707   return tie_t;
    708 }
    709 
    710 static void
    711 Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    712 {
    713   uint32 tie_t;
    714   tie_t = (val << 28) >> 28;
    715   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    716   tie_t = (val << 27) >> 31;
    717   insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
    718 }
    719 
    720 static unsigned
    721 Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
    722 {
    723   unsigned tie_t = 0;
    724   tie_t = (tie_t << 12) | ((insn[0] << 8) >> 20);
    725   return tie_t;
    726 }
    727 
    728 static void
    729 Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    730 {
    731   uint32 tie_t;
    732   tie_t = (val << 20) >> 20;
    733   insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
    734 }
    735 
    736 static unsigned
    737 Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
    738 {
    739   unsigned tie_t = 0;
    740   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    741   return tie_t;
    742 }
    743 
    744 static void
    745 Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    746 {
    747   uint32 tie_t;
    748   tie_t = (val << 24) >> 24;
    749   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    750 }
    751 
    752 static unsigned
    753 Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
    754 {
    755   unsigned tie_t = 0;
    756   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    757   return tie_t;
    758 }
    759 
    760 static void
    761 Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    762 {
    763   uint32 tie_t;
    764   tie_t = (val << 28) >> 28;
    765   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    766 }
    767 
    768 static unsigned
    769 Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
    770 {
    771   unsigned tie_t = 0;
    772   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    773   tie_t = (tie_t << 8) | ((insn[0] << 8) >> 24);
    774   return tie_t;
    775 }
    776 
    777 static void
    778 Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    779 {
    780   uint32 tie_t;
    781   tie_t = (val << 24) >> 24;
    782   insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
    783   tie_t = (val << 20) >> 28;
    784   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    785 }
    786 
    787 static unsigned
    788 Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
    789 {
    790   unsigned tie_t = 0;
    791   tie_t = (tie_t << 16) | ((insn[0] << 8) >> 16);
    792   return tie_t;
    793 }
    794 
    795 static void
    796 Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    797 {
    798   uint32 tie_t;
    799   tie_t = (val << 16) >> 16;
    800   insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
    801 }
    802 
    803 static unsigned
    804 Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
    805 {
    806   unsigned tie_t = 0;
    807   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
    808   return tie_t;
    809 }
    810 
    811 static void
    812 Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    813 {
    814   uint32 tie_t;
    815   tie_t = (val << 14) >> 14;
    816   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
    817 }
    818 
    819 static unsigned
    820 Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
    821 {
    822   unsigned tie_t = 0;
    823   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    824   return tie_t;
    825 }
    826 
    827 static void
    828 Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    829 {
    830   uint32 tie_t;
    831   tie_t = (val << 28) >> 28;
    832   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    833 }
    834 
    835 static unsigned
    836 Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
    837 {
    838   unsigned tie_t = 0;
    839   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    840   return tie_t;
    841 }
    842 
    843 static void
    844 Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    845 {
    846   uint32 tie_t;
    847   tie_t = (val << 31) >> 31;
    848   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    849 }
    850 
    851 static unsigned
    852 Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
    853 {
    854   unsigned tie_t = 0;
    855   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    856   return tie_t;
    857 }
    858 
    859 static void
    860 Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    861 {
    862   uint32 tie_t;
    863   tie_t = (val << 31) >> 31;
    864   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    865 }
    866 
    867 static unsigned
    868 Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
    869 {
    870   unsigned tie_t = 0;
    871   tie_t = (tie_t << 1) | ((insn[0] << 15) >> 31);
    872   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    873   return tie_t;
    874 }
    875 
    876 static void
    877 Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    878 {
    879   uint32 tie_t;
    880   tie_t = (val << 28) >> 28;
    881   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    882   tie_t = (val << 27) >> 31;
    883   insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
    884 }
    885 
    886 static unsigned
    887 Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
    888 {
    889   unsigned tie_t = 0;
    890   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    891   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
    892   return tie_t;
    893 }
    894 
    895 static void
    896 Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    897 {
    898   uint32 tie_t;
    899   tie_t = (val << 28) >> 28;
    900   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
    901   tie_t = (val << 27) >> 31;
    902   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    903 }
    904 
    905 static unsigned
    906 Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
    907 {
    908   unsigned tie_t = 0;
    909   tie_t = (tie_t << 1) | ((insn[0] << 11) >> 31);
    910   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    911   return tie_t;
    912 }
    913 
    914 static void
    915 Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    916 {
    917   uint32 tie_t;
    918   tie_t = (val << 28) >> 28;
    919   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    920   tie_t = (val << 27) >> 31;
    921   insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
    922 }
    923 
    924 static unsigned
    925 Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
    926 {
    927   unsigned tie_t = 0;
    928   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
    929   return tie_t;
    930 }
    931 
    932 static void
    933 Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    934 {
    935   uint32 tie_t;
    936   tie_t = (val << 31) >> 31;
    937   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
    938 }
    939 
    940 static unsigned
    941 Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
    942 {
    943   unsigned tie_t = 0;
    944   tie_t = (tie_t << 1) | ((insn[0] << 27) >> 31);
    945   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    946   return tie_t;
    947 }
    948 
    949 static void
    950 Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
    951 {
    952   uint32 tie_t;
    953   tie_t = (val << 28) >> 28;
    954   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    955   tie_t = (val << 27) >> 31;
    956   insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
    957 }
    958 
    959 static unsigned
    960 Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
    961 {
    962   unsigned tie_t = 0;
    963   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    964   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    965   return tie_t;
    966 }
    967 
    968 static void
    969 Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
    970 {
    971   uint32 tie_t;
    972   tie_t = (val << 28) >> 28;
    973   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    974   tie_t = (val << 24) >> 28;
    975   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    976 }
    977 
    978 static unsigned
    979 Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
    980 {
    981   unsigned tie_t = 0;
    982   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
    983   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
    984   return tie_t;
    985 }
    986 
    987 static void
    988 Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
    989 {
    990   uint32 tie_t;
    991   tie_t = (val << 28) >> 28;
    992   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
    993   tie_t = (val << 24) >> 28;
    994   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
    995 }
    996 
    997 static unsigned
    998 Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
    999 {
   1000   unsigned tie_t = 0;
   1001   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
   1002   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1003   return tie_t;
   1004 }
   1005 
   1006 static void
   1007 Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1008 {
   1009   uint32 tie_t;
   1010   tie_t = (val << 28) >> 28;
   1011   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1012   tie_t = (val << 24) >> 28;
   1013   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
   1014 }
   1015 
   1016 static unsigned
   1017 Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
   1018 {
   1019   unsigned tie_t = 0;
   1020   tie_t = (tie_t << 4) | ((insn[0] << 20) >> 28);
   1021   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1022   return tie_t;
   1023 }
   1024 
   1025 static void
   1026 Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1027 {
   1028   uint32 tie_t;
   1029   tie_t = (val << 28) >> 28;
   1030   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1031   tie_t = (val << 24) >> 28;
   1032   insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
   1033 }
   1034 
   1035 static unsigned
   1036 Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
   1037 {
   1038   unsigned tie_t = 0;
   1039   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1040   return tie_t;
   1041 }
   1042 
   1043 static void
   1044 Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1045 {
   1046   uint32 tie_t;
   1047   tie_t = (val << 28) >> 28;
   1048   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1049 }
   1050 
   1051 static unsigned
   1052 Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
   1053 {
   1054   unsigned tie_t = 0;
   1055   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1056   return tie_t;
   1057 }
   1058 
   1059 static void
   1060 Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1061 {
   1062   uint32 tie_t;
   1063   tie_t = (val << 28) >> 28;
   1064   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1065 }
   1066 
   1067 static unsigned
   1068 Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
   1069 {
   1070   unsigned tie_t = 0;
   1071   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1072   return tie_t;
   1073 }
   1074 
   1075 static void
   1076 Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1077 {
   1078   uint32 tie_t;
   1079   tie_t = (val << 28) >> 28;
   1080   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1081 }
   1082 
   1083 static unsigned
   1084 Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
   1085 {
   1086   unsigned tie_t = 0;
   1087   tie_t = (tie_t << 2) | ((insn[0] << 24) >> 30);
   1088   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1089   return tie_t;
   1090 }
   1091 
   1092 static void
   1093 Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1094 {
   1095   uint32 tie_t;
   1096   tie_t = (val << 30) >> 30;
   1097   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1098   tie_t = (val << 28) >> 30;
   1099   insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
   1100 }
   1101 
   1102 static unsigned
   1103 Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
   1104 {
   1105   unsigned tie_t = 0;
   1106   tie_t = (tie_t << 1) | ((insn[0] << 24) >> 31);
   1107   return tie_t;
   1108 }
   1109 
   1110 static void
   1111 Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1112 {
   1113   uint32 tie_t;
   1114   tie_t = (val << 31) >> 31;
   1115   insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
   1116 }
   1117 
   1118 static unsigned
   1119 Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
   1120 {
   1121   unsigned tie_t = 0;
   1122   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1123   return tie_t;
   1124 }
   1125 
   1126 static void
   1127 Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1128 {
   1129   uint32 tie_t;
   1130   tie_t = (val << 28) >> 28;
   1131   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1132 }
   1133 
   1134 static unsigned
   1135 Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1136 {
   1137   unsigned tie_t = 0;
   1138   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1139   return tie_t;
   1140 }
   1141 
   1142 static void
   1143 Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1144 {
   1145   uint32 tie_t;
   1146   tie_t = (val << 28) >> 28;
   1147   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1148 }
   1149 
   1150 static unsigned
   1151 Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1152 {
   1153   unsigned tie_t = 0;
   1154   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1155   return tie_t;
   1156 }
   1157 
   1158 static void
   1159 Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1160 {
   1161   uint32 tie_t;
   1162   tie_t = (val << 30) >> 30;
   1163   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1164 }
   1165 
   1166 static unsigned
   1167 Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1168 {
   1169   unsigned tie_t = 0;
   1170   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1171   return tie_t;
   1172 }
   1173 
   1174 static void
   1175 Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1176 {
   1177   uint32 tie_t;
   1178   tie_t = (val << 30) >> 30;
   1179   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1180 }
   1181 
   1182 static unsigned
   1183 Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
   1184 {
   1185   unsigned tie_t = 0;
   1186   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1187   return tie_t;
   1188 }
   1189 
   1190 static void
   1191 Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1192 {
   1193   uint32 tie_t;
   1194   tie_t = (val << 28) >> 28;
   1195   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1196 }
   1197 
   1198 static unsigned
   1199 Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
   1200 {
   1201   unsigned tie_t = 0;
   1202   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1203   return tie_t;
   1204 }
   1205 
   1206 static void
   1207 Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1208 {
   1209   uint32 tie_t;
   1210   tie_t = (val << 28) >> 28;
   1211   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1212 }
   1213 
   1214 static unsigned
   1215 Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
   1216 {
   1217   unsigned tie_t = 0;
   1218   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1219   return tie_t;
   1220 }
   1221 
   1222 static void
   1223 Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1224 {
   1225   uint32 tie_t;
   1226   tie_t = (val << 29) >> 29;
   1227   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1228 }
   1229 
   1230 static unsigned
   1231 Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
   1232 {
   1233   unsigned tie_t = 0;
   1234   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1235   return tie_t;
   1236 }
   1237 
   1238 static void
   1239 Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1240 {
   1241   uint32 tie_t;
   1242   tie_t = (val << 29) >> 29;
   1243   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1244 }
   1245 
   1246 static unsigned
   1247 Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
   1248 {
   1249   unsigned tie_t = 0;
   1250   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1251   return tie_t;
   1252 }
   1253 
   1254 static void
   1255 Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1256 {
   1257   uint32 tie_t;
   1258   tie_t = (val << 31) >> 31;
   1259   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1260 }
   1261 
   1262 static unsigned
   1263 Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
   1264 {
   1265   unsigned tie_t = 0;
   1266   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1267   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1268   return tie_t;
   1269 }
   1270 
   1271 static void
   1272 Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1273 {
   1274   uint32 tie_t;
   1275   tie_t = (val << 28) >> 28;
   1276   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1277   tie_t = (val << 26) >> 30;
   1278   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1279 }
   1280 
   1281 static unsigned
   1282 Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
   1283 {
   1284   unsigned tie_t = 0;
   1285   tie_t = (tie_t << 2) | ((insn[0] << 26) >> 30);
   1286   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1287   return tie_t;
   1288 }
   1289 
   1290 static void
   1291 Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1292 {
   1293   uint32 tie_t;
   1294   tie_t = (val << 28) >> 28;
   1295   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1296   tie_t = (val << 26) >> 30;
   1297   insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
   1298 }
   1299 
   1300 static unsigned
   1301 Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
   1302 {
   1303   unsigned tie_t = 0;
   1304   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1305   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1306   return tie_t;
   1307 }
   1308 
   1309 static void
   1310 Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1311 {
   1312   uint32 tie_t;
   1313   tie_t = (val << 28) >> 28;
   1314   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1315   tie_t = (val << 25) >> 29;
   1316   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1317 }
   1318 
   1319 static unsigned
   1320 Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
   1321 {
   1322   unsigned tie_t = 0;
   1323   tie_t = (tie_t << 3) | ((insn[0] << 25) >> 29);
   1324   tie_t = (tie_t << 4) | ((insn[0] << 16) >> 28);
   1325   return tie_t;
   1326 }
   1327 
   1328 static void
   1329 Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1330 {
   1331   uint32 tie_t;
   1332   tie_t = (val << 28) >> 28;
   1333   insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
   1334   tie_t = (val << 25) >> 29;
   1335   insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
   1336 }
   1337 
   1338 static unsigned
   1339 Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
   1340 {
   1341   unsigned tie_t = 0;
   1342   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
   1343   return tie_t;
   1344 }
   1345 
   1346 static void
   1347 Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1348 {
   1349   uint32 tie_t;
   1350   tie_t = (val << 31) >> 31;
   1351   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
   1352 }
   1353 
   1354 static unsigned
   1355 Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
   1356 {
   1357   unsigned tie_t = 0;
   1358   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1359   return tie_t;
   1360 }
   1361 
   1362 static void
   1363 Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1364 {
   1365   uint32 tie_t;
   1366   tie_t = (val << 31) >> 31;
   1367   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1368 }
   1369 
   1370 static unsigned
   1371 Field_y_Slot_inst_get (const xtensa_insnbuf insn)
   1372 {
   1373   unsigned tie_t = 0;
   1374   tie_t = (tie_t << 1) | ((insn[0] << 25) >> 31);
   1375   return tie_t;
   1376 }
   1377 
   1378 static void
   1379 Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1380 {
   1381   uint32 tie_t;
   1382   tie_t = (val << 31) >> 31;
   1383   insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
   1384 }
   1385 
   1386 static unsigned
   1387 Field_x_Slot_inst_get (const xtensa_insnbuf insn)
   1388 {
   1389   unsigned tie_t = 0;
   1390   tie_t = (tie_t << 1) | ((insn[0] << 17) >> 31);
   1391   return tie_t;
   1392 }
   1393 
   1394 static void
   1395 Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1396 {
   1397   uint32 tie_t;
   1398   tie_t = (val << 31) >> 31;
   1399   insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
   1400 }
   1401 
   1402 static unsigned
   1403 Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1404 {
   1405   unsigned tie_t = 0;
   1406   tie_t = (tie_t << 15) | ((insn[0] << 8) >> 17);
   1407   return tie_t;
   1408 }
   1409 
   1410 static void
   1411 Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1412 {
   1413   uint32 tie_t;
   1414   tie_t = (val << 17) >> 17;
   1415   insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
   1416 }
   1417 
   1418 static unsigned
   1419 Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
   1420 {
   1421   unsigned tie_t = 0;
   1422   tie_t = (tie_t << 18) | ((insn[0] << 8) >> 14);
   1423   return tie_t;
   1424 }
   1425 
   1426 static void
   1427 Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1428 {
   1429   uint32 tie_t;
   1430   tie_t = (val << 14) >> 14;
   1431   insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
   1432 }
   1433 
   1434 static unsigned
   1435 Field_bitindex_Slot_inst_get (const xtensa_insnbuf insn)
   1436 {
   1437   unsigned tie_t = 0;
   1438   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1439   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1440   return tie_t;
   1441 }
   1442 
   1443 static void
   1444 Field_bitindex_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   1445 {
   1446   uint32 tie_t;
   1447   tie_t = (val << 28) >> 28;
   1448   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1449   tie_t = (val << 27) >> 31;
   1450   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1451 }
   1452 
   1453 static unsigned
   1454 Field_bitindex_Slot_inst16a_get (const xtensa_insnbuf insn)
   1455 {
   1456   unsigned tie_t = 0;
   1457   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1458   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1459   return tie_t;
   1460 }
   1461 
   1462 static void
   1463 Field_bitindex_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1464 {
   1465   uint32 tie_t;
   1466   tie_t = (val << 28) >> 28;
   1467   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1468   tie_t = (val << 27) >> 31;
   1469   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1470 }
   1471 
   1472 static unsigned
   1473 Field_bitindex_Slot_inst16b_get (const xtensa_insnbuf insn)
   1474 {
   1475   unsigned tie_t = 0;
   1476   tie_t = (tie_t << 1) | ((insn[0] << 23) >> 31);
   1477   tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28);
   1478   return tie_t;
   1479 }
   1480 
   1481 static void
   1482 Field_bitindex_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1483 {
   1484   uint32 tie_t;
   1485   tie_t = (val << 28) >> 28;
   1486   insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
   1487   tie_t = (val << 27) >> 31;
   1488   insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
   1489 }
   1490 
   1491 static unsigned
   1492 Field_s3to1_Slot_inst16a_get (const xtensa_insnbuf insn)
   1493 {
   1494   unsigned tie_t = 0;
   1495   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
   1496   return tie_t;
   1497 }
   1498 
   1499 static void
   1500 Field_s3to1_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
   1501 {
   1502   uint32 tie_t;
   1503   tie_t = (val << 29) >> 29;
   1504   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
   1505 }
   1506 
   1507 static unsigned
   1508 Field_s3to1_Slot_inst16b_get (const xtensa_insnbuf insn)
   1509 {
   1510   unsigned tie_t = 0;
   1511   tie_t = (tie_t << 3) | ((insn[0] << 20) >> 29);
   1512   return tie_t;
   1513 }
   1514 
   1515 static void
   1516 Field_s3to1_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
   1517 {
   1518   uint32 tie_t;
   1519   tie_t = (val << 29) >> 29;
   1520   insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
   1521 }
   1522 
   1523 static void
   1524 Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
   1525 		    uint32 val ATTRIBUTE_UNUSED)
   1526 {
   1527   /* Do nothing.  */
   1528 }
   1529 
   1530 static unsigned
   1531 Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1532 {
   1533   return 0;
   1534 }
   1535 
   1536 static unsigned
   1537 Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1538 {
   1539   return 4;
   1540 }
   1541 
   1542 static unsigned
   1543 Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1544 {
   1545   return 8;
   1546 }
   1547 
   1548 static unsigned
   1549 Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1550 {
   1551   return 12;
   1552 }
   1553 
   1554 static unsigned
   1555 Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1556 {
   1557   return 0;
   1558 }
   1559 
   1560 static unsigned
   1561 Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1562 {
   1563   return 1;
   1564 }
   1565 
   1566 static unsigned
   1567 Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1568 {
   1569   return 2;
   1570 }
   1571 
   1572 static unsigned
   1573 Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
   1574 {
   1575   return 3;
   1576 }
   1577 
   1578 enum xtensa_field_id {
   1579   FIELD_t,
   1580   FIELD_bbi4,
   1581   FIELD_bbi,
   1582   FIELD_imm12,
   1583   FIELD_imm8,
   1584   FIELD_s,
   1585   FIELD_imm12b,
   1586   FIELD_imm16,
   1587   FIELD_m,
   1588   FIELD_n,
   1589   FIELD_offset,
   1590   FIELD_op0,
   1591   FIELD_op1,
   1592   FIELD_op2,
   1593   FIELD_r,
   1594   FIELD_sa4,
   1595   FIELD_sae4,
   1596   FIELD_sae,
   1597   FIELD_sal,
   1598   FIELD_sargt,
   1599   FIELD_sas4,
   1600   FIELD_sas,
   1601   FIELD_sr,
   1602   FIELD_st,
   1603   FIELD_thi3,
   1604   FIELD_imm4,
   1605   FIELD_mn,
   1606   FIELD_i,
   1607   FIELD_imm6lo,
   1608   FIELD_imm6hi,
   1609   FIELD_imm7lo,
   1610   FIELD_imm7hi,
   1611   FIELD_z,
   1612   FIELD_imm6,
   1613   FIELD_imm7,
   1614   FIELD_r3,
   1615   FIELD_rbit2,
   1616   FIELD_rhi,
   1617   FIELD_t3,
   1618   FIELD_tbit2,
   1619   FIELD_tlo,
   1620   FIELD_w,
   1621   FIELD_y,
   1622   FIELD_x,
   1623   FIELD_xt_wbr15_imm,
   1624   FIELD_xt_wbr18_imm,
   1625   FIELD_bitindex,
   1626   FIELD_s3to1,
   1627   FIELD__ar0,
   1628   FIELD__ar4,
   1629   FIELD__ar8,
   1630   FIELD__ar12,
   1631   FIELD__mr0,
   1632   FIELD__mr1,
   1633   FIELD__mr2,
   1634   FIELD__mr3
   1635 };
   1636 
   1637 
   1638 /* Functional units.  */
   1639 
   1640 static xtensa_funcUnit_internal funcUnits[] = {
   1641 
   1642 };
   1643 
   1644 
   1645 /* Register files.  */
   1646 
   1647 enum xtensa_regfile_id {
   1648   REGFILE_AR,
   1649   REGFILE_MR
   1650 };
   1651 
   1652 static xtensa_regfile_internal regfiles[] = {
   1653   { "AR", "a", REGFILE_AR, 32, 32 },
   1654   { "MR", "m", REGFILE_MR, 32, 4 }
   1655 };
   1656 
   1657 
   1658 /* Interfaces.  */
   1659 
   1660 static xtensa_interface_internal interfaces[] = {
   1661   { "IMPWIRE", 32, 0, 0, 'i' }
   1662 };
   1663 
   1664 enum xtensa_interface_id {
   1665   INTERFACE_IMPWIRE
   1666 };
   1667 
   1668 
   1669 /* Constant tables.  */
   1670 
   1671 /* constant table ai4c */
   1672 static const unsigned CONST_TBL_ai4c_0[] = {
   1673   0xffffffff,
   1674   0x1,
   1675   0x2,
   1676   0x3,
   1677   0x4,
   1678   0x5,
   1679   0x6,
   1680   0x7,
   1681   0x8,
   1682   0x9,
   1683   0xa,
   1684   0xb,
   1685   0xc,
   1686   0xd,
   1687   0xe,
   1688   0xf,
   1689   0
   1690 };
   1691 
   1692 /* constant table b4c */
   1693 static const unsigned CONST_TBL_b4c_0[] = {
   1694   0xffffffff,
   1695   0x1,
   1696   0x2,
   1697   0x3,
   1698   0x4,
   1699   0x5,
   1700   0x6,
   1701   0x7,
   1702   0x8,
   1703   0xa,
   1704   0xc,
   1705   0x10,
   1706   0x20,
   1707   0x40,
   1708   0x80,
   1709   0x100,
   1710   0
   1711 };
   1712 
   1713 /* constant table b4cu */
   1714 static const unsigned CONST_TBL_b4cu_0[] = {
   1715   0x8000,
   1716   0x10000,
   1717   0x2,
   1718   0x3,
   1719   0x4,
   1720   0x5,
   1721   0x6,
   1722   0x7,
   1723   0x8,
   1724   0xa,
   1725   0xc,
   1726   0x10,
   1727   0x20,
   1728   0x40,
   1729   0x80,
   1730   0x100,
   1731   0
   1732 };
   1733 
   1734 
   1735 /* Instruction operands.  */
   1736 
   1737 static int
   1738 Operand_soffsetx4_decode (uint32 *valp)
   1739 {
   1740   unsigned soffsetx4_0, offset_0;
   1741   offset_0 = *valp & 0x3ffff;
   1742   soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
   1743   *valp = soffsetx4_0;
   1744   return 0;
   1745 }
   1746 
   1747 static int
   1748 Operand_soffsetx4_encode (uint32 *valp)
   1749 {
   1750   unsigned offset_0, soffsetx4_0;
   1751   soffsetx4_0 = *valp;
   1752   offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
   1753   *valp = offset_0;
   1754   return 0;
   1755 }
   1756 
   1757 static int
   1758 Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
   1759 {
   1760   *valp -= (pc & ~0x3);
   1761   return 0;
   1762 }
   1763 
   1764 static int
   1765 Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
   1766 {
   1767   *valp += (pc & ~0x3);
   1768   return 0;
   1769 }
   1770 
   1771 static int
   1772 Operand_uimm12x8_decode (uint32 *valp)
   1773 {
   1774   unsigned uimm12x8_0, imm12_0;
   1775   imm12_0 = *valp & 0xfff;
   1776   uimm12x8_0 = imm12_0 << 3;
   1777   *valp = uimm12x8_0;
   1778   return 0;
   1779 }
   1780 
   1781 static int
   1782 Operand_uimm12x8_encode (uint32 *valp)
   1783 {
   1784   unsigned imm12_0, uimm12x8_0;
   1785   uimm12x8_0 = *valp;
   1786   imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
   1787   *valp = imm12_0;
   1788   return 0;
   1789 }
   1790 
   1791 static int
   1792 Operand_simm4_decode (uint32 *valp)
   1793 {
   1794   unsigned simm4_0, mn_0;
   1795   mn_0 = *valp & 0xf;
   1796   simm4_0 = ((int) mn_0 << 28) >> 28;
   1797   *valp = simm4_0;
   1798   return 0;
   1799 }
   1800 
   1801 static int
   1802 Operand_simm4_encode (uint32 *valp)
   1803 {
   1804   unsigned mn_0, simm4_0;
   1805   simm4_0 = *valp;
   1806   mn_0 = (simm4_0 & 0xf);
   1807   *valp = mn_0;
   1808   return 0;
   1809 }
   1810 
   1811 static int
   1812 Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1813 {
   1814   return 0;
   1815 }
   1816 
   1817 static int
   1818 Operand_arr_encode (uint32 *valp)
   1819 {
   1820   return (*valp & ~0xf) != 0;
   1821 }
   1822 
   1823 static int
   1824 Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1825 {
   1826   return 0;
   1827 }
   1828 
   1829 static int
   1830 Operand_ars_encode (uint32 *valp)
   1831 {
   1832   return (*valp & ~0xf) != 0;
   1833 }
   1834 
   1835 static int
   1836 Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1837 {
   1838   return 0;
   1839 }
   1840 
   1841 static int
   1842 Operand_art_encode (uint32 *valp)
   1843 {
   1844   return (*valp & ~0xf) != 0;
   1845 }
   1846 
   1847 static int
   1848 Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1849 {
   1850   return 0;
   1851 }
   1852 
   1853 static int
   1854 Operand_ar0_encode (uint32 *valp)
   1855 {
   1856   return (*valp & ~0x1f) != 0;
   1857 }
   1858 
   1859 static int
   1860 Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1861 {
   1862   return 0;
   1863 }
   1864 
   1865 static int
   1866 Operand_ar4_encode (uint32 *valp)
   1867 {
   1868   return (*valp & ~0x1f) != 0;
   1869 }
   1870 
   1871 static int
   1872 Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1873 {
   1874   return 0;
   1875 }
   1876 
   1877 static int
   1878 Operand_ar8_encode (uint32 *valp)
   1879 {
   1880   return (*valp & ~0x1f) != 0;
   1881 }
   1882 
   1883 static int
   1884 Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1885 {
   1886   return 0;
   1887 }
   1888 
   1889 static int
   1890 Operand_ar12_encode (uint32 *valp)
   1891 {
   1892   return (*valp & ~0x1f) != 0;
   1893 }
   1894 
   1895 static int
   1896 Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
   1897 {
   1898   return 0;
   1899 }
   1900 
   1901 static int
   1902 Operand_ars_entry_encode (uint32 *valp)
   1903 {
   1904   return (*valp & ~0x1f) != 0;
   1905 }
   1906 
   1907 static int
   1908 Operand_immrx4_decode (uint32 *valp)
   1909 {
   1910   unsigned immrx4_0, r_0;
   1911   r_0 = *valp & 0xf;
   1912   immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
   1913   *valp = immrx4_0;
   1914   return 0;
   1915 }
   1916 
   1917 static int
   1918 Operand_immrx4_encode (uint32 *valp)
   1919 {
   1920   unsigned r_0, immrx4_0;
   1921   immrx4_0 = *valp;
   1922   r_0 = ((immrx4_0 >> 2) & 0xf);
   1923   *valp = r_0;
   1924   return 0;
   1925 }
   1926 
   1927 static int
   1928 Operand_lsi4x4_decode (uint32 *valp)
   1929 {
   1930   unsigned lsi4x4_0, r_0;
   1931   r_0 = *valp & 0xf;
   1932   lsi4x4_0 = r_0 << 2;
   1933   *valp = lsi4x4_0;
   1934   return 0;
   1935 }
   1936 
   1937 static int
   1938 Operand_lsi4x4_encode (uint32 *valp)
   1939 {
   1940   unsigned r_0, lsi4x4_0;
   1941   lsi4x4_0 = *valp;
   1942   r_0 = ((lsi4x4_0 >> 2) & 0xf);
   1943   *valp = r_0;
   1944   return 0;
   1945 }
   1946 
   1947 static int
   1948 Operand_simm7_decode (uint32 *valp)
   1949 {
   1950   unsigned simm7_0, imm7_0;
   1951   imm7_0 = *valp & 0x7f;
   1952   simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
   1953   *valp = simm7_0;
   1954   return 0;
   1955 }
   1956 
   1957 static int
   1958 Operand_simm7_encode (uint32 *valp)
   1959 {
   1960   unsigned imm7_0, simm7_0;
   1961   simm7_0 = *valp;
   1962   imm7_0 = (simm7_0 & 0x7f);
   1963   *valp = imm7_0;
   1964   return 0;
   1965 }
   1966 
   1967 static int
   1968 Operand_uimm6_decode (uint32 *valp)
   1969 {
   1970   unsigned uimm6_0, imm6_0;
   1971   imm6_0 = *valp & 0x3f;
   1972   uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
   1973   *valp = uimm6_0;
   1974   return 0;
   1975 }
   1976 
   1977 static int
   1978 Operand_uimm6_encode (uint32 *valp)
   1979 {
   1980   unsigned imm6_0, uimm6_0;
   1981   uimm6_0 = *valp;
   1982   imm6_0 = (uimm6_0 - 0x4) & 0x3f;
   1983   *valp = imm6_0;
   1984   return 0;
   1985 }
   1986 
   1987 static int
   1988 Operand_uimm6_ator (uint32 *valp, uint32 pc)
   1989 {
   1990   *valp -= pc;
   1991   return 0;
   1992 }
   1993 
   1994 static int
   1995 Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
   1996 {
   1997   *valp += pc;
   1998   return 0;
   1999 }
   2000 
   2001 static int
   2002 Operand_ai4const_decode (uint32 *valp)
   2003 {
   2004   unsigned ai4const_0, t_0;
   2005   t_0 = *valp & 0xf;
   2006   ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
   2007   *valp = ai4const_0;
   2008   return 0;
   2009 }
   2010 
   2011 static int
   2012 Operand_ai4const_encode (uint32 *valp)
   2013 {
   2014   unsigned t_0, ai4const_0;
   2015   ai4const_0 = *valp;
   2016   switch (ai4const_0)
   2017     {
   2018     case 0xffffffff: t_0 = 0; break;
   2019     case 0x1: t_0 = 0x1; break;
   2020     case 0x2: t_0 = 0x2; break;
   2021     case 0x3: t_0 = 0x3; break;
   2022     case 0x4: t_0 = 0x4; break;
   2023     case 0x5: t_0 = 0x5; break;
   2024     case 0x6: t_0 = 0x6; break;
   2025     case 0x7: t_0 = 0x7; break;
   2026     case 0x8: t_0 = 0x8; break;
   2027     case 0x9: t_0 = 0x9; break;
   2028     case 0xa: t_0 = 0xa; break;
   2029     case 0xb: t_0 = 0xb; break;
   2030     case 0xc: t_0 = 0xc; break;
   2031     case 0xd: t_0 = 0xd; break;
   2032     case 0xe: t_0 = 0xe; break;
   2033     default: t_0 = 0xf; break;
   2034     }
   2035   *valp = t_0;
   2036   return 0;
   2037 }
   2038 
   2039 static int
   2040 Operand_b4const_decode (uint32 *valp)
   2041 {
   2042   unsigned b4const_0, r_0;
   2043   r_0 = *valp & 0xf;
   2044   b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
   2045   *valp = b4const_0;
   2046   return 0;
   2047 }
   2048 
   2049 static int
   2050 Operand_b4const_encode (uint32 *valp)
   2051 {
   2052   unsigned r_0, b4const_0;
   2053   b4const_0 = *valp;
   2054   switch (b4const_0)
   2055     {
   2056     case 0xffffffff: r_0 = 0; break;
   2057     case 0x1: r_0 = 0x1; break;
   2058     case 0x2: r_0 = 0x2; break;
   2059     case 0x3: r_0 = 0x3; break;
   2060     case 0x4: r_0 = 0x4; break;
   2061     case 0x5: r_0 = 0x5; break;
   2062     case 0x6: r_0 = 0x6; break;
   2063     case 0x7: r_0 = 0x7; break;
   2064     case 0x8: r_0 = 0x8; break;
   2065     case 0xa: r_0 = 0x9; break;
   2066     case 0xc: r_0 = 0xa; break;
   2067     case 0x10: r_0 = 0xb; break;
   2068     case 0x20: r_0 = 0xc; break;
   2069     case 0x40: r_0 = 0xd; break;
   2070     case 0x80: r_0 = 0xe; break;
   2071     default: r_0 = 0xf; break;
   2072     }
   2073   *valp = r_0;
   2074   return 0;
   2075 }
   2076 
   2077 static int
   2078 Operand_b4constu_decode (uint32 *valp)
   2079 {
   2080   unsigned b4constu_0, r_0;
   2081   r_0 = *valp & 0xf;
   2082   b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
   2083   *valp = b4constu_0;
   2084   return 0;
   2085 }
   2086 
   2087 static int
   2088 Operand_b4constu_encode (uint32 *valp)
   2089 {
   2090   unsigned r_0, b4constu_0;
   2091   b4constu_0 = *valp;
   2092   switch (b4constu_0)
   2093     {
   2094     case 0x8000: r_0 = 0; break;
   2095     case 0x10000: r_0 = 0x1; break;
   2096     case 0x2: r_0 = 0x2; break;
   2097     case 0x3: r_0 = 0x3; break;
   2098     case 0x4: r_0 = 0x4; break;
   2099     case 0x5: r_0 = 0x5; break;
   2100     case 0x6: r_0 = 0x6; break;
   2101     case 0x7: r_0 = 0x7; break;
   2102     case 0x8: r_0 = 0x8; break;
   2103     case 0xa: r_0 = 0x9; break;
   2104     case 0xc: r_0 = 0xa; break;
   2105     case 0x10: r_0 = 0xb; break;
   2106     case 0x20: r_0 = 0xc; break;
   2107     case 0x40: r_0 = 0xd; break;
   2108     case 0x80: r_0 = 0xe; break;
   2109     default: r_0 = 0xf; break;
   2110     }
   2111   *valp = r_0;
   2112   return 0;
   2113 }
   2114 
   2115 static int
   2116 Operand_uimm8_decode (uint32 *valp)
   2117 {
   2118   unsigned uimm8_0, imm8_0;
   2119   imm8_0 = *valp & 0xff;
   2120   uimm8_0 = imm8_0;
   2121   *valp = uimm8_0;
   2122   return 0;
   2123 }
   2124 
   2125 static int
   2126 Operand_uimm8_encode (uint32 *valp)
   2127 {
   2128   unsigned imm8_0, uimm8_0;
   2129   uimm8_0 = *valp;
   2130   imm8_0 = (uimm8_0 & 0xff);
   2131   *valp = imm8_0;
   2132   return 0;
   2133 }
   2134 
   2135 static int
   2136 Operand_uimm8x2_decode (uint32 *valp)
   2137 {
   2138   unsigned uimm8x2_0, imm8_0;
   2139   imm8_0 = *valp & 0xff;
   2140   uimm8x2_0 = imm8_0 << 1;
   2141   *valp = uimm8x2_0;
   2142   return 0;
   2143 }
   2144 
   2145 static int
   2146 Operand_uimm8x2_encode (uint32 *valp)
   2147 {
   2148   unsigned imm8_0, uimm8x2_0;
   2149   uimm8x2_0 = *valp;
   2150   imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
   2151   *valp = imm8_0;
   2152   return 0;
   2153 }
   2154 
   2155 static int
   2156 Operand_uimm8x4_decode (uint32 *valp)
   2157 {
   2158   unsigned uimm8x4_0, imm8_0;
   2159   imm8_0 = *valp & 0xff;
   2160   uimm8x4_0 = imm8_0 << 2;
   2161   *valp = uimm8x4_0;
   2162   return 0;
   2163 }
   2164 
   2165 static int
   2166 Operand_uimm8x4_encode (uint32 *valp)
   2167 {
   2168   unsigned imm8_0, uimm8x4_0;
   2169   uimm8x4_0 = *valp;
   2170   imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
   2171   *valp = imm8_0;
   2172   return 0;
   2173 }
   2174 
   2175 static int
   2176 Operand_uimm4x16_decode (uint32 *valp)
   2177 {
   2178   unsigned uimm4x16_0, op2_0;
   2179   op2_0 = *valp & 0xf;
   2180   uimm4x16_0 = op2_0 << 4;
   2181   *valp = uimm4x16_0;
   2182   return 0;
   2183 }
   2184 
   2185 static int
   2186 Operand_uimm4x16_encode (uint32 *valp)
   2187 {
   2188   unsigned op2_0, uimm4x16_0;
   2189   uimm4x16_0 = *valp;
   2190   op2_0 = ((uimm4x16_0 >> 4) & 0xf);
   2191   *valp = op2_0;
   2192   return 0;
   2193 }
   2194 
   2195 static int
   2196 Operand_simm8_decode (uint32 *valp)
   2197 {
   2198   unsigned simm8_0, imm8_0;
   2199   imm8_0 = *valp & 0xff;
   2200   simm8_0 = ((int) imm8_0 << 24) >> 24;
   2201   *valp = simm8_0;
   2202   return 0;
   2203 }
   2204 
   2205 static int
   2206 Operand_simm8_encode (uint32 *valp)
   2207 {
   2208   unsigned imm8_0, simm8_0;
   2209   simm8_0 = *valp;
   2210   imm8_0 = (simm8_0 & 0xff);
   2211   *valp = imm8_0;
   2212   return 0;
   2213 }
   2214 
   2215 static int
   2216 Operand_simm8x256_decode (uint32 *valp)
   2217 {
   2218   unsigned simm8x256_0, imm8_0;
   2219   imm8_0 = *valp & 0xff;
   2220   simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
   2221   *valp = simm8x256_0;
   2222   return 0;
   2223 }
   2224 
   2225 static int
   2226 Operand_simm8x256_encode (uint32 *valp)
   2227 {
   2228   unsigned imm8_0, simm8x256_0;
   2229   simm8x256_0 = *valp;
   2230   imm8_0 = ((simm8x256_0 >> 8) & 0xff);
   2231   *valp = imm8_0;
   2232   return 0;
   2233 }
   2234 
   2235 static int
   2236 Operand_simm12b_decode (uint32 *valp)
   2237 {
   2238   unsigned simm12b_0, imm12b_0;
   2239   imm12b_0 = *valp & 0xfff;
   2240   simm12b_0 = ((int) imm12b_0 << 20) >> 20;
   2241   *valp = simm12b_0;
   2242   return 0;
   2243 }
   2244 
   2245 static int
   2246 Operand_simm12b_encode (uint32 *valp)
   2247 {
   2248   unsigned imm12b_0, simm12b_0;
   2249   simm12b_0 = *valp;
   2250   imm12b_0 = (simm12b_0 & 0xfff);
   2251   *valp = imm12b_0;
   2252   return 0;
   2253 }
   2254 
   2255 static int
   2256 Operand_msalp32_decode (uint32 *valp)
   2257 {
   2258   unsigned msalp32_0, sal_0;
   2259   sal_0 = *valp & 0x1f;
   2260   msalp32_0 = 0x20 - sal_0;
   2261   *valp = msalp32_0;
   2262   return 0;
   2263 }
   2264 
   2265 static int
   2266 Operand_msalp32_encode (uint32 *valp)
   2267 {
   2268   unsigned sal_0, msalp32_0;
   2269   msalp32_0 = *valp;
   2270   sal_0 = (0x20 - msalp32_0) & 0x1f;
   2271   *valp = sal_0;
   2272   return 0;
   2273 }
   2274 
   2275 static int
   2276 Operand_op2p1_decode (uint32 *valp)
   2277 {
   2278   unsigned op2p1_0, op2_0;
   2279   op2_0 = *valp & 0xf;
   2280   op2p1_0 = op2_0 + 0x1;
   2281   *valp = op2p1_0;
   2282   return 0;
   2283 }
   2284 
   2285 static int
   2286 Operand_op2p1_encode (uint32 *valp)
   2287 {
   2288   unsigned op2_0, op2p1_0;
   2289   op2p1_0 = *valp;
   2290   op2_0 = (op2p1_0 - 0x1) & 0xf;
   2291   *valp = op2_0;
   2292   return 0;
   2293 }
   2294 
   2295 static int
   2296 Operand_label8_decode (uint32 *valp)
   2297 {
   2298   unsigned label8_0, imm8_0;
   2299   imm8_0 = *valp & 0xff;
   2300   label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
   2301   *valp = label8_0;
   2302   return 0;
   2303 }
   2304 
   2305 static int
   2306 Operand_label8_encode (uint32 *valp)
   2307 {
   2308   unsigned imm8_0, label8_0;
   2309   label8_0 = *valp;
   2310   imm8_0 = (label8_0 - 0x4) & 0xff;
   2311   *valp = imm8_0;
   2312   return 0;
   2313 }
   2314 
   2315 static int
   2316 Operand_label8_ator (uint32 *valp, uint32 pc)
   2317 {
   2318   *valp -= pc;
   2319   return 0;
   2320 }
   2321 
   2322 static int
   2323 Operand_label8_rtoa (uint32 *valp, uint32 pc)
   2324 {
   2325   *valp += pc;
   2326   return 0;
   2327 }
   2328 
   2329 static int
   2330 Operand_ulabel8_decode (uint32 *valp)
   2331 {
   2332   unsigned ulabel8_0, imm8_0;
   2333   imm8_0 = *valp & 0xff;
   2334   ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
   2335   *valp = ulabel8_0;
   2336   return 0;
   2337 }
   2338 
   2339 static int
   2340 Operand_ulabel8_encode (uint32 *valp)
   2341 {
   2342   unsigned imm8_0, ulabel8_0;
   2343   ulabel8_0 = *valp;
   2344   imm8_0 = (ulabel8_0 - 0x4) & 0xff;
   2345   *valp = imm8_0;
   2346   return 0;
   2347 }
   2348 
   2349 static int
   2350 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
   2351 {
   2352   *valp -= pc;
   2353   return 0;
   2354 }
   2355 
   2356 static int
   2357 Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
   2358 {
   2359   *valp += pc;
   2360   return 0;
   2361 }
   2362 
   2363 static int
   2364 Operand_label12_decode (uint32 *valp)
   2365 {
   2366   unsigned label12_0, imm12_0;
   2367   imm12_0 = *valp & 0xfff;
   2368   label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
   2369   *valp = label12_0;
   2370   return 0;
   2371 }
   2372 
   2373 static int
   2374 Operand_label12_encode (uint32 *valp)
   2375 {
   2376   unsigned imm12_0, label12_0;
   2377   label12_0 = *valp;
   2378   imm12_0 = (label12_0 - 0x4) & 0xfff;
   2379   *valp = imm12_0;
   2380   return 0;
   2381 }
   2382 
   2383 static int
   2384 Operand_label12_ator (uint32 *valp, uint32 pc)
   2385 {
   2386   *valp -= pc;
   2387   return 0;
   2388 }
   2389 
   2390 static int
   2391 Operand_label12_rtoa (uint32 *valp, uint32 pc)
   2392 {
   2393   *valp += pc;
   2394   return 0;
   2395 }
   2396 
   2397 static int
   2398 Operand_soffset_decode (uint32 *valp)
   2399 {
   2400   unsigned soffset_0, offset_0;
   2401   offset_0 = *valp & 0x3ffff;
   2402   soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
   2403   *valp = soffset_0;
   2404   return 0;
   2405 }
   2406 
   2407 static int
   2408 Operand_soffset_encode (uint32 *valp)
   2409 {
   2410   unsigned offset_0, soffset_0;
   2411   soffset_0 = *valp;
   2412   offset_0 = (soffset_0 - 0x4) & 0x3ffff;
   2413   *valp = offset_0;
   2414   return 0;
   2415 }
   2416 
   2417 static int
   2418 Operand_soffset_ator (uint32 *valp, uint32 pc)
   2419 {
   2420   *valp -= pc;
   2421   return 0;
   2422 }
   2423 
   2424 static int
   2425 Operand_soffset_rtoa (uint32 *valp, uint32 pc)
   2426 {
   2427   *valp += pc;
   2428   return 0;
   2429 }
   2430 
   2431 static int
   2432 Operand_uimm16x4_decode (uint32 *valp)
   2433 {
   2434   unsigned uimm16x4_0, imm16_0;
   2435   imm16_0 = *valp & 0xffff;
   2436   uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
   2437   *valp = uimm16x4_0;
   2438   return 0;
   2439 }
   2440 
   2441 static int
   2442 Operand_uimm16x4_encode (uint32 *valp)
   2443 {
   2444   unsigned imm16_0, uimm16x4_0;
   2445   uimm16x4_0 = *valp;
   2446   imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
   2447   *valp = imm16_0;
   2448   return 0;
   2449 }
   2450 
   2451 static int
   2452 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
   2453 {
   2454   *valp -= ((pc + 3) & ~0x3);
   2455   return 0;
   2456 }
   2457 
   2458 static int
   2459 Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
   2460 {
   2461   *valp += ((pc + 3) & ~0x3);
   2462   return 0;
   2463 }
   2464 
   2465 static int
   2466 Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2467 {
   2468   return 0;
   2469 }
   2470 
   2471 static int
   2472 Operand_mx_encode (uint32 *valp)
   2473 {
   2474   return (*valp & ~0x3) != 0;
   2475 }
   2476 
   2477 static int
   2478 Operand_my_decode (uint32 *valp)
   2479 {
   2480   *valp += 2;
   2481   return 0;
   2482 }
   2483 
   2484 static int
   2485 Operand_my_encode (uint32 *valp)
   2486 {
   2487   int error;
   2488   error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
   2489   *valp = *valp & 1;
   2490   return error;
   2491 }
   2492 
   2493 static int
   2494 Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2495 {
   2496   return 0;
   2497 }
   2498 
   2499 static int
   2500 Operand_mw_encode (uint32 *valp)
   2501 {
   2502   return (*valp & ~0x3) != 0;
   2503 }
   2504 
   2505 static int
   2506 Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2507 {
   2508   return 0;
   2509 }
   2510 
   2511 static int
   2512 Operand_mr0_encode (uint32 *valp)
   2513 {
   2514   return (*valp & ~0x3) != 0;
   2515 }
   2516 
   2517 static int
   2518 Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2519 {
   2520   return 0;
   2521 }
   2522 
   2523 static int
   2524 Operand_mr1_encode (uint32 *valp)
   2525 {
   2526   return (*valp & ~0x3) != 0;
   2527 }
   2528 
   2529 static int
   2530 Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2531 {
   2532   return 0;
   2533 }
   2534 
   2535 static int
   2536 Operand_mr2_encode (uint32 *valp)
   2537 {
   2538   return (*valp & ~0x3) != 0;
   2539 }
   2540 
   2541 static int
   2542 Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
   2543 {
   2544   return 0;
   2545 }
   2546 
   2547 static int
   2548 Operand_mr3_encode (uint32 *valp)
   2549 {
   2550   return (*valp & ~0x3) != 0;
   2551 }
   2552 
   2553 static int
   2554 Operand_immt_decode (uint32 *valp)
   2555 {
   2556   unsigned immt_0, t_0;
   2557   t_0 = *valp & 0xf;
   2558   immt_0 = t_0;
   2559   *valp = immt_0;
   2560   return 0;
   2561 }
   2562 
   2563 static int
   2564 Operand_immt_encode (uint32 *valp)
   2565 {
   2566   unsigned t_0, immt_0;
   2567   immt_0 = *valp;
   2568   t_0 = immt_0 & 0xf;
   2569   *valp = t_0;
   2570   return 0;
   2571 }
   2572 
   2573 static int
   2574 Operand_imms_decode (uint32 *valp)
   2575 {
   2576   unsigned imms_0, s_0;
   2577   s_0 = *valp & 0xf;
   2578   imms_0 = s_0;
   2579   *valp = imms_0;
   2580   return 0;
   2581 }
   2582 
   2583 static int
   2584 Operand_imms_encode (uint32 *valp)
   2585 {
   2586   unsigned s_0, imms_0;
   2587   imms_0 = *valp;
   2588   s_0 = imms_0 & 0xf;
   2589   *valp = s_0;
   2590   return 0;
   2591 }
   2592 
   2593 static int
   2594 Operand_tp7_decode (uint32 *valp)
   2595 {
   2596   unsigned tp7_0, t_0;
   2597   t_0 = *valp & 0xf;
   2598   tp7_0 = t_0 + 0x7;
   2599   *valp = tp7_0;
   2600   return 0;
   2601 }
   2602 
   2603 static int
   2604 Operand_tp7_encode (uint32 *valp)
   2605 {
   2606   unsigned t_0, tp7_0;
   2607   tp7_0 = *valp;
   2608   t_0 = (tp7_0 - 0x7) & 0xf;
   2609   *valp = t_0;
   2610   return 0;
   2611 }
   2612 
   2613 static int
   2614 Operand_xt_wbr15_label_decode (uint32 *valp)
   2615 {
   2616   unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
   2617   xt_wbr15_imm_0 = *valp & 0x7fff;
   2618   xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
   2619   *valp = xt_wbr15_label_0;
   2620   return 0;
   2621 }
   2622 
   2623 static int
   2624 Operand_xt_wbr15_label_encode (uint32 *valp)
   2625 {
   2626   unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
   2627   xt_wbr15_label_0 = *valp;
   2628   xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
   2629   *valp = xt_wbr15_imm_0;
   2630   return 0;
   2631 }
   2632 
   2633 static int
   2634 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
   2635 {
   2636   *valp -= pc;
   2637   return 0;
   2638 }
   2639 
   2640 static int
   2641 Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
   2642 {
   2643   *valp += pc;
   2644   return 0;
   2645 }
   2646 
   2647 static int
   2648 Operand_xt_wbr18_label_decode (uint32 *valp)
   2649 {
   2650   unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
   2651   xt_wbr18_imm_0 = *valp & 0x3ffff;
   2652   xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
   2653   *valp = xt_wbr18_label_0;
   2654   return 0;
   2655 }
   2656 
   2657 static int
   2658 Operand_xt_wbr18_label_encode (uint32 *valp)
   2659 {
   2660   unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
   2661   xt_wbr18_label_0 = *valp;
   2662   xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
   2663   *valp = xt_wbr18_imm_0;
   2664   return 0;
   2665 }
   2666 
   2667 static int
   2668 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
   2669 {
   2670   *valp -= pc;
   2671   return 0;
   2672 }
   2673 
   2674 static int
   2675 Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
   2676 {
   2677   *valp += pc;
   2678   return 0;
   2679 }
   2680 
   2681 static xtensa_operand_internal operands[] = {
   2682   { "soffsetx4", FIELD_offset, -1, 0,
   2683     XTENSA_OPERAND_IS_PCRELATIVE,
   2684     Operand_soffsetx4_encode, Operand_soffsetx4_decode,
   2685     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
   2686   { "uimm12x8", FIELD_imm12, -1, 0,
   2687     0,
   2688     Operand_uimm12x8_encode, Operand_uimm12x8_decode,
   2689     0, 0 },
   2690   { "simm4", FIELD_mn, -1, 0,
   2691     0,
   2692     Operand_simm4_encode, Operand_simm4_decode,
   2693     0, 0 },
   2694   { "arr", FIELD_r, REGFILE_AR, 1,
   2695     XTENSA_OPERAND_IS_REGISTER,
   2696     Operand_arr_encode, Operand_arr_decode,
   2697     0, 0 },
   2698   { "ars", FIELD_s, REGFILE_AR, 1,
   2699     XTENSA_OPERAND_IS_REGISTER,
   2700     Operand_ars_encode, Operand_ars_decode,
   2701     0, 0 },
   2702   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
   2703     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2704     Operand_ars_encode, Operand_ars_decode,
   2705     0, 0 },
   2706   { "art", FIELD_t, REGFILE_AR, 1,
   2707     XTENSA_OPERAND_IS_REGISTER,
   2708     Operand_art_encode, Operand_art_decode,
   2709     0, 0 },
   2710   { "ar0", FIELD__ar0, REGFILE_AR, 1,
   2711     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2712     Operand_ar0_encode, Operand_ar0_decode,
   2713     0, 0 },
   2714   { "ar4", FIELD__ar4, REGFILE_AR, 1,
   2715     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2716     Operand_ar4_encode, Operand_ar4_decode,
   2717     0, 0 },
   2718   { "ar8", FIELD__ar8, REGFILE_AR, 1,
   2719     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2720     Operand_ar8_encode, Operand_ar8_decode,
   2721     0, 0 },
   2722   { "ar12", FIELD__ar12, REGFILE_AR, 1,
   2723     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2724     Operand_ar12_encode, Operand_ar12_decode,
   2725     0, 0 },
   2726   { "ars_entry", FIELD_s, REGFILE_AR, 1,
   2727     XTENSA_OPERAND_IS_REGISTER,
   2728     Operand_ars_entry_encode, Operand_ars_entry_decode,
   2729     0, 0 },
   2730   { "immrx4", FIELD_r, -1, 0,
   2731     0,
   2732     Operand_immrx4_encode, Operand_immrx4_decode,
   2733     0, 0 },
   2734   { "lsi4x4", FIELD_r, -1, 0,
   2735     0,
   2736     Operand_lsi4x4_encode, Operand_lsi4x4_decode,
   2737     0, 0 },
   2738   { "simm7", FIELD_imm7, -1, 0,
   2739     0,
   2740     Operand_simm7_encode, Operand_simm7_decode,
   2741     0, 0 },
   2742   { "uimm6", FIELD_imm6, -1, 0,
   2743     XTENSA_OPERAND_IS_PCRELATIVE,
   2744     Operand_uimm6_encode, Operand_uimm6_decode,
   2745     Operand_uimm6_ator, Operand_uimm6_rtoa },
   2746   { "ai4const", FIELD_t, -1, 0,
   2747     0,
   2748     Operand_ai4const_encode, Operand_ai4const_decode,
   2749     0, 0 },
   2750   { "b4const", FIELD_r, -1, 0,
   2751     0,
   2752     Operand_b4const_encode, Operand_b4const_decode,
   2753     0, 0 },
   2754   { "b4constu", FIELD_r, -1, 0,
   2755     0,
   2756     Operand_b4constu_encode, Operand_b4constu_decode,
   2757     0, 0 },
   2758   { "uimm8", FIELD_imm8, -1, 0,
   2759     0,
   2760     Operand_uimm8_encode, Operand_uimm8_decode,
   2761     0, 0 },
   2762   { "uimm8x2", FIELD_imm8, -1, 0,
   2763     0,
   2764     Operand_uimm8x2_encode, Operand_uimm8x2_decode,
   2765     0, 0 },
   2766   { "uimm8x4", FIELD_imm8, -1, 0,
   2767     0,
   2768     Operand_uimm8x4_encode, Operand_uimm8x4_decode,
   2769     0, 0 },
   2770   { "uimm4x16", FIELD_op2, -1, 0,
   2771     0,
   2772     Operand_uimm4x16_encode, Operand_uimm4x16_decode,
   2773     0, 0 },
   2774   { "simm8", FIELD_imm8, -1, 0,
   2775     0,
   2776     Operand_simm8_encode, Operand_simm8_decode,
   2777     0, 0 },
   2778   { "simm8x256", FIELD_imm8, -1, 0,
   2779     0,
   2780     Operand_simm8x256_encode, Operand_simm8x256_decode,
   2781     0, 0 },
   2782   { "simm12b", FIELD_imm12b, -1, 0,
   2783     0,
   2784     Operand_simm12b_encode, Operand_simm12b_decode,
   2785     0, 0 },
   2786   { "msalp32", FIELD_sal, -1, 0,
   2787     0,
   2788     Operand_msalp32_encode, Operand_msalp32_decode,
   2789     0, 0 },
   2790   { "op2p1", FIELD_op2, -1, 0,
   2791     0,
   2792     Operand_op2p1_encode, Operand_op2p1_decode,
   2793     0, 0 },
   2794   { "label8", FIELD_imm8, -1, 0,
   2795     XTENSA_OPERAND_IS_PCRELATIVE,
   2796     Operand_label8_encode, Operand_label8_decode,
   2797     Operand_label8_ator, Operand_label8_rtoa },
   2798   { "ulabel8", FIELD_imm8, -1, 0,
   2799     XTENSA_OPERAND_IS_PCRELATIVE,
   2800     Operand_ulabel8_encode, Operand_ulabel8_decode,
   2801     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
   2802   { "label12", FIELD_imm12, -1, 0,
   2803     XTENSA_OPERAND_IS_PCRELATIVE,
   2804     Operand_label12_encode, Operand_label12_decode,
   2805     Operand_label12_ator, Operand_label12_rtoa },
   2806   { "soffset", FIELD_offset, -1, 0,
   2807     XTENSA_OPERAND_IS_PCRELATIVE,
   2808     Operand_soffset_encode, Operand_soffset_decode,
   2809     Operand_soffset_ator, Operand_soffset_rtoa },
   2810   { "uimm16x4", FIELD_imm16, -1, 0,
   2811     XTENSA_OPERAND_IS_PCRELATIVE,
   2812     Operand_uimm16x4_encode, Operand_uimm16x4_decode,
   2813     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
   2814   { "mx", FIELD_x, REGFILE_MR, 1,
   2815     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
   2816     Operand_mx_encode, Operand_mx_decode,
   2817     0, 0 },
   2818   { "my", FIELD_y, REGFILE_MR, 1,
   2819     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
   2820     Operand_my_encode, Operand_my_decode,
   2821     0, 0 },
   2822   { "mw", FIELD_w, REGFILE_MR, 1,
   2823     XTENSA_OPERAND_IS_REGISTER,
   2824     Operand_mw_encode, Operand_mw_decode,
   2825     0, 0 },
   2826   { "mr0", FIELD__mr0, REGFILE_MR, 1,
   2827     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2828     Operand_mr0_encode, Operand_mr0_decode,
   2829     0, 0 },
   2830   { "mr1", FIELD__mr1, REGFILE_MR, 1,
   2831     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2832     Operand_mr1_encode, Operand_mr1_decode,
   2833     0, 0 },
   2834   { "mr2", FIELD__mr2, REGFILE_MR, 1,
   2835     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2836     Operand_mr2_encode, Operand_mr2_decode,
   2837     0, 0 },
   2838   { "mr3", FIELD__mr3, REGFILE_MR, 1,
   2839     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
   2840     Operand_mr3_encode, Operand_mr3_decode,
   2841     0, 0 },
   2842   { "immt", FIELD_t, -1, 0,
   2843     0,
   2844     Operand_immt_encode, Operand_immt_decode,
   2845     0, 0 },
   2846   { "imms", FIELD_s, -1, 0,
   2847     0,
   2848     Operand_imms_encode, Operand_imms_decode,
   2849     0, 0 },
   2850   { "tp7", FIELD_t, -1, 0,
   2851     0,
   2852     Operand_tp7_encode, Operand_tp7_decode,
   2853     0, 0 },
   2854   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
   2855     XTENSA_OPERAND_IS_PCRELATIVE,
   2856     Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
   2857     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
   2858   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
   2859     XTENSA_OPERAND_IS_PCRELATIVE,
   2860     Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
   2861     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
   2862   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
   2863   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
   2864   { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
   2865   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
   2866   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
   2867   { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
   2868   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
   2869   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
   2870   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
   2871   { "n", FIELD_n, -1, 0, 0, 0, 0, 0, 0 },
   2872   { "offset", FIELD_offset, -1, 0, 0, 0, 0, 0, 0 },
   2873   { "op0", FIELD_op0, -1, 0, 0, 0, 0, 0, 0 },
   2874   { "op1", FIELD_op1, -1, 0, 0, 0, 0, 0, 0 },
   2875   { "op2", FIELD_op2, -1, 0, 0, 0, 0, 0, 0 },
   2876   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
   2877   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
   2878   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
   2879   { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
   2880   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
   2881   { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
   2882   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
   2883   { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
   2884   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
   2885   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
   2886   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
   2887   { "imm4", FIELD_imm4, -1, 0, 0, 0, 0, 0, 0 },
   2888   { "mn", FIELD_mn, -1, 0, 0, 0, 0, 0, 0 },
   2889   { "i", FIELD_i, -1, 0, 0, 0, 0, 0, 0 },
   2890   { "imm6lo", FIELD_imm6lo, -1, 0, 0, 0, 0, 0, 0 },
   2891   { "imm6hi", FIELD_imm6hi, -1, 0, 0, 0, 0, 0, 0 },
   2892   { "imm7lo", FIELD_imm7lo, -1, 0, 0, 0, 0, 0, 0 },
   2893   { "imm7hi", FIELD_imm7hi, -1, 0, 0, 0, 0, 0, 0 },
   2894   { "z", FIELD_z, -1, 0, 0, 0, 0, 0, 0 },
   2895   { "imm6", FIELD_imm6, -1, 0, 0, 0, 0, 0, 0 },
   2896   { "imm7", FIELD_imm7, -1, 0, 0, 0, 0, 0, 0 },
   2897   { "r3", FIELD_r3, -1, 0, 0, 0, 0, 0, 0 },
   2898   { "rbit2", FIELD_rbit2, -1, 0, 0, 0, 0, 0, 0 },
   2899   { "rhi", FIELD_rhi, -1, 0, 0, 0, 0, 0, 0 },
   2900   { "t3", FIELD_t3, -1, 0, 0, 0, 0, 0, 0 },
   2901   { "tbit2", FIELD_tbit2, -1, 0, 0, 0, 0, 0, 0 },
   2902   { "tlo", FIELD_tlo, -1, 0, 0, 0, 0, 0, 0 },
   2903   { "w", FIELD_w, -1, 0, 0, 0, 0, 0, 0 },
   2904   { "y", FIELD_y, -1, 0, 0, 0, 0, 0, 0 },
   2905   { "x", FIELD_x, -1, 0, 0, 0, 0, 0, 0 },
   2906   { "xt_wbr15_imm", FIELD_xt_wbr15_imm, -1, 0, 0, 0, 0, 0, 0 },
   2907   { "xt_wbr18_imm", FIELD_xt_wbr18_imm, -1, 0, 0, 0, 0, 0, 0 },
   2908   { "bitindex", FIELD_bitindex, -1, 0, 0, 0, 0, 0, 0 },
   2909   { "s3to1", FIELD_s3to1, -1, 0, 0, 0, 0, 0, 0 }
   2910 };
   2911 
   2912 enum xtensa_operand_id {
   2913   OPERAND_soffsetx4,
   2914   OPERAND_uimm12x8,
   2915   OPERAND_simm4,
   2916   OPERAND_arr,
   2917   OPERAND_ars,
   2918   OPERAND__ars_invisible,
   2919   OPERAND_art,
   2920   OPERAND_ar0,
   2921   OPERAND_ar4,
   2922   OPERAND_ar8,
   2923   OPERAND_ar12,
   2924   OPERAND_ars_entry,
   2925   OPERAND_immrx4,
   2926   OPERAND_lsi4x4,
   2927   OPERAND_simm7,
   2928   OPERAND_uimm6,
   2929   OPERAND_ai4const,
   2930   OPERAND_b4const,
   2931   OPERAND_b4constu,
   2932   OPERAND_uimm8,
   2933   OPERAND_uimm8x2,
   2934   OPERAND_uimm8x4,
   2935   OPERAND_uimm4x16,
   2936   OPERAND_simm8,
   2937   OPERAND_simm8x256,
   2938   OPERAND_simm12b,
   2939   OPERAND_msalp32,
   2940   OPERAND_op2p1,
   2941   OPERAND_label8,
   2942   OPERAND_ulabel8,
   2943   OPERAND_label12,
   2944   OPERAND_soffset,
   2945   OPERAND_uimm16x4,
   2946   OPERAND_mx,
   2947   OPERAND_my,
   2948   OPERAND_mw,
   2949   OPERAND_mr0,
   2950   OPERAND_mr1,
   2951   OPERAND_mr2,
   2952   OPERAND_mr3,
   2953   OPERAND_immt,
   2954   OPERAND_imms,
   2955   OPERAND_tp7,
   2956   OPERAND_xt_wbr15_label,
   2957   OPERAND_xt_wbr18_label,
   2958   OPERAND_t,
   2959   OPERAND_bbi4,
   2960   OPERAND_bbi,
   2961   OPERAND_imm12,
   2962   OPERAND_imm8,
   2963   OPERAND_s,
   2964   OPERAND_imm12b,
   2965   OPERAND_imm16,
   2966   OPERAND_m,
   2967   OPERAND_n,
   2968   OPERAND_offset,
   2969   OPERAND_op0,
   2970   OPERAND_op1,
   2971   OPERAND_op2,
   2972   OPERAND_r,
   2973   OPERAND_sa4,
   2974   OPERAND_sae4,
   2975   OPERAND_sae,
   2976   OPERAND_sal,
   2977   OPERAND_sargt,
   2978   OPERAND_sas4,
   2979   OPERAND_sas,
   2980   OPERAND_sr,
   2981   OPERAND_st,
   2982   OPERAND_thi3,
   2983   OPERAND_imm4,
   2984   OPERAND_mn,
   2985   OPERAND_i,
   2986   OPERAND_imm6lo,
   2987   OPERAND_imm6hi,
   2988   OPERAND_imm7lo,
   2989   OPERAND_imm7hi,
   2990   OPERAND_z,
   2991   OPERAND_imm6,
   2992   OPERAND_imm7,
   2993   OPERAND_r3,
   2994   OPERAND_rbit2,
   2995   OPERAND_rhi,
   2996   OPERAND_t3,
   2997   OPERAND_tbit2,
   2998   OPERAND_tlo,
   2999   OPERAND_w,
   3000   OPERAND_y,
   3001   OPERAND_x,
   3002   OPERAND_xt_wbr15_imm,
   3003   OPERAND_xt_wbr18_imm,
   3004   OPERAND_bitindex,
   3005   OPERAND_s3to1
   3006 };
   3007 
   3008 
   3009 /* Iclass table.  */
   3010 
   3011 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
   3012   { { STATE_PSRING }, 'i' },
   3013   { { STATE_PSEXCM }, 'm' },
   3014   { { STATE_EPC1 }, 'i' }
   3015 };
   3016 
   3017 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
   3018   { { STATE_PSEXCM }, 'i' },
   3019   { { STATE_PSRING }, 'i' },
   3020   { { STATE_DEPC }, 'i' }
   3021 };
   3022 
   3023 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
   3024   { { OPERAND_soffsetx4 }, 'i' },
   3025   { { OPERAND_ar12 }, 'o' }
   3026 };
   3027 
   3028 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
   3029   { { STATE_PSCALLINC }, 'o' }
   3030 };
   3031 
   3032 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
   3033   { { OPERAND_soffsetx4 }, 'i' },
   3034   { { OPERAND_ar8 }, 'o' }
   3035 };
   3036 
   3037 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
   3038   { { STATE_PSCALLINC }, 'o' }
   3039 };
   3040 
   3041 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
   3042   { { OPERAND_soffsetx4 }, 'i' },
   3043   { { OPERAND_ar4 }, 'o' }
   3044 };
   3045 
   3046 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
   3047   { { STATE_PSCALLINC }, 'o' }
   3048 };
   3049 
   3050 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
   3051   { { OPERAND_ars }, 'i' },
   3052   { { OPERAND_ar12 }, 'o' }
   3053 };
   3054 
   3055 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
   3056   { { STATE_PSCALLINC }, 'o' }
   3057 };
   3058 
   3059 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
   3060   { { OPERAND_ars }, 'i' },
   3061   { { OPERAND_ar8 }, 'o' }
   3062 };
   3063 
   3064 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
   3065   { { STATE_PSCALLINC }, 'o' }
   3066 };
   3067 
   3068 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
   3069   { { OPERAND_ars }, 'i' },
   3070   { { OPERAND_ar4 }, 'o' }
   3071 };
   3072 
   3073 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
   3074   { { STATE_PSCALLINC }, 'o' }
   3075 };
   3076 
   3077 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
   3078   { { OPERAND_ars_entry }, 's' },
   3079   { { OPERAND_ars }, 'i' },
   3080   { { OPERAND_uimm12x8 }, 'i' }
   3081 };
   3082 
   3083 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
   3084   { { STATE_PSCALLINC }, 'i' },
   3085   { { STATE_PSEXCM }, 'i' },
   3086   { { STATE_PSWOE }, 'i' },
   3087   { { STATE_WindowBase }, 'm' },
   3088   { { STATE_WindowStart }, 'm' }
   3089 };
   3090 
   3091 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
   3092   { { OPERAND_art }, 'o' },
   3093   { { OPERAND_ars }, 'i' }
   3094 };
   3095 
   3096 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
   3097   { { STATE_WindowBase }, 'i' },
   3098   { { STATE_WindowStart }, 'i' }
   3099 };
   3100 
   3101 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
   3102   { { OPERAND_simm4 }, 'i' }
   3103 };
   3104 
   3105 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
   3106   { { STATE_PSEXCM }, 'i' },
   3107   { { STATE_PSRING }, 'i' },
   3108   { { STATE_WindowBase }, 'm' }
   3109 };
   3110 
   3111 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
   3112   { { OPERAND__ars_invisible }, 'i' }
   3113 };
   3114 
   3115 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
   3116   { { STATE_WindowBase }, 'm' },
   3117   { { STATE_WindowStart }, 'm' },
   3118   { { STATE_PSEXCM }, 'i' },
   3119   { { STATE_PSWOE }, 'i' }
   3120 };
   3121 
   3122 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
   3123   { { STATE_EPC1 }, 'i' },
   3124   { { STATE_PSEXCM }, 'm' },
   3125   { { STATE_PSRING }, 'i' },
   3126   { { STATE_WindowBase }, 'm' },
   3127   { { STATE_WindowStart }, 'm' },
   3128   { { STATE_PSOWB }, 'i' }
   3129 };
   3130 
   3131 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
   3132   { { OPERAND_art }, 'o' },
   3133   { { OPERAND_ars }, 'i' },
   3134   { { OPERAND_immrx4 }, 'i' }
   3135 };
   3136 
   3137 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
   3138   { { STATE_PSEXCM }, 'i' },
   3139   { { STATE_PSRING }, 'i' }
   3140 };
   3141 
   3142 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
   3143   { { OPERAND_art }, 'i' },
   3144   { { OPERAND_ars }, 'i' },
   3145   { { OPERAND_immrx4 }, 'i' }
   3146 };
   3147 
   3148 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
   3149   { { STATE_PSEXCM }, 'i' },
   3150   { { STATE_PSRING }, 'i' }
   3151 };
   3152 
   3153 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
   3154   { { OPERAND_art }, 'o' }
   3155 };
   3156 
   3157 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
   3158   { { STATE_PSEXCM }, 'i' },
   3159   { { STATE_PSRING }, 'i' },
   3160   { { STATE_WindowBase }, 'i' }
   3161 };
   3162 
   3163 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
   3164   { { OPERAND_art }, 'i' }
   3165 };
   3166 
   3167 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
   3168   { { STATE_PSEXCM }, 'i' },
   3169   { { STATE_PSRING }, 'i' },
   3170   { { STATE_WindowBase }, 'o' }
   3171 };
   3172 
   3173 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
   3174   { { OPERAND_art }, 'm' }
   3175 };
   3176 
   3177 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
   3178   { { STATE_PSEXCM }, 'i' },
   3179   { { STATE_PSRING }, 'i' },
   3180   { { STATE_WindowBase }, 'm' }
   3181 };
   3182 
   3183 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
   3184   { { OPERAND_art }, 'o' }
   3185 };
   3186 
   3187 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
   3188   { { STATE_PSEXCM }, 'i' },
   3189   { { STATE_PSRING }, 'i' },
   3190   { { STATE_WindowStart }, 'i' }
   3191 };
   3192 
   3193 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
   3194   { { OPERAND_art }, 'i' }
   3195 };
   3196 
   3197 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
   3198   { { STATE_PSEXCM }, 'i' },
   3199   { { STATE_PSRING }, 'i' },
   3200   { { STATE_WindowStart }, 'o' }
   3201 };
   3202 
   3203 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
   3204   { { OPERAND_art }, 'm' }
   3205 };
   3206 
   3207 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
   3208   { { STATE_PSEXCM }, 'i' },
   3209   { { STATE_PSRING }, 'i' },
   3210   { { STATE_WindowStart }, 'm' }
   3211 };
   3212 
   3213 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
   3214   { { OPERAND_arr }, 'o' },
   3215   { { OPERAND_ars }, 'i' },
   3216   { { OPERAND_art }, 'i' }
   3217 };
   3218 
   3219 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
   3220   { { OPERAND_arr }, 'o' },
   3221   { { OPERAND_ars }, 'i' },
   3222   { { OPERAND_ai4const }, 'i' }
   3223 };
   3224 
   3225 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
   3226   { { OPERAND_ars }, 'i' },
   3227   { { OPERAND_uimm6 }, 'i' }
   3228 };
   3229 
   3230 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
   3231   { { OPERAND_art }, 'o' },
   3232   { { OPERAND_ars }, 'i' },
   3233   { { OPERAND_lsi4x4 }, 'i' }
   3234 };
   3235 
   3236 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
   3237   { { OPERAND_art }, 'o' },
   3238   { { OPERAND_ars }, 'i' }
   3239 };
   3240 
   3241 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
   3242   { { OPERAND_ars }, 'o' },
   3243   { { OPERAND_simm7 }, 'i' }
   3244 };
   3245 
   3246 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
   3247   { { OPERAND__ars_invisible }, 'i' }
   3248 };
   3249 
   3250 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
   3251   { { OPERAND_art }, 'i' },
   3252   { { OPERAND_ars }, 'i' },
   3253   { { OPERAND_lsi4x4 }, 'i' }
   3254 };
   3255 
   3256 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
   3257   { { OPERAND_arr }, 'o' }
   3258 };
   3259 
   3260 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
   3261   { { STATE_THREADPTR }, 'i' }
   3262 };
   3263 
   3264 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
   3265   { { OPERAND_art }, 'i' }
   3266 };
   3267 
   3268 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
   3269   { { STATE_THREADPTR }, 'o' }
   3270 };
   3271 
   3272 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
   3273   { { OPERAND_art }, 'o' },
   3274   { { OPERAND_ars }, 'i' },
   3275   { { OPERAND_simm8 }, 'i' }
   3276 };
   3277 
   3278 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
   3279   { { OPERAND_art }, 'o' },
   3280   { { OPERAND_ars }, 'i' },
   3281   { { OPERAND_simm8x256 }, 'i' }
   3282 };
   3283 
   3284 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
   3285   { { OPERAND_arr }, 'o' },
   3286   { { OPERAND_ars }, 'i' },
   3287   { { OPERAND_art }, 'i' }
   3288 };
   3289 
   3290 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
   3291   { { OPERAND_arr }, 'o' },
   3292   { { OPERAND_ars }, 'i' },
   3293   { { OPERAND_art }, 'i' }
   3294 };
   3295 
   3296 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
   3297   { { OPERAND_ars }, 'i' },
   3298   { { OPERAND_b4const }, 'i' },
   3299   { { OPERAND_label8 }, 'i' }
   3300 };
   3301 
   3302 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
   3303   { { OPERAND_ars }, 'i' },
   3304   { { OPERAND_bbi }, 'i' },
   3305   { { OPERAND_label8 }, 'i' }
   3306 };
   3307 
   3308 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
   3309   { { OPERAND_ars }, 'i' },
   3310   { { OPERAND_b4constu }, 'i' },
   3311   { { OPERAND_label8 }, 'i' }
   3312 };
   3313 
   3314 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
   3315   { { OPERAND_ars }, 'i' },
   3316   { { OPERAND_art }, 'i' },
   3317   { { OPERAND_label8 }, 'i' }
   3318 };
   3319 
   3320 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
   3321   { { OPERAND_ars }, 'i' },
   3322   { { OPERAND_label12 }, 'i' }
   3323 };
   3324 
   3325 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
   3326   { { OPERAND_soffsetx4 }, 'i' },
   3327   { { OPERAND_ar0 }, 'o' }
   3328 };
   3329 
   3330 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
   3331   { { OPERAND_ars }, 'i' },
   3332   { { OPERAND_ar0 }, 'o' }
   3333 };
   3334 
   3335 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
   3336   { { OPERAND_arr }, 'o' },
   3337   { { OPERAND_art }, 'i' },
   3338   { { OPERAND_sae }, 'i' },
   3339   { { OPERAND_op2p1 }, 'i' }
   3340 };
   3341 
   3342 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
   3343   { { OPERAND_soffset }, 'i' }
   3344 };
   3345 
   3346 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
   3347   { { OPERAND_ars }, 'i' }
   3348 };
   3349 
   3350 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
   3351   { { OPERAND_art }, 'o' },
   3352   { { OPERAND_ars }, 'i' },
   3353   { { OPERAND_uimm8x2 }, 'i' }
   3354 };
   3355 
   3356 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
   3357   { { OPERAND_art }, 'o' },
   3358   { { OPERAND_ars }, 'i' },
   3359   { { OPERAND_uimm8x2 }, 'i' }
   3360 };
   3361 
   3362 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
   3363   { { OPERAND_art }, 'o' },
   3364   { { OPERAND_ars }, 'i' },
   3365   { { OPERAND_uimm8x4 }, 'i' }
   3366 };
   3367 
   3368 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
   3369   { { OPERAND_art }, 'o' },
   3370   { { OPERAND_uimm16x4 }, 'i' }
   3371 };
   3372 
   3373 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
   3374   { { STATE_LITBADDR }, 'i' },
   3375   { { STATE_LITBEN }, 'i' }
   3376 };
   3377 
   3378 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
   3379   { { OPERAND_art }, 'o' },
   3380   { { OPERAND_ars }, 'i' },
   3381   { { OPERAND_uimm8 }, 'i' }
   3382 };
   3383 
   3384 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
   3385   { { OPERAND_ars }, 'i' },
   3386   { { OPERAND_ulabel8 }, 'i' }
   3387 };
   3388 
   3389 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
   3390   { { STATE_LBEG }, 'o' },
   3391   { { STATE_LEND }, 'o' },
   3392   { { STATE_LCOUNT }, 'o' }
   3393 };
   3394 
   3395 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
   3396   { { OPERAND_ars }, 'i' },
   3397   { { OPERAND_ulabel8 }, 'i' }
   3398 };
   3399 
   3400 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
   3401   { { STATE_LBEG }, 'o' },
   3402   { { STATE_LEND }, 'o' },
   3403   { { STATE_LCOUNT }, 'o' }
   3404 };
   3405 
   3406 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
   3407   { { OPERAND_art }, 'o' },
   3408   { { OPERAND_simm12b }, 'i' }
   3409 };
   3410 
   3411 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
   3412   { { OPERAND_arr }, 'm' },
   3413   { { OPERAND_ars }, 'i' },
   3414   { { OPERAND_art }, 'i' }
   3415 };
   3416 
   3417 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
   3418   { { OPERAND_arr }, 'o' },
   3419   { { OPERAND_art }, 'i' }
   3420 };
   3421 
   3422 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
   3423   { { OPERAND__ars_invisible }, 'i' }
   3424 };
   3425 
   3426 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
   3427   { { OPERAND_art }, 'i' },
   3428   { { OPERAND_ars }, 'i' },
   3429   { { OPERAND_uimm8x2 }, 'i' }
   3430 };
   3431 
   3432 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
   3433   { { OPERAND_art }, 'i' },
   3434   { { OPERAND_ars }, 'i' },
   3435   { { OPERAND_uimm8x4 }, 'i' }
   3436 };
   3437 
   3438 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
   3439   { { OPERAND_art }, 'i' },
   3440   { { OPERAND_ars }, 'i' },
   3441   { { OPERAND_uimm8 }, 'i' }
   3442 };
   3443 
   3444 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
   3445   { { OPERAND_ars }, 'i' }
   3446 };
   3447 
   3448 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
   3449   { { STATE_SAR }, 'o' }
   3450 };
   3451 
   3452 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
   3453   { { OPERAND_sas }, 'i' }
   3454 };
   3455 
   3456 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
   3457   { { STATE_SAR }, 'o' }
   3458 };
   3459 
   3460 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
   3461   { { OPERAND_arr }, 'o' },
   3462   { { OPERAND_ars }, 'i' }
   3463 };
   3464 
   3465 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
   3466   { { STATE_SAR }, 'i' }
   3467 };
   3468 
   3469 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
   3470   { { OPERAND_arr }, 'o' },
   3471   { { OPERAND_ars }, 'i' },
   3472   { { OPERAND_art }, 'i' }
   3473 };
   3474 
   3475 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
   3476   { { STATE_SAR }, 'i' }
   3477 };
   3478 
   3479 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
   3480   { { OPERAND_arr }, 'o' },
   3481   { { OPERAND_art }, 'i' }
   3482 };
   3483 
   3484 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
   3485   { { STATE_SAR }, 'i' }
   3486 };
   3487 
   3488 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
   3489   { { OPERAND_arr }, 'o' },
   3490   { { OPERAND_ars }, 'i' },
   3491   { { OPERAND_msalp32 }, 'i' }
   3492 };
   3493 
   3494 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
   3495   { { OPERAND_arr }, 'o' },
   3496   { { OPERAND_art }, 'i' },
   3497   { { OPERAND_sargt }, 'i' }
   3498 };
   3499 
   3500 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
   3501   { { OPERAND_arr }, 'o' },
   3502   { { OPERAND_art }, 'i' },
   3503   { { OPERAND_s }, 'i' }
   3504 };
   3505 
   3506 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
   3507   { { STATE_XTSYNC }, 'i' }
   3508 };
   3509 
   3510 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
   3511   { { OPERAND_art }, 'o' },
   3512   { { OPERAND_s }, 'i' }
   3513 };
   3514 
   3515 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
   3516   { { STATE_PSWOE }, 'i' },
   3517   { { STATE_PSCALLINC }, 'i' },
   3518   { { STATE_PSOWB }, 'i' },
   3519   { { STATE_PSRING }, 'i' },
   3520   { { STATE_PSUM }, 'i' },
   3521   { { STATE_PSEXCM }, 'i' },
   3522   { { STATE_PSINTLEVEL }, 'm' }
   3523 };
   3524 
   3525 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
   3526   { { OPERAND_art }, 'o' }
   3527 };
   3528 
   3529 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
   3530   { { STATE_LEND }, 'i' }
   3531 };
   3532 
   3533 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
   3534   { { OPERAND_art }, 'i' }
   3535 };
   3536 
   3537 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
   3538   { { STATE_LEND }, 'o' }
   3539 };
   3540 
   3541 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
   3542   { { OPERAND_art }, 'm' }
   3543 };
   3544 
   3545 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
   3546   { { STATE_LEND }, 'm' }
   3547 };
   3548 
   3549 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
   3550   { { OPERAND_art }, 'o' }
   3551 };
   3552 
   3553 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
   3554   { { STATE_LCOUNT }, 'i' }
   3555 };
   3556 
   3557 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
   3558   { { OPERAND_art }, 'i' }
   3559 };
   3560 
   3561 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
   3562   { { STATE_XTSYNC }, 'o' },
   3563   { { STATE_LCOUNT }, 'o' }
   3564 };
   3565 
   3566 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
   3567   { { OPERAND_art }, 'm' }
   3568 };
   3569 
   3570 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
   3571   { { STATE_XTSYNC }, 'o' },
   3572   { { STATE_LCOUNT }, 'm' }
   3573 };
   3574 
   3575 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
   3576   { { OPERAND_art }, 'o' }
   3577 };
   3578 
   3579 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
   3580   { { STATE_LBEG }, 'i' }
   3581 };
   3582 
   3583 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
   3584   { { OPERAND_art }, 'i' }
   3585 };
   3586 
   3587 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
   3588   { { STATE_LBEG }, 'o' }
   3589 };
   3590 
   3591 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
   3592   { { OPERAND_art }, 'm' }
   3593 };
   3594 
   3595 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
   3596   { { STATE_LBEG }, 'm' }
   3597 };
   3598 
   3599 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
   3600   { { OPERAND_art }, 'o' }
   3601 };
   3602 
   3603 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
   3604   { { STATE_SAR }, 'i' }
   3605 };
   3606 
   3607 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
   3608   { { OPERAND_art }, 'i' }
   3609 };
   3610 
   3611 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
   3612   { { STATE_SAR }, 'o' },
   3613   { { STATE_XTSYNC }, 'o' }
   3614 };
   3615 
   3616 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
   3617   { { OPERAND_art }, 'm' }
   3618 };
   3619 
   3620 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
   3621   { { STATE_SAR }, 'm' }
   3622 };
   3623 
   3624 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
   3625   { { OPERAND_art }, 'o' }
   3626 };
   3627 
   3628 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
   3629   { { STATE_LITBADDR }, 'i' },
   3630   { { STATE_LITBEN }, 'i' }
   3631 };
   3632 
   3633 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
   3634   { { OPERAND_art }, 'i' }
   3635 };
   3636 
   3637 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
   3638   { { STATE_LITBADDR }, 'o' },
   3639   { { STATE_LITBEN }, 'o' }
   3640 };
   3641 
   3642 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
   3643   { { OPERAND_art }, 'm' }
   3644 };
   3645 
   3646 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
   3647   { { STATE_LITBADDR }, 'm' },
   3648   { { STATE_LITBEN }, 'm' }
   3649 };
   3650 
   3651 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
   3652   { { OPERAND_art }, 'o' }
   3653 };
   3654 
   3655 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
   3656   { { STATE_PSEXCM }, 'i' },
   3657   { { STATE_PSRING }, 'i' }
   3658 };
   3659 
   3660 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
   3661   { { OPERAND_art }, 'i' }
   3662 };
   3663 
   3664 static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
   3665   { { STATE_PSEXCM }, 'i' },
   3666   { { STATE_PSRING }, 'i' }
   3667 };
   3668 
   3669 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
   3670   { { OPERAND_art }, 'o' }
   3671 };
   3672 
   3673 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
   3674   { { STATE_PSEXCM }, 'i' },
   3675   { { STATE_PSRING }, 'i' }
   3676 };
   3677 
   3678 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
   3679   { { OPERAND_art }, 'o' }
   3680 };
   3681 
   3682 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
   3683   { { STATE_PSWOE }, 'i' },
   3684   { { STATE_PSCALLINC }, 'i' },
   3685   { { STATE_PSOWB }, 'i' },
   3686   { { STATE_PSRING }, 'i' },
   3687   { { STATE_PSUM }, 'i' },
   3688   { { STATE_PSEXCM }, 'i' },
   3689   { { STATE_PSINTLEVEL }, 'i' }
   3690 };
   3691 
   3692 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
   3693   { { OPERAND_art }, 'i' }
   3694 };
   3695 
   3696 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
   3697   { { STATE_PSWOE }, 'o' },
   3698   { { STATE_PSCALLINC }, 'o' },
   3699   { { STATE_PSOWB }, 'o' },
   3700   { { STATE_PSRING }, 'm' },
   3701   { { STATE_PSUM }, 'o' },
   3702   { { STATE_PSEXCM }, 'm' },
   3703   { { STATE_PSINTLEVEL }, 'o' }
   3704 };
   3705 
   3706 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
   3707   { { OPERAND_art }, 'm' }
   3708 };
   3709 
   3710 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
   3711   { { STATE_PSWOE }, 'm' },
   3712   { { STATE_PSCALLINC }, 'm' },
   3713   { { STATE_PSOWB }, 'm' },
   3714   { { STATE_PSRING }, 'm' },
   3715   { { STATE_PSUM }, 'm' },
   3716   { { STATE_PSEXCM }, 'm' },
   3717   { { STATE_PSINTLEVEL }, 'm' }
   3718 };
   3719 
   3720 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
   3721   { { OPERAND_art }, 'o' }
   3722 };
   3723 
   3724 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
   3725   { { STATE_PSEXCM }, 'i' },
   3726   { { STATE_PSRING }, 'i' },
   3727   { { STATE_EPC1 }, 'i' }
   3728 };
   3729 
   3730 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
   3731   { { OPERAND_art }, 'i' }
   3732 };
   3733 
   3734 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
   3735   { { STATE_PSEXCM }, 'i' },
   3736   { { STATE_PSRING }, 'i' },
   3737   { { STATE_EPC1 }, 'o' }
   3738 };
   3739 
   3740 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
   3741   { { OPERAND_art }, 'm' }
   3742 };
   3743 
   3744 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
   3745   { { STATE_PSEXCM }, 'i' },
   3746   { { STATE_PSRING }, 'i' },
   3747   { { STATE_EPC1 }, 'm' }
   3748 };
   3749 
   3750 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
   3751   { { OPERAND_art }, 'o' }
   3752 };
   3753 
   3754 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
   3755   { { STATE_PSEXCM }, 'i' },
   3756   { { STATE_PSRING }, 'i' },
   3757   { { STATE_EXCSAVE1 }, 'i' }
   3758 };
   3759 
   3760 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
   3761   { { OPERAND_art }, 'i' }
   3762 };
   3763 
   3764 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
   3765   { { STATE_PSEXCM }, 'i' },
   3766   { { STATE_PSRING }, 'i' },
   3767   { { STATE_EXCSAVE1 }, 'o' }
   3768 };
   3769 
   3770 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
   3771   { { OPERAND_art }, 'm' }
   3772 };
   3773 
   3774 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
   3775   { { STATE_PSEXCM }, 'i' },
   3776   { { STATE_PSRING }, 'i' },
   3777   { { STATE_EXCSAVE1 }, 'm' }
   3778 };
   3779 
   3780 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
   3781   { { OPERAND_art }, 'o' }
   3782 };
   3783 
   3784 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
   3785   { { STATE_PSEXCM }, 'i' },
   3786   { { STATE_PSRING }, 'i' },
   3787   { { STATE_EPC2 }, 'i' }
   3788 };
   3789 
   3790 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
   3791   { { OPERAND_art }, 'i' }
   3792 };
   3793 
   3794 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
   3795   { { STATE_PSEXCM }, 'i' },
   3796   { { STATE_PSRING }, 'i' },
   3797   { { STATE_EPC2 }, 'o' }
   3798 };
   3799 
   3800 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
   3801   { { OPERAND_art }, 'm' }
   3802 };
   3803 
   3804 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
   3805   { { STATE_PSEXCM }, 'i' },
   3806   { { STATE_PSRING }, 'i' },
   3807   { { STATE_EPC2 }, 'm' }
   3808 };
   3809 
   3810 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
   3811   { { OPERAND_art }, 'o' }
   3812 };
   3813 
   3814 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
   3815   { { STATE_PSEXCM }, 'i' },
   3816   { { STATE_PSRING }, 'i' },
   3817   { { STATE_EXCSAVE2 }, 'i' }
   3818 };
   3819 
   3820 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
   3821   { { OPERAND_art }, 'i' }
   3822 };
   3823 
   3824 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
   3825   { { STATE_PSEXCM }, 'i' },
   3826   { { STATE_PSRING }, 'i' },
   3827   { { STATE_EXCSAVE2 }, 'o' }
   3828 };
   3829 
   3830 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
   3831   { { OPERAND_art }, 'm' }
   3832 };
   3833 
   3834 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
   3835   { { STATE_PSEXCM }, 'i' },
   3836   { { STATE_PSRING }, 'i' },
   3837   { { STATE_EXCSAVE2 }, 'm' }
   3838 };
   3839 
   3840 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
   3841   { { OPERAND_art }, 'o' }
   3842 };
   3843 
   3844 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
   3845   { { STATE_PSEXCM }, 'i' },
   3846   { { STATE_PSRING }, 'i' },
   3847   { { STATE_EPC3 }, 'i' }
   3848 };
   3849 
   3850 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
   3851   { { OPERAND_art }, 'i' }
   3852 };
   3853 
   3854 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
   3855   { { STATE_PSEXCM }, 'i' },
   3856   { { STATE_PSRING }, 'i' },
   3857   { { STATE_EPC3 }, 'o' }
   3858 };
   3859 
   3860 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
   3861   { { OPERAND_art }, 'm' }
   3862 };
   3863 
   3864 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
   3865   { { STATE_PSEXCM }, 'i' },
   3866   { { STATE_PSRING }, 'i' },
   3867   { { STATE_EPC3 }, 'm' }
   3868 };
   3869 
   3870 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
   3871   { { OPERAND_art }, 'o' }
   3872 };
   3873 
   3874 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
   3875   { { STATE_PSEXCM }, 'i' },
   3876   { { STATE_PSRING }, 'i' },
   3877   { { STATE_EXCSAVE3 }, 'i' }
   3878 };
   3879 
   3880 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
   3881   { { OPERAND_art }, 'i' }
   3882 };
   3883 
   3884 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
   3885   { { STATE_PSEXCM }, 'i' },
   3886   { { STATE_PSRING }, 'i' },
   3887   { { STATE_EXCSAVE3 }, 'o' }
   3888 };
   3889 
   3890 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
   3891   { { OPERAND_art }, 'm' }
   3892 };
   3893 
   3894 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
   3895   { { STATE_PSEXCM }, 'i' },
   3896   { { STATE_PSRING }, 'i' },
   3897   { { STATE_EXCSAVE3 }, 'm' }
   3898 };
   3899 
   3900 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
   3901   { { OPERAND_art }, 'o' }
   3902 };
   3903 
   3904 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
   3905   { { STATE_PSEXCM }, 'i' },
   3906   { { STATE_PSRING }, 'i' },
   3907   { { STATE_EPC4 }, 'i' }
   3908 };
   3909 
   3910 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
   3911   { { OPERAND_art }, 'i' }
   3912 };
   3913 
   3914 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
   3915   { { STATE_PSEXCM }, 'i' },
   3916   { { STATE_PSRING }, 'i' },
   3917   { { STATE_EPC4 }, 'o' }
   3918 };
   3919 
   3920 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
   3921   { { OPERAND_art }, 'm' }
   3922 };
   3923 
   3924 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
   3925   { { STATE_PSEXCM }, 'i' },
   3926   { { STATE_PSRING }, 'i' },
   3927   { { STATE_EPC4 }, 'm' }
   3928 };
   3929 
   3930 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
   3931   { { OPERAND_art }, 'o' }
   3932 };
   3933 
   3934 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
   3935   { { STATE_PSEXCM }, 'i' },
   3936   { { STATE_PSRING }, 'i' },
   3937   { { STATE_EXCSAVE4 }, 'i' }
   3938 };
   3939 
   3940 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
   3941   { { OPERAND_art }, 'i' }
   3942 };
   3943 
   3944 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
   3945   { { STATE_PSEXCM }, 'i' },
   3946   { { STATE_PSRING }, 'i' },
   3947   { { STATE_EXCSAVE4 }, 'o' }
   3948 };
   3949 
   3950 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
   3951   { { OPERAND_art }, 'm' }
   3952 };
   3953 
   3954 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
   3955   { { STATE_PSEXCM }, 'i' },
   3956   { { STATE_PSRING }, 'i' },
   3957   { { STATE_EXCSAVE4 }, 'm' }
   3958 };
   3959 
   3960 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
   3961   { { OPERAND_art }, 'o' }
   3962 };
   3963 
   3964 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
   3965   { { STATE_PSEXCM }, 'i' },
   3966   { { STATE_PSRING }, 'i' },
   3967   { { STATE_EPC5 }, 'i' }
   3968 };
   3969 
   3970 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
   3971   { { OPERAND_art }, 'i' }
   3972 };
   3973 
   3974 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
   3975   { { STATE_PSEXCM }, 'i' },
   3976   { { STATE_PSRING }, 'i' },
   3977   { { STATE_EPC5 }, 'o' }
   3978 };
   3979 
   3980 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
   3981   { { OPERAND_art }, 'm' }
   3982 };
   3983 
   3984 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
   3985   { { STATE_PSEXCM }, 'i' },
   3986   { { STATE_PSRING }, 'i' },
   3987   { { STATE_EPC5 }, 'm' }
   3988 };
   3989 
   3990 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
   3991   { { OPERAND_art }, 'o' }
   3992 };
   3993 
   3994 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
   3995   { { STATE_PSEXCM }, 'i' },
   3996   { { STATE_PSRING }, 'i' },
   3997   { { STATE_EXCSAVE5 }, 'i' }
   3998 };
   3999 
   4000 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
   4001   { { OPERAND_art }, 'i' }
   4002 };
   4003 
   4004 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
   4005   { { STATE_PSEXCM }, 'i' },
   4006   { { STATE_PSRING }, 'i' },
   4007   { { STATE_EXCSAVE5 }, 'o' }
   4008 };
   4009 
   4010 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
   4011   { { OPERAND_art }, 'm' }
   4012 };
   4013 
   4014 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
   4015   { { STATE_PSEXCM }, 'i' },
   4016   { { STATE_PSRING }, 'i' },
   4017   { { STATE_EXCSAVE5 }, 'm' }
   4018 };
   4019 
   4020 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
   4021   { { OPERAND_art }, 'o' }
   4022 };
   4023 
   4024 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
   4025   { { STATE_PSEXCM }, 'i' },
   4026   { { STATE_PSRING }, 'i' },
   4027   { { STATE_EPC6 }, 'i' }
   4028 };
   4029 
   4030 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
   4031   { { OPERAND_art }, 'i' }
   4032 };
   4033 
   4034 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
   4035   { { STATE_PSEXCM }, 'i' },
   4036   { { STATE_PSRING }, 'i' },
   4037   { { STATE_EPC6 }, 'o' }
   4038 };
   4039 
   4040 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
   4041   { { OPERAND_art }, 'm' }
   4042 };
   4043 
   4044 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
   4045   { { STATE_PSEXCM }, 'i' },
   4046   { { STATE_PSRING }, 'i' },
   4047   { { STATE_EPC6 }, 'm' }
   4048 };
   4049 
   4050 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
   4051   { { OPERAND_art }, 'o' }
   4052 };
   4053 
   4054 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
   4055   { { STATE_PSEXCM }, 'i' },
   4056   { { STATE_PSRING }, 'i' },
   4057   { { STATE_EXCSAVE6 }, 'i' }
   4058 };
   4059 
   4060 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
   4061   { { OPERAND_art }, 'i' }
   4062 };
   4063 
   4064 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
   4065   { { STATE_PSEXCM }, 'i' },
   4066   { { STATE_PSRING }, 'i' },
   4067   { { STATE_EXCSAVE6 }, 'o' }
   4068 };
   4069 
   4070 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
   4071   { { OPERAND_art }, 'm' }
   4072 };
   4073 
   4074 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
   4075   { { STATE_PSEXCM }, 'i' },
   4076   { { STATE_PSRING }, 'i' },
   4077   { { STATE_EXCSAVE6 }, 'm' }
   4078 };
   4079 
   4080 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
   4081   { { OPERAND_art }, 'o' }
   4082 };
   4083 
   4084 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
   4085   { { STATE_PSEXCM }, 'i' },
   4086   { { STATE_PSRING }, 'i' },
   4087   { { STATE_EPC7 }, 'i' }
   4088 };
   4089 
   4090 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
   4091   { { OPERAND_art }, 'i' }
   4092 };
   4093 
   4094 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
   4095   { { STATE_PSEXCM }, 'i' },
   4096   { { STATE_PSRING }, 'i' },
   4097   { { STATE_EPC7 }, 'o' }
   4098 };
   4099 
   4100 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
   4101   { { OPERAND_art }, 'm' }
   4102 };
   4103 
   4104 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
   4105   { { STATE_PSEXCM }, 'i' },
   4106   { { STATE_PSRING }, 'i' },
   4107   { { STATE_EPC7 }, 'm' }
   4108 };
   4109 
   4110 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
   4111   { { OPERAND_art }, 'o' }
   4112 };
   4113 
   4114 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
   4115   { { STATE_PSEXCM }, 'i' },
   4116   { { STATE_PSRING }, 'i' },
   4117   { { STATE_EXCSAVE7 }, 'i' }
   4118 };
   4119 
   4120 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
   4121   { { OPERAND_art }, 'i' }
   4122 };
   4123 
   4124 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
   4125   { { STATE_PSEXCM }, 'i' },
   4126   { { STATE_PSRING }, 'i' },
   4127   { { STATE_EXCSAVE7 }, 'o' }
   4128 };
   4129 
   4130 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
   4131   { { OPERAND_art }, 'm' }
   4132 };
   4133 
   4134 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
   4135   { { STATE_PSEXCM }, 'i' },
   4136   { { STATE_PSRING }, 'i' },
   4137   { { STATE_EXCSAVE7 }, 'm' }
   4138 };
   4139 
   4140 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
   4141   { { OPERAND_art }, 'o' }
   4142 };
   4143 
   4144 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
   4145   { { STATE_PSEXCM }, 'i' },
   4146   { { STATE_PSRING }, 'i' },
   4147   { { STATE_EPS2 }, 'i' }
   4148 };
   4149 
   4150 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
   4151   { { OPERAND_art }, 'i' }
   4152 };
   4153 
   4154 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
   4155   { { STATE_PSEXCM }, 'i' },
   4156   { { STATE_PSRING }, 'i' },
   4157   { { STATE_EPS2 }, 'o' }
   4158 };
   4159 
   4160 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
   4161   { { OPERAND_art }, 'm' }
   4162 };
   4163 
   4164 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
   4165   { { STATE_PSEXCM }, 'i' },
   4166   { { STATE_PSRING }, 'i' },
   4167   { { STATE_EPS2 }, 'm' }
   4168 };
   4169 
   4170 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
   4171   { { OPERAND_art }, 'o' }
   4172 };
   4173 
   4174 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
   4175   { { STATE_PSEXCM }, 'i' },
   4176   { { STATE_PSRING }, 'i' },
   4177   { { STATE_EPS3 }, 'i' }
   4178 };
   4179 
   4180 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
   4181   { { OPERAND_art }, 'i' }
   4182 };
   4183 
   4184 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
   4185   { { STATE_PSEXCM }, 'i' },
   4186   { { STATE_PSRING }, 'i' },
   4187   { { STATE_EPS3 }, 'o' }
   4188 };
   4189 
   4190 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
   4191   { { OPERAND_art }, 'm' }
   4192 };
   4193 
   4194 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
   4195   { { STATE_PSEXCM }, 'i' },
   4196   { { STATE_PSRING }, 'i' },
   4197   { { STATE_EPS3 }, 'm' }
   4198 };
   4199 
   4200 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
   4201   { { OPERAND_art }, 'o' }
   4202 };
   4203 
   4204 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
   4205   { { STATE_PSEXCM }, 'i' },
   4206   { { STATE_PSRING }, 'i' },
   4207   { { STATE_EPS4 }, 'i' }
   4208 };
   4209 
   4210 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
   4211   { { OPERAND_art }, 'i' }
   4212 };
   4213 
   4214 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
   4215   { { STATE_PSEXCM }, 'i' },
   4216   { { STATE_PSRING }, 'i' },
   4217   { { STATE_EPS4 }, 'o' }
   4218 };
   4219 
   4220 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
   4221   { { OPERAND_art }, 'm' }
   4222 };
   4223 
   4224 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
   4225   { { STATE_PSEXCM }, 'i' },
   4226   { { STATE_PSRING }, 'i' },
   4227   { { STATE_EPS4 }, 'm' }
   4228 };
   4229 
   4230 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
   4231   { { OPERAND_art }, 'o' }
   4232 };
   4233 
   4234 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
   4235   { { STATE_PSEXCM }, 'i' },
   4236   { { STATE_PSRING }, 'i' },
   4237   { { STATE_EPS5 }, 'i' }
   4238 };
   4239 
   4240 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
   4241   { { OPERAND_art }, 'i' }
   4242 };
   4243 
   4244 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
   4245   { { STATE_PSEXCM }, 'i' },
   4246   { { STATE_PSRING }, 'i' },
   4247   { { STATE_EPS5 }, 'o' }
   4248 };
   4249 
   4250 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
   4251   { { OPERAND_art }, 'm' }
   4252 };
   4253 
   4254 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
   4255   { { STATE_PSEXCM }, 'i' },
   4256   { { STATE_PSRING }, 'i' },
   4257   { { STATE_EPS5 }, 'm' }
   4258 };
   4259 
   4260 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
   4261   { { OPERAND_art }, 'o' }
   4262 };
   4263 
   4264 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
   4265   { { STATE_PSEXCM }, 'i' },
   4266   { { STATE_PSRING }, 'i' },
   4267   { { STATE_EPS6 }, 'i' }
   4268 };
   4269 
   4270 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
   4271   { { OPERAND_art }, 'i' }
   4272 };
   4273 
   4274 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
   4275   { { STATE_PSEXCM }, 'i' },
   4276   { { STATE_PSRING }, 'i' },
   4277   { { STATE_EPS6 }, 'o' }
   4278 };
   4279 
   4280 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
   4281   { { OPERAND_art }, 'm' }
   4282 };
   4283 
   4284 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
   4285   { { STATE_PSEXCM }, 'i' },
   4286   { { STATE_PSRING }, 'i' },
   4287   { { STATE_EPS6 }, 'm' }
   4288 };
   4289 
   4290 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
   4291   { { OPERAND_art }, 'o' }
   4292 };
   4293 
   4294 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
   4295   { { STATE_PSEXCM }, 'i' },
   4296   { { STATE_PSRING }, 'i' },
   4297   { { STATE_EPS7 }, 'i' }
   4298 };
   4299 
   4300 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
   4301   { { OPERAND_art }, 'i' }
   4302 };
   4303 
   4304 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
   4305   { { STATE_PSEXCM }, 'i' },
   4306   { { STATE_PSRING }, 'i' },
   4307   { { STATE_EPS7 }, 'o' }
   4308 };
   4309 
   4310 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
   4311   { { OPERAND_art }, 'm' }
   4312 };
   4313 
   4314 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
   4315   { { STATE_PSEXCM }, 'i' },
   4316   { { STATE_PSRING }, 'i' },
   4317   { { STATE_EPS7 }, 'm' }
   4318 };
   4319 
   4320 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
   4321   { { OPERAND_art }, 'o' }
   4322 };
   4323 
   4324 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
   4325   { { STATE_PSEXCM }, 'i' },
   4326   { { STATE_PSRING }, 'i' },
   4327   { { STATE_EXCVADDR }, 'i' }
   4328 };
   4329 
   4330 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
   4331   { { OPERAND_art }, 'i' }
   4332 };
   4333 
   4334 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
   4335   { { STATE_PSEXCM }, 'i' },
   4336   { { STATE_PSRING }, 'i' },
   4337   { { STATE_EXCVADDR }, 'o' }
   4338 };
   4339 
   4340 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
   4341   { { OPERAND_art }, 'm' }
   4342 };
   4343 
   4344 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
   4345   { { STATE_PSEXCM }, 'i' },
   4346   { { STATE_PSRING }, 'i' },
   4347   { { STATE_EXCVADDR }, 'm' }
   4348 };
   4349 
   4350 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
   4351   { { OPERAND_art }, 'o' }
   4352 };
   4353 
   4354 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
   4355   { { STATE_PSEXCM }, 'i' },
   4356   { { STATE_PSRING }, 'i' },
   4357   { { STATE_DEPC }, 'i' }
   4358 };
   4359 
   4360 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
   4361   { { OPERAND_art }, 'i' }
   4362 };
   4363 
   4364 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
   4365   { { STATE_PSEXCM }, 'i' },
   4366   { { STATE_PSRING }, 'i' },
   4367   { { STATE_DEPC }, 'o' }
   4368 };
   4369 
   4370 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
   4371   { { OPERAND_art }, 'm' }
   4372 };
   4373 
   4374 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
   4375   { { STATE_PSEXCM }, 'i' },
   4376   { { STATE_PSRING }, 'i' },
   4377   { { STATE_DEPC }, 'm' }
   4378 };
   4379 
   4380 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
   4381   { { OPERAND_art }, 'o' }
   4382 };
   4383 
   4384 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
   4385   { { STATE_PSEXCM }, 'i' },
   4386   { { STATE_PSRING }, 'i' },
   4387   { { STATE_EXCCAUSE }, 'i' },
   4388   { { STATE_XTSYNC }, 'i' }
   4389 };
   4390 
   4391 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
   4392   { { OPERAND_art }, 'i' }
   4393 };
   4394 
   4395 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
   4396   { { STATE_PSEXCM }, 'i' },
   4397   { { STATE_PSRING }, 'i' },
   4398   { { STATE_EXCCAUSE }, 'o' }
   4399 };
   4400 
   4401 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
   4402   { { OPERAND_art }, 'm' }
   4403 };
   4404 
   4405 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
   4406   { { STATE_PSEXCM }, 'i' },
   4407   { { STATE_PSRING }, 'i' },
   4408   { { STATE_EXCCAUSE }, 'm' }
   4409 };
   4410 
   4411 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
   4412   { { OPERAND_art }, 'o' }
   4413 };
   4414 
   4415 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
   4416   { { STATE_PSEXCM }, 'i' },
   4417   { { STATE_PSRING }, 'i' },
   4418   { { STATE_MISC0 }, 'i' }
   4419 };
   4420 
   4421 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
   4422   { { OPERAND_art }, 'i' }
   4423 };
   4424 
   4425 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
   4426   { { STATE_PSEXCM }, 'i' },
   4427   { { STATE_PSRING }, 'i' },
   4428   { { STATE_MISC0 }, 'o' }
   4429 };
   4430 
   4431 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
   4432   { { OPERAND_art }, 'm' }
   4433 };
   4434 
   4435 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
   4436   { { STATE_PSEXCM }, 'i' },
   4437   { { STATE_PSRING }, 'i' },
   4438   { { STATE_MISC0 }, 'm' }
   4439 };
   4440 
   4441 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
   4442   { { OPERAND_art }, 'o' }
   4443 };
   4444 
   4445 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
   4446   { { STATE_PSEXCM }, 'i' },
   4447   { { STATE_PSRING }, 'i' },
   4448   { { STATE_MISC1 }, 'i' }
   4449 };
   4450 
   4451 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
   4452   { { OPERAND_art }, 'i' }
   4453 };
   4454 
   4455 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
   4456   { { STATE_PSEXCM }, 'i' },
   4457   { { STATE_PSRING }, 'i' },
   4458   { { STATE_MISC1 }, 'o' }
   4459 };
   4460 
   4461 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
   4462   { { OPERAND_art }, 'm' }
   4463 };
   4464 
   4465 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
   4466   { { STATE_PSEXCM }, 'i' },
   4467   { { STATE_PSRING }, 'i' },
   4468   { { STATE_MISC1 }, 'm' }
   4469 };
   4470 
   4471 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
   4472   { { OPERAND_art }, 'o' }
   4473 };
   4474 
   4475 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
   4476   { { STATE_PSEXCM }, 'i' },
   4477   { { STATE_PSRING }, 'i' }
   4478 };
   4479 
   4480 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
   4481   { { OPERAND_art }, 'o' }
   4482 };
   4483 
   4484 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
   4485   { { STATE_PSEXCM }, 'i' },
   4486   { { STATE_PSRING }, 'i' },
   4487   { { STATE_VECBASE }, 'i' }
   4488 };
   4489 
   4490 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
   4491   { { OPERAND_art }, 'i' }
   4492 };
   4493 
   4494 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
   4495   { { STATE_PSEXCM }, 'i' },
   4496   { { STATE_PSRING }, 'i' },
   4497   { { STATE_VECBASE }, 'o' }
   4498 };
   4499 
   4500 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
   4501   { { OPERAND_art }, 'm' }
   4502 };
   4503 
   4504 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
   4505   { { STATE_PSEXCM }, 'i' },
   4506   { { STATE_PSRING }, 'i' },
   4507   { { STATE_VECBASE }, 'm' }
   4508 };
   4509 
   4510 static xtensa_arg_internal Iclass_xt_mul16_args[] = {
   4511   { { OPERAND_arr }, 'o' },
   4512   { { OPERAND_ars }, 'i' },
   4513   { { OPERAND_art }, 'i' }
   4514 };
   4515 
   4516 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
   4517   { { OPERAND_arr }, 'o' },
   4518   { { OPERAND_ars }, 'i' },
   4519   { { OPERAND_art }, 'i' }
   4520 };
   4521 
   4522 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
   4523   { { OPERAND_ars }, 'i' },
   4524   { { OPERAND_art }, 'i' }
   4525 };
   4526 
   4527 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
   4528   { { STATE_ACC }, 'o' }
   4529 };
   4530 
   4531 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
   4532   { { OPERAND_ars }, 'i' },
   4533   { { OPERAND_my }, 'i' }
   4534 };
   4535 
   4536 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
   4537   { { STATE_ACC }, 'o' }
   4538 };
   4539 
   4540 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
   4541   { { OPERAND_mx }, 'i' },
   4542   { { OPERAND_art }, 'i' }
   4543 };
   4544 
   4545 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
   4546   { { STATE_ACC }, 'o' }
   4547 };
   4548 
   4549 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
   4550   { { OPERAND_mx }, 'i' },
   4551   { { OPERAND_my }, 'i' }
   4552 };
   4553 
   4554 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
   4555   { { STATE_ACC }, 'o' }
   4556 };
   4557 
   4558 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
   4559   { { OPERAND_ars }, 'i' },
   4560   { { OPERAND_art }, 'i' }
   4561 };
   4562 
   4563 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
   4564   { { STATE_ACC }, 'm' }
   4565 };
   4566 
   4567 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
   4568   { { OPERAND_ars }, 'i' },
   4569   { { OPERAND_my }, 'i' }
   4570 };
   4571 
   4572 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
   4573   { { STATE_ACC }, 'm' }
   4574 };
   4575 
   4576 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
   4577   { { OPERAND_mx }, 'i' },
   4578   { { OPERAND_art }, 'i' }
   4579 };
   4580 
   4581 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
   4582   { { STATE_ACC }, 'm' }
   4583 };
   4584 
   4585 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
   4586   { { OPERAND_mx }, 'i' },
   4587   { { OPERAND_my }, 'i' }
   4588 };
   4589 
   4590 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
   4591   { { STATE_ACC }, 'm' }
   4592 };
   4593 
   4594 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
   4595   { { OPERAND_mw }, 'o' },
   4596   { { OPERAND_ars }, 'm' },
   4597   { { OPERAND_mx }, 'i' },
   4598   { { OPERAND_art }, 'i' }
   4599 };
   4600 
   4601 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
   4602   { { STATE_ACC }, 'm' }
   4603 };
   4604 
   4605 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
   4606   { { OPERAND_mw }, 'o' },
   4607   { { OPERAND_ars }, 'm' },
   4608   { { OPERAND_mx }, 'i' },
   4609   { { OPERAND_my }, 'i' }
   4610 };
   4611 
   4612 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
   4613   { { STATE_ACC }, 'm' }
   4614 };
   4615 
   4616 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
   4617   { { OPERAND_mw }, 'o' },
   4618   { { OPERAND_ars }, 'm' }
   4619 };
   4620 
   4621 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
   4622   { { OPERAND_art }, 'o' },
   4623   { { OPERAND_mr0 }, 'i' }
   4624 };
   4625 
   4626 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
   4627   { { OPERAND_art }, 'i' },
   4628   { { OPERAND_mr0 }, 'o' }
   4629 };
   4630 
   4631 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
   4632   { { OPERAND_art }, 'm' },
   4633   { { OPERAND_mr0 }, 'm' }
   4634 };
   4635 
   4636 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
   4637   { { OPERAND_art }, 'o' },
   4638   { { OPERAND_mr1 }, 'i' }
   4639 };
   4640 
   4641 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
   4642   { { OPERAND_art }, 'i' },
   4643   { { OPERAND_mr1 }, 'o' }
   4644 };
   4645 
   4646 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
   4647   { { OPERAND_art }, 'm' },
   4648   { { OPERAND_mr1 }, 'm' }
   4649 };
   4650 
   4651 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
   4652   { { OPERAND_art }, 'o' },
   4653   { { OPERAND_mr2 }, 'i' }
   4654 };
   4655 
   4656 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
   4657   { { OPERAND_art }, 'i' },
   4658   { { OPERAND_mr2 }, 'o' }
   4659 };
   4660 
   4661 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
   4662   { { OPERAND_art }, 'm' },
   4663   { { OPERAND_mr2 }, 'm' }
   4664 };
   4665 
   4666 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
   4667   { { OPERAND_art }, 'o' },
   4668   { { OPERAND_mr3 }, 'i' }
   4669 };
   4670 
   4671 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
   4672   { { OPERAND_art }, 'i' },
   4673   { { OPERAND_mr3 }, 'o' }
   4674 };
   4675 
   4676 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
   4677   { { OPERAND_art }, 'm' },
   4678   { { OPERAND_mr3 }, 'm' }
   4679 };
   4680 
   4681 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
   4682   { { OPERAND_art }, 'o' }
   4683 };
   4684 
   4685 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
   4686   { { STATE_ACC }, 'i' }
   4687 };
   4688 
   4689 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
   4690   { { OPERAND_art }, 'i' }
   4691 };
   4692 
   4693 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
   4694   { { STATE_ACC }, 'm' }
   4695 };
   4696 
   4697 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
   4698   { { OPERAND_art }, 'm' }
   4699 };
   4700 
   4701 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
   4702   { { STATE_ACC }, 'm' }
   4703 };
   4704 
   4705 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
   4706   { { OPERAND_art }, 'o' }
   4707 };
   4708 
   4709 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
   4710   { { STATE_ACC }, 'i' }
   4711 };
   4712 
   4713 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
   4714   { { OPERAND_art }, 'i' }
   4715 };
   4716 
   4717 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
   4718   { { STATE_ACC }, 'm' }
   4719 };
   4720 
   4721 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
   4722   { { OPERAND_art }, 'm' }
   4723 };
   4724 
   4725 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
   4726   { { STATE_ACC }, 'm' }
   4727 };
   4728 
   4729 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
   4730   { { OPERAND_s }, 'i' }
   4731 };
   4732 
   4733 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
   4734   { { STATE_PSWOE }, 'o' },
   4735   { { STATE_PSCALLINC }, 'o' },
   4736   { { STATE_PSOWB }, 'o' },
   4737   { { STATE_PSRING }, 'm' },
   4738   { { STATE_PSUM }, 'o' },
   4739   { { STATE_PSEXCM }, 'm' },
   4740   { { STATE_PSINTLEVEL }, 'o' },
   4741   { { STATE_EPC1 }, 'i' },
   4742   { { STATE_EPC2 }, 'i' },
   4743   { { STATE_EPC3 }, 'i' },
   4744   { { STATE_EPC4 }, 'i' },
   4745   { { STATE_EPC5 }, 'i' },
   4746   { { STATE_EPC6 }, 'i' },
   4747   { { STATE_EPC7 }, 'i' },
   4748   { { STATE_EPS2 }, 'i' },
   4749   { { STATE_EPS3 }, 'i' },
   4750   { { STATE_EPS4 }, 'i' },
   4751   { { STATE_EPS5 }, 'i' },
   4752   { { STATE_EPS6 }, 'i' },
   4753   { { STATE_EPS7 }, 'i' },
   4754   { { STATE_InOCDMode }, 'm' }
   4755 };
   4756 
   4757 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
   4758   { { OPERAND_s }, 'i' }
   4759 };
   4760 
   4761 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
   4762   { { STATE_PSEXCM }, 'i' },
   4763   { { STATE_PSRING }, 'i' },
   4764   { { STATE_PSINTLEVEL }, 'o' }
   4765 };
   4766 
   4767 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
   4768   { { OPERAND_art }, 'o' }
   4769 };
   4770 
   4771 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
   4772   { { STATE_PSEXCM }, 'i' },
   4773   { { STATE_PSRING }, 'i' },
   4774   { { STATE_INTERRUPT }, 'i' }
   4775 };
   4776 
   4777 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
   4778   { { OPERAND_art }, 'i' }
   4779 };
   4780 
   4781 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
   4782   { { STATE_PSEXCM }, 'i' },
   4783   { { STATE_PSRING }, 'i' },
   4784   { { STATE_XTSYNC }, 'o' },
   4785   { { STATE_INTERRUPT }, 'm' }
   4786 };
   4787 
   4788 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
   4789   { { OPERAND_art }, 'i' }
   4790 };
   4791 
   4792 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
   4793   { { STATE_PSEXCM }, 'i' },
   4794   { { STATE_PSRING }, 'i' },
   4795   { { STATE_XTSYNC }, 'o' },
   4796   { { STATE_INTERRUPT }, 'm' }
   4797 };
   4798 
   4799 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
   4800   { { OPERAND_art }, 'o' }
   4801 };
   4802 
   4803 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
   4804   { { STATE_PSEXCM }, 'i' },
   4805   { { STATE_PSRING }, 'i' },
   4806   { { STATE_INTENABLE }, 'i' }
   4807 };
   4808 
   4809 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
   4810   { { OPERAND_art }, 'i' }
   4811 };
   4812 
   4813 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
   4814   { { STATE_PSEXCM }, 'i' },
   4815   { { STATE_PSRING }, 'i' },
   4816   { { STATE_INTENABLE }, 'o' }
   4817 };
   4818 
   4819 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
   4820   { { OPERAND_art }, 'm' }
   4821 };
   4822 
   4823 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
   4824   { { STATE_PSEXCM }, 'i' },
   4825   { { STATE_PSRING }, 'i' },
   4826   { { STATE_INTENABLE }, 'm' }
   4827 };
   4828 
   4829 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
   4830   { { OPERAND_imms }, 'i' },
   4831   { { OPERAND_immt }, 'i' }
   4832 };
   4833 
   4834 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
   4835   { { STATE_PSEXCM }, 'i' },
   4836   { { STATE_PSINTLEVEL }, 'i' }
   4837 };
   4838 
   4839 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
   4840   { { OPERAND_imms }, 'i' }
   4841 };
   4842 
   4843 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
   4844   { { STATE_PSEXCM }, 'i' },
   4845   { { STATE_PSINTLEVEL }, 'i' }
   4846 };
   4847 
   4848 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
   4849   { { OPERAND_art }, 'o' }
   4850 };
   4851 
   4852 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
   4853   { { STATE_PSEXCM }, 'i' },
   4854   { { STATE_PSRING }, 'i' },
   4855   { { STATE_DBREAKA0 }, 'i' }
   4856 };
   4857 
   4858 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
   4859   { { OPERAND_art }, 'i' }
   4860 };
   4861 
   4862 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
   4863   { { STATE_PSEXCM }, 'i' },
   4864   { { STATE_PSRING }, 'i' },
   4865   { { STATE_DBREAKA0 }, 'o' },
   4866   { { STATE_XTSYNC }, 'o' }
   4867 };
   4868 
   4869 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
   4870   { { OPERAND_art }, 'm' }
   4871 };
   4872 
   4873 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
   4874   { { STATE_PSEXCM }, 'i' },
   4875   { { STATE_PSRING }, 'i' },
   4876   { { STATE_DBREAKA0 }, 'm' },
   4877   { { STATE_XTSYNC }, 'o' }
   4878 };
   4879 
   4880 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
   4881   { { OPERAND_art }, 'o' }
   4882 };
   4883 
   4884 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
   4885   { { STATE_PSEXCM }, 'i' },
   4886   { { STATE_PSRING }, 'i' },
   4887   { { STATE_DBREAKC0 }, 'i' }
   4888 };
   4889 
   4890 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
   4891   { { OPERAND_art }, 'i' }
   4892 };
   4893 
   4894 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
   4895   { { STATE_PSEXCM }, 'i' },
   4896   { { STATE_PSRING }, 'i' },
   4897   { { STATE_DBREAKC0 }, 'o' },
   4898   { { STATE_XTSYNC }, 'o' }
   4899 };
   4900 
   4901 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
   4902   { { OPERAND_art }, 'm' }
   4903 };
   4904 
   4905 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
   4906   { { STATE_PSEXCM }, 'i' },
   4907   { { STATE_PSRING }, 'i' },
   4908   { { STATE_DBREAKC0 }, 'm' },
   4909   { { STATE_XTSYNC }, 'o' }
   4910 };
   4911 
   4912 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
   4913   { { OPERAND_art }, 'o' }
   4914 };
   4915 
   4916 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
   4917   { { STATE_PSEXCM }, 'i' },
   4918   { { STATE_PSRING }, 'i' },
   4919   { { STATE_DBREAKA1 }, 'i' }
   4920 };
   4921 
   4922 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
   4923   { { OPERAND_art }, 'i' }
   4924 };
   4925 
   4926 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
   4927   { { STATE_PSEXCM }, 'i' },
   4928   { { STATE_PSRING }, 'i' },
   4929   { { STATE_DBREAKA1 }, 'o' },
   4930   { { STATE_XTSYNC }, 'o' }
   4931 };
   4932 
   4933 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
   4934   { { OPERAND_art }, 'm' }
   4935 };
   4936 
   4937 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
   4938   { { STATE_PSEXCM }, 'i' },
   4939   { { STATE_PSRING }, 'i' },
   4940   { { STATE_DBREAKA1 }, 'm' },
   4941   { { STATE_XTSYNC }, 'o' }
   4942 };
   4943 
   4944 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
   4945   { { OPERAND_art }, 'o' }
   4946 };
   4947 
   4948 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
   4949   { { STATE_PSEXCM }, 'i' },
   4950   { { STATE_PSRING }, 'i' },
   4951   { { STATE_DBREAKC1 }, 'i' }
   4952 };
   4953 
   4954 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
   4955   { { OPERAND_art }, 'i' }
   4956 };
   4957 
   4958 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
   4959   { { STATE_PSEXCM }, 'i' },
   4960   { { STATE_PSRING }, 'i' },
   4961   { { STATE_DBREAKC1 }, 'o' },
   4962   { { STATE_XTSYNC }, 'o' }
   4963 };
   4964 
   4965 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
   4966   { { OPERAND_art }, 'm' }
   4967 };
   4968 
   4969 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
   4970   { { STATE_PSEXCM }, 'i' },
   4971   { { STATE_PSRING }, 'i' },
   4972   { { STATE_DBREAKC1 }, 'm' },
   4973   { { STATE_XTSYNC }, 'o' }
   4974 };
   4975 
   4976 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
   4977   { { OPERAND_art }, 'o' }
   4978 };
   4979 
   4980 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
   4981   { { STATE_PSEXCM }, 'i' },
   4982   { { STATE_PSRING }, 'i' },
   4983   { { STATE_IBREAKA0 }, 'i' }
   4984 };
   4985 
   4986 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
   4987   { { OPERAND_art }, 'i' }
   4988 };
   4989 
   4990 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
   4991   { { STATE_PSEXCM }, 'i' },
   4992   { { STATE_PSRING }, 'i' },
   4993   { { STATE_IBREAKA0 }, 'o' }
   4994 };
   4995 
   4996 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
   4997   { { OPERAND_art }, 'm' }
   4998 };
   4999 
   5000 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
   5001   { { STATE_PSEXCM }, 'i' },
   5002   { { STATE_PSRING }, 'i' },
   5003   { { STATE_IBREAKA0 }, 'm' }
   5004 };
   5005 
   5006 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
   5007   { { OPERAND_art }, 'o' }
   5008 };
   5009 
   5010 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
   5011   { { STATE_PSEXCM }, 'i' },
   5012   { { STATE_PSRING }, 'i' },
   5013   { { STATE_IBREAKA1 }, 'i' }
   5014 };
   5015 
   5016 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
   5017   { { OPERAND_art }, 'i' }
   5018 };
   5019 
   5020 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
   5021   { { STATE_PSEXCM }, 'i' },
   5022   { { STATE_PSRING }, 'i' },
   5023   { { STATE_IBREAKA1 }, 'o' }
   5024 };
   5025 
   5026 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
   5027   { { OPERAND_art }, 'm' }
   5028 };
   5029 
   5030 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
   5031   { { STATE_PSEXCM }, 'i' },
   5032   { { STATE_PSRING }, 'i' },
   5033   { { STATE_IBREAKA1 }, 'm' }
   5034 };
   5035 
   5036 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
   5037   { { OPERAND_art }, 'o' }
   5038 };
   5039 
   5040 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
   5041   { { STATE_PSEXCM }, 'i' },
   5042   { { STATE_PSRING }, 'i' },
   5043   { { STATE_IBREAKENABLE }, 'i' }
   5044 };
   5045 
   5046 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
   5047   { { OPERAND_art }, 'i' }
   5048 };
   5049 
   5050 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
   5051   { { STATE_PSEXCM }, 'i' },
   5052   { { STATE_PSRING }, 'i' },
   5053   { { STATE_IBREAKENABLE }, 'o' }
   5054 };
   5055 
   5056 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
   5057   { { OPERAND_art }, 'm' }
   5058 };
   5059 
   5060 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
   5061   { { STATE_PSEXCM }, 'i' },
   5062   { { STATE_PSRING }, 'i' },
   5063   { { STATE_IBREAKENABLE }, 'm' }
   5064 };
   5065 
   5066 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
   5067   { { OPERAND_art }, 'o' }
   5068 };
   5069 
   5070 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
   5071   { { STATE_PSEXCM }, 'i' },
   5072   { { STATE_PSRING }, 'i' },
   5073   { { STATE_DEBUGCAUSE }, 'i' },
   5074   { { STATE_DBNUM }, 'i' }
   5075 };
   5076 
   5077 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
   5078   { { OPERAND_art }, 'i' }
   5079 };
   5080 
   5081 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
   5082   { { STATE_PSEXCM }, 'i' },
   5083   { { STATE_PSRING }, 'i' },
   5084   { { STATE_DEBUGCAUSE }, 'o' },
   5085   { { STATE_DBNUM }, 'o' }
   5086 };
   5087 
   5088 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
   5089   { { OPERAND_art }, 'm' }
   5090 };
   5091 
   5092 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
   5093   { { STATE_PSEXCM }, 'i' },
   5094   { { STATE_PSRING }, 'i' },
   5095   { { STATE_DEBUGCAUSE }, 'm' },
   5096   { { STATE_DBNUM }, 'm' }
   5097 };
   5098 
   5099 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
   5100   { { OPERAND_art }, 'o' }
   5101 };
   5102 
   5103 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
   5104   { { STATE_PSEXCM }, 'i' },
   5105   { { STATE_PSRING }, 'i' },
   5106   { { STATE_ICOUNT }, 'i' }
   5107 };
   5108 
   5109 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
   5110   { { OPERAND_art }, 'i' }
   5111 };
   5112 
   5113 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
   5114   { { STATE_PSEXCM }, 'i' },
   5115   { { STATE_PSRING }, 'i' },
   5116   { { STATE_XTSYNC }, 'o' },
   5117   { { STATE_ICOUNT }, 'o' }
   5118 };
   5119 
   5120 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
   5121   { { OPERAND_art }, 'm' }
   5122 };
   5123 
   5124 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
   5125   { { STATE_PSEXCM }, 'i' },
   5126   { { STATE_PSRING }, 'i' },
   5127   { { STATE_XTSYNC }, 'o' },
   5128   { { STATE_ICOUNT }, 'm' }
   5129 };
   5130 
   5131 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
   5132   { { OPERAND_art }, 'o' }
   5133 };
   5134 
   5135 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
   5136   { { STATE_PSEXCM }, 'i' },
   5137   { { STATE_PSRING }, 'i' },
   5138   { { STATE_ICOUNTLEVEL }, 'i' }
   5139 };
   5140 
   5141 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
   5142   { { OPERAND_art }, 'i' }
   5143 };
   5144 
   5145 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
   5146   { { STATE_PSEXCM }, 'i' },
   5147   { { STATE_PSRING }, 'i' },
   5148   { { STATE_ICOUNTLEVEL }, 'o' }
   5149 };
   5150 
   5151 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
   5152   { { OPERAND_art }, 'm' }
   5153 };
   5154 
   5155 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
   5156   { { STATE_PSEXCM }, 'i' },
   5157   { { STATE_PSRING }, 'i' },
   5158   { { STATE_ICOUNTLEVEL }, 'm' }
   5159 };
   5160 
   5161 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
   5162   { { OPERAND_art }, 'o' }
   5163 };
   5164 
   5165 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
   5166   { { STATE_PSEXCM }, 'i' },
   5167   { { STATE_PSRING }, 'i' },
   5168   { { STATE_DDR }, 'i' }
   5169 };
   5170 
   5171 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
   5172   { { OPERAND_art }, 'i' }
   5173 };
   5174 
   5175 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
   5176   { { STATE_PSEXCM }, 'i' },
   5177   { { STATE_PSRING }, 'i' },
   5178   { { STATE_XTSYNC }, 'o' },
   5179   { { STATE_DDR }, 'o' }
   5180 };
   5181 
   5182 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
   5183   { { OPERAND_art }, 'm' }
   5184 };
   5185 
   5186 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
   5187   { { STATE_PSEXCM }, 'i' },
   5188   { { STATE_PSRING }, 'i' },
   5189   { { STATE_XTSYNC }, 'o' },
   5190   { { STATE_DDR }, 'm' }
   5191 };
   5192 
   5193 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
   5194   { { OPERAND_imms }, 'i' }
   5195 };
   5196 
   5197 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
   5198   { { STATE_InOCDMode }, 'm' },
   5199   { { STATE_EPC6 }, 'i' },
   5200   { { STATE_PSWOE }, 'o' },
   5201   { { STATE_PSCALLINC }, 'o' },
   5202   { { STATE_PSOWB }, 'o' },
   5203   { { STATE_PSRING }, 'o' },
   5204   { { STATE_PSUM }, 'o' },
   5205   { { STATE_PSEXCM }, 'o' },
   5206   { { STATE_PSINTLEVEL }, 'o' },
   5207   { { STATE_EPS6 }, 'i' }
   5208 };
   5209 
   5210 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
   5211   { { STATE_InOCDMode }, 'm' }
   5212 };
   5213 
   5214 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
   5215   { { OPERAND_art }, 'i' }
   5216 };
   5217 
   5218 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
   5219   { { STATE_PSEXCM }, 'i' },
   5220   { { STATE_PSRING }, 'i' },
   5221   { { STATE_XTSYNC }, 'o' }
   5222 };
   5223 
   5224 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
   5225   { { OPERAND_art }, 'o' }
   5226 };
   5227 
   5228 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
   5229   { { STATE_PSEXCM }, 'i' },
   5230   { { STATE_PSRING }, 'i' },
   5231   { { STATE_CCOUNT }, 'i' }
   5232 };
   5233 
   5234 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
   5235   { { OPERAND_art }, 'i' }
   5236 };
   5237 
   5238 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
   5239   { { STATE_PSEXCM }, 'i' },
   5240   { { STATE_PSRING }, 'i' },
   5241   { { STATE_XTSYNC }, 'o' },
   5242   { { STATE_CCOUNT }, 'o' }
   5243 };
   5244 
   5245 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
   5246   { { OPERAND_art }, 'm' }
   5247 };
   5248 
   5249 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
   5250   { { STATE_PSEXCM }, 'i' },
   5251   { { STATE_PSRING }, 'i' },
   5252   { { STATE_XTSYNC }, 'o' },
   5253   { { STATE_CCOUNT }, 'm' }
   5254 };
   5255 
   5256 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
   5257   { { OPERAND_art }, 'o' }
   5258 };
   5259 
   5260 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
   5261   { { STATE_PSEXCM }, 'i' },
   5262   { { STATE_PSRING }, 'i' },
   5263   { { STATE_CCOMPARE0 }, 'i' }
   5264 };
   5265 
   5266 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
   5267   { { OPERAND_art }, 'i' }
   5268 };
   5269 
   5270 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
   5271   { { STATE_PSEXCM }, 'i' },
   5272   { { STATE_PSRING }, 'i' },
   5273   { { STATE_CCOMPARE0 }, 'o' },
   5274   { { STATE_INTERRUPT }, 'm' }
   5275 };
   5276 
   5277 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
   5278   { { OPERAND_art }, 'm' }
   5279 };
   5280 
   5281 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
   5282   { { STATE_PSEXCM }, 'i' },
   5283   { { STATE_PSRING }, 'i' },
   5284   { { STATE_CCOMPARE0 }, 'm' },
   5285   { { STATE_INTERRUPT }, 'm' }
   5286 };
   5287 
   5288 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
   5289   { { OPERAND_art }, 'o' }
   5290 };
   5291 
   5292 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
   5293   { { STATE_PSEXCM }, 'i' },
   5294   { { STATE_PSRING }, 'i' },
   5295   { { STATE_CCOMPARE1 }, 'i' }
   5296 };
   5297 
   5298 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
   5299   { { OPERAND_art }, 'i' }
   5300 };
   5301 
   5302 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
   5303   { { STATE_PSEXCM }, 'i' },
   5304   { { STATE_PSRING }, 'i' },
   5305   { { STATE_CCOMPARE1 }, 'o' },
   5306   { { STATE_INTERRUPT }, 'm' }
   5307 };
   5308 
   5309 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
   5310   { { OPERAND_art }, 'm' }
   5311 };
   5312 
   5313 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
   5314   { { STATE_PSEXCM }, 'i' },
   5315   { { STATE_PSRING }, 'i' },
   5316   { { STATE_CCOMPARE1 }, 'm' },
   5317   { { STATE_INTERRUPT }, 'm' }
   5318 };
   5319 
   5320 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
   5321   { { OPERAND_art }, 'o' }
   5322 };
   5323 
   5324 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
   5325   { { STATE_PSEXCM }, 'i' },
   5326   { { STATE_PSRING }, 'i' },
   5327   { { STATE_CCOMPARE2 }, 'i' }
   5328 };
   5329 
   5330 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
   5331   { { OPERAND_art }, 'i' }
   5332 };
   5333 
   5334 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
   5335   { { STATE_PSEXCM }, 'i' },
   5336   { { STATE_PSRING }, 'i' },
   5337   { { STATE_CCOMPARE2 }, 'o' },
   5338   { { STATE_INTERRUPT }, 'm' }
   5339 };
   5340 
   5341 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
   5342   { { OPERAND_art }, 'm' }
   5343 };
   5344 
   5345 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
   5346   { { STATE_PSEXCM }, 'i' },
   5347   { { STATE_PSRING }, 'i' },
   5348   { { STATE_CCOMPARE2 }, 'm' },
   5349   { { STATE_INTERRUPT }, 'm' }
   5350 };
   5351 
   5352 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
   5353   { { OPERAND_ars }, 'i' },
   5354   { { OPERAND_uimm8x4 }, 'i' }
   5355 };
   5356 
   5357 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
   5358   { { OPERAND_ars }, 'i' },
   5359   { { OPERAND_uimm4x16 }, 'i' }
   5360 };
   5361 
   5362 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
   5363   { { STATE_PSEXCM }, 'i' },
   5364   { { STATE_PSRING }, 'i' }
   5365 };
   5366 
   5367 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
   5368   { { OPERAND_ars }, 'i' },
   5369   { { OPERAND_uimm8x4 }, 'i' }
   5370 };
   5371 
   5372 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
   5373   { { STATE_PSEXCM }, 'i' },
   5374   { { STATE_PSRING }, 'i' }
   5375 };
   5376 
   5377 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
   5378   { { OPERAND_art }, 'o' },
   5379   { { OPERAND_ars }, 'i' }
   5380 };
   5381 
   5382 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
   5383   { { STATE_PSEXCM }, 'i' },
   5384   { { STATE_PSRING }, 'i' }
   5385 };
   5386 
   5387 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
   5388   { { OPERAND_art }, 'i' },
   5389   { { OPERAND_ars }, 'i' }
   5390 };
   5391 
   5392 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
   5393   { { STATE_PSEXCM }, 'i' },
   5394   { { STATE_PSRING }, 'i' }
   5395 };
   5396 
   5397 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
   5398   { { OPERAND_ars }, 'i' },
   5399   { { OPERAND_uimm8x4 }, 'i' }
   5400 };
   5401 
   5402 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
   5403   { { OPERAND_ars }, 'i' },
   5404   { { OPERAND_uimm4x16 }, 'i' }
   5405 };
   5406 
   5407 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
   5408   { { STATE_PSEXCM }, 'i' },
   5409   { { STATE_PSRING }, 'i' }
   5410 };
   5411 
   5412 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
   5413   { { OPERAND_ars }, 'i' },
   5414   { { OPERAND_uimm8x4 }, 'i' }
   5415 };
   5416 
   5417 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
   5418   { { STATE_PSEXCM }, 'i' },
   5419   { { STATE_PSRING }, 'i' }
   5420 };
   5421 
   5422 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
   5423   { { OPERAND_ars }, 'i' },
   5424   { { OPERAND_uimm8x4 }, 'i' }
   5425 };
   5426 
   5427 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
   5428   { { OPERAND_ars }, 'i' },
   5429   { { OPERAND_uimm4x16 }, 'i' }
   5430 };
   5431 
   5432 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
   5433   { { STATE_PSEXCM }, 'i' },
   5434   { { STATE_PSRING }, 'i' }
   5435 };
   5436 
   5437 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
   5438   { { OPERAND_art }, 'i' },
   5439   { { OPERAND_ars }, 'i' }
   5440 };
   5441 
   5442 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
   5443   { { STATE_PSEXCM }, 'i' },
   5444   { { STATE_PSRING }, 'i' }
   5445 };
   5446 
   5447 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
   5448   { { OPERAND_art }, 'o' },
   5449   { { OPERAND_ars }, 'i' }
   5450 };
   5451 
   5452 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
   5453   { { STATE_PSEXCM }, 'i' },
   5454   { { STATE_PSRING }, 'i' }
   5455 };
   5456 
   5457 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
   5458   { { OPERAND_art }, 'i' }
   5459 };
   5460 
   5461 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
   5462   { { STATE_PSEXCM }, 'i' },
   5463   { { STATE_PSRING }, 'i' },
   5464   { { STATE_PTBASE }, 'o' },
   5465   { { STATE_XTSYNC }, 'o' }
   5466 };
   5467 
   5468 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
   5469   { { OPERAND_art }, 'o' }
   5470 };
   5471 
   5472 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
   5473   { { STATE_PSEXCM }, 'i' },
   5474   { { STATE_PSRING }, 'i' },
   5475   { { STATE_PTBASE }, 'i' },
   5476   { { STATE_EXCVADDR }, 'i' }
   5477 };
   5478 
   5479 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
   5480   { { OPERAND_art }, 'm' }
   5481 };
   5482 
   5483 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
   5484   { { STATE_PSEXCM }, 'i' },
   5485   { { STATE_PSRING }, 'i' },
   5486   { { STATE_PTBASE }, 'm' },
   5487   { { STATE_EXCVADDR }, 'i' },
   5488   { { STATE_XTSYNC }, 'o' }
   5489 };
   5490 
   5491 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
   5492   { { OPERAND_art }, 'o' }
   5493 };
   5494 
   5495 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
   5496   { { STATE_PSEXCM }, 'i' },
   5497   { { STATE_PSRING }, 'i' },
   5498   { { STATE_ASID3 }, 'i' },
   5499   { { STATE_ASID2 }, 'i' },
   5500   { { STATE_ASID1 }, 'i' }
   5501 };
   5502 
   5503 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
   5504   { { OPERAND_art }, 'i' }
   5505 };
   5506 
   5507 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
   5508   { { STATE_XTSYNC }, 'o' },
   5509   { { STATE_PSEXCM }, 'i' },
   5510   { { STATE_PSRING }, 'i' },
   5511   { { STATE_ASID3 }, 'o' },
   5512   { { STATE_ASID2 }, 'o' },
   5513   { { STATE_ASID1 }, 'o' }
   5514 };
   5515 
   5516 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
   5517   { { OPERAND_art }, 'm' }
   5518 };
   5519 
   5520 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
   5521   { { STATE_XTSYNC }, 'o' },
   5522   { { STATE_PSEXCM }, 'i' },
   5523   { { STATE_PSRING }, 'i' },
   5524   { { STATE_ASID3 }, 'm' },
   5525   { { STATE_ASID2 }, 'm' },
   5526   { { STATE_ASID1 }, 'm' }
   5527 };
   5528 
   5529 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
   5530   { { OPERAND_art }, 'o' }
   5531 };
   5532 
   5533 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
   5534   { { STATE_PSEXCM }, 'i' },
   5535   { { STATE_PSRING }, 'i' },
   5536   { { STATE_INSTPGSZID6 }, 'i' },
   5537   { { STATE_INSTPGSZID5 }, 'i' },
   5538   { { STATE_INSTPGSZID4 }, 'i' }
   5539 };
   5540 
   5541 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
   5542   { { OPERAND_art }, 'i' }
   5543 };
   5544 
   5545 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
   5546   { { STATE_XTSYNC }, 'o' },
   5547   { { STATE_PSEXCM }, 'i' },
   5548   { { STATE_PSRING }, 'i' },
   5549   { { STATE_INSTPGSZID6 }, 'o' },
   5550   { { STATE_INSTPGSZID5 }, 'o' },
   5551   { { STATE_INSTPGSZID4 }, 'o' }
   5552 };
   5553 
   5554 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
   5555   { { OPERAND_art }, 'm' }
   5556 };
   5557 
   5558 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
   5559   { { STATE_XTSYNC }, 'o' },
   5560   { { STATE_PSEXCM }, 'i' },
   5561   { { STATE_PSRING }, 'i' },
   5562   { { STATE_INSTPGSZID6 }, 'm' },
   5563   { { STATE_INSTPGSZID5 }, 'm' },
   5564   { { STATE_INSTPGSZID4 }, 'm' }
   5565 };
   5566 
   5567 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
   5568   { { OPERAND_art }, 'o' }
   5569 };
   5570 
   5571 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
   5572   { { STATE_PSEXCM }, 'i' },
   5573   { { STATE_PSRING }, 'i' },
   5574   { { STATE_DATAPGSZID6 }, 'i' },
   5575   { { STATE_DATAPGSZID5 }, 'i' },
   5576   { { STATE_DATAPGSZID4 }, 'i' }
   5577 };
   5578 
   5579 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
   5580   { { OPERAND_art }, 'i' }
   5581 };
   5582 
   5583 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
   5584   { { STATE_XTSYNC }, 'o' },
   5585   { { STATE_PSEXCM }, 'i' },
   5586   { { STATE_PSRING }, 'i' },
   5587   { { STATE_DATAPGSZID6 }, 'o' },
   5588   { { STATE_DATAPGSZID5 }, 'o' },
   5589   { { STATE_DATAPGSZID4 }, 'o' }
   5590 };
   5591 
   5592 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
   5593   { { OPERAND_art }, 'm' }
   5594 };
   5595 
   5596 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
   5597   { { STATE_XTSYNC }, 'o' },
   5598   { { STATE_PSEXCM }, 'i' },
   5599   { { STATE_PSRING }, 'i' },
   5600   { { STATE_DATAPGSZID6 }, 'm' },
   5601   { { STATE_DATAPGSZID5 }, 'm' },
   5602   { { STATE_DATAPGSZID4 }, 'm' }
   5603 };
   5604 
   5605 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
   5606   { { OPERAND_ars }, 'i' }
   5607 };
   5608 
   5609 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
   5610   { { STATE_PSEXCM }, 'i' },
   5611   { { STATE_PSRING }, 'i' },
   5612   { { STATE_XTSYNC }, 'o' }
   5613 };
   5614 
   5615 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
   5616   { { OPERAND_art }, 'o' },
   5617   { { OPERAND_ars }, 'i' }
   5618 };
   5619 
   5620 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
   5621   { { STATE_PSEXCM }, 'i' },
   5622   { { STATE_PSRING }, 'i' }
   5623 };
   5624 
   5625 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
   5626   { { OPERAND_art }, 'i' },
   5627   { { OPERAND_ars }, 'i' }
   5628 };
   5629 
   5630 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
   5631   { { STATE_PSEXCM }, 'i' },
   5632   { { STATE_PSRING }, 'i' },
   5633   { { STATE_XTSYNC }, 'o' }
   5634 };
   5635 
   5636 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
   5637   { { OPERAND_ars }, 'i' }
   5638 };
   5639 
   5640 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
   5641   { { STATE_PSEXCM }, 'i' },
   5642   { { STATE_PSRING }, 'i' }
   5643 };
   5644 
   5645 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
   5646   { { OPERAND_art }, 'o' },
   5647   { { OPERAND_ars }, 'i' }
   5648 };
   5649 
   5650 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
   5651   { { STATE_PSEXCM }, 'i' },
   5652   { { STATE_PSRING }, 'i' }
   5653 };
   5654 
   5655 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
   5656   { { OPERAND_art }, 'i' },
   5657   { { OPERAND_ars }, 'i' }
   5658 };
   5659 
   5660 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
   5661   { { STATE_PSEXCM }, 'i' },
   5662   { { STATE_PSRING }, 'i' }
   5663 };
   5664 
   5665 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
   5666   { { STATE_PTBASE }, 'i' },
   5667   { { STATE_EXCVADDR }, 'i' }
   5668 };
   5669 
   5670 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
   5671   { { STATE_EXCVADDR }, 'i' }
   5672 };
   5673 
   5674 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
   5675   { { STATE_EXCVADDR }, 'i' }
   5676 };
   5677 
   5678 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
   5679   { { OPERAND_art }, 'o' }
   5680 };
   5681 
   5682 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
   5683   { { STATE_PSEXCM }, 'i' },
   5684   { { STATE_PSRING }, 'i' },
   5685   { { STATE_CPENABLE }, 'i' }
   5686 };
   5687 
   5688 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
   5689   { { OPERAND_art }, 'i' }
   5690 };
   5691 
   5692 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
   5693   { { STATE_PSEXCM }, 'i' },
   5694   { { STATE_PSRING }, 'i' },
   5695   { { STATE_CPENABLE }, 'o' }
   5696 };
   5697 
   5698 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
   5699   { { OPERAND_art }, 'm' }
   5700 };
   5701 
   5702 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
   5703   { { STATE_PSEXCM }, 'i' },
   5704   { { STATE_PSRING }, 'i' },
   5705   { { STATE_CPENABLE }, 'm' }
   5706 };
   5707 
   5708 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
   5709   { { OPERAND_arr }, 'o' },
   5710   { { OPERAND_ars }, 'i' },
   5711   { { OPERAND_tp7 }, 'i' }
   5712 };
   5713 
   5714 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
   5715   { { OPERAND_arr }, 'o' },
   5716   { { OPERAND_ars }, 'i' },
   5717   { { OPERAND_art }, 'i' }
   5718 };
   5719 
   5720 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
   5721   { { OPERAND_art }, 'o' },
   5722   { { OPERAND_ars }, 'i' }
   5723 };
   5724 
   5725 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
   5726   { { OPERAND_arr }, 'o' },
   5727   { { OPERAND_ars }, 'i' },
   5728   { { OPERAND_tp7 }, 'i' }
   5729 };
   5730 
   5731 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
   5732   { { OPERAND_art }, 'o' },
   5733   { { OPERAND_ars }, 'i' },
   5734   { { OPERAND_uimm8x4 }, 'i' }
   5735 };
   5736 
   5737 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
   5738   { { OPERAND_art }, 'i' },
   5739   { { OPERAND_ars }, 'i' },
   5740   { { OPERAND_uimm8x4 }, 'i' }
   5741 };
   5742 
   5743 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
   5744   { { OPERAND_art }, 'm' },
   5745   { { OPERAND_ars }, 'i' },
   5746   { { OPERAND_uimm8x4 }, 'i' }
   5747 };
   5748 
   5749 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
   5750   { { STATE_SCOMPARE1 }, 'i' },
   5751   { { STATE_XTSYNC }, 'i' },
   5752   { { STATE_SCOMPARE1 }, 'i' }
   5753 };
   5754 
   5755 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
   5756   { { OPERAND_art }, 'o' }
   5757 };
   5758 
   5759 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
   5760   { { STATE_SCOMPARE1 }, 'i' }
   5761 };
   5762 
   5763 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
   5764   { { OPERAND_art }, 'i' }
   5765 };
   5766 
   5767 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
   5768   { { STATE_SCOMPARE1 }, 'o' }
   5769 };
   5770 
   5771 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
   5772   { { OPERAND_art }, 'm' }
   5773 };
   5774 
   5775 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
   5776   { { STATE_SCOMPARE1 }, 'm' }
   5777 };
   5778 
   5779 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_args[] = {
   5780   { { OPERAND_art }, 'o' }
   5781 };
   5782 
   5783 static xtensa_arg_internal Iclass_xt_iclass_rsr_atomctl_stateArgs[] = {
   5784   { { STATE_PSEXCM }, 'i' },
   5785   { { STATE_PSRING }, 'i' },
   5786   { { STATE_ATOMCTL }, 'i' }
   5787 };
   5788 
   5789 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_args[] = {
   5790   { { OPERAND_art }, 'i' }
   5791 };
   5792 
   5793 static xtensa_arg_internal Iclass_xt_iclass_wsr_atomctl_stateArgs[] = {
   5794   { { STATE_PSEXCM }, 'i' },
   5795   { { STATE_PSRING }, 'i' },
   5796   { { STATE_ATOMCTL }, 'o' },
   5797   { { STATE_XTSYNC }, 'o' }
   5798 };
   5799 
   5800 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_args[] = {
   5801   { { OPERAND_art }, 'm' }
   5802 };
   5803 
   5804 static xtensa_arg_internal Iclass_xt_iclass_xsr_atomctl_stateArgs[] = {
   5805   { { STATE_PSEXCM }, 'i' },
   5806   { { STATE_PSRING }, 'i' },
   5807   { { STATE_ATOMCTL }, 'm' },
   5808   { { STATE_XTSYNC }, 'o' }
   5809 };
   5810 
   5811 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
   5812   { { OPERAND_arr }, 'o' },
   5813   { { OPERAND_ars }, 'i' },
   5814   { { OPERAND_art }, 'i' }
   5815 };
   5816 
   5817 static xtensa_arg_internal Iclass_xt_iclass_rer_stateArgs[] = {
   5818   { { STATE_PSEXCM }, 'i' },
   5819   { { STATE_PSRING }, 'i' }
   5820 };
   5821 
   5822 static xtensa_arg_internal Iclass_xt_iclass_wer_stateArgs[] = {
   5823   { { STATE_PSEXCM }, 'i' },
   5824   { { STATE_PSRING }, 'i' }
   5825 };
   5826 
   5827 static xtensa_arg_internal Iclass_rur_expstate_args[] = {
   5828   { { OPERAND_arr }, 'o' }
   5829 };
   5830 
   5831 static xtensa_arg_internal Iclass_rur_expstate_stateArgs[] = {
   5832   { { STATE_EXPSTATE }, 'i' },
   5833   { { STATE_CPENABLE }, 'i' }
   5834 };
   5835 
   5836 static xtensa_arg_internal Iclass_wur_expstate_args[] = {
   5837   { { OPERAND_art }, 'i' }
   5838 };
   5839 
   5840 static xtensa_arg_internal Iclass_wur_expstate_stateArgs[] = {
   5841   { { STATE_EXPSTATE }, 'o' },
   5842   { { STATE_CPENABLE }, 'i' }
   5843 };
   5844 
   5845 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_args[] = {
   5846   { { OPERAND_art }, 'o' }
   5847 };
   5848 
   5849 static xtensa_arg_internal Iclass_iclass_READ_IMPWIRE_stateArgs[] = {
   5850   { { STATE_CPENABLE }, 'i' }
   5851 };
   5852 
   5853 static xtensa_interface Iclass_iclass_READ_IMPWIRE_intfArgs[] = {
   5854   INTERFACE_IMPWIRE
   5855 };
   5856 
   5857 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_args[] = {
   5858   { { OPERAND_bitindex }, 'i' }
   5859 };
   5860 
   5861 static xtensa_arg_internal Iclass_iclass_SETB_EXPSTATE_stateArgs[] = {
   5862   { { STATE_EXPSTATE }, 'm' },
   5863   { { STATE_CPENABLE }, 'i' }
   5864 };
   5865 
   5866 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_args[] = {
   5867   { { OPERAND_bitindex }, 'i' }
   5868 };
   5869 
   5870 static xtensa_arg_internal Iclass_iclass_CLRB_EXPSTATE_stateArgs[] = {
   5871   { { STATE_EXPSTATE }, 'm' },
   5872   { { STATE_CPENABLE }, 'i' }
   5873 };
   5874 
   5875 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_args[] = {
   5876   { { OPERAND_art }, 'i' },
   5877   { { OPERAND_ars }, 'i' }
   5878 };
   5879 
   5880 static xtensa_arg_internal Iclass_iclass_WRMSK_EXPSTATE_stateArgs[] = {
   5881   { { STATE_EXPSTATE }, 'm' },
   5882   { { STATE_CPENABLE }, 'i' }
   5883 };
   5884 
   5885 static xtensa_iclass_internal iclasses[] = {
   5886   { 0, 0 /* xt_iclass_excw */,
   5887     0, 0, 0, 0 },
   5888   { 0, 0 /* xt_iclass_rfe */,
   5889     3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
   5890   { 0, 0 /* xt_iclass_rfde */,
   5891     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
   5892   { 0, 0 /* xt_iclass_syscall */,
   5893     0, 0, 0, 0 },
   5894   { 0, 0 /* xt_iclass_simcall */,
   5895     0, 0, 0, 0 },
   5896   { 2, Iclass_xt_iclass_call12_args,
   5897     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
   5898   { 2, Iclass_xt_iclass_call8_args,
   5899     1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
   5900   { 2, Iclass_xt_iclass_call4_args,
   5901     1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
   5902   { 2, Iclass_xt_iclass_callx12_args,
   5903     1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
   5904   { 2, Iclass_xt_iclass_callx8_args,
   5905     1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
   5906   { 2, Iclass_xt_iclass_callx4_args,
   5907     1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
   5908   { 3, Iclass_xt_iclass_entry_args,
   5909     5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
   5910   { 2, Iclass_xt_iclass_movsp_args,
   5911     2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
   5912   { 1, Iclass_xt_iclass_rotw_args,
   5913     3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
   5914   { 1, Iclass_xt_iclass_retw_args,
   5915     4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
   5916   { 0, 0 /* xt_iclass_rfwou */,
   5917     6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
   5918   { 3, Iclass_xt_iclass_l32e_args,
   5919     2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
   5920   { 3, Iclass_xt_iclass_s32e_args,
   5921     2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
   5922   { 1, Iclass_xt_iclass_rsr_windowbase_args,
   5923     3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
   5924   { 1, Iclass_xt_iclass_wsr_windowbase_args,
   5925     3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
   5926   { 1, Iclass_xt_iclass_xsr_windowbase_args,
   5927     3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
   5928   { 1, Iclass_xt_iclass_rsr_windowstart_args,
   5929     3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
   5930   { 1, Iclass_xt_iclass_wsr_windowstart_args,
   5931     3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
   5932   { 1, Iclass_xt_iclass_xsr_windowstart_args,
   5933     3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
   5934   { 3, Iclass_xt_iclass_add_n_args,
   5935     0, 0, 0, 0 },
   5936   { 3, Iclass_xt_iclass_addi_n_args,
   5937     0, 0, 0, 0 },
   5938   { 2, Iclass_xt_iclass_bz6_args,
   5939     0, 0, 0, 0 },
   5940   { 0, 0 /* xt_iclass_ill_n */,
   5941     0, 0, 0, 0 },
   5942   { 3, Iclass_xt_iclass_loadi4_args,
   5943     0, 0, 0, 0 },
   5944   { 2, Iclass_xt_iclass_mov_n_args,
   5945     0, 0, 0, 0 },
   5946   { 2, Iclass_xt_iclass_movi_n_args,
   5947     0, 0, 0, 0 },
   5948   { 0, 0 /* xt_iclass_nopn */,
   5949     0, 0, 0, 0 },
   5950   { 1, Iclass_xt_iclass_retn_args,
   5951     0, 0, 0, 0 },
   5952   { 3, Iclass_xt_iclass_storei4_args,
   5953     0, 0, 0, 0 },
   5954   { 1, Iclass_rur_threadptr_args,
   5955     1, Iclass_rur_threadptr_stateArgs, 0, 0 },
   5956   { 1, Iclass_wur_threadptr_args,
   5957     1, Iclass_wur_threadptr_stateArgs, 0, 0 },
   5958   { 3, Iclass_xt_iclass_addi_args,
   5959     0, 0, 0, 0 },
   5960   { 3, Iclass_xt_iclass_addmi_args,
   5961     0, 0, 0, 0 },
   5962   { 3, Iclass_xt_iclass_addsub_args,
   5963     0, 0, 0, 0 },
   5964   { 3, Iclass_xt_iclass_bit_args,
   5965     0, 0, 0, 0 },
   5966   { 3, Iclass_xt_iclass_bsi8_args,
   5967     0, 0, 0, 0 },
   5968   { 3, Iclass_xt_iclass_bsi8b_args,
   5969     0, 0, 0, 0 },
   5970   { 3, Iclass_xt_iclass_bsi8u_args,
   5971     0, 0, 0, 0 },
   5972   { 3, Iclass_xt_iclass_bst8_args,
   5973     0, 0, 0, 0 },
   5974   { 2, Iclass_xt_iclass_bsz12_args,
   5975     0, 0, 0, 0 },
   5976   { 2, Iclass_xt_iclass_call0_args,
   5977     0, 0, 0, 0 },
   5978   { 2, Iclass_xt_iclass_callx0_args,
   5979     0, 0, 0, 0 },
   5980   { 4, Iclass_xt_iclass_exti_args,
   5981     0, 0, 0, 0 },
   5982   { 0, 0 /* xt_iclass_ill */,
   5983     0, 0, 0, 0 },
   5984   { 1, Iclass_xt_iclass_jump_args,
   5985     0, 0, 0, 0 },
   5986   { 1, Iclass_xt_iclass_jumpx_args,
   5987     0, 0, 0, 0 },
   5988   { 3, Iclass_xt_iclass_l16ui_args,
   5989     0, 0, 0, 0 },
   5990   { 3, Iclass_xt_iclass_l16si_args,
   5991     0, 0, 0, 0 },
   5992   { 3, Iclass_xt_iclass_l32i_args,
   5993     0, 0, 0, 0 },
   5994   { 2, Iclass_xt_iclass_l32r_args,
   5995     2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
   5996   { 3, Iclass_xt_iclass_l8i_args,
   5997     0, 0, 0, 0 },
   5998   { 2, Iclass_xt_iclass_loop_args,
   5999     3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
   6000   { 2, Iclass_xt_iclass_loopz_args,
   6001     3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
   6002   { 2, Iclass_xt_iclass_movi_args,
   6003     0, 0, 0, 0 },
   6004   { 3, Iclass_xt_iclass_movz_args,
   6005     0, 0, 0, 0 },
   6006   { 2, Iclass_xt_iclass_neg_args,
   6007     0, 0, 0, 0 },
   6008   { 0, 0 /* xt_iclass_nop */,
   6009     0, 0, 0, 0 },
   6010   { 1, Iclass_xt_iclass_return_args,
   6011     0, 0, 0, 0 },
   6012   { 3, Iclass_xt_iclass_s16i_args,
   6013     0, 0, 0, 0 },
   6014   { 3, Iclass_xt_iclass_s32i_args,
   6015     0, 0, 0, 0 },
   6016   { 3, Iclass_xt_iclass_s8i_args,
   6017     0, 0, 0, 0 },
   6018   { 1, Iclass_xt_iclass_sar_args,
   6019     1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
   6020   { 1, Iclass_xt_iclass_sari_args,
   6021     1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
   6022   { 2, Iclass_xt_iclass_shifts_args,
   6023     1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
   6024   { 3, Iclass_xt_iclass_shiftst_args,
   6025     1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
   6026   { 2, Iclass_xt_iclass_shiftt_args,
   6027     1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
   6028   { 3, Iclass_xt_iclass_slli_args,
   6029     0, 0, 0, 0 },
   6030   { 3, Iclass_xt_iclass_srai_args,
   6031     0, 0, 0, 0 },
   6032   { 3, Iclass_xt_iclass_srli_args,
   6033     0, 0, 0, 0 },
   6034   { 0, 0 /* xt_iclass_memw */,
   6035     0, 0, 0, 0 },
   6036   { 0, 0 /* xt_iclass_extw */,
   6037     0, 0, 0, 0 },
   6038   { 0, 0 /* xt_iclass_isync */,
   6039     0, 0, 0, 0 },
   6040   { 0, 0 /* xt_iclass_sync */,
   6041     1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
   6042   { 2, Iclass_xt_iclass_rsil_args,
   6043     7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
   6044   { 1, Iclass_xt_iclass_rsr_lend_args,
   6045     1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
   6046   { 1, Iclass_xt_iclass_wsr_lend_args,
   6047     1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
   6048   { 1, Iclass_xt_iclass_xsr_lend_args,
   6049     1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
   6050   { 1, Iclass_xt_iclass_rsr_lcount_args,
   6051     1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
   6052   { 1, Iclass_xt_iclass_wsr_lcount_args,
   6053     2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
   6054   { 1, Iclass_xt_iclass_xsr_lcount_args,
   6055     2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
   6056   { 1, Iclass_xt_iclass_rsr_lbeg_args,
   6057     1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
   6058   { 1, Iclass_xt_iclass_wsr_lbeg_args,
   6059     1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
   6060   { 1, Iclass_xt_iclass_xsr_lbeg_args,
   6061     1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
   6062   { 1, Iclass_xt_iclass_rsr_sar_args,
   6063     1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
   6064   { 1, Iclass_xt_iclass_wsr_sar_args,
   6065     2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
   6066   { 1, Iclass_xt_iclass_xsr_sar_args,
   6067     1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
   6068   { 1, Iclass_xt_iclass_rsr_litbase_args,
   6069     2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
   6070   { 1, Iclass_xt_iclass_wsr_litbase_args,
   6071     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
   6072   { 1, Iclass_xt_iclass_xsr_litbase_args,
   6073     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
   6074   { 1, Iclass_xt_iclass_rsr_176_args,
   6075     2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
   6076   { 1, Iclass_xt_iclass_wsr_176_args,
   6077     2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
   6078   { 1, Iclass_xt_iclass_rsr_208_args,
   6079     2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
   6080   { 1, Iclass_xt_iclass_rsr_ps_args,
   6081     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
   6082   { 1, Iclass_xt_iclass_wsr_ps_args,
   6083     7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
   6084   { 1, Iclass_xt_iclass_xsr_ps_args,
   6085     7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
   6086   { 1, Iclass_xt_iclass_rsr_epc1_args,
   6087     3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
   6088   { 1, Iclass_xt_iclass_wsr_epc1_args,
   6089     3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
   6090   { 1, Iclass_xt_iclass_xsr_epc1_args,
   6091     3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
   6092   { 1, Iclass_xt_iclass_rsr_excsave1_args,
   6093     3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
   6094   { 1, Iclass_xt_iclass_wsr_excsave1_args,
   6095     3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
   6096   { 1, Iclass_xt_iclass_xsr_excsave1_args,
   6097     3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
   6098   { 1, Iclass_xt_iclass_rsr_epc2_args,
   6099     3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
   6100   { 1, Iclass_xt_iclass_wsr_epc2_args,
   6101     3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
   6102   { 1, Iclass_xt_iclass_xsr_epc2_args,
   6103     3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
   6104   { 1, Iclass_xt_iclass_rsr_excsave2_args,
   6105     3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
   6106   { 1, Iclass_xt_iclass_wsr_excsave2_args,
   6107     3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
   6108   { 1, Iclass_xt_iclass_xsr_excsave2_args,
   6109     3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
   6110   { 1, Iclass_xt_iclass_rsr_epc3_args,
   6111     3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
   6112   { 1, Iclass_xt_iclass_wsr_epc3_args,
   6113     3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
   6114   { 1, Iclass_xt_iclass_xsr_epc3_args,
   6115     3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
   6116   { 1, Iclass_xt_iclass_rsr_excsave3_args,
   6117     3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
   6118   { 1, Iclass_xt_iclass_wsr_excsave3_args,
   6119     3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
   6120   { 1, Iclass_xt_iclass_xsr_excsave3_args,
   6121     3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
   6122   { 1, Iclass_xt_iclass_rsr_epc4_args,
   6123     3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
   6124   { 1, Iclass_xt_iclass_wsr_epc4_args,
   6125     3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
   6126   { 1, Iclass_xt_iclass_xsr_epc4_args,
   6127     3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
   6128   { 1, Iclass_xt_iclass_rsr_excsave4_args,
   6129     3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
   6130   { 1, Iclass_xt_iclass_wsr_excsave4_args,
   6131     3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
   6132   { 1, Iclass_xt_iclass_xsr_excsave4_args,
   6133     3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
   6134   { 1, Iclass_xt_iclass_rsr_epc5_args,
   6135     3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
   6136   { 1, Iclass_xt_iclass_wsr_epc5_args,
   6137     3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
   6138   { 1, Iclass_xt_iclass_xsr_epc5_args,
   6139     3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
   6140   { 1, Iclass_xt_iclass_rsr_excsave5_args,
   6141     3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
   6142   { 1, Iclass_xt_iclass_wsr_excsave5_args,
   6143     3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
   6144   { 1, Iclass_xt_iclass_xsr_excsave5_args,
   6145     3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
   6146   { 1, Iclass_xt_iclass_rsr_epc6_args,
   6147     3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
   6148   { 1, Iclass_xt_iclass_wsr_epc6_args,
   6149     3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
   6150   { 1, Iclass_xt_iclass_xsr_epc6_args,
   6151     3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
   6152   { 1, Iclass_xt_iclass_rsr_excsave6_args,
   6153     3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
   6154   { 1, Iclass_xt_iclass_wsr_excsave6_args,
   6155     3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
   6156   { 1, Iclass_xt_iclass_xsr_excsave6_args,
   6157     3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
   6158   { 1, Iclass_xt_iclass_rsr_epc7_args,
   6159     3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
   6160   { 1, Iclass_xt_iclass_wsr_epc7_args,
   6161     3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
   6162   { 1, Iclass_xt_iclass_xsr_epc7_args,
   6163     3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
   6164   { 1, Iclass_xt_iclass_rsr_excsave7_args,
   6165     3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
   6166   { 1, Iclass_xt_iclass_wsr_excsave7_args,
   6167     3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
   6168   { 1, Iclass_xt_iclass_xsr_excsave7_args,
   6169     3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
   6170   { 1, Iclass_xt_iclass_rsr_eps2_args,
   6171     3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
   6172   { 1, Iclass_xt_iclass_wsr_eps2_args,
   6173     3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
   6174   { 1, Iclass_xt_iclass_xsr_eps2_args,
   6175     3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
   6176   { 1, Iclass_xt_iclass_rsr_eps3_args,
   6177     3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
   6178   { 1, Iclass_xt_iclass_wsr_eps3_args,
   6179     3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
   6180   { 1, Iclass_xt_iclass_xsr_eps3_args,
   6181     3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
   6182   { 1, Iclass_xt_iclass_rsr_eps4_args,
   6183     3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
   6184   { 1, Iclass_xt_iclass_wsr_eps4_args,
   6185     3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
   6186   { 1, Iclass_xt_iclass_xsr_eps4_args,
   6187     3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
   6188   { 1, Iclass_xt_iclass_rsr_eps5_args,
   6189     3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
   6190   { 1, Iclass_xt_iclass_wsr_eps5_args,
   6191     3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
   6192   { 1, Iclass_xt_iclass_xsr_eps5_args,
   6193     3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
   6194   { 1, Iclass_xt_iclass_rsr_eps6_args,
   6195     3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
   6196   { 1, Iclass_xt_iclass_wsr_eps6_args,
   6197     3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
   6198   { 1, Iclass_xt_iclass_xsr_eps6_args,
   6199     3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
   6200   { 1, Iclass_xt_iclass_rsr_eps7_args,
   6201     3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
   6202   { 1, Iclass_xt_iclass_wsr_eps7_args,
   6203     3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
   6204   { 1, Iclass_xt_iclass_xsr_eps7_args,
   6205     3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
   6206   { 1, Iclass_xt_iclass_rsr_excvaddr_args,
   6207     3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
   6208   { 1, Iclass_xt_iclass_wsr_excvaddr_args,
   6209     3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
   6210   { 1, Iclass_xt_iclass_xsr_excvaddr_args,
   6211     3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
   6212   { 1, Iclass_xt_iclass_rsr_depc_args,
   6213     3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
   6214   { 1, Iclass_xt_iclass_wsr_depc_args,
   6215     3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
   6216   { 1, Iclass_xt_iclass_xsr_depc_args,
   6217     3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
   6218   { 1, Iclass_xt_iclass_rsr_exccause_args,
   6219     4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
   6220   { 1, Iclass_xt_iclass_wsr_exccause_args,
   6221     3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
   6222   { 1, Iclass_xt_iclass_xsr_exccause_args,
   6223     3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
   6224   { 1, Iclass_xt_iclass_rsr_misc0_args,
   6225     3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
   6226   { 1, Iclass_xt_iclass_wsr_misc0_args,
   6227     3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
   6228   { 1, Iclass_xt_iclass_xsr_misc0_args,
   6229     3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
   6230   { 1, Iclass_xt_iclass_rsr_misc1_args,
   6231     3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
   6232   { 1, Iclass_xt_iclass_wsr_misc1_args,
   6233     3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
   6234   { 1, Iclass_xt_iclass_xsr_misc1_args,
   6235     3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
   6236   { 1, Iclass_xt_iclass_rsr_prid_args,
   6237     2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
   6238   { 1, Iclass_xt_iclass_rsr_vecbase_args,
   6239     3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
   6240   { 1, Iclass_xt_iclass_wsr_vecbase_args,
   6241     3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
   6242   { 1, Iclass_xt_iclass_xsr_vecbase_args,
   6243     3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
   6244   { 3, Iclass_xt_mul16_args,
   6245     0, 0, 0, 0 },
   6246   { 3, Iclass_xt_mul32_args,
   6247     0, 0, 0, 0 },
   6248   { 2, Iclass_xt_iclass_mac16_aa_args,
   6249     1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
   6250   { 2, Iclass_xt_iclass_mac16_ad_args,
   6251     1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
   6252   { 2, Iclass_xt_iclass_mac16_da_args,
   6253     1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
   6254   { 2, Iclass_xt_iclass_mac16_dd_args,
   6255     1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
   6256   { 2, Iclass_xt_iclass_mac16a_aa_args,
   6257     1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
   6258   { 2, Iclass_xt_iclass_mac16a_ad_args,
   6259     1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
   6260   { 2, Iclass_xt_iclass_mac16a_da_args,
   6261     1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
   6262   { 2, Iclass_xt_iclass_mac16a_dd_args,
   6263     1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
   6264   { 4, Iclass_xt_iclass_mac16al_da_args,
   6265     1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
   6266   { 4, Iclass_xt_iclass_mac16al_dd_args,
   6267     1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
   6268   { 2, Iclass_xt_iclass_mac16_l_args,
   6269     0, 0, 0, 0 },
   6270   { 2, Iclass_xt_iclass_rsr_m0_args,
   6271     0, 0, 0, 0 },
   6272   { 2, Iclass_xt_iclass_wsr_m0_args,
   6273     0, 0, 0, 0 },
   6274   { 2, Iclass_xt_iclass_xsr_m0_args,
   6275     0, 0, 0, 0 },
   6276   { 2, Iclass_xt_iclass_rsr_m1_args,
   6277     0, 0, 0, 0 },
   6278   { 2, Iclass_xt_iclass_wsr_m1_args,
   6279     0, 0, 0, 0 },
   6280   { 2, Iclass_xt_iclass_xsr_m1_args,
   6281     0, 0, 0, 0 },
   6282   { 2, Iclass_xt_iclass_rsr_m2_args,
   6283     0, 0, 0, 0 },
   6284   { 2, Iclass_xt_iclass_wsr_m2_args,
   6285     0, 0, 0, 0 },
   6286   { 2, Iclass_xt_iclass_xsr_m2_args,
   6287     0, 0, 0, 0 },
   6288   { 2, Iclass_xt_iclass_rsr_m3_args,
   6289     0, 0, 0, 0 },
   6290   { 2, Iclass_xt_iclass_wsr_m3_args,
   6291     0, 0, 0, 0 },
   6292   { 2, Iclass_xt_iclass_xsr_m3_args,
   6293     0, 0, 0, 0 },
   6294   { 1, Iclass_xt_iclass_rsr_acclo_args,
   6295     1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
   6296   { 1, Iclass_xt_iclass_wsr_acclo_args,
   6297     1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
   6298   { 1, Iclass_xt_iclass_xsr_acclo_args,
   6299     1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
   6300   { 1, Iclass_xt_iclass_rsr_acchi_args,
   6301     1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
   6302   { 1, Iclass_xt_iclass_wsr_acchi_args,
   6303     1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
   6304   { 1, Iclass_xt_iclass_xsr_acchi_args,
   6305     1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
   6306   { 1, Iclass_xt_iclass_rfi_args,
   6307     21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
   6308   { 1, Iclass_xt_iclass_wait_args,
   6309     3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
   6310   { 1, Iclass_xt_iclass_rsr_interrupt_args,
   6311     3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
   6312   { 1, Iclass_xt_iclass_wsr_intset_args,
   6313     4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
   6314   { 1, Iclass_xt_iclass_wsr_intclear_args,
   6315     4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
   6316   { 1, Iclass_xt_iclass_rsr_intenable_args,
   6317     3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
   6318   { 1, Iclass_xt_iclass_wsr_intenable_args,
   6319     3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
   6320   { 1, Iclass_xt_iclass_xsr_intenable_args,
   6321     3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
   6322   { 2, Iclass_xt_iclass_break_args,
   6323     2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
   6324   { 1, Iclass_xt_iclass_break_n_args,
   6325     2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
   6326   { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
   6327     3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
   6328   { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
   6329     4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
   6330   { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
   6331     4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
   6332   { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
   6333     3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
   6334   { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
   6335     4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
   6336   { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
   6337     4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
   6338   { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
   6339     3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
   6340   { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
   6341     4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
   6342   { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
   6343     4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
   6344   { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
   6345     3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
   6346   { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
   6347     4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
   6348   { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
   6349     4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
   6350   { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
   6351     3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
   6352   { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
   6353     3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
   6354   { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
   6355     3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
   6356   { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
   6357     3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
   6358   { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
   6359     3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
   6360   { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
   6361     3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
   6362   { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
   6363     3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
   6364   { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
   6365     3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
   6366   { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
   6367     3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
   6368   { 1, Iclass_xt_iclass_rsr_debugcause_args,
   6369     4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
   6370   { 1, Iclass_xt_iclass_wsr_debugcause_args,
   6371     4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
   6372   { 1, Iclass_xt_iclass_xsr_debugcause_args,
   6373     4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
   6374   { 1, Iclass_xt_iclass_rsr_icount_args,
   6375     3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
   6376   { 1, Iclass_xt_iclass_wsr_icount_args,
   6377     4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
   6378   { 1, Iclass_xt_iclass_xsr_icount_args,
   6379     4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
   6380   { 1, Iclass_xt_iclass_rsr_icountlevel_args,
   6381     3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
   6382   { 1, Iclass_xt_iclass_wsr_icountlevel_args,
   6383     3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
   6384   { 1, Iclass_xt_iclass_xsr_icountlevel_args,
   6385     3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
   6386   { 1, Iclass_xt_iclass_rsr_ddr_args,
   6387     3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
   6388   { 1, Iclass_xt_iclass_wsr_ddr_args,
   6389     4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
   6390   { 1, Iclass_xt_iclass_xsr_ddr_args,
   6391     4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
   6392   { 1, Iclass_xt_iclass_rfdo_args,
   6393     10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
   6394   { 0, 0 /* xt_iclass_rfdd */,
   6395     1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
   6396   { 1, Iclass_xt_iclass_wsr_mmid_args,
   6397     3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
   6398   { 1, Iclass_xt_iclass_rsr_ccount_args,
   6399     3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
   6400   { 1, Iclass_xt_iclass_wsr_ccount_args,
   6401     4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
   6402   { 1, Iclass_xt_iclass_xsr_ccount_args,
   6403     4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
   6404   { 1, Iclass_xt_iclass_rsr_ccompare0_args,
   6405     3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
   6406   { 1, Iclass_xt_iclass_wsr_ccompare0_args,
   6407     4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
   6408   { 1, Iclass_xt_iclass_xsr_ccompare0_args,
   6409     4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
   6410   { 1, Iclass_xt_iclass_rsr_ccompare1_args,
   6411     3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
   6412   { 1, Iclass_xt_iclass_wsr_ccompare1_args,
   6413     4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
   6414   { 1, Iclass_xt_iclass_xsr_ccompare1_args,
   6415     4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
   6416   { 1, Iclass_xt_iclass_rsr_ccompare2_args,
   6417     3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
   6418   { 1, Iclass_xt_iclass_wsr_ccompare2_args,
   6419     4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
   6420   { 1, Iclass_xt_iclass_xsr_ccompare2_args,
   6421     4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
   6422   { 2, Iclass_xt_iclass_icache_args,
   6423     0, 0, 0, 0 },
   6424   { 2, Iclass_xt_iclass_icache_lock_args,
   6425     2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
   6426   { 2, Iclass_xt_iclass_icache_inv_args,
   6427     2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
   6428   { 2, Iclass_xt_iclass_licx_args,
   6429     2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
   6430   { 2, Iclass_xt_iclass_sicx_args,
   6431     2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
   6432   { 2, Iclass_xt_iclass_dcache_args,
   6433     0, 0, 0, 0 },
   6434   { 2, Iclass_xt_iclass_dcache_ind_args,
   6435     2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
   6436   { 2, Iclass_xt_iclass_dcache_inv_args,
   6437     2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
   6438   { 2, Iclass_xt_iclass_dpf_args,
   6439     0, 0, 0, 0 },
   6440   { 2, Iclass_xt_iclass_dcache_lock_args,
   6441     2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
   6442   { 2, Iclass_xt_iclass_sdct_args,
   6443     2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
   6444   { 2, Iclass_xt_iclass_ldct_args,
   6445     2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
   6446   { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
   6447     4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
   6448   { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
   6449     4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
   6450   { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
   6451     5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
   6452   { 1, Iclass_xt_iclass_rsr_rasid_args,
   6453     5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
   6454   { 1, Iclass_xt_iclass_wsr_rasid_args,
   6455     6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
   6456   { 1, Iclass_xt_iclass_xsr_rasid_args,
   6457     6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
   6458   { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
   6459     5, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
   6460   { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
   6461     6, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
   6462   { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
   6463     6, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
   6464   { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
   6465     5, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
   6466   { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
   6467     6, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
   6468   { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
   6469     6, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
   6470   { 1, Iclass_xt_iclass_idtlb_args,
   6471     3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
   6472   { 2, Iclass_xt_iclass_rdtlb_args,
   6473     2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
   6474   { 2, Iclass_xt_iclass_wdtlb_args,
   6475     3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
   6476   { 1, Iclass_xt_iclass_iitlb_args,
   6477     2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
   6478   { 2, Iclass_xt_iclass_ritlb_args,
   6479     2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
   6480   { 2, Iclass_xt_iclass_witlb_args,
   6481     2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
   6482   { 0, 0 /* xt_iclass_ldpte */,
   6483     2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
   6484   { 0, 0 /* xt_iclass_hwwitlba */,
   6485     1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
   6486   { 0, 0 /* xt_iclass_hwwdtlba */,
   6487     1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
   6488   { 1, Iclass_xt_iclass_rsr_cpenable_args,
   6489     3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
   6490   { 1, Iclass_xt_iclass_wsr_cpenable_args,
   6491     3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
   6492   { 1, Iclass_xt_iclass_xsr_cpenable_args,
   6493     3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
   6494   { 3, Iclass_xt_iclass_clamp_args,
   6495     0, 0, 0, 0 },
   6496   { 3, Iclass_xt_iclass_minmax_args,
   6497     0, 0, 0, 0 },
   6498   { 2, Iclass_xt_iclass_nsa_args,
   6499     0, 0, 0, 0 },
   6500   { 3, Iclass_xt_iclass_sx_args,
   6501     0, 0, 0, 0 },
   6502   { 3, Iclass_xt_iclass_l32ai_args,
   6503     0, 0, 0, 0 },
   6504   { 3, Iclass_xt_iclass_s32ri_args,
   6505     0, 0, 0, 0 },
   6506   { 3, Iclass_xt_iclass_s32c1i_args,
   6507     3, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
   6508   { 1, Iclass_xt_iclass_rsr_scompare1_args,
   6509     1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
   6510   { 1, Iclass_xt_iclass_wsr_scompare1_args,
   6511     1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
   6512   { 1, Iclass_xt_iclass_xsr_scompare1_args,
   6513     1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
   6514   { 1, Iclass_xt_iclass_rsr_atomctl_args,
   6515     3, Iclass_xt_iclass_rsr_atomctl_stateArgs, 0, 0 },
   6516   { 1, Iclass_xt_iclass_wsr_atomctl_args,
   6517     4, Iclass_xt_iclass_wsr_atomctl_stateArgs, 0, 0 },
   6518   { 1, Iclass_xt_iclass_xsr_atomctl_args,
   6519     4, Iclass_xt_iclass_xsr_atomctl_stateArgs, 0, 0 },
   6520   { 3, Iclass_xt_iclass_div_args,
   6521     0, 0, 0, 0 },
   6522   { 0, 0 /* xt_iclass_rer */,
   6523     2, Iclass_xt_iclass_rer_stateArgs, 0, 0 },
   6524   { 0, 0 /* xt_iclass_wer */,
   6525     2, Iclass_xt_iclass_wer_stateArgs, 0, 0 },
   6526   { 1, Iclass_rur_expstate_args,
   6527     2, Iclass_rur_expstate_stateArgs, 0, 0 },
   6528   { 1, Iclass_wur_expstate_args,
   6529     2, Iclass_wur_expstate_stateArgs, 0, 0 },
   6530   { 1, Iclass_iclass_READ_IMPWIRE_args,
   6531     1, Iclass_iclass_READ_IMPWIRE_stateArgs, 1, Iclass_iclass_READ_IMPWIRE_intfArgs },
   6532   { 1, Iclass_iclass_SETB_EXPSTATE_args,
   6533     2, Iclass_iclass_SETB_EXPSTATE_stateArgs, 0, 0 },
   6534   { 1, Iclass_iclass_CLRB_EXPSTATE_args,
   6535     2, Iclass_iclass_CLRB_EXPSTATE_stateArgs, 0, 0 },
   6536   { 2, Iclass_iclass_WRMSK_EXPSTATE_args,
   6537     2, Iclass_iclass_WRMSK_EXPSTATE_stateArgs, 0, 0 }
   6538 };
   6539 
   6540 enum xtensa_iclass_id {
   6541   ICLASS_xt_iclass_excw,
   6542   ICLASS_xt_iclass_rfe,
   6543   ICLASS_xt_iclass_rfde,
   6544   ICLASS_xt_iclass_syscall,
   6545   ICLASS_xt_iclass_simcall,
   6546   ICLASS_xt_iclass_call12,
   6547   ICLASS_xt_iclass_call8,
   6548   ICLASS_xt_iclass_call4,
   6549   ICLASS_xt_iclass_callx12,
   6550   ICLASS_xt_iclass_callx8,
   6551   ICLASS_xt_iclass_callx4,
   6552   ICLASS_xt_iclass_entry,
   6553   ICLASS_xt_iclass_movsp,
   6554   ICLASS_xt_iclass_rotw,
   6555   ICLASS_xt_iclass_retw,
   6556   ICLASS_xt_iclass_rfwou,
   6557   ICLASS_xt_iclass_l32e,
   6558   ICLASS_xt_iclass_s32e,
   6559   ICLASS_xt_iclass_rsr_windowbase,
   6560   ICLASS_xt_iclass_wsr_windowbase,
   6561   ICLASS_xt_iclass_xsr_windowbase,
   6562   ICLASS_xt_iclass_rsr_windowstart,
   6563   ICLASS_xt_iclass_wsr_windowstart,
   6564   ICLASS_xt_iclass_xsr_windowstart,
   6565   ICLASS_xt_iclass_add_n,
   6566   ICLASS_xt_iclass_addi_n,
   6567   ICLASS_xt_iclass_bz6,
   6568   ICLASS_xt_iclass_ill_n,
   6569   ICLASS_xt_iclass_loadi4,
   6570   ICLASS_xt_iclass_mov_n,
   6571   ICLASS_xt_iclass_movi_n,
   6572   ICLASS_xt_iclass_nopn,
   6573   ICLASS_xt_iclass_retn,
   6574   ICLASS_xt_iclass_storei4,
   6575   ICLASS_rur_threadptr,
   6576   ICLASS_wur_threadptr,
   6577   ICLASS_xt_iclass_addi,
   6578   ICLASS_xt_iclass_addmi,
   6579   ICLASS_xt_iclass_addsub,
   6580   ICLASS_xt_iclass_bit,
   6581   ICLASS_xt_iclass_bsi8,
   6582   ICLASS_xt_iclass_bsi8b,
   6583   ICLASS_xt_iclass_bsi8u,
   6584   ICLASS_xt_iclass_bst8,
   6585   ICLASS_xt_iclass_bsz12,
   6586   ICLASS_xt_iclass_call0,
   6587   ICLASS_xt_iclass_callx0,
   6588   ICLASS_xt_iclass_exti,
   6589   ICLASS_xt_iclass_ill,
   6590   ICLASS_xt_iclass_jump,
   6591   ICLASS_xt_iclass_jumpx,
   6592   ICLASS_xt_iclass_l16ui,
   6593   ICLASS_xt_iclass_l16si,
   6594   ICLASS_xt_iclass_l32i,
   6595   ICLASS_xt_iclass_l32r,
   6596   ICLASS_xt_iclass_l8i,
   6597   ICLASS_xt_iclass_loop,
   6598   ICLASS_xt_iclass_loopz,
   6599   ICLASS_xt_iclass_movi,
   6600   ICLASS_xt_iclass_movz,
   6601   ICLASS_xt_iclass_neg,
   6602   ICLASS_xt_iclass_nop,
   6603   ICLASS_xt_iclass_return,
   6604   ICLASS_xt_iclass_s16i,
   6605   ICLASS_xt_iclass_s32i,
   6606   ICLASS_xt_iclass_s8i,
   6607   ICLASS_xt_iclass_sar,
   6608   ICLASS_xt_iclass_sari,
   6609   ICLASS_xt_iclass_shifts,
   6610   ICLASS_xt_iclass_shiftst,
   6611   ICLASS_xt_iclass_shiftt,
   6612   ICLASS_xt_iclass_slli,
   6613   ICLASS_xt_iclass_srai,
   6614   ICLASS_xt_iclass_srli,
   6615   ICLASS_xt_iclass_memw,
   6616   ICLASS_xt_iclass_extw,
   6617   ICLASS_xt_iclass_isync,
   6618   ICLASS_xt_iclass_sync,
   6619   ICLASS_xt_iclass_rsil,
   6620   ICLASS_xt_iclass_rsr_lend,
   6621   ICLASS_xt_iclass_wsr_lend,
   6622   ICLASS_xt_iclass_xsr_lend,
   6623   ICLASS_xt_iclass_rsr_lcount,
   6624   ICLASS_xt_iclass_wsr_lcount,
   6625   ICLASS_xt_iclass_xsr_lcount,
   6626   ICLASS_xt_iclass_rsr_lbeg,
   6627   ICLASS_xt_iclass_wsr_lbeg,
   6628   ICLASS_xt_iclass_xsr_lbeg,
   6629   ICLASS_xt_iclass_rsr_sar,
   6630   ICLASS_xt_iclass_wsr_sar,
   6631   ICLASS_xt_iclass_xsr_sar,
   6632   ICLASS_xt_iclass_rsr_litbase,
   6633   ICLASS_xt_iclass_wsr_litbase,
   6634   ICLASS_xt_iclass_xsr_litbase,
   6635   ICLASS_xt_iclass_rsr_176,
   6636   ICLASS_xt_iclass_wsr_176,
   6637   ICLASS_xt_iclass_rsr_208,
   6638   ICLASS_xt_iclass_rsr_ps,
   6639   ICLASS_xt_iclass_wsr_ps,
   6640   ICLASS_xt_iclass_xsr_ps,
   6641   ICLASS_xt_iclass_rsr_epc1,
   6642   ICLASS_xt_iclass_wsr_epc1,
   6643   ICLASS_xt_iclass_xsr_epc1,
   6644   ICLASS_xt_iclass_rsr_excsave1,
   6645   ICLASS_xt_iclass_wsr_excsave1,
   6646   ICLASS_xt_iclass_xsr_excsave1,
   6647   ICLASS_xt_iclass_rsr_epc2,
   6648   ICLASS_xt_iclass_wsr_epc2,
   6649   ICLASS_xt_iclass_xsr_epc2,
   6650   ICLASS_xt_iclass_rsr_excsave2,
   6651   ICLASS_xt_iclass_wsr_excsave2,
   6652   ICLASS_xt_iclass_xsr_excsave2,
   6653   ICLASS_xt_iclass_rsr_epc3,
   6654   ICLASS_xt_iclass_wsr_epc3,
   6655   ICLASS_xt_iclass_xsr_epc3,
   6656   ICLASS_xt_iclass_rsr_excsave3,
   6657   ICLASS_xt_iclass_wsr_excsave3,
   6658   ICLASS_xt_iclass_xsr_excsave3,
   6659   ICLASS_xt_iclass_rsr_epc4,
   6660   ICLASS_xt_iclass_wsr_epc4,
   6661   ICLASS_xt_iclass_xsr_epc4,
   6662   ICLASS_xt_iclass_rsr_excsave4,
   6663   ICLASS_xt_iclass_wsr_excsave4,
   6664   ICLASS_xt_iclass_xsr_excsave4,
   6665   ICLASS_xt_iclass_rsr_epc5,
   6666   ICLASS_xt_iclass_wsr_epc5,
   6667   ICLASS_xt_iclass_xsr_epc5,
   6668   ICLASS_xt_iclass_rsr_excsave5,
   6669   ICLASS_xt_iclass_wsr_excsave5,
   6670   ICLASS_xt_iclass_xsr_excsave5,
   6671   ICLASS_xt_iclass_rsr_epc6,
   6672   ICLASS_xt_iclass_wsr_epc6,
   6673   ICLASS_xt_iclass_xsr_epc6,
   6674   ICLASS_xt_iclass_rsr_excsave6,
   6675   ICLASS_xt_iclass_wsr_excsave6,
   6676   ICLASS_xt_iclass_xsr_excsave6,
   6677   ICLASS_xt_iclass_rsr_epc7,
   6678   ICLASS_xt_iclass_wsr_epc7,
   6679   ICLASS_xt_iclass_xsr_epc7,
   6680   ICLASS_xt_iclass_rsr_excsave7,
   6681   ICLASS_xt_iclass_wsr_excsave7,
   6682   ICLASS_xt_iclass_xsr_excsave7,
   6683   ICLASS_xt_iclass_rsr_eps2,
   6684   ICLASS_xt_iclass_wsr_eps2,
   6685   ICLASS_xt_iclass_xsr_eps2,
   6686   ICLASS_xt_iclass_rsr_eps3,
   6687   ICLASS_xt_iclass_wsr_eps3,
   6688   ICLASS_xt_iclass_xsr_eps3,
   6689   ICLASS_xt_iclass_rsr_eps4,
   6690   ICLASS_xt_iclass_wsr_eps4,
   6691   ICLASS_xt_iclass_xsr_eps4,
   6692   ICLASS_xt_iclass_rsr_eps5,
   6693   ICLASS_xt_iclass_wsr_eps5,
   6694   ICLASS_xt_iclass_xsr_eps5,
   6695   ICLASS_xt_iclass_rsr_eps6,
   6696   ICLASS_xt_iclass_wsr_eps6,
   6697   ICLASS_xt_iclass_xsr_eps6,
   6698   ICLASS_xt_iclass_rsr_eps7,
   6699   ICLASS_xt_iclass_wsr_eps7,
   6700   ICLASS_xt_iclass_xsr_eps7,
   6701   ICLASS_xt_iclass_rsr_excvaddr,
   6702   ICLASS_xt_iclass_wsr_excvaddr,
   6703   ICLASS_xt_iclass_xsr_excvaddr,
   6704   ICLASS_xt_iclass_rsr_depc,
   6705   ICLASS_xt_iclass_wsr_depc,
   6706   ICLASS_xt_iclass_xsr_depc,
   6707   ICLASS_xt_iclass_rsr_exccause,
   6708   ICLASS_xt_iclass_wsr_exccause,
   6709   ICLASS_xt_iclass_xsr_exccause,
   6710   ICLASS_xt_iclass_rsr_misc0,
   6711   ICLASS_xt_iclass_wsr_misc0,
   6712   ICLASS_xt_iclass_xsr_misc0,
   6713   ICLASS_xt_iclass_rsr_misc1,
   6714   ICLASS_xt_iclass_wsr_misc1,
   6715   ICLASS_xt_iclass_xsr_misc1,
   6716   ICLASS_xt_iclass_rsr_prid,
   6717   ICLASS_xt_iclass_rsr_vecbase,
   6718   ICLASS_xt_iclass_wsr_vecbase,
   6719   ICLASS_xt_iclass_xsr_vecbase,
   6720   ICLASS_xt_mul16,
   6721   ICLASS_xt_mul32,
   6722   ICLASS_xt_iclass_mac16_aa,
   6723   ICLASS_xt_iclass_mac16_ad,
   6724   ICLASS_xt_iclass_mac16_da,
   6725   ICLASS_xt_iclass_mac16_dd,
   6726   ICLASS_xt_iclass_mac16a_aa,
   6727   ICLASS_xt_iclass_mac16a_ad,
   6728   ICLASS_xt_iclass_mac16a_da,
   6729   ICLASS_xt_iclass_mac16a_dd,
   6730   ICLASS_xt_iclass_mac16al_da,
   6731   ICLASS_xt_iclass_mac16al_dd,
   6732   ICLASS_xt_iclass_mac16_l,
   6733   ICLASS_xt_iclass_rsr_m0,
   6734   ICLASS_xt_iclass_wsr_m0,
   6735   ICLASS_xt_iclass_xsr_m0,
   6736   ICLASS_xt_iclass_rsr_m1,
   6737   ICLASS_xt_iclass_wsr_m1,
   6738   ICLASS_xt_iclass_xsr_m1,
   6739   ICLASS_xt_iclass_rsr_m2,
   6740   ICLASS_xt_iclass_wsr_m2,
   6741   ICLASS_xt_iclass_xsr_m2,
   6742   ICLASS_xt_iclass_rsr_m3,
   6743   ICLASS_xt_iclass_wsr_m3,
   6744   ICLASS_xt_iclass_xsr_m3,
   6745   ICLASS_xt_iclass_rsr_acclo,
   6746   ICLASS_xt_iclass_wsr_acclo,
   6747   ICLASS_xt_iclass_xsr_acclo,
   6748   ICLASS_xt_iclass_rsr_acchi,
   6749   ICLASS_xt_iclass_wsr_acchi,
   6750   ICLASS_xt_iclass_xsr_acchi,
   6751   ICLASS_xt_iclass_rfi,
   6752   ICLASS_xt_iclass_wait,
   6753   ICLASS_xt_iclass_rsr_interrupt,
   6754   ICLASS_xt_iclass_wsr_intset,
   6755   ICLASS_xt_iclass_wsr_intclear,
   6756   ICLASS_xt_iclass_rsr_intenable,
   6757   ICLASS_xt_iclass_wsr_intenable,
   6758   ICLASS_xt_iclass_xsr_intenable,
   6759   ICLASS_xt_iclass_break,
   6760   ICLASS_xt_iclass_break_n,
   6761   ICLASS_xt_iclass_rsr_dbreaka0,
   6762   ICLASS_xt_iclass_wsr_dbreaka0,
   6763   ICLASS_xt_iclass_xsr_dbreaka0,
   6764   ICLASS_xt_iclass_rsr_dbreakc0,
   6765   ICLASS_xt_iclass_wsr_dbreakc0,
   6766   ICLASS_xt_iclass_xsr_dbreakc0,
   6767   ICLASS_xt_iclass_rsr_dbreaka1,
   6768   ICLASS_xt_iclass_wsr_dbreaka1,
   6769   ICLASS_xt_iclass_xsr_dbreaka1,
   6770   ICLASS_xt_iclass_rsr_dbreakc1,
   6771   ICLASS_xt_iclass_wsr_dbreakc1,
   6772   ICLASS_xt_iclass_xsr_dbreakc1,
   6773   ICLASS_xt_iclass_rsr_ibreaka0,
   6774   ICLASS_xt_iclass_wsr_ibreaka0,
   6775   ICLASS_xt_iclass_xsr_ibreaka0,
   6776   ICLASS_xt_iclass_rsr_ibreaka1,
   6777   ICLASS_xt_iclass_wsr_ibreaka1,
   6778   ICLASS_xt_iclass_xsr_ibreaka1,
   6779   ICLASS_xt_iclass_rsr_ibreakenable,
   6780   ICLASS_xt_iclass_wsr_ibreakenable,
   6781   ICLASS_xt_iclass_xsr_ibreakenable,
   6782   ICLASS_xt_iclass_rsr_debugcause,
   6783   ICLASS_xt_iclass_wsr_debugcause,
   6784   ICLASS_xt_iclass_xsr_debugcause,
   6785   ICLASS_xt_iclass_rsr_icount,
   6786   ICLASS_xt_iclass_wsr_icount,
   6787   ICLASS_xt_iclass_xsr_icount,
   6788   ICLASS_xt_iclass_rsr_icountlevel,
   6789   ICLASS_xt_iclass_wsr_icountlevel,
   6790   ICLASS_xt_iclass_xsr_icountlevel,
   6791   ICLASS_xt_iclass_rsr_ddr,
   6792   ICLASS_xt_iclass_wsr_ddr,
   6793   ICLASS_xt_iclass_xsr_ddr,
   6794   ICLASS_xt_iclass_rfdo,
   6795   ICLASS_xt_iclass_rfdd,
   6796   ICLASS_xt_iclass_wsr_mmid,
   6797   ICLASS_xt_iclass_rsr_ccount,
   6798   ICLASS_xt_iclass_wsr_ccount,
   6799   ICLASS_xt_iclass_xsr_ccount,
   6800   ICLASS_xt_iclass_rsr_ccompare0,
   6801   ICLASS_xt_iclass_wsr_ccompare0,
   6802   ICLASS_xt_iclass_xsr_ccompare0,
   6803   ICLASS_xt_iclass_rsr_ccompare1,
   6804   ICLASS_xt_iclass_wsr_ccompare1,
   6805   ICLASS_xt_iclass_xsr_ccompare1,
   6806   ICLASS_xt_iclass_rsr_ccompare2,
   6807   ICLASS_xt_iclass_wsr_ccompare2,
   6808   ICLASS_xt_iclass_xsr_ccompare2,
   6809   ICLASS_xt_iclass_icache,
   6810   ICLASS_xt_iclass_icache_lock,
   6811   ICLASS_xt_iclass_icache_inv,
   6812   ICLASS_xt_iclass_licx,
   6813   ICLASS_xt_iclass_sicx,
   6814   ICLASS_xt_iclass_dcache,
   6815   ICLASS_xt_iclass_dcache_ind,
   6816   ICLASS_xt_iclass_dcache_inv,
   6817   ICLASS_xt_iclass_dpf,
   6818   ICLASS_xt_iclass_dcache_lock,
   6819   ICLASS_xt_iclass_sdct,
   6820   ICLASS_xt_iclass_ldct,
   6821   ICLASS_xt_iclass_wsr_ptevaddr,
   6822   ICLASS_xt_iclass_rsr_ptevaddr,
   6823   ICLASS_xt_iclass_xsr_ptevaddr,
   6824   ICLASS_xt_iclass_rsr_rasid,
   6825   ICLASS_xt_iclass_wsr_rasid,
   6826   ICLASS_xt_iclass_xsr_rasid,
   6827   ICLASS_xt_iclass_rsr_itlbcfg,
   6828   ICLASS_xt_iclass_wsr_itlbcfg,
   6829   ICLASS_xt_iclass_xsr_itlbcfg,
   6830   ICLASS_xt_iclass_rsr_dtlbcfg,
   6831   ICLASS_xt_iclass_wsr_dtlbcfg,
   6832   ICLASS_xt_iclass_xsr_dtlbcfg,
   6833   ICLASS_xt_iclass_idtlb,
   6834   ICLASS_xt_iclass_rdtlb,
   6835   ICLASS_xt_iclass_wdtlb,
   6836   ICLASS_xt_iclass_iitlb,
   6837   ICLASS_xt_iclass_ritlb,
   6838   ICLASS_xt_iclass_witlb,
   6839   ICLASS_xt_iclass_ldpte,
   6840   ICLASS_xt_iclass_hwwitlba,
   6841   ICLASS_xt_iclass_hwwdtlba,
   6842   ICLASS_xt_iclass_rsr_cpenable,
   6843   ICLASS_xt_iclass_wsr_cpenable,
   6844   ICLASS_xt_iclass_xsr_cpenable,
   6845   ICLASS_xt_iclass_clamp,
   6846   ICLASS_xt_iclass_minmax,
   6847   ICLASS_xt_iclass_nsa,
   6848   ICLASS_xt_iclass_sx,
   6849   ICLASS_xt_iclass_l32ai,
   6850   ICLASS_xt_iclass_s32ri,
   6851   ICLASS_xt_iclass_s32c1i,
   6852   ICLASS_xt_iclass_rsr_scompare1,
   6853   ICLASS_xt_iclass_wsr_scompare1,
   6854   ICLASS_xt_iclass_xsr_scompare1,
   6855   ICLASS_xt_iclass_rsr_atomctl,
   6856   ICLASS_xt_iclass_wsr_atomctl,
   6857   ICLASS_xt_iclass_xsr_atomctl,
   6858   ICLASS_xt_iclass_div,
   6859   ICLASS_xt_iclass_rer,
   6860   ICLASS_xt_iclass_wer,
   6861   ICLASS_rur_expstate,
   6862   ICLASS_wur_expstate,
   6863   ICLASS_iclass_READ_IMPWIRE,
   6864   ICLASS_iclass_SETB_EXPSTATE,
   6865   ICLASS_iclass_CLRB_EXPSTATE,
   6866   ICLASS_iclass_WRMSK_EXPSTATE
   6867 };
   6868 
   6869 
   6870 /*  Opcode encodings.  */
   6871 
   6872 static void
   6873 Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6874 {
   6875   slotbuf[0] = 0x2080;
   6876 }
   6877 
   6878 static void
   6879 Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6880 {
   6881   slotbuf[0] = 0x3000;
   6882 }
   6883 
   6884 static void
   6885 Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6886 {
   6887   slotbuf[0] = 0x3200;
   6888 }
   6889 
   6890 static void
   6891 Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6892 {
   6893   slotbuf[0] = 0x5000;
   6894 }
   6895 
   6896 static void
   6897 Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6898 {
   6899   slotbuf[0] = 0x5100;
   6900 }
   6901 
   6902 static void
   6903 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6904 {
   6905   slotbuf[0] = 0x35;
   6906 }
   6907 
   6908 static void
   6909 Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6910 {
   6911   slotbuf[0] = 0x25;
   6912 }
   6913 
   6914 static void
   6915 Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6916 {
   6917   slotbuf[0] = 0x15;
   6918 }
   6919 
   6920 static void
   6921 Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6922 {
   6923   slotbuf[0] = 0xf0;
   6924 }
   6925 
   6926 static void
   6927 Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6928 {
   6929   slotbuf[0] = 0xe0;
   6930 }
   6931 
   6932 static void
   6933 Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6934 {
   6935   slotbuf[0] = 0xd0;
   6936 }
   6937 
   6938 static void
   6939 Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6940 {
   6941   slotbuf[0] = 0x36;
   6942 }
   6943 
   6944 static void
   6945 Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6946 {
   6947   slotbuf[0] = 0x1000;
   6948 }
   6949 
   6950 static void
   6951 Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6952 {
   6953   slotbuf[0] = 0x408000;
   6954 }
   6955 
   6956 static void
   6957 Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6958 {
   6959   slotbuf[0] = 0x90;
   6960 }
   6961 
   6962 static void
   6963 Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   6964 {
   6965   slotbuf[0] = 0xf01d;
   6966 }
   6967 
   6968 static void
   6969 Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6970 {
   6971   slotbuf[0] = 0x3400;
   6972 }
   6973 
   6974 static void
   6975 Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6976 {
   6977   slotbuf[0] = 0x3500;
   6978 }
   6979 
   6980 static void
   6981 Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6982 {
   6983   slotbuf[0] = 0x90000;
   6984 }
   6985 
   6986 static void
   6987 Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6988 {
   6989   slotbuf[0] = 0x490000;
   6990 }
   6991 
   6992 static void
   6993 Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   6994 {
   6995   slotbuf[0] = 0x34800;
   6996 }
   6997 
   6998 static void
   6999 Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7000 {
   7001   slotbuf[0] = 0x134800;
   7002 }
   7003 
   7004 static void
   7005 Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7006 {
   7007   slotbuf[0] = 0x614800;
   7008 }
   7009 
   7010 static void
   7011 Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7012 {
   7013   slotbuf[0] = 0x34900;
   7014 }
   7015 
   7016 static void
   7017 Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7018 {
   7019   slotbuf[0] = 0x134900;
   7020 }
   7021 
   7022 static void
   7023 Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7024 {
   7025   slotbuf[0] = 0x614900;
   7026 }
   7027 
   7028 static void
   7029 Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   7030 {
   7031   slotbuf[0] = 0xa;
   7032 }
   7033 
   7034 static void
   7035 Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   7036 {
   7037   slotbuf[0] = 0xb;
   7038 }
   7039 
   7040 static void
   7041 Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7042 {
   7043   slotbuf[0] = 0x8c;
   7044 }
   7045 
   7046 static void
   7047 Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7048 {
   7049   slotbuf[0] = 0xcc;
   7050 }
   7051 
   7052 static void
   7053 Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7054 {
   7055   slotbuf[0] = 0xf06d;
   7056 }
   7057 
   7058 static void
   7059 Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   7060 {
   7061   slotbuf[0] = 0x8;
   7062 }
   7063 
   7064 static void
   7065 Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7066 {
   7067   slotbuf[0] = 0xd;
   7068 }
   7069 
   7070 static void
   7071 Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7072 {
   7073   slotbuf[0] = 0xc;
   7074 }
   7075 
   7076 static void
   7077 Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7078 {
   7079   slotbuf[0] = 0xf03d;
   7080 }
   7081 
   7082 static void
   7083 Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   7084 {
   7085   slotbuf[0] = 0xf00d;
   7086 }
   7087 
   7088 static void
   7089 Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
   7090 {
   7091   slotbuf[0] = 0x9;
   7092 }
   7093 
   7094 static void
   7095 Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7096 {
   7097   slotbuf[0] = 0xe30e70;
   7098 }
   7099 
   7100 static void
   7101 Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7102 {
   7103   slotbuf[0] = 0xf3e700;
   7104 }
   7105 
   7106 static void
   7107 Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7108 {
   7109   slotbuf[0] = 0xc002;
   7110 }
   7111 
   7112 static void
   7113 Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7114 {
   7115   slotbuf[0] = 0xd002;
   7116 }
   7117 
   7118 static void
   7119 Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7120 {
   7121   slotbuf[0] = 0x800000;
   7122 }
   7123 
   7124 static void
   7125 Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7126 {
   7127   slotbuf[0] = 0xc00000;
   7128 }
   7129 
   7130 static void
   7131 Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7132 {
   7133   slotbuf[0] = 0x900000;
   7134 }
   7135 
   7136 static void
   7137 Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7138 {
   7139   slotbuf[0] = 0xa00000;
   7140 }
   7141 
   7142 static void
   7143 Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7144 {
   7145   slotbuf[0] = 0xb00000;
   7146 }
   7147 
   7148 static void
   7149 Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7150 {
   7151   slotbuf[0] = 0xd00000;
   7152 }
   7153 
   7154 static void
   7155 Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7156 {
   7157   slotbuf[0] = 0xe00000;
   7158 }
   7159 
   7160 static void
   7161 Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7162 {
   7163   slotbuf[0] = 0xf00000;
   7164 }
   7165 
   7166 static void
   7167 Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7168 {
   7169   slotbuf[0] = 0x100000;
   7170 }
   7171 
   7172 static void
   7173 Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7174 {
   7175   slotbuf[0] = 0x200000;
   7176 }
   7177 
   7178 static void
   7179 Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7180 {
   7181   slotbuf[0] = 0x300000;
   7182 }
   7183 
   7184 static void
   7185 Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7186 {
   7187   slotbuf[0] = 0x26;
   7188 }
   7189 
   7190 static void
   7191 Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7192 {
   7193   slotbuf[0] = 0x66;
   7194 }
   7195 
   7196 static void
   7197 Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7198 {
   7199   slotbuf[0] = 0xe6;
   7200 }
   7201 
   7202 static void
   7203 Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7204 {
   7205   slotbuf[0] = 0xa6;
   7206 }
   7207 
   7208 static void
   7209 Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7210 {
   7211   slotbuf[0] = 0x6007;
   7212 }
   7213 
   7214 static void
   7215 Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7216 {
   7217   slotbuf[0] = 0xe007;
   7218 }
   7219 
   7220 static void
   7221 Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7222 {
   7223   slotbuf[0] = 0xf6;
   7224 }
   7225 
   7226 static void
   7227 Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7228 {
   7229   slotbuf[0] = 0xb6;
   7230 }
   7231 
   7232 static void
   7233 Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7234 {
   7235   slotbuf[0] = 0x1007;
   7236 }
   7237 
   7238 static void
   7239 Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7240 {
   7241   slotbuf[0] = 0x9007;
   7242 }
   7243 
   7244 static void
   7245 Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7246 {
   7247   slotbuf[0] = 0xa007;
   7248 }
   7249 
   7250 static void
   7251 Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7252 {
   7253   slotbuf[0] = 0x2007;
   7254 }
   7255 
   7256 static void
   7257 Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7258 {
   7259   slotbuf[0] = 0xb007;
   7260 }
   7261 
   7262 static void
   7263 Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7264 {
   7265   slotbuf[0] = 0x3007;
   7266 }
   7267 
   7268 static void
   7269 Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7270 {
   7271   slotbuf[0] = 0x8007;
   7272 }
   7273 
   7274 static void
   7275 Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7276 {
   7277   slotbuf[0] = 0x7;
   7278 }
   7279 
   7280 static void
   7281 Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7282 {
   7283   slotbuf[0] = 0x4007;
   7284 }
   7285 
   7286 static void
   7287 Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7288 {
   7289   slotbuf[0] = 0xc007;
   7290 }
   7291 
   7292 static void
   7293 Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7294 {
   7295   slotbuf[0] = 0x5007;
   7296 }
   7297 
   7298 static void
   7299 Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7300 {
   7301   slotbuf[0] = 0xd007;
   7302 }
   7303 
   7304 static void
   7305 Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7306 {
   7307   slotbuf[0] = 0x16;
   7308 }
   7309 
   7310 static void
   7311 Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7312 {
   7313   slotbuf[0] = 0x56;
   7314 }
   7315 
   7316 static void
   7317 Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7318 {
   7319   slotbuf[0] = 0xd6;
   7320 }
   7321 
   7322 static void
   7323 Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7324 {
   7325   slotbuf[0] = 0x96;
   7326 }
   7327 
   7328 static void
   7329 Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7330 {
   7331   slotbuf[0] = 0x5;
   7332 }
   7333 
   7334 static void
   7335 Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7336 {
   7337   slotbuf[0] = 0xc0;
   7338 }
   7339 
   7340 static void
   7341 Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7342 {
   7343   slotbuf[0] = 0x40000;
   7344 }
   7345 
   7346 static void
   7347 Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7348 {
   7349   slotbuf[0] = 0;
   7350 }
   7351 
   7352 static void
   7353 Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7354 {
   7355   slotbuf[0] = 0x6;
   7356 }
   7357 
   7358 static void
   7359 Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7360 {
   7361   slotbuf[0] = 0xa0;
   7362 }
   7363 
   7364 static void
   7365 Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7366 {
   7367   slotbuf[0] = 0x1002;
   7368 }
   7369 
   7370 static void
   7371 Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7372 {
   7373   slotbuf[0] = 0x9002;
   7374 }
   7375 
   7376 static void
   7377 Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7378 {
   7379   slotbuf[0] = 0x2002;
   7380 }
   7381 
   7382 static void
   7383 Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7384 {
   7385   slotbuf[0] = 0x1;
   7386 }
   7387 
   7388 static void
   7389 Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7390 {
   7391   slotbuf[0] = 0x2;
   7392 }
   7393 
   7394 static void
   7395 Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7396 {
   7397   slotbuf[0] = 0x8076;
   7398 }
   7399 
   7400 static void
   7401 Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7402 {
   7403   slotbuf[0] = 0x9076;
   7404 }
   7405 
   7406 static void
   7407 Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7408 {
   7409   slotbuf[0] = 0xa076;
   7410 }
   7411 
   7412 static void
   7413 Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7414 {
   7415   slotbuf[0] = 0xa002;
   7416 }
   7417 
   7418 static void
   7419 Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7420 {
   7421   slotbuf[0] = 0x830000;
   7422 }
   7423 
   7424 static void
   7425 Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7426 {
   7427   slotbuf[0] = 0x930000;
   7428 }
   7429 
   7430 static void
   7431 Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7432 {
   7433   slotbuf[0] = 0xa30000;
   7434 }
   7435 
   7436 static void
   7437 Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7438 {
   7439   slotbuf[0] = 0xb30000;
   7440 }
   7441 
   7442 static void
   7443 Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7444 {
   7445   slotbuf[0] = 0x600000;
   7446 }
   7447 
   7448 static void
   7449 Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7450 {
   7451   slotbuf[0] = 0x600100;
   7452 }
   7453 
   7454 static void
   7455 Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7456 {
   7457   slotbuf[0] = 0x20f0;
   7458 }
   7459 
   7460 static void
   7461 Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7462 {
   7463   slotbuf[0] = 0x80;
   7464 }
   7465 
   7466 static void
   7467 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7468 {
   7469   slotbuf[0] = 0x5002;
   7470 }
   7471 
   7472 static void
   7473 Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7474 {
   7475   slotbuf[0] = 0x6002;
   7476 }
   7477 
   7478 static void
   7479 Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7480 {
   7481   slotbuf[0] = 0x4002;
   7482 }
   7483 
   7484 static void
   7485 Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7486 {
   7487   slotbuf[0] = 0x400000;
   7488 }
   7489 
   7490 static void
   7491 Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7492 {
   7493   slotbuf[0] = 0x401000;
   7494 }
   7495 
   7496 static void
   7497 Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7498 {
   7499   slotbuf[0] = 0x402000;
   7500 }
   7501 
   7502 static void
   7503 Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7504 {
   7505   slotbuf[0] = 0x403000;
   7506 }
   7507 
   7508 static void
   7509 Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7510 {
   7511   slotbuf[0] = 0x404000;
   7512 }
   7513 
   7514 static void
   7515 Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7516 {
   7517   slotbuf[0] = 0xa10000;
   7518 }
   7519 
   7520 static void
   7521 Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7522 {
   7523   slotbuf[0] = 0x810000;
   7524 }
   7525 
   7526 static void
   7527 Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7528 {
   7529   slotbuf[0] = 0x910000;
   7530 }
   7531 
   7532 static void
   7533 Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7534 {
   7535   slotbuf[0] = 0xb10000;
   7536 }
   7537 
   7538 static void
   7539 Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7540 {
   7541   slotbuf[0] = 0x10000;
   7542 }
   7543 
   7544 static void
   7545 Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7546 {
   7547   slotbuf[0] = 0x210000;
   7548 }
   7549 
   7550 static void
   7551 Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7552 {
   7553   slotbuf[0] = 0x410000;
   7554 }
   7555 
   7556 static void
   7557 Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7558 {
   7559   slotbuf[0] = 0x20c0;
   7560 }
   7561 
   7562 static void
   7563 Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7564 {
   7565   slotbuf[0] = 0x20d0;
   7566 }
   7567 
   7568 static void
   7569 Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7570 {
   7571   slotbuf[0] = 0x2000;
   7572 }
   7573 
   7574 static void
   7575 Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7576 {
   7577   slotbuf[0] = 0x2010;
   7578 }
   7579 
   7580 static void
   7581 Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7582 {
   7583   slotbuf[0] = 0x2020;
   7584 }
   7585 
   7586 static void
   7587 Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7588 {
   7589   slotbuf[0] = 0x2030;
   7590 }
   7591 
   7592 static void
   7593 Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7594 {
   7595   slotbuf[0] = 0x6000;
   7596 }
   7597 
   7598 static void
   7599 Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7600 {
   7601   slotbuf[0] = 0x30100;
   7602 }
   7603 
   7604 static void
   7605 Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7606 {
   7607   slotbuf[0] = 0x130100;
   7608 }
   7609 
   7610 static void
   7611 Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7612 {
   7613   slotbuf[0] = 0x610100;
   7614 }
   7615 
   7616 static void
   7617 Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7618 {
   7619   slotbuf[0] = 0x30200;
   7620 }
   7621 
   7622 static void
   7623 Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7624 {
   7625   slotbuf[0] = 0x130200;
   7626 }
   7627 
   7628 static void
   7629 Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7630 {
   7631   slotbuf[0] = 0x610200;
   7632 }
   7633 
   7634 static void
   7635 Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7636 {
   7637   slotbuf[0] = 0x30000;
   7638 }
   7639 
   7640 static void
   7641 Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7642 {
   7643   slotbuf[0] = 0x130000;
   7644 }
   7645 
   7646 static void
   7647 Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7648 {
   7649   slotbuf[0] = 0x610000;
   7650 }
   7651 
   7652 static void
   7653 Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7654 {
   7655   slotbuf[0] = 0x30300;
   7656 }
   7657 
   7658 static void
   7659 Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7660 {
   7661   slotbuf[0] = 0x130300;
   7662 }
   7663 
   7664 static void
   7665 Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7666 {
   7667   slotbuf[0] = 0x610300;
   7668 }
   7669 
   7670 static void
   7671 Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7672 {
   7673   slotbuf[0] = 0x30500;
   7674 }
   7675 
   7676 static void
   7677 Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7678 {
   7679   slotbuf[0] = 0x130500;
   7680 }
   7681 
   7682 static void
   7683 Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7684 {
   7685   slotbuf[0] = 0x610500;
   7686 }
   7687 
   7688 static void
   7689 Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7690 {
   7691   slotbuf[0] = 0x3b000;
   7692 }
   7693 
   7694 static void
   7695 Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7696 {
   7697   slotbuf[0] = 0x13b000;
   7698 }
   7699 
   7700 static void
   7701 Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7702 {
   7703   slotbuf[0] = 0x3d000;
   7704 }
   7705 
   7706 static void
   7707 Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7708 {
   7709   slotbuf[0] = 0x3e600;
   7710 }
   7711 
   7712 static void
   7713 Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7714 {
   7715   slotbuf[0] = 0x13e600;
   7716 }
   7717 
   7718 static void
   7719 Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7720 {
   7721   slotbuf[0] = 0x61e600;
   7722 }
   7723 
   7724 static void
   7725 Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7726 {
   7727   slotbuf[0] = 0x3b100;
   7728 }
   7729 
   7730 static void
   7731 Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7732 {
   7733   slotbuf[0] = 0x13b100;
   7734 }
   7735 
   7736 static void
   7737 Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7738 {
   7739   slotbuf[0] = 0x61b100;
   7740 }
   7741 
   7742 static void
   7743 Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7744 {
   7745   slotbuf[0] = 0x3d100;
   7746 }
   7747 
   7748 static void
   7749 Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7750 {
   7751   slotbuf[0] = 0x13d100;
   7752 }
   7753 
   7754 static void
   7755 Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7756 {
   7757   slotbuf[0] = 0x61d100;
   7758 }
   7759 
   7760 static void
   7761 Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7762 {
   7763   slotbuf[0] = 0x3b200;
   7764 }
   7765 
   7766 static void
   7767 Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7768 {
   7769   slotbuf[0] = 0x13b200;
   7770 }
   7771 
   7772 static void
   7773 Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7774 {
   7775   slotbuf[0] = 0x61b200;
   7776 }
   7777 
   7778 static void
   7779 Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7780 {
   7781   slotbuf[0] = 0x3d200;
   7782 }
   7783 
   7784 static void
   7785 Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7786 {
   7787   slotbuf[0] = 0x13d200;
   7788 }
   7789 
   7790 static void
   7791 Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7792 {
   7793   slotbuf[0] = 0x61d200;
   7794 }
   7795 
   7796 static void
   7797 Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7798 {
   7799   slotbuf[0] = 0x3b300;
   7800 }
   7801 
   7802 static void
   7803 Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7804 {
   7805   slotbuf[0] = 0x13b300;
   7806 }
   7807 
   7808 static void
   7809 Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7810 {
   7811   slotbuf[0] = 0x61b300;
   7812 }
   7813 
   7814 static void
   7815 Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7816 {
   7817   slotbuf[0] = 0x3d300;
   7818 }
   7819 
   7820 static void
   7821 Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7822 {
   7823   slotbuf[0] = 0x13d300;
   7824 }
   7825 
   7826 static void
   7827 Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7828 {
   7829   slotbuf[0] = 0x61d300;
   7830 }
   7831 
   7832 static void
   7833 Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7834 {
   7835   slotbuf[0] = 0x3b400;
   7836 }
   7837 
   7838 static void
   7839 Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7840 {
   7841   slotbuf[0] = 0x13b400;
   7842 }
   7843 
   7844 static void
   7845 Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7846 {
   7847   slotbuf[0] = 0x61b400;
   7848 }
   7849 
   7850 static void
   7851 Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7852 {
   7853   slotbuf[0] = 0x3d400;
   7854 }
   7855 
   7856 static void
   7857 Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7858 {
   7859   slotbuf[0] = 0x13d400;
   7860 }
   7861 
   7862 static void
   7863 Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7864 {
   7865   slotbuf[0] = 0x61d400;
   7866 }
   7867 
   7868 static void
   7869 Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7870 {
   7871   slotbuf[0] = 0x3b500;
   7872 }
   7873 
   7874 static void
   7875 Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7876 {
   7877   slotbuf[0] = 0x13b500;
   7878 }
   7879 
   7880 static void
   7881 Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7882 {
   7883   slotbuf[0] = 0x61b500;
   7884 }
   7885 
   7886 static void
   7887 Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7888 {
   7889   slotbuf[0] = 0x3d500;
   7890 }
   7891 
   7892 static void
   7893 Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7894 {
   7895   slotbuf[0] = 0x13d500;
   7896 }
   7897 
   7898 static void
   7899 Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7900 {
   7901   slotbuf[0] = 0x61d500;
   7902 }
   7903 
   7904 static void
   7905 Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7906 {
   7907   slotbuf[0] = 0x3b600;
   7908 }
   7909 
   7910 static void
   7911 Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7912 {
   7913   slotbuf[0] = 0x13b600;
   7914 }
   7915 
   7916 static void
   7917 Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7918 {
   7919   slotbuf[0] = 0x61b600;
   7920 }
   7921 
   7922 static void
   7923 Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7924 {
   7925   slotbuf[0] = 0x3d600;
   7926 }
   7927 
   7928 static void
   7929 Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7930 {
   7931   slotbuf[0] = 0x13d600;
   7932 }
   7933 
   7934 static void
   7935 Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7936 {
   7937   slotbuf[0] = 0x61d600;
   7938 }
   7939 
   7940 static void
   7941 Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7942 {
   7943   slotbuf[0] = 0x3b700;
   7944 }
   7945 
   7946 static void
   7947 Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7948 {
   7949   slotbuf[0] = 0x13b700;
   7950 }
   7951 
   7952 static void
   7953 Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7954 {
   7955   slotbuf[0] = 0x61b700;
   7956 }
   7957 
   7958 static void
   7959 Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7960 {
   7961   slotbuf[0] = 0x3d700;
   7962 }
   7963 
   7964 static void
   7965 Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7966 {
   7967   slotbuf[0] = 0x13d700;
   7968 }
   7969 
   7970 static void
   7971 Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7972 {
   7973   slotbuf[0] = 0x61d700;
   7974 }
   7975 
   7976 static void
   7977 Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7978 {
   7979   slotbuf[0] = 0x3c200;
   7980 }
   7981 
   7982 static void
   7983 Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7984 {
   7985   slotbuf[0] = 0x13c200;
   7986 }
   7987 
   7988 static void
   7989 Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7990 {
   7991   slotbuf[0] = 0x61c200;
   7992 }
   7993 
   7994 static void
   7995 Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   7996 {
   7997   slotbuf[0] = 0x3c300;
   7998 }
   7999 
   8000 static void
   8001 Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8002 {
   8003   slotbuf[0] = 0x13c300;
   8004 }
   8005 
   8006 static void
   8007 Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8008 {
   8009   slotbuf[0] = 0x61c300;
   8010 }
   8011 
   8012 static void
   8013 Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8014 {
   8015   slotbuf[0] = 0x3c400;
   8016 }
   8017 
   8018 static void
   8019 Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8020 {
   8021   slotbuf[0] = 0x13c400;
   8022 }
   8023 
   8024 static void
   8025 Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8026 {
   8027   slotbuf[0] = 0x61c400;
   8028 }
   8029 
   8030 static void
   8031 Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8032 {
   8033   slotbuf[0] = 0x3c500;
   8034 }
   8035 
   8036 static void
   8037 Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8038 {
   8039   slotbuf[0] = 0x13c500;
   8040 }
   8041 
   8042 static void
   8043 Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8044 {
   8045   slotbuf[0] = 0x61c500;
   8046 }
   8047 
   8048 static void
   8049 Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8050 {
   8051   slotbuf[0] = 0x3c600;
   8052 }
   8053 
   8054 static void
   8055 Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8056 {
   8057   slotbuf[0] = 0x13c600;
   8058 }
   8059 
   8060 static void
   8061 Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8062 {
   8063   slotbuf[0] = 0x61c600;
   8064 }
   8065 
   8066 static void
   8067 Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8068 {
   8069   slotbuf[0] = 0x3c700;
   8070 }
   8071 
   8072 static void
   8073 Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8074 {
   8075   slotbuf[0] = 0x13c700;
   8076 }
   8077 
   8078 static void
   8079 Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8080 {
   8081   slotbuf[0] = 0x61c700;
   8082 }
   8083 
   8084 static void
   8085 Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8086 {
   8087   slotbuf[0] = 0x3ee00;
   8088 }
   8089 
   8090 static void
   8091 Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8092 {
   8093   slotbuf[0] = 0x13ee00;
   8094 }
   8095 
   8096 static void
   8097 Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8098 {
   8099   slotbuf[0] = 0x61ee00;
   8100 }
   8101 
   8102 static void
   8103 Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8104 {
   8105   slotbuf[0] = 0x3c000;
   8106 }
   8107 
   8108 static void
   8109 Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8110 {
   8111   slotbuf[0] = 0x13c000;
   8112 }
   8113 
   8114 static void
   8115 Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8116 {
   8117   slotbuf[0] = 0x61c000;
   8118 }
   8119 
   8120 static void
   8121 Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8122 {
   8123   slotbuf[0] = 0x3e800;
   8124 }
   8125 
   8126 static void
   8127 Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8128 {
   8129   slotbuf[0] = 0x13e800;
   8130 }
   8131 
   8132 static void
   8133 Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8134 {
   8135   slotbuf[0] = 0x61e800;
   8136 }
   8137 
   8138 static void
   8139 Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8140 {
   8141   slotbuf[0] = 0x3f400;
   8142 }
   8143 
   8144 static void
   8145 Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8146 {
   8147   slotbuf[0] = 0x13f400;
   8148 }
   8149 
   8150 static void
   8151 Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8152 {
   8153   slotbuf[0] = 0x61f400;
   8154 }
   8155 
   8156 static void
   8157 Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8158 {
   8159   slotbuf[0] = 0x3f500;
   8160 }
   8161 
   8162 static void
   8163 Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8164 {
   8165   slotbuf[0] = 0x13f500;
   8166 }
   8167 
   8168 static void
   8169 Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8170 {
   8171   slotbuf[0] = 0x61f500;
   8172 }
   8173 
   8174 static void
   8175 Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8176 {
   8177   slotbuf[0] = 0x3eb00;
   8178 }
   8179 
   8180 static void
   8181 Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8182 {
   8183   slotbuf[0] = 0x3e700;
   8184 }
   8185 
   8186 static void
   8187 Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8188 {
   8189   slotbuf[0] = 0x13e700;
   8190 }
   8191 
   8192 static void
   8193 Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8194 {
   8195   slotbuf[0] = 0x61e700;
   8196 }
   8197 
   8198 static void
   8199 Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8200 {
   8201   slotbuf[0] = 0xc10000;
   8202 }
   8203 
   8204 static void
   8205 Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8206 {
   8207   slotbuf[0] = 0xd10000;
   8208 }
   8209 
   8210 static void
   8211 Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8212 {
   8213   slotbuf[0] = 0x820000;
   8214 }
   8215 
   8216 static void
   8217 Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8218 {
   8219   slotbuf[0] = 0x740004;
   8220 }
   8221 
   8222 static void
   8223 Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8224 {
   8225   slotbuf[0] = 0x750004;
   8226 }
   8227 
   8228 static void
   8229 Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8230 {
   8231   slotbuf[0] = 0x760004;
   8232 }
   8233 
   8234 static void
   8235 Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8236 {
   8237   slotbuf[0] = 0x770004;
   8238 }
   8239 
   8240 static void
   8241 Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8242 {
   8243   slotbuf[0] = 0x700004;
   8244 }
   8245 
   8246 static void
   8247 Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8248 {
   8249   slotbuf[0] = 0x710004;
   8250 }
   8251 
   8252 static void
   8253 Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8254 {
   8255   slotbuf[0] = 0x720004;
   8256 }
   8257 
   8258 static void
   8259 Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8260 {
   8261   slotbuf[0] = 0x730004;
   8262 }
   8263 
   8264 static void
   8265 Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8266 {
   8267   slotbuf[0] = 0x340004;
   8268 }
   8269 
   8270 static void
   8271 Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8272 {
   8273   slotbuf[0] = 0x350004;
   8274 }
   8275 
   8276 static void
   8277 Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8278 {
   8279   slotbuf[0] = 0x360004;
   8280 }
   8281 
   8282 static void
   8283 Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8284 {
   8285   slotbuf[0] = 0x370004;
   8286 }
   8287 
   8288 static void
   8289 Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8290 {
   8291   slotbuf[0] = 0x640004;
   8292 }
   8293 
   8294 static void
   8295 Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8296 {
   8297   slotbuf[0] = 0x650004;
   8298 }
   8299 
   8300 static void
   8301 Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8302 {
   8303   slotbuf[0] = 0x660004;
   8304 }
   8305 
   8306 static void
   8307 Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8308 {
   8309   slotbuf[0] = 0x670004;
   8310 }
   8311 
   8312 static void
   8313 Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8314 {
   8315   slotbuf[0] = 0x240004;
   8316 }
   8317 
   8318 static void
   8319 Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8320 {
   8321   slotbuf[0] = 0x250004;
   8322 }
   8323 
   8324 static void
   8325 Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8326 {
   8327   slotbuf[0] = 0x260004;
   8328 }
   8329 
   8330 static void
   8331 Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8332 {
   8333   slotbuf[0] = 0x270004;
   8334 }
   8335 
   8336 static void
   8337 Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8338 {
   8339   slotbuf[0] = 0x780004;
   8340 }
   8341 
   8342 static void
   8343 Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8344 {
   8345   slotbuf[0] = 0x790004;
   8346 }
   8347 
   8348 static void
   8349 Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8350 {
   8351   slotbuf[0] = 0x7a0004;
   8352 }
   8353 
   8354 static void
   8355 Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8356 {
   8357   slotbuf[0] = 0x7b0004;
   8358 }
   8359 
   8360 static void
   8361 Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8362 {
   8363   slotbuf[0] = 0x7c0004;
   8364 }
   8365 
   8366 static void
   8367 Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8368 {
   8369   slotbuf[0] = 0x7d0004;
   8370 }
   8371 
   8372 static void
   8373 Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8374 {
   8375   slotbuf[0] = 0x7e0004;
   8376 }
   8377 
   8378 static void
   8379 Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8380 {
   8381   slotbuf[0] = 0x7f0004;
   8382 }
   8383 
   8384 static void
   8385 Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8386 {
   8387   slotbuf[0] = 0x380004;
   8388 }
   8389 
   8390 static void
   8391 Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8392 {
   8393   slotbuf[0] = 0x390004;
   8394 }
   8395 
   8396 static void
   8397 Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8398 {
   8399   slotbuf[0] = 0x3a0004;
   8400 }
   8401 
   8402 static void
   8403 Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8404 {
   8405   slotbuf[0] = 0x3b0004;
   8406 }
   8407 
   8408 static void
   8409 Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8410 {
   8411   slotbuf[0] = 0x3c0004;
   8412 }
   8413 
   8414 static void
   8415 Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8416 {
   8417   slotbuf[0] = 0x3d0004;
   8418 }
   8419 
   8420 static void
   8421 Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8422 {
   8423   slotbuf[0] = 0x3e0004;
   8424 }
   8425 
   8426 static void
   8427 Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8428 {
   8429   slotbuf[0] = 0x3f0004;
   8430 }
   8431 
   8432 static void
   8433 Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8434 {
   8435   slotbuf[0] = 0x680004;
   8436 }
   8437 
   8438 static void
   8439 Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8440 {
   8441   slotbuf[0] = 0x690004;
   8442 }
   8443 
   8444 static void
   8445 Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8446 {
   8447   slotbuf[0] = 0x6a0004;
   8448 }
   8449 
   8450 static void
   8451 Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8452 {
   8453   slotbuf[0] = 0x6b0004;
   8454 }
   8455 
   8456 static void
   8457 Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8458 {
   8459   slotbuf[0] = 0x6c0004;
   8460 }
   8461 
   8462 static void
   8463 Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8464 {
   8465   slotbuf[0] = 0x6d0004;
   8466 }
   8467 
   8468 static void
   8469 Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8470 {
   8471   slotbuf[0] = 0x6e0004;
   8472 }
   8473 
   8474 static void
   8475 Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8476 {
   8477   slotbuf[0] = 0x6f0004;
   8478 }
   8479 
   8480 static void
   8481 Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8482 {
   8483   slotbuf[0] = 0x280004;
   8484 }
   8485 
   8486 static void
   8487 Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8488 {
   8489   slotbuf[0] = 0x290004;
   8490 }
   8491 
   8492 static void
   8493 Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8494 {
   8495   slotbuf[0] = 0x2a0004;
   8496 }
   8497 
   8498 static void
   8499 Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8500 {
   8501   slotbuf[0] = 0x2b0004;
   8502 }
   8503 
   8504 static void
   8505 Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8506 {
   8507   slotbuf[0] = 0x2c0004;
   8508 }
   8509 
   8510 static void
   8511 Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8512 {
   8513   slotbuf[0] = 0x2d0004;
   8514 }
   8515 
   8516 static void
   8517 Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8518 {
   8519   slotbuf[0] = 0x2e0004;
   8520 }
   8521 
   8522 static void
   8523 Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8524 {
   8525   slotbuf[0] = 0x2f0004;
   8526 }
   8527 
   8528 static void
   8529 Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8530 {
   8531   slotbuf[0] = 0x580004;
   8532 }
   8533 
   8534 static void
   8535 Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8536 {
   8537   slotbuf[0] = 0x480004;
   8538 }
   8539 
   8540 static void
   8541 Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8542 {
   8543   slotbuf[0] = 0x590004;
   8544 }
   8545 
   8546 static void
   8547 Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8548 {
   8549   slotbuf[0] = 0x490004;
   8550 }
   8551 
   8552 static void
   8553 Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8554 {
   8555   slotbuf[0] = 0x5a0004;
   8556 }
   8557 
   8558 static void
   8559 Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8560 {
   8561   slotbuf[0] = 0x4a0004;
   8562 }
   8563 
   8564 static void
   8565 Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8566 {
   8567   slotbuf[0] = 0x5b0004;
   8568 }
   8569 
   8570 static void
   8571 Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8572 {
   8573   slotbuf[0] = 0x4b0004;
   8574 }
   8575 
   8576 static void
   8577 Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8578 {
   8579   slotbuf[0] = 0x180004;
   8580 }
   8581 
   8582 static void
   8583 Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8584 {
   8585   slotbuf[0] = 0x80004;
   8586 }
   8587 
   8588 static void
   8589 Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8590 {
   8591   slotbuf[0] = 0x190004;
   8592 }
   8593 
   8594 static void
   8595 Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8596 {
   8597   slotbuf[0] = 0x90004;
   8598 }
   8599 
   8600 static void
   8601 Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8602 {
   8603   slotbuf[0] = 0x1a0004;
   8604 }
   8605 
   8606 static void
   8607 Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8608 {
   8609   slotbuf[0] = 0xa0004;
   8610 }
   8611 
   8612 static void
   8613 Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8614 {
   8615   slotbuf[0] = 0x1b0004;
   8616 }
   8617 
   8618 static void
   8619 Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8620 {
   8621   slotbuf[0] = 0xb0004;
   8622 }
   8623 
   8624 static void
   8625 Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8626 {
   8627   slotbuf[0] = 0x900004;
   8628 }
   8629 
   8630 static void
   8631 Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8632 {
   8633   slotbuf[0] = 0x800004;
   8634 }
   8635 
   8636 static void
   8637 Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8638 {
   8639   slotbuf[0] = 0x32000;
   8640 }
   8641 
   8642 static void
   8643 Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8644 {
   8645   slotbuf[0] = 0x132000;
   8646 }
   8647 
   8648 static void
   8649 Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8650 {
   8651   slotbuf[0] = 0x612000;
   8652 }
   8653 
   8654 static void
   8655 Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8656 {
   8657   slotbuf[0] = 0x32100;
   8658 }
   8659 
   8660 static void
   8661 Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8662 {
   8663   slotbuf[0] = 0x132100;
   8664 }
   8665 
   8666 static void
   8667 Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8668 {
   8669   slotbuf[0] = 0x612100;
   8670 }
   8671 
   8672 static void
   8673 Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8674 {
   8675   slotbuf[0] = 0x32200;
   8676 }
   8677 
   8678 static void
   8679 Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8680 {
   8681   slotbuf[0] = 0x132200;
   8682 }
   8683 
   8684 static void
   8685 Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8686 {
   8687   slotbuf[0] = 0x612200;
   8688 }
   8689 
   8690 static void
   8691 Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8692 {
   8693   slotbuf[0] = 0x32300;
   8694 }
   8695 
   8696 static void
   8697 Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8698 {
   8699   slotbuf[0] = 0x132300;
   8700 }
   8701 
   8702 static void
   8703 Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8704 {
   8705   slotbuf[0] = 0x612300;
   8706 }
   8707 
   8708 static void
   8709 Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8710 {
   8711   slotbuf[0] = 0x31000;
   8712 }
   8713 
   8714 static void
   8715 Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8716 {
   8717   slotbuf[0] = 0x131000;
   8718 }
   8719 
   8720 static void
   8721 Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8722 {
   8723   slotbuf[0] = 0x611000;
   8724 }
   8725 
   8726 static void
   8727 Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8728 {
   8729   slotbuf[0] = 0x31100;
   8730 }
   8731 
   8732 static void
   8733 Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8734 {
   8735   slotbuf[0] = 0x131100;
   8736 }
   8737 
   8738 static void
   8739 Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8740 {
   8741   slotbuf[0] = 0x611100;
   8742 }
   8743 
   8744 static void
   8745 Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8746 {
   8747   slotbuf[0] = 0x3010;
   8748 }
   8749 
   8750 static void
   8751 Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8752 {
   8753   slotbuf[0] = 0x7000;
   8754 }
   8755 
   8756 static void
   8757 Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8758 {
   8759   slotbuf[0] = 0x3e200;
   8760 }
   8761 
   8762 static void
   8763 Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8764 {
   8765   slotbuf[0] = 0x13e200;
   8766 }
   8767 
   8768 static void
   8769 Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8770 {
   8771   slotbuf[0] = 0x13e300;
   8772 }
   8773 
   8774 static void
   8775 Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8776 {
   8777   slotbuf[0] = 0x3e400;
   8778 }
   8779 
   8780 static void
   8781 Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8782 {
   8783   slotbuf[0] = 0x13e400;
   8784 }
   8785 
   8786 static void
   8787 Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8788 {
   8789   slotbuf[0] = 0x61e400;
   8790 }
   8791 
   8792 static void
   8793 Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8794 {
   8795   slotbuf[0] = 0x4000;
   8796 }
   8797 
   8798 static void
   8799 Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
   8800 {
   8801   slotbuf[0] = 0xf02d;
   8802 }
   8803 
   8804 static void
   8805 Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8806 {
   8807   slotbuf[0] = 0x39000;
   8808 }
   8809 
   8810 static void
   8811 Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8812 {
   8813   slotbuf[0] = 0x139000;
   8814 }
   8815 
   8816 static void
   8817 Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8818 {
   8819   slotbuf[0] = 0x619000;
   8820 }
   8821 
   8822 static void
   8823 Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8824 {
   8825   slotbuf[0] = 0x3a000;
   8826 }
   8827 
   8828 static void
   8829 Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8830 {
   8831   slotbuf[0] = 0x13a000;
   8832 }
   8833 
   8834 static void
   8835 Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8836 {
   8837   slotbuf[0] = 0x61a000;
   8838 }
   8839 
   8840 static void
   8841 Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8842 {
   8843   slotbuf[0] = 0x39100;
   8844 }
   8845 
   8846 static void
   8847 Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8848 {
   8849   slotbuf[0] = 0x139100;
   8850 }
   8851 
   8852 static void
   8853 Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8854 {
   8855   slotbuf[0] = 0x619100;
   8856 }
   8857 
   8858 static void
   8859 Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8860 {
   8861   slotbuf[0] = 0x3a100;
   8862 }
   8863 
   8864 static void
   8865 Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8866 {
   8867   slotbuf[0] = 0x13a100;
   8868 }
   8869 
   8870 static void
   8871 Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8872 {
   8873   slotbuf[0] = 0x61a100;
   8874 }
   8875 
   8876 static void
   8877 Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8878 {
   8879   slotbuf[0] = 0x38000;
   8880 }
   8881 
   8882 static void
   8883 Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8884 {
   8885   slotbuf[0] = 0x138000;
   8886 }
   8887 
   8888 static void
   8889 Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8890 {
   8891   slotbuf[0] = 0x618000;
   8892 }
   8893 
   8894 static void
   8895 Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8896 {
   8897   slotbuf[0] = 0x38100;
   8898 }
   8899 
   8900 static void
   8901 Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8902 {
   8903   slotbuf[0] = 0x138100;
   8904 }
   8905 
   8906 static void
   8907 Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8908 {
   8909   slotbuf[0] = 0x618100;
   8910 }
   8911 
   8912 static void
   8913 Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8914 {
   8915   slotbuf[0] = 0x36000;
   8916 }
   8917 
   8918 static void
   8919 Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8920 {
   8921   slotbuf[0] = 0x136000;
   8922 }
   8923 
   8924 static void
   8925 Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8926 {
   8927   slotbuf[0] = 0x616000;
   8928 }
   8929 
   8930 static void
   8931 Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8932 {
   8933   slotbuf[0] = 0x3e900;
   8934 }
   8935 
   8936 static void
   8937 Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8938 {
   8939   slotbuf[0] = 0x13e900;
   8940 }
   8941 
   8942 static void
   8943 Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8944 {
   8945   slotbuf[0] = 0x61e900;
   8946 }
   8947 
   8948 static void
   8949 Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8950 {
   8951   slotbuf[0] = 0x3ec00;
   8952 }
   8953 
   8954 static void
   8955 Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8956 {
   8957   slotbuf[0] = 0x13ec00;
   8958 }
   8959 
   8960 static void
   8961 Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8962 {
   8963   slotbuf[0] = 0x61ec00;
   8964 }
   8965 
   8966 static void
   8967 Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8968 {
   8969   slotbuf[0] = 0x3ed00;
   8970 }
   8971 
   8972 static void
   8973 Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8974 {
   8975   slotbuf[0] = 0x13ed00;
   8976 }
   8977 
   8978 static void
   8979 Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8980 {
   8981   slotbuf[0] = 0x61ed00;
   8982 }
   8983 
   8984 static void
   8985 Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8986 {
   8987   slotbuf[0] = 0x36800;
   8988 }
   8989 
   8990 static void
   8991 Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8992 {
   8993   slotbuf[0] = 0x136800;
   8994 }
   8995 
   8996 static void
   8997 Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   8998 {
   8999   slotbuf[0] = 0x616800;
   9000 }
   9001 
   9002 static void
   9003 Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9004 {
   9005   slotbuf[0] = 0xf1e000;
   9006 }
   9007 
   9008 static void
   9009 Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9010 {
   9011   slotbuf[0] = 0xf1e010;
   9012 }
   9013 
   9014 static void
   9015 Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9016 {
   9017   slotbuf[0] = 0x135900;
   9018 }
   9019 
   9020 static void
   9021 Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9022 {
   9023   slotbuf[0] = 0x3ea00;
   9024 }
   9025 
   9026 static void
   9027 Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9028 {
   9029   slotbuf[0] = 0x13ea00;
   9030 }
   9031 
   9032 static void
   9033 Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9034 {
   9035   slotbuf[0] = 0x61ea00;
   9036 }
   9037 
   9038 static void
   9039 Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9040 {
   9041   slotbuf[0] = 0x3f000;
   9042 }
   9043 
   9044 static void
   9045 Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9046 {
   9047   slotbuf[0] = 0x13f000;
   9048 }
   9049 
   9050 static void
   9051 Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9052 {
   9053   slotbuf[0] = 0x61f000;
   9054 }
   9055 
   9056 static void
   9057 Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9058 {
   9059   slotbuf[0] = 0x3f100;
   9060 }
   9061 
   9062 static void
   9063 Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9064 {
   9065   slotbuf[0] = 0x13f100;
   9066 }
   9067 
   9068 static void
   9069 Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9070 {
   9071   slotbuf[0] = 0x61f100;
   9072 }
   9073 
   9074 static void
   9075 Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9076 {
   9077   slotbuf[0] = 0x3f200;
   9078 }
   9079 
   9080 static void
   9081 Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9082 {
   9083   slotbuf[0] = 0x13f200;
   9084 }
   9085 
   9086 static void
   9087 Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9088 {
   9089   slotbuf[0] = 0x61f200;
   9090 }
   9091 
   9092 static void
   9093 Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9094 {
   9095   slotbuf[0] = 0x70c2;
   9096 }
   9097 
   9098 static void
   9099 Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9100 {
   9101   slotbuf[0] = 0x70e2;
   9102 }
   9103 
   9104 static void
   9105 Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9106 {
   9107   slotbuf[0] = 0x70d2;
   9108 }
   9109 
   9110 static void
   9111 Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9112 {
   9113   slotbuf[0] = 0x270d2;
   9114 }
   9115 
   9116 static void
   9117 Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9118 {
   9119   slotbuf[0] = 0x370d2;
   9120 }
   9121 
   9122 static void
   9123 Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9124 {
   9125   slotbuf[0] = 0x70f2;
   9126 }
   9127 
   9128 static void
   9129 Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9130 {
   9131   slotbuf[0] = 0xf10000;
   9132 }
   9133 
   9134 static void
   9135 Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9136 {
   9137   slotbuf[0] = 0xf12000;
   9138 }
   9139 
   9140 static void
   9141 Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9142 {
   9143   slotbuf[0] = 0xf11000;
   9144 }
   9145 
   9146 static void
   9147 Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9148 {
   9149   slotbuf[0] = 0xf13000;
   9150 }
   9151 
   9152 static void
   9153 Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9154 {
   9155   slotbuf[0] = 0x7042;
   9156 }
   9157 
   9158 static void
   9159 Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9160 {
   9161   slotbuf[0] = 0x7052;
   9162 }
   9163 
   9164 static void
   9165 Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9166 {
   9167   slotbuf[0] = 0x47082;
   9168 }
   9169 
   9170 static void
   9171 Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9172 {
   9173   slotbuf[0] = 0x57082;
   9174 }
   9175 
   9176 static void
   9177 Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9178 {
   9179   slotbuf[0] = 0x7062;
   9180 }
   9181 
   9182 static void
   9183 Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9184 {
   9185   slotbuf[0] = 0x7072;
   9186 }
   9187 
   9188 static void
   9189 Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9190 {
   9191   slotbuf[0] = 0x7002;
   9192 }
   9193 
   9194 static void
   9195 Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9196 {
   9197   slotbuf[0] = 0x7012;
   9198 }
   9199 
   9200 static void
   9201 Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9202 {
   9203   slotbuf[0] = 0x7022;
   9204 }
   9205 
   9206 static void
   9207 Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9208 {
   9209   slotbuf[0] = 0x7032;
   9210 }
   9211 
   9212 static void
   9213 Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9214 {
   9215   slotbuf[0] = 0x7082;
   9216 }
   9217 
   9218 static void
   9219 Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9220 {
   9221   slotbuf[0] = 0x27082;
   9222 }
   9223 
   9224 static void
   9225 Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9226 {
   9227   slotbuf[0] = 0x37082;
   9228 }
   9229 
   9230 static void
   9231 Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9232 {
   9233   slotbuf[0] = 0xf19000;
   9234 }
   9235 
   9236 static void
   9237 Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9238 {
   9239   slotbuf[0] = 0xf18000;
   9240 }
   9241 
   9242 static void
   9243 Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9244 {
   9245   slotbuf[0] = 0x135300;
   9246 }
   9247 
   9248 static void
   9249 Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9250 {
   9251   slotbuf[0] = 0x35300;
   9252 }
   9253 
   9254 static void
   9255 Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9256 {
   9257   slotbuf[0] = 0x615300;
   9258 }
   9259 
   9260 static void
   9261 Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9262 {
   9263   slotbuf[0] = 0x35a00;
   9264 }
   9265 
   9266 static void
   9267 Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9268 {
   9269   slotbuf[0] = 0x135a00;
   9270 }
   9271 
   9272 static void
   9273 Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9274 {
   9275   slotbuf[0] = 0x615a00;
   9276 }
   9277 
   9278 static void
   9279 Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9280 {
   9281   slotbuf[0] = 0x35b00;
   9282 }
   9283 
   9284 static void
   9285 Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9286 {
   9287   slotbuf[0] = 0x135b00;
   9288 }
   9289 
   9290 static void
   9291 Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9292 {
   9293   slotbuf[0] = 0x615b00;
   9294 }
   9295 
   9296 static void
   9297 Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9298 {
   9299   slotbuf[0] = 0x35c00;
   9300 }
   9301 
   9302 static void
   9303 Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9304 {
   9305   slotbuf[0] = 0x135c00;
   9306 }
   9307 
   9308 static void
   9309 Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9310 {
   9311   slotbuf[0] = 0x615c00;
   9312 }
   9313 
   9314 static void
   9315 Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9316 {
   9317   slotbuf[0] = 0x50c000;
   9318 }
   9319 
   9320 static void
   9321 Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9322 {
   9323   slotbuf[0] = 0x50d000;
   9324 }
   9325 
   9326 static void
   9327 Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9328 {
   9329   slotbuf[0] = 0x50b000;
   9330 }
   9331 
   9332 static void
   9333 Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9334 {
   9335   slotbuf[0] = 0x50f000;
   9336 }
   9337 
   9338 static void
   9339 Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9340 {
   9341   slotbuf[0] = 0x50e000;
   9342 }
   9343 
   9344 static void
   9345 Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9346 {
   9347   slotbuf[0] = 0x504000;
   9348 }
   9349 
   9350 static void
   9351 Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9352 {
   9353   slotbuf[0] = 0x505000;
   9354 }
   9355 
   9356 static void
   9357 Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9358 {
   9359   slotbuf[0] = 0x503000;
   9360 }
   9361 
   9362 static void
   9363 Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9364 {
   9365   slotbuf[0] = 0x507000;
   9366 }
   9367 
   9368 static void
   9369 Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9370 {
   9371   slotbuf[0] = 0x506000;
   9372 }
   9373 
   9374 static void
   9375 Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9376 {
   9377   slotbuf[0] = 0xf1f000;
   9378 }
   9379 
   9380 static void
   9381 Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9382 {
   9383   slotbuf[0] = 0x501000;
   9384 }
   9385 
   9386 static void
   9387 Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9388 {
   9389   slotbuf[0] = 0x509000;
   9390 }
   9391 
   9392 static void
   9393 Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9394 {
   9395   slotbuf[0] = 0x3e000;
   9396 }
   9397 
   9398 static void
   9399 Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9400 {
   9401   slotbuf[0] = 0x13e000;
   9402 }
   9403 
   9404 static void
   9405 Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9406 {
   9407   slotbuf[0] = 0x61e000;
   9408 }
   9409 
   9410 static void
   9411 Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9412 {
   9413   slotbuf[0] = 0x330000;
   9414 }
   9415 
   9416 static void
   9417 Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9418 {
   9419   slotbuf[0] = 0x430000;
   9420 }
   9421 
   9422 static void
   9423 Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9424 {
   9425   slotbuf[0] = 0x530000;
   9426 }
   9427 
   9428 static void
   9429 Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9430 {
   9431   slotbuf[0] = 0x630000;
   9432 }
   9433 
   9434 static void
   9435 Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9436 {
   9437   slotbuf[0] = 0x730000;
   9438 }
   9439 
   9440 static void
   9441 Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9442 {
   9443   slotbuf[0] = 0x40e000;
   9444 }
   9445 
   9446 static void
   9447 Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9448 {
   9449   slotbuf[0] = 0x40f000;
   9450 }
   9451 
   9452 static void
   9453 Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9454 {
   9455   slotbuf[0] = 0x230000;
   9456 }
   9457 
   9458 static void
   9459 Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9460 {
   9461   slotbuf[0] = 0xb002;
   9462 }
   9463 
   9464 static void
   9465 Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9466 {
   9467   slotbuf[0] = 0xf002;
   9468 }
   9469 
   9470 static void
   9471 Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9472 {
   9473   slotbuf[0] = 0xe002;
   9474 }
   9475 
   9476 static void
   9477 Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9478 {
   9479   slotbuf[0] = 0x30c00;
   9480 }
   9481 
   9482 static void
   9483 Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9484 {
   9485   slotbuf[0] = 0x130c00;
   9486 }
   9487 
   9488 static void
   9489 Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9490 {
   9491   slotbuf[0] = 0x610c00;
   9492 }
   9493 
   9494 static void
   9495 Opcode_rsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9496 {
   9497   slotbuf[0] = 0x36300;
   9498 }
   9499 
   9500 static void
   9501 Opcode_wsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9502 {
   9503   slotbuf[0] = 0x136300;
   9504 }
   9505 
   9506 static void
   9507 Opcode_xsr_atomctl_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9508 {
   9509   slotbuf[0] = 0x616300;
   9510 }
   9511 
   9512 static void
   9513 Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9514 {
   9515   slotbuf[0] = 0xc20000;
   9516 }
   9517 
   9518 static void
   9519 Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9520 {
   9521   slotbuf[0] = 0xd20000;
   9522 }
   9523 
   9524 static void
   9525 Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9526 {
   9527   slotbuf[0] = 0xe20000;
   9528 }
   9529 
   9530 static void
   9531 Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9532 {
   9533   slotbuf[0] = 0xf20000;
   9534 }
   9535 
   9536 static void
   9537 Opcode_rer_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9538 {
   9539   slotbuf[0] = 0x406000;
   9540 }
   9541 
   9542 static void
   9543 Opcode_wer_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9544 {
   9545   slotbuf[0] = 0x407000;
   9546 }
   9547 
   9548 static void
   9549 Opcode_rur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9550 {
   9551   slotbuf[0] = 0xe30e60;
   9552 }
   9553 
   9554 static void
   9555 Opcode_wur_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9556 {
   9557   slotbuf[0] = 0xf3e600;
   9558 }
   9559 
   9560 static void
   9561 Opcode_read_impwire_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9562 {
   9563   slotbuf[0] = 0xe0000;
   9564 }
   9565 
   9566 static void
   9567 Opcode_setb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9568 {
   9569   slotbuf[0] = 0xe1000;
   9570 }
   9571 
   9572 static void
   9573 Opcode_clrb_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9574 {
   9575   slotbuf[0] = 0xe1200;
   9576 }
   9577 
   9578 static void
   9579 Opcode_wrmsk_expstate_Slot_inst_encode (xtensa_insnbuf slotbuf)
   9580 {
   9581   slotbuf[0] = 0xe2000;
   9582 }
   9583 
   9584 static xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
   9585   Opcode_excw_Slot_inst_encode, 0, 0
   9586 };
   9587 
   9588 static xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
   9589   Opcode_rfe_Slot_inst_encode, 0, 0
   9590 };
   9591 
   9592 static xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
   9593   Opcode_rfde_Slot_inst_encode, 0, 0
   9594 };
   9595 
   9596 static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
   9597   Opcode_syscall_Slot_inst_encode, 0, 0
   9598 };
   9599 
   9600 static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
   9601   Opcode_simcall_Slot_inst_encode, 0, 0
   9602 };
   9603 
   9604 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
   9605   Opcode_call12_Slot_inst_encode, 0, 0
   9606 };
   9607 
   9608 static xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
   9609   Opcode_call8_Slot_inst_encode, 0, 0
   9610 };
   9611 
   9612 static xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
   9613   Opcode_call4_Slot_inst_encode, 0, 0
   9614 };
   9615 
   9616 static xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
   9617   Opcode_callx12_Slot_inst_encode, 0, 0
   9618 };
   9619 
   9620 static xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
   9621   Opcode_callx8_Slot_inst_encode, 0, 0
   9622 };
   9623 
   9624 static xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
   9625   Opcode_callx4_Slot_inst_encode, 0, 0
   9626 };
   9627 
   9628 static xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
   9629   Opcode_entry_Slot_inst_encode, 0, 0
   9630 };
   9631 
   9632 static xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
   9633   Opcode_movsp_Slot_inst_encode, 0, 0
   9634 };
   9635 
   9636 static xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
   9637   Opcode_rotw_Slot_inst_encode, 0, 0
   9638 };
   9639 
   9640 static xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
   9641   Opcode_retw_Slot_inst_encode, 0, 0
   9642 };
   9643 
   9644 static xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
   9645   0, 0, Opcode_retw_n_Slot_inst16b_encode
   9646 };
   9647 
   9648 static xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
   9649   Opcode_rfwo_Slot_inst_encode, 0, 0
   9650 };
   9651 
   9652 static xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
   9653   Opcode_rfwu_Slot_inst_encode, 0, 0
   9654 };
   9655 
   9656 static xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
   9657   Opcode_l32e_Slot_inst_encode, 0, 0
   9658 };
   9659 
   9660 static xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
   9661   Opcode_s32e_Slot_inst_encode, 0, 0
   9662 };
   9663 
   9664 static xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
   9665   Opcode_rsr_windowbase_Slot_inst_encode, 0, 0
   9666 };
   9667 
   9668 static xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
   9669   Opcode_wsr_windowbase_Slot_inst_encode, 0, 0
   9670 };
   9671 
   9672 static xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
   9673   Opcode_xsr_windowbase_Slot_inst_encode, 0, 0
   9674 };
   9675 
   9676 static xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
   9677   Opcode_rsr_windowstart_Slot_inst_encode, 0, 0
   9678 };
   9679 
   9680 static xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
   9681   Opcode_wsr_windowstart_Slot_inst_encode, 0, 0
   9682 };
   9683 
   9684 static xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
   9685   Opcode_xsr_windowstart_Slot_inst_encode, 0, 0
   9686 };
   9687 
   9688 static xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
   9689   0, Opcode_add_n_Slot_inst16a_encode, 0
   9690 };
   9691 
   9692 static xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
   9693   0, Opcode_addi_n_Slot_inst16a_encode, 0
   9694 };
   9695 
   9696 static xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
   9697   0, 0, Opcode_beqz_n_Slot_inst16b_encode
   9698 };
   9699 
   9700 static xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
   9701   0, 0, Opcode_bnez_n_Slot_inst16b_encode
   9702 };
   9703 
   9704 static xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
   9705   0, 0, Opcode_ill_n_Slot_inst16b_encode
   9706 };
   9707 
   9708 static xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
   9709   0, Opcode_l32i_n_Slot_inst16a_encode, 0
   9710 };
   9711 
   9712 static xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
   9713   0, 0, Opcode_mov_n_Slot_inst16b_encode
   9714 };
   9715 
   9716 static xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
   9717   0, 0, Opcode_movi_n_Slot_inst16b_encode
   9718 };
   9719 
   9720 static xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
   9721   0, 0, Opcode_nop_n_Slot_inst16b_encode
   9722 };
   9723 
   9724 static xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
   9725   0, 0, Opcode_ret_n_Slot_inst16b_encode
   9726 };
   9727 
   9728 static xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
   9729   0, Opcode_s32i_n_Slot_inst16a_encode, 0
   9730 };
   9731 
   9732 static xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
   9733   Opcode_rur_threadptr_Slot_inst_encode, 0, 0
   9734 };
   9735 
   9736 static xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
   9737   Opcode_wur_threadptr_Slot_inst_encode, 0, 0
   9738 };
   9739 
   9740 static xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
   9741   Opcode_addi_Slot_inst_encode, 0, 0
   9742 };
   9743 
   9744 static xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
   9745   Opcode_addmi_Slot_inst_encode, 0, 0
   9746 };
   9747 
   9748 static xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
   9749   Opcode_add_Slot_inst_encode, 0, 0
   9750 };
   9751 
   9752 static xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
   9753   Opcode_sub_Slot_inst_encode, 0, 0
   9754 };
   9755 
   9756 static xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
   9757   Opcode_addx2_Slot_inst_encode, 0, 0
   9758 };
   9759 
   9760 static xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
   9761   Opcode_addx4_Slot_inst_encode, 0, 0
   9762 };
   9763 
   9764 static xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
   9765   Opcode_addx8_Slot_inst_encode, 0, 0
   9766 };
   9767 
   9768 static xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
   9769   Opcode_subx2_Slot_inst_encode, 0, 0
   9770 };
   9771 
   9772 static xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
   9773   Opcode_subx4_Slot_inst_encode, 0, 0
   9774 };
   9775 
   9776 static xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
   9777   Opcode_subx8_Slot_inst_encode, 0, 0
   9778 };
   9779 
   9780 static xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
   9781   Opcode_and_Slot_inst_encode, 0, 0
   9782 };
   9783 
   9784 static xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
   9785   Opcode_or_Slot_inst_encode, 0, 0
   9786 };
   9787 
   9788 static xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
   9789   Opcode_xor_Slot_inst_encode, 0, 0
   9790 };
   9791 
   9792 static xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
   9793   Opcode_beqi_Slot_inst_encode, 0, 0
   9794 };
   9795 
   9796 static xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
   9797   Opcode_bnei_Slot_inst_encode, 0, 0
   9798 };
   9799 
   9800 static xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
   9801   Opcode_bgei_Slot_inst_encode, 0, 0
   9802 };
   9803 
   9804 static xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
   9805   Opcode_blti_Slot_inst_encode, 0, 0
   9806 };
   9807 
   9808 static xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
   9809   Opcode_bbci_Slot_inst_encode, 0, 0
   9810 };
   9811 
   9812 static xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
   9813   Opcode_bbsi_Slot_inst_encode, 0, 0
   9814 };
   9815 
   9816 static xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
   9817   Opcode_bgeui_Slot_inst_encode, 0, 0
   9818 };
   9819 
   9820 static xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
   9821   Opcode_bltui_Slot_inst_encode, 0, 0
   9822 };
   9823 
   9824 static xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
   9825   Opcode_beq_Slot_inst_encode, 0, 0
   9826 };
   9827 
   9828 static xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
   9829   Opcode_bne_Slot_inst_encode, 0, 0
   9830 };
   9831 
   9832 static xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
   9833   Opcode_bge_Slot_inst_encode, 0, 0
   9834 };
   9835 
   9836 static xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
   9837   Opcode_blt_Slot_inst_encode, 0, 0
   9838 };
   9839 
   9840 static xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
   9841   Opcode_bgeu_Slot_inst_encode, 0, 0
   9842 };
   9843 
   9844 static xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
   9845   Opcode_bltu_Slot_inst_encode, 0, 0
   9846 };
   9847 
   9848 static xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
   9849   Opcode_bany_Slot_inst_encode, 0, 0
   9850 };
   9851 
   9852 static xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
   9853   Opcode_bnone_Slot_inst_encode, 0, 0
   9854 };
   9855 
   9856 static xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
   9857   Opcode_ball_Slot_inst_encode, 0, 0
   9858 };
   9859 
   9860 static xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
   9861   Opcode_bnall_Slot_inst_encode, 0, 0
   9862 };
   9863 
   9864 static xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
   9865   Opcode_bbc_Slot_inst_encode, 0, 0
   9866 };
   9867 
   9868 static xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
   9869   Opcode_bbs_Slot_inst_encode, 0, 0
   9870 };
   9871 
   9872 static xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
   9873   Opcode_beqz_Slot_inst_encode, 0, 0
   9874 };
   9875 
   9876 static xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
   9877   Opcode_bnez_Slot_inst_encode, 0, 0
   9878 };
   9879 
   9880 static xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
   9881   Opcode_bgez_Slot_inst_encode, 0, 0
   9882 };
   9883 
   9884 static xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
   9885   Opcode_bltz_Slot_inst_encode, 0, 0
   9886 };
   9887 
   9888 static xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
   9889   Opcode_call0_Slot_inst_encode, 0, 0
   9890 };
   9891 
   9892 static xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
   9893   Opcode_callx0_Slot_inst_encode, 0, 0
   9894 };
   9895 
   9896 static xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
   9897   Opcode_extui_Slot_inst_encode, 0, 0
   9898 };
   9899 
   9900 static xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
   9901   Opcode_ill_Slot_inst_encode, 0, 0
   9902 };
   9903 
   9904 static xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
   9905   Opcode_j_Slot_inst_encode, 0, 0
   9906 };
   9907 
   9908 static xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
   9909   Opcode_jx_Slot_inst_encode, 0, 0
   9910 };
   9911 
   9912 static xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
   9913   Opcode_l16ui_Slot_inst_encode, 0, 0
   9914 };
   9915 
   9916 static xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
   9917   Opcode_l16si_Slot_inst_encode, 0, 0
   9918 };
   9919 
   9920 static xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
   9921   Opcode_l32i_Slot_inst_encode, 0, 0
   9922 };
   9923 
   9924 static xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
   9925   Opcode_l32r_Slot_inst_encode, 0, 0
   9926 };
   9927 
   9928 static xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
   9929   Opcode_l8ui_Slot_inst_encode, 0, 0
   9930 };
   9931 
   9932 static xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
   9933   Opcode_loop_Slot_inst_encode, 0, 0
   9934 };
   9935 
   9936 static xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
   9937   Opcode_loopnez_Slot_inst_encode, 0, 0
   9938 };
   9939 
   9940 static xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
   9941   Opcode_loopgtz_Slot_inst_encode, 0, 0
   9942 };
   9943 
   9944 static xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
   9945   Opcode_movi_Slot_inst_encode, 0, 0
   9946 };
   9947 
   9948 static xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
   9949   Opcode_moveqz_Slot_inst_encode, 0, 0
   9950 };
   9951 
   9952 static xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
   9953   Opcode_movnez_Slot_inst_encode, 0, 0
   9954 };
   9955 
   9956 static xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
   9957   Opcode_movltz_Slot_inst_encode, 0, 0
   9958 };
   9959 
   9960 static xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
   9961   Opcode_movgez_Slot_inst_encode, 0, 0
   9962 };
   9963 
   9964 static xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
   9965   Opcode_neg_Slot_inst_encode, 0, 0
   9966 };
   9967 
   9968 static xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
   9969   Opcode_abs_Slot_inst_encode, 0, 0
   9970 };
   9971 
   9972 static xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
   9973   Opcode_nop_Slot_inst_encode, 0, 0
   9974 };
   9975 
   9976 static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
   9977   Opcode_ret_Slot_inst_encode, 0, 0
   9978 };
   9979 
   9980 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
   9981   Opcode_s16i_Slot_inst_encode, 0, 0
   9982 };
   9983 
   9984 static xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
   9985   Opcode_s32i_Slot_inst_encode, 0, 0
   9986 };
   9987 
   9988 static xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
   9989   Opcode_s8i_Slot_inst_encode, 0, 0
   9990 };
   9991 
   9992 static xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
   9993   Opcode_ssr_Slot_inst_encode, 0, 0
   9994 };
   9995 
   9996 static xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
   9997   Opcode_ssl_Slot_inst_encode, 0, 0
   9998 };
   9999 
  10000 static xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
  10001   Opcode_ssa8l_Slot_inst_encode, 0, 0
  10002 };
  10003 
  10004 static xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
  10005   Opcode_ssa8b_Slot_inst_encode, 0, 0
  10006 };
  10007 
  10008 static xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
  10009   Opcode_ssai_Slot_inst_encode, 0, 0
  10010 };
  10011 
  10012 static xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
  10013   Opcode_sll_Slot_inst_encode, 0, 0
  10014 };
  10015 
  10016 static xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
  10017   Opcode_src_Slot_inst_encode, 0, 0
  10018 };
  10019 
  10020 static xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
  10021   Opcode_srl_Slot_inst_encode, 0, 0
  10022 };
  10023 
  10024 static xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
  10025   Opcode_sra_Slot_inst_encode, 0, 0
  10026 };
  10027 
  10028 static xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
  10029   Opcode_slli_Slot_inst_encode, 0, 0
  10030 };
  10031 
  10032 static xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
  10033   Opcode_srai_Slot_inst_encode, 0, 0
  10034 };
  10035 
  10036 static xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
  10037   Opcode_srli_Slot_inst_encode, 0, 0
  10038 };
  10039 
  10040 static xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
  10041   Opcode_memw_Slot_inst_encode, 0, 0
  10042 };
  10043 
  10044 static xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
  10045   Opcode_extw_Slot_inst_encode, 0, 0
  10046 };
  10047 
  10048 static xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
  10049   Opcode_isync_Slot_inst_encode, 0, 0
  10050 };
  10051 
  10052 static xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
  10053   Opcode_rsync_Slot_inst_encode, 0, 0
  10054 };
  10055 
  10056 static xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
  10057   Opcode_esync_Slot_inst_encode, 0, 0
  10058 };
  10059 
  10060 static xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
  10061   Opcode_dsync_Slot_inst_encode, 0, 0
  10062 };
  10063 
  10064 static xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
  10065   Opcode_rsil_Slot_inst_encode, 0, 0
  10066 };
  10067 
  10068 static xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
  10069   Opcode_rsr_lend_Slot_inst_encode, 0, 0
  10070 };
  10071 
  10072 static xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
  10073   Opcode_wsr_lend_Slot_inst_encode, 0, 0
  10074 };
  10075 
  10076 static xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
  10077   Opcode_xsr_lend_Slot_inst_encode, 0, 0
  10078 };
  10079 
  10080 static xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
  10081   Opcode_rsr_lcount_Slot_inst_encode, 0, 0
  10082 };
  10083 
  10084 static xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
  10085   Opcode_wsr_lcount_Slot_inst_encode, 0, 0
  10086 };
  10087 
  10088 static xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
  10089   Opcode_xsr_lcount_Slot_inst_encode, 0, 0
  10090 };
  10091 
  10092 static xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
  10093   Opcode_rsr_lbeg_Slot_inst_encode, 0, 0
  10094 };
  10095 
  10096 static xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
  10097   Opcode_wsr_lbeg_Slot_inst_encode, 0, 0
  10098 };
  10099 
  10100 static xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
  10101   Opcode_xsr_lbeg_Slot_inst_encode, 0, 0
  10102 };
  10103 
  10104 static xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
  10105   Opcode_rsr_sar_Slot_inst_encode, 0, 0
  10106 };
  10107 
  10108 static xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
  10109   Opcode_wsr_sar_Slot_inst_encode, 0, 0
  10110 };
  10111 
  10112 static xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
  10113   Opcode_xsr_sar_Slot_inst_encode, 0, 0
  10114 };
  10115 
  10116 static xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
  10117   Opcode_rsr_litbase_Slot_inst_encode, 0, 0
  10118 };
  10119 
  10120 static xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
  10121   Opcode_wsr_litbase_Slot_inst_encode, 0, 0
  10122 };
  10123 
  10124 static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
  10125   Opcode_xsr_litbase_Slot_inst_encode, 0, 0
  10126 };
  10127 
  10128 static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
  10129   Opcode_rsr_176_Slot_inst_encode, 0, 0
  10130 };
  10131 
  10132 static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
  10133   Opcode_wsr_176_Slot_inst_encode, 0, 0
  10134 };
  10135 
  10136 static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
  10137   Opcode_rsr_208_Slot_inst_encode, 0, 0
  10138 };
  10139 
  10140 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
  10141   Opcode_rsr_ps_Slot_inst_encode, 0, 0
  10142 };
  10143 
  10144 static xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
  10145   Opcode_wsr_ps_Slot_inst_encode, 0, 0
  10146 };
  10147 
  10148 static xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
  10149   Opcode_xsr_ps_Slot_inst_encode, 0, 0
  10150 };
  10151 
  10152 static xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
  10153   Opcode_rsr_epc1_Slot_inst_encode, 0, 0
  10154 };
  10155 
  10156 static xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
  10157   Opcode_wsr_epc1_Slot_inst_encode, 0, 0
  10158 };
  10159 
  10160 static xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
  10161   Opcode_xsr_epc1_Slot_inst_encode, 0, 0
  10162 };
  10163 
  10164 static xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
  10165   Opcode_rsr_excsave1_Slot_inst_encode, 0, 0
  10166 };
  10167 
  10168 static xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
  10169   Opcode_wsr_excsave1_Slot_inst_encode, 0, 0
  10170 };
  10171 
  10172 static xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
  10173   Opcode_xsr_excsave1_Slot_inst_encode, 0, 0
  10174 };
  10175 
  10176 static xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
  10177   Opcode_rsr_epc2_Slot_inst_encode, 0, 0
  10178 };
  10179 
  10180 static xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
  10181   Opcode_wsr_epc2_Slot_inst_encode, 0, 0
  10182 };
  10183 
  10184 static xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
  10185   Opcode_xsr_epc2_Slot_inst_encode, 0, 0
  10186 };
  10187 
  10188 static xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
  10189   Opcode_rsr_excsave2_Slot_inst_encode, 0, 0
  10190 };
  10191 
  10192 static xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
  10193   Opcode_wsr_excsave2_Slot_inst_encode, 0, 0
  10194 };
  10195 
  10196 static xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
  10197   Opcode_xsr_excsave2_Slot_inst_encode, 0, 0
  10198 };
  10199 
  10200 static xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
  10201   Opcode_rsr_epc3_Slot_inst_encode, 0, 0
  10202 };
  10203 
  10204 static xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
  10205   Opcode_wsr_epc3_Slot_inst_encode, 0, 0
  10206 };
  10207 
  10208 static xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
  10209   Opcode_xsr_epc3_Slot_inst_encode, 0, 0
  10210 };
  10211 
  10212 static xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
  10213   Opcode_rsr_excsave3_Slot_inst_encode, 0, 0
  10214 };
  10215 
  10216 static xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
  10217   Opcode_wsr_excsave3_Slot_inst_encode, 0, 0
  10218 };
  10219 
  10220 static xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
  10221   Opcode_xsr_excsave3_Slot_inst_encode, 0, 0
  10222 };
  10223 
  10224 static xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
  10225   Opcode_rsr_epc4_Slot_inst_encode, 0, 0
  10226 };
  10227 
  10228 static xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
  10229   Opcode_wsr_epc4_Slot_inst_encode, 0, 0
  10230 };
  10231 
  10232 static xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
  10233   Opcode_xsr_epc4_Slot_inst_encode, 0, 0
  10234 };
  10235 
  10236 static xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
  10237   Opcode_rsr_excsave4_Slot_inst_encode, 0, 0
  10238 };
  10239 
  10240 static xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
  10241   Opcode_wsr_excsave4_Slot_inst_encode, 0, 0
  10242 };
  10243 
  10244 static xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
  10245   Opcode_xsr_excsave4_Slot_inst_encode, 0, 0
  10246 };
  10247 
  10248 static xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
  10249   Opcode_rsr_epc5_Slot_inst_encode, 0, 0
  10250 };
  10251 
  10252 static xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
  10253   Opcode_wsr_epc5_Slot_inst_encode, 0, 0
  10254 };
  10255 
  10256 static xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
  10257   Opcode_xsr_epc5_Slot_inst_encode, 0, 0
  10258 };
  10259 
  10260 static xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
  10261   Opcode_rsr_excsave5_Slot_inst_encode, 0, 0
  10262 };
  10263 
  10264 static xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
  10265   Opcode_wsr_excsave5_Slot_inst_encode, 0, 0
  10266 };
  10267 
  10268 static xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
  10269   Opcode_xsr_excsave5_Slot_inst_encode, 0, 0
  10270 };
  10271 
  10272 static xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
  10273   Opcode_rsr_epc6_Slot_inst_encode, 0, 0
  10274 };
  10275 
  10276 static xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
  10277   Opcode_wsr_epc6_Slot_inst_encode, 0, 0
  10278 };
  10279 
  10280 static xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
  10281   Opcode_xsr_epc6_Slot_inst_encode, 0, 0
  10282 };
  10283 
  10284 static xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
  10285   Opcode_rsr_excsave6_Slot_inst_encode, 0, 0
  10286 };
  10287 
  10288 static xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
  10289   Opcode_wsr_excsave6_Slot_inst_encode, 0, 0
  10290 };
  10291 
  10292 static xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
  10293   Opcode_xsr_excsave6_Slot_inst_encode, 0, 0
  10294 };
  10295 
  10296 static xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
  10297   Opcode_rsr_epc7_Slot_inst_encode, 0, 0
  10298 };
  10299 
  10300 static xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
  10301   Opcode_wsr_epc7_Slot_inst_encode, 0, 0
  10302 };
  10303 
  10304 static xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
  10305   Opcode_xsr_epc7_Slot_inst_encode, 0, 0
  10306 };
  10307 
  10308 static xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
  10309   Opcode_rsr_excsave7_Slot_inst_encode, 0, 0
  10310 };
  10311 
  10312 static xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
  10313   Opcode_wsr_excsave7_Slot_inst_encode, 0, 0
  10314 };
  10315 
  10316 static xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
  10317   Opcode_xsr_excsave7_Slot_inst_encode, 0, 0
  10318 };
  10319 
  10320 static xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
  10321   Opcode_rsr_eps2_Slot_inst_encode, 0, 0
  10322 };
  10323 
  10324 static xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
  10325   Opcode_wsr_eps2_Slot_inst_encode, 0, 0
  10326 };
  10327 
  10328 static xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
  10329   Opcode_xsr_eps2_Slot_inst_encode, 0, 0
  10330 };
  10331 
  10332 static xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
  10333   Opcode_rsr_eps3_Slot_inst_encode, 0, 0
  10334 };
  10335 
  10336 static xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
  10337   Opcode_wsr_eps3_Slot_inst_encode, 0, 0
  10338 };
  10339 
  10340 static xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
  10341   Opcode_xsr_eps3_Slot_inst_encode, 0, 0
  10342 };
  10343 
  10344 static xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
  10345   Opcode_rsr_eps4_Slot_inst_encode, 0, 0
  10346 };
  10347 
  10348 static xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
  10349   Opcode_wsr_eps4_Slot_inst_encode, 0, 0
  10350 };
  10351 
  10352 static xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
  10353   Opcode_xsr_eps4_Slot_inst_encode, 0, 0
  10354 };
  10355 
  10356 static xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
  10357   Opcode_rsr_eps5_Slot_inst_encode, 0, 0
  10358 };
  10359 
  10360 static xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
  10361   Opcode_wsr_eps5_Slot_inst_encode, 0, 0
  10362 };
  10363 
  10364 static xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
  10365   Opcode_xsr_eps5_Slot_inst_encode, 0, 0
  10366 };
  10367 
  10368 static xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
  10369   Opcode_rsr_eps6_Slot_inst_encode, 0, 0
  10370 };
  10371 
  10372 static xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
  10373   Opcode_wsr_eps6_Slot_inst_encode, 0, 0
  10374 };
  10375 
  10376 static xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
  10377   Opcode_xsr_eps6_Slot_inst_encode, 0, 0
  10378 };
  10379 
  10380 static xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
  10381   Opcode_rsr_eps7_Slot_inst_encode, 0, 0
  10382 };
  10383 
  10384 static xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
  10385   Opcode_wsr_eps7_Slot_inst_encode, 0, 0
  10386 };
  10387 
  10388 static xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
  10389   Opcode_xsr_eps7_Slot_inst_encode, 0, 0
  10390 };
  10391 
  10392 static xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
  10393   Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0
  10394 };
  10395 
  10396 static xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
  10397   Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0
  10398 };
  10399 
  10400 static xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
  10401   Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0
  10402 };
  10403 
  10404 static xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
  10405   Opcode_rsr_depc_Slot_inst_encode, 0, 0
  10406 };
  10407 
  10408 static xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
  10409   Opcode_wsr_depc_Slot_inst_encode, 0, 0
  10410 };
  10411 
  10412 static xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
  10413   Opcode_xsr_depc_Slot_inst_encode, 0, 0
  10414 };
  10415 
  10416 static xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
  10417   Opcode_rsr_exccause_Slot_inst_encode, 0, 0
  10418 };
  10419 
  10420 static xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
  10421   Opcode_wsr_exccause_Slot_inst_encode, 0, 0
  10422 };
  10423 
  10424 static xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
  10425   Opcode_xsr_exccause_Slot_inst_encode, 0, 0
  10426 };
  10427 
  10428 static xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
  10429   Opcode_rsr_misc0_Slot_inst_encode, 0, 0
  10430 };
  10431 
  10432 static xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
  10433   Opcode_wsr_misc0_Slot_inst_encode, 0, 0
  10434 };
  10435 
  10436 static xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
  10437   Opcode_xsr_misc0_Slot_inst_encode, 0, 0
  10438 };
  10439 
  10440 static xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
  10441   Opcode_rsr_misc1_Slot_inst_encode, 0, 0
  10442 };
  10443 
  10444 static xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
  10445   Opcode_wsr_misc1_Slot_inst_encode, 0, 0
  10446 };
  10447 
  10448 static xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
  10449   Opcode_xsr_misc1_Slot_inst_encode, 0, 0
  10450 };
  10451 
  10452 static xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
  10453   Opcode_rsr_prid_Slot_inst_encode, 0, 0
  10454 };
  10455 
  10456 static xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
  10457   Opcode_rsr_vecbase_Slot_inst_encode, 0, 0
  10458 };
  10459 
  10460 static xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
  10461   Opcode_wsr_vecbase_Slot_inst_encode, 0, 0
  10462 };
  10463 
  10464 static xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
  10465   Opcode_xsr_vecbase_Slot_inst_encode, 0, 0
  10466 };
  10467 
  10468 static xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
  10469   Opcode_mul16u_Slot_inst_encode, 0, 0
  10470 };
  10471 
  10472 static xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
  10473   Opcode_mul16s_Slot_inst_encode, 0, 0
  10474 };
  10475 
  10476 static xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
  10477   Opcode_mull_Slot_inst_encode, 0, 0
  10478 };
  10479 
  10480 static xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
  10481   Opcode_mul_aa_ll_Slot_inst_encode, 0, 0
  10482 };
  10483 
  10484 static xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
  10485   Opcode_mul_aa_hl_Slot_inst_encode, 0, 0
  10486 };
  10487 
  10488 static xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
  10489   Opcode_mul_aa_lh_Slot_inst_encode, 0, 0
  10490 };
  10491 
  10492 static xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
  10493   Opcode_mul_aa_hh_Slot_inst_encode, 0, 0
  10494 };
  10495 
  10496 static xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
  10497   Opcode_umul_aa_ll_Slot_inst_encode, 0, 0
  10498 };
  10499 
  10500 static xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
  10501   Opcode_umul_aa_hl_Slot_inst_encode, 0, 0
  10502 };
  10503 
  10504 static xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
  10505   Opcode_umul_aa_lh_Slot_inst_encode, 0, 0
  10506 };
  10507 
  10508 static xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
  10509   Opcode_umul_aa_hh_Slot_inst_encode, 0, 0
  10510 };
  10511 
  10512 static xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
  10513   Opcode_mul_ad_ll_Slot_inst_encode, 0, 0
  10514 };
  10515 
  10516 static xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
  10517   Opcode_mul_ad_hl_Slot_inst_encode, 0, 0
  10518 };
  10519 
  10520 static xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
  10521   Opcode_mul_ad_lh_Slot_inst_encode, 0, 0
  10522 };
  10523 
  10524 static xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
  10525   Opcode_mul_ad_hh_Slot_inst_encode, 0, 0
  10526 };
  10527 
  10528 static xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
  10529   Opcode_mul_da_ll_Slot_inst_encode, 0, 0
  10530 };
  10531 
  10532 static xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
  10533   Opcode_mul_da_hl_Slot_inst_encode, 0, 0
  10534 };
  10535 
  10536 static xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
  10537   Opcode_mul_da_lh_Slot_inst_encode, 0, 0
  10538 };
  10539 
  10540 static xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
  10541   Opcode_mul_da_hh_Slot_inst_encode, 0, 0
  10542 };
  10543 
  10544 static xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
  10545   Opcode_mul_dd_ll_Slot_inst_encode, 0, 0
  10546 };
  10547 
  10548 static xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
  10549   Opcode_mul_dd_hl_Slot_inst_encode, 0, 0
  10550 };
  10551 
  10552 static xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
  10553   Opcode_mul_dd_lh_Slot_inst_encode, 0, 0
  10554 };
  10555 
  10556 static xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
  10557   Opcode_mul_dd_hh_Slot_inst_encode, 0, 0
  10558 };
  10559 
  10560 static xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
  10561   Opcode_mula_aa_ll_Slot_inst_encode, 0, 0
  10562 };
  10563 
  10564 static xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
  10565   Opcode_mula_aa_hl_Slot_inst_encode, 0, 0
  10566 };
  10567 
  10568 static xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
  10569   Opcode_mula_aa_lh_Slot_inst_encode, 0, 0
  10570 };
  10571 
  10572 static xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
  10573   Opcode_mula_aa_hh_Slot_inst_encode, 0, 0
  10574 };
  10575 
  10576 static xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
  10577   Opcode_muls_aa_ll_Slot_inst_encode, 0, 0
  10578 };
  10579 
  10580 static xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
  10581   Opcode_muls_aa_hl_Slot_inst_encode, 0, 0
  10582 };
  10583 
  10584 static xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
  10585   Opcode_muls_aa_lh_Slot_inst_encode, 0, 0
  10586 };
  10587 
  10588 static xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
  10589   Opcode_muls_aa_hh_Slot_inst_encode, 0, 0
  10590 };
  10591 
  10592 static xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
  10593   Opcode_mula_ad_ll_Slot_inst_encode, 0, 0
  10594 };
  10595 
  10596 static xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
  10597   Opcode_mula_ad_hl_Slot_inst_encode, 0, 0
  10598 };
  10599 
  10600 static xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
  10601   Opcode_mula_ad_lh_Slot_inst_encode, 0, 0
  10602 };
  10603 
  10604 static xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
  10605   Opcode_mula_ad_hh_Slot_inst_encode, 0, 0
  10606 };
  10607 
  10608 static xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
  10609   Opcode_muls_ad_ll_Slot_inst_encode, 0, 0
  10610 };
  10611 
  10612 static xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
  10613   Opcode_muls_ad_hl_Slot_inst_encode, 0, 0
  10614 };
  10615 
  10616 static xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
  10617   Opcode_muls_ad_lh_Slot_inst_encode, 0, 0
  10618 };
  10619 
  10620 static xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
  10621   Opcode_muls_ad_hh_Slot_inst_encode, 0, 0
  10622 };
  10623 
  10624 static xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
  10625   Opcode_mula_da_ll_Slot_inst_encode, 0, 0
  10626 };
  10627 
  10628 static xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
  10629   Opcode_mula_da_hl_Slot_inst_encode, 0, 0
  10630 };
  10631 
  10632 static xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
  10633   Opcode_mula_da_lh_Slot_inst_encode, 0, 0
  10634 };
  10635 
  10636 static xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
  10637   Opcode_mula_da_hh_Slot_inst_encode, 0, 0
  10638 };
  10639 
  10640 static xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
  10641   Opcode_muls_da_ll_Slot_inst_encode, 0, 0
  10642 };
  10643 
  10644 static xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
  10645   Opcode_muls_da_hl_Slot_inst_encode, 0, 0
  10646 };
  10647 
  10648 static xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
  10649   Opcode_muls_da_lh_Slot_inst_encode, 0, 0
  10650 };
  10651 
  10652 static xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
  10653   Opcode_muls_da_hh_Slot_inst_encode, 0, 0
  10654 };
  10655 
  10656 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
  10657   Opcode_mula_dd_ll_Slot_inst_encode, 0, 0
  10658 };
  10659 
  10660 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
  10661   Opcode_mula_dd_hl_Slot_inst_encode, 0, 0
  10662 };
  10663 
  10664 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
  10665   Opcode_mula_dd_lh_Slot_inst_encode, 0, 0
  10666 };
  10667 
  10668 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
  10669   Opcode_mula_dd_hh_Slot_inst_encode, 0, 0
  10670 };
  10671 
  10672 static xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
  10673   Opcode_muls_dd_ll_Slot_inst_encode, 0, 0
  10674 };
  10675 
  10676 static xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
  10677   Opcode_muls_dd_hl_Slot_inst_encode, 0, 0
  10678 };
  10679 
  10680 static xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
  10681   Opcode_muls_dd_lh_Slot_inst_encode, 0, 0
  10682 };
  10683 
  10684 static xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
  10685   Opcode_muls_dd_hh_Slot_inst_encode, 0, 0
  10686 };
  10687 
  10688 static xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
  10689   Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0
  10690 };
  10691 
  10692 static xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
  10693   Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0
  10694 };
  10695 
  10696 static xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
  10697   Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0
  10698 };
  10699 
  10700 static xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
  10701   Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0
  10702 };
  10703 
  10704 static xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
  10705   Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0
  10706 };
  10707 
  10708 static xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
  10709   Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0
  10710 };
  10711 
  10712 static xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
  10713   Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0
  10714 };
  10715 
  10716 static xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
  10717   Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0
  10718 };
  10719 
  10720 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
  10721   Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0
  10722 };
  10723 
  10724 static xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
  10725   Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0
  10726 };
  10727 
  10728 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
  10729   Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0
  10730 };
  10731 
  10732 static xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
  10733   Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0
  10734 };
  10735 
  10736 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
  10737   Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0
  10738 };
  10739 
  10740 static xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
  10741   Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0
  10742 };
  10743 
  10744 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
  10745   Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0
  10746 };
  10747 
  10748 static xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
  10749   Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0
  10750 };
  10751 
  10752 static xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
  10753   Opcode_lddec_Slot_inst_encode, 0, 0
  10754 };
  10755 
  10756 static xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
  10757   Opcode_ldinc_Slot_inst_encode, 0, 0
  10758 };
  10759 
  10760 static xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
  10761   Opcode_rsr_m0_Slot_inst_encode, 0, 0
  10762 };
  10763 
  10764 static xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
  10765   Opcode_wsr_m0_Slot_inst_encode, 0, 0
  10766 };
  10767 
  10768 static xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
  10769   Opcode_xsr_m0_Slot_inst_encode, 0, 0
  10770 };
  10771 
  10772 static xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
  10773   Opcode_rsr_m1_Slot_inst_encode, 0, 0
  10774 };
  10775 
  10776 static xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
  10777   Opcode_wsr_m1_Slot_inst_encode, 0, 0
  10778 };
  10779 
  10780 static xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
  10781   Opcode_xsr_m1_Slot_inst_encode, 0, 0
  10782 };
  10783 
  10784 static xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
  10785   Opcode_rsr_m2_Slot_inst_encode, 0, 0
  10786 };
  10787 
  10788 static xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
  10789   Opcode_wsr_m2_Slot_inst_encode, 0, 0
  10790 };
  10791 
  10792 static xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
  10793   Opcode_xsr_m2_Slot_inst_encode, 0, 0
  10794 };
  10795 
  10796 static xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
  10797   Opcode_rsr_m3_Slot_inst_encode, 0, 0
  10798 };
  10799 
  10800 static xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
  10801   Opcode_wsr_m3_Slot_inst_encode, 0, 0
  10802 };
  10803 
  10804 static xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
  10805   Opcode_xsr_m3_Slot_inst_encode, 0, 0
  10806 };
  10807 
  10808 static xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
  10809   Opcode_rsr_acclo_Slot_inst_encode, 0, 0
  10810 };
  10811 
  10812 static xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
  10813   Opcode_wsr_acclo_Slot_inst_encode, 0, 0
  10814 };
  10815 
  10816 static xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
  10817   Opcode_xsr_acclo_Slot_inst_encode, 0, 0
  10818 };
  10819 
  10820 static xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
  10821   Opcode_rsr_acchi_Slot_inst_encode, 0, 0
  10822 };
  10823 
  10824 static xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
  10825   Opcode_wsr_acchi_Slot_inst_encode, 0, 0
  10826 };
  10827 
  10828 static xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
  10829   Opcode_xsr_acchi_Slot_inst_encode, 0, 0
  10830 };
  10831 
  10832 static xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
  10833   Opcode_rfi_Slot_inst_encode, 0, 0
  10834 };
  10835 
  10836 static xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
  10837   Opcode_waiti_Slot_inst_encode, 0, 0
  10838 };
  10839 
  10840 static xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
  10841   Opcode_rsr_interrupt_Slot_inst_encode, 0, 0
  10842 };
  10843 
  10844 static xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
  10845   Opcode_wsr_intset_Slot_inst_encode, 0, 0
  10846 };
  10847 
  10848 static xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
  10849   Opcode_wsr_intclear_Slot_inst_encode, 0, 0
  10850 };
  10851 
  10852 static xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
  10853   Opcode_rsr_intenable_Slot_inst_encode, 0, 0
  10854 };
  10855 
  10856 static xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
  10857   Opcode_wsr_intenable_Slot_inst_encode, 0, 0
  10858 };
  10859 
  10860 static xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
  10861   Opcode_xsr_intenable_Slot_inst_encode, 0, 0
  10862 };
  10863 
  10864 static xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
  10865   Opcode_break_Slot_inst_encode, 0, 0
  10866 };
  10867 
  10868 static xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
  10869   0, 0, Opcode_break_n_Slot_inst16b_encode
  10870 };
  10871 
  10872 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
  10873   Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0
  10874 };
  10875 
  10876 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
  10877   Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0
  10878 };
  10879 
  10880 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
  10881   Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0
  10882 };
  10883 
  10884 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
  10885   Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0
  10886 };
  10887 
  10888 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
  10889   Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0
  10890 };
  10891 
  10892 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
  10893   Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0
  10894 };
  10895 
  10896 static xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
  10897   Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0
  10898 };
  10899 
  10900 static xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
  10901   Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0
  10902 };
  10903 
  10904 static xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
  10905   Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0
  10906 };
  10907 
  10908 static xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
  10909   Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0
  10910 };
  10911 
  10912 static xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
  10913   Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0
  10914 };
  10915 
  10916 static xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
  10917   Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0
  10918 };
  10919 
  10920 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
  10921   Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0
  10922 };
  10923 
  10924 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
  10925   Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0
  10926 };
  10927 
  10928 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
  10929   Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0
  10930 };
  10931 
  10932 static xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
  10933   Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0
  10934 };
  10935 
  10936 static xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
  10937   Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0
  10938 };
  10939 
  10940 static xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
  10941   Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0
  10942 };
  10943 
  10944 static xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
  10945   Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0
  10946 };
  10947 
  10948 static xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
  10949   Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0
  10950 };
  10951 
  10952 static xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
  10953   Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0
  10954 };
  10955 
  10956 static xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
  10957   Opcode_rsr_debugcause_Slot_inst_encode, 0, 0
  10958 };
  10959 
  10960 static xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
  10961   Opcode_wsr_debugcause_Slot_inst_encode, 0, 0
  10962 };
  10963 
  10964 static xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
  10965   Opcode_xsr_debugcause_Slot_inst_encode, 0, 0
  10966 };
  10967 
  10968 static xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
  10969   Opcode_rsr_icount_Slot_inst_encode, 0, 0
  10970 };
  10971 
  10972 static xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
  10973   Opcode_wsr_icount_Slot_inst_encode, 0, 0
  10974 };
  10975 
  10976 static xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
  10977   Opcode_xsr_icount_Slot_inst_encode, 0, 0
  10978 };
  10979 
  10980 static xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
  10981   Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0
  10982 };
  10983 
  10984 static xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
  10985   Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0
  10986 };
  10987 
  10988 static xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
  10989   Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0
  10990 };
  10991 
  10992 static xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
  10993   Opcode_rsr_ddr_Slot_inst_encode, 0, 0
  10994 };
  10995 
  10996 static xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
  10997   Opcode_wsr_ddr_Slot_inst_encode, 0, 0
  10998 };
  10999 
  11000 static xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
  11001   Opcode_xsr_ddr_Slot_inst_encode, 0, 0
  11002 };
  11003 
  11004 static xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
  11005   Opcode_rfdo_Slot_inst_encode, 0, 0
  11006 };
  11007 
  11008 static xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
  11009   Opcode_rfdd_Slot_inst_encode, 0, 0
  11010 };
  11011 
  11012 static xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
  11013   Opcode_wsr_mmid_Slot_inst_encode, 0, 0
  11014 };
  11015 
  11016 static xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
  11017   Opcode_rsr_ccount_Slot_inst_encode, 0, 0
  11018 };
  11019 
  11020 static xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
  11021   Opcode_wsr_ccount_Slot_inst_encode, 0, 0
  11022 };
  11023 
  11024 static xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
  11025   Opcode_xsr_ccount_Slot_inst_encode, 0, 0
  11026 };
  11027 
  11028 static xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
  11029   Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0
  11030 };
  11031 
  11032 static xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
  11033   Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0
  11034 };
  11035 
  11036 static xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
  11037   Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0
  11038 };
  11039 
  11040 static xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
  11041   Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0
  11042 };
  11043 
  11044 static xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
  11045   Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0
  11046 };
  11047 
  11048 static xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
  11049   Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0
  11050 };
  11051 
  11052 static xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
  11053   Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0
  11054 };
  11055 
  11056 static xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
  11057   Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0
  11058 };
  11059 
  11060 static xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
  11061   Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0
  11062 };
  11063 
  11064 static xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
  11065   Opcode_ipf_Slot_inst_encode, 0, 0
  11066 };
  11067 
  11068 static xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
  11069   Opcode_ihi_Slot_inst_encode, 0, 0
  11070 };
  11071 
  11072 static xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
  11073   Opcode_ipfl_Slot_inst_encode, 0, 0
  11074 };
  11075 
  11076 static xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
  11077   Opcode_ihu_Slot_inst_encode, 0, 0
  11078 };
  11079 
  11080 static xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
  11081   Opcode_iiu_Slot_inst_encode, 0, 0
  11082 };
  11083 
  11084 static xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
  11085   Opcode_iii_Slot_inst_encode, 0, 0
  11086 };
  11087 
  11088 static xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
  11089   Opcode_lict_Slot_inst_encode, 0, 0
  11090 };
  11091 
  11092 static xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
  11093   Opcode_licw_Slot_inst_encode, 0, 0
  11094 };
  11095 
  11096 static xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
  11097   Opcode_sict_Slot_inst_encode, 0, 0
  11098 };
  11099 
  11100 static xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
  11101   Opcode_sicw_Slot_inst_encode, 0, 0
  11102 };
  11103 
  11104 static xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
  11105   Opcode_dhwb_Slot_inst_encode, 0, 0
  11106 };
  11107 
  11108 static xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
  11109   Opcode_dhwbi_Slot_inst_encode, 0, 0
  11110 };
  11111 
  11112 static xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
  11113   Opcode_diwb_Slot_inst_encode, 0, 0
  11114 };
  11115 
  11116 static xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
  11117   Opcode_diwbi_Slot_inst_encode, 0, 0
  11118 };
  11119 
  11120 static xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
  11121   Opcode_dhi_Slot_inst_encode, 0, 0
  11122 };
  11123 
  11124 static xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
  11125   Opcode_dii_Slot_inst_encode, 0, 0
  11126 };
  11127 
  11128 static xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
  11129   Opcode_dpfr_Slot_inst_encode, 0, 0
  11130 };
  11131 
  11132 static xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
  11133   Opcode_dpfw_Slot_inst_encode, 0, 0
  11134 };
  11135 
  11136 static xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
  11137   Opcode_dpfro_Slot_inst_encode, 0, 0
  11138 };
  11139 
  11140 static xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
  11141   Opcode_dpfwo_Slot_inst_encode, 0, 0
  11142 };
  11143 
  11144 static xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
  11145   Opcode_dpfl_Slot_inst_encode, 0, 0
  11146 };
  11147 
  11148 static xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
  11149   Opcode_dhu_Slot_inst_encode, 0, 0
  11150 };
  11151 
  11152 static xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
  11153   Opcode_diu_Slot_inst_encode, 0, 0
  11154 };
  11155 
  11156 static xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
  11157   Opcode_sdct_Slot_inst_encode, 0, 0
  11158 };
  11159 
  11160 static xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
  11161   Opcode_ldct_Slot_inst_encode, 0, 0
  11162 };
  11163 
  11164 static xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
  11165   Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0
  11166 };
  11167 
  11168 static xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
  11169   Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0
  11170 };
  11171 
  11172 static xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
  11173   Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0
  11174 };
  11175 
  11176 static xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
  11177   Opcode_rsr_rasid_Slot_inst_encode, 0, 0
  11178 };
  11179 
  11180 static xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
  11181   Opcode_wsr_rasid_Slot_inst_encode, 0, 0
  11182 };
  11183 
  11184 static xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
  11185   Opcode_xsr_rasid_Slot_inst_encode, 0, 0
  11186 };
  11187 
  11188 static xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
  11189   Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0
  11190 };
  11191 
  11192 static xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
  11193   Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0
  11194 };
  11195 
  11196 static xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
  11197   Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0
  11198 };
  11199 
  11200 static xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
  11201   Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0
  11202 };
  11203 
  11204 static xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
  11205   Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0
  11206 };
  11207 
  11208 static xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
  11209   Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0
  11210 };
  11211 
  11212 static xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
  11213   Opcode_idtlb_Slot_inst_encode, 0, 0
  11214 };
  11215 
  11216 static xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
  11217   Opcode_pdtlb_Slot_inst_encode, 0, 0
  11218 };
  11219 
  11220 static xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
  11221   Opcode_rdtlb0_Slot_inst_encode, 0, 0
  11222 };
  11223 
  11224 static xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
  11225   Opcode_rdtlb1_Slot_inst_encode, 0, 0
  11226 };
  11227 
  11228 static xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
  11229   Opcode_wdtlb_Slot_inst_encode, 0, 0
  11230 };
  11231 
  11232 static xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
  11233   Opcode_iitlb_Slot_inst_encode, 0, 0
  11234 };
  11235 
  11236 static xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
  11237   Opcode_pitlb_Slot_inst_encode, 0, 0
  11238 };
  11239 
  11240 static xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
  11241   Opcode_ritlb0_Slot_inst_encode, 0, 0
  11242 };
  11243 
  11244 static xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
  11245   Opcode_ritlb1_Slot_inst_encode, 0, 0
  11246 };
  11247 
  11248 static xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
  11249   Opcode_witlb_Slot_inst_encode, 0, 0
  11250 };
  11251 
  11252 static xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
  11253   Opcode_ldpte_Slot_inst_encode, 0, 0
  11254 };
  11255 
  11256 static xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
  11257   Opcode_hwwitlba_Slot_inst_encode, 0, 0
  11258 };
  11259 
  11260 static xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
  11261   Opcode_hwwdtlba_Slot_inst_encode, 0, 0
  11262 };
  11263 
  11264 static xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
  11265   Opcode_rsr_cpenable_Slot_inst_encode, 0, 0
  11266 };
  11267 
  11268 static xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
  11269   Opcode_wsr_cpenable_Slot_inst_encode, 0, 0
  11270 };
  11271 
  11272 static xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
  11273   Opcode_xsr_cpenable_Slot_inst_encode, 0, 0
  11274 };
  11275 
  11276 static xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
  11277   Opcode_clamps_Slot_inst_encode, 0, 0
  11278 };
  11279 
  11280 static xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
  11281   Opcode_min_Slot_inst_encode, 0, 0
  11282 };
  11283 
  11284 static xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
  11285   Opcode_max_Slot_inst_encode, 0, 0
  11286 };
  11287 
  11288 static xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
  11289   Opcode_minu_Slot_inst_encode, 0, 0
  11290 };
  11291 
  11292 static xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
  11293   Opcode_maxu_Slot_inst_encode, 0, 0
  11294 };
  11295 
  11296 static xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
  11297   Opcode_nsa_Slot_inst_encode, 0, 0
  11298 };
  11299 
  11300 static xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
  11301   Opcode_nsau_Slot_inst_encode, 0, 0
  11302 };
  11303 
  11304 static xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
  11305   Opcode_sext_Slot_inst_encode, 0, 0
  11306 };
  11307 
  11308 static xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
  11309   Opcode_l32ai_Slot_inst_encode, 0, 0
  11310 };
  11311 
  11312 static xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
  11313   Opcode_s32ri_Slot_inst_encode, 0, 0
  11314 };
  11315 
  11316 static xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
  11317   Opcode_s32c1i_Slot_inst_encode, 0, 0
  11318 };
  11319 
  11320 static xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
  11321   Opcode_rsr_scompare1_Slot_inst_encode, 0, 0
  11322 };
  11323 
  11324 static xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
  11325   Opcode_wsr_scompare1_Slot_inst_encode, 0, 0
  11326 };
  11327 
  11328 static xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
  11329   Opcode_xsr_scompare1_Slot_inst_encode, 0, 0
  11330 };
  11331 
  11332 static xtensa_opcode_encode_fn Opcode_rsr_atomctl_encode_fns[] = {
  11333   Opcode_rsr_atomctl_Slot_inst_encode, 0, 0
  11334 };
  11335 
  11336 static xtensa_opcode_encode_fn Opcode_wsr_atomctl_encode_fns[] = {
  11337   Opcode_wsr_atomctl_Slot_inst_encode, 0, 0
  11338 };
  11339 
  11340 static xtensa_opcode_encode_fn Opcode_xsr_atomctl_encode_fns[] = {
  11341   Opcode_xsr_atomctl_Slot_inst_encode, 0, 0
  11342 };
  11343 
  11344 static xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
  11345   Opcode_quou_Slot_inst_encode, 0, 0
  11346 };
  11347 
  11348 static xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
  11349   Opcode_quos_Slot_inst_encode, 0, 0
  11350 };
  11351 
  11352 static xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
  11353   Opcode_remu_Slot_inst_encode, 0, 0
  11354 };
  11355 
  11356 static xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
  11357   Opcode_rems_Slot_inst_encode, 0, 0
  11358 };
  11359 
  11360 static xtensa_opcode_encode_fn Opcode_rer_encode_fns[] = {
  11361   Opcode_rer_Slot_inst_encode, 0, 0
  11362 };
  11363 
  11364 static xtensa_opcode_encode_fn Opcode_wer_encode_fns[] = {
  11365   Opcode_wer_Slot_inst_encode, 0, 0
  11366 };
  11367 
  11368 static xtensa_opcode_encode_fn Opcode_rur_expstate_encode_fns[] = {
  11369   Opcode_rur_expstate_Slot_inst_encode, 0, 0
  11370 };
  11371 
  11372 static xtensa_opcode_encode_fn Opcode_wur_expstate_encode_fns[] = {
  11373   Opcode_wur_expstate_Slot_inst_encode, 0, 0
  11374 };
  11375 
  11376 static xtensa_opcode_encode_fn Opcode_read_impwire_encode_fns[] = {
  11377   Opcode_read_impwire_Slot_inst_encode, 0, 0
  11378 };
  11379 
  11380 static xtensa_opcode_encode_fn Opcode_setb_expstate_encode_fns[] = {
  11381   Opcode_setb_expstate_Slot_inst_encode, 0, 0
  11382 };
  11383 
  11384 static xtensa_opcode_encode_fn Opcode_clrb_expstate_encode_fns[] = {
  11385   Opcode_clrb_expstate_Slot_inst_encode, 0, 0
  11386 };
  11387 
  11388 static xtensa_opcode_encode_fn Opcode_wrmsk_expstate_encode_fns[] = {
  11389   Opcode_wrmsk_expstate_Slot_inst_encode, 0, 0
  11390 };
  11391 
  11392 
  11393 /* Opcode table.  */
  11394 
  11395 static xtensa_opcode_internal opcodes[] = {
  11396   { "excw", ICLASS_xt_iclass_excw,
  11397     0,
  11398     Opcode_excw_encode_fns, 0, 0 },
  11399   { "rfe", ICLASS_xt_iclass_rfe,
  11400     XTENSA_OPCODE_IS_JUMP,
  11401     Opcode_rfe_encode_fns, 0, 0 },
  11402   { "rfde", ICLASS_xt_iclass_rfde,
  11403     XTENSA_OPCODE_IS_JUMP,
  11404     Opcode_rfde_encode_fns, 0, 0 },
  11405   { "syscall", ICLASS_xt_iclass_syscall,
  11406     0,
  11407     Opcode_syscall_encode_fns, 0, 0 },
  11408   { "simcall", ICLASS_xt_iclass_simcall,
  11409     0,
  11410     Opcode_simcall_encode_fns, 0, 0 },
  11411   { "call12", ICLASS_xt_iclass_call12,
  11412     XTENSA_OPCODE_IS_CALL,
  11413     Opcode_call12_encode_fns, 0, 0 },
  11414   { "call8", ICLASS_xt_iclass_call8,
  11415     XTENSA_OPCODE_IS_CALL,
  11416     Opcode_call8_encode_fns, 0, 0 },
  11417   { "call4", ICLASS_xt_iclass_call4,
  11418     XTENSA_OPCODE_IS_CALL,
  11419     Opcode_call4_encode_fns, 0, 0 },
  11420   { "callx12", ICLASS_xt_iclass_callx12,
  11421     XTENSA_OPCODE_IS_CALL,
  11422     Opcode_callx12_encode_fns, 0, 0 },
  11423   { "callx8", ICLASS_xt_iclass_callx8,
  11424     XTENSA_OPCODE_IS_CALL,
  11425     Opcode_callx8_encode_fns, 0, 0 },
  11426   { "callx4", ICLASS_xt_iclass_callx4,
  11427     XTENSA_OPCODE_IS_CALL,
  11428     Opcode_callx4_encode_fns, 0, 0 },
  11429   { "entry", ICLASS_xt_iclass_entry,
  11430     0,
  11431     Opcode_entry_encode_fns, 0, 0 },
  11432   { "movsp", ICLASS_xt_iclass_movsp,
  11433     0,
  11434     Opcode_movsp_encode_fns, 0, 0 },
  11435   { "rotw", ICLASS_xt_iclass_rotw,
  11436     0,
  11437     Opcode_rotw_encode_fns, 0, 0 },
  11438   { "retw", ICLASS_xt_iclass_retw,
  11439     XTENSA_OPCODE_IS_JUMP,
  11440     Opcode_retw_encode_fns, 0, 0 },
  11441   { "retw.n", ICLASS_xt_iclass_retw,
  11442     XTENSA_OPCODE_IS_JUMP,
  11443     Opcode_retw_n_encode_fns, 0, 0 },
  11444   { "rfwo", ICLASS_xt_iclass_rfwou,
  11445     XTENSA_OPCODE_IS_JUMP,
  11446     Opcode_rfwo_encode_fns, 0, 0 },
  11447   { "rfwu", ICLASS_xt_iclass_rfwou,
  11448     XTENSA_OPCODE_IS_JUMP,
  11449     Opcode_rfwu_encode_fns, 0, 0 },
  11450   { "l32e", ICLASS_xt_iclass_l32e,
  11451     0,
  11452     Opcode_l32e_encode_fns, 0, 0 },
  11453   { "s32e", ICLASS_xt_iclass_s32e,
  11454     0,
  11455     Opcode_s32e_encode_fns, 0, 0 },
  11456   { "rsr.windowbase", ICLASS_xt_iclass_rsr_windowbase,
  11457     0,
  11458     Opcode_rsr_windowbase_encode_fns, 0, 0 },
  11459   { "wsr.windowbase", ICLASS_xt_iclass_wsr_windowbase,
  11460     0,
  11461     Opcode_wsr_windowbase_encode_fns, 0, 0 },
  11462   { "xsr.windowbase", ICLASS_xt_iclass_xsr_windowbase,
  11463     0,
  11464     Opcode_xsr_windowbase_encode_fns, 0, 0 },
  11465   { "rsr.windowstart", ICLASS_xt_iclass_rsr_windowstart,
  11466     0,
  11467     Opcode_rsr_windowstart_encode_fns, 0, 0 },
  11468   { "wsr.windowstart", ICLASS_xt_iclass_wsr_windowstart,
  11469     0,
  11470     Opcode_wsr_windowstart_encode_fns, 0, 0 },
  11471   { "xsr.windowstart", ICLASS_xt_iclass_xsr_windowstart,
  11472     0,
  11473     Opcode_xsr_windowstart_encode_fns, 0, 0 },
  11474   { "add.n", ICLASS_xt_iclass_add_n,
  11475     0,
  11476     Opcode_add_n_encode_fns, 0, 0 },
  11477   { "addi.n", ICLASS_xt_iclass_addi_n,
  11478     0,
  11479     Opcode_addi_n_encode_fns, 0, 0 },
  11480   { "beqz.n", ICLASS_xt_iclass_bz6,
  11481     XTENSA_OPCODE_IS_BRANCH,
  11482     Opcode_beqz_n_encode_fns, 0, 0 },
  11483   { "bnez.n", ICLASS_xt_iclass_bz6,
  11484     XTENSA_OPCODE_IS_BRANCH,
  11485     Opcode_bnez_n_encode_fns, 0, 0 },
  11486   { "ill.n", ICLASS_xt_iclass_ill_n,
  11487     0,
  11488     Opcode_ill_n_encode_fns, 0, 0 },
  11489   { "l32i.n", ICLASS_xt_iclass_loadi4,
  11490     0,
  11491     Opcode_l32i_n_encode_fns, 0, 0 },
  11492   { "mov.n", ICLASS_xt_iclass_mov_n,
  11493     0,
  11494     Opcode_mov_n_encode_fns, 0, 0 },
  11495   { "movi.n", ICLASS_xt_iclass_movi_n,
  11496     0,
  11497     Opcode_movi_n_encode_fns, 0, 0 },
  11498   { "nop.n", ICLASS_xt_iclass_nopn,
  11499     0,
  11500     Opcode_nop_n_encode_fns, 0, 0 },
  11501   { "ret.n", ICLASS_xt_iclass_retn,
  11502     XTENSA_OPCODE_IS_JUMP,
  11503     Opcode_ret_n_encode_fns, 0, 0 },
  11504   { "s32i.n", ICLASS_xt_iclass_storei4,
  11505     0,
  11506     Opcode_s32i_n_encode_fns, 0, 0 },
  11507   { "rur.threadptr", ICLASS_rur_threadptr,
  11508     0,
  11509     Opcode_rur_threadptr_encode_fns, 0, 0 },
  11510   { "wur.threadptr", ICLASS_wur_threadptr,
  11511     0,
  11512     Opcode_wur_threadptr_encode_fns, 0, 0 },
  11513   { "addi", ICLASS_xt_iclass_addi,
  11514     0,
  11515     Opcode_addi_encode_fns, 0, 0 },
  11516   { "addmi", ICLASS_xt_iclass_addmi,
  11517     0,
  11518     Opcode_addmi_encode_fns, 0, 0 },
  11519   { "add", ICLASS_xt_iclass_addsub,
  11520     0,
  11521     Opcode_add_encode_fns, 0, 0 },
  11522   { "sub", ICLASS_xt_iclass_addsub,
  11523     0,
  11524     Opcode_sub_encode_fns, 0, 0 },
  11525   { "addx2", ICLASS_xt_iclass_addsub,
  11526     0,
  11527     Opcode_addx2_encode_fns, 0, 0 },
  11528   { "addx4", ICLASS_xt_iclass_addsub,
  11529     0,
  11530     Opcode_addx4_encode_fns, 0, 0 },
  11531   { "addx8", ICLASS_xt_iclass_addsub,
  11532     0,
  11533     Opcode_addx8_encode_fns, 0, 0 },
  11534   { "subx2", ICLASS_xt_iclass_addsub,
  11535     0,
  11536     Opcode_subx2_encode_fns, 0, 0 },
  11537   { "subx4", ICLASS_xt_iclass_addsub,
  11538     0,
  11539     Opcode_subx4_encode_fns, 0, 0 },
  11540   { "subx8", ICLASS_xt_iclass_addsub,
  11541     0,
  11542     Opcode_subx8_encode_fns, 0, 0 },
  11543   { "and", ICLASS_xt_iclass_bit,
  11544     0,
  11545     Opcode_and_encode_fns, 0, 0 },
  11546   { "or", ICLASS_xt_iclass_bit,
  11547     0,
  11548     Opcode_or_encode_fns, 0, 0 },
  11549   { "xor", ICLASS_xt_iclass_bit,
  11550     0,
  11551     Opcode_xor_encode_fns, 0, 0 },
  11552   { "beqi", ICLASS_xt_iclass_bsi8,
  11553     XTENSA_OPCODE_IS_BRANCH,
  11554     Opcode_beqi_encode_fns, 0, 0 },
  11555   { "bnei", ICLASS_xt_iclass_bsi8,
  11556     XTENSA_OPCODE_IS_BRANCH,
  11557     Opcode_bnei_encode_fns, 0, 0 },
  11558   { "bgei", ICLASS_xt_iclass_bsi8,
  11559     XTENSA_OPCODE_IS_BRANCH,
  11560     Opcode_bgei_encode_fns, 0, 0 },
  11561   { "blti", ICLASS_xt_iclass_bsi8,
  11562     XTENSA_OPCODE_IS_BRANCH,
  11563     Opcode_blti_encode_fns, 0, 0 },
  11564   { "bbci", ICLASS_xt_iclass_bsi8b,
  11565     XTENSA_OPCODE_IS_BRANCH,
  11566     Opcode_bbci_encode_fns, 0, 0 },
  11567   { "bbsi", ICLASS_xt_iclass_bsi8b,
  11568     XTENSA_OPCODE_IS_BRANCH,
  11569     Opcode_bbsi_encode_fns, 0, 0 },
  11570   { "bgeui", ICLASS_xt_iclass_bsi8u,
  11571     XTENSA_OPCODE_IS_BRANCH,
  11572     Opcode_bgeui_encode_fns, 0, 0 },
  11573   { "bltui", ICLASS_xt_iclass_bsi8u,
  11574     XTENSA_OPCODE_IS_BRANCH,
  11575     Opcode_bltui_encode_fns, 0, 0 },
  11576   { "beq", ICLASS_xt_iclass_bst8,
  11577     XTENSA_OPCODE_IS_BRANCH,
  11578     Opcode_beq_encode_fns, 0, 0 },
  11579   { "bne", ICLASS_xt_iclass_bst8,
  11580     XTENSA_OPCODE_IS_BRANCH,
  11581     Opcode_bne_encode_fns, 0, 0 },
  11582   { "bge", ICLASS_xt_iclass_bst8,
  11583     XTENSA_OPCODE_IS_BRANCH,
  11584     Opcode_bge_encode_fns, 0, 0 },
  11585   { "blt", ICLASS_xt_iclass_bst8,
  11586     XTENSA_OPCODE_IS_BRANCH,
  11587     Opcode_blt_encode_fns, 0, 0 },
  11588   { "bgeu", ICLASS_xt_iclass_bst8,
  11589     XTENSA_OPCODE_IS_BRANCH,
  11590     Opcode_bgeu_encode_fns, 0, 0 },
  11591   { "bltu", ICLASS_xt_iclass_bst8,
  11592     XTENSA_OPCODE_IS_BRANCH,
  11593     Opcode_bltu_encode_fns, 0, 0 },
  11594   { "bany", ICLASS_xt_iclass_bst8,
  11595     XTENSA_OPCODE_IS_BRANCH,
  11596     Opcode_bany_encode_fns, 0, 0 },
  11597   { "bnone", ICLASS_xt_iclass_bst8,
  11598     XTENSA_OPCODE_IS_BRANCH,
  11599     Opcode_bnone_encode_fns, 0, 0 },
  11600   { "ball", ICLASS_xt_iclass_bst8,
  11601     XTENSA_OPCODE_IS_BRANCH,
  11602     Opcode_ball_encode_fns, 0, 0 },
  11603   { "bnall", ICLASS_xt_iclass_bst8,
  11604     XTENSA_OPCODE_IS_BRANCH,
  11605     Opcode_bnall_encode_fns, 0, 0 },
  11606   { "bbc", ICLASS_xt_iclass_bst8,
  11607     XTENSA_OPCODE_IS_BRANCH,
  11608     Opcode_bbc_encode_fns, 0, 0 },
  11609   { "bbs", ICLASS_xt_iclass_bst8,
  11610     XTENSA_OPCODE_IS_BRANCH,
  11611     Opcode_bbs_encode_fns, 0, 0 },
  11612   { "beqz", ICLASS_xt_iclass_bsz12,
  11613     XTENSA_OPCODE_IS_BRANCH,
  11614     Opcode_beqz_encode_fns, 0, 0 },
  11615   { "bnez", ICLASS_xt_iclass_bsz12,
  11616     XTENSA_OPCODE_IS_BRANCH,
  11617     Opcode_bnez_encode_fns, 0, 0 },
  11618   { "bgez", ICLASS_xt_iclass_bsz12,
  11619     XTENSA_OPCODE_IS_BRANCH,
  11620     Opcode_bgez_encode_fns, 0, 0 },
  11621   { "bltz", ICLASS_xt_iclass_bsz12,
  11622     XTENSA_OPCODE_IS_BRANCH,
  11623     Opcode_bltz_encode_fns, 0, 0 },
  11624   { "call0", ICLASS_xt_iclass_call0,
  11625     XTENSA_OPCODE_IS_CALL,
  11626     Opcode_call0_encode_fns, 0, 0 },
  11627   { "callx0", ICLASS_xt_iclass_callx0,
  11628     XTENSA_OPCODE_IS_CALL,
  11629     Opcode_callx0_encode_fns, 0, 0 },
  11630   { "extui", ICLASS_xt_iclass_exti,
  11631     0,
  11632     Opcode_extui_encode_fns, 0, 0 },
  11633   { "ill", ICLASS_xt_iclass_ill,
  11634     0,
  11635     Opcode_ill_encode_fns, 0, 0 },
  11636   { "j", ICLASS_xt_iclass_jump,
  11637     XTENSA_OPCODE_IS_JUMP,
  11638     Opcode_j_encode_fns, 0, 0 },
  11639   { "jx", ICLASS_xt_iclass_jumpx,
  11640     XTENSA_OPCODE_IS_JUMP,
  11641     Opcode_jx_encode_fns, 0, 0 },
  11642   { "l16ui", ICLASS_xt_iclass_l16ui,
  11643     0,
  11644     Opcode_l16ui_encode_fns, 0, 0 },
  11645   { "l16si", ICLASS_xt_iclass_l16si,
  11646     0,
  11647     Opcode_l16si_encode_fns, 0, 0 },
  11648   { "l32i", ICLASS_xt_iclass_l32i,
  11649     0,
  11650     Opcode_l32i_encode_fns, 0, 0 },
  11651   { "l32r", ICLASS_xt_iclass_l32r,
  11652     0,
  11653     Opcode_l32r_encode_fns, 0, 0 },
  11654   { "l8ui", ICLASS_xt_iclass_l8i,
  11655     0,
  11656     Opcode_l8ui_encode_fns, 0, 0 },
  11657   { "loop", ICLASS_xt_iclass_loop,
  11658     XTENSA_OPCODE_IS_LOOP,
  11659     Opcode_loop_encode_fns, 0, 0 },
  11660   { "loopnez", ICLASS_xt_iclass_loopz,
  11661     XTENSA_OPCODE_IS_LOOP,
  11662     Opcode_loopnez_encode_fns, 0, 0 },
  11663   { "loopgtz", ICLASS_xt_iclass_loopz,
  11664     XTENSA_OPCODE_IS_LOOP,
  11665     Opcode_loopgtz_encode_fns, 0, 0 },
  11666   { "movi", ICLASS_xt_iclass_movi,
  11667     0,
  11668     Opcode_movi_encode_fns, 0, 0 },
  11669   { "moveqz", ICLASS_xt_iclass_movz,
  11670     0,
  11671     Opcode_moveqz_encode_fns, 0, 0 },
  11672   { "movnez", ICLASS_xt_iclass_movz,
  11673     0,
  11674     Opcode_movnez_encode_fns, 0, 0 },
  11675   { "movltz", ICLASS_xt_iclass_movz,
  11676     0,
  11677     Opcode_movltz_encode_fns, 0, 0 },
  11678   { "movgez", ICLASS_xt_iclass_movz,
  11679     0,
  11680     Opcode_movgez_encode_fns, 0, 0 },
  11681   { "neg", ICLASS_xt_iclass_neg,
  11682     0,
  11683     Opcode_neg_encode_fns, 0, 0 },
  11684   { "abs", ICLASS_xt_iclass_neg,
  11685     0,
  11686     Opcode_abs_encode_fns, 0, 0 },
  11687   { "nop", ICLASS_xt_iclass_nop,
  11688     0,
  11689     Opcode_nop_encode_fns, 0, 0 },
  11690   { "ret", ICLASS_xt_iclass_return,
  11691     XTENSA_OPCODE_IS_JUMP,
  11692     Opcode_ret_encode_fns, 0, 0 },
  11693   { "s16i", ICLASS_xt_iclass_s16i,
  11694     0,
  11695     Opcode_s16i_encode_fns, 0, 0 },
  11696   { "s32i", ICLASS_xt_iclass_s32i,
  11697     0,
  11698     Opcode_s32i_encode_fns, 0, 0 },
  11699   { "s8i", ICLASS_xt_iclass_s8i,
  11700     0,
  11701     Opcode_s8i_encode_fns, 0, 0 },
  11702   { "ssr", ICLASS_xt_iclass_sar,
  11703     0,
  11704     Opcode_ssr_encode_fns, 0, 0 },
  11705   { "ssl", ICLASS_xt_iclass_sar,
  11706     0,
  11707     Opcode_ssl_encode_fns, 0, 0 },
  11708   { "ssa8l", ICLASS_xt_iclass_sar,
  11709     0,
  11710     Opcode_ssa8l_encode_fns, 0, 0 },
  11711   { "ssa8b", ICLASS_xt_iclass_sar,
  11712     0,
  11713     Opcode_ssa8b_encode_fns, 0, 0 },
  11714   { "ssai", ICLASS_xt_iclass_sari,
  11715     0,
  11716     Opcode_ssai_encode_fns, 0, 0 },
  11717   { "sll", ICLASS_xt_iclass_shifts,
  11718     0,
  11719     Opcode_sll_encode_fns, 0, 0 },
  11720   { "src", ICLASS_xt_iclass_shiftst,
  11721     0,
  11722     Opcode_src_encode_fns, 0, 0 },
  11723   { "srl", ICLASS_xt_iclass_shiftt,
  11724     0,
  11725     Opcode_srl_encode_fns, 0, 0 },
  11726   { "sra", ICLASS_xt_iclass_shiftt,
  11727     0,
  11728     Opcode_sra_encode_fns, 0, 0 },
  11729   { "slli", ICLASS_xt_iclass_slli,
  11730     0,
  11731     Opcode_slli_encode_fns, 0, 0 },
  11732   { "srai", ICLASS_xt_iclass_srai,
  11733     0,
  11734     Opcode_srai_encode_fns, 0, 0 },
  11735   { "srli", ICLASS_xt_iclass_srli,
  11736     0,
  11737     Opcode_srli_encode_fns, 0, 0 },
  11738   { "memw", ICLASS_xt_iclass_memw,
  11739     0,
  11740     Opcode_memw_encode_fns, 0, 0 },
  11741   { "extw", ICLASS_xt_iclass_extw,
  11742     0,
  11743     Opcode_extw_encode_fns, 0, 0 },
  11744   { "isync", ICLASS_xt_iclass_isync,
  11745     0,
  11746     Opcode_isync_encode_fns, 0, 0 },
  11747   { "rsync", ICLASS_xt_iclass_sync,
  11748     0,
  11749     Opcode_rsync_encode_fns, 0, 0 },
  11750   { "esync", ICLASS_xt_iclass_sync,
  11751     0,
  11752     Opcode_esync_encode_fns, 0, 0 },
  11753   { "dsync", ICLASS_xt_iclass_sync,
  11754     0,
  11755     Opcode_dsync_encode_fns, 0, 0 },
  11756   { "rsil", ICLASS_xt_iclass_rsil,
  11757     0,
  11758     Opcode_rsil_encode_fns, 0, 0 },
  11759   { "rsr.lend", ICLASS_xt_iclass_rsr_lend,
  11760     0,
  11761     Opcode_rsr_lend_encode_fns, 0, 0 },
  11762   { "wsr.lend", ICLASS_xt_iclass_wsr_lend,
  11763     0,
  11764     Opcode_wsr_lend_encode_fns, 0, 0 },
  11765   { "xsr.lend", ICLASS_xt_iclass_xsr_lend,
  11766     0,
  11767     Opcode_xsr_lend_encode_fns, 0, 0 },
  11768   { "rsr.lcount", ICLASS_xt_iclass_rsr_lcount,
  11769     0,
  11770     Opcode_rsr_lcount_encode_fns, 0, 0 },
  11771   { "wsr.lcount", ICLASS_xt_iclass_wsr_lcount,
  11772     0,
  11773     Opcode_wsr_lcount_encode_fns, 0, 0 },
  11774   { "xsr.lcount", ICLASS_xt_iclass_xsr_lcount,
  11775     0,
  11776     Opcode_xsr_lcount_encode_fns, 0, 0 },
  11777   { "rsr.lbeg", ICLASS_xt_iclass_rsr_lbeg,
  11778     0,
  11779     Opcode_rsr_lbeg_encode_fns, 0, 0 },
  11780   { "wsr.lbeg", ICLASS_xt_iclass_wsr_lbeg,
  11781     0,
  11782     Opcode_wsr_lbeg_encode_fns, 0, 0 },
  11783   { "xsr.lbeg", ICLASS_xt_iclass_xsr_lbeg,
  11784     0,
  11785     Opcode_xsr_lbeg_encode_fns, 0, 0 },
  11786   { "rsr.sar", ICLASS_xt_iclass_rsr_sar,
  11787     0,
  11788     Opcode_rsr_sar_encode_fns, 0, 0 },
  11789   { "wsr.sar", ICLASS_xt_iclass_wsr_sar,
  11790     0,
  11791     Opcode_wsr_sar_encode_fns, 0, 0 },
  11792   { "xsr.sar", ICLASS_xt_iclass_xsr_sar,
  11793     0,
  11794     Opcode_xsr_sar_encode_fns, 0, 0 },
  11795   { "rsr.litbase", ICLASS_xt_iclass_rsr_litbase,
  11796     0,
  11797     Opcode_rsr_litbase_encode_fns, 0, 0 },
  11798   { "wsr.litbase", ICLASS_xt_iclass_wsr_litbase,
  11799     0,
  11800     Opcode_wsr_litbase_encode_fns, 0, 0 },
  11801   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
  11802     0,
  11803     Opcode_xsr_litbase_encode_fns, 0, 0 },
  11804   { "rsr.176", ICLASS_xt_iclass_rsr_176,
  11805     0,
  11806     Opcode_rsr_176_encode_fns, 0, 0 },
  11807   { "wsr.176", ICLASS_xt_iclass_wsr_176,
  11808     0,
  11809     Opcode_wsr_176_encode_fns, 0, 0 },
  11810   { "rsr.208", ICLASS_xt_iclass_rsr_208,
  11811     0,
  11812     Opcode_rsr_208_encode_fns, 0, 0 },
  11813   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
  11814     0,
  11815     Opcode_rsr_ps_encode_fns, 0, 0 },
  11816   { "wsr.ps", ICLASS_xt_iclass_wsr_ps,
  11817     0,
  11818     Opcode_wsr_ps_encode_fns, 0, 0 },
  11819   { "xsr.ps", ICLASS_xt_iclass_xsr_ps,
  11820     0,
  11821     Opcode_xsr_ps_encode_fns, 0, 0 },
  11822   { "rsr.epc1", ICLASS_xt_iclass_rsr_epc1,
  11823     0,
  11824     Opcode_rsr_epc1_encode_fns, 0, 0 },
  11825   { "wsr.epc1", ICLASS_xt_iclass_wsr_epc1,
  11826     0,
  11827     Opcode_wsr_epc1_encode_fns, 0, 0 },
  11828   { "xsr.epc1", ICLASS_xt_iclass_xsr_epc1,
  11829     0,
  11830     Opcode_xsr_epc1_encode_fns, 0, 0 },
  11831   { "rsr.excsave1", ICLASS_xt_iclass_rsr_excsave1,
  11832     0,
  11833     Opcode_rsr_excsave1_encode_fns, 0, 0 },
  11834   { "wsr.excsave1", ICLASS_xt_iclass_wsr_excsave1,
  11835     0,
  11836     Opcode_wsr_excsave1_encode_fns, 0, 0 },
  11837   { "xsr.excsave1", ICLASS_xt_iclass_xsr_excsave1,
  11838     0,
  11839     Opcode_xsr_excsave1_encode_fns, 0, 0 },
  11840   { "rsr.epc2", ICLASS_xt_iclass_rsr_epc2,
  11841     0,
  11842     Opcode_rsr_epc2_encode_fns, 0, 0 },
  11843   { "wsr.epc2", ICLASS_xt_iclass_wsr_epc2,
  11844     0,
  11845     Opcode_wsr_epc2_encode_fns, 0, 0 },
  11846   { "xsr.epc2", ICLASS_xt_iclass_xsr_epc2,
  11847     0,
  11848     Opcode_xsr_epc2_encode_fns, 0, 0 },
  11849   { "rsr.excsave2", ICLASS_xt_iclass_rsr_excsave2,
  11850     0,
  11851     Opcode_rsr_excsave2_encode_fns, 0, 0 },
  11852   { "wsr.excsave2", ICLASS_xt_iclass_wsr_excsave2,
  11853     0,
  11854     Opcode_wsr_excsave2_encode_fns, 0, 0 },
  11855   { "xsr.excsave2", ICLASS_xt_iclass_xsr_excsave2,
  11856     0,
  11857     Opcode_xsr_excsave2_encode_fns, 0, 0 },
  11858   { "rsr.epc3", ICLASS_xt_iclass_rsr_epc3,
  11859     0,
  11860     Opcode_rsr_epc3_encode_fns, 0, 0 },
  11861   { "wsr.epc3", ICLASS_xt_iclass_wsr_epc3,
  11862     0,
  11863     Opcode_wsr_epc3_encode_fns, 0, 0 },
  11864   { "xsr.epc3", ICLASS_xt_iclass_xsr_epc3,
  11865     0,
  11866     Opcode_xsr_epc3_encode_fns, 0, 0 },
  11867   { "rsr.excsave3", ICLASS_xt_iclass_rsr_excsave3,
  11868     0,
  11869     Opcode_rsr_excsave3_encode_fns, 0, 0 },
  11870   { "wsr.excsave3", ICLASS_xt_iclass_wsr_excsave3,
  11871     0,
  11872     Opcode_wsr_excsave3_encode_fns, 0, 0 },
  11873   { "xsr.excsave3", ICLASS_xt_iclass_xsr_excsave3,
  11874     0,
  11875     Opcode_xsr_excsave3_encode_fns, 0, 0 },
  11876   { "rsr.epc4", ICLASS_xt_iclass_rsr_epc4,
  11877     0,
  11878     Opcode_rsr_epc4_encode_fns, 0, 0 },
  11879   { "wsr.epc4", ICLASS_xt_iclass_wsr_epc4,
  11880     0,
  11881     Opcode_wsr_epc4_encode_fns, 0, 0 },
  11882   { "xsr.epc4", ICLASS_xt_iclass_xsr_epc4,
  11883     0,
  11884     Opcode_xsr_epc4_encode_fns, 0, 0 },
  11885   { "rsr.excsave4", ICLASS_xt_iclass_rsr_excsave4,
  11886     0,
  11887     Opcode_rsr_excsave4_encode_fns, 0, 0 },
  11888   { "wsr.excsave4", ICLASS_xt_iclass_wsr_excsave4,
  11889     0,
  11890     Opcode_wsr_excsave4_encode_fns, 0, 0 },
  11891   { "xsr.excsave4", ICLASS_xt_iclass_xsr_excsave4,
  11892     0,
  11893     Opcode_xsr_excsave4_encode_fns, 0, 0 },
  11894   { "rsr.epc5", ICLASS_xt_iclass_rsr_epc5,
  11895     0,
  11896     Opcode_rsr_epc5_encode_fns, 0, 0 },
  11897   { "wsr.epc5", ICLASS_xt_iclass_wsr_epc5,
  11898     0,
  11899     Opcode_wsr_epc5_encode_fns, 0, 0 },
  11900   { "xsr.epc5", ICLASS_xt_iclass_xsr_epc5,
  11901     0,
  11902     Opcode_xsr_epc5_encode_fns, 0, 0 },
  11903   { "rsr.excsave5", ICLASS_xt_iclass_rsr_excsave5,
  11904     0,
  11905     Opcode_rsr_excsave5_encode_fns, 0, 0 },
  11906   { "wsr.excsave5", ICLASS_xt_iclass_wsr_excsave5,
  11907     0,
  11908     Opcode_wsr_excsave5_encode_fns, 0, 0 },
  11909   { "xsr.excsave5", ICLASS_xt_iclass_xsr_excsave5,
  11910     0,
  11911     Opcode_xsr_excsave5_encode_fns, 0, 0 },
  11912   { "rsr.epc6", ICLASS_xt_iclass_rsr_epc6,
  11913     0,
  11914     Opcode_rsr_epc6_encode_fns, 0, 0 },
  11915   { "wsr.epc6", ICLASS_xt_iclass_wsr_epc6,
  11916     0,
  11917     Opcode_wsr_epc6_encode_fns, 0, 0 },
  11918   { "xsr.epc6", ICLASS_xt_iclass_xsr_epc6,
  11919     0,
  11920     Opcode_xsr_epc6_encode_fns, 0, 0 },
  11921   { "rsr.excsave6", ICLASS_xt_iclass_rsr_excsave6,
  11922     0,
  11923     Opcode_rsr_excsave6_encode_fns, 0, 0 },
  11924   { "wsr.excsave6", ICLASS_xt_iclass_wsr_excsave6,
  11925     0,
  11926     Opcode_wsr_excsave6_encode_fns, 0, 0 },
  11927   { "xsr.excsave6", ICLASS_xt_iclass_xsr_excsave6,
  11928     0,
  11929     Opcode_xsr_excsave6_encode_fns, 0, 0 },
  11930   { "rsr.epc7", ICLASS_xt_iclass_rsr_epc7,
  11931     0,
  11932     Opcode_rsr_epc7_encode_fns, 0, 0 },
  11933   { "wsr.epc7", ICLASS_xt_iclass_wsr_epc7,
  11934     0,
  11935     Opcode_wsr_epc7_encode_fns, 0, 0 },
  11936   { "xsr.epc7", ICLASS_xt_iclass_xsr_epc7,
  11937     0,
  11938     Opcode_xsr_epc7_encode_fns, 0, 0 },
  11939   { "rsr.excsave7", ICLASS_xt_iclass_rsr_excsave7,
  11940     0,
  11941     Opcode_rsr_excsave7_encode_fns, 0, 0 },
  11942   { "wsr.excsave7", ICLASS_xt_iclass_wsr_excsave7,
  11943     0,
  11944     Opcode_wsr_excsave7_encode_fns, 0, 0 },
  11945   { "xsr.excsave7", ICLASS_xt_iclass_xsr_excsave7,
  11946     0,
  11947     Opcode_xsr_excsave7_encode_fns, 0, 0 },
  11948   { "rsr.eps2", ICLASS_xt_iclass_rsr_eps2,
  11949     0,
  11950     Opcode_rsr_eps2_encode_fns, 0, 0 },
  11951   { "wsr.eps2", ICLASS_xt_iclass_wsr_eps2,
  11952     0,
  11953     Opcode_wsr_eps2_encode_fns, 0, 0 },
  11954   { "xsr.eps2", ICLASS_xt_iclass_xsr_eps2,
  11955     0,
  11956     Opcode_xsr_eps2_encode_fns, 0, 0 },
  11957   { "rsr.eps3", ICLASS_xt_iclass_rsr_eps3,
  11958     0,
  11959     Opcode_rsr_eps3_encode_fns, 0, 0 },
  11960   { "wsr.eps3", ICLASS_xt_iclass_wsr_eps3,
  11961     0,
  11962     Opcode_wsr_eps3_encode_fns, 0, 0 },
  11963   { "xsr.eps3", ICLASS_xt_iclass_xsr_eps3,
  11964     0,
  11965     Opcode_xsr_eps3_encode_fns, 0, 0 },
  11966   { "rsr.eps4", ICLASS_xt_iclass_rsr_eps4,
  11967     0,
  11968     Opcode_rsr_eps4_encode_fns, 0, 0 },
  11969   { "wsr.eps4", ICLASS_xt_iclass_wsr_eps4,
  11970     0,
  11971     Opcode_wsr_eps4_encode_fns, 0, 0 },
  11972   { "xsr.eps4", ICLASS_xt_iclass_xsr_eps4,
  11973     0,
  11974     Opcode_xsr_eps4_encode_fns, 0, 0 },
  11975   { "rsr.eps5", ICLASS_xt_iclass_rsr_eps5,
  11976     0,
  11977     Opcode_rsr_eps5_encode_fns, 0, 0 },
  11978   { "wsr.eps5", ICLASS_xt_iclass_wsr_eps5,
  11979     0,
  11980     Opcode_wsr_eps5_encode_fns, 0, 0 },
  11981   { "xsr.eps5", ICLASS_xt_iclass_xsr_eps5,
  11982     0,
  11983     Opcode_xsr_eps5_encode_fns, 0, 0 },
  11984   { "rsr.eps6", ICLASS_xt_iclass_rsr_eps6,
  11985     0,
  11986     Opcode_rsr_eps6_encode_fns, 0, 0 },
  11987   { "wsr.eps6", ICLASS_xt_iclass_wsr_eps6,
  11988     0,
  11989     Opcode_wsr_eps6_encode_fns, 0, 0 },
  11990   { "xsr.eps6", ICLASS_xt_iclass_xsr_eps6,
  11991     0,
  11992     Opcode_xsr_eps6_encode_fns, 0, 0 },
  11993   { "rsr.eps7", ICLASS_xt_iclass_rsr_eps7,
  11994     0,
  11995     Opcode_rsr_eps7_encode_fns, 0, 0 },
  11996   { "wsr.eps7", ICLASS_xt_iclass_wsr_eps7,
  11997     0,
  11998     Opcode_wsr_eps7_encode_fns, 0, 0 },
  11999   { "xsr.eps7", ICLASS_xt_iclass_xsr_eps7,
  12000     0,
  12001     Opcode_xsr_eps7_encode_fns, 0, 0 },
  12002   { "rsr.excvaddr", ICLASS_xt_iclass_rsr_excvaddr,
  12003     0,
  12004     Opcode_rsr_excvaddr_encode_fns, 0, 0 },
  12005   { "wsr.excvaddr", ICLASS_xt_iclass_wsr_excvaddr,
  12006     0,
  12007     Opcode_wsr_excvaddr_encode_fns, 0, 0 },
  12008   { "xsr.excvaddr", ICLASS_xt_iclass_xsr_excvaddr,
  12009     0,
  12010     Opcode_xsr_excvaddr_encode_fns, 0, 0 },
  12011   { "rsr.depc", ICLASS_xt_iclass_rsr_depc,
  12012     0,
  12013     Opcode_rsr_depc_encode_fns, 0, 0 },
  12014   { "wsr.depc", ICLASS_xt_iclass_wsr_depc,
  12015     0,
  12016     Opcode_wsr_depc_encode_fns, 0, 0 },
  12017   { "xsr.depc", ICLASS_xt_iclass_xsr_depc,
  12018     0,
  12019     Opcode_xsr_depc_encode_fns, 0, 0 },
  12020   { "rsr.exccause", ICLASS_xt_iclass_rsr_exccause,
  12021     0,
  12022     Opcode_rsr_exccause_encode_fns, 0, 0 },
  12023   { "wsr.exccause", ICLASS_xt_iclass_wsr_exccause,
  12024     0,
  12025     Opcode_wsr_exccause_encode_fns, 0, 0 },
  12026   { "xsr.exccause", ICLASS_xt_iclass_xsr_exccause,
  12027     0,
  12028     Opcode_xsr_exccause_encode_fns, 0, 0 },
  12029   { "rsr.misc0", ICLASS_xt_iclass_rsr_misc0,
  12030     0,
  12031     Opcode_rsr_misc0_encode_fns, 0, 0 },
  12032   { "wsr.misc0", ICLASS_xt_iclass_wsr_misc0,
  12033     0,
  12034     Opcode_wsr_misc0_encode_fns, 0, 0 },
  12035   { "xsr.misc0", ICLASS_xt_iclass_xsr_misc0,
  12036     0,
  12037     Opcode_xsr_misc0_encode_fns, 0, 0 },
  12038   { "rsr.misc1", ICLASS_xt_iclass_rsr_misc1,
  12039     0,
  12040     Opcode_rsr_misc1_encode_fns, 0, 0 },
  12041   { "wsr.misc1", ICLASS_xt_iclass_wsr_misc1,
  12042     0,
  12043     Opcode_wsr_misc1_encode_fns, 0, 0 },
  12044   { "xsr.misc1", ICLASS_xt_iclass_xsr_misc1,
  12045     0,
  12046     Opcode_xsr_misc1_encode_fns, 0, 0 },
  12047   { "rsr.prid", ICLASS_xt_iclass_rsr_prid,
  12048     0,
  12049     Opcode_rsr_prid_encode_fns, 0, 0 },
  12050   { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
  12051     0,
  12052     Opcode_rsr_vecbase_encode_fns, 0, 0 },
  12053   { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
  12054     0,
  12055     Opcode_wsr_vecbase_encode_fns, 0, 0 },
  12056   { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
  12057     0,
  12058     Opcode_xsr_vecbase_encode_fns, 0, 0 },
  12059   { "mul16u", ICLASS_xt_mul16,
  12060     0,
  12061     Opcode_mul16u_encode_fns, 0, 0 },
  12062   { "mul16s", ICLASS_xt_mul16,
  12063     0,
  12064     Opcode_mul16s_encode_fns, 0, 0 },
  12065   { "mull", ICLASS_xt_mul32,
  12066     0,
  12067     Opcode_mull_encode_fns, 0, 0 },
  12068   { "mul.aa.ll", ICLASS_xt_iclass_mac16_aa,
  12069     0,
  12070     Opcode_mul_aa_ll_encode_fns, 0, 0 },
  12071   { "mul.aa.hl", ICLASS_xt_iclass_mac16_aa,
  12072     0,
  12073     Opcode_mul_aa_hl_encode_fns, 0, 0 },
  12074   { "mul.aa.lh", ICLASS_xt_iclass_mac16_aa,
  12075     0,
  12076     Opcode_mul_aa_lh_encode_fns, 0, 0 },
  12077   { "mul.aa.hh", ICLASS_xt_iclass_mac16_aa,
  12078     0,
  12079     Opcode_mul_aa_hh_encode_fns, 0, 0 },
  12080   { "umul.aa.ll", ICLASS_xt_iclass_mac16_aa,
  12081     0,
  12082     Opcode_umul_aa_ll_encode_fns, 0, 0 },
  12083   { "umul.aa.hl", ICLASS_xt_iclass_mac16_aa,
  12084     0,
  12085     Opcode_umul_aa_hl_encode_fns, 0, 0 },
  12086   { "umul.aa.lh", ICLASS_xt_iclass_mac16_aa,
  12087     0,
  12088     Opcode_umul_aa_lh_encode_fns, 0, 0 },
  12089   { "umul.aa.hh", ICLASS_xt_iclass_mac16_aa,
  12090     0,
  12091     Opcode_umul_aa_hh_encode_fns, 0, 0 },
  12092   { "mul.ad.ll", ICLASS_xt_iclass_mac16_ad,
  12093     0,
  12094     Opcode_mul_ad_ll_encode_fns, 0, 0 },
  12095   { "mul.ad.hl", ICLASS_xt_iclass_mac16_ad,
  12096     0,
  12097     Opcode_mul_ad_hl_encode_fns, 0, 0 },
  12098   { "mul.ad.lh", ICLASS_xt_iclass_mac16_ad,
  12099     0,
  12100     Opcode_mul_ad_lh_encode_fns, 0, 0 },
  12101   { "mul.ad.hh", ICLASS_xt_iclass_mac16_ad,
  12102     0,
  12103     Opcode_mul_ad_hh_encode_fns, 0, 0 },
  12104   { "mul.da.ll", ICLASS_xt_iclass_mac16_da,
  12105     0,
  12106     Opcode_mul_da_ll_encode_fns, 0, 0 },
  12107   { "mul.da.hl", ICLASS_xt_iclass_mac16_da,
  12108     0,
  12109     Opcode_mul_da_hl_encode_fns, 0, 0 },
  12110   { "mul.da.lh", ICLASS_xt_iclass_mac16_da,
  12111     0,
  12112     Opcode_mul_da_lh_encode_fns, 0, 0 },
  12113   { "mul.da.hh", ICLASS_xt_iclass_mac16_da,
  12114     0,
  12115     Opcode_mul_da_hh_encode_fns, 0, 0 },
  12116   { "mul.dd.ll", ICLASS_xt_iclass_mac16_dd,
  12117     0,
  12118     Opcode_mul_dd_ll_encode_fns, 0, 0 },
  12119   { "mul.dd.hl", ICLASS_xt_iclass_mac16_dd,
  12120     0,
  12121     Opcode_mul_dd_hl_encode_fns, 0, 0 },
  12122   { "mul.dd.lh", ICLASS_xt_iclass_mac16_dd,
  12123     0,
  12124     Opcode_mul_dd_lh_encode_fns, 0, 0 },
  12125   { "mul.dd.hh", ICLASS_xt_iclass_mac16_dd,
  12126     0,
  12127     Opcode_mul_dd_hh_encode_fns, 0, 0 },
  12128   { "mula.aa.ll", ICLASS_xt_iclass_mac16a_aa,
  12129     0,
  12130     Opcode_mula_aa_ll_encode_fns, 0, 0 },
  12131   { "mula.aa.hl", ICLASS_xt_iclass_mac16a_aa,
  12132     0,
  12133     Opcode_mula_aa_hl_encode_fns, 0, 0 },
  12134   { "mula.aa.lh", ICLASS_xt_iclass_mac16a_aa,
  12135     0,
  12136     Opcode_mula_aa_lh_encode_fns, 0, 0 },
  12137   { "mula.aa.hh", ICLASS_xt_iclass_mac16a_aa,
  12138     0,
  12139     Opcode_mula_aa_hh_encode_fns, 0, 0 },
  12140   { "muls.aa.ll", ICLASS_xt_iclass_mac16a_aa,
  12141     0,
  12142     Opcode_muls_aa_ll_encode_fns, 0, 0 },
  12143   { "muls.aa.hl", ICLASS_xt_iclass_mac16a_aa,
  12144     0,
  12145     Opcode_muls_aa_hl_encode_fns, 0, 0 },
  12146   { "muls.aa.lh", ICLASS_xt_iclass_mac16a_aa,
  12147     0,
  12148     Opcode_muls_aa_lh_encode_fns, 0, 0 },
  12149   { "muls.aa.hh", ICLASS_xt_iclass_mac16a_aa,
  12150     0,
  12151     Opcode_muls_aa_hh_encode_fns, 0, 0 },
  12152   { "mula.ad.ll", ICLASS_xt_iclass_mac16a_ad,
  12153     0,
  12154     Opcode_mula_ad_ll_encode_fns, 0, 0 },
  12155   { "mula.ad.hl", ICLASS_xt_iclass_mac16a_ad,
  12156     0,
  12157     Opcode_mula_ad_hl_encode_fns, 0, 0 },
  12158   { "mula.ad.lh", ICLASS_xt_iclass_mac16a_ad,
  12159     0,
  12160     Opcode_mula_ad_lh_encode_fns, 0, 0 },
  12161   { "mula.ad.hh", ICLASS_xt_iclass_mac16a_ad,
  12162     0,
  12163     Opcode_mula_ad_hh_encode_fns, 0, 0 },
  12164   { "muls.ad.ll", ICLASS_xt_iclass_mac16a_ad,
  12165     0,
  12166     Opcode_muls_ad_ll_encode_fns, 0, 0 },
  12167   { "muls.ad.hl", ICLASS_xt_iclass_mac16a_ad,
  12168     0,
  12169     Opcode_muls_ad_hl_encode_fns, 0, 0 },
  12170   { "muls.ad.lh", ICLASS_xt_iclass_mac16a_ad,
  12171     0,
  12172     Opcode_muls_ad_lh_encode_fns, 0, 0 },
  12173   { "muls.ad.hh", ICLASS_xt_iclass_mac16a_ad,
  12174     0,
  12175     Opcode_muls_ad_hh_encode_fns, 0, 0 },
  12176   { "mula.da.ll", ICLASS_xt_iclass_mac16a_da,
  12177     0,
  12178     Opcode_mula_da_ll_encode_fns, 0, 0 },
  12179   { "mula.da.hl", ICLASS_xt_iclass_mac16a_da,
  12180     0,
  12181     Opcode_mula_da_hl_encode_fns, 0, 0 },
  12182   { "mula.da.lh", ICLASS_xt_iclass_mac16a_da,
  12183     0,
  12184     Opcode_mula_da_lh_encode_fns, 0, 0 },
  12185   { "mula.da.hh", ICLASS_xt_iclass_mac16a_da,
  12186     0,
  12187     Opcode_mula_da_hh_encode_fns, 0, 0 },
  12188   { "muls.da.ll", ICLASS_xt_iclass_mac16a_da,
  12189     0,
  12190     Opcode_muls_da_ll_encode_fns, 0, 0 },
  12191   { "muls.da.hl", ICLASS_xt_iclass_mac16a_da,
  12192     0,
  12193     Opcode_muls_da_hl_encode_fns, 0, 0 },
  12194   { "muls.da.lh", ICLASS_xt_iclass_mac16a_da,
  12195     0,
  12196     Opcode_muls_da_lh_encode_fns, 0, 0 },
  12197   { "muls.da.hh", ICLASS_xt_iclass_mac16a_da,
  12198     0,
  12199     Opcode_muls_da_hh_encode_fns, 0, 0 },
  12200   { "mula.dd.ll", ICLASS_xt_iclass_mac16a_dd,
  12201     0,
  12202     Opcode_mula_dd_ll_encode_fns, 0, 0 },
  12203   { "mula.dd.hl", ICLASS_xt_iclass_mac16a_dd,
  12204     0,
  12205     Opcode_mula_dd_hl_encode_fns, 0, 0 },
  12206   { "mula.dd.lh", ICLASS_xt_iclass_mac16a_dd,
  12207     0,
  12208     Opcode_mula_dd_lh_encode_fns, 0, 0 },
  12209   { "mula.dd.hh", ICLASS_xt_iclass_mac16a_dd,
  12210     0,
  12211     Opcode_mula_dd_hh_encode_fns, 0, 0 },
  12212   { "muls.dd.ll", ICLASS_xt_iclass_mac16a_dd,
  12213     0,
  12214     Opcode_muls_dd_ll_encode_fns, 0, 0 },
  12215   { "muls.dd.hl", ICLASS_xt_iclass_mac16a_dd,
  12216     0,
  12217     Opcode_muls_dd_hl_encode_fns, 0, 0 },
  12218   { "muls.dd.lh", ICLASS_xt_iclass_mac16a_dd,
  12219     0,
  12220     Opcode_muls_dd_lh_encode_fns, 0, 0 },
  12221   { "muls.dd.hh", ICLASS_xt_iclass_mac16a_dd,
  12222     0,
  12223     Opcode_muls_dd_hh_encode_fns, 0, 0 },
  12224   { "mula.da.ll.lddec", ICLASS_xt_iclass_mac16al_da,
  12225     0,
  12226     Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
  12227   { "mula.da.ll.ldinc", ICLASS_xt_iclass_mac16al_da,
  12228     0,
  12229     Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
  12230   { "mula.da.hl.lddec", ICLASS_xt_iclass_mac16al_da,
  12231     0,
  12232     Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
  12233   { "mula.da.hl.ldinc", ICLASS_xt_iclass_mac16al_da,
  12234     0,
  12235     Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
  12236   { "mula.da.lh.lddec", ICLASS_xt_iclass_mac16al_da,
  12237     0,
  12238     Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
  12239   { "mula.da.lh.ldinc", ICLASS_xt_iclass_mac16al_da,
  12240     0,
  12241     Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
  12242   { "mula.da.hh.lddec", ICLASS_xt_iclass_mac16al_da,
  12243     0,
  12244     Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
  12245   { "mula.da.hh.ldinc", ICLASS_xt_iclass_mac16al_da,
  12246     0,
  12247     Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
  12248   { "mula.dd.ll.lddec", ICLASS_xt_iclass_mac16al_dd,
  12249     0,
  12250     Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
  12251   { "mula.dd.ll.ldinc", ICLASS_xt_iclass_mac16al_dd,
  12252     0,
  12253     Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
  12254   { "mula.dd.hl.lddec", ICLASS_xt_iclass_mac16al_dd,
  12255     0,
  12256     Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
  12257   { "mula.dd.hl.ldinc", ICLASS_xt_iclass_mac16al_dd,
  12258     0,
  12259     Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
  12260   { "mula.dd.lh.lddec", ICLASS_xt_iclass_mac16al_dd,
  12261     0,
  12262     Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
  12263   { "mula.dd.lh.ldinc", ICLASS_xt_iclass_mac16al_dd,
  12264     0,
  12265     Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
  12266   { "mula.dd.hh.lddec", ICLASS_xt_iclass_mac16al_dd,
  12267     0,
  12268     Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
  12269   { "mula.dd.hh.ldinc", ICLASS_xt_iclass_mac16al_dd,
  12270     0,
  12271     Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
  12272   { "lddec", ICLASS_xt_iclass_mac16_l,
  12273     0,
  12274     Opcode_lddec_encode_fns, 0, 0 },
  12275   { "ldinc", ICLASS_xt_iclass_mac16_l,
  12276     0,
  12277     Opcode_ldinc_encode_fns, 0, 0 },
  12278   { "rsr.m0", ICLASS_xt_iclass_rsr_m0,
  12279     0,
  12280     Opcode_rsr_m0_encode_fns, 0, 0 },
  12281   { "wsr.m0", ICLASS_xt_iclass_wsr_m0,
  12282     0,
  12283     Opcode_wsr_m0_encode_fns, 0, 0 },
  12284   { "xsr.m0", ICLASS_xt_iclass_xsr_m0,
  12285     0,
  12286     Opcode_xsr_m0_encode_fns, 0, 0 },
  12287   { "rsr.m1", ICLASS_xt_iclass_rsr_m1,
  12288     0,
  12289     Opcode_rsr_m1_encode_fns, 0, 0 },
  12290   { "wsr.m1", ICLASS_xt_iclass_wsr_m1,
  12291     0,
  12292     Opcode_wsr_m1_encode_fns, 0, 0 },
  12293   { "xsr.m1", ICLASS_xt_iclass_xsr_m1,
  12294     0,
  12295     Opcode_xsr_m1_encode_fns, 0, 0 },
  12296   { "rsr.m2", ICLASS_xt_iclass_rsr_m2,
  12297     0,
  12298     Opcode_rsr_m2_encode_fns, 0, 0 },
  12299   { "wsr.m2", ICLASS_xt_iclass_wsr_m2,
  12300     0,
  12301     Opcode_wsr_m2_encode_fns, 0, 0 },
  12302   { "xsr.m2", ICLASS_xt_iclass_xsr_m2,
  12303     0,
  12304     Opcode_xsr_m2_encode_fns, 0, 0 },
  12305   { "rsr.m3", ICLASS_xt_iclass_rsr_m3,
  12306     0,
  12307     Opcode_rsr_m3_encode_fns, 0, 0 },
  12308   { "wsr.m3", ICLASS_xt_iclass_wsr_m3,
  12309     0,
  12310     Opcode_wsr_m3_encode_fns, 0, 0 },
  12311   { "xsr.m3", ICLASS_xt_iclass_xsr_m3,
  12312     0,
  12313     Opcode_xsr_m3_encode_fns, 0, 0 },
  12314   { "rsr.acclo", ICLASS_xt_iclass_rsr_acclo,
  12315     0,
  12316     Opcode_rsr_acclo_encode_fns, 0, 0 },
  12317   { "wsr.acclo", ICLASS_xt_iclass_wsr_acclo,
  12318     0,
  12319     Opcode_wsr_acclo_encode_fns, 0, 0 },
  12320   { "xsr.acclo", ICLASS_xt_iclass_xsr_acclo,
  12321     0,
  12322     Opcode_xsr_acclo_encode_fns, 0, 0 },
  12323   { "rsr.acchi", ICLASS_xt_iclass_rsr_acchi,
  12324     0,
  12325     Opcode_rsr_acchi_encode_fns, 0, 0 },
  12326   { "wsr.acchi", ICLASS_xt_iclass_wsr_acchi,
  12327     0,
  12328     Opcode_wsr_acchi_encode_fns, 0, 0 },
  12329   { "xsr.acchi", ICLASS_xt_iclass_xsr_acchi,
  12330     0,
  12331     Opcode_xsr_acchi_encode_fns, 0, 0 },
  12332   { "rfi", ICLASS_xt_iclass_rfi,
  12333     XTENSA_OPCODE_IS_JUMP,
  12334     Opcode_rfi_encode_fns, 0, 0 },
  12335   { "waiti", ICLASS_xt_iclass_wait,
  12336     0,
  12337     Opcode_waiti_encode_fns, 0, 0 },
  12338   { "rsr.interrupt", ICLASS_xt_iclass_rsr_interrupt,
  12339     0,
  12340     Opcode_rsr_interrupt_encode_fns, 0, 0 },
  12341   { "wsr.intset", ICLASS_xt_iclass_wsr_intset,
  12342     0,
  12343     Opcode_wsr_intset_encode_fns, 0, 0 },
  12344   { "wsr.intclear", ICLASS_xt_iclass_wsr_intclear,
  12345     0,
  12346     Opcode_wsr_intclear_encode_fns, 0, 0 },
  12347   { "rsr.intenable", ICLASS_xt_iclass_rsr_intenable,
  12348     0,
  12349     Opcode_rsr_intenable_encode_fns, 0, 0 },
  12350   { "wsr.intenable", ICLASS_xt_iclass_wsr_intenable,
  12351     0,
  12352     Opcode_wsr_intenable_encode_fns, 0, 0 },
  12353   { "xsr.intenable", ICLASS_xt_iclass_xsr_intenable,
  12354     0,
  12355     Opcode_xsr_intenable_encode_fns, 0, 0 },
  12356   { "break", ICLASS_xt_iclass_break,
  12357     0,
  12358     Opcode_break_encode_fns, 0, 0 },
  12359   { "break.n", ICLASS_xt_iclass_break_n,
  12360     0,
  12361     Opcode_break_n_encode_fns, 0, 0 },
  12362   { "rsr.dbreaka0", ICLASS_xt_iclass_rsr_dbreaka0,
  12363     0,
  12364     Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
  12365   { "wsr.dbreaka0", ICLASS_xt_iclass_wsr_dbreaka0,
  12366     0,
  12367     Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
  12368   { "xsr.dbreaka0", ICLASS_xt_iclass_xsr_dbreaka0,
  12369     0,
  12370     Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
  12371   { "rsr.dbreakc0", ICLASS_xt_iclass_rsr_dbreakc0,
  12372     0,
  12373     Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
  12374   { "wsr.dbreakc0", ICLASS_xt_iclass_wsr_dbreakc0,
  12375     0,
  12376     Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
  12377   { "xsr.dbreakc0", ICLASS_xt_iclass_xsr_dbreakc0,
  12378     0,
  12379     Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
  12380   { "rsr.dbreaka1", ICLASS_xt_iclass_rsr_dbreaka1,
  12381     0,
  12382     Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
  12383   { "wsr.dbreaka1", ICLASS_xt_iclass_wsr_dbreaka1,
  12384     0,
  12385     Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
  12386   { "xsr.dbreaka1", ICLASS_xt_iclass_xsr_dbreaka1,
  12387     0,
  12388     Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
  12389   { "rsr.dbreakc1", ICLASS_xt_iclass_rsr_dbreakc1,
  12390     0,
  12391     Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
  12392   { "wsr.dbreakc1", ICLASS_xt_iclass_wsr_dbreakc1,
  12393     0,
  12394     Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
  12395   { "xsr.dbreakc1", ICLASS_xt_iclass_xsr_dbreakc1,
  12396     0,
  12397     Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
  12398   { "rsr.ibreaka0", ICLASS_xt_iclass_rsr_ibreaka0,
  12399     0,
  12400     Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
  12401   { "wsr.ibreaka0", ICLASS_xt_iclass_wsr_ibreaka0,
  12402     0,
  12403     Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
  12404   { "xsr.ibreaka0", ICLASS_xt_iclass_xsr_ibreaka0,
  12405     0,
  12406     Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
  12407   { "rsr.ibreaka1", ICLASS_xt_iclass_rsr_ibreaka1,
  12408     0,
  12409     Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
  12410   { "wsr.ibreaka1", ICLASS_xt_iclass_wsr_ibreaka1,
  12411     0,
  12412     Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
  12413   { "xsr.ibreaka1", ICLASS_xt_iclass_xsr_ibreaka1,
  12414     0,
  12415     Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
  12416   { "rsr.ibreakenable", ICLASS_xt_iclass_rsr_ibreakenable,
  12417     0,
  12418     Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
  12419   { "wsr.ibreakenable", ICLASS_xt_iclass_wsr_ibreakenable,
  12420     0,
  12421     Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
  12422   { "xsr.ibreakenable", ICLASS_xt_iclass_xsr_ibreakenable,
  12423     0,
  12424     Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
  12425   { "rsr.debugcause", ICLASS_xt_iclass_rsr_debugcause,
  12426     0,
  12427     Opcode_rsr_debugcause_encode_fns, 0, 0 },
  12428   { "wsr.debugcause", ICLASS_xt_iclass_wsr_debugcause,
  12429     0,
  12430     Opcode_wsr_debugcause_encode_fns, 0, 0 },
  12431   { "xsr.debugcause", ICLASS_xt_iclass_xsr_debugcause,
  12432     0,
  12433     Opcode_xsr_debugcause_encode_fns, 0, 0 },
  12434   { "rsr.icount", ICLASS_xt_iclass_rsr_icount,
  12435     0,
  12436     Opcode_rsr_icount_encode_fns, 0, 0 },
  12437   { "wsr.icount", ICLASS_xt_iclass_wsr_icount,
  12438     0,
  12439     Opcode_wsr_icount_encode_fns, 0, 0 },
  12440   { "xsr.icount", ICLASS_xt_iclass_xsr_icount,
  12441     0,
  12442     Opcode_xsr_icount_encode_fns, 0, 0 },
  12443   { "rsr.icountlevel", ICLASS_xt_iclass_rsr_icountlevel,
  12444     0,
  12445     Opcode_rsr_icountlevel_encode_fns, 0, 0 },
  12446   { "wsr.icountlevel", ICLASS_xt_iclass_wsr_icountlevel,
  12447     0,
  12448     Opcode_wsr_icountlevel_encode_fns, 0, 0 },
  12449   { "xsr.icountlevel", ICLASS_xt_iclass_xsr_icountlevel,
  12450     0,
  12451     Opcode_xsr_icountlevel_encode_fns, 0, 0 },
  12452   { "rsr.ddr", ICLASS_xt_iclass_rsr_ddr,
  12453     0,
  12454     Opcode_rsr_ddr_encode_fns, 0, 0 },
  12455   { "wsr.ddr", ICLASS_xt_iclass_wsr_ddr,
  12456     0,
  12457     Opcode_wsr_ddr_encode_fns, 0, 0 },
  12458   { "xsr.ddr", ICLASS_xt_iclass_xsr_ddr,
  12459     0,
  12460     Opcode_xsr_ddr_encode_fns, 0, 0 },
  12461   { "rfdo", ICLASS_xt_iclass_rfdo,
  12462     XTENSA_OPCODE_IS_JUMP,
  12463     Opcode_rfdo_encode_fns, 0, 0 },
  12464   { "rfdd", ICLASS_xt_iclass_rfdd,
  12465     XTENSA_OPCODE_IS_JUMP,
  12466     Opcode_rfdd_encode_fns, 0, 0 },
  12467   { "wsr.mmid", ICLASS_xt_iclass_wsr_mmid,
  12468     0,
  12469     Opcode_wsr_mmid_encode_fns, 0, 0 },
  12470   { "rsr.ccount", ICLASS_xt_iclass_rsr_ccount,
  12471     0,
  12472     Opcode_rsr_ccount_encode_fns, 0, 0 },
  12473   { "wsr.ccount", ICLASS_xt_iclass_wsr_ccount,
  12474     0,
  12475     Opcode_wsr_ccount_encode_fns, 0, 0 },
  12476   { "xsr.ccount", ICLASS_xt_iclass_xsr_ccount,
  12477     0,
  12478     Opcode_xsr_ccount_encode_fns, 0, 0 },
  12479   { "rsr.ccompare0", ICLASS_xt_iclass_rsr_ccompare0,
  12480     0,
  12481     Opcode_rsr_ccompare0_encode_fns, 0, 0 },
  12482   { "wsr.ccompare0", ICLASS_xt_iclass_wsr_ccompare0,
  12483     0,
  12484     Opcode_wsr_ccompare0_encode_fns, 0, 0 },
  12485   { "xsr.ccompare0", ICLASS_xt_iclass_xsr_ccompare0,
  12486     0,
  12487     Opcode_xsr_ccompare0_encode_fns, 0, 0 },
  12488   { "rsr.ccompare1", ICLASS_xt_iclass_rsr_ccompare1,
  12489     0,
  12490     Opcode_rsr_ccompare1_encode_fns, 0, 0 },
  12491   { "wsr.ccompare1", ICLASS_xt_iclass_wsr_ccompare1,
  12492     0,
  12493     Opcode_wsr_ccompare1_encode_fns, 0, 0 },
  12494   { "xsr.ccompare1", ICLASS_xt_iclass_xsr_ccompare1,
  12495     0,
  12496     Opcode_xsr_ccompare1_encode_fns, 0, 0 },
  12497   { "rsr.ccompare2", ICLASS_xt_iclass_rsr_ccompare2,
  12498     0,
  12499     Opcode_rsr_ccompare2_encode_fns, 0, 0 },
  12500   { "wsr.ccompare2", ICLASS_xt_iclass_wsr_ccompare2,
  12501     0,
  12502     Opcode_wsr_ccompare2_encode_fns, 0, 0 },
  12503   { "xsr.ccompare2", ICLASS_xt_iclass_xsr_ccompare2,
  12504     0,
  12505     Opcode_xsr_ccompare2_encode_fns, 0, 0 },
  12506   { "ipf", ICLASS_xt_iclass_icache,
  12507     0,
  12508     Opcode_ipf_encode_fns, 0, 0 },
  12509   { "ihi", ICLASS_xt_iclass_icache,
  12510     0,
  12511     Opcode_ihi_encode_fns, 0, 0 },
  12512   { "ipfl", ICLASS_xt_iclass_icache_lock,
  12513     0,
  12514     Opcode_ipfl_encode_fns, 0, 0 },
  12515   { "ihu", ICLASS_xt_iclass_icache_lock,
  12516     0,
  12517     Opcode_ihu_encode_fns, 0, 0 },
  12518   { "iiu", ICLASS_xt_iclass_icache_lock,
  12519     0,
  12520     Opcode_iiu_encode_fns, 0, 0 },
  12521   { "iii", ICLASS_xt_iclass_icache_inv,
  12522     0,
  12523     Opcode_iii_encode_fns, 0, 0 },
  12524   { "lict", ICLASS_xt_iclass_licx,
  12525     0,
  12526     Opcode_lict_encode_fns, 0, 0 },
  12527   { "licw", ICLASS_xt_iclass_licx,
  12528     0,
  12529     Opcode_licw_encode_fns, 0, 0 },
  12530   { "sict", ICLASS_xt_iclass_sicx,
  12531     0,
  12532     Opcode_sict_encode_fns, 0, 0 },
  12533   { "sicw", ICLASS_xt_iclass_sicx,
  12534     0,
  12535     Opcode_sicw_encode_fns, 0, 0 },
  12536   { "dhwb", ICLASS_xt_iclass_dcache,
  12537     0,
  12538     Opcode_dhwb_encode_fns, 0, 0 },
  12539   { "dhwbi", ICLASS_xt_iclass_dcache,
  12540     0,
  12541     Opcode_dhwbi_encode_fns, 0, 0 },
  12542   { "diwb", ICLASS_xt_iclass_dcache_ind,
  12543     0,
  12544     Opcode_diwb_encode_fns, 0, 0 },
  12545   { "diwbi", ICLASS_xt_iclass_dcache_ind,
  12546     0,
  12547     Opcode_diwbi_encode_fns, 0, 0 },
  12548   { "dhi", ICLASS_xt_iclass_dcache_inv,
  12549     0,
  12550     Opcode_dhi_encode_fns, 0, 0 },
  12551   { "dii", ICLASS_xt_iclass_dcache_inv,
  12552     0,
  12553     Opcode_dii_encode_fns, 0, 0 },
  12554   { "dpfr", ICLASS_xt_iclass_dpf,
  12555     0,
  12556     Opcode_dpfr_encode_fns, 0, 0 },
  12557   { "dpfw", ICLASS_xt_iclass_dpf,
  12558     0,
  12559     Opcode_dpfw_encode_fns, 0, 0 },
  12560   { "dpfro", ICLASS_xt_iclass_dpf,
  12561     0,
  12562     Opcode_dpfro_encode_fns, 0, 0 },
  12563   { "dpfwo", ICLASS_xt_iclass_dpf,
  12564     0,
  12565     Opcode_dpfwo_encode_fns, 0, 0 },
  12566   { "dpfl", ICLASS_xt_iclass_dcache_lock,
  12567     0,
  12568     Opcode_dpfl_encode_fns, 0, 0 },
  12569   { "dhu", ICLASS_xt_iclass_dcache_lock,
  12570     0,
  12571     Opcode_dhu_encode_fns, 0, 0 },
  12572   { "diu", ICLASS_xt_iclass_dcache_lock,
  12573     0,
  12574     Opcode_diu_encode_fns, 0, 0 },
  12575   { "sdct", ICLASS_xt_iclass_sdct,
  12576     0,
  12577     Opcode_sdct_encode_fns, 0, 0 },
  12578   { "ldct", ICLASS_xt_iclass_ldct,
  12579     0,
  12580     Opcode_ldct_encode_fns, 0, 0 },
  12581   { "wsr.ptevaddr", ICLASS_xt_iclass_wsr_ptevaddr,
  12582     0,
  12583     Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
  12584   { "rsr.ptevaddr", ICLASS_xt_iclass_rsr_ptevaddr,
  12585     0,
  12586     Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
  12587   { "xsr.ptevaddr", ICLASS_xt_iclass_xsr_ptevaddr,
  12588     0,
  12589     Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
  12590   { "rsr.rasid", ICLASS_xt_iclass_rsr_rasid,
  12591     0,
  12592     Opcode_rsr_rasid_encode_fns, 0, 0 },
  12593   { "wsr.rasid", ICLASS_xt_iclass_wsr_rasid,
  12594     0,
  12595     Opcode_wsr_rasid_encode_fns, 0, 0 },
  12596   { "xsr.rasid", ICLASS_xt_iclass_xsr_rasid,
  12597     0,
  12598     Opcode_xsr_rasid_encode_fns, 0, 0 },
  12599   { "rsr.itlbcfg", ICLASS_xt_iclass_rsr_itlbcfg,
  12600     0,
  12601     Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
  12602   { "wsr.itlbcfg", ICLASS_xt_iclass_wsr_itlbcfg,
  12603     0,
  12604     Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
  12605   { "xsr.itlbcfg", ICLASS_xt_iclass_xsr_itlbcfg,
  12606     0,
  12607     Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
  12608   { "rsr.dtlbcfg", ICLASS_xt_iclass_rsr_dtlbcfg,
  12609     0,
  12610     Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
  12611   { "wsr.dtlbcfg", ICLASS_xt_iclass_wsr_dtlbcfg,
  12612     0,
  12613     Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
  12614   { "xsr.dtlbcfg", ICLASS_xt_iclass_xsr_dtlbcfg,
  12615     0,
  12616     Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
  12617   { "idtlb", ICLASS_xt_iclass_idtlb,
  12618     0,
  12619     Opcode_idtlb_encode_fns, 0, 0 },
  12620   { "pdtlb", ICLASS_xt_iclass_rdtlb,
  12621     0,
  12622     Opcode_pdtlb_encode_fns, 0, 0 },
  12623   { "rdtlb0", ICLASS_xt_iclass_rdtlb,
  12624     0,
  12625     Opcode_rdtlb0_encode_fns, 0, 0 },
  12626   { "rdtlb1", ICLASS_xt_iclass_rdtlb,
  12627     0,
  12628     Opcode_rdtlb1_encode_fns, 0, 0 },
  12629   { "wdtlb", ICLASS_xt_iclass_wdtlb,
  12630     0,
  12631     Opcode_wdtlb_encode_fns, 0, 0 },
  12632   { "iitlb", ICLASS_xt_iclass_iitlb,
  12633     0,
  12634     Opcode_iitlb_encode_fns, 0, 0 },
  12635   { "pitlb", ICLASS_xt_iclass_ritlb,
  12636     0,
  12637     Opcode_pitlb_encode_fns, 0, 0 },
  12638   { "ritlb0", ICLASS_xt_iclass_ritlb,
  12639     0,
  12640     Opcode_ritlb0_encode_fns, 0, 0 },
  12641   { "ritlb1", ICLASS_xt_iclass_ritlb,
  12642     0,
  12643     Opcode_ritlb1_encode_fns, 0, 0 },
  12644   { "witlb", ICLASS_xt_iclass_witlb,
  12645     0,
  12646     Opcode_witlb_encode_fns, 0, 0 },
  12647   { "ldpte", ICLASS_xt_iclass_ldpte,
  12648     0,
  12649     Opcode_ldpte_encode_fns, 0, 0 },
  12650   { "hwwitlba", ICLASS_xt_iclass_hwwitlba,
  12651     XTENSA_OPCODE_IS_BRANCH,
  12652     Opcode_hwwitlba_encode_fns, 0, 0 },
  12653   { "hwwdtlba", ICLASS_xt_iclass_hwwdtlba,
  12654     0,
  12655     Opcode_hwwdtlba_encode_fns, 0, 0 },
  12656   { "rsr.cpenable", ICLASS_xt_iclass_rsr_cpenable,
  12657     0,
  12658     Opcode_rsr_cpenable_encode_fns, 0, 0 },
  12659   { "wsr.cpenable", ICLASS_xt_iclass_wsr_cpenable,
  12660     0,
  12661     Opcode_wsr_cpenable_encode_fns, 0, 0 },
  12662   { "xsr.cpenable", ICLASS_xt_iclass_xsr_cpenable,
  12663     0,
  12664     Opcode_xsr_cpenable_encode_fns, 0, 0 },
  12665   { "clamps", ICLASS_xt_iclass_clamp,
  12666     0,
  12667     Opcode_clamps_encode_fns, 0, 0 },
  12668   { "min", ICLASS_xt_iclass_minmax,
  12669     0,
  12670     Opcode_min_encode_fns, 0, 0 },
  12671   { "max", ICLASS_xt_iclass_minmax,
  12672     0,
  12673     Opcode_max_encode_fns, 0, 0 },
  12674   { "minu", ICLASS_xt_iclass_minmax,
  12675     0,
  12676     Opcode_minu_encode_fns, 0, 0 },
  12677   { "maxu", ICLASS_xt_iclass_minmax,
  12678     0,
  12679     Opcode_maxu_encode_fns, 0, 0 },
  12680   { "nsa", ICLASS_xt_iclass_nsa,
  12681     0,
  12682     Opcode_nsa_encode_fns, 0, 0 },
  12683   { "nsau", ICLASS_xt_iclass_nsa,
  12684     0,
  12685     Opcode_nsau_encode_fns, 0, 0 },
  12686   { "sext", ICLASS_xt_iclass_sx,
  12687     0,
  12688     Opcode_sext_encode_fns, 0, 0 },
  12689   { "l32ai", ICLASS_xt_iclass_l32ai,
  12690     0,
  12691     Opcode_l32ai_encode_fns, 0, 0 },
  12692   { "s32ri", ICLASS_xt_iclass_s32ri,
  12693     0,
  12694     Opcode_s32ri_encode_fns, 0, 0 },
  12695   { "s32c1i", ICLASS_xt_iclass_s32c1i,
  12696     0,
  12697     Opcode_s32c1i_encode_fns, 0, 0 },
  12698   { "rsr.scompare1", ICLASS_xt_iclass_rsr_scompare1,
  12699     0,
  12700     Opcode_rsr_scompare1_encode_fns, 0, 0 },
  12701   { "wsr.scompare1", ICLASS_xt_iclass_wsr_scompare1,
  12702     0,
  12703     Opcode_wsr_scompare1_encode_fns, 0, 0 },
  12704   { "xsr.scompare1", ICLASS_xt_iclass_xsr_scompare1,
  12705     0,
  12706     Opcode_xsr_scompare1_encode_fns, 0, 0 },
  12707   { "rsr.atomctl", ICLASS_xt_iclass_rsr_atomctl,
  12708     0,
  12709     Opcode_rsr_atomctl_encode_fns, 0, 0 },
  12710   { "wsr.atomctl", ICLASS_xt_iclass_wsr_atomctl,
  12711     0,
  12712     Opcode_wsr_atomctl_encode_fns, 0, 0 },
  12713   { "xsr.atomctl", ICLASS_xt_iclass_xsr_atomctl,
  12714     0,
  12715     Opcode_xsr_atomctl_encode_fns, 0, 0 },
  12716   { "quou", ICLASS_xt_iclass_div,
  12717     0,
  12718     Opcode_quou_encode_fns, 0, 0 },
  12719   { "quos", ICLASS_xt_iclass_div,
  12720     0,
  12721     Opcode_quos_encode_fns, 0, 0 },
  12722   { "remu", ICLASS_xt_iclass_div,
  12723     0,
  12724     Opcode_remu_encode_fns, 0, 0 },
  12725   { "rems", ICLASS_xt_iclass_div,
  12726     0,
  12727     Opcode_rems_encode_fns, 0, 0 },
  12728   { "rer", ICLASS_xt_iclass_rer,
  12729     0,
  12730     Opcode_rer_encode_fns, 0, 0 },
  12731   { "wer", ICLASS_xt_iclass_wer,
  12732     0,
  12733     Opcode_wer_encode_fns, 0, 0 },
  12734   { "rur.expstate", ICLASS_rur_expstate,
  12735     0,
  12736     Opcode_rur_expstate_encode_fns, 0, 0 },
  12737   { "wur.expstate", ICLASS_wur_expstate,
  12738     0,
  12739     Opcode_wur_expstate_encode_fns, 0, 0 },
  12740   { "read_impwire", ICLASS_iclass_READ_IMPWIRE,
  12741     0,
  12742     Opcode_read_impwire_encode_fns, 0, 0 },
  12743   { "setb_expstate", ICLASS_iclass_SETB_EXPSTATE,
  12744     0,
  12745     Opcode_setb_expstate_encode_fns, 0, 0 },
  12746   { "clrb_expstate", ICLASS_iclass_CLRB_EXPSTATE,
  12747     0,
  12748     Opcode_clrb_expstate_encode_fns, 0, 0 },
  12749   { "wrmsk_expstate", ICLASS_iclass_WRMSK_EXPSTATE,
  12750     0,
  12751     Opcode_wrmsk_expstate_encode_fns, 0, 0 }
  12752 };
  12753 
  12754 enum xtensa_opcode_id {
  12755   OPCODE_EXCW,
  12756   OPCODE_RFE,
  12757   OPCODE_RFDE,
  12758   OPCODE_SYSCALL,
  12759   OPCODE_SIMCALL,
  12760   OPCODE_CALL12,
  12761   OPCODE_CALL8,
  12762   OPCODE_CALL4,
  12763   OPCODE_CALLX12,
  12764   OPCODE_CALLX8,
  12765   OPCODE_CALLX4,
  12766   OPCODE_ENTRY,
  12767   OPCODE_MOVSP,
  12768   OPCODE_ROTW,
  12769   OPCODE_RETW,
  12770   OPCODE_RETW_N,
  12771   OPCODE_RFWO,
  12772   OPCODE_RFWU,
  12773   OPCODE_L32E,
  12774   OPCODE_S32E,
  12775   OPCODE_RSR_WINDOWBASE,
  12776   OPCODE_WSR_WINDOWBASE,
  12777   OPCODE_XSR_WINDOWBASE,
  12778   OPCODE_RSR_WINDOWSTART,
  12779   OPCODE_WSR_WINDOWSTART,
  12780   OPCODE_XSR_WINDOWSTART,
  12781   OPCODE_ADD_N,
  12782   OPCODE_ADDI_N,
  12783   OPCODE_BEQZ_N,
  12784   OPCODE_BNEZ_N,
  12785   OPCODE_ILL_N,
  12786   OPCODE_L32I_N,
  12787   OPCODE_MOV_N,
  12788   OPCODE_MOVI_N,
  12789   OPCODE_NOP_N,
  12790   OPCODE_RET_N,
  12791   OPCODE_S32I_N,
  12792   OPCODE_RUR_THREADPTR,
  12793   OPCODE_WUR_THREADPTR,
  12794   OPCODE_ADDI,
  12795   OPCODE_ADDMI,
  12796   OPCODE_ADD,
  12797   OPCODE_SUB,
  12798   OPCODE_ADDX2,
  12799   OPCODE_ADDX4,
  12800   OPCODE_ADDX8,
  12801   OPCODE_SUBX2,
  12802   OPCODE_SUBX4,
  12803   OPCODE_SUBX8,
  12804   OPCODE_AND,
  12805   OPCODE_OR,
  12806   OPCODE_XOR,
  12807   OPCODE_BEQI,
  12808   OPCODE_BNEI,
  12809   OPCODE_BGEI,
  12810   OPCODE_BLTI,
  12811   OPCODE_BBCI,
  12812   OPCODE_BBSI,
  12813   OPCODE_BGEUI,
  12814   OPCODE_BLTUI,
  12815   OPCODE_BEQ,
  12816   OPCODE_BNE,
  12817   OPCODE_BGE,
  12818   OPCODE_BLT,
  12819   OPCODE_BGEU,
  12820   OPCODE_BLTU,
  12821   OPCODE_BANY,
  12822   OPCODE_BNONE,
  12823   OPCODE_BALL,
  12824   OPCODE_BNALL,
  12825   OPCODE_BBC,
  12826   OPCODE_BBS,
  12827   OPCODE_BEQZ,
  12828   OPCODE_BNEZ,
  12829   OPCODE_BGEZ,
  12830   OPCODE_BLTZ,
  12831   OPCODE_CALL0,
  12832   OPCODE_CALLX0,
  12833   OPCODE_EXTUI,
  12834   OPCODE_ILL,
  12835   OPCODE_J,
  12836   OPCODE_JX,
  12837   OPCODE_L16UI,
  12838   OPCODE_L16SI,
  12839   OPCODE_L32I,
  12840   OPCODE_L32R,
  12841   OPCODE_L8UI,
  12842   OPCODE_LOOP,
  12843   OPCODE_LOOPNEZ,
  12844   OPCODE_LOOPGTZ,
  12845   OPCODE_MOVI,
  12846   OPCODE_MOVEQZ,
  12847   OPCODE_MOVNEZ,
  12848   OPCODE_MOVLTZ,
  12849   OPCODE_MOVGEZ,
  12850   OPCODE_NEG,
  12851   OPCODE_ABS,
  12852   OPCODE_NOP,
  12853   OPCODE_RET,
  12854   OPCODE_S16I,
  12855   OPCODE_S32I,
  12856   OPCODE_S8I,
  12857   OPCODE_SSR,
  12858   OPCODE_SSL,
  12859   OPCODE_SSA8L,
  12860   OPCODE_SSA8B,
  12861   OPCODE_SSAI,
  12862   OPCODE_SLL,
  12863   OPCODE_SRC,
  12864   OPCODE_SRL,
  12865   OPCODE_SRA,
  12866   OPCODE_SLLI,
  12867   OPCODE_SRAI,
  12868   OPCODE_SRLI,
  12869   OPCODE_MEMW,
  12870   OPCODE_EXTW,
  12871   OPCODE_ISYNC,
  12872   OPCODE_RSYNC,
  12873   OPCODE_ESYNC,
  12874   OPCODE_DSYNC,
  12875   OPCODE_RSIL,
  12876   OPCODE_RSR_LEND,
  12877   OPCODE_WSR_LEND,
  12878   OPCODE_XSR_LEND,
  12879   OPCODE_RSR_LCOUNT,
  12880   OPCODE_WSR_LCOUNT,
  12881   OPCODE_XSR_LCOUNT,
  12882   OPCODE_RSR_LBEG,
  12883   OPCODE_WSR_LBEG,
  12884   OPCODE_XSR_LBEG,
  12885   OPCODE_RSR_SAR,
  12886   OPCODE_WSR_SAR,
  12887   OPCODE_XSR_SAR,
  12888   OPCODE_RSR_LITBASE,
  12889   OPCODE_WSR_LITBASE,
  12890   OPCODE_XSR_LITBASE,
  12891   OPCODE_RSR_176,
  12892   OPCODE_WSR_176,
  12893   OPCODE_RSR_208,
  12894   OPCODE_RSR_PS,
  12895   OPCODE_WSR_PS,
  12896   OPCODE_XSR_PS,
  12897   OPCODE_RSR_EPC1,
  12898   OPCODE_WSR_EPC1,
  12899   OPCODE_XSR_EPC1,
  12900   OPCODE_RSR_EXCSAVE1,
  12901   OPCODE_WSR_EXCSAVE1,
  12902   OPCODE_XSR_EXCSAVE1,
  12903   OPCODE_RSR_EPC2,
  12904   OPCODE_WSR_EPC2,
  12905   OPCODE_XSR_EPC2,
  12906   OPCODE_RSR_EXCSAVE2,
  12907   OPCODE_WSR_EXCSAVE2,
  12908   OPCODE_XSR_EXCSAVE2,
  12909   OPCODE_RSR_EPC3,
  12910   OPCODE_WSR_EPC3,
  12911   OPCODE_XSR_EPC3,
  12912   OPCODE_RSR_EXCSAVE3,
  12913   OPCODE_WSR_EXCSAVE3,
  12914   OPCODE_XSR_EXCSAVE3,
  12915   OPCODE_RSR_EPC4,
  12916   OPCODE_WSR_EPC4,
  12917   OPCODE_XSR_EPC4,
  12918   OPCODE_RSR_EXCSAVE4,
  12919   OPCODE_WSR_EXCSAVE4,
  12920   OPCODE_XSR_EXCSAVE4,
  12921   OPCODE_RSR_EPC5,
  12922   OPCODE_WSR_EPC5,
  12923   OPCODE_XSR_EPC5,
  12924   OPCODE_RSR_EXCSAVE5,
  12925   OPCODE_WSR_EXCSAVE5,
  12926   OPCODE_XSR_EXCSAVE5,
  12927   OPCODE_RSR_EPC6,
  12928   OPCODE_WSR_EPC6,
  12929   OPCODE_XSR_EPC6,
  12930   OPCODE_RSR_EXCSAVE6,
  12931   OPCODE_WSR_EXCSAVE6,
  12932   OPCODE_XSR_EXCSAVE6,
  12933   OPCODE_RSR_EPC7,
  12934   OPCODE_WSR_EPC7,
  12935   OPCODE_XSR_EPC7,
  12936   OPCODE_RSR_EXCSAVE7,
  12937   OPCODE_WSR_EXCSAVE7,
  12938   OPCODE_XSR_EXCSAVE7,
  12939   OPCODE_RSR_EPS2,
  12940   OPCODE_WSR_EPS2,
  12941   OPCODE_XSR_EPS2,
  12942   OPCODE_RSR_EPS3,
  12943   OPCODE_WSR_EPS3,
  12944   OPCODE_XSR_EPS3,
  12945   OPCODE_RSR_EPS4,
  12946   OPCODE_WSR_EPS4,
  12947   OPCODE_XSR_EPS4,
  12948   OPCODE_RSR_EPS5,
  12949   OPCODE_WSR_EPS5,
  12950   OPCODE_XSR_EPS5,
  12951   OPCODE_RSR_EPS6,
  12952   OPCODE_WSR_EPS6,
  12953   OPCODE_XSR_EPS6,
  12954   OPCODE_RSR_EPS7,
  12955   OPCODE_WSR_EPS7,
  12956   OPCODE_XSR_EPS7,
  12957   OPCODE_RSR_EXCVADDR,
  12958   OPCODE_WSR_EXCVADDR,
  12959   OPCODE_XSR_EXCVADDR,
  12960   OPCODE_RSR_DEPC,
  12961   OPCODE_WSR_DEPC,
  12962   OPCODE_XSR_DEPC,
  12963   OPCODE_RSR_EXCCAUSE,
  12964   OPCODE_WSR_EXCCAUSE,
  12965   OPCODE_XSR_EXCCAUSE,
  12966   OPCODE_RSR_MISC0,
  12967   OPCODE_WSR_MISC0,
  12968   OPCODE_XSR_MISC0,
  12969   OPCODE_RSR_MISC1,
  12970   OPCODE_WSR_MISC1,
  12971   OPCODE_XSR_MISC1,
  12972   OPCODE_RSR_PRID,
  12973   OPCODE_RSR_VECBASE,
  12974   OPCODE_WSR_VECBASE,
  12975   OPCODE_XSR_VECBASE,
  12976   OPCODE_MUL16U,
  12977   OPCODE_MUL16S,
  12978   OPCODE_MULL,
  12979   OPCODE_MUL_AA_LL,
  12980   OPCODE_MUL_AA_HL,
  12981   OPCODE_MUL_AA_LH,
  12982   OPCODE_MUL_AA_HH,
  12983   OPCODE_UMUL_AA_LL,
  12984   OPCODE_UMUL_AA_HL,
  12985   OPCODE_UMUL_AA_LH,
  12986   OPCODE_UMUL_AA_HH,
  12987   OPCODE_MUL_AD_LL,
  12988   OPCODE_MUL_AD_HL,
  12989   OPCODE_MUL_AD_LH,
  12990   OPCODE_MUL_AD_HH,
  12991   OPCODE_MUL_DA_LL,
  12992   OPCODE_MUL_DA_HL,
  12993   OPCODE_MUL_DA_LH,
  12994   OPCODE_MUL_DA_HH,
  12995   OPCODE_MUL_DD_LL,
  12996   OPCODE_MUL_DD_HL,
  12997   OPCODE_MUL_DD_LH,
  12998   OPCODE_MUL_DD_HH,
  12999   OPCODE_MULA_AA_LL,
  13000   OPCODE_MULA_AA_HL,
  13001   OPCODE_MULA_AA_LH,
  13002   OPCODE_MULA_AA_HH,
  13003   OPCODE_MULS_AA_LL,
  13004   OPCODE_MULS_AA_HL,
  13005   OPCODE_MULS_AA_LH,
  13006   OPCODE_MULS_AA_HH,
  13007   OPCODE_MULA_AD_LL,
  13008   OPCODE_MULA_AD_HL,
  13009   OPCODE_MULA_AD_LH,
  13010   OPCODE_MULA_AD_HH,
  13011   OPCODE_MULS_AD_LL,
  13012   OPCODE_MULS_AD_HL,
  13013   OPCODE_MULS_AD_LH,
  13014   OPCODE_MULS_AD_HH,
  13015   OPCODE_MULA_DA_LL,
  13016   OPCODE_MULA_DA_HL,
  13017   OPCODE_MULA_DA_LH,
  13018   OPCODE_MULA_DA_HH,
  13019   OPCODE_MULS_DA_LL,
  13020   OPCODE_MULS_DA_HL,
  13021   OPCODE_MULS_DA_LH,
  13022   OPCODE_MULS_DA_HH,
  13023   OPCODE_MULA_DD_LL,
  13024   OPCODE_MULA_DD_HL,
  13025   OPCODE_MULA_DD_LH,
  13026   OPCODE_MULA_DD_HH,
  13027   OPCODE_MULS_DD_LL,
  13028   OPCODE_MULS_DD_HL,
  13029   OPCODE_MULS_DD_LH,
  13030   OPCODE_MULS_DD_HH,
  13031   OPCODE_MULA_DA_LL_LDDEC,
  13032   OPCODE_MULA_DA_LL_LDINC,
  13033   OPCODE_MULA_DA_HL_LDDEC,
  13034   OPCODE_MULA_DA_HL_LDINC,
  13035   OPCODE_MULA_DA_LH_LDDEC,
  13036   OPCODE_MULA_DA_LH_LDINC,
  13037   OPCODE_MULA_DA_HH_LDDEC,
  13038   OPCODE_MULA_DA_HH_LDINC,
  13039   OPCODE_MULA_DD_LL_LDDEC,
  13040   OPCODE_MULA_DD_LL_LDINC,
  13041   OPCODE_MULA_DD_HL_LDDEC,
  13042   OPCODE_MULA_DD_HL_LDINC,
  13043   OPCODE_MULA_DD_LH_LDDEC,
  13044   OPCODE_MULA_DD_LH_LDINC,
  13045   OPCODE_MULA_DD_HH_LDDEC,
  13046   OPCODE_MULA_DD_HH_LDINC,
  13047   OPCODE_LDDEC,
  13048   OPCODE_LDINC,
  13049   OPCODE_RSR_M0,
  13050   OPCODE_WSR_M0,
  13051   OPCODE_XSR_M0,
  13052   OPCODE_RSR_M1,
  13053   OPCODE_WSR_M1,
  13054   OPCODE_XSR_M1,
  13055   OPCODE_RSR_M2,
  13056   OPCODE_WSR_M2,
  13057   OPCODE_XSR_M2,
  13058   OPCODE_RSR_M3,
  13059   OPCODE_WSR_M3,
  13060   OPCODE_XSR_M3,
  13061   OPCODE_RSR_ACCLO,
  13062   OPCODE_WSR_ACCLO,
  13063   OPCODE_XSR_ACCLO,
  13064   OPCODE_RSR_ACCHI,
  13065   OPCODE_WSR_ACCHI,
  13066   OPCODE_XSR_ACCHI,
  13067   OPCODE_RFI,
  13068   OPCODE_WAITI,
  13069   OPCODE_RSR_INTERRUPT,
  13070   OPCODE_WSR_INTSET,
  13071   OPCODE_WSR_INTCLEAR,
  13072   OPCODE_RSR_INTENABLE,
  13073   OPCODE_WSR_INTENABLE,
  13074   OPCODE_XSR_INTENABLE,
  13075   OPCODE_BREAK,
  13076   OPCODE_BREAK_N,
  13077   OPCODE_RSR_DBREAKA0,
  13078   OPCODE_WSR_DBREAKA0,
  13079   OPCODE_XSR_DBREAKA0,
  13080   OPCODE_RSR_DBREAKC0,
  13081   OPCODE_WSR_DBREAKC0,
  13082   OPCODE_XSR_DBREAKC0,
  13083   OPCODE_RSR_DBREAKA1,
  13084   OPCODE_WSR_DBREAKA1,
  13085   OPCODE_XSR_DBREAKA1,
  13086   OPCODE_RSR_DBREAKC1,
  13087   OPCODE_WSR_DBREAKC1,
  13088   OPCODE_XSR_DBREAKC1,
  13089   OPCODE_RSR_IBREAKA0,
  13090   OPCODE_WSR_IBREAKA0,
  13091   OPCODE_XSR_IBREAKA0,
  13092   OPCODE_RSR_IBREAKA1,
  13093   OPCODE_WSR_IBREAKA1,
  13094   OPCODE_XSR_IBREAKA1,
  13095   OPCODE_RSR_IBREAKENABLE,
  13096   OPCODE_WSR_IBREAKENABLE,
  13097   OPCODE_XSR_IBREAKENABLE,
  13098   OPCODE_RSR_DEBUGCAUSE,
  13099   OPCODE_WSR_DEBUGCAUSE,
  13100   OPCODE_XSR_DEBUGCAUSE,
  13101   OPCODE_RSR_ICOUNT,
  13102   OPCODE_WSR_ICOUNT,
  13103   OPCODE_XSR_ICOUNT,
  13104   OPCODE_RSR_ICOUNTLEVEL,
  13105   OPCODE_WSR_ICOUNTLEVEL,
  13106   OPCODE_XSR_ICOUNTLEVEL,
  13107   OPCODE_RSR_DDR,
  13108   OPCODE_WSR_DDR,
  13109   OPCODE_XSR_DDR,
  13110   OPCODE_RFDO,
  13111   OPCODE_RFDD,
  13112   OPCODE_WSR_MMID,
  13113   OPCODE_RSR_CCOUNT,
  13114   OPCODE_WSR_CCOUNT,
  13115   OPCODE_XSR_CCOUNT,
  13116   OPCODE_RSR_CCOMPARE0,
  13117   OPCODE_WSR_CCOMPARE0,
  13118   OPCODE_XSR_CCOMPARE0,
  13119   OPCODE_RSR_CCOMPARE1,
  13120   OPCODE_WSR_CCOMPARE1,
  13121   OPCODE_XSR_CCOMPARE1,
  13122   OPCODE_RSR_CCOMPARE2,
  13123   OPCODE_WSR_CCOMPARE2,
  13124   OPCODE_XSR_CCOMPARE2,
  13125   OPCODE_IPF,
  13126   OPCODE_IHI,
  13127   OPCODE_IPFL,
  13128   OPCODE_IHU,
  13129   OPCODE_IIU,
  13130   OPCODE_III,
  13131   OPCODE_LICT,
  13132   OPCODE_LICW,
  13133   OPCODE_SICT,
  13134   OPCODE_SICW,
  13135   OPCODE_DHWB,
  13136   OPCODE_DHWBI,
  13137   OPCODE_DIWB,
  13138   OPCODE_DIWBI,
  13139   OPCODE_DHI,
  13140   OPCODE_DII,
  13141   OPCODE_DPFR,
  13142   OPCODE_DPFW,
  13143   OPCODE_DPFRO,
  13144   OPCODE_DPFWO,
  13145   OPCODE_DPFL,
  13146   OPCODE_DHU,
  13147   OPCODE_DIU,
  13148   OPCODE_SDCT,
  13149   OPCODE_LDCT,
  13150   OPCODE_WSR_PTEVADDR,
  13151   OPCODE_RSR_PTEVADDR,
  13152   OPCODE_XSR_PTEVADDR,
  13153   OPCODE_RSR_RASID,
  13154   OPCODE_WSR_RASID,
  13155   OPCODE_XSR_RASID,
  13156   OPCODE_RSR_ITLBCFG,
  13157   OPCODE_WSR_ITLBCFG,
  13158   OPCODE_XSR_ITLBCFG,
  13159   OPCODE_RSR_DTLBCFG,
  13160   OPCODE_WSR_DTLBCFG,
  13161   OPCODE_XSR_DTLBCFG,
  13162   OPCODE_IDTLB,
  13163   OPCODE_PDTLB,
  13164   OPCODE_RDTLB0,
  13165   OPCODE_RDTLB1,
  13166   OPCODE_WDTLB,
  13167   OPCODE_IITLB,
  13168   OPCODE_PITLB,
  13169   OPCODE_RITLB0,
  13170   OPCODE_RITLB1,
  13171   OPCODE_WITLB,
  13172   OPCODE_LDPTE,
  13173   OPCODE_HWWITLBA,
  13174   OPCODE_HWWDTLBA,
  13175   OPCODE_RSR_CPENABLE,
  13176   OPCODE_WSR_CPENABLE,
  13177   OPCODE_XSR_CPENABLE,
  13178   OPCODE_CLAMPS,
  13179   OPCODE_MIN,
  13180   OPCODE_MAX,
  13181   OPCODE_MINU,
  13182   OPCODE_MAXU,
  13183   OPCODE_NSA,
  13184   OPCODE_NSAU,
  13185   OPCODE_SEXT,
  13186   OPCODE_L32AI,
  13187   OPCODE_S32RI,
  13188   OPCODE_S32C1I,
  13189   OPCODE_RSR_SCOMPARE1,
  13190   OPCODE_WSR_SCOMPARE1,
  13191   OPCODE_XSR_SCOMPARE1,
  13192   OPCODE_RSR_ATOMCTL,
  13193   OPCODE_WSR_ATOMCTL,
  13194   OPCODE_XSR_ATOMCTL,
  13195   OPCODE_QUOU,
  13196   OPCODE_QUOS,
  13197   OPCODE_REMU,
  13198   OPCODE_REMS,
  13199   OPCODE_RER,
  13200   OPCODE_WER,
  13201   OPCODE_RUR_EXPSTATE,
  13202   OPCODE_WUR_EXPSTATE,
  13203   OPCODE_READ_IMPWIRE,
  13204   OPCODE_SETB_EXPSTATE,
  13205   OPCODE_CLRB_EXPSTATE,
  13206   OPCODE_WRMSK_EXPSTATE
  13207 };
  13208 
  13209 
  13210 /* Slot-specific opcode decode functions.  */
  13211 
  13212 static int
  13213 Slot_inst_decode (const xtensa_insnbuf insn)
  13214 {
  13215   switch (Field_op0_Slot_inst_get (insn))
  13216     {
  13217     case 0:
  13218       switch (Field_op1_Slot_inst_get (insn))
  13219 	{
  13220 	case 0:
  13221 	  switch (Field_op2_Slot_inst_get (insn))
  13222 	    {
  13223 	    case 0:
  13224 	      switch (Field_r_Slot_inst_get (insn))
  13225 		{
  13226 		case 0:
  13227 		  switch (Field_m_Slot_inst_get (insn))
  13228 		    {
  13229 		    case 0:
  13230 		      if (Field_s_Slot_inst_get (insn) == 0 &&
  13231 			  Field_n_Slot_inst_get (insn) == 0)
  13232 			return OPCODE_ILL;
  13233 		      break;
  13234 		    case 2:
  13235 		      switch (Field_n_Slot_inst_get (insn))
  13236 			{
  13237 			case 0:
  13238 			  return OPCODE_RET;
  13239 			case 1:
  13240 			  return OPCODE_RETW;
  13241 			case 2:
  13242 			  return OPCODE_JX;
  13243 			}
  13244 		      break;
  13245 		    case 3:
  13246 		      switch (Field_n_Slot_inst_get (insn))
  13247 			{
  13248 			case 0:
  13249 			  return OPCODE_CALLX0;
  13250 			case 1:
  13251 			  return OPCODE_CALLX4;
  13252 			case 2:
  13253 			  return OPCODE_CALLX8;
  13254 			case 3:
  13255 			  return OPCODE_CALLX12;
  13256 			}
  13257 		      break;
  13258 		    }
  13259 		  break;
  13260 		case 1:
  13261 		  return OPCODE_MOVSP;
  13262 		case 2:
  13263 		  if (Field_s_Slot_inst_get (insn) == 0)
  13264 		    {
  13265 		      switch (Field_t_Slot_inst_get (insn))
  13266 			{
  13267 			case 0:
  13268 			  return OPCODE_ISYNC;
  13269 			case 1:
  13270 			  return OPCODE_RSYNC;
  13271 			case 2:
  13272 			  return OPCODE_ESYNC;
  13273 			case 3:
  13274 			  return OPCODE_DSYNC;
  13275 			case 8:
  13276 			  return OPCODE_EXCW;
  13277 			case 12:
  13278 			  return OPCODE_MEMW;
  13279 			case 13:
  13280 			  return OPCODE_EXTW;
  13281 			case 15:
  13282 			  return OPCODE_NOP;
  13283 			}
  13284 		    }
  13285 		  break;
  13286 		case 3:
  13287 		  switch (Field_t_Slot_inst_get (insn))
  13288 		    {
  13289 		    case 0:
  13290 		      switch (Field_s_Slot_inst_get (insn))
  13291 			{
  13292 			case 0:
  13293 			  return OPCODE_RFE;
  13294 			case 2:
  13295 			  return OPCODE_RFDE;
  13296 			case 4:
  13297 			  return OPCODE_RFWO;
  13298 			case 5:
  13299 			  return OPCODE_RFWU;
  13300 			}
  13301 		      break;
  13302 		    case 1:
  13303 		      return OPCODE_RFI;
  13304 		    }
  13305 		  break;
  13306 		case 4:
  13307 		  return OPCODE_BREAK;
  13308 		case 5:
  13309 		  switch (Field_s_Slot_inst_get (insn))
  13310 		    {
  13311 		    case 0:
  13312 		      if (Field_t_Slot_inst_get (insn) == 0)
  13313 			return OPCODE_SYSCALL;
  13314 		      break;
  13315 		    case 1:
  13316 		      if (Field_t_Slot_inst_get (insn) == 0)
  13317 			return OPCODE_SIMCALL;
  13318 		      break;
  13319 		    }
  13320 		  break;
  13321 		case 6:
  13322 		  return OPCODE_RSIL;
  13323 		case 7:
  13324 		  if (Field_t_Slot_inst_get (insn) == 0)
  13325 		    return OPCODE_WAITI;
  13326 		  break;
  13327 		}
  13328 	      break;
  13329 	    case 1:
  13330 	      return OPCODE_AND;
  13331 	    case 2:
  13332 	      return OPCODE_OR;
  13333 	    case 3:
  13334 	      return OPCODE_XOR;
  13335 	    case 4:
  13336 	      switch (Field_r_Slot_inst_get (insn))
  13337 		{
  13338 		case 0:
  13339 		  if (Field_t_Slot_inst_get (insn) == 0)
  13340 		    return OPCODE_SSR;
  13341 		  break;
  13342 		case 1:
  13343 		  if (Field_t_Slot_inst_get (insn) == 0)
  13344 		    return OPCODE_SSL;
  13345 		  break;
  13346 		case 2:
  13347 		  if (Field_t_Slot_inst_get (insn) == 0)
  13348 		    return OPCODE_SSA8L;
  13349 		  break;
  13350 		case 3:
  13351 		  if (Field_t_Slot_inst_get (insn) == 0)
  13352 		    return OPCODE_SSA8B;
  13353 		  break;
  13354 		case 4:
  13355 		  if (Field_thi3_Slot_inst_get (insn) == 0)
  13356 		    return OPCODE_SSAI;
  13357 		  break;
  13358 		case 6:
  13359 		  return OPCODE_RER;
  13360 		case 7:
  13361 		  return OPCODE_WER;
  13362 		case 8:
  13363 		  if (Field_s_Slot_inst_get (insn) == 0)
  13364 		    return OPCODE_ROTW;
  13365 		  break;
  13366 		case 14:
  13367 		  return OPCODE_NSA;
  13368 		case 15:
  13369 		  return OPCODE_NSAU;
  13370 		}
  13371 	      break;
  13372 	    case 5:
  13373 	      switch (Field_r_Slot_inst_get (insn))
  13374 		{
  13375 		case 1:
  13376 		  return OPCODE_HWWITLBA;
  13377 		case 3:
  13378 		  return OPCODE_RITLB0;
  13379 		case 4:
  13380 		  if (Field_t_Slot_inst_get (insn) == 0)
  13381 		    return OPCODE_IITLB;
  13382 		  break;
  13383 		case 5:
  13384 		  return OPCODE_PITLB;
  13385 		case 6:
  13386 		  return OPCODE_WITLB;
  13387 		case 7:
  13388 		  return OPCODE_RITLB1;
  13389 		case 9:
  13390 		  return OPCODE_HWWDTLBA;
  13391 		case 11:
  13392 		  return OPCODE_RDTLB0;
  13393 		case 12:
  13394 		  if (Field_t_Slot_inst_get (insn) == 0)
  13395 		    return OPCODE_IDTLB;
  13396 		  break;
  13397 		case 13:
  13398 		  return OPCODE_PDTLB;
  13399 		case 14:
  13400 		  return OPCODE_WDTLB;
  13401 		case 15:
  13402 		  return OPCODE_RDTLB1;
  13403 		}
  13404 	      break;
  13405 	    case 6:
  13406 	      switch (Field_s_Slot_inst_get (insn))
  13407 		{
  13408 		case 0:
  13409 		  return OPCODE_NEG;
  13410 		case 1:
  13411 		  return OPCODE_ABS;
  13412 		}
  13413 	      break;
  13414 	    case 8:
  13415 	      return OPCODE_ADD;
  13416 	    case 9:
  13417 	      return OPCODE_ADDX2;
  13418 	    case 10:
  13419 	      return OPCODE_ADDX4;
  13420 	    case 11:
  13421 	      return OPCODE_ADDX8;
  13422 	    case 12:
  13423 	      return OPCODE_SUB;
  13424 	    case 13:
  13425 	      return OPCODE_SUBX2;
  13426 	    case 14:
  13427 	      return OPCODE_SUBX4;
  13428 	    case 15:
  13429 	      return OPCODE_SUBX8;
  13430 	    }
  13431 	  break;
  13432 	case 1:
  13433 	  switch (Field_op2_Slot_inst_get (insn))
  13434 	    {
  13435 	    case 0:
  13436 	    case 1:
  13437 	      return OPCODE_SLLI;
  13438 	    case 2:
  13439 	    case 3:
  13440 	      return OPCODE_SRAI;
  13441 	    case 4:
  13442 	      return OPCODE_SRLI;
  13443 	    case 6:
  13444 	      switch (Field_sr_Slot_inst_get (insn))
  13445 		{
  13446 		case 0:
  13447 		  return OPCODE_XSR_LBEG;
  13448 		case 1:
  13449 		  return OPCODE_XSR_LEND;
  13450 		case 2:
  13451 		  return OPCODE_XSR_LCOUNT;
  13452 		case 3:
  13453 		  return OPCODE_XSR_SAR;
  13454 		case 5:
  13455 		  return OPCODE_XSR_LITBASE;
  13456 		case 12:
  13457 		  return OPCODE_XSR_SCOMPARE1;
  13458 		case 16:
  13459 		  return OPCODE_XSR_ACCLO;
  13460 		case 17:
  13461 		  return OPCODE_XSR_ACCHI;
  13462 		case 32:
  13463 		  return OPCODE_XSR_M0;
  13464 		case 33:
  13465 		  return OPCODE_XSR_M1;
  13466 		case 34:
  13467 		  return OPCODE_XSR_M2;
  13468 		case 35:
  13469 		  return OPCODE_XSR_M3;
  13470 		case 72:
  13471 		  return OPCODE_XSR_WINDOWBASE;
  13472 		case 73:
  13473 		  return OPCODE_XSR_WINDOWSTART;
  13474 		case 83:
  13475 		  return OPCODE_XSR_PTEVADDR;
  13476 		case 90:
  13477 		  return OPCODE_XSR_RASID;
  13478 		case 91:
  13479 		  return OPCODE_XSR_ITLBCFG;
  13480 		case 92:
  13481 		  return OPCODE_XSR_DTLBCFG;
  13482 		case 96:
  13483 		  return OPCODE_XSR_IBREAKENABLE;
  13484 		case 99:
  13485 		  return OPCODE_XSR_ATOMCTL;
  13486 		case 104:
  13487 		  return OPCODE_XSR_DDR;
  13488 		case 128:
  13489 		  return OPCODE_XSR_IBREAKA0;
  13490 		case 129:
  13491 		  return OPCODE_XSR_IBREAKA1;
  13492 		case 144:
  13493 		  return OPCODE_XSR_DBREAKA0;
  13494 		case 145:
  13495 		  return OPCODE_XSR_DBREAKA1;
  13496 		case 160:
  13497 		  return OPCODE_XSR_DBREAKC0;
  13498 		case 161:
  13499 		  return OPCODE_XSR_DBREAKC1;
  13500 		case 177:
  13501 		  return OPCODE_XSR_EPC1;
  13502 		case 178:
  13503 		  return OPCODE_XSR_EPC2;
  13504 		case 179:
  13505 		  return OPCODE_XSR_EPC3;
  13506 		case 180:
  13507 		  return OPCODE_XSR_EPC4;
  13508 		case 181:
  13509 		  return OPCODE_XSR_EPC5;
  13510 		case 182:
  13511 		  return OPCODE_XSR_EPC6;
  13512 		case 183:
  13513 		  return OPCODE_XSR_EPC7;
  13514 		case 192:
  13515 		  return OPCODE_XSR_DEPC;
  13516 		case 194:
  13517 		  return OPCODE_XSR_EPS2;
  13518 		case 195:
  13519 		  return OPCODE_XSR_EPS3;
  13520 		case 196:
  13521 		  return OPCODE_XSR_EPS4;
  13522 		case 197:
  13523 		  return OPCODE_XSR_EPS5;
  13524 		case 198:
  13525 		  return OPCODE_XSR_EPS6;
  13526 		case 199:
  13527 		  return OPCODE_XSR_EPS7;
  13528 		case 209:
  13529 		  return OPCODE_XSR_EXCSAVE1;
  13530 		case 210:
  13531 		  return OPCODE_XSR_EXCSAVE2;
  13532 		case 211:
  13533 		  return OPCODE_XSR_EXCSAVE3;
  13534 		case 212:
  13535 		  return OPCODE_XSR_EXCSAVE4;
  13536 		case 213:
  13537 		  return OPCODE_XSR_EXCSAVE5;
  13538 		case 214:
  13539 		  return OPCODE_XSR_EXCSAVE6;
  13540 		case 215:
  13541 		  return OPCODE_XSR_EXCSAVE7;
  13542 		case 224:
  13543 		  return OPCODE_XSR_CPENABLE;
  13544 		case 228:
  13545 		  return OPCODE_XSR_INTENABLE;
  13546 		case 230:
  13547 		  return OPCODE_XSR_PS;
  13548 		case 231:
  13549 		  return OPCODE_XSR_VECBASE;
  13550 		case 232:
  13551 		  return OPCODE_XSR_EXCCAUSE;
  13552 		case 233:
  13553 		  return OPCODE_XSR_DEBUGCAUSE;
  13554 		case 234:
  13555 		  return OPCODE_XSR_CCOUNT;
  13556 		case 236:
  13557 		  return OPCODE_XSR_ICOUNT;
  13558 		case 237:
  13559 		  return OPCODE_XSR_ICOUNTLEVEL;
  13560 		case 238:
  13561 		  return OPCODE_XSR_EXCVADDR;
  13562 		case 240:
  13563 		  return OPCODE_XSR_CCOMPARE0;
  13564 		case 241:
  13565 		  return OPCODE_XSR_CCOMPARE1;
  13566 		case 242:
  13567 		  return OPCODE_XSR_CCOMPARE2;
  13568 		case 244:
  13569 		  return OPCODE_XSR_MISC0;
  13570 		case 245:
  13571 		  return OPCODE_XSR_MISC1;
  13572 		}
  13573 	      break;
  13574 	    case 8:
  13575 	      return OPCODE_SRC;
  13576 	    case 9:
  13577 	      if (Field_s_Slot_inst_get (insn) == 0)
  13578 		return OPCODE_SRL;
  13579 	      break;
  13580 	    case 10:
  13581 	      if (Field_t_Slot_inst_get (insn) == 0)
  13582 		return OPCODE_SLL;
  13583 	      break;
  13584 	    case 11:
  13585 	      if (Field_s_Slot_inst_get (insn) == 0)
  13586 		return OPCODE_SRA;
  13587 	      break;
  13588 	    case 12:
  13589 	      return OPCODE_MUL16U;
  13590 	    case 13:
  13591 	      return OPCODE_MUL16S;
  13592 	    case 15:
  13593 	      switch (Field_r_Slot_inst_get (insn))
  13594 		{
  13595 		case 0:
  13596 		  return OPCODE_LICT;
  13597 		case 1:
  13598 		  return OPCODE_SICT;
  13599 		case 2:
  13600 		  return OPCODE_LICW;
  13601 		case 3:
  13602 		  return OPCODE_SICW;
  13603 		case 8:
  13604 		  return OPCODE_LDCT;
  13605 		case 9:
  13606 		  return OPCODE_SDCT;
  13607 		case 14:
  13608 		  if (Field_t_Slot_inst_get (insn) == 0)
  13609 		    return OPCODE_RFDO;
  13610 		  if (Field_t_Slot_inst_get (insn) == 1)
  13611 		    return OPCODE_RFDD;
  13612 		  break;
  13613 		case 15:
  13614 		  return OPCODE_LDPTE;
  13615 		}
  13616 	      break;
  13617 	    }
  13618 	  break;
  13619 	case 2:
  13620 	  switch (Field_op2_Slot_inst_get (insn))
  13621 	    {
  13622 	    case 8:
  13623 	      return OPCODE_MULL;
  13624 	    case 12:
  13625 	      return OPCODE_QUOU;
  13626 	    case 13:
  13627 	      return OPCODE_QUOS;
  13628 	    case 14:
  13629 	      return OPCODE_REMU;
  13630 	    case 15:
  13631 	      return OPCODE_REMS;
  13632 	    }
  13633 	  break;
  13634 	case 3:
  13635 	  switch (Field_op2_Slot_inst_get (insn))
  13636 	    {
  13637 	    case 0:
  13638 	      switch (Field_sr_Slot_inst_get (insn))
  13639 		{
  13640 		case 0:
  13641 		  return OPCODE_RSR_LBEG;
  13642 		case 1:
  13643 		  return OPCODE_RSR_LEND;
  13644 		case 2:
  13645 		  return OPCODE_RSR_LCOUNT;
  13646 		case 3:
  13647 		  return OPCODE_RSR_SAR;
  13648 		case 5:
  13649 		  return OPCODE_RSR_LITBASE;
  13650 		case 12:
  13651 		  return OPCODE_RSR_SCOMPARE1;
  13652 		case 16:
  13653 		  return OPCODE_RSR_ACCLO;
  13654 		case 17:
  13655 		  return OPCODE_RSR_ACCHI;
  13656 		case 32:
  13657 		  return OPCODE_RSR_M0;
  13658 		case 33:
  13659 		  return OPCODE_RSR_M1;
  13660 		case 34:
  13661 		  return OPCODE_RSR_M2;
  13662 		case 35:
  13663 		  return OPCODE_RSR_M3;
  13664 		case 72:
  13665 		  return OPCODE_RSR_WINDOWBASE;
  13666 		case 73:
  13667 		  return OPCODE_RSR_WINDOWSTART;
  13668 		case 83:
  13669 		  return OPCODE_RSR_PTEVADDR;
  13670 		case 90:
  13671 		  return OPCODE_RSR_RASID;
  13672 		case 91:
  13673 		  return OPCODE_RSR_ITLBCFG;
  13674 		case 92:
  13675 		  return OPCODE_RSR_DTLBCFG;
  13676 		case 96:
  13677 		  return OPCODE_RSR_IBREAKENABLE;
  13678 		case 99:
  13679 		  return OPCODE_RSR_ATOMCTL;
  13680 		case 104:
  13681 		  return OPCODE_RSR_DDR;
  13682 		case 128:
  13683 		  return OPCODE_RSR_IBREAKA0;
  13684 		case 129:
  13685 		  return OPCODE_RSR_IBREAKA1;
  13686 		case 144:
  13687 		  return OPCODE_RSR_DBREAKA0;
  13688 		case 145:
  13689 		  return OPCODE_RSR_DBREAKA1;
  13690 		case 160:
  13691 		  return OPCODE_RSR_DBREAKC0;
  13692 		case 161:
  13693 		  return OPCODE_RSR_DBREAKC1;
  13694 		case 176:
  13695 		  return OPCODE_RSR_176;
  13696 		case 177:
  13697 		  return OPCODE_RSR_EPC1;
  13698 		case 178:
  13699 		  return OPCODE_RSR_EPC2;
  13700 		case 179:
  13701 		  return OPCODE_RSR_EPC3;
  13702 		case 180:
  13703 		  return OPCODE_RSR_EPC4;
  13704 		case 181:
  13705 		  return OPCODE_RSR_EPC5;
  13706 		case 182:
  13707 		  return OPCODE_RSR_EPC6;
  13708 		case 183:
  13709 		  return OPCODE_RSR_EPC7;
  13710 		case 192:
  13711 		  return OPCODE_RSR_DEPC;
  13712 		case 194:
  13713 		  return OPCODE_RSR_EPS2;
  13714 		case 195:
  13715 		  return OPCODE_RSR_EPS3;
  13716 		case 196:
  13717 		  return OPCODE_RSR_EPS4;
  13718 		case 197:
  13719 		  return OPCODE_RSR_EPS5;
  13720 		case 198:
  13721 		  return OPCODE_RSR_EPS6;
  13722 		case 199:
  13723 		  return OPCODE_RSR_EPS7;
  13724 		case 208:
  13725 		  return OPCODE_RSR_208;
  13726 		case 209:
  13727 		  return OPCODE_RSR_EXCSAVE1;
  13728 		case 210:
  13729 		  return OPCODE_RSR_EXCSAVE2;
  13730 		case 211:
  13731 		  return OPCODE_RSR_EXCSAVE3;
  13732 		case 212:
  13733 		  return OPCODE_RSR_EXCSAVE4;
  13734 		case 213:
  13735 		  return OPCODE_RSR_EXCSAVE5;
  13736 		case 214:
  13737 		  return OPCODE_RSR_EXCSAVE6;
  13738 		case 215:
  13739 		  return OPCODE_RSR_EXCSAVE7;
  13740 		case 224:
  13741 		  return OPCODE_RSR_CPENABLE;
  13742 		case 226:
  13743 		  return OPCODE_RSR_INTERRUPT;
  13744 		case 228:
  13745 		  return OPCODE_RSR_INTENABLE;
  13746 		case 230:
  13747 		  return OPCODE_RSR_PS;
  13748 		case 231:
  13749 		  return OPCODE_RSR_VECBASE;
  13750 		case 232:
  13751 		  return OPCODE_RSR_EXCCAUSE;
  13752 		case 233:
  13753 		  return OPCODE_RSR_DEBUGCAUSE;
  13754 		case 234:
  13755 		  return OPCODE_RSR_CCOUNT;
  13756 		case 235:
  13757 		  return OPCODE_RSR_PRID;
  13758 		case 236:
  13759 		  return OPCODE_RSR_ICOUNT;
  13760 		case 237:
  13761 		  return OPCODE_RSR_ICOUNTLEVEL;
  13762 		case 238:
  13763 		  return OPCODE_RSR_EXCVADDR;
  13764 		case 240:
  13765 		  return OPCODE_RSR_CCOMPARE0;
  13766 		case 241:
  13767 		  return OPCODE_RSR_CCOMPARE1;
  13768 		case 242:
  13769 		  return OPCODE_RSR_CCOMPARE2;
  13770 		case 244:
  13771 		  return OPCODE_RSR_MISC0;
  13772 		case 245:
  13773 		  return OPCODE_RSR_MISC1;
  13774 		}
  13775 	      break;
  13776 	    case 1:
  13777 	      switch (Field_sr_Slot_inst_get (insn))
  13778 		{
  13779 		case 0:
  13780 		  return OPCODE_WSR_LBEG;
  13781 		case 1:
  13782 		  return OPCODE_WSR_LEND;
  13783 		case 2:
  13784 		  return OPCODE_WSR_LCOUNT;
  13785 		case 3:
  13786 		  return OPCODE_WSR_SAR;
  13787 		case 5:
  13788 		  return OPCODE_WSR_LITBASE;
  13789 		case 12:
  13790 		  return OPCODE_WSR_SCOMPARE1;
  13791 		case 16:
  13792 		  return OPCODE_WSR_ACCLO;
  13793 		case 17:
  13794 		  return OPCODE_WSR_ACCHI;
  13795 		case 32:
  13796 		  return OPCODE_WSR_M0;
  13797 		case 33:
  13798 		  return OPCODE_WSR_M1;
  13799 		case 34:
  13800 		  return OPCODE_WSR_M2;
  13801 		case 35:
  13802 		  return OPCODE_WSR_M3;
  13803 		case 72:
  13804 		  return OPCODE_WSR_WINDOWBASE;
  13805 		case 73:
  13806 		  return OPCODE_WSR_WINDOWSTART;
  13807 		case 83:
  13808 		  return OPCODE_WSR_PTEVADDR;
  13809 		case 89:
  13810 		  return OPCODE_WSR_MMID;
  13811 		case 90:
  13812 		  return OPCODE_WSR_RASID;
  13813 		case 91:
  13814 		  return OPCODE_WSR_ITLBCFG;
  13815 		case 92:
  13816 		  return OPCODE_WSR_DTLBCFG;
  13817 		case 96:
  13818 		  return OPCODE_WSR_IBREAKENABLE;
  13819 		case 99:
  13820 		  return OPCODE_WSR_ATOMCTL;
  13821 		case 104:
  13822 		  return OPCODE_WSR_DDR;
  13823 		case 128:
  13824 		  return OPCODE_WSR_IBREAKA0;
  13825 		case 129:
  13826 		  return OPCODE_WSR_IBREAKA1;
  13827 		case 144:
  13828 		  return OPCODE_WSR_DBREAKA0;
  13829 		case 145:
  13830 		  return OPCODE_WSR_DBREAKA1;
  13831 		case 160:
  13832 		  return OPCODE_WSR_DBREAKC0;
  13833 		case 161:
  13834 		  return OPCODE_WSR_DBREAKC1;
  13835 		case 176:
  13836 		  return OPCODE_WSR_176;
  13837 		case 177:
  13838 		  return OPCODE_WSR_EPC1;
  13839 		case 178:
  13840 		  return OPCODE_WSR_EPC2;
  13841 		case 179:
  13842 		  return OPCODE_WSR_EPC3;
  13843 		case 180:
  13844 		  return OPCODE_WSR_EPC4;
  13845 		case 181:
  13846 		  return OPCODE_WSR_EPC5;
  13847 		case 182:
  13848 		  return OPCODE_WSR_EPC6;
  13849 		case 183:
  13850 		  return OPCODE_WSR_EPC7;
  13851 		case 192:
  13852 		  return OPCODE_WSR_DEPC;
  13853 		case 194:
  13854 		  return OPCODE_WSR_EPS2;
  13855 		case 195:
  13856 		  return OPCODE_WSR_EPS3;
  13857 		case 196:
  13858 		  return OPCODE_WSR_EPS4;
  13859 		case 197:
  13860 		  return OPCODE_WSR_EPS5;
  13861 		case 198:
  13862 		  return OPCODE_WSR_EPS6;
  13863 		case 199:
  13864 		  return OPCODE_WSR_EPS7;
  13865 		case 209:
  13866 		  return OPCODE_WSR_EXCSAVE1;
  13867 		case 210:
  13868 		  return OPCODE_WSR_EXCSAVE2;
  13869 		case 211:
  13870 		  return OPCODE_WSR_EXCSAVE3;
  13871 		case 212:
  13872 		  return OPCODE_WSR_EXCSAVE4;
  13873 		case 213:
  13874 		  return OPCODE_WSR_EXCSAVE5;
  13875 		case 214:
  13876 		  return OPCODE_WSR_EXCSAVE6;
  13877 		case 215:
  13878 		  return OPCODE_WSR_EXCSAVE7;
  13879 		case 224:
  13880 		  return OPCODE_WSR_CPENABLE;
  13881 		case 226:
  13882 		  return OPCODE_WSR_INTSET;
  13883 		case 227:
  13884 		  return OPCODE_WSR_INTCLEAR;
  13885 		case 228:
  13886 		  return OPCODE_WSR_INTENABLE;
  13887 		case 230:
  13888 		  return OPCODE_WSR_PS;
  13889 		case 231:
  13890 		  return OPCODE_WSR_VECBASE;
  13891 		case 232:
  13892 		  return OPCODE_WSR_EXCCAUSE;
  13893 		case 233:
  13894 		  return OPCODE_WSR_DEBUGCAUSE;
  13895 		case 234:
  13896 		  return OPCODE_WSR_CCOUNT;
  13897 		case 236:
  13898 		  return OPCODE_WSR_ICOUNT;
  13899 		case 237:
  13900 		  return OPCODE_WSR_ICOUNTLEVEL;
  13901 		case 238:
  13902 		  return OPCODE_WSR_EXCVADDR;
  13903 		case 240:
  13904 		  return OPCODE_WSR_CCOMPARE0;
  13905 		case 241:
  13906 		  return OPCODE_WSR_CCOMPARE1;
  13907 		case 242:
  13908 		  return OPCODE_WSR_CCOMPARE2;
  13909 		case 244:
  13910 		  return OPCODE_WSR_MISC0;
  13911 		case 245:
  13912 		  return OPCODE_WSR_MISC1;
  13913 		}
  13914 	      break;
  13915 	    case 2:
  13916 	      return OPCODE_SEXT;
  13917 	    case 3:
  13918 	      return OPCODE_CLAMPS;
  13919 	    case 4:
  13920 	      return OPCODE_MIN;
  13921 	    case 5:
  13922 	      return OPCODE_MAX;
  13923 	    case 6:
  13924 	      return OPCODE_MINU;
  13925 	    case 7:
  13926 	      return OPCODE_MAXU;
  13927 	    case 8:
  13928 	      return OPCODE_MOVEQZ;
  13929 	    case 9:
  13930 	      return OPCODE_MOVNEZ;
  13931 	    case 10:
  13932 	      return OPCODE_MOVLTZ;
  13933 	    case 11:
  13934 	      return OPCODE_MOVGEZ;
  13935 	    case 14:
  13936 	      switch (Field_st_Slot_inst_get (insn))
  13937 		{
  13938 		case 230:
  13939 		  return OPCODE_RUR_EXPSTATE;
  13940 		case 231:
  13941 		  return OPCODE_RUR_THREADPTR;
  13942 		}
  13943 	      break;
  13944 	    case 15:
  13945 	      switch (Field_sr_Slot_inst_get (insn))
  13946 		{
  13947 		case 230:
  13948 		  return OPCODE_WUR_EXPSTATE;
  13949 		case 231:
  13950 		  return OPCODE_WUR_THREADPTR;
  13951 		}
  13952 	      break;
  13953 	    }
  13954 	  break;
  13955 	case 4:
  13956 	case 5:
  13957 	  return OPCODE_EXTUI;
  13958 	case 9:
  13959 	  switch (Field_op2_Slot_inst_get (insn))
  13960 	    {
  13961 	    case 0:
  13962 	      return OPCODE_L32E;
  13963 	    case 4:
  13964 	      return OPCODE_S32E;
  13965 	    }
  13966 	  break;
  13967 	}
  13968       switch (Field_r_Slot_inst_get (insn))
  13969 	{
  13970 	case 0:
  13971 	  if (Field_s_Slot_inst_get (insn) == 0 &&
  13972 	      Field_op2_Slot_inst_get (insn) == 0 &&
  13973 	      Field_op1_Slot_inst_get (insn) == 14)
  13974 	    return OPCODE_READ_IMPWIRE;
  13975 	  break;
  13976 	case 1:
  13977 	  if (Field_s3to1_Slot_inst_get (insn) == 0 &&
  13978 	      Field_op2_Slot_inst_get (insn) == 0 &&
  13979 	      Field_op1_Slot_inst_get (insn) == 14)
  13980 	    return OPCODE_SETB_EXPSTATE;
  13981 	  if (Field_s3to1_Slot_inst_get (insn) == 1 &&
  13982 	      Field_op2_Slot_inst_get (insn) == 0 &&
  13983 	      Field_op1_Slot_inst_get (insn) == 14)
  13984 	    return OPCODE_CLRB_EXPSTATE;
  13985 	  break;
  13986 	case 2:
  13987 	  if (Field_op2_Slot_inst_get (insn) == 0 &&
  13988 	      Field_op1_Slot_inst_get (insn) == 14)
  13989 	    return OPCODE_WRMSK_EXPSTATE;
  13990 	  break;
  13991 	}
  13992       break;
  13993     case 1:
  13994       return OPCODE_L32R;
  13995     case 2:
  13996       switch (Field_r_Slot_inst_get (insn))
  13997 	{
  13998 	case 0:
  13999 	  return OPCODE_L8UI;
  14000 	case 1:
  14001 	  return OPCODE_L16UI;
  14002 	case 2:
  14003 	  return OPCODE_L32I;
  14004 	case 4:
  14005 	  return OPCODE_S8I;
  14006 	case 5:
  14007 	  return OPCODE_S16I;
  14008 	case 6:
  14009 	  return OPCODE_S32I;
  14010 	case 7:
  14011 	  switch (Field_t_Slot_inst_get (insn))
  14012 	    {
  14013 	    case 0:
  14014 	      return OPCODE_DPFR;
  14015 	    case 1:
  14016 	      return OPCODE_DPFW;
  14017 	    case 2:
  14018 	      return OPCODE_DPFRO;
  14019 	    case 3:
  14020 	      return OPCODE_DPFWO;
  14021 	    case 4:
  14022 	      return OPCODE_DHWB;
  14023 	    case 5:
  14024 	      return OPCODE_DHWBI;
  14025 	    case 6:
  14026 	      return OPCODE_DHI;
  14027 	    case 7:
  14028 	      return OPCODE_DII;
  14029 	    case 8:
  14030 	      switch (Field_op1_Slot_inst_get (insn))
  14031 		{
  14032 		case 0:
  14033 		  return OPCODE_DPFL;
  14034 		case 2:
  14035 		  return OPCODE_DHU;
  14036 		case 3:
  14037 		  return OPCODE_DIU;
  14038 		case 4:
  14039 		  return OPCODE_DIWB;
  14040 		case 5:
  14041 		  return OPCODE_DIWBI;
  14042 		}
  14043 	      break;
  14044 	    case 12:
  14045 	      return OPCODE_IPF;
  14046 	    case 13:
  14047 	      switch (Field_op1_Slot_inst_get (insn))
  14048 		{
  14049 		case 0:
  14050 		  return OPCODE_IPFL;
  14051 		case 2:
  14052 		  return OPCODE_IHU;
  14053 		case 3:
  14054 		  return OPCODE_IIU;
  14055 		}
  14056 	      break;
  14057 	    case 14:
  14058 	      return OPCODE_IHI;
  14059 	    case 15:
  14060 	      return OPCODE_III;
  14061 	    }
  14062 	  break;
  14063 	case 9:
  14064 	  return OPCODE_L16SI;
  14065 	case 10:
  14066 	  return OPCODE_MOVI;
  14067 	case 11:
  14068 	  return OPCODE_L32AI;
  14069 	case 12:
  14070 	  return OPCODE_ADDI;
  14071 	case 13:
  14072 	  return OPCODE_ADDMI;
  14073 	case 14:
  14074 	  return OPCODE_S32C1I;
  14075 	case 15:
  14076 	  return OPCODE_S32RI;
  14077 	}
  14078       break;
  14079     case 4:
  14080       switch (Field_op2_Slot_inst_get (insn))
  14081 	{
  14082 	case 0:
  14083 	  switch (Field_op1_Slot_inst_get (insn))
  14084 	    {
  14085 	    case 8:
  14086 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14087 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14088 		  Field_r3_Slot_inst_get (insn) == 0)
  14089 		return OPCODE_MULA_DD_LL_LDINC;
  14090 	      break;
  14091 	    case 9:
  14092 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14093 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14094 		  Field_r3_Slot_inst_get (insn) == 0)
  14095 		return OPCODE_MULA_DD_HL_LDINC;
  14096 	      break;
  14097 	    case 10:
  14098 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14099 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14100 		  Field_r3_Slot_inst_get (insn) == 0)
  14101 		return OPCODE_MULA_DD_LH_LDINC;
  14102 	      break;
  14103 	    case 11:
  14104 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14105 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14106 		  Field_r3_Slot_inst_get (insn) == 0)
  14107 		return OPCODE_MULA_DD_HH_LDINC;
  14108 	      break;
  14109 	    }
  14110 	  break;
  14111 	case 1:
  14112 	  switch (Field_op1_Slot_inst_get (insn))
  14113 	    {
  14114 	    case 8:
  14115 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14116 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14117 		  Field_r3_Slot_inst_get (insn) == 0)
  14118 		return OPCODE_MULA_DD_LL_LDDEC;
  14119 	      break;
  14120 	    case 9:
  14121 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14122 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14123 		  Field_r3_Slot_inst_get (insn) == 0)
  14124 		return OPCODE_MULA_DD_HL_LDDEC;
  14125 	      break;
  14126 	    case 10:
  14127 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14128 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14129 		  Field_r3_Slot_inst_get (insn) == 0)
  14130 		return OPCODE_MULA_DD_LH_LDDEC;
  14131 	      break;
  14132 	    case 11:
  14133 	      if (Field_t3_Slot_inst_get (insn) == 0 &&
  14134 		  Field_tlo_Slot_inst_get (insn) == 0 &&
  14135 		  Field_r3_Slot_inst_get (insn) == 0)
  14136 		return OPCODE_MULA_DD_HH_LDDEC;
  14137 	      break;
  14138 	    }
  14139 	  break;
  14140 	case 2:
  14141 	  switch (Field_op1_Slot_inst_get (insn))
  14142 	    {
  14143 	    case 4:
  14144 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14145 		  Field_w_Slot_inst_get (insn) == 0 &&
  14146 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14147 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14148 		  Field_tlo_Slot_inst_get (insn) == 0)
  14149 		return OPCODE_MUL_DD_LL;
  14150 	      break;
  14151 	    case 5:
  14152 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14153 		  Field_w_Slot_inst_get (insn) == 0 &&
  14154 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14155 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14156 		  Field_tlo_Slot_inst_get (insn) == 0)
  14157 		return OPCODE_MUL_DD_HL;
  14158 	      break;
  14159 	    case 6:
  14160 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14161 		  Field_w_Slot_inst_get (insn) == 0 &&
  14162 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14163 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14164 		  Field_tlo_Slot_inst_get (insn) == 0)
  14165 		return OPCODE_MUL_DD_LH;
  14166 	      break;
  14167 	    case 7:
  14168 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14169 		  Field_w_Slot_inst_get (insn) == 0 &&
  14170 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14171 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14172 		  Field_tlo_Slot_inst_get (insn) == 0)
  14173 		return OPCODE_MUL_DD_HH;
  14174 	      break;
  14175 	    case 8:
  14176 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14177 		  Field_w_Slot_inst_get (insn) == 0 &&
  14178 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14179 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14180 		  Field_tlo_Slot_inst_get (insn) == 0)
  14181 		return OPCODE_MULA_DD_LL;
  14182 	      break;
  14183 	    case 9:
  14184 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14185 		  Field_w_Slot_inst_get (insn) == 0 &&
  14186 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14187 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14188 		  Field_tlo_Slot_inst_get (insn) == 0)
  14189 		return OPCODE_MULA_DD_HL;
  14190 	      break;
  14191 	    case 10:
  14192 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14193 		  Field_w_Slot_inst_get (insn) == 0 &&
  14194 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14195 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14196 		  Field_tlo_Slot_inst_get (insn) == 0)
  14197 		return OPCODE_MULA_DD_LH;
  14198 	      break;
  14199 	    case 11:
  14200 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14201 		  Field_w_Slot_inst_get (insn) == 0 &&
  14202 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14203 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14204 		  Field_tlo_Slot_inst_get (insn) == 0)
  14205 		return OPCODE_MULA_DD_HH;
  14206 	      break;
  14207 	    case 12:
  14208 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14209 		  Field_w_Slot_inst_get (insn) == 0 &&
  14210 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14211 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14212 		  Field_tlo_Slot_inst_get (insn) == 0)
  14213 		return OPCODE_MULS_DD_LL;
  14214 	      break;
  14215 	    case 13:
  14216 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14217 		  Field_w_Slot_inst_get (insn) == 0 &&
  14218 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14219 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14220 		  Field_tlo_Slot_inst_get (insn) == 0)
  14221 		return OPCODE_MULS_DD_HL;
  14222 	      break;
  14223 	    case 14:
  14224 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14225 		  Field_w_Slot_inst_get (insn) == 0 &&
  14226 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14227 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14228 		  Field_tlo_Slot_inst_get (insn) == 0)
  14229 		return OPCODE_MULS_DD_LH;
  14230 	      break;
  14231 	    case 15:
  14232 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14233 		  Field_w_Slot_inst_get (insn) == 0 &&
  14234 		  Field_r3_Slot_inst_get (insn) == 0 &&
  14235 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14236 		  Field_tlo_Slot_inst_get (insn) == 0)
  14237 		return OPCODE_MULS_DD_HH;
  14238 	      break;
  14239 	    }
  14240 	  break;
  14241 	case 3:
  14242 	  switch (Field_op1_Slot_inst_get (insn))
  14243 	    {
  14244 	    case 4:
  14245 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14246 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14247 		  Field_tlo_Slot_inst_get (insn) == 0)
  14248 		return OPCODE_MUL_AD_LL;
  14249 	      break;
  14250 	    case 5:
  14251 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14252 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14253 		  Field_tlo_Slot_inst_get (insn) == 0)
  14254 		return OPCODE_MUL_AD_HL;
  14255 	      break;
  14256 	    case 6:
  14257 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14258 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14259 		  Field_tlo_Slot_inst_get (insn) == 0)
  14260 		return OPCODE_MUL_AD_LH;
  14261 	      break;
  14262 	    case 7:
  14263 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14264 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14265 		  Field_tlo_Slot_inst_get (insn) == 0)
  14266 		return OPCODE_MUL_AD_HH;
  14267 	      break;
  14268 	    case 8:
  14269 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14270 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14271 		  Field_tlo_Slot_inst_get (insn) == 0)
  14272 		return OPCODE_MULA_AD_LL;
  14273 	      break;
  14274 	    case 9:
  14275 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14276 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14277 		  Field_tlo_Slot_inst_get (insn) == 0)
  14278 		return OPCODE_MULA_AD_HL;
  14279 	      break;
  14280 	    case 10:
  14281 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14282 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14283 		  Field_tlo_Slot_inst_get (insn) == 0)
  14284 		return OPCODE_MULA_AD_LH;
  14285 	      break;
  14286 	    case 11:
  14287 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14288 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14289 		  Field_tlo_Slot_inst_get (insn) == 0)
  14290 		return OPCODE_MULA_AD_HH;
  14291 	      break;
  14292 	    case 12:
  14293 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14294 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14295 		  Field_tlo_Slot_inst_get (insn) == 0)
  14296 		return OPCODE_MULS_AD_LL;
  14297 	      break;
  14298 	    case 13:
  14299 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14300 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14301 		  Field_tlo_Slot_inst_get (insn) == 0)
  14302 		return OPCODE_MULS_AD_HL;
  14303 	      break;
  14304 	    case 14:
  14305 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14306 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14307 		  Field_tlo_Slot_inst_get (insn) == 0)
  14308 		return OPCODE_MULS_AD_LH;
  14309 	      break;
  14310 	    case 15:
  14311 	      if (Field_r_Slot_inst_get (insn) == 0 &&
  14312 		  Field_t3_Slot_inst_get (insn) == 0 &&
  14313 		  Field_tlo_Slot_inst_get (insn) == 0)
  14314 		return OPCODE_MULS_AD_HH;
  14315 	      break;
  14316 	    }
  14317 	  break;
  14318 	case 4:
  14319 	  switch (Field_op1_Slot_inst_get (insn))
  14320 	    {
  14321 	    case 8:
  14322 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14323 		return OPCODE_MULA_DA_LL_LDINC;
  14324 	      break;
  14325 	    case 9:
  14326 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14327 		return OPCODE_MULA_DA_HL_LDINC;
  14328 	      break;
  14329 	    case 10:
  14330 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14331 		return OPCODE_MULA_DA_LH_LDINC;
  14332 	      break;
  14333 	    case 11:
  14334 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14335 		return OPCODE_MULA_DA_HH_LDINC;
  14336 	      break;
  14337 	    }
  14338 	  break;
  14339 	case 5:
  14340 	  switch (Field_op1_Slot_inst_get (insn))
  14341 	    {
  14342 	    case 8:
  14343 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14344 		return OPCODE_MULA_DA_LL_LDDEC;
  14345 	      break;
  14346 	    case 9:
  14347 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14348 		return OPCODE_MULA_DA_HL_LDDEC;
  14349 	      break;
  14350 	    case 10:
  14351 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14352 		return OPCODE_MULA_DA_LH_LDDEC;
  14353 	      break;
  14354 	    case 11:
  14355 	      if (Field_r3_Slot_inst_get (insn) == 0)
  14356 		return OPCODE_MULA_DA_HH_LDDEC;
  14357 	      break;
  14358 	    }
  14359 	  break;
  14360 	case 6:
  14361 	  switch (Field_op1_Slot_inst_get (insn))
  14362 	    {
  14363 	    case 4:
  14364 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14365 		  Field_w_Slot_inst_get (insn) == 0 &&
  14366 		  Field_r3_Slot_inst_get (insn) == 0)
  14367 		return OPCODE_MUL_DA_LL;
  14368 	      break;
  14369 	    case 5:
  14370 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14371 		  Field_w_Slot_inst_get (insn) == 0 &&
  14372 		  Field_r3_Slot_inst_get (insn) == 0)
  14373 		return OPCODE_MUL_DA_HL;
  14374 	      break;
  14375 	    case 6:
  14376 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14377 		  Field_w_Slot_inst_get (insn) == 0 &&
  14378 		  Field_r3_Slot_inst_get (insn) == 0)
  14379 		return OPCODE_MUL_DA_LH;
  14380 	      break;
  14381 	    case 7:
  14382 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14383 		  Field_w_Slot_inst_get (insn) == 0 &&
  14384 		  Field_r3_Slot_inst_get (insn) == 0)
  14385 		return OPCODE_MUL_DA_HH;
  14386 	      break;
  14387 	    case 8:
  14388 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14389 		  Field_w_Slot_inst_get (insn) == 0 &&
  14390 		  Field_r3_Slot_inst_get (insn) == 0)
  14391 		return OPCODE_MULA_DA_LL;
  14392 	      break;
  14393 	    case 9:
  14394 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14395 		  Field_w_Slot_inst_get (insn) == 0 &&
  14396 		  Field_r3_Slot_inst_get (insn) == 0)
  14397 		return OPCODE_MULA_DA_HL;
  14398 	      break;
  14399 	    case 10:
  14400 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14401 		  Field_w_Slot_inst_get (insn) == 0 &&
  14402 		  Field_r3_Slot_inst_get (insn) == 0)
  14403 		return OPCODE_MULA_DA_LH;
  14404 	      break;
  14405 	    case 11:
  14406 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14407 		  Field_w_Slot_inst_get (insn) == 0 &&
  14408 		  Field_r3_Slot_inst_get (insn) == 0)
  14409 		return OPCODE_MULA_DA_HH;
  14410 	      break;
  14411 	    case 12:
  14412 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14413 		  Field_w_Slot_inst_get (insn) == 0 &&
  14414 		  Field_r3_Slot_inst_get (insn) == 0)
  14415 		return OPCODE_MULS_DA_LL;
  14416 	      break;
  14417 	    case 13:
  14418 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14419 		  Field_w_Slot_inst_get (insn) == 0 &&
  14420 		  Field_r3_Slot_inst_get (insn) == 0)
  14421 		return OPCODE_MULS_DA_HL;
  14422 	      break;
  14423 	    case 14:
  14424 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14425 		  Field_w_Slot_inst_get (insn) == 0 &&
  14426 		  Field_r3_Slot_inst_get (insn) == 0)
  14427 		return OPCODE_MULS_DA_LH;
  14428 	      break;
  14429 	    case 15:
  14430 	      if (Field_s_Slot_inst_get (insn) == 0 &&
  14431 		  Field_w_Slot_inst_get (insn) == 0 &&
  14432 		  Field_r3_Slot_inst_get (insn) == 0)
  14433 		return OPCODE_MULS_DA_HH;
  14434 	      break;
  14435 	    }
  14436 	  break;
  14437 	case 7:
  14438 	  switch (Field_op1_Slot_inst_get (insn))
  14439 	    {
  14440 	    case 0:
  14441 	      if (Field_r_Slot_inst_get (insn) == 0)
  14442 		return OPCODE_UMUL_AA_LL;
  14443 	      break;
  14444 	    case 1:
  14445 	      if (Field_r_Slot_inst_get (insn) == 0)
  14446 		return OPCODE_UMUL_AA_HL;
  14447 	      break;
  14448 	    case 2:
  14449 	      if (Field_r_Slot_inst_get (insn) == 0)
  14450 		return OPCODE_UMUL_AA_LH;
  14451 	      break;
  14452 	    case 3:
  14453 	      if (Field_r_Slot_inst_get (insn) == 0)
  14454 		return OPCODE_UMUL_AA_HH;
  14455 	      break;
  14456 	    case 4:
  14457 	      if (Field_r_Slot_inst_get (insn) == 0)
  14458 		return OPCODE_MUL_AA_LL;
  14459 	      break;
  14460 	    case 5:
  14461 	      if (Field_r_Slot_inst_get (insn) == 0)
  14462 		return OPCODE_MUL_AA_HL;
  14463 	      break;
  14464 	    case 6:
  14465 	      if (Field_r_Slot_inst_get (insn) == 0)
  14466 		return OPCODE_MUL_AA_LH;
  14467 	      break;
  14468 	    case 7:
  14469 	      if (Field_r_Slot_inst_get (insn) == 0)
  14470 		return OPCODE_MUL_AA_HH;
  14471 	      break;
  14472 	    case 8:
  14473 	      if (Field_r_Slot_inst_get (insn) == 0)
  14474 		return OPCODE_MULA_AA_LL;
  14475 	      break;
  14476 	    case 9:
  14477 	      if (Field_r_Slot_inst_get (insn) == 0)
  14478 		return OPCODE_MULA_AA_HL;
  14479 	      break;
  14480 	    case 10:
  14481 	      if (Field_r_Slot_inst_get (insn) == 0)
  14482 		return OPCODE_MULA_AA_LH;
  14483 	      break;
  14484 	    case 11:
  14485 	      if (Field_r_Slot_inst_get (insn) == 0)
  14486 		return OPCODE_MULA_AA_HH;
  14487 	      break;
  14488 	    case 12:
  14489 	      if (Field_r_Slot_inst_get (insn) == 0)
  14490 		return OPCODE_MULS_AA_LL;
  14491 	      break;
  14492 	    case 13:
  14493 	      if (Field_r_Slot_inst_get (insn) == 0)
  14494 		return OPCODE_MULS_AA_HL;
  14495 	      break;
  14496 	    case 14:
  14497 	      if (Field_r_Slot_inst_get (insn) == 0)
  14498 		return OPCODE_MULS_AA_LH;
  14499 	      break;
  14500 	    case 15:
  14501 	      if (Field_r_Slot_inst_get (insn) == 0)
  14502 		return OPCODE_MULS_AA_HH;
  14503 	      break;
  14504 	    }
  14505 	  break;
  14506 	case 8:
  14507 	  if (Field_op1_Slot_inst_get (insn) == 0 &&
  14508 	      Field_t_Slot_inst_get (insn) == 0 &&
  14509 	      Field_rhi_Slot_inst_get (insn) == 0)
  14510 	    return OPCODE_LDINC;
  14511 	  break;
  14512 	case 9:
  14513 	  if (Field_op1_Slot_inst_get (insn) == 0 &&
  14514 	      Field_t_Slot_inst_get (insn) == 0 &&
  14515 	      Field_rhi_Slot_inst_get (insn) == 0)
  14516 	    return OPCODE_LDDEC;
  14517 	  break;
  14518 	}
  14519       break;
  14520     case 5:
  14521       switch (Field_n_Slot_inst_get (insn))
  14522 	{
  14523 	case 0:
  14524 	  return OPCODE_CALL0;
  14525 	case 1:
  14526 	  return OPCODE_CALL4;
  14527 	case 2:
  14528 	  return OPCODE_CALL8;
  14529 	case 3:
  14530 	  return OPCODE_CALL12;
  14531 	}
  14532       break;
  14533     case 6:
  14534       switch (Field_n_Slot_inst_get (insn))
  14535 	{
  14536 	case 0:
  14537 	  return OPCODE_J;
  14538 	case 1:
  14539 	  switch (Field_m_Slot_inst_get (insn))
  14540 	    {
  14541 	    case 0:
  14542 	      return OPCODE_BEQZ;
  14543 	    case 1:
  14544 	      return OPCODE_BNEZ;
  14545 	    case 2:
  14546 	      return OPCODE_BLTZ;
  14547 	    case 3:
  14548 	      return OPCODE_BGEZ;
  14549 	    }
  14550 	  break;
  14551 	case 2:
  14552 	  switch (Field_m_Slot_inst_get (insn))
  14553 	    {
  14554 	    case 0:
  14555 	      return OPCODE_BEQI;
  14556 	    case 1:
  14557 	      return OPCODE_BNEI;
  14558 	    case 2:
  14559 	      return OPCODE_BLTI;
  14560 	    case 3:
  14561 	      return OPCODE_BGEI;
  14562 	    }
  14563 	  break;
  14564 	case 3:
  14565 	  switch (Field_m_Slot_inst_get (insn))
  14566 	    {
  14567 	    case 0:
  14568 	      return OPCODE_ENTRY;
  14569 	    case 1:
  14570 	      switch (Field_r_Slot_inst_get (insn))
  14571 		{
  14572 		case 8:
  14573 		  return OPCODE_LOOP;
  14574 		case 9:
  14575 		  return OPCODE_LOOPNEZ;
  14576 		case 10:
  14577 		  return OPCODE_LOOPGTZ;
  14578 		}
  14579 	      break;
  14580 	    case 2:
  14581 	      return OPCODE_BLTUI;
  14582 	    case 3:
  14583 	      return OPCODE_BGEUI;
  14584 	    }
  14585 	  break;
  14586 	}
  14587       break;
  14588     case 7:
  14589       switch (Field_r_Slot_inst_get (insn))
  14590 	{
  14591 	case 0:
  14592 	  return OPCODE_BNONE;
  14593 	case 1:
  14594 	  return OPCODE_BEQ;
  14595 	case 2:
  14596 	  return OPCODE_BLT;
  14597 	case 3:
  14598 	  return OPCODE_BLTU;
  14599 	case 4:
  14600 	  return OPCODE_BALL;
  14601 	case 5:
  14602 	  return OPCODE_BBC;
  14603 	case 6:
  14604 	case 7:
  14605 	  return OPCODE_BBCI;
  14606 	case 8:
  14607 	  return OPCODE_BANY;
  14608 	case 9:
  14609 	  return OPCODE_BNE;
  14610 	case 10:
  14611 	  return OPCODE_BGE;
  14612 	case 11:
  14613 	  return OPCODE_BGEU;
  14614 	case 12:
  14615 	  return OPCODE_BNALL;
  14616 	case 13:
  14617 	  return OPCODE_BBS;
  14618 	case 14:
  14619 	case 15:
  14620 	  return OPCODE_BBSI;
  14621 	}
  14622       break;
  14623     }
  14624   return XTENSA_UNDEFINED;
  14625 }
  14626 
  14627 static int
  14628 Slot_inst16b_decode (const xtensa_insnbuf insn)
  14629 {
  14630   switch (Field_op0_Slot_inst16b_get (insn))
  14631     {
  14632     case 12:
  14633       switch (Field_i_Slot_inst16b_get (insn))
  14634 	{
  14635 	case 0:
  14636 	  return OPCODE_MOVI_N;
  14637 	case 1:
  14638 	  switch (Field_z_Slot_inst16b_get (insn))
  14639 	    {
  14640 	    case 0:
  14641 	      return OPCODE_BEQZ_N;
  14642 	    case 1:
  14643 	      return OPCODE_BNEZ_N;
  14644 	    }
  14645 	  break;
  14646 	}
  14647       break;
  14648     case 13:
  14649       switch (Field_r_Slot_inst16b_get (insn))
  14650 	{
  14651 	case 0:
  14652 	  return OPCODE_MOV_N;
  14653 	case 15:
  14654 	  switch (Field_t_Slot_inst16b_get (insn))
  14655 	    {
  14656 	    case 0:
  14657 	      return OPCODE_RET_N;
  14658 	    case 1:
  14659 	      return OPCODE_RETW_N;
  14660 	    case 2:
  14661 	      return OPCODE_BREAK_N;
  14662 	    case 3:
  14663 	      if (Field_s_Slot_inst16b_get (insn) == 0)
  14664 		return OPCODE_NOP_N;
  14665 	      break;
  14666 	    case 6:
  14667 	      if (Field_s_Slot_inst16b_get (insn) == 0)
  14668 		return OPCODE_ILL_N;
  14669 	      break;
  14670 	    }
  14671 	  break;
  14672 	}
  14673       break;
  14674     }
  14675   return XTENSA_UNDEFINED;
  14676 }
  14677 
  14678 static int
  14679 Slot_inst16a_decode (const xtensa_insnbuf insn)
  14680 {
  14681   switch (Field_op0_Slot_inst16a_get (insn))
  14682     {
  14683     case 8:
  14684       return OPCODE_L32I_N;
  14685     case 9:
  14686       return OPCODE_S32I_N;
  14687     case 10:
  14688       return OPCODE_ADD_N;
  14689     case 11:
  14690       return OPCODE_ADDI_N;
  14691     }
  14692   return XTENSA_UNDEFINED;
  14693 }
  14694 
  14695 
  14696 /* Instruction slots.  */
  14697 
  14698 static void
  14699 Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
  14700 			    xtensa_insnbuf slotbuf)
  14701 {
  14702   slotbuf[0] = (insn[0] & 0xffffff);
  14703 }
  14704 
  14705 static void
  14706 Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
  14707 			    const xtensa_insnbuf slotbuf)
  14708 {
  14709   insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
  14710 }
  14711 
  14712 static void
  14713 Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
  14714 				xtensa_insnbuf slotbuf)
  14715 {
  14716   slotbuf[0] = (insn[0] & 0xffff);
  14717 }
  14718 
  14719 static void
  14720 Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
  14721 				const xtensa_insnbuf slotbuf)
  14722 {
  14723   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  14724 }
  14725 
  14726 static void
  14727 Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
  14728 				xtensa_insnbuf slotbuf)
  14729 {
  14730   slotbuf[0] = (insn[0] & 0xffff);
  14731 }
  14732 
  14733 static void
  14734 Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
  14735 				const xtensa_insnbuf slotbuf)
  14736 {
  14737   insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
  14738 }
  14739 
  14740 static xtensa_get_field_fn
  14741 Slot_inst_get_field_fns[] = {
  14742   Field_t_Slot_inst_get,
  14743   Field_bbi4_Slot_inst_get,
  14744   Field_bbi_Slot_inst_get,
  14745   Field_imm12_Slot_inst_get,
  14746   Field_imm8_Slot_inst_get,
  14747   Field_s_Slot_inst_get,
  14748   Field_imm12b_Slot_inst_get,
  14749   Field_imm16_Slot_inst_get,
  14750   Field_m_Slot_inst_get,
  14751   Field_n_Slot_inst_get,
  14752   Field_offset_Slot_inst_get,
  14753   Field_op0_Slot_inst_get,
  14754   Field_op1_Slot_inst_get,
  14755   Field_op2_Slot_inst_get,
  14756   Field_r_Slot_inst_get,
  14757   Field_sa4_Slot_inst_get,
  14758   Field_sae4_Slot_inst_get,
  14759   Field_sae_Slot_inst_get,
  14760   Field_sal_Slot_inst_get,
  14761   Field_sargt_Slot_inst_get,
  14762   Field_sas4_Slot_inst_get,
  14763   Field_sas_Slot_inst_get,
  14764   Field_sr_Slot_inst_get,
  14765   Field_st_Slot_inst_get,
  14766   Field_thi3_Slot_inst_get,
  14767   Field_imm4_Slot_inst_get,
  14768   Field_mn_Slot_inst_get,
  14769   0,
  14770   0,
  14771   0,
  14772   0,
  14773   0,
  14774   0,
  14775   0,
  14776   0,
  14777   Field_r3_Slot_inst_get,
  14778   Field_rbit2_Slot_inst_get,
  14779   Field_rhi_Slot_inst_get,
  14780   Field_t3_Slot_inst_get,
  14781   Field_tbit2_Slot_inst_get,
  14782   Field_tlo_Slot_inst_get,
  14783   Field_w_Slot_inst_get,
  14784   Field_y_Slot_inst_get,
  14785   Field_x_Slot_inst_get,
  14786   Field_xt_wbr15_imm_Slot_inst_get,
  14787   Field_xt_wbr18_imm_Slot_inst_get,
  14788   Field_bitindex_Slot_inst_get,
  14789   Field_s3to1_Slot_inst_get,
  14790   Implicit_Field_ar0_get,
  14791   Implicit_Field_ar4_get,
  14792   Implicit_Field_ar8_get,
  14793   Implicit_Field_ar12_get,
  14794   Implicit_Field_mr0_get,
  14795   Implicit_Field_mr1_get,
  14796   Implicit_Field_mr2_get,
  14797   Implicit_Field_mr3_get
  14798 };
  14799 
  14800 static xtensa_set_field_fn
  14801 Slot_inst_set_field_fns[] = {
  14802   Field_t_Slot_inst_set,
  14803   Field_bbi4_Slot_inst_set,
  14804   Field_bbi_Slot_inst_set,
  14805   Field_imm12_Slot_inst_set,
  14806   Field_imm8_Slot_inst_set,
  14807   Field_s_Slot_inst_set,
  14808   Field_imm12b_Slot_inst_set,
  14809   Field_imm16_Slot_inst_set,
  14810   Field_m_Slot_inst_set,
  14811   Field_n_Slot_inst_set,
  14812   Field_offset_Slot_inst_set,
  14813   Field_op0_Slot_inst_set,
  14814   Field_op1_Slot_inst_set,
  14815   Field_op2_Slot_inst_set,
  14816   Field_r_Slot_inst_set,
  14817   Field_sa4_Slot_inst_set,
  14818   Field_sae4_Slot_inst_set,
  14819   Field_sae_Slot_inst_set,
  14820   Field_sal_Slot_inst_set,
  14821   Field_sargt_Slot_inst_set,
  14822   Field_sas4_Slot_inst_set,
  14823   Field_sas_Slot_inst_set,
  14824   Field_sr_Slot_inst_set,
  14825   Field_st_Slot_inst_set,
  14826   Field_thi3_Slot_inst_set,
  14827   Field_imm4_Slot_inst_set,
  14828   Field_mn_Slot_inst_set,
  14829   0,
  14830   0,
  14831   0,
  14832   0,
  14833   0,
  14834   0,
  14835   0,
  14836   0,
  14837   Field_r3_Slot_inst_set,
  14838   Field_rbit2_Slot_inst_set,
  14839   Field_rhi_Slot_inst_set,
  14840   Field_t3_Slot_inst_set,
  14841   Field_tbit2_Slot_inst_set,
  14842   Field_tlo_Slot_inst_set,
  14843   Field_w_Slot_inst_set,
  14844   Field_y_Slot_inst_set,
  14845   Field_x_Slot_inst_set,
  14846   Field_xt_wbr15_imm_Slot_inst_set,
  14847   Field_xt_wbr18_imm_Slot_inst_set,
  14848   Field_bitindex_Slot_inst_set,
  14849   Field_s3to1_Slot_inst_set,
  14850   Implicit_Field_set,
  14851   Implicit_Field_set,
  14852   Implicit_Field_set,
  14853   Implicit_Field_set,
  14854   Implicit_Field_set,
  14855   Implicit_Field_set,
  14856   Implicit_Field_set,
  14857   Implicit_Field_set
  14858 };
  14859 
  14860 static xtensa_get_field_fn
  14861 Slot_inst16a_get_field_fns[] = {
  14862   Field_t_Slot_inst16a_get,
  14863   0,
  14864   0,
  14865   0,
  14866   0,
  14867   Field_s_Slot_inst16a_get,
  14868   0,
  14869   0,
  14870   0,
  14871   0,
  14872   0,
  14873   Field_op0_Slot_inst16a_get,
  14874   0,
  14875   0,
  14876   Field_r_Slot_inst16a_get,
  14877   0,
  14878   0,
  14879   0,
  14880   0,
  14881   0,
  14882   0,
  14883   0,
  14884   Field_sr_Slot_inst16a_get,
  14885   Field_st_Slot_inst16a_get,
  14886   0,
  14887   Field_imm4_Slot_inst16a_get,
  14888   0,
  14889   Field_i_Slot_inst16a_get,
  14890   Field_imm6lo_Slot_inst16a_get,
  14891   Field_imm6hi_Slot_inst16a_get,
  14892   Field_imm7lo_Slot_inst16a_get,
  14893   Field_imm7hi_Slot_inst16a_get,
  14894   Field_z_Slot_inst16a_get,
  14895   Field_imm6_Slot_inst16a_get,
  14896   Field_imm7_Slot_inst16a_get,
  14897   0,
  14898   0,
  14899   0,
  14900   0,
  14901   0,
  14902   0,
  14903   0,
  14904   0,
  14905   0,
  14906   0,
  14907   0,
  14908   Field_bitindex_Slot_inst16a_get,
  14909   Field_s3to1_Slot_inst16a_get,
  14910   Implicit_Field_ar0_get,
  14911   Implicit_Field_ar4_get,
  14912   Implicit_Field_ar8_get,
  14913   Implicit_Field_ar12_get,
  14914   Implicit_Field_mr0_get,
  14915   Implicit_Field_mr1_get,
  14916   Implicit_Field_mr2_get,
  14917   Implicit_Field_mr3_get
  14918 };
  14919 
  14920 static xtensa_set_field_fn
  14921 Slot_inst16a_set_field_fns[] = {
  14922   Field_t_Slot_inst16a_set,
  14923   0,
  14924   0,
  14925   0,
  14926   0,
  14927   Field_s_Slot_inst16a_set,
  14928   0,
  14929   0,
  14930   0,
  14931   0,
  14932   0,
  14933   Field_op0_Slot_inst16a_set,
  14934   0,
  14935   0,
  14936   Field_r_Slot_inst16a_set,
  14937   0,
  14938   0,
  14939   0,
  14940   0,
  14941   0,
  14942   0,
  14943   0,
  14944   Field_sr_Slot_inst16a_set,
  14945   Field_st_Slot_inst16a_set,
  14946   0,
  14947   Field_imm4_Slot_inst16a_set,
  14948   0,
  14949   Field_i_Slot_inst16a_set,
  14950   Field_imm6lo_Slot_inst16a_set,
  14951   Field_imm6hi_Slot_inst16a_set,
  14952   Field_imm7lo_Slot_inst16a_set,
  14953   Field_imm7hi_Slot_inst16a_set,
  14954   Field_z_Slot_inst16a_set,
  14955   Field_imm6_Slot_inst16a_set,
  14956   Field_imm7_Slot_inst16a_set,
  14957   0,
  14958   0,
  14959   0,
  14960   0,
  14961   0,
  14962   0,
  14963   0,
  14964   0,
  14965   0,
  14966   0,
  14967   0,
  14968   Field_bitindex_Slot_inst16a_set,
  14969   Field_s3to1_Slot_inst16a_set,
  14970   Implicit_Field_set,
  14971   Implicit_Field_set,
  14972   Implicit_Field_set,
  14973   Implicit_Field_set,
  14974   Implicit_Field_set,
  14975   Implicit_Field_set,
  14976   Implicit_Field_set,
  14977   Implicit_Field_set
  14978 };
  14979 
  14980 static xtensa_get_field_fn
  14981 Slot_inst16b_get_field_fns[] = {
  14982   Field_t_Slot_inst16b_get,
  14983   0,
  14984   0,
  14985   0,
  14986   0,
  14987   Field_s_Slot_inst16b_get,
  14988   0,
  14989   0,
  14990   0,
  14991   0,
  14992   0,
  14993   Field_op0_Slot_inst16b_get,
  14994   0,
  14995   0,
  14996   Field_r_Slot_inst16b_get,
  14997   0,
  14998   0,
  14999   0,
  15000   0,
  15001   0,
  15002   0,
  15003   0,
  15004   Field_sr_Slot_inst16b_get,
  15005   Field_st_Slot_inst16b_get,
  15006   0,
  15007   Field_imm4_Slot_inst16b_get,
  15008   0,
  15009   Field_i_Slot_inst16b_get,
  15010   Field_imm6lo_Slot_inst16b_get,
  15011   Field_imm6hi_Slot_inst16b_get,
  15012   Field_imm7lo_Slot_inst16b_get,
  15013   Field_imm7hi_Slot_inst16b_get,
  15014   Field_z_Slot_inst16b_get,
  15015   Field_imm6_Slot_inst16b_get,
  15016   Field_imm7_Slot_inst16b_get,
  15017   0,
  15018   0,
  15019   0,
  15020   0,
  15021   0,
  15022   0,
  15023   0,
  15024   0,
  15025   0,
  15026   0,
  15027   0,
  15028   Field_bitindex_Slot_inst16b_get,
  15029   Field_s3to1_Slot_inst16b_get,
  15030   Implicit_Field_ar0_get,
  15031   Implicit_Field_ar4_get,
  15032   Implicit_Field_ar8_get,
  15033   Implicit_Field_ar12_get,
  15034   Implicit_Field_mr0_get,
  15035   Implicit_Field_mr1_get,
  15036   Implicit_Field_mr2_get,
  15037   Implicit_Field_mr3_get
  15038 };
  15039 
  15040 static xtensa_set_field_fn
  15041 Slot_inst16b_set_field_fns[] = {
  15042   Field_t_Slot_inst16b_set,
  15043   0,
  15044   0,
  15045   0,
  15046   0,
  15047   Field_s_Slot_inst16b_set,
  15048   0,
  15049   0,
  15050   0,
  15051   0,
  15052   0,
  15053   Field_op0_Slot_inst16b_set,
  15054   0,
  15055   0,
  15056   Field_r_Slot_inst16b_set,
  15057   0,
  15058   0,
  15059   0,
  15060   0,
  15061   0,
  15062   0,
  15063   0,
  15064   Field_sr_Slot_inst16b_set,
  15065   Field_st_Slot_inst16b_set,
  15066   0,
  15067   Field_imm4_Slot_inst16b_set,
  15068   0,
  15069   Field_i_Slot_inst16b_set,
  15070   Field_imm6lo_Slot_inst16b_set,
  15071   Field_imm6hi_Slot_inst16b_set,
  15072   Field_imm7lo_Slot_inst16b_set,
  15073   Field_imm7hi_Slot_inst16b_set,
  15074   Field_z_Slot_inst16b_set,
  15075   Field_imm6_Slot_inst16b_set,
  15076   Field_imm7_Slot_inst16b_set,
  15077   0,
  15078   0,
  15079   0,
  15080   0,
  15081   0,
  15082   0,
  15083   0,
  15084   0,
  15085   0,
  15086   0,
  15087   0,
  15088   Field_bitindex_Slot_inst16b_set,
  15089   Field_s3to1_Slot_inst16b_set,
  15090   Implicit_Field_set,
  15091   Implicit_Field_set,
  15092   Implicit_Field_set,
  15093   Implicit_Field_set,
  15094   Implicit_Field_set,
  15095   Implicit_Field_set,
  15096   Implicit_Field_set,
  15097   Implicit_Field_set
  15098 };
  15099 
  15100 static xtensa_slot_internal slots[] = {
  15101   { "Inst", "x24", 0,
  15102     Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
  15103     Slot_inst_get_field_fns, Slot_inst_set_field_fns,
  15104     Slot_inst_decode, "nop" },
  15105   { "Inst16a", "x16a", 0,
  15106     Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
  15107     Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
  15108     Slot_inst16a_decode, "" },
  15109   { "Inst16b", "x16b", 0,
  15110     Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
  15111     Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
  15112     Slot_inst16b_decode, "nop.n" }
  15113 };
  15114 
  15115 
  15116 /* Instruction formats.  */
  15117 
  15118 static void
  15119 Format_x24_encode (xtensa_insnbuf insn)
  15120 {
  15121   insn[0] = 0;
  15122 }
  15123 
  15124 static void
  15125 Format_x16a_encode (xtensa_insnbuf insn)
  15126 {
  15127   insn[0] = 0x8;
  15128 }
  15129 
  15130 static void
  15131 Format_x16b_encode (xtensa_insnbuf insn)
  15132 {
  15133   insn[0] = 0xc;
  15134 }
  15135 
  15136 static int Format_x24_slots[] = { 0 };
  15137 
  15138 static int Format_x16a_slots[] = { 1 };
  15139 
  15140 static int Format_x16b_slots[] = { 2 };
  15141 
  15142 static xtensa_format_internal formats[] = {
  15143   { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
  15144   { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
  15145   { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots }
  15146 };
  15147 
  15148 
  15149 static int
  15150 format_decoder (const xtensa_insnbuf insn)
  15151 {
  15152   if ((insn[0] & 0x8) == 0)
  15153     return 0; /* x24 */
  15154   if ((insn[0] & 0xc) == 0x8)
  15155     return 1; /* x16a */
  15156   if ((insn[0] & 0xe) == 0xc)
  15157     return 2; /* x16b */
  15158   return -1;
  15159 }
  15160 
  15161 static int length_table[16] = {
  15162   3,
  15163   3,
  15164   3,
  15165   3,
  15166   3,
  15167   3,
  15168   3,
  15169   3,
  15170   2,
  15171   2,
  15172   2,
  15173   2,
  15174   2,
  15175   2,
  15176   -1,
  15177   -1
  15178 };
  15179 
  15180 static int
  15181 length_decoder (const unsigned char *insn)
  15182 {
  15183   int op0 = insn[0] & 0xf;
  15184   return length_table[op0];
  15185 }
  15186 
  15187 
  15188 /* Top-level ISA structure.  */
  15189 
  15190 xtensa_isa_internal xtensa_modules = {
  15191   0 /* little-endian */,
  15192   3 /* insn_size */, 0,
  15193   3, formats, format_decoder, length_decoder,
  15194   3, slots,
  15195   56 /* num_fields */,
  15196   93, operands,
  15197   326, iclasses,
  15198   452, opcodes, 0,
  15199   2, regfiles,
  15200   NUM_STATES, states, 0,
  15201   NUM_SYSREGS, sysregs, 0,
  15202   { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
  15203   1, interfaces, 0,
  15204   0, funcUnits, 0
  15205 };
	qemu FORK: QEMU emulator
	git clone https://git.neptards.moe/neptards/qemu.git
	Log \| Files \| Refs \| Submodules \| LICENSE