cpu.c (9218B)
1 /* 2 * QEMU SuperH CPU 3 * 4 * Copyright (c) 2005 Samuel Tardieu 5 * Copyright (c) 2012 SUSE LINUX Products GmbH 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see 19 * <http://www.gnu.org/licenses/lgpl-2.1.html> 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qapi/error.h" 24 #include "qemu/qemu-print.h" 25 #include "cpu.h" 26 #include "migration/vmstate.h" 27 #include "exec/exec-all.h" 28 #include "fpu/softfloat-helpers.h" 29 30 static void superh_cpu_set_pc(CPUState *cs, vaddr value) 31 { 32 SuperHCPU *cpu = SUPERH_CPU(cs); 33 34 cpu->env.pc = value; 35 } 36 37 static vaddr superh_cpu_get_pc(CPUState *cs) 38 { 39 SuperHCPU *cpu = SUPERH_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void superh_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 SuperHCPU *cpu = SUPERH_CPU(cs); 48 49 cpu->env.pc = tb_pc(tb); 50 cpu->env.flags = tb->flags; 51 } 52 53 static void superh_restore_state_to_opc(CPUState *cs, 54 const TranslationBlock *tb, 55 const uint64_t *data) 56 { 57 SuperHCPU *cpu = SUPERH_CPU(cs); 58 59 cpu->env.pc = data[0]; 60 cpu->env.flags = data[1]; 61 /* 62 * Theoretically delayed_pc should also be restored. In practice the 63 * branch instruction is re-executed after exception, so the delayed 64 * branch target will be recomputed. 65 */ 66 } 67 68 #ifndef CONFIG_USER_ONLY 69 static bool superh_io_recompile_replay_branch(CPUState *cs, 70 const TranslationBlock *tb) 71 { 72 SuperHCPU *cpu = SUPERH_CPU(cs); 73 CPUSH4State *env = &cpu->env; 74 75 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND)) 76 && env->pc != tb_pc(tb)) { 77 env->pc -= 2; 78 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND); 79 return true; 80 } 81 return false; 82 } 83 #endif 84 85 static bool superh_cpu_has_work(CPUState *cs) 86 { 87 return cs->interrupt_request & CPU_INTERRUPT_HARD; 88 } 89 90 static void superh_cpu_reset(DeviceState *dev) 91 { 92 CPUState *s = CPU(dev); 93 SuperHCPU *cpu = SUPERH_CPU(s); 94 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); 95 CPUSH4State *env = &cpu->env; 96 97 scc->parent_reset(dev); 98 99 memset(env, 0, offsetof(CPUSH4State, end_reset_fields)); 100 101 env->pc = 0xA0000000; 102 #if defined(CONFIG_USER_ONLY) 103 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */ 104 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */ 105 #else 106 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | 107 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0); 108 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */ 109 set_float_rounding_mode(float_round_to_zero, &env->fp_status); 110 set_flush_to_zero(1, &env->fp_status); 111 #endif 112 set_default_nan_mode(1, &env->fp_status); 113 } 114 115 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 116 { 117 info->mach = bfd_mach_sh4; 118 info->print_insn = print_insn_sh; 119 } 120 121 static void superh_cpu_list_entry(gpointer data, gpointer user_data) 122 { 123 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 124 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX); 125 126 qemu_printf("%.*s\n", len, typename); 127 } 128 129 void sh4_cpu_list(void) 130 { 131 GSList *list; 132 133 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false); 134 g_slist_foreach(list, superh_cpu_list_entry, NULL); 135 g_slist_free(list); 136 } 137 138 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model) 139 { 140 ObjectClass *oc; 141 char *s, *typename = NULL; 142 143 s = g_ascii_strdown(cpu_model, -1); 144 if (strcmp(s, "any") == 0) { 145 oc = object_class_by_name(TYPE_SH7750R_CPU); 146 goto out; 147 } 148 149 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s); 150 oc = object_class_by_name(typename); 151 if (oc != NULL && object_class_is_abstract(oc)) { 152 oc = NULL; 153 } 154 155 out: 156 g_free(s); 157 g_free(typename); 158 return oc; 159 } 160 161 static void sh7750r_cpu_initfn(Object *obj) 162 { 163 SuperHCPU *cpu = SUPERH_CPU(obj); 164 CPUSH4State *env = &cpu->env; 165 166 env->id = SH_CPU_SH7750R; 167 env->features = SH_FEATURE_BCR3_AND_BCR4; 168 } 169 170 static void sh7750r_class_init(ObjectClass *oc, void *data) 171 { 172 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 173 174 scc->pvr = 0x00050000; 175 scc->prr = 0x00000100; 176 scc->cvr = 0x00110000; 177 } 178 179 static void sh7751r_cpu_initfn(Object *obj) 180 { 181 SuperHCPU *cpu = SUPERH_CPU(obj); 182 CPUSH4State *env = &cpu->env; 183 184 env->id = SH_CPU_SH7751R; 185 env->features = SH_FEATURE_BCR3_AND_BCR4; 186 } 187 188 static void sh7751r_class_init(ObjectClass *oc, void *data) 189 { 190 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 191 192 scc->pvr = 0x04050005; 193 scc->prr = 0x00000113; 194 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */ 195 } 196 197 static void sh7785_cpu_initfn(Object *obj) 198 { 199 SuperHCPU *cpu = SUPERH_CPU(obj); 200 CPUSH4State *env = &cpu->env; 201 202 env->id = SH_CPU_SH7785; 203 env->features = SH_FEATURE_SH4A; 204 } 205 206 static void sh7785_class_init(ObjectClass *oc, void *data) 207 { 208 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 209 210 scc->pvr = 0x10300700; 211 scc->prr = 0x00000200; 212 scc->cvr = 0x71440211; 213 } 214 215 static void superh_cpu_realizefn(DeviceState *dev, Error **errp) 216 { 217 CPUState *cs = CPU(dev); 218 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev); 219 Error *local_err = NULL; 220 221 cpu_exec_realizefn(cs, &local_err); 222 if (local_err != NULL) { 223 error_propagate(errp, local_err); 224 return; 225 } 226 227 cpu_reset(cs); 228 qemu_init_vcpu(cs); 229 230 scc->parent_realize(dev, errp); 231 } 232 233 static void superh_cpu_initfn(Object *obj) 234 { 235 SuperHCPU *cpu = SUPERH_CPU(obj); 236 CPUSH4State *env = &cpu->env; 237 238 cpu_set_cpustate_pointers(cpu); 239 240 env->movcal_backup_tail = &(env->movcal_backup); 241 } 242 243 #ifndef CONFIG_USER_ONLY 244 static const VMStateDescription vmstate_sh_cpu = { 245 .name = "cpu", 246 .unmigratable = 1, 247 }; 248 249 #include "hw/core/sysemu-cpu-ops.h" 250 251 static const struct SysemuCPUOps sh4_sysemu_ops = { 252 .get_phys_page_debug = superh_cpu_get_phys_page_debug, 253 }; 254 #endif 255 256 #include "hw/core/tcg-cpu-ops.h" 257 258 static const struct TCGCPUOps superh_tcg_ops = { 259 .initialize = sh4_translate_init, 260 .synchronize_from_tb = superh_cpu_synchronize_from_tb, 261 .restore_state_to_opc = superh_restore_state_to_opc, 262 263 #ifndef CONFIG_USER_ONLY 264 .tlb_fill = superh_cpu_tlb_fill, 265 .cpu_exec_interrupt = superh_cpu_exec_interrupt, 266 .do_interrupt = superh_cpu_do_interrupt, 267 .do_unaligned_access = superh_cpu_do_unaligned_access, 268 .io_recompile_replay_branch = superh_io_recompile_replay_branch, 269 #endif /* !CONFIG_USER_ONLY */ 270 }; 271 272 static void superh_cpu_class_init(ObjectClass *oc, void *data) 273 { 274 DeviceClass *dc = DEVICE_CLASS(oc); 275 CPUClass *cc = CPU_CLASS(oc); 276 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc); 277 278 device_class_set_parent_realize(dc, superh_cpu_realizefn, 279 &scc->parent_realize); 280 281 device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset); 282 283 cc->class_by_name = superh_cpu_class_by_name; 284 cc->has_work = superh_cpu_has_work; 285 cc->dump_state = superh_cpu_dump_state; 286 cc->set_pc = superh_cpu_set_pc; 287 cc->get_pc = superh_cpu_get_pc; 288 cc->gdb_read_register = superh_cpu_gdb_read_register; 289 cc->gdb_write_register = superh_cpu_gdb_write_register; 290 #ifndef CONFIG_USER_ONLY 291 cc->sysemu_ops = &sh4_sysemu_ops; 292 dc->vmsd = &vmstate_sh_cpu; 293 #endif 294 cc->disas_set_info = superh_cpu_disas_set_info; 295 296 cc->gdb_num_core_regs = 59; 297 cc->tcg_ops = &superh_tcg_ops; 298 } 299 300 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \ 301 { \ 302 .name = type_name, \ 303 .parent = TYPE_SUPERH_CPU, \ 304 .class_init = cinit, \ 305 .instance_init = initfn, \ 306 } 307 static const TypeInfo superh_cpu_type_infos[] = { 308 { 309 .name = TYPE_SUPERH_CPU, 310 .parent = TYPE_CPU, 311 .instance_size = sizeof(SuperHCPU), 312 .instance_init = superh_cpu_initfn, 313 .abstract = true, 314 .class_size = sizeof(SuperHCPUClass), 315 .class_init = superh_cpu_class_init, 316 }, 317 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init, 318 sh7750r_cpu_initfn), 319 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init, 320 sh7751r_cpu_initfn), 321 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init, 322 sh7785_cpu_initfn), 323 324 }; 325 326 DEFINE_TYPES(superh_cpu_type_infos)