debug.h (3979B)
1 /* 2 * QEMU RISC-V Native Debug Support 3 * 4 * Copyright (c) 2022 Wind River Systems, Inc. 5 * 6 * Author: 7 * Bin Meng <bin.meng@windriver.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms and conditions of the GNU General Public License, 11 * version 2 or later, as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope it will be useful, but WITHOUT 14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 16 * more details. 17 * 18 * You should have received a copy of the GNU General Public License along with 19 * this program. If not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef RISCV_DEBUG_H 23 #define RISCV_DEBUG_H 24 25 #define RV_MAX_TRIGGERS 2 26 27 /* register index of tdata CSRs */ 28 enum { 29 TDATA1 = 0, 30 TDATA2, 31 TDATA3, 32 TDATA_NUM 33 }; 34 35 typedef enum { 36 TRIGGER_TYPE_NO_EXIST = 0, /* trigger does not exist */ 37 TRIGGER_TYPE_AD_MATCH = 2, /* address/data match trigger */ 38 TRIGGER_TYPE_INST_CNT = 3, /* instruction count trigger */ 39 TRIGGER_TYPE_INT = 4, /* interrupt trigger */ 40 TRIGGER_TYPE_EXCP = 5, /* exception trigger */ 41 TRIGGER_TYPE_AD_MATCH6 = 6, /* new address/data match trigger */ 42 TRIGGER_TYPE_EXT_SRC = 7, /* external source trigger */ 43 TRIGGER_TYPE_UNAVAIL = 15, /* trigger exists, but unavailable */ 44 TRIGGER_TYPE_NUM 45 } trigger_type_t; 46 47 /* actions */ 48 typedef enum { 49 DBG_ACTION_NONE = -1, /* sentinel value */ 50 DBG_ACTION_BP = 0, 51 DBG_ACTION_DBG_MODE, 52 DBG_ACTION_TRACE0, 53 DBG_ACTION_TRACE1, 54 DBG_ACTION_TRACE2, 55 DBG_ACTION_TRACE3, 56 DBG_ACTION_EXT_DBG0 = 8, 57 DBG_ACTION_EXT_DBG1 58 } trigger_action_t; 59 60 /* tdata1 field masks */ 61 62 #define RV32_TYPE(t) ((uint32_t)(t) << 28) 63 #define RV32_TYPE_MASK (0xf << 28) 64 #define RV32_DMODE BIT(27) 65 #define RV32_DATA_MASK 0x7ffffff 66 #define RV64_TYPE(t) ((uint64_t)(t) << 60) 67 #define RV64_TYPE_MASK (0xfULL << 60) 68 #define RV64_DMODE BIT_ULL(59) 69 #define RV64_DATA_MASK 0x7ffffffffffffff 70 71 /* mcontrol field masks */ 72 73 #define TYPE2_LOAD BIT(0) 74 #define TYPE2_STORE BIT(1) 75 #define TYPE2_EXEC BIT(2) 76 #define TYPE2_U BIT(3) 77 #define TYPE2_S BIT(4) 78 #define TYPE2_M BIT(6) 79 #define TYPE2_MATCH (0xf << 7) 80 #define TYPE2_CHAIN BIT(11) 81 #define TYPE2_ACTION (0xf << 12) 82 #define TYPE2_SIZELO (0x3 << 16) 83 #define TYPE2_TIMING BIT(18) 84 #define TYPE2_SELECT BIT(19) 85 #define TYPE2_HIT BIT(20) 86 #define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ 87 88 /* mcontrol6 field masks */ 89 90 #define TYPE6_LOAD BIT(0) 91 #define TYPE6_STORE BIT(1) 92 #define TYPE6_EXEC BIT(2) 93 #define TYPE6_U BIT(3) 94 #define TYPE6_S BIT(4) 95 #define TYPE6_M BIT(6) 96 #define TYPE6_MATCH (0xf << 7) 97 #define TYPE6_CHAIN BIT(11) 98 #define TYPE6_ACTION (0xf << 12) 99 #define TYPE6_SIZE (0xf << 16) 100 #define TYPE6_TIMING BIT(20) 101 #define TYPE6_SELECT BIT(21) 102 #define TYPE6_HIT BIT(22) 103 #define TYPE6_VU BIT(23) 104 #define TYPE6_VS BIT(24) 105 106 /* access size */ 107 enum { 108 SIZE_ANY = 0, 109 SIZE_1B, 110 SIZE_2B, 111 SIZE_4B, 112 SIZE_6B, 113 SIZE_8B, 114 SIZE_10B, 115 SIZE_12B, 116 SIZE_14B, 117 SIZE_16B, 118 SIZE_NUM = 16 119 }; 120 121 bool tdata_available(CPURISCVState *env, int tdata_index); 122 123 target_ulong tselect_csr_read(CPURISCVState *env); 124 void tselect_csr_write(CPURISCVState *env, target_ulong val); 125 126 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); 127 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val); 128 129 target_ulong tinfo_csr_read(CPURISCVState *env); 130 131 void riscv_cpu_debug_excp_handler(CPUState *cs); 132 bool riscv_cpu_debug_check_breakpoint(CPUState *cs); 133 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); 134 135 void riscv_trigger_init(CPURISCVState *env); 136 137 #endif /* RISCV_DEBUG_H */