qemu

FORK: QEMU emulator
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processor-ctrl-impl.c.inc (2849B)

      1 /*
      2  * Power ISA decode for Storage Control instructions
      3  *
      4  * Copyright (c) 2022 Instituto de Pesquisas Eldorado (eldorado.org.br)
      5  *
      6  * This library is free software; you can redistribute it and/or
      7  * modify it under the terms of the GNU Lesser General Public
      8  * License as published by the Free Software Foundation; either
      9  * version 2.1 of the License, or (at your option) any later version.
     10  *
     11  * This library is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14  * Lesser General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU Lesser General Public
     17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18  */
     19 
     20 /*
     21  * Processor Control Instructions
     22  */
     23 
     24 static bool trans_MSGCLR(DisasContext *ctx, arg_X_rb *a)
     25 {
     26     if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
     27         /*
     28          * Before Power ISA 2.07, processor control instructions were only
     29          * implemented in the "Embedded.Processor Control" category.
     30          */
     31         REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
     32     }
     33 
     34     REQUIRE_HV(ctx);
     35 
     36 #if !defined(CONFIG_USER_ONLY)
     37     if (is_book3s_arch2x(ctx)) {
     38         gen_helper_book3s_msgclr(cpu_env, cpu_gpr[a->rb]);
     39     } else {
     40         gen_helper_msgclr(cpu_env, cpu_gpr[a->rb]);
     41     }
     42 #else
     43     qemu_build_not_reached();
     44 #endif
     45     return true;
     46 }
     47 
     48 static bool trans_MSGSND(DisasContext *ctx, arg_X_rb *a)
     49 {
     50     if (!(ctx->insns_flags2 & PPC2_ISA207S)) {
     51         /*
     52          * Before Power ISA 2.07, processor control instructions were only
     53          * implemented in the "Embedded.Processor Control" category.
     54          */
     55         REQUIRE_INSNS_FLAGS2(ctx, PRCNTL);
     56     }
     57 
     58     REQUIRE_HV(ctx);
     59 
     60 #if !defined(CONFIG_USER_ONLY)
     61     if (is_book3s_arch2x(ctx)) {
     62         gen_helper_book3s_msgsnd(cpu_gpr[a->rb]);
     63     } else {
     64         gen_helper_msgsnd(cpu_gpr[a->rb]);
     65     }
     66 #else
     67     qemu_build_not_reached();
     68 #endif
     69     return true;
     70 }
     71 
     72 static bool trans_MSGCLRP(DisasContext *ctx, arg_X_rb *a)
     73 {
     74     REQUIRE_64BIT(ctx);
     75     REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
     76     REQUIRE_SV(ctx);
     77 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
     78     gen_helper_book3s_msgclrp(cpu_env, cpu_gpr[a->rb]);
     79 #else
     80     qemu_build_not_reached();
     81 #endif
     82     return true;
     83 }
     84 
     85 static bool trans_MSGSNDP(DisasContext *ctx, arg_X_rb *a)
     86 {
     87     REQUIRE_64BIT(ctx);
     88     REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
     89     REQUIRE_SV(ctx);
     90 #if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
     91     gen_helper_book3s_msgsndp(cpu_env, cpu_gpr[a->rb]);
     92 #else
     93     qemu_build_not_reached();
     94 #endif
     95     return true;
     96 }
     97 
     98 static bool trans_MSGSYNC(DisasContext *ctx, arg_MSGSYNC *a)
     99 {
    100     REQUIRE_INSNS_FLAGS2(ctx, ISA300);
    101     REQUIRE_HV(ctx);
    102 
    103     /* interpreted as no-op */
    104     return true;
    105 }