qemu

FORK: QEMU emulator
git clone https://git.neptards.moe/neptards/qemu.git
Log | Files | Refs | Submodules | LICENSE

misc_helper.c (7680B)

      1 /*
      2  * Miscellaneous PowerPC emulation helpers for QEMU.
      3  *
      4  *  Copyright (c) 2003-2007 Jocelyn Mayer
      5  *
      6  * This library is free software; you can redistribute it and/or
      7  * modify it under the terms of the GNU Lesser General Public
      8  * License as published by the Free Software Foundation; either
      9  * version 2.1 of the License, or (at your option) any later version.
     10  *
     11  * This library is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14  * Lesser General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU Lesser General Public
     17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18  */
     19 
     20 #include "qemu/osdep.h"
     21 #include "qemu/log.h"
     22 #include "cpu.h"
     23 #include "exec/exec-all.h"
     24 #include "exec/helper-proto.h"
     25 #include "qemu/error-report.h"
     26 #include "qemu/main-loop.h"
     27 #include "mmu-book3s-v3.h"
     28 #include "hw/ppc/ppc.h"
     29 
     30 #include "helper_regs.h"
     31 
     32 /*****************************************************************************/
     33 /* SPR accesses */
     34 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
     35 {
     36     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
     37              env->spr[sprn]);
     38 }
     39 
     40 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
     41 {
     42     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
     43              env->spr[sprn]);
     44 }
     45 
     46 #ifdef TARGET_PPC64
     47 static void raise_hv_fu_exception(CPUPPCState *env, uint32_t bit,
     48                                   const char *caller, uint32_t cause,
     49                                   uintptr_t raddr)
     50 {
     51     qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
     52                   bit, caller);
     53 
     54     env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
     55 
     56     raise_exception_err_ra(env, POWERPC_EXCP_HV_FU, cause, raddr);
     57 }
     58 
     59 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
     60                                uint32_t sprn, uint32_t cause,
     61                                uintptr_t raddr)
     62 {
     63     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
     64 
     65     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
     66     cause &= FSCR_IC_MASK;
     67     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
     68 
     69     raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
     70 }
     71 #endif
     72 
     73 void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
     74                                  const char *caller, uint32_t cause)
     75 {
     76 #ifdef TARGET_PPC64
     77     if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
     78                                      !(env->spr[SPR_HFSCR] & (1UL << bit))) {
     79         raise_hv_fu_exception(env, bit, caller, cause, GETPC());
     80     }
     81 #endif
     82 }
     83 
     84 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
     85                                 uint32_t sprn, uint32_t cause)
     86 {
     87 #ifdef TARGET_PPC64
     88     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
     89         /* Facility is enabled, continue */
     90         return;
     91     }
     92     raise_fu_exception(env, bit, sprn, cause, GETPC());
     93 #endif
     94 }
     95 
     96 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
     97                                uint32_t sprn, uint32_t cause)
     98 {
     99 #ifdef TARGET_PPC64
    100     if (env->msr & (1ULL << bit)) {
    101         /* Facility is enabled, continue */
    102         return;
    103     }
    104     raise_fu_exception(env, bit, sprn, cause, GETPC());
    105 #endif
    106 }
    107 
    108 #if !defined(CONFIG_USER_ONLY)
    109 
    110 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
    111 {
    112     if (env->spr[SPR_SDR1] != val) {
    113         ppc_store_sdr1(env, val);
    114         tlb_flush(env_cpu(env));
    115     }
    116 }
    117 
    118 #if defined(TARGET_PPC64)
    119 void helper_store_ptcr(CPUPPCState *env, target_ulong val)
    120 {
    121     if (env->spr[SPR_PTCR] != val) {
    122         PowerPCCPU *cpu = env_archcpu(env);
    123         target_ulong ptcr_mask = PTCR_PATB | PTCR_PATS;
    124         target_ulong patbsize = val & PTCR_PATS;
    125 
    126         qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, val);
    127 
    128         assert(!cpu->vhyp);
    129         assert(env->mmu_model & POWERPC_MMU_3_00);
    130 
    131         if (val & ~ptcr_mask) {
    132             error_report("Invalid bits 0x"TARGET_FMT_lx" set in PTCR",
    133                          val & ~ptcr_mask);
    134             val &= ptcr_mask;
    135         }
    136 
    137         if (patbsize > 24) {
    138             error_report("Invalid Partition Table size 0x" TARGET_FMT_lx
    139                          " stored in PTCR", patbsize);
    140             return;
    141         }
    142 
    143         env->spr[SPR_PTCR] = val;
    144         tlb_flush(env_cpu(env));
    145     }
    146 }
    147 
    148 void helper_store_pcr(CPUPPCState *env, target_ulong value)
    149 {
    150     PowerPCCPU *cpu = env_archcpu(env);
    151     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
    152 
    153     env->spr[SPR_PCR] = value & pcc->pcr_mask;
    154 }
    155 
    156 /*
    157  * DPDES register is shared. Each bit reflects the state of the
    158  * doorbell interrupt of a thread of the same core.
    159  */
    160 target_ulong helper_load_dpdes(CPUPPCState *env)
    161 {
    162     target_ulong dpdes = 0;
    163 
    164     helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
    165 
    166     /* TODO: TCG supports only one thread */
    167     if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
    168         dpdes = 1;
    169     }
    170 
    171     return dpdes;
    172 }
    173 
    174 void helper_store_dpdes(CPUPPCState *env, target_ulong val)
    175 {
    176     PowerPCCPU *cpu = env_archcpu(env);
    177 
    178     helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
    179 
    180     /* TODO: TCG supports only one thread */
    181     if (val & ~0x1) {
    182         qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
    183                       TARGET_FMT_lx"\n", val);
    184         return;
    185     }
    186 
    187     ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
    188 }
    189 #endif /* defined(TARGET_PPC64) */
    190 
    191 void helper_store_pidr(CPUPPCState *env, target_ulong val)
    192 {
    193     env->spr[SPR_BOOKS_PID] = val;
    194     tlb_flush(env_cpu(env));
    195 }
    196 
    197 void helper_store_lpidr(CPUPPCState *env, target_ulong val)
    198 {
    199     env->spr[SPR_LPIDR] = val;
    200 
    201     /*
    202      * We need to flush the TLB on LPID changes as we only tag HV vs
    203      * guest in TCG TLB. Also the quadrants means the HV will
    204      * potentially access and cache entries for the current LPID as
    205      * well.
    206      */
    207     tlb_flush(env_cpu(env));
    208 }
    209 
    210 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
    211 {
    212     /* Bits 26 & 27 affect single-stepping. */
    213     hreg_compute_hflags(env);
    214     /* Bits 28 & 29 affect reset or shutdown. */
    215     store_40x_dbcr0(env, val);
    216 }
    217 
    218 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
    219 {
    220     store_40x_sler(env, val);
    221 }
    222 #endif
    223 
    224 /*****************************************************************************/
    225 /* Special registers manipulation */
    226 
    227 /*
    228  * This code is lifted from MacOnLinux. It is called whenever THRM1,2
    229  * or 3 is read an fixes up the values in such a way that will make
    230  * MacOS not hang. These registers exist on some 75x and 74xx
    231  * processors.
    232  */
    233 void helper_fixup_thrm(CPUPPCState *env)
    234 {
    235     target_ulong v, t;
    236     int i;
    237 
    238 #define THRM1_TIN       (1 << 31)
    239 #define THRM1_TIV       (1 << 30)
    240 #define THRM1_THRES(x)  (((x) & 0x7f) << 23)
    241 #define THRM1_TID       (1 << 2)
    242 #define THRM1_TIE       (1 << 1)
    243 #define THRM1_V         (1 << 0)
    244 #define THRM3_E         (1 << 0)
    245 
    246     if (!(env->spr[SPR_THRM3] & THRM3_E)) {
    247         return;
    248     }
    249 
    250     /* Note: Thermal interrupts are unimplemented */
    251     for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
    252         v = env->spr[i];
    253         if (!(v & THRM1_V)) {
    254             continue;
    255         }
    256         v |= THRM1_TIV;
    257         v &= ~THRM1_TIN;
    258         t = v & THRM1_THRES(127);
    259         if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
    260             v |= THRM1_TIN;
    261         }
    262         if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
    263             v |= THRM1_TIN;
    264         }
    265         env->spr[i] = v;
    266     }
    267 }