helper_regs.c (23944B)
1 /* 2 * PowerPC emulation special registers manipulation helpers for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "qemu/main-loop.h" 23 #include "exec/exec-all.h" 24 #include "sysemu/kvm.h" 25 #include "helper_regs.h" 26 #include "power8-pmu.h" 27 #include "cpu-models.h" 28 #include "spr_common.h" 29 30 /* Swap temporary saved registers with GPRs */ 31 void hreg_swap_gpr_tgpr(CPUPPCState *env) 32 { 33 target_ulong tmp; 34 35 tmp = env->gpr[0]; 36 env->gpr[0] = env->tgpr[0]; 37 env->tgpr[0] = tmp; 38 tmp = env->gpr[1]; 39 env->gpr[1] = env->tgpr[1]; 40 env->tgpr[1] = tmp; 41 tmp = env->gpr[2]; 42 env->gpr[2] = env->tgpr[2]; 43 env->tgpr[2] = tmp; 44 tmp = env->gpr[3]; 45 env->gpr[3] = env->tgpr[3]; 46 env->tgpr[3] = tmp; 47 } 48 49 static uint32_t hreg_compute_hflags_value(CPUPPCState *env) 50 { 51 target_ulong msr = env->msr; 52 uint32_t ppc_flags = env->flags; 53 uint32_t hflags = 0; 54 uint32_t msr_mask; 55 56 /* Some bits come straight across from MSR. */ 57 QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); 58 QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); 59 QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); 60 QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); 61 msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | 62 (1 << MSR_DR) | (1 << MSR_FP)); 63 64 if (ppc_flags & POWERPC_FLAG_DE) { 65 target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 66 if ((dbcr0 & DBCR0_ICMP) && FIELD_EX64(env->msr, MSR, DE)) { 67 hflags |= 1 << HFLAGS_SE; 68 } 69 if ((dbcr0 & DBCR0_BRT) && FIELD_EX64(env->msr, MSR, DE)) { 70 hflags |= 1 << HFLAGS_BE; 71 } 72 } else { 73 if (ppc_flags & POWERPC_FLAG_BE) { 74 QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); 75 msr_mask |= 1 << MSR_BE; 76 } 77 if (ppc_flags & POWERPC_FLAG_SE) { 78 QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); 79 msr_mask |= 1 << MSR_SE; 80 } 81 } 82 83 if (msr_is_64bit(env, msr)) { 84 hflags |= 1 << HFLAGS_64; 85 } 86 if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { 87 hflags |= 1 << HFLAGS_SPE; 88 } 89 if (ppc_flags & POWERPC_FLAG_VRE) { 90 QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); 91 msr_mask |= 1 << MSR_VR; 92 } 93 if (ppc_flags & POWERPC_FLAG_VSX) { 94 QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX); 95 msr_mask |= 1 << MSR_VSX; 96 } 97 if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { 98 hflags |= 1 << HFLAGS_TM; 99 } 100 if (env->spr[SPR_LPCR] & LPCR_GTSE) { 101 hflags |= 1 << HFLAGS_GTSE; 102 } 103 if (env->spr[SPR_LPCR] & LPCR_HR) { 104 hflags |= 1 << HFLAGS_HR; 105 } 106 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) { 107 hflags |= 1 << HFLAGS_PMCC0; 108 } 109 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { 110 hflags |= 1 << HFLAGS_PMCC1; 111 } 112 if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCjCE) { 113 hflags |= 1 << HFLAGS_PMCJCE; 114 } 115 116 #ifndef CONFIG_USER_ONLY 117 if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { 118 hflags |= 1 << HFLAGS_HV; 119 } 120 121 #if defined(TARGET_PPC64) 122 if (env->pmc_ins_cnt) { 123 hflags |= 1 << HFLAGS_INSN_CNT; 124 } 125 if (env->pmc_ins_cnt & 0x1e) { 126 hflags |= 1 << HFLAGS_PMC_OTHER; 127 } 128 #endif 129 130 /* 131 * This is our encoding for server processors. The architecture 132 * specifies that there is no such thing as userspace with 133 * translation off, however it appears that MacOS does it and some 134 * 32-bit CPUs support it. Weird... 135 * 136 * 0 = Guest User space virtual mode 137 * 1 = Guest Kernel space virtual mode 138 * 2 = Guest User space real mode 139 * 3 = Guest Kernel space real mode 140 * 4 = HV User space virtual mode 141 * 5 = HV Kernel space virtual mode 142 * 6 = HV User space real mode 143 * 7 = HV Kernel space real mode 144 * 145 * For BookE, we need 8 MMU modes as follow: 146 * 147 * 0 = AS 0 HV User space 148 * 1 = AS 0 HV Kernel space 149 * 2 = AS 1 HV User space 150 * 3 = AS 1 HV Kernel space 151 * 4 = AS 0 Guest User space 152 * 5 = AS 0 Guest Kernel space 153 * 6 = AS 1 Guest User space 154 * 7 = AS 1 Guest Kernel space 155 */ 156 unsigned immu_idx, dmmu_idx; 157 dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; 158 if (env->mmu_model == POWERPC_MMU_BOOKE || 159 env->mmu_model == POWERPC_MMU_BOOKE206) { 160 dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; 161 immu_idx = dmmu_idx; 162 immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; 163 dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; 164 } else { 165 dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; 166 immu_idx = dmmu_idx; 167 immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; 168 dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; 169 } 170 hflags |= immu_idx << HFLAGS_IMMU_IDX; 171 hflags |= dmmu_idx << HFLAGS_DMMU_IDX; 172 #endif 173 174 return hflags | (msr & msr_mask); 175 } 176 177 void hreg_compute_hflags(CPUPPCState *env) 178 { 179 env->hflags = hreg_compute_hflags_value(env); 180 } 181 182 #ifdef CONFIG_DEBUG_TCG 183 void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 184 target_ulong *cs_base, uint32_t *flags) 185 { 186 uint32_t hflags_current = env->hflags; 187 uint32_t hflags_rebuilt; 188 189 *pc = env->nip; 190 *cs_base = 0; 191 *flags = hflags_current; 192 193 hflags_rebuilt = hreg_compute_hflags_value(env); 194 if (unlikely(hflags_current != hflags_rebuilt)) { 195 cpu_abort(env_cpu(env), 196 "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", 197 hflags_current, hflags_rebuilt); 198 } 199 } 200 #endif 201 202 void cpu_interrupt_exittb(CPUState *cs) 203 { 204 /* 205 * We don't need to worry about translation blocks 206 * when running with KVM. 207 */ 208 if (kvm_enabled()) { 209 return; 210 } 211 212 if (!qemu_mutex_iothread_locked()) { 213 qemu_mutex_lock_iothread(); 214 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 215 qemu_mutex_unlock_iothread(); 216 } else { 217 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 218 } 219 } 220 221 int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) 222 { 223 int excp; 224 #if !defined(CONFIG_USER_ONLY) 225 CPUState *cs = env_cpu(env); 226 #endif 227 228 excp = 0; 229 value &= env->msr_mask; 230 #if !defined(CONFIG_USER_ONLY) 231 /* Neither mtmsr nor guest state can alter HV */ 232 if (!alter_hv || !(env->msr & MSR_HVB)) { 233 value &= ~MSR_HVB; 234 value |= env->msr & MSR_HVB; 235 } 236 if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) { 237 cpu_interrupt_exittb(cs); 238 } 239 if ((env->mmu_model == POWERPC_MMU_BOOKE || 240 env->mmu_model == POWERPC_MMU_BOOKE206) && 241 ((value ^ env->msr) & R_MSR_GS_MASK)) { 242 cpu_interrupt_exittb(cs); 243 } 244 if (unlikely((env->flags & POWERPC_FLAG_TGPR) && 245 ((value ^ env->msr) & (1 << MSR_TGPR)))) { 246 /* Swap temporary saved registers with GPRs */ 247 hreg_swap_gpr_tgpr(env); 248 } 249 if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) { 250 env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000; 251 } 252 /* 253 * If PR=1 then EE, IR and DR must be 1 254 * 255 * Note: We only enforce this on 64-bit server processors. 256 * It appears that: 257 * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS 258 * exploits it. 259 * - 64-bit embedded implementations do not need any operation to be 260 * performed when PR is set. 261 */ 262 if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { 263 value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); 264 } 265 #endif 266 env->msr = value; 267 hreg_compute_hflags(env); 268 #if !defined(CONFIG_USER_ONLY) 269 ppc_maybe_interrupt(env); 270 271 if (unlikely(FIELD_EX64(env->msr, MSR, POW))) { 272 if (!env->pending_interrupts && (*env->check_pow)(env)) { 273 cs->halted = 1; 274 excp = EXCP_HALTED; 275 } 276 } 277 #endif 278 279 return excp; 280 } 281 282 #ifdef CONFIG_SOFTMMU 283 void store_40x_sler(CPUPPCState *env, uint32_t val) 284 { 285 /* XXX: TO BE FIXED */ 286 if (val != 0x00000000) { 287 cpu_abort(env_cpu(env), 288 "Little-endian regions are not supported by now\n"); 289 } 290 env->spr[SPR_405_SLER] = val; 291 } 292 #endif /* CONFIG_SOFTMMU */ 293 294 #ifndef CONFIG_USER_ONLY 295 void check_tlb_flush(CPUPPCState *env, bool global) 296 { 297 CPUState *cs = env_cpu(env); 298 299 /* Handle global flushes first */ 300 if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { 301 env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; 302 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 303 tlb_flush_all_cpus(cs); 304 return; 305 } 306 307 /* Then handle local ones */ 308 if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { 309 env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 310 tlb_flush(cs); 311 } 312 } 313 #endif 314 315 /** 316 * _spr_register 317 * 318 * Register an SPR with all the callbacks required for tcg, 319 * and the ID number for KVM. 320 * 321 * The reason for the conditional compilation is that the tcg functions 322 * may be compiled out, and the system kvm header may not be available 323 * for supplying the ID numbers. This is ugly, but the best we can do. 324 */ 325 void _spr_register(CPUPPCState *env, int num, const char *name, 326 USR_ARG(spr_callback *uea_read) 327 USR_ARG(spr_callback *uea_write) 328 SYS_ARG(spr_callback *oea_read) 329 SYS_ARG(spr_callback *oea_write) 330 SYS_ARG(spr_callback *hea_read) 331 SYS_ARG(spr_callback *hea_write) 332 KVM_ARG(uint64_t one_reg_id) 333 target_ulong initial_value) 334 { 335 ppc_spr_t *spr = &env->spr_cb[num]; 336 337 /* No SPR should be registered twice. */ 338 assert(spr->name == NULL); 339 assert(name != NULL); 340 341 spr->name = name; 342 spr->default_value = initial_value; 343 env->spr[num] = initial_value; 344 345 #ifdef CONFIG_TCG 346 spr->uea_read = uea_read; 347 spr->uea_write = uea_write; 348 # ifndef CONFIG_USER_ONLY 349 spr->oea_read = oea_read; 350 spr->oea_write = oea_write; 351 spr->hea_read = hea_read; 352 spr->hea_write = hea_write; 353 # endif 354 #endif 355 #ifdef CONFIG_KVM 356 spr->one_reg_id = one_reg_id; 357 #endif 358 } 359 360 /* Generic PowerPC SPRs */ 361 void register_generic_sprs(PowerPCCPU *cpu) 362 { 363 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 364 CPUPPCState *env = &cpu->env; 365 366 /* Integer processing */ 367 spr_register(env, SPR_XER, "XER", 368 &spr_read_xer, &spr_write_xer, 369 &spr_read_xer, &spr_write_xer, 370 0x00000000); 371 /* Branch control */ 372 spr_register(env, SPR_LR, "LR", 373 &spr_read_lr, &spr_write_lr, 374 &spr_read_lr, &spr_write_lr, 375 0x00000000); 376 spr_register(env, SPR_CTR, "CTR", 377 &spr_read_ctr, &spr_write_ctr, 378 &spr_read_ctr, &spr_write_ctr, 379 0x00000000); 380 /* Interrupt processing */ 381 spr_register(env, SPR_SRR0, "SRR0", 382 SPR_NOACCESS, SPR_NOACCESS, 383 &spr_read_generic, &spr_write_generic, 384 0x00000000); 385 spr_register(env, SPR_SRR1, "SRR1", 386 SPR_NOACCESS, SPR_NOACCESS, 387 &spr_read_generic, &spr_write_generic, 388 0x00000000); 389 /* Processor control */ 390 spr_register(env, SPR_SPRG0, "SPRG0", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, &spr_write_generic, 393 0x00000000); 394 spr_register(env, SPR_SPRG1, "SPRG1", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, &spr_write_generic, 397 0x00000000); 398 spr_register(env, SPR_SPRG2, "SPRG2", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_generic, &spr_write_generic, 401 0x00000000); 402 spr_register(env, SPR_SPRG3, "SPRG3", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_generic, &spr_write_generic, 405 0x00000000); 406 407 spr_register(env, SPR_PVR, "PVR", 408 /* Linux permits userspace to read PVR */ 409 #if defined(CONFIG_LINUX_USER) 410 &spr_read_generic, 411 #else 412 SPR_NOACCESS, 413 #endif 414 SPR_NOACCESS, 415 &spr_read_generic, SPR_NOACCESS, 416 pcc->pvr); 417 418 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 419 if (pcc->svr != POWERPC_SVR_NONE) { 420 if (pcc->svr & POWERPC_SVR_E500) { 421 spr_register(env, SPR_E500_SVR, "SVR", 422 SPR_NOACCESS, SPR_NOACCESS, 423 &spr_read_generic, SPR_NOACCESS, 424 pcc->svr & ~POWERPC_SVR_E500); 425 } else { 426 spr_register(env, SPR_SVR, "SVR", 427 SPR_NOACCESS, SPR_NOACCESS, 428 &spr_read_generic, SPR_NOACCESS, 429 pcc->svr); 430 } 431 } 432 433 /* Time base */ 434 spr_register(env, SPR_VTBL, "TBL", 435 &spr_read_tbl, SPR_NOACCESS, 436 &spr_read_tbl, SPR_NOACCESS, 437 0x00000000); 438 spr_register(env, SPR_TBL, "TBL", 439 &spr_read_tbl, SPR_NOACCESS, 440 &spr_read_tbl, &spr_write_tbl, 441 0x00000000); 442 spr_register(env, SPR_VTBU, "TBU", 443 &spr_read_tbu, SPR_NOACCESS, 444 &spr_read_tbu, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_TBU, "TBU", 447 &spr_read_tbu, SPR_NOACCESS, 448 &spr_read_tbu, &spr_write_tbu, 449 0x00000000); 450 } 451 452 void register_non_embedded_sprs(CPUPPCState *env) 453 { 454 /* Exception processing */ 455 spr_register_kvm(env, SPR_DSISR, "DSISR", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 KVM_REG_PPC_DSISR, 0x00000000); 459 spr_register_kvm(env, SPR_DAR, "DAR", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 KVM_REG_PPC_DAR, 0x00000000); 463 /* Timer */ 464 spr_register(env, SPR_DECR, "DECR", 465 SPR_NOACCESS, SPR_NOACCESS, 466 &spr_read_decr, &spr_write_decr, 467 0x00000000); 468 } 469 470 /* Storage Description Register 1 */ 471 void register_sdr1_sprs(CPUPPCState *env) 472 { 473 #ifndef CONFIG_USER_ONLY 474 if (env->has_hv_mode) { 475 /* 476 * SDR1 is a hypervisor resource on CPUs which have a 477 * hypervisor mode 478 */ 479 spr_register_hv(env, SPR_SDR1, "SDR1", 480 SPR_NOACCESS, SPR_NOACCESS, 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_sdr1, 483 0x00000000); 484 } else { 485 spr_register(env, SPR_SDR1, "SDR1", 486 SPR_NOACCESS, SPR_NOACCESS, 487 &spr_read_generic, &spr_write_sdr1, 488 0x00000000); 489 } 490 #endif 491 } 492 493 /* BATs 0-3 */ 494 void register_low_BATs(CPUPPCState *env) 495 { 496 #if !defined(CONFIG_USER_ONLY) 497 spr_register(env, SPR_IBAT0U, "IBAT0U", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_ibat, &spr_write_ibatu, 500 0x00000000); 501 spr_register(env, SPR_IBAT0L, "IBAT0L", 502 SPR_NOACCESS, SPR_NOACCESS, 503 &spr_read_ibat, &spr_write_ibatl, 504 0x00000000); 505 spr_register(env, SPR_IBAT1U, "IBAT1U", 506 SPR_NOACCESS, SPR_NOACCESS, 507 &spr_read_ibat, &spr_write_ibatu, 508 0x00000000); 509 spr_register(env, SPR_IBAT1L, "IBAT1L", 510 SPR_NOACCESS, SPR_NOACCESS, 511 &spr_read_ibat, &spr_write_ibatl, 512 0x00000000); 513 spr_register(env, SPR_IBAT2U, "IBAT2U", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_ibat, &spr_write_ibatu, 516 0x00000000); 517 spr_register(env, SPR_IBAT2L, "IBAT2L", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_ibat, &spr_write_ibatl, 520 0x00000000); 521 spr_register(env, SPR_IBAT3U, "IBAT3U", 522 SPR_NOACCESS, SPR_NOACCESS, 523 &spr_read_ibat, &spr_write_ibatu, 524 0x00000000); 525 spr_register(env, SPR_IBAT3L, "IBAT3L", 526 SPR_NOACCESS, SPR_NOACCESS, 527 &spr_read_ibat, &spr_write_ibatl, 528 0x00000000); 529 spr_register(env, SPR_DBAT0U, "DBAT0U", 530 SPR_NOACCESS, SPR_NOACCESS, 531 &spr_read_dbat, &spr_write_dbatu, 532 0x00000000); 533 spr_register(env, SPR_DBAT0L, "DBAT0L", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_dbat, &spr_write_dbatl, 536 0x00000000); 537 spr_register(env, SPR_DBAT1U, "DBAT1U", 538 SPR_NOACCESS, SPR_NOACCESS, 539 &spr_read_dbat, &spr_write_dbatu, 540 0x00000000); 541 spr_register(env, SPR_DBAT1L, "DBAT1L", 542 SPR_NOACCESS, SPR_NOACCESS, 543 &spr_read_dbat, &spr_write_dbatl, 544 0x00000000); 545 spr_register(env, SPR_DBAT2U, "DBAT2U", 546 SPR_NOACCESS, SPR_NOACCESS, 547 &spr_read_dbat, &spr_write_dbatu, 548 0x00000000); 549 spr_register(env, SPR_DBAT2L, "DBAT2L", 550 SPR_NOACCESS, SPR_NOACCESS, 551 &spr_read_dbat, &spr_write_dbatl, 552 0x00000000); 553 spr_register(env, SPR_DBAT3U, "DBAT3U", 554 SPR_NOACCESS, SPR_NOACCESS, 555 &spr_read_dbat, &spr_write_dbatu, 556 0x00000000); 557 spr_register(env, SPR_DBAT3L, "DBAT3L", 558 SPR_NOACCESS, SPR_NOACCESS, 559 &spr_read_dbat, &spr_write_dbatl, 560 0x00000000); 561 env->nb_BATs += 4; 562 #endif 563 } 564 565 /* BATs 4-7 */ 566 void register_high_BATs(CPUPPCState *env) 567 { 568 #if !defined(CONFIG_USER_ONLY) 569 spr_register(env, SPR_IBAT4U, "IBAT4U", 570 SPR_NOACCESS, SPR_NOACCESS, 571 &spr_read_ibat_h, &spr_write_ibatu_h, 572 0x00000000); 573 spr_register(env, SPR_IBAT4L, "IBAT4L", 574 SPR_NOACCESS, SPR_NOACCESS, 575 &spr_read_ibat_h, &spr_write_ibatl_h, 576 0x00000000); 577 spr_register(env, SPR_IBAT5U, "IBAT5U", 578 SPR_NOACCESS, SPR_NOACCESS, 579 &spr_read_ibat_h, &spr_write_ibatu_h, 580 0x00000000); 581 spr_register(env, SPR_IBAT5L, "IBAT5L", 582 SPR_NOACCESS, SPR_NOACCESS, 583 &spr_read_ibat_h, &spr_write_ibatl_h, 584 0x00000000); 585 spr_register(env, SPR_IBAT6U, "IBAT6U", 586 SPR_NOACCESS, SPR_NOACCESS, 587 &spr_read_ibat_h, &spr_write_ibatu_h, 588 0x00000000); 589 spr_register(env, SPR_IBAT6L, "IBAT6L", 590 SPR_NOACCESS, SPR_NOACCESS, 591 &spr_read_ibat_h, &spr_write_ibatl_h, 592 0x00000000); 593 spr_register(env, SPR_IBAT7U, "IBAT7U", 594 SPR_NOACCESS, SPR_NOACCESS, 595 &spr_read_ibat_h, &spr_write_ibatu_h, 596 0x00000000); 597 spr_register(env, SPR_IBAT7L, "IBAT7L", 598 SPR_NOACCESS, SPR_NOACCESS, 599 &spr_read_ibat_h, &spr_write_ibatl_h, 600 0x00000000); 601 spr_register(env, SPR_DBAT4U, "DBAT4U", 602 SPR_NOACCESS, SPR_NOACCESS, 603 &spr_read_dbat_h, &spr_write_dbatu_h, 604 0x00000000); 605 spr_register(env, SPR_DBAT4L, "DBAT4L", 606 SPR_NOACCESS, SPR_NOACCESS, 607 &spr_read_dbat_h, &spr_write_dbatl_h, 608 0x00000000); 609 spr_register(env, SPR_DBAT5U, "DBAT5U", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_dbat_h, &spr_write_dbatu_h, 612 0x00000000); 613 spr_register(env, SPR_DBAT5L, "DBAT5L", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_dbat_h, &spr_write_dbatl_h, 616 0x00000000); 617 spr_register(env, SPR_DBAT6U, "DBAT6U", 618 SPR_NOACCESS, SPR_NOACCESS, 619 &spr_read_dbat_h, &spr_write_dbatu_h, 620 0x00000000); 621 spr_register(env, SPR_DBAT6L, "DBAT6L", 622 SPR_NOACCESS, SPR_NOACCESS, 623 &spr_read_dbat_h, &spr_write_dbatl_h, 624 0x00000000); 625 spr_register(env, SPR_DBAT7U, "DBAT7U", 626 SPR_NOACCESS, SPR_NOACCESS, 627 &spr_read_dbat_h, &spr_write_dbatu_h, 628 0x00000000); 629 spr_register(env, SPR_DBAT7L, "DBAT7L", 630 SPR_NOACCESS, SPR_NOACCESS, 631 &spr_read_dbat_h, &spr_write_dbatl_h, 632 0x00000000); 633 env->nb_BATs += 4; 634 #endif 635 } 636 637 /* Softare table search registers */ 638 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 639 { 640 #if !defined(CONFIG_USER_ONLY) 641 env->nb_tlb = nb_tlbs; 642 env->nb_ways = nb_ways; 643 env->id_tlbs = 1; 644 env->tlb_type = TLB_6XX; 645 spr_register(env, SPR_DMISS, "DMISS", 646 SPR_NOACCESS, SPR_NOACCESS, 647 &spr_read_generic, SPR_NOACCESS, 648 0x00000000); 649 spr_register(env, SPR_DCMP, "DCMP", 650 SPR_NOACCESS, SPR_NOACCESS, 651 &spr_read_generic, SPR_NOACCESS, 652 0x00000000); 653 spr_register(env, SPR_HASH1, "HASH1", 654 SPR_NOACCESS, SPR_NOACCESS, 655 &spr_read_generic, SPR_NOACCESS, 656 0x00000000); 657 spr_register(env, SPR_HASH2, "HASH2", 658 SPR_NOACCESS, SPR_NOACCESS, 659 &spr_read_generic, SPR_NOACCESS, 660 0x00000000); 661 spr_register(env, SPR_IMISS, "IMISS", 662 SPR_NOACCESS, SPR_NOACCESS, 663 &spr_read_generic, SPR_NOACCESS, 664 0x00000000); 665 spr_register(env, SPR_ICMP, "ICMP", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 spr_register(env, SPR_RPA, "RPA", 670 SPR_NOACCESS, SPR_NOACCESS, 671 &spr_read_generic, &spr_write_generic, 672 0x00000000); 673 #endif 674 } 675 676 void register_thrm_sprs(CPUPPCState *env) 677 { 678 /* Thermal management */ 679 spr_register(env, SPR_THRM1, "THRM1", 680 SPR_NOACCESS, SPR_NOACCESS, 681 &spr_read_thrm, &spr_write_generic, 682 0x00000000); 683 684 spr_register(env, SPR_THRM2, "THRM2", 685 SPR_NOACCESS, SPR_NOACCESS, 686 &spr_read_thrm, &spr_write_generic, 687 0x00000000); 688 689 spr_register(env, SPR_THRM3, "THRM3", 690 SPR_NOACCESS, SPR_NOACCESS, 691 &spr_read_thrm, &spr_write_generic, 692 0x00000000); 693 } 694 695 void register_usprgh_sprs(CPUPPCState *env) 696 { 697 spr_register(env, SPR_USPRG4, "USPRG4", 698 &spr_read_ureg, SPR_NOACCESS, 699 &spr_read_ureg, SPR_NOACCESS, 700 0x00000000); 701 spr_register(env, SPR_USPRG5, "USPRG5", 702 &spr_read_ureg, SPR_NOACCESS, 703 &spr_read_ureg, SPR_NOACCESS, 704 0x00000000); 705 spr_register(env, SPR_USPRG6, "USPRG6", 706 &spr_read_ureg, SPR_NOACCESS, 707 &spr_read_ureg, SPR_NOACCESS, 708 0x00000000); 709 spr_register(env, SPR_USPRG7, "USPRG7", 710 &spr_read_ureg, SPR_NOACCESS, 711 &spr_read_ureg, SPR_NOACCESS, 712 0x00000000); 713 }