cpu.c (11157B)
1 /* 2 * QEMU Nios II CPU 3 * 4 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/module.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "exec/log.h" 26 #include "exec/gdbstub.h" 27 #include "hw/qdev-properties.h" 28 29 static void nios2_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 Nios2CPU *cpu = NIOS2_CPU(cs); 32 CPUNios2State *env = &cpu->env; 33 34 env->pc = value; 35 } 36 37 static vaddr nios2_cpu_get_pc(CPUState *cs) 38 { 39 Nios2CPU *cpu = NIOS2_CPU(cs); 40 CPUNios2State *env = &cpu->env; 41 42 return env->pc; 43 } 44 45 static void nios2_restore_state_to_opc(CPUState *cs, 46 const TranslationBlock *tb, 47 const uint64_t *data) 48 { 49 Nios2CPU *cpu = NIOS2_CPU(cs); 50 CPUNios2State *env = &cpu->env; 51 52 env->pc = data[0]; 53 } 54 55 static bool nios2_cpu_has_work(CPUState *cs) 56 { 57 return cs->interrupt_request & CPU_INTERRUPT_HARD; 58 } 59 60 static void nios2_cpu_reset(DeviceState *dev) 61 { 62 CPUState *cs = CPU(dev); 63 Nios2CPU *cpu = NIOS2_CPU(cs); 64 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu); 65 CPUNios2State *env = &cpu->env; 66 67 ncc->parent_reset(dev); 68 69 memset(env->ctrl, 0, sizeof(env->ctrl)); 70 env->pc = cpu->reset_addr; 71 72 #if defined(CONFIG_USER_ONLY) 73 /* Start in user mode with interrupts enabled. */ 74 env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; 75 memset(env->regs, 0, sizeof(env->regs)); 76 #else 77 env->ctrl[CR_STATUS] = CR_STATUS_RSIE; 78 nios2_update_crs(env); 79 memset(env->shadow_regs, 0, sizeof(env->shadow_regs)); 80 #endif 81 } 82 83 #ifndef CONFIG_USER_ONLY 84 static void eic_set_irq(void *opaque, int irq, int level) 85 { 86 Nios2CPU *cpu = opaque; 87 CPUState *cs = CPU(cpu); 88 89 if (level) { 90 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 91 } else { 92 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 93 } 94 } 95 96 static void iic_set_irq(void *opaque, int irq, int level) 97 { 98 Nios2CPU *cpu = opaque; 99 CPUNios2State *env = &cpu->env; 100 CPUState *cs = CPU(cpu); 101 102 env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level); 103 104 if (env->ctrl[CR_IPENDING]) { 105 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 106 } else { 107 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 108 } 109 } 110 #endif 111 112 static void nios2_cpu_initfn(Object *obj) 113 { 114 Nios2CPU *cpu = NIOS2_CPU(obj); 115 116 cpu_set_cpustate_pointers(cpu); 117 118 #if !defined(CONFIG_USER_ONLY) 119 mmu_init(&cpu->env); 120 #endif 121 } 122 123 static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model) 124 { 125 return object_class_by_name(TYPE_NIOS2_CPU); 126 } 127 128 static void realize_cr_status(CPUState *cs) 129 { 130 Nios2CPU *cpu = NIOS2_CPU(cs); 131 132 /* Begin with all fields of all registers are reserved. */ 133 memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); 134 135 /* 136 * The combination of writable and readonly is the set of all 137 * non-reserved fields. We apply writable as a mask to bits, 138 * and merge in existing readonly bits, before storing. 139 */ 140 #define WR_REG(C) cpu->cr_state[C].writable = -1 141 #define RO_REG(C) cpu->cr_state[C].readonly = -1 142 #define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK 143 #define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK 144 145 WR_FIELD(CR_STATUS, PIE); 146 WR_REG(CR_ESTATUS); 147 WR_REG(CR_BSTATUS); 148 RO_REG(CR_CPUID); 149 RO_REG(CR_EXCEPTION); 150 WR_REG(CR_BADADDR); 151 152 if (cpu->eic_present) { 153 WR_FIELD(CR_STATUS, RSIE); 154 RO_FIELD(CR_STATUS, NMI); 155 WR_FIELD(CR_STATUS, PRS); 156 RO_FIELD(CR_STATUS, CRS); 157 WR_FIELD(CR_STATUS, IL); 158 WR_FIELD(CR_STATUS, IH); 159 } else { 160 RO_FIELD(CR_STATUS, RSIE); 161 WR_REG(CR_IENABLE); 162 RO_REG(CR_IPENDING); 163 } 164 165 if (cpu->mmu_present) { 166 WR_FIELD(CR_STATUS, U); 167 WR_FIELD(CR_STATUS, EH); 168 169 WR_FIELD(CR_PTEADDR, VPN); 170 WR_FIELD(CR_PTEADDR, PTBASE); 171 172 RO_FIELD(CR_TLBMISC, D); 173 RO_FIELD(CR_TLBMISC, PERM); 174 RO_FIELD(CR_TLBMISC, BAD); 175 RO_FIELD(CR_TLBMISC, DBL); 176 WR_FIELD(CR_TLBMISC, PID); 177 WR_FIELD(CR_TLBMISC, WE); 178 WR_FIELD(CR_TLBMISC, RD); 179 WR_FIELD(CR_TLBMISC, WAY); 180 181 WR_REG(CR_TLBACC); 182 } 183 184 /* 185 * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are 186 * unimplemented, so their corresponding control regs remain reserved. 187 */ 188 189 #undef WR_REG 190 #undef RO_REG 191 #undef WR_FIELD 192 #undef RO_FIELD 193 } 194 195 static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) 196 { 197 CPUState *cs = CPU(dev); 198 Nios2CPU *cpu = NIOS2_CPU(cs); 199 Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev); 200 Error *local_err = NULL; 201 202 #ifndef CONFIG_USER_ONLY 203 if (cpu->eic_present) { 204 qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); 205 } else { 206 qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); 207 } 208 #endif 209 210 cpu_exec_realizefn(cs, &local_err); 211 if (local_err != NULL) { 212 error_propagate(errp, local_err); 213 return; 214 } 215 216 realize_cr_status(cs); 217 qemu_init_vcpu(cs); 218 cpu_reset(cs); 219 220 /* We have reserved storage for cpuid; might as well use it. */ 221 cpu->env.ctrl[CR_CPUID] = cs->cpu_index; 222 223 ncc->parent_realize(dev, errp); 224 } 225 226 #ifndef CONFIG_USER_ONLY 227 static bool eic_take_interrupt(Nios2CPU *cpu) 228 { 229 CPUNios2State *env = &cpu->env; 230 const uint32_t status = env->ctrl[CR_STATUS]; 231 232 if (cpu->rnmi) { 233 return !(status & CR_STATUS_NMI); 234 } 235 if (!(status & CR_STATUS_PIE)) { 236 return false; 237 } 238 if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) { 239 return false; 240 } 241 if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) { 242 return true; 243 } 244 return status & CR_STATUS_RSIE; 245 } 246 247 static bool iic_take_interrupt(Nios2CPU *cpu) 248 { 249 CPUNios2State *env = &cpu->env; 250 251 if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) { 252 return false; 253 } 254 return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE]; 255 } 256 257 static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 258 { 259 Nios2CPU *cpu = NIOS2_CPU(cs); 260 261 if (interrupt_request & CPU_INTERRUPT_HARD) { 262 if (cpu->eic_present 263 ? eic_take_interrupt(cpu) 264 : iic_take_interrupt(cpu)) { 265 cs->exception_index = EXCP_IRQ; 266 nios2_cpu_do_interrupt(cs); 267 return true; 268 } 269 } 270 return false; 271 } 272 #endif /* !CONFIG_USER_ONLY */ 273 274 static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 275 { 276 /* NOTE: NiosII R2 is not supported yet. */ 277 info->mach = bfd_arch_nios2; 278 info->print_insn = print_insn_nios2; 279 } 280 281 static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) 282 { 283 Nios2CPU *cpu = NIOS2_CPU(cs); 284 CPUNios2State *env = &cpu->env; 285 uint32_t val; 286 287 if (n < 32) { /* GP regs */ 288 val = env->regs[n]; 289 } else if (n == 32) { /* PC */ 290 val = env->pc; 291 } else if (n < 49) { /* Status regs */ 292 unsigned cr = n - 33; 293 if (nios2_cr_reserved(&cpu->cr_state[cr])) { 294 val = 0; 295 } else { 296 val = env->ctrl[n - 33]; 297 } 298 } else { 299 /* Invalid regs */ 300 return 0; 301 } 302 303 return gdb_get_reg32(mem_buf, val); 304 } 305 306 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) 307 { 308 Nios2CPU *cpu = NIOS2_CPU(cs); 309 CPUClass *cc = CPU_GET_CLASS(cs); 310 CPUNios2State *env = &cpu->env; 311 uint32_t val; 312 313 if (n > cc->gdb_num_core_regs) { 314 return 0; 315 } 316 val = ldl_p(mem_buf); 317 318 if (n < 32) { /* GP regs */ 319 env->regs[n] = val; 320 } else if (n == 32) { /* PC */ 321 env->pc = val; 322 } else if (n < 49) { /* Status regs */ 323 unsigned cr = n - 33; 324 /* ??? Maybe allow the debugger to write to readonly fields. */ 325 val &= cpu->cr_state[cr].writable; 326 val |= cpu->cr_state[cr].readonly & env->ctrl[cr]; 327 env->ctrl[cr] = val; 328 } else { 329 g_assert_not_reached(); 330 } 331 332 return 4; 333 } 334 335 static Property nios2_properties[] = { 336 DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true), 337 DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), 338 /* ALTR,pid-num-bits */ 339 DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), 340 /* ALTR,tlb-num-ways */ 341 DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16), 342 /* ALTR,tlb-num-entries */ 343 DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256), 344 DEFINE_PROP_END_OF_LIST(), 345 }; 346 347 #ifndef CONFIG_USER_ONLY 348 #include "hw/core/sysemu-cpu-ops.h" 349 350 static const struct SysemuCPUOps nios2_sysemu_ops = { 351 .get_phys_page_debug = nios2_cpu_get_phys_page_debug, 352 }; 353 #endif 354 355 #include "hw/core/tcg-cpu-ops.h" 356 357 static const struct TCGCPUOps nios2_tcg_ops = { 358 .initialize = nios2_tcg_init, 359 .restore_state_to_opc = nios2_restore_state_to_opc, 360 361 #ifndef CONFIG_USER_ONLY 362 .tlb_fill = nios2_cpu_tlb_fill, 363 .cpu_exec_interrupt = nios2_cpu_exec_interrupt, 364 .do_interrupt = nios2_cpu_do_interrupt, 365 .do_unaligned_access = nios2_cpu_do_unaligned_access, 366 #endif /* !CONFIG_USER_ONLY */ 367 }; 368 369 static void nios2_cpu_class_init(ObjectClass *oc, void *data) 370 { 371 DeviceClass *dc = DEVICE_CLASS(oc); 372 CPUClass *cc = CPU_CLASS(oc); 373 Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc); 374 375 device_class_set_parent_realize(dc, nios2_cpu_realizefn, 376 &ncc->parent_realize); 377 device_class_set_props(dc, nios2_properties); 378 device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset); 379 380 cc->class_by_name = nios2_cpu_class_by_name; 381 cc->has_work = nios2_cpu_has_work; 382 cc->dump_state = nios2_cpu_dump_state; 383 cc->set_pc = nios2_cpu_set_pc; 384 cc->get_pc = nios2_cpu_get_pc; 385 cc->disas_set_info = nios2_cpu_disas_set_info; 386 #ifndef CONFIG_USER_ONLY 387 cc->sysemu_ops = &nios2_sysemu_ops; 388 #endif 389 cc->gdb_read_register = nios2_cpu_gdb_read_register; 390 cc->gdb_write_register = nios2_cpu_gdb_write_register; 391 cc->gdb_num_core_regs = 49; 392 cc->tcg_ops = &nios2_tcg_ops; 393 } 394 395 static const TypeInfo nios2_cpu_type_info = { 396 .name = TYPE_NIOS2_CPU, 397 .parent = TYPE_CPU, 398 .instance_size = sizeof(Nios2CPU), 399 .instance_init = nios2_cpu_initfn, 400 .class_size = sizeof(Nios2CPUClass), 401 .class_init = nios2_cpu_class_init, 402 }; 403 404 static void nios2_cpu_register_types(void) 405 { 406 type_register_static(&nios2_cpu_type_info); 407 } 408 409 type_init(nios2_cpu_register_types)