machine.c (10975B)
1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "internal.h" 4 #include "migration/cpu.h" 5 #include "fpu_helper.h" 6 7 static int cpu_post_load(void *opaque, int version_id) 8 { 9 MIPSCPU *cpu = opaque; 10 CPUMIPSState *env = &cpu->env; 11 12 restore_fp_status(env); 13 restore_msa_fp_status(env); 14 compute_hflags(env); 15 restore_pamask(env); 16 17 return 0; 18 } 19 20 /* FPU state */ 21 22 static int get_fpr(QEMUFile *f, void *pv, size_t size, 23 const VMStateField *field) 24 { 25 int i; 26 fpr_t *v = pv; 27 /* Restore entire MSA vector register */ 28 for (i = 0; i < MSA_WRLEN / 64; i++) { 29 qemu_get_sbe64s(f, &v->wr.d[i]); 30 } 31 return 0; 32 } 33 34 static int put_fpr(QEMUFile *f, void *pv, size_t size, 35 const VMStateField *field, JSONWriter *vmdesc) 36 { 37 int i; 38 fpr_t *v = pv; 39 /* Save entire MSA vector register */ 40 for (i = 0; i < MSA_WRLEN / 64; i++) { 41 qemu_put_sbe64s(f, &v->wr.d[i]); 42 } 43 44 return 0; 45 } 46 47 const VMStateInfo vmstate_info_fpr = { 48 .name = "fpr", 49 .get = get_fpr, 50 .put = put_fpr, 51 }; 52 53 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ 54 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t) 55 56 #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ 57 VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) 58 59 static VMStateField vmstate_fpu_fields[] = { 60 VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), 61 VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), 62 VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), 63 VMSTATE_END_OF_LIST() 64 }; 65 66 const VMStateDescription vmstate_fpu = { 67 .name = "cpu/fpu", 68 .version_id = 1, 69 .minimum_version_id = 1, 70 .fields = vmstate_fpu_fields 71 }; 72 73 const VMStateDescription vmstate_inactive_fpu = { 74 .name = "cpu/inactive_fpu", 75 .version_id = 1, 76 .minimum_version_id = 1, 77 .fields = vmstate_fpu_fields 78 }; 79 80 /* TC state */ 81 82 static VMStateField vmstate_tc_fields[] = { 83 VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), 84 #if defined(TARGET_MIPS64) 85 VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32), 86 #endif /* TARGET_MIPS64 */ 87 VMSTATE_UINTTL(PC, TCState), 88 VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), 89 VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), 90 VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), 91 VMSTATE_UINTTL(DSPControl, TCState), 92 VMSTATE_INT32(CP0_TCStatus, TCState), 93 VMSTATE_INT32(CP0_TCBind, TCState), 94 VMSTATE_UINTTL(CP0_TCHalt, TCState), 95 VMSTATE_UINTTL(CP0_TCContext, TCState), 96 VMSTATE_UINTTL(CP0_TCSchedule, TCState), 97 VMSTATE_UINTTL(CP0_TCScheFBack, TCState), 98 VMSTATE_INT32(CP0_Debug_tcstatus, TCState), 99 VMSTATE_UINTTL(CP0_UserLocal, TCState), 100 VMSTATE_INT32(msacsr, TCState), 101 VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1), 102 VMSTATE_UINTTL(mxu_cr, TCState), 103 VMSTATE_END_OF_LIST() 104 }; 105 106 const VMStateDescription vmstate_tc = { 107 .name = "cpu/tc", 108 .version_id = 2, 109 .minimum_version_id = 2, 110 .fields = vmstate_tc_fields 111 }; 112 113 const VMStateDescription vmstate_inactive_tc = { 114 .name = "cpu/inactive_tc", 115 .version_id = 2, 116 .minimum_version_id = 2, 117 .fields = vmstate_tc_fields 118 }; 119 120 /* MVP state */ 121 122 const VMStateDescription vmstate_mvp = { 123 .name = "cpu/mvp", 124 .version_id = 1, 125 .minimum_version_id = 1, 126 .fields = (VMStateField[]) { 127 VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext), 128 VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext), 129 VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext), 130 VMSTATE_END_OF_LIST() 131 } 132 }; 133 134 /* TLB state */ 135 136 static int get_tlb(QEMUFile *f, void *pv, size_t size, 137 const VMStateField *field) 138 { 139 r4k_tlb_t *v = pv; 140 uint16_t flags; 141 142 qemu_get_betls(f, &v->VPN); 143 qemu_get_be32s(f, &v->PageMask); 144 qemu_get_be16s(f, &v->ASID); 145 qemu_get_be16s(f, &flags); 146 v->G = (flags >> 10) & 1; 147 v->C0 = (flags >> 7) & 3; 148 v->C1 = (flags >> 4) & 3; 149 v->V0 = (flags >> 3) & 1; 150 v->V1 = (flags >> 2) & 1; 151 v->D0 = (flags >> 1) & 1; 152 v->D1 = (flags >> 0) & 1; 153 v->EHINV = (flags >> 15) & 1; 154 v->RI1 = (flags >> 14) & 1; 155 v->RI0 = (flags >> 13) & 1; 156 v->XI1 = (flags >> 12) & 1; 157 v->XI0 = (flags >> 11) & 1; 158 qemu_get_be64s(f, &v->PFN[0]); 159 qemu_get_be64s(f, &v->PFN[1]); 160 161 return 0; 162 } 163 164 static int put_tlb(QEMUFile *f, void *pv, size_t size, 165 const VMStateField *field, JSONWriter *vmdesc) 166 { 167 r4k_tlb_t *v = pv; 168 169 uint16_t asid = v->ASID; 170 uint16_t flags = ((v->EHINV << 15) | 171 (v->RI1 << 14) | 172 (v->RI0 << 13) | 173 (v->XI1 << 12) | 174 (v->XI0 << 11) | 175 (v->G << 10) | 176 (v->C0 << 7) | 177 (v->C1 << 4) | 178 (v->V0 << 3) | 179 (v->V1 << 2) | 180 (v->D0 << 1) | 181 (v->D1 << 0)); 182 183 qemu_put_betls(f, &v->VPN); 184 qemu_put_be32s(f, &v->PageMask); 185 qemu_put_be16s(f, &asid); 186 qemu_put_be16s(f, &flags); 187 qemu_put_be64s(f, &v->PFN[0]); 188 qemu_put_be64s(f, &v->PFN[1]); 189 190 return 0; 191 } 192 193 const VMStateInfo vmstate_info_tlb = { 194 .name = "tlb_entry", 195 .get = get_tlb, 196 .put = put_tlb, 197 }; 198 199 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \ 200 VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t) 201 202 #define VMSTATE_TLB_ARRAY(_f, _s, _n) \ 203 VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0) 204 205 const VMStateDescription vmstate_tlb = { 206 .name = "cpu/tlb", 207 .version_id = 2, 208 .minimum_version_id = 2, 209 .fields = (VMStateField[]) { 210 VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), 211 VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), 212 VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX), 213 VMSTATE_END_OF_LIST() 214 } 215 }; 216 217 /* MIPS CPU state */ 218 219 const VMStateDescription vmstate_mips_cpu = { 220 .name = "cpu", 221 .version_id = 21, 222 .minimum_version_id = 21, 223 .post_load = cpu_post_load, 224 .fields = (VMStateField[]) { 225 /* Active TC */ 226 VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState), 227 228 /* Active FPU */ 229 VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu, 230 CPUMIPSFPUContext), 231 232 /* MVP */ 233 VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp, 234 CPUMIPSMVPContext), 235 236 /* TLB */ 237 VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb, 238 CPUMIPSTLBContext), 239 240 /* CPU metastate */ 241 VMSTATE_UINT32(env.current_tc, MIPSCPU), 242 VMSTATE_UINT32(env.current_fpu, MIPSCPU), 243 VMSTATE_INT32(env.error_code, MIPSCPU), 244 VMSTATE_UINTTL(env.btarget, MIPSCPU), 245 VMSTATE_UINTTL(env.bcond, MIPSCPU), 246 247 /* Remaining CP0 registers */ 248 VMSTATE_INT32(env.CP0_Index, MIPSCPU), 249 VMSTATE_INT32(env.CP0_VPControl, MIPSCPU), 250 VMSTATE_INT32(env.CP0_Random, MIPSCPU), 251 VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), 252 VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), 253 VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU), 254 VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU), 255 VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU), 256 VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU), 257 VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), 258 VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), 259 VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), 260 VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU), 261 VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), 262 VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), 263 VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), 264 VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), 265 VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), 266 VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), 267 VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), 268 VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), 269 VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), 270 VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU), 271 VMSTATE_INT32(env.CP0_Wired, MIPSCPU), 272 VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU), 273 VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), 274 VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), 275 VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), 276 VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU), 277 VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU), 278 VMSTATE_INT32(env.CP0_HWREna, MIPSCPU), 279 VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), 280 VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), 281 VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), 282 VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), 283 VMSTATE_INT32(env.CP0_Count, MIPSCPU), 284 VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), 285 VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), 286 VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), 287 VMSTATE_INT32(env.CP0_Compare, MIPSCPU), 288 VMSTATE_INT32(env.CP0_Status, MIPSCPU), 289 VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), 290 VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), 291 VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), 292 VMSTATE_INT32(env.CP0_Cause, MIPSCPU), 293 VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), 294 VMSTATE_INT32(env.CP0_PRid, MIPSCPU), 295 VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), 296 VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU), 297 VMSTATE_INT32(env.CP0_Config0, MIPSCPU), 298 VMSTATE_INT32(env.CP0_Config1, MIPSCPU), 299 VMSTATE_INT32(env.CP0_Config2, MIPSCPU), 300 VMSTATE_INT32(env.CP0_Config3, MIPSCPU), 301 VMSTATE_INT32(env.CP0_Config4, MIPSCPU), 302 VMSTATE_INT32(env.CP0_Config5, MIPSCPU), 303 VMSTATE_INT32(env.CP0_Config6, MIPSCPU), 304 VMSTATE_INT32(env.CP0_Config7, MIPSCPU), 305 VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), 306 VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), 307 VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), 308 VMSTATE_UINTTL(env.lladdr, MIPSCPU), 309 VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), 310 VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), 311 VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), 312 VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), 313 VMSTATE_INT32(env.CP0_Debug, MIPSCPU), 314 VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), 315 VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), 316 VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU), 317 VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), 318 VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), 319 VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), 320 VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), 321 VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), 322 VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), 323 VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), 324 325 /* Inactive TC */ 326 VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, 327 vmstate_inactive_tc, TCState), 328 VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, 329 vmstate_inactive_fpu, CPUMIPSFPUContext), 330 331 VMSTATE_END_OF_LIST() 332 }, 333 };