cpu-defs.c.inc (44760B)
1 /* 2 * MIPS emulation for qemu: CPU initialisation routines. 3 * 4 * Copyright (c) 2004-2005 Jocelyn Mayer 5 * Copyright (c) 2007 Herve Poussineau 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 /* CPU / CPU family specific config register values. */ 22 23 /* Have config1, uncached coherency */ 24 #define MIPS_CONFIG0 \ 25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) 26 27 /* Have config2, no coprocessor2 attached, no MDMX support attached, 28 no performance counters, watch registers present, 29 no code compression, EJTAG present, no FPU */ 30 #define MIPS_CONFIG1 \ 31 ((1U << CP0C1_M) | \ 32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ 33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ 34 (0 << CP0C1_FP)) 35 36 /* Have config3, no tertiary/secondary caches implemented */ 37 #define MIPS_CONFIG2 \ 38 ((1U << CP0C2_M)) 39 40 /* No config4, no DSP ASE, no large physaddr (PABITS), 41 no external interrupt controller, no vectored interrupts, 42 no 1kb pages, no SmartMIPS ASE, no trace logic */ 43 #define MIPS_CONFIG3 \ 44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ 45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ 46 (0 << CP0C3_SM) | (0 << CP0C3_TL)) 47 48 #define MIPS_CONFIG4 \ 49 ((0 << CP0C4_M)) 50 51 #define MIPS_CONFIG5 \ 52 ((0 << CP0C5_M)) 53 54 /*****************************************************************************/ 55 /* MIPS CPU definitions */ 56 const mips_def_t mips_defs[] = 57 { 58 { 59 .name = "4Kc", 60 .CP0_PRid = 0x00018000, 61 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), 62 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 65 (0 << CP0C1_CA), 66 .CP0_Config2 = MIPS_CONFIG2, 67 .CP0_Config3 = MIPS_CONFIG3, 68 .CP0_LLAddr_rw_bitmask = 0, 69 .CP0_LLAddr_shift = 4, 70 .SYNCI_Step = 32, 71 .CCRes = 2, 72 .CP0_Status_rw_bitmask = 0x1278FF17, 73 .SEGBITS = 32, 74 .PABITS = 32, 75 .insn_flags = CPU_MIPS32R1, 76 .mmu_type = MMU_TYPE_R4000, 77 }, 78 { 79 .name = "4Km", 80 .CP0_PRid = 0x00018300, 81 /* Config1 implemented, fixed mapping MMU, 82 no virtual icache, uncached coherency. */ 83 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), 84 .CP0_Config1 = MIPS_CONFIG1 | 85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 87 (1 << CP0C1_CA), 88 .CP0_Config2 = MIPS_CONFIG2, 89 .CP0_Config3 = MIPS_CONFIG3, 90 .CP0_LLAddr_rw_bitmask = 0, 91 .CP0_LLAddr_shift = 4, 92 .SYNCI_Step = 32, 93 .CCRes = 2, 94 .CP0_Status_rw_bitmask = 0x1258FF17, 95 .SEGBITS = 32, 96 .PABITS = 32, 97 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, 98 .mmu_type = MMU_TYPE_FMT, 99 }, 100 { 101 .name = "4KEcR1", 102 .CP0_PRid = 0x00018400, 103 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), 104 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 105 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 106 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 107 (0 << CP0C1_CA), 108 .CP0_Config2 = MIPS_CONFIG2, 109 .CP0_Config3 = MIPS_CONFIG3, 110 .CP0_LLAddr_rw_bitmask = 0, 111 .CP0_LLAddr_shift = 4, 112 .SYNCI_Step = 32, 113 .CCRes = 2, 114 .CP0_Status_rw_bitmask = 0x1278FF17, 115 .SEGBITS = 32, 116 .PABITS = 32, 117 .insn_flags = CPU_MIPS32R1, 118 .mmu_type = MMU_TYPE_R4000, 119 }, 120 { 121 .name = "4KEmR1", 122 .CP0_PRid = 0x00018500, 123 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), 124 .CP0_Config1 = MIPS_CONFIG1 | 125 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 126 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 127 (1 << CP0C1_CA), 128 .CP0_Config2 = MIPS_CONFIG2, 129 .CP0_Config3 = MIPS_CONFIG3, 130 .CP0_LLAddr_rw_bitmask = 0, 131 .CP0_LLAddr_shift = 4, 132 .SYNCI_Step = 32, 133 .CCRes = 2, 134 .CP0_Status_rw_bitmask = 0x1258FF17, 135 .SEGBITS = 32, 136 .PABITS = 32, 137 .insn_flags = CPU_MIPS32R1 | ASE_MIPS16, 138 .mmu_type = MMU_TYPE_FMT, 139 }, 140 { 141 .name = "4KEc", 142 .CP0_PRid = 0x00019000, 143 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 144 (MMU_TYPE_R4000 << CP0C0_MT), 145 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 146 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 147 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 148 (0 << CP0C1_CA), 149 .CP0_Config2 = MIPS_CONFIG2, 150 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 151 .CP0_LLAddr_rw_bitmask = 0, 152 .CP0_LLAddr_shift = 4, 153 .SYNCI_Step = 32, 154 .CCRes = 2, 155 .CP0_Status_rw_bitmask = 0x1278FF17, 156 .SEGBITS = 32, 157 .PABITS = 32, 158 .insn_flags = CPU_MIPS32R2, 159 .mmu_type = MMU_TYPE_R4000, 160 }, 161 { 162 .name = "4KEm", 163 .CP0_PRid = 0x00019100, 164 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 165 (MMU_TYPE_FMT << CP0C0_MT), 166 .CP0_Config1 = MIPS_CONFIG1 | 167 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 168 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 169 (1 << CP0C1_CA), 170 .CP0_Config2 = MIPS_CONFIG2, 171 .CP0_Config3 = MIPS_CONFIG3, 172 .CP0_LLAddr_rw_bitmask = 0, 173 .CP0_LLAddr_shift = 4, 174 .SYNCI_Step = 32, 175 .CCRes = 2, 176 .CP0_Status_rw_bitmask = 0x1258FF17, 177 .SEGBITS = 32, 178 .PABITS = 32, 179 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 180 .mmu_type = MMU_TYPE_FMT, 181 }, 182 { 183 .name = "24Kc", 184 .CP0_PRid = 0x00019300, 185 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 186 (MMU_TYPE_R4000 << CP0C0_MT), 187 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 188 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 189 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 190 (1 << CP0C1_CA), 191 .CP0_Config2 = MIPS_CONFIG2, 192 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 193 .CP0_LLAddr_rw_bitmask = 0, 194 .CP0_LLAddr_shift = 4, 195 .SYNCI_Step = 32, 196 .CCRes = 2, 197 /* No DSP implemented. */ 198 .CP0_Status_rw_bitmask = 0x1278FF1F, 199 .SEGBITS = 32, 200 .PABITS = 32, 201 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 202 .mmu_type = MMU_TYPE_R4000, 203 }, 204 { 205 .name = "24KEc", 206 .CP0_PRid = 0x00019600, 207 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 208 (MMU_TYPE_R4000 << CP0C0_MT), 209 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 210 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 211 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 212 (1 << CP0C1_CA), 213 .CP0_Config2 = MIPS_CONFIG2, 214 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), 215 .CP0_LLAddr_rw_bitmask = 0, 216 .CP0_LLAddr_shift = 4, 217 .SYNCI_Step = 32, 218 .CCRes = 2, 219 /* we have a DSP, but no FPU */ 220 .CP0_Status_rw_bitmask = 0x1378FF1F, 221 .SEGBITS = 32, 222 .PABITS = 32, 223 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, 224 .mmu_type = MMU_TYPE_R4000, 225 }, 226 { 227 .name = "24Kf", 228 .CP0_PRid = 0x00019300, 229 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 230 (MMU_TYPE_R4000 << CP0C0_MT), 231 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 232 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 233 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 234 (1 << CP0C1_CA), 235 .CP0_Config2 = MIPS_CONFIG2, 236 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), 237 .CP0_LLAddr_rw_bitmask = 0, 238 .CP0_LLAddr_shift = 4, 239 .SYNCI_Step = 32, 240 .CCRes = 2, 241 /* No DSP implemented. */ 242 .CP0_Status_rw_bitmask = 0x3678FF1F, 243 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 244 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), 245 .CP1_fcr31 = 0, 246 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 247 .SEGBITS = 32, 248 .PABITS = 32, 249 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, 250 .mmu_type = MMU_TYPE_R4000, 251 }, 252 { 253 .name = "34Kf", 254 .CP0_PRid = 0x00019500, 255 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 256 (MMU_TYPE_R4000 << CP0C0_MT), 257 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 258 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 259 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 260 (1 << CP0C1_CA), 261 .CP0_Config2 = MIPS_CONFIG2, 262 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | 263 (1 << CP0C3_DSPP), 264 .CP0_LLAddr_rw_bitmask = 0, 265 .CP0_LLAddr_shift = 0, 266 .SYNCI_Step = 32, 267 .CCRes = 2, 268 .CP0_Status_rw_bitmask = 0x3778FF1F, 269 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | 270 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | 271 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | 272 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | 273 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | 274 (0xff << CP0TCSt_TASID), 275 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 276 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), 277 .CP1_fcr31 = 0, 278 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 279 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), 280 .CP0_SRSConf0_rw_bitmask = 0x3fffffff, 281 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | 282 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), 283 .CP0_SRSConf1_rw_bitmask = 0x3fffffff, 284 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | 285 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), 286 .CP0_SRSConf2_rw_bitmask = 0x3fffffff, 287 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | 288 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), 289 .CP0_SRSConf3_rw_bitmask = 0x3fffffff, 290 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | 291 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), 292 .CP0_SRSConf4_rw_bitmask = 0x3fffffff, 293 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | 294 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), 295 .SEGBITS = 32, 296 .PABITS = 32, 297 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, 298 .mmu_type = MMU_TYPE_R4000, 299 }, 300 { 301 .name = "74Kf", 302 .CP0_PRid = 0x00019700, 303 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 304 (MMU_TYPE_R4000 << CP0C0_MT), 305 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 306 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 307 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | 308 (1 << CP0C1_CA), 309 .CP0_Config2 = MIPS_CONFIG2, 310 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | 311 (1 << CP0C3_VInt), 312 .CP0_LLAddr_rw_bitmask = 0, 313 .CP0_LLAddr_shift = 4, 314 .SYNCI_Step = 32, 315 .CCRes = 2, 316 .CP0_Status_rw_bitmask = 0x3778FF1F, 317 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 318 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), 319 .CP1_fcr31 = 0, 320 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 321 .SEGBITS = 32, 322 .PABITS = 32, 323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, 324 .mmu_type = MMU_TYPE_R4000, 325 }, 326 { 327 .name = "M14K", 328 .CP0_PRid = 0x00019b00, 329 /* Config1 implemented, fixed mapping MMU, 330 no virtual icache, uncached coherency. */ 331 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | 332 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), 333 .CP0_Config1 = MIPS_CONFIG1, 334 .CP0_Config2 = MIPS_CONFIG2, 335 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), 336 .CP0_LLAddr_rw_bitmask = 0, 337 .CP0_LLAddr_shift = 4, 338 .SYNCI_Step = 32, 339 .CCRes = 2, 340 .CP0_Status_rw_bitmask = 0x1258FF17, 341 .SEGBITS = 32, 342 .PABITS = 32, 343 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, 344 .mmu_type = MMU_TYPE_FMT, 345 }, 346 { 347 .name = "M14Kc", 348 /* This is the TLB-based MMU core. */ 349 .CP0_PRid = 0x00019c00, 350 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | 351 (MMU_TYPE_R4000 << CP0C0_MT), 352 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | 353 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | 354 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), 355 .CP0_Config2 = MIPS_CONFIG2, 356 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), 357 .CP0_LLAddr_rw_bitmask = 0, 358 .CP0_LLAddr_shift = 4, 359 .SYNCI_Step = 32, 360 .CCRes = 2, 361 .CP0_Status_rw_bitmask = 0x1278FF17, 362 .SEGBITS = 32, 363 .PABITS = 32, 364 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, 365 .mmu_type = MMU_TYPE_R4000, 366 }, 367 { 368 /* FIXME: 369 * Config3: VZ, CTXTC, CDMM, TL 370 * Config4: MMUExtDef 371 * Config5: MRP 372 * */ 373 .name = "P5600", 374 .CP0_PRid = 0x0001A800, 375 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | 376 (MMU_TYPE_R4000 << CP0C0_MT), 377 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | 378 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 379 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 380 (1 << CP0C1_PC) | (1 << CP0C1_FP), 381 .CP0_Config2 = MIPS_CONFIG2, 382 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | 383 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | 384 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | 385 (1 << CP0C3_PW) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | 386 (1 << CP0C3_LPA) | (1 << CP0C3_VInt), 387 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | 388 (0x1c << CP0C4_KScrExist), 389 .CP0_Config4_rw_bitmask = 0, 390 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) | 391 (1 << CP0C5_LLB) | (1 << CP0C5_MRP), 392 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | 393 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | 394 (1 << CP0C5_FRE) | (1 << CP0C5_UFR), 395 .CP0_LLAddr_rw_bitmask = 0, 396 .CP0_LLAddr_shift = 0, 397 .SYNCI_Step = 32, 398 .CCRes = 2, 399 .CP0_Status_rw_bitmask = 0x3C68FF1F, 400 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | 401 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), 402 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), 403 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | 404 (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 405 (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), 406 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), 407 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 408 .SEGBITS = 32, 409 .PABITS = 40, 410 .insn_flags = CPU_MIPS32R5, 411 .mmu_type = MMU_TYPE_R4000, 412 }, 413 { 414 /* A generic CPU supporting MIPS32 Release 6 ISA. 415 FIXME: Support IEEE 754-2008 FP. 416 Eventually this should be replaced by a real CPU model. */ 417 .name = "mips32r6-generic", 418 .CP0_PRid = 0x00010000, 419 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | 420 (MMU_TYPE_R4000 << CP0C0_MT), 421 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | 422 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 423 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 424 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 425 .CP0_Config2 = MIPS_CONFIG2, 426 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | 427 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | 428 (1 << CP0C3_RXI) | (1U << CP0C3_M), 429 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | 430 (3 << CP0C4_IE) | (1U << CP0C4_M), 431 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), 432 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | 433 (1 << CP0C5_UFE), 434 .CP0_LLAddr_rw_bitmask = 0, 435 .CP0_LLAddr_shift = 0, 436 .SYNCI_Step = 32, 437 .CCRes = 2, 438 .CP0_Status_rw_bitmask = 0x3058FF1F, 439 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | 440 (1U << CP0PG_RIE), 441 .CP0_PageGrain_rw_bitmask = 0, 442 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | 443 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 444 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), 445 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), 446 .CP1_fcr31_rw_bitmask = 0x0103FFFF, 447 .SEGBITS = 32, 448 .PABITS = 32, 449 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, 450 .mmu_type = MMU_TYPE_R4000, 451 }, 452 { 453 .name = "I7200", 454 .CP0_PRid = 0x00010000, 455 .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | 456 (MMU_TYPE_R4000 << CP0C0_MT), 457 .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | 458 (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | 459 (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | 460 (1 << CP0C1_EP), 461 .CP0_Config2 = MIPS_CONFIG2, 462 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | 463 (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | 464 (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | 465 (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | 466 (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | 467 (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | 468 (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), 469 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | 470 (2 << CP0C4_IE) | (1U << CP0C4_M), 471 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), 472 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | 473 (1 << CP0C5_UFE), 474 .CP0_LLAddr_rw_bitmask = 0, 475 .CP0_LLAddr_shift = 0, 476 .SYNCI_Step = 32, 477 .CCRes = 2, 478 .CP0_Status_rw_bitmask = 0x3158FF1F, 479 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | 480 (1U << CP0PG_RIE), 481 .CP0_PageGrain_rw_bitmask = 0, 482 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | 483 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 484 (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), 485 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), 486 .SEGBITS = 32, 487 .PABITS = 32, 488 .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 | 489 ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT, 490 .mmu_type = MMU_TYPE_R4000, 491 }, 492 #if defined(TARGET_MIPS64) 493 { 494 .name = "R4000", 495 .CP0_PRid = 0x00000400, 496 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ 497 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) | 498 (2 << CP0C0_K0), 499 /* Note: Config1 is only used internally, the R4000 has only Config0. */ 500 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 501 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, 502 .CP0_LLAddr_shift = 4, 503 .SYNCI_Step = 16, 504 .CCRes = 2, 505 .CP0_Status_rw_bitmask = 0x3678FFFF, 506 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ 507 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), 508 .CP1_fcr31 = 0, 509 .CP1_fcr31_rw_bitmask = 0x0183FFFF, 510 .SEGBITS = 40, 511 .PABITS = 36, 512 .insn_flags = CPU_MIPS3, 513 .mmu_type = MMU_TYPE_R4000, 514 }, 515 { 516 .name = "VR5432", 517 .CP0_PRid = 0x00005400, 518 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ 519 .CP0_Config0 = (2 << CP0C0_Impl) | (1 << CP0C0_IC) | (1 << CP0C0_DC) | 520 (2 << CP0C0_K0), 521 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 522 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, 523 .CP0_LLAddr_shift = 4, 524 .SYNCI_Step = 16, 525 .CCRes = 2, 526 .CP0_Status_rw_bitmask = 0x3678FFFF, 527 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ 528 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), 529 .CP1_fcr31 = 0, 530 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 531 .SEGBITS = 40, 532 .PABITS = 32, 533 .insn_flags = CPU_MIPS4 | INSN_VR54XX, 534 .mmu_type = MMU_TYPE_R4000, 535 }, 536 { 537 .name = "5Kc", 538 .CP0_PRid = 0x00018100, 539 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 540 (MMU_TYPE_R4000 << CP0C0_MT), 541 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | 542 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 543 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 544 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 545 .CP0_Config2 = MIPS_CONFIG2, 546 .CP0_Config3 = MIPS_CONFIG3, 547 .CP0_LLAddr_rw_bitmask = 0, 548 .CP0_LLAddr_shift = 4, 549 .SYNCI_Step = 32, 550 .CCRes = 2, 551 .CP0_Status_rw_bitmask = 0x12F8FFFF, 552 .SEGBITS = 42, 553 .PABITS = 36, 554 .insn_flags = CPU_MIPS64R1, 555 .mmu_type = MMU_TYPE_R4000, 556 }, 557 { 558 .name = "5Kf", 559 .CP0_PRid = 0x00018100, 560 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 561 (MMU_TYPE_R4000 << CP0C0_MT), 562 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | 563 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 564 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 565 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 566 .CP0_Config2 = MIPS_CONFIG2, 567 .CP0_Config3 = MIPS_CONFIG3, 568 .CP0_LLAddr_rw_bitmask = 0, 569 .CP0_LLAddr_shift = 4, 570 .SYNCI_Step = 32, 571 .CCRes = 2, 572 .CP0_Status_rw_bitmask = 0x36F8FFFF, 573 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ 574 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | 575 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), 576 .CP1_fcr31 = 0, 577 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 578 .SEGBITS = 42, 579 .PABITS = 36, 580 .insn_flags = CPU_MIPS64R1, 581 .mmu_type = MMU_TYPE_R4000, 582 }, 583 { 584 .name = "20Kc", 585 /* We emulate a later version of the 20Kc, earlier ones had a broken 586 WAIT instruction. */ 587 .CP0_PRid = 0x000182a0, 588 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | 589 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), 590 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | 591 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 592 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 593 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 594 .CP0_Config2 = MIPS_CONFIG2, 595 .CP0_Config3 = MIPS_CONFIG3, 596 .CP0_LLAddr_rw_bitmask = 0, 597 .CP0_LLAddr_shift = 0, 598 .SYNCI_Step = 32, 599 .CCRes = 1, 600 .CP0_Status_rw_bitmask = 0x36FBFFFF, 601 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ 602 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | 603 (1 << FCR0_D) | (1 << FCR0_S) | 604 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), 605 .CP1_fcr31 = 0, 606 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 607 .SEGBITS = 40, 608 .PABITS = 36, 609 .insn_flags = CPU_MIPS64R1 | ASE_MIPS3D, 610 .mmu_type = MMU_TYPE_R4000, 611 }, 612 { 613 /* A generic CPU providing MIPS64 Release 2 features. 614 FIXME: Eventually this should be replaced by a real CPU model. */ 615 .name = "MIPS64R2-generic", 616 .CP0_PRid = 0x00010000, 617 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 618 (MMU_TYPE_R4000 << CP0C0_MT), 619 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 620 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 621 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 622 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 623 .CP0_Config2 = MIPS_CONFIG2, 624 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), 625 .CP0_LLAddr_rw_bitmask = 0, 626 .CP0_LLAddr_shift = 0, 627 .SYNCI_Step = 32, 628 .CCRes = 2, 629 .CP0_Status_rw_bitmask = 0x36FBFFFF, 630 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), 631 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | 632 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 633 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), 634 .CP1_fcr31 = 0, 635 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 636 .SEGBITS = 42, 637 .PABITS = 36, 638 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, 639 .mmu_type = MMU_TYPE_R4000, 640 }, 641 { 642 .name = "5KEc", 643 .CP0_PRid = 0x00018900, 644 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 645 (MMU_TYPE_R4000 << CP0C0_MT), 646 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | 647 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 648 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 649 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 650 .CP0_Config2 = MIPS_CONFIG2, 651 .CP0_Config3 = MIPS_CONFIG3, 652 .CP0_LLAddr_rw_bitmask = 0, 653 .CP0_LLAddr_shift = 4, 654 .SYNCI_Step = 32, 655 .CCRes = 2, 656 .CP0_Status_rw_bitmask = 0x12F8FFFF, 657 .SEGBITS = 42, 658 .PABITS = 36, 659 .insn_flags = CPU_MIPS64R2, 660 .mmu_type = MMU_TYPE_R4000, 661 }, 662 { 663 .name = "5KEf", 664 .CP0_PRid = 0x00018900, 665 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 666 (MMU_TYPE_R4000 << CP0C0_MT), 667 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | 668 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 669 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 670 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 671 .CP0_Config2 = MIPS_CONFIG2, 672 .CP0_Config3 = MIPS_CONFIG3, 673 .CP0_LLAddr_rw_bitmask = 0, 674 .CP0_LLAddr_shift = 4, 675 .SYNCI_Step = 32, 676 .CCRes = 2, 677 .CP0_Status_rw_bitmask = 0x36F8FFFF, 678 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | 679 (1 << FCR0_D) | (1 << FCR0_S) | 680 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), 681 .SEGBITS = 42, 682 .PABITS = 36, 683 .insn_flags = CPU_MIPS64R2, 684 .mmu_type = MMU_TYPE_R4000, 685 }, 686 { 687 .name = "I6400", 688 .CP0_PRid = 0x1A900, 689 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | 690 (MMU_TYPE_R4000 << CP0C0_MT), 691 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 692 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | 693 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | 694 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 695 .CP0_Config2 = MIPS_CONFIG2, 696 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | 697 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | 698 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | 699 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), 700 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | 701 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), 702 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | 703 (1 << CP0C5_LLB) | (1 << CP0C5_MRP), 704 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | 705 (1 << CP0C5_FRE) | (1 << CP0C5_UFE), 706 .CP0_LLAddr_rw_bitmask = 0, 707 .CP0_LLAddr_shift = 0, 708 .SYNCI_Step = 32, 709 .CCRes = 2, 710 .CP0_Status_rw_bitmask = 0x30D8FFFF, 711 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | 712 (1U << CP0PG_RIE), 713 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), 714 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), 715 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | 716 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 717 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), 718 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), 719 .CP1_fcr31_rw_bitmask = 0x0103FFFF, 720 .MSAIR = 0x03 << MSAIR_ProcID, 721 .SEGBITS = 48, 722 .PABITS = 48, 723 .insn_flags = CPU_MIPS64R6, 724 .mmu_type = MMU_TYPE_R4000, 725 }, 726 { 727 .name = "I6500", 728 .CP0_PRid = 0x1B000, 729 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | 730 (MMU_TYPE_R4000 << CP0C0_MT), 731 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | 732 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | 733 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | 734 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 735 .CP0_Config2 = MIPS_CONFIG2, 736 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | 737 (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | 738 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | 739 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), 740 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | 741 (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), 742 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | 743 (1 << CP0C5_LLB) | (1 << CP0C5_MRP), 744 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | 745 (1 << CP0C5_FRE) | (1 << CP0C5_UFE), 746 .CP0_LLAddr_rw_bitmask = 0, 747 .CP0_LLAddr_shift = 0, 748 .SYNCI_Step = 64, 749 .CCRes = 2, 750 .CP0_Status_rw_bitmask = 0x30D8FFFF, 751 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | 752 (1U << CP0PG_RIE), 753 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), 754 .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), 755 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | 756 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 757 (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), 758 .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), 759 .CP1_fcr31_rw_bitmask = 0x0103FFFF, 760 .MSAIR = 0x03 << MSAIR_ProcID, 761 .SEGBITS = 48, 762 .PABITS = 48, 763 .insn_flags = CPU_MIPS64R6, 764 .mmu_type = MMU_TYPE_R4000, 765 }, 766 { 767 .name = "Loongson-2E", 768 .CP0_PRid = 0x6302, 769 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ 770 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) | 771 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0), 772 /* Note: Config1 is only used internally, 773 Loongson-2E has only Config0. */ 774 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 775 .SYNCI_Step = 16, 776 .CCRes = 2, 777 .CP0_Status_rw_bitmask = 0x35D0FFFF, 778 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), 779 .CP1_fcr31 = 0, 780 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 781 .SEGBITS = 40, 782 .PABITS = 40, 783 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2E, 784 .mmu_type = MMU_TYPE_R4000, 785 }, 786 { 787 .name = "Loongson-2F", 788 .CP0_PRid = 0x6303, 789 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ 790 .CP0_Config0 = (3 << CP0C0_Impl) | (4 << CP0C0_IC) | (4 << CP0C0_DC) | 791 (1 << CP0C0_IB) | (1 << CP0C0_DB) | (0x2 << CP0C0_K0), 792 /* Note: Config1 is only used internally, 793 Loongson-2F has only Config0. */ 794 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), 795 .SYNCI_Step = 16, 796 .CCRes = 2, 797 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ 798 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), 799 .CP1_fcr31 = 0, 800 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 801 .SEGBITS = 40, 802 .PABITS = 40, 803 .insn_flags = CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI, 804 .mmu_type = MMU_TYPE_R4000, 805 }, 806 { 807 .name = "Loongson-3A1000", /* Loongson-3A R1, GS464-based */ 808 .CP0_PRid = 0x6305, 809 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ 810 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 811 (MMU_TYPE_R4000 << CP0C0_MT), 812 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 813 (3 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 814 (3 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 815 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 816 .CP0_Config2 = MIPS_CONFIG2 | (7 << CP0C2_SS) | (4 << CP0C2_SL) | 817 (3 << CP0C2_SA), 818 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), 819 .CP0_LLAddr_rw_bitmask = 0, 820 .SYNCI_Step = 32, 821 .CCRes = 2, 822 .CP0_Status_rw_bitmask = 0x74D8FFFF, 823 .CP0_PageGrain = (1 << CP0PG_ELPA), 824 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), 825 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | 826 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | 827 (0x1 << FCR0_D) | (0x1 << FCR0_S), 828 .CP1_fcr31 = 0, 829 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 830 .SEGBITS = 48, 831 .PABITS = 48, 832 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 833 ASE_LMMI | ASE_LEXT, 834 .mmu_type = MMU_TYPE_R4000, 835 }, 836 { 837 .name = "Loongson-3A4000", /* Loongson-3A R4, GS464V-based */ 838 .CP0_PRid = 0x14C000, 839 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ 840 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 841 (MMU_TYPE_R4000 << CP0C0_MT), 842 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 843 (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | 844 (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | 845 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 846 .CP0_Config2 = MIPS_CONFIG2 | (5 << CP0C2_SS) | (5 << CP0C2_SL) | 847 (15 << CP0C2_SA), 848 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | 849 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | 850 (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), 851 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | 852 (1 << CP0C4_AE) | (0x1c << CP0C4_KScrExist), 853 .CP0_Config4_rw_bitmask = 0, 854 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_CRCP) | (1 << CP0C5_NFExists), 855 .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | 856 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | 857 (1 << CP0C5_FRE) | (1 << CP0C5_SBRI), 858 .CP0_Config6 = (1 << CP0C6_VCLRU) | (1 << CP0C6_DCLRU) | 859 (1 << CP0C6_SFBEN) | (1 << CP0C6_VLTINT) | 860 (1 << CP0C6_INSTPREF) | (1 << CP0C6_DATAPREF), 861 .CP0_Config6_rw_bitmask = (1 << CP0C6_BPPASS) | (0x3f << CP0C6_KPOS) | 862 (1 << CP0C6_KE) | (1 << CP0C6_VTLBONLY) | 863 (1 << CP0C6_LASX) | (1 << CP0C6_SSEN) | 864 (1 << CP0C6_DISDRTIME) | (1 << CP0C6_PIXNUEN) | 865 (1 << CP0C6_SCRAND) | (1 << CP0C6_LLEXCEN) | 866 (1 << CP0C6_DISVC) | (1 << CP0C6_VCLRU) | 867 (1 << CP0C6_DCLRU) | (1 << CP0C6_PIXUEN) | 868 (1 << CP0C6_DISBLKLYEN) | (1 << CP0C6_UMEMUALEN) | 869 (1 << CP0C6_SFBEN) | (1 << CP0C6_FLTINT) | 870 (1 << CP0C6_VLTINT) | (1 << CP0C6_DISBTB) | 871 (3 << CP0C6_STPREFCTL) | (1 << CP0C6_INSTPREF) | 872 (1 << CP0C6_DATAPREF), 873 .CP0_Config7 = 0, 874 .CP0_Config7_rw_bitmask = (1 << CP0C7_NAPCGEN) | (1 << CP0C7_UNIMUEN) | 875 (1 << CP0C7_VFPUCGEN), 876 .CP0_LLAddr_rw_bitmask = 1, 877 .SYNCI_Step = 16, 878 .CCRes = 2, 879 .CP0_Status_rw_bitmask = 0x7DDBFFFF, 880 .CP0_PageGrain = (1 << CP0PG_ELPA), 881 .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | 882 (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), 883 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV) | (0x1 << FCR0_F64) | 884 (0x1 << FCR0_PS) | (0x1 << FCR0_L) | (0x1 << FCR0_W) | 885 (0x1 << FCR0_D) | (0x1 << FCR0_S), 886 .CP1_fcr31 = 0, 887 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 888 .MSAIR = (0x01 << MSAIR_ProcID) | (0x40 << MSAIR_Rev), 889 .SEGBITS = 48, 890 .PABITS = 48, 891 .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | 892 ASE_LMMI | ASE_LEXT, 893 .mmu_type = MMU_TYPE_R4000, 894 }, 895 { 896 /* A generic CPU providing MIPS64 DSP R2 ASE features. 897 FIXME: Eventually this should be replaced by a real CPU model. */ 898 .name = "mips64dspr2", 899 .CP0_PRid = 0x00010000, 900 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 901 (MMU_TYPE_R4000 << CP0C0_MT), 902 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | 903 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | 904 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | 905 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 906 .CP0_Config2 = MIPS_CONFIG2, 907 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | 908 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), 909 .CP0_LLAddr_rw_bitmask = 0, 910 .CP0_LLAddr_shift = 0, 911 .SYNCI_Step = 32, 912 .CCRes = 2, 913 .CP0_Status_rw_bitmask = 0x37FBFFFF, 914 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | 915 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | 916 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), 917 .CP1_fcr31 = 0, 918 .CP1_fcr31_rw_bitmask = 0xFF83FFFF, 919 .SEGBITS = 42, 920 .PABITS = 36, 921 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, 922 .mmu_type = MMU_TYPE_R4000, 923 }, 924 { 925 /* 926 * Octeon 68xx with MIPS64 Cavium Octeon features. 927 */ 928 .name = "Octeon68XX", 929 .CP0_PRid = 0x000D9100, 930 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | 931 (MMU_TYPE_R4000 << CP0C0_MT), 932 .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | 933 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | 934 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | 935 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), 936 .CP0_Config2 = MIPS_CONFIG2, 937 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), 938 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | 939 (0x3c << CP0C4_KScrExist) | (1U << CP0C4_MMUExtDef) | 940 (3U << CP0C4_MMUSizeExt), 941 .CP0_LLAddr_rw_bitmask = 0, 942 .CP0_LLAddr_shift = 4, 943 .CP0_PageGrain = (1 << CP0PG_ELPA), 944 .SYNCI_Step = 32, 945 .CCRes = 2, 946 .CP0_Status_rw_bitmask = 0x12F8FFFF, 947 .SEGBITS = 42, 948 .PABITS = 49, 949 .insn_flags = CPU_MIPS64R2 | INSN_OCTEON, 950 .mmu_type = MMU_TYPE_R4000, 951 }, 952 953 #endif 954 }; 955 const int mips_defs_number = ARRAY_SIZE(mips_defs); 956 957 void mips_cpu_list(void) 958 { 959 int i; 960 961 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { 962 qemu_printf("MIPS '%s'\n", mips_defs[i].name); 963 } 964 } 965 966 static void fpu_init (CPUMIPSState *env, const mips_def_t *def) 967 { 968 int i; 969 970 for (i = 0; i < MIPS_FPU_MAX; i++) 971 env->fpus[i].fcr0 = def->CP1_fcr0; 972 973 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); 974 } 975 976 static void mvp_init(CPUMIPSState *env) 977 { 978 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); 979 980 if (!ase_mt_available(env)) { 981 return; 982 } 983 984 /* MVPConf1 implemented, TLB sharable, no gating storage support, 985 programmable cache partitioning implemented, number of allocatable 986 and shareable TLB entries, MVP has allocatable TCs, 2 VPEs 987 implemented, 5 TCs implemented. */ 988 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | 989 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | 990 // TODO: actually do 2 VPEs. 991 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | 992 // (0x04 << CP0MVPC0_PTC); 993 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | 994 (0x00 << CP0MVPC0_PTC); 995 #if !defined(CONFIG_USER_ONLY) 996 /* Usermode has no TLB support */ 997 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); 998 #endif 999 1000 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, 1001 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ 1002 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | 1003 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | 1004 (0x1 << CP0MVPC1_PCP1); 1005 }