qemu

FORK: QEMU emulator
git clone https://git.neptards.moe/neptards/qemu.git
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gdbstub.c (3496B)

      1 /*
      2  * MicroBlaze gdb server stub
      3  *
      4  * Copyright (c) 2003-2005 Fabrice Bellard
      5  * Copyright (c) 2013 SUSE LINUX Products GmbH
      6  *
      7  * This library is free software; you can redistribute it and/or
      8  * modify it under the terms of the GNU Lesser General Public
      9  * License as published by the Free Software Foundation; either
     10  * version 2.1 of the License, or (at your option) any later version.
     11  *
     12  * This library is distributed in the hope that it will be useful,
     13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     15  * Lesser General Public License for more details.
     16  *
     17  * You should have received a copy of the GNU Lesser General Public
     18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     19  */
     20 #include "qemu/osdep.h"
     21 #include "cpu.h"
     22 #include "exec/gdbstub.h"
     23 
     24 /*
     25  * GDB expects SREGs in the following order:
     26  * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
     27  *
     28  * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
     29  * map them to anything and return a value of 0 instead.
     30  */
     31 
     32 enum {
     33     GDB_PC    = 32 + 0,
     34     GDB_MSR   = 32 + 1,
     35     GDB_EAR   = 32 + 2,
     36     GDB_ESR   = 32 + 3,
     37     GDB_FSR   = 32 + 4,
     38     GDB_BTR   = 32 + 5,
     39     GDB_PVR0  = 32 + 6,
     40     GDB_PVR11 = 32 + 17,
     41     GDB_EDR   = 32 + 18,
     42     GDB_SLR   = 32 + 25,
     43     GDB_SHR   = 32 + 26,
     44 };
     45 
     46 int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
     47 {
     48     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
     49     CPUClass *cc = CPU_GET_CLASS(cs);
     50     CPUMBState *env = &cpu->env;
     51     uint32_t val;
     52 
     53     if (n > cc->gdb_num_core_regs) {
     54         return 0;
     55     }
     56 
     57     switch (n) {
     58     case 1 ... 31:
     59         val = env->regs[n];
     60         break;
     61     case GDB_PC:
     62         val = env->pc;
     63         break;
     64     case GDB_MSR:
     65         val = mb_cpu_read_msr(env);
     66         break;
     67     case GDB_EAR:
     68         val = env->ear;
     69         break;
     70     case GDB_ESR:
     71         val = env->esr;
     72         break;
     73     case GDB_FSR:
     74         val = env->fsr;
     75         break;
     76     case GDB_BTR:
     77         val = env->btr;
     78         break;
     79     case GDB_PVR0 ... GDB_PVR11:
     80         /* PVR12 is intentionally skipped */
     81         val = cpu->cfg.pvr_regs[n - GDB_PVR0];
     82         break;
     83     case GDB_EDR:
     84         val = env->edr;
     85         break;
     86     case GDB_SLR:
     87         val = env->slr;
     88         break;
     89     case GDB_SHR:
     90         val = env->shr;
     91         break;
     92     default:
     93         /* Other SRegs aren't modeled, so report a value of 0 */
     94         val = 0;
     95         break;
     96     }
     97     return gdb_get_reg32(mem_buf, val);
     98 }
     99 
    100 int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
    101 {
    102     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
    103     CPUClass *cc = CPU_GET_CLASS(cs);
    104     CPUMBState *env = &cpu->env;
    105     uint32_t tmp;
    106 
    107     if (n > cc->gdb_num_core_regs) {
    108         return 0;
    109     }
    110 
    111     tmp = ldl_p(mem_buf);
    112 
    113     switch (n) {
    114     case 1 ... 31:
    115         env->regs[n] = tmp;
    116         break;
    117     case GDB_PC:
    118         env->pc = tmp;
    119         break;
    120     case GDB_MSR:
    121         mb_cpu_write_msr(env, tmp);
    122         break;
    123     case GDB_EAR:
    124         env->ear = tmp;
    125         break;
    126     case GDB_ESR:
    127         env->esr = tmp;
    128         break;
    129     case GDB_FSR:
    130         env->fsr = tmp;
    131         break;
    132     case GDB_BTR:
    133         env->btr = tmp;
    134         break;
    135     case GDB_EDR:
    136         env->edr = tmp;
    137         break;
    138     case GDB_SLR:
    139         env->slr = tmp;
    140         break;
    141     case GDB_SHR:
    142         env->shr = tmp;
    143         break;
    144     }
    145     return 4;
    146 }