cpu.c (14245B)
1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "qemu/module.h" 29 #include "hw/qdev-properties.h" 30 #include "exec/exec-all.h" 31 #include "fpu/softfloat-helpers.h" 32 33 static const struct { 34 const char *name; 35 uint8_t version_id; 36 } mb_cpu_lookup[] = { 37 /* These key value are as per MBV field in PVR0 */ 38 {"5.00.a", 0x01}, 39 {"5.00.b", 0x02}, 40 {"5.00.c", 0x03}, 41 {"6.00.a", 0x04}, 42 {"6.00.b", 0x06}, 43 {"7.00.a", 0x05}, 44 {"7.00.b", 0x07}, 45 {"7.10.a", 0x08}, 46 {"7.10.b", 0x09}, 47 {"7.10.c", 0x0a}, 48 {"7.10.d", 0x0b}, 49 {"7.20.a", 0x0c}, 50 {"7.20.b", 0x0d}, 51 {"7.20.c", 0x0e}, 52 {"7.20.d", 0x0f}, 53 {"7.30.a", 0x10}, 54 {"7.30.b", 0x11}, 55 {"8.00.a", 0x12}, 56 {"8.00.b", 0x13}, 57 {"8.10.a", 0x14}, 58 {"8.20.a", 0x15}, 59 {"8.20.b", 0x16}, 60 {"8.30.a", 0x17}, 61 {"8.40.a", 0x18}, 62 {"8.40.b", 0x19}, 63 {"8.50.a", 0x1A}, 64 {"9.0", 0x1B}, 65 {"9.1", 0x1D}, 66 {"9.2", 0x1F}, 67 {"9.3", 0x20}, 68 {"9.4", 0x21}, 69 {"9.5", 0x22}, 70 {"9.6", 0x23}, 71 {"10.0", 0x24}, 72 {NULL, 0}, 73 }; 74 75 /* If no specific version gets selected, default to the following. */ 76 #define DEFAULT_CPU_VERSION "10.0" 77 78 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 79 { 80 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 81 82 cpu->env.pc = value; 83 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ 84 cpu->env.iflags = 0; 85 } 86 87 static vaddr mb_cpu_get_pc(CPUState *cs) 88 { 89 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 90 91 return cpu->env.pc; 92 } 93 94 static void mb_cpu_synchronize_from_tb(CPUState *cs, 95 const TranslationBlock *tb) 96 { 97 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 98 99 cpu->env.pc = tb_pc(tb); 100 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; 101 } 102 103 static void mb_restore_state_to_opc(CPUState *cs, 104 const TranslationBlock *tb, 105 const uint64_t *data) 106 { 107 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 108 109 cpu->env.pc = data[0]; 110 cpu->env.iflags = data[1]; 111 } 112 113 static bool mb_cpu_has_work(CPUState *cs) 114 { 115 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 116 } 117 118 #ifndef CONFIG_USER_ONLY 119 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) 120 { 121 MicroBlazeCPU *cpu = opaque; 122 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; 123 124 cpu->ns_axi_dp = level & en; 125 } 126 127 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) 128 { 129 MicroBlazeCPU *cpu = opaque; 130 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; 131 132 cpu->ns_axi_ip = level & en; 133 } 134 135 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) 136 { 137 MicroBlazeCPU *cpu = opaque; 138 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; 139 140 cpu->ns_axi_dc = level & en; 141 } 142 143 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) 144 { 145 MicroBlazeCPU *cpu = opaque; 146 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; 147 148 cpu->ns_axi_ic = level & en; 149 } 150 151 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 152 { 153 MicroBlazeCPU *cpu = opaque; 154 CPUState *cs = CPU(cpu); 155 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 156 157 if (level) { 158 cpu_interrupt(cs, type); 159 } else { 160 cpu_reset_interrupt(cs, type); 161 } 162 } 163 #endif 164 165 static void mb_cpu_reset(DeviceState *dev) 166 { 167 CPUState *s = CPU(dev); 168 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); 169 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); 170 CPUMBState *env = &cpu->env; 171 172 mcc->parent_reset(dev); 173 174 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 175 env->res_addr = RES_ADDR_NONE; 176 177 /* Disable stack protector. */ 178 env->shr = ~0; 179 180 env->pc = cpu->cfg.base_vectors; 181 182 #if defined(CONFIG_USER_ONLY) 183 /* start in user mode with interrupts enabled. */ 184 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); 185 #else 186 mb_cpu_write_msr(env, 0); 187 mmu_init(&env->mmu); 188 #endif 189 } 190 191 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 192 { 193 info->mach = bfd_arch_microblaze; 194 info->print_insn = print_insn_microblaze; 195 } 196 197 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 198 { 199 CPUState *cs = CPU(dev); 200 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 201 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 202 uint8_t version_code = 0; 203 const char *version; 204 int i = 0; 205 Error *local_err = NULL; 206 207 cpu_exec_realizefn(cs, &local_err); 208 if (local_err != NULL) { 209 error_propagate(errp, local_err); 210 return; 211 } 212 213 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { 214 error_setg(errp, "addr-size %d is out of range (32 - 64)", 215 cpu->cfg.addr_size); 216 return; 217 } 218 219 qemu_init_vcpu(cs); 220 221 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; 222 for (i = 0; mb_cpu_lookup[i].name && version; i++) { 223 if (strcmp(mb_cpu_lookup[i].name, version) == 0) { 224 version_code = mb_cpu_lookup[i].version_id; 225 break; 226 } 227 } 228 229 if (!version_code) { 230 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 231 } 232 233 cpu->cfg.pvr_regs[0] = 234 (PVR0_USE_EXC_MASK | 235 PVR0_USE_ICACHE_MASK | 236 PVR0_USE_DCACHE_MASK | 237 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 238 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 239 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 240 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 241 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 242 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 243 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 244 (version_code << PVR0_VERSION_SHIFT) | 245 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | 246 cpu->cfg.pvr_user1); 247 248 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; 249 250 cpu->cfg.pvr_regs[2] = 251 (PVR2_D_OPB_MASK | 252 PVR2_D_LMB_MASK | 253 PVR2_I_OPB_MASK | 254 PVR2_I_LMB_MASK | 255 PVR2_FPU_EXC_MASK | 256 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 257 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 258 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 259 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 260 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 261 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 262 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 263 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | 264 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | 265 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | 266 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | 267 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | 268 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | 269 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); 270 271 cpu->cfg.pvr_regs[5] |= 272 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; 273 274 cpu->cfg.pvr_regs[10] = 275 (0x0c000000 | /* Default to spartan 3a dsp family. */ 276 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); 277 278 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | 279 16 << 17); 280 281 cpu->cfg.mmu = 3; 282 cpu->cfg.mmu_tlb_access = 3; 283 cpu->cfg.mmu_zones = 16; 284 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); 285 286 mcc->parent_realize(dev, errp); 287 } 288 289 static void mb_cpu_initfn(Object *obj) 290 { 291 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 292 CPUMBState *env = &cpu->env; 293 294 cpu_set_cpustate_pointers(cpu); 295 296 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 297 298 #ifndef CONFIG_USER_ONLY 299 /* Inbound IRQ and FIR lines */ 300 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 301 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); 302 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); 303 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); 304 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); 305 #endif 306 } 307 308 static Property mb_properties[] = { 309 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 310 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 311 false), 312 /* 313 * This is the C_ADDR_SIZE synth-time configuration option of the 314 * MicroBlaze cores. Supported values range between 32 and 64. 315 * 316 * When set to > 32, 32bit MicroBlaze can emit load/stores 317 * with extended addressing. 318 */ 319 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32), 320 /* If use-fpu > 0 - FPU is enabled 321 * If use-fpu = 2 - Floating point conversion and square root instructions 322 * are enabled 323 */ 324 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 325 /* If use-hw-mul > 0 - Multiplier is enabled 326 * If use-hw-mul = 2 - 64-bit multiplier is enabled 327 */ 328 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 329 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 330 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 331 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 332 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 333 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 334 /* 335 * use-non-secure enables/disables the use of the non_secure[3:0] signals. 336 * It is a bitfield where 1 = non-secure for the following bits and their 337 * corresponding interfaces: 338 * 0x1 - M_AXI_DP 339 * 0x2 - M_AXI_IP 340 * 0x4 - M_AXI_DC 341 * 0x8 - M_AXI_IC 342 */ 343 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), 344 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 345 false), 346 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 347 /* Enables bus exceptions on failed data accesses (load/stores). */ 348 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, 349 cfg.dopb_bus_exception, false), 350 /* Enables bus exceptions on failed instruction fetches. */ 351 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, 352 cfg.iopb_bus_exception, false), 353 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, 354 cfg.illegal_opcode_exception, false), 355 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, 356 cfg.div_zero_exception, false), 357 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU, 358 cfg.unaligned_exceptions, false), 359 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, 360 cfg.opcode_0_illegal, false), 361 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 362 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 363 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), 364 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), 365 DEFINE_PROP_END_OF_LIST(), 366 }; 367 368 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 369 { 370 return object_class_by_name(TYPE_MICROBLAZE_CPU); 371 } 372 373 #ifndef CONFIG_USER_ONLY 374 #include "hw/core/sysemu-cpu-ops.h" 375 376 static const struct SysemuCPUOps mb_sysemu_ops = { 377 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug, 378 }; 379 #endif 380 381 #include "hw/core/tcg-cpu-ops.h" 382 383 static const struct TCGCPUOps mb_tcg_ops = { 384 .initialize = mb_tcg_init, 385 .synchronize_from_tb = mb_cpu_synchronize_from_tb, 386 .restore_state_to_opc = mb_restore_state_to_opc, 387 388 #ifndef CONFIG_USER_ONLY 389 .tlb_fill = mb_cpu_tlb_fill, 390 .cpu_exec_interrupt = mb_cpu_exec_interrupt, 391 .do_interrupt = mb_cpu_do_interrupt, 392 .do_transaction_failed = mb_cpu_transaction_failed, 393 .do_unaligned_access = mb_cpu_do_unaligned_access, 394 #endif /* !CONFIG_USER_ONLY */ 395 }; 396 397 static void mb_cpu_class_init(ObjectClass *oc, void *data) 398 { 399 DeviceClass *dc = DEVICE_CLASS(oc); 400 CPUClass *cc = CPU_CLASS(oc); 401 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 402 403 device_class_set_parent_realize(dc, mb_cpu_realizefn, 404 &mcc->parent_realize); 405 device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); 406 407 cc->class_by_name = mb_cpu_class_by_name; 408 cc->has_work = mb_cpu_has_work; 409 410 cc->dump_state = mb_cpu_dump_state; 411 cc->set_pc = mb_cpu_set_pc; 412 cc->get_pc = mb_cpu_get_pc; 413 cc->gdb_read_register = mb_cpu_gdb_read_register; 414 cc->gdb_write_register = mb_cpu_gdb_write_register; 415 416 #ifndef CONFIG_USER_ONLY 417 dc->vmsd = &vmstate_mb_cpu; 418 cc->sysemu_ops = &mb_sysemu_ops; 419 #endif 420 device_class_set_props(dc, mb_properties); 421 cc->gdb_num_core_regs = 32 + 27; 422 423 cc->disas_set_info = mb_disas_set_info; 424 cc->tcg_ops = &mb_tcg_ops; 425 } 426 427 static const TypeInfo mb_cpu_type_info = { 428 .name = TYPE_MICROBLAZE_CPU, 429 .parent = TYPE_CPU, 430 .instance_size = sizeof(MicroBlazeCPU), 431 .instance_init = mb_cpu_initfn, 432 .class_size = sizeof(MicroBlazeCPUClass), 433 .class_init = mb_cpu_class_init, 434 }; 435 436 static void mb_cpu_register_types(void) 437 { 438 type_register_static(&mb_cpu_type_info); 439 } 440 441 type_init(mb_cpu_register_types)