qemu

FORK: QEMU emulator
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trans_shift.c.inc (3060B)


      1 /* SPDX-License-Identifier: GPL-2.0-or-later */
      2 /*
      3  * Copyright (c) 2021 Loongson Technology Corporation Limited
      4  */
      5 
      6 static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
      7 {
      8     TCGv t0 = tcg_temp_new();
      9     tcg_gen_andi_tl(t0, src2, 0x1f);
     10     tcg_gen_shl_tl(dest, src1, t0);
     11     tcg_temp_free(t0);
     12 }
     13 
     14 static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
     15 {
     16     TCGv t0 = tcg_temp_new();
     17     tcg_gen_andi_tl(t0, src2, 0x1f);
     18     tcg_gen_shr_tl(dest, src1, t0);
     19     tcg_temp_free(t0);
     20 }
     21 
     22 static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
     23 {
     24     TCGv t0 = tcg_temp_new();
     25     tcg_gen_andi_tl(t0, src2, 0x1f);
     26     tcg_gen_sar_tl(dest, src1, t0);
     27     tcg_temp_free(t0);
     28 }
     29 
     30 static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
     31 {
     32     TCGv t0 = tcg_temp_new();
     33     tcg_gen_andi_tl(t0, src2, 0x3f);
     34     tcg_gen_shl_tl(dest, src1, t0);
     35     tcg_temp_free(t0);
     36 }
     37 
     38 static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
     39 {
     40     TCGv t0 = tcg_temp_new();
     41     tcg_gen_andi_tl(t0, src2, 0x3f);
     42     tcg_gen_shr_tl(dest, src1, t0);
     43     tcg_temp_free(t0);
     44 }
     45 
     46 static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
     47 {
     48     TCGv t0 = tcg_temp_new();
     49     tcg_gen_andi_tl(t0, src2, 0x3f);
     50     tcg_gen_sar_tl(dest, src1, t0);
     51     tcg_temp_free(t0);
     52 }
     53 
     54 static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
     55 {
     56     TCGv_i32 t1 = tcg_temp_new_i32();
     57     TCGv_i32 t2 = tcg_temp_new_i32();
     58     TCGv t0 = tcg_temp_new();
     59 
     60     tcg_gen_andi_tl(t0, src2, 0x1f);
     61 
     62     tcg_gen_trunc_tl_i32(t1, src1);
     63     tcg_gen_trunc_tl_i32(t2, t0);
     64 
     65     tcg_gen_rotr_i32(t1, t1, t2);
     66     tcg_gen_ext_i32_tl(dest, t1);
     67 
     68     tcg_temp_free_i32(t1);
     69     tcg_temp_free_i32(t2);
     70     tcg_temp_free(t0);
     71 }
     72 
     73 static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
     74 {
     75     TCGv t0 = tcg_temp_new();
     76     tcg_gen_andi_tl(t0, src2, 0x3f);
     77     tcg_gen_rotr_tl(dest, src1, t0);
     78     tcg_temp_free(t0);
     79 }
     80 
     81 static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
     82 {
     83     TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
     84     TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
     85 
     86     tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);
     87     gen_set_gpr(a->rd, dest, EXT_NONE);
     88 
     89     return true;
     90 }
     91 
     92 TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
     93 TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
     94 TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
     95 TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
     96 TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
     97 TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
     98 TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
     99 TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
    100 TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
    101 TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
    102 TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
    103 TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
    104 TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
    105 TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
    106 TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)