qemu

FORK: QEMU emulator
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trans_farith.c.inc (4112B)

      1 /* SPDX-License-Identifier: GPL-2.0-or-later */
      2 /*
      3  * Copyright (c) 2021 Loongson Technology Corporation Limited
      4  */
      5 
      6 #ifndef CONFIG_USER_ONLY
      7 #define CHECK_FPE do { \
      8     if ((ctx->base.tb->flags & HW_FLAGS_EUEN_FPE) == 0) { \
      9         generate_exception(ctx, EXCCODE_FPD); \
     10         return true; \
     11     } \
     12 } while (0)
     13 #else
     14 #define CHECK_FPE
     15 #endif
     16 
     17 static bool gen_fff(DisasContext *ctx, arg_fff *a,
     18                     void (*func)(TCGv, TCGv_env, TCGv, TCGv))
     19 {
     20     CHECK_FPE;
     21 
     22     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj], cpu_fpr[a->fk]);
     23     return true;
     24 }
     25 
     26 static bool gen_ff(DisasContext *ctx, arg_ff *a,
     27                    void (*func)(TCGv, TCGv_env, TCGv))
     28 {
     29     CHECK_FPE;
     30 
     31     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj]);
     32     return true;
     33 }
     34 
     35 static bool gen_muladd(DisasContext *ctx, arg_ffff *a,
     36                        void (*func)(TCGv, TCGv_env, TCGv, TCGv, TCGv, TCGv_i32),
     37                        int flag)
     38 {
     39     TCGv_i32 tflag = tcg_constant_i32(flag);
     40 
     41     CHECK_FPE;
     42 
     43     func(cpu_fpr[a->fd], cpu_env, cpu_fpr[a->fj],
     44          cpu_fpr[a->fk], cpu_fpr[a->fa], tflag);
     45     return true;
     46 }
     47 
     48 static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)
     49 {
     50     CHECK_FPE;
     51 
     52     tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 31);
     53     return true;
     54 }
     55 
     56 static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)
     57 {
     58     CHECK_FPE;
     59 
     60     tcg_gen_deposit_i64(cpu_fpr[a->fd], cpu_fpr[a->fk], cpu_fpr[a->fj], 0, 63);
     61     return true;
     62 }
     63 
     64 static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)
     65 {
     66     CHECK_FPE;
     67 
     68     tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 31));
     69     gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
     70     return true;
     71 }
     72 
     73 static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)
     74 {
     75     CHECK_FPE;
     76 
     77     tcg_gen_andi_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], MAKE_64BIT_MASK(0, 63));
     78     return true;
     79 }
     80 
     81 static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)
     82 {
     83     CHECK_FPE;
     84 
     85     tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x80000000);
     86     gen_nanbox_s(cpu_fpr[a->fd], cpu_fpr[a->fd]);
     87     return true;
     88 }
     89 
     90 static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)
     91 {
     92     CHECK_FPE;
     93 
     94     tcg_gen_xori_i64(cpu_fpr[a->fd], cpu_fpr[a->fj], 0x8000000000000000LL);
     95     return true;
     96 }
     97 
     98 TRANS(fadd_s, gen_fff, gen_helper_fadd_s)
     99 TRANS(fadd_d, gen_fff, gen_helper_fadd_d)
    100 TRANS(fsub_s, gen_fff, gen_helper_fsub_s)
    101 TRANS(fsub_d, gen_fff, gen_helper_fsub_d)
    102 TRANS(fmul_s, gen_fff, gen_helper_fmul_s)
    103 TRANS(fmul_d, gen_fff, gen_helper_fmul_d)
    104 TRANS(fdiv_s, gen_fff, gen_helper_fdiv_s)
    105 TRANS(fdiv_d, gen_fff, gen_helper_fdiv_d)
    106 TRANS(fmax_s, gen_fff, gen_helper_fmax_s)
    107 TRANS(fmax_d, gen_fff, gen_helper_fmax_d)
    108 TRANS(fmin_s, gen_fff, gen_helper_fmin_s)
    109 TRANS(fmin_d, gen_fff, gen_helper_fmin_d)
    110 TRANS(fmaxa_s, gen_fff, gen_helper_fmaxa_s)
    111 TRANS(fmaxa_d, gen_fff, gen_helper_fmaxa_d)
    112 TRANS(fmina_s, gen_fff, gen_helper_fmina_s)
    113 TRANS(fmina_d, gen_fff, gen_helper_fmina_d)
    114 TRANS(fscaleb_s, gen_fff, gen_helper_fscaleb_s)
    115 TRANS(fscaleb_d, gen_fff, gen_helper_fscaleb_d)
    116 TRANS(fsqrt_s, gen_ff, gen_helper_fsqrt_s)
    117 TRANS(fsqrt_d, gen_ff, gen_helper_fsqrt_d)
    118 TRANS(frecip_s, gen_ff, gen_helper_frecip_s)
    119 TRANS(frecip_d, gen_ff, gen_helper_frecip_d)
    120 TRANS(frsqrt_s, gen_ff, gen_helper_frsqrt_s)
    121 TRANS(frsqrt_d, gen_ff, gen_helper_frsqrt_d)
    122 TRANS(flogb_s, gen_ff, gen_helper_flogb_s)
    123 TRANS(flogb_d, gen_ff, gen_helper_flogb_d)
    124 TRANS(fclass_s, gen_ff, gen_helper_fclass_s)
    125 TRANS(fclass_d, gen_ff, gen_helper_fclass_d)
    126 TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0)
    127 TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0)
    128 TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)
    129 TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)
    130 TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)
    131 TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)
    132 TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s,
    133       float_muladd_negate_c | float_muladd_negate_result)
    134 TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d,
    135       float_muladd_negate_c | float_muladd_negate_result)