cpu.c (285441B)
1 /* 2 * i386 CPUID, CPU class, definitions, models 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/units.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/hw-version.h" 25 #include "cpu.h" 26 #include "tcg/helper-tcg.h" 27 #include "sysemu/reset.h" 28 #include "sysemu/hvf.h" 29 #include "kvm/kvm_i386.h" 30 #include "sev.h" 31 #include "qapi/error.h" 32 #include "qapi/qapi-visit-machine.h" 33 #include "qapi/qmp/qerror.h" 34 #include "qapi/qapi-commands-machine-target.h" 35 #include "standard-headers/asm-x86/kvm_para.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/i386/topology.h" 38 #ifndef CONFIG_USER_ONLY 39 #include "exec/address-spaces.h" 40 #include "hw/boards.h" 41 #include "hw/i386/sgx-epc.h" 42 #endif 43 44 #include "disas/capstone.h" 45 #include "cpu-internal.h" 46 47 /* Helpers for building CPUID[2] descriptors: */ 48 49 struct CPUID2CacheDescriptorInfo { 50 enum CacheType type; 51 int level; 52 int size; 53 int line_size; 54 int associativity; 55 }; 56 57 /* 58 * Known CPUID 2 cache descriptors. 59 * From Intel SDM Volume 2A, CPUID instruction 60 */ 61 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = { 62 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB, 63 .associativity = 4, .line_size = 32, }, 64 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB, 65 .associativity = 4, .line_size = 32, }, 66 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 67 .associativity = 4, .line_size = 64, }, 68 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 69 .associativity = 2, .line_size = 32, }, 70 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 71 .associativity = 4, .line_size = 32, }, 72 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 73 .associativity = 4, .line_size = 64, }, 74 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB, 75 .associativity = 6, .line_size = 64, }, 76 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 77 .associativity = 2, .line_size = 64, }, 78 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 79 .associativity = 8, .line_size = 64, }, 80 /* lines per sector is not supported cpuid2_cache_descriptor(), 81 * so descriptors 0x22, 0x23 are not included 82 */ 83 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 84 .associativity = 16, .line_size = 64, }, 85 /* lines per sector is not supported cpuid2_cache_descriptor(), 86 * so descriptors 0x25, 0x20 are not included 87 */ 88 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 89 .associativity = 8, .line_size = 64, }, 90 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB, 91 .associativity = 8, .line_size = 64, }, 92 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB, 93 .associativity = 4, .line_size = 32, }, 94 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 95 .associativity = 4, .line_size = 32, }, 96 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 97 .associativity = 4, .line_size = 32, }, 98 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 99 .associativity = 4, .line_size = 32, }, 100 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 101 .associativity = 4, .line_size = 32, }, 102 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 103 .associativity = 4, .line_size = 64, }, 104 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 105 .associativity = 8, .line_size = 64, }, 106 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB, 107 .associativity = 12, .line_size = 64, }, 108 /* Descriptor 0x49 depends on CPU family/model, so it is not included */ 109 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 110 .associativity = 12, .line_size = 64, }, 111 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 112 .associativity = 16, .line_size = 64, }, 113 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 114 .associativity = 12, .line_size = 64, }, 115 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB, 116 .associativity = 16, .line_size = 64, }, 117 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB, 118 .associativity = 24, .line_size = 64, }, 119 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 120 .associativity = 8, .line_size = 64, }, 121 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB, 122 .associativity = 4, .line_size = 64, }, 123 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB, 124 .associativity = 4, .line_size = 64, }, 125 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB, 126 .associativity = 4, .line_size = 64, }, 127 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 128 .associativity = 4, .line_size = 64, }, 129 /* lines per sector is not supported cpuid2_cache_descriptor(), 130 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included. 131 */ 132 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 133 .associativity = 8, .line_size = 64, }, 134 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 135 .associativity = 2, .line_size = 64, }, 136 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 137 .associativity = 8, .line_size = 64, }, 138 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB, 139 .associativity = 8, .line_size = 32, }, 140 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 141 .associativity = 8, .line_size = 32, }, 142 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 143 .associativity = 8, .line_size = 32, }, 144 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB, 145 .associativity = 8, .line_size = 32, }, 146 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB, 147 .associativity = 4, .line_size = 64, }, 148 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB, 149 .associativity = 8, .line_size = 64, }, 150 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB, 151 .associativity = 4, .line_size = 64, }, 152 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 153 .associativity = 4, .line_size = 64, }, 154 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 155 .associativity = 4, .line_size = 64, }, 156 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB, 157 .associativity = 8, .line_size = 64, }, 158 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 159 .associativity = 8, .line_size = 64, }, 160 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 161 .associativity = 8, .line_size = 64, }, 162 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB, 163 .associativity = 12, .line_size = 64, }, 164 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB, 165 .associativity = 12, .line_size = 64, }, 166 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB, 167 .associativity = 12, .line_size = 64, }, 168 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB, 169 .associativity = 16, .line_size = 64, }, 170 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB, 171 .associativity = 16, .line_size = 64, }, 172 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB, 173 .associativity = 16, .line_size = 64, }, 174 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB, 175 .associativity = 24, .line_size = 64, }, 176 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB, 177 .associativity = 24, .line_size = 64, }, 178 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB, 179 .associativity = 24, .line_size = 64, }, 180 }; 181 182 /* 183 * "CPUID leaf 2 does not report cache descriptor information, 184 * use CPUID leaf 4 to query cache parameters" 185 */ 186 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF 187 188 /* 189 * Return a CPUID 2 cache descriptor for a given cache. 190 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE 191 */ 192 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache) 193 { 194 int i; 195 196 assert(cache->size > 0); 197 assert(cache->level > 0); 198 assert(cache->line_size > 0); 199 assert(cache->associativity > 0); 200 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) { 201 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i]; 202 if (d->level == cache->level && d->type == cache->type && 203 d->size == cache->size && d->line_size == cache->line_size && 204 d->associativity == cache->associativity) { 205 return i; 206 } 207 } 208 209 return CACHE_DESCRIPTOR_UNAVAILABLE; 210 } 211 212 /* CPUID Leaf 4 constants: */ 213 214 /* EAX: */ 215 #define CACHE_TYPE_D 1 216 #define CACHE_TYPE_I 2 217 #define CACHE_TYPE_UNIFIED 3 218 219 #define CACHE_LEVEL(l) (l << 5) 220 221 #define CACHE_SELF_INIT_LEVEL (1 << 8) 222 223 /* EDX: */ 224 #define CACHE_NO_INVD_SHARING (1 << 0) 225 #define CACHE_INCLUSIVE (1 << 1) 226 #define CACHE_COMPLEX_IDX (1 << 2) 227 228 /* Encode CacheType for CPUID[4].EAX */ 229 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \ 230 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \ 231 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 232 0 /* Invalid value */) 233 234 235 /* Encode cache info for CPUID[4] */ 236 static void encode_cache_cpuid4(CPUCacheInfo *cache, 237 int num_apic_ids, int num_cores, 238 uint32_t *eax, uint32_t *ebx, 239 uint32_t *ecx, uint32_t *edx) 240 { 241 assert(cache->size == cache->line_size * cache->associativity * 242 cache->partitions * cache->sets); 243 244 assert(num_apic_ids > 0); 245 *eax = CACHE_TYPE(cache->type) | 246 CACHE_LEVEL(cache->level) | 247 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) | 248 ((num_cores - 1) << 26) | 249 ((num_apic_ids - 1) << 14); 250 251 assert(cache->line_size > 0); 252 assert(cache->partitions > 0); 253 assert(cache->associativity > 0); 254 /* We don't implement fully-associative caches */ 255 assert(cache->associativity < cache->sets); 256 *ebx = (cache->line_size - 1) | 257 ((cache->partitions - 1) << 12) | 258 ((cache->associativity - 1) << 22); 259 260 assert(cache->sets > 0); 261 *ecx = cache->sets - 1; 262 263 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 264 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 265 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 266 } 267 268 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */ 269 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache) 270 { 271 assert(cache->size % 1024 == 0); 272 assert(cache->lines_per_tag > 0); 273 assert(cache->associativity > 0); 274 assert(cache->line_size > 0); 275 return ((cache->size / 1024) << 24) | (cache->associativity << 16) | 276 (cache->lines_per_tag << 8) | (cache->line_size); 277 } 278 279 #define ASSOC_FULL 0xFF 280 281 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */ 282 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \ 283 a == 2 ? 0x2 : \ 284 a == 4 ? 0x4 : \ 285 a == 8 ? 0x6 : \ 286 a == 16 ? 0x8 : \ 287 a == 32 ? 0xA : \ 288 a == 48 ? 0xB : \ 289 a == 64 ? 0xC : \ 290 a == 96 ? 0xD : \ 291 a == 128 ? 0xE : \ 292 a == ASSOC_FULL ? 0xF : \ 293 0 /* invalid value */) 294 295 /* 296 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX 297 * @l3 can be NULL. 298 */ 299 static void encode_cache_cpuid80000006(CPUCacheInfo *l2, 300 CPUCacheInfo *l3, 301 uint32_t *ecx, uint32_t *edx) 302 { 303 assert(l2->size % 1024 == 0); 304 assert(l2->associativity > 0); 305 assert(l2->lines_per_tag > 0); 306 assert(l2->line_size > 0); 307 *ecx = ((l2->size / 1024) << 16) | 308 (AMD_ENC_ASSOC(l2->associativity) << 12) | 309 (l2->lines_per_tag << 8) | (l2->line_size); 310 311 if (l3) { 312 assert(l3->size % (512 * 1024) == 0); 313 assert(l3->associativity > 0); 314 assert(l3->lines_per_tag > 0); 315 assert(l3->line_size > 0); 316 *edx = ((l3->size / (512 * 1024)) << 18) | 317 (AMD_ENC_ASSOC(l3->associativity) << 12) | 318 (l3->lines_per_tag << 8) | (l3->line_size); 319 } else { 320 *edx = 0; 321 } 322 } 323 324 /* Encode cache info for CPUID[8000001D] */ 325 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, 326 X86CPUTopoInfo *topo_info, 327 uint32_t *eax, uint32_t *ebx, 328 uint32_t *ecx, uint32_t *edx) 329 { 330 uint32_t l3_threads; 331 assert(cache->size == cache->line_size * cache->associativity * 332 cache->partitions * cache->sets); 333 334 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) | 335 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0); 336 337 /* L3 is shared among multiple cores */ 338 if (cache->level == 3) { 339 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core; 340 *eax |= (l3_threads - 1) << 14; 341 } else { 342 *eax |= ((topo_info->threads_per_core - 1) << 14); 343 } 344 345 assert(cache->line_size > 0); 346 assert(cache->partitions > 0); 347 assert(cache->associativity > 0); 348 /* We don't implement fully-associative caches */ 349 assert(cache->associativity < cache->sets); 350 *ebx = (cache->line_size - 1) | 351 ((cache->partitions - 1) << 12) | 352 ((cache->associativity - 1) << 22); 353 354 assert(cache->sets > 0); 355 *ecx = cache->sets - 1; 356 357 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) | 358 (cache->inclusive ? CACHE_INCLUSIVE : 0) | 359 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); 360 } 361 362 /* Encode cache info for CPUID[8000001E] */ 363 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info, 364 uint32_t *eax, uint32_t *ebx, 365 uint32_t *ecx, uint32_t *edx) 366 { 367 X86CPUTopoIDs topo_ids; 368 369 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); 370 371 *eax = cpu->apic_id; 372 373 /* 374 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) 375 * Read-only. Reset: 0000_XXXXh. 376 * See Core::X86::Cpuid::ExtApicId. 377 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; 378 * Bits Description 379 * 31:16 Reserved. 380 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. 381 * The number of threads per core is ThreadsPerCore+1. 382 * 7:0 CoreId: core ID. Read-only. Reset: XXh. 383 * 384 * NOTE: CoreId is already part of apic_id. Just use it. We can 385 * use all the 8 bits to represent the core_id here. 386 */ 387 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF); 388 389 /* 390 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) 391 * Read-only. Reset: 0000_0XXXh. 392 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; 393 * Bits Description 394 * 31:11 Reserved. 395 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. 396 * ValidValues: 397 * Value Description 398 * 000b 1 node per processor. 399 * 001b 2 nodes per processor. 400 * 010b Reserved. 401 * 011b 4 nodes per processor. 402 * 111b-100b Reserved. 403 * 7:0 NodeId: Node ID. Read-only. Reset: XXh. 404 * 405 * NOTE: Hardware reserves 3 bits for number of nodes per processor. 406 * But users can create more nodes than the actual hardware can 407 * support. To genaralize we can use all the upper 8 bits for nodes. 408 * NodeId is combination of node and socket_id which is already decoded 409 * in apic_id. Just use it by shifting. 410 */ 411 *ecx = ((topo_info->dies_per_pkg - 1) << 8) | 412 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); 413 414 *edx = 0; 415 } 416 417 /* 418 * Definitions of the hardcoded cache entries we expose: 419 * These are legacy cache values. If there is a need to change any 420 * of these values please use builtin_x86_defs 421 */ 422 423 /* L1 data cache: */ 424 static CPUCacheInfo legacy_l1d_cache = { 425 .type = DATA_CACHE, 426 .level = 1, 427 .size = 32 * KiB, 428 .self_init = 1, 429 .line_size = 64, 430 .associativity = 8, 431 .sets = 64, 432 .partitions = 1, 433 .no_invd_sharing = true, 434 }; 435 436 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 437 static CPUCacheInfo legacy_l1d_cache_amd = { 438 .type = DATA_CACHE, 439 .level = 1, 440 .size = 64 * KiB, 441 .self_init = 1, 442 .line_size = 64, 443 .associativity = 2, 444 .sets = 512, 445 .partitions = 1, 446 .lines_per_tag = 1, 447 .no_invd_sharing = true, 448 }; 449 450 /* L1 instruction cache: */ 451 static CPUCacheInfo legacy_l1i_cache = { 452 .type = INSTRUCTION_CACHE, 453 .level = 1, 454 .size = 32 * KiB, 455 .self_init = 1, 456 .line_size = 64, 457 .associativity = 8, 458 .sets = 64, 459 .partitions = 1, 460 .no_invd_sharing = true, 461 }; 462 463 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ 464 static CPUCacheInfo legacy_l1i_cache_amd = { 465 .type = INSTRUCTION_CACHE, 466 .level = 1, 467 .size = 64 * KiB, 468 .self_init = 1, 469 .line_size = 64, 470 .associativity = 2, 471 .sets = 512, 472 .partitions = 1, 473 .lines_per_tag = 1, 474 .no_invd_sharing = true, 475 }; 476 477 /* Level 2 unified cache: */ 478 static CPUCacheInfo legacy_l2_cache = { 479 .type = UNIFIED_CACHE, 480 .level = 2, 481 .size = 4 * MiB, 482 .self_init = 1, 483 .line_size = 64, 484 .associativity = 16, 485 .sets = 4096, 486 .partitions = 1, 487 .no_invd_sharing = true, 488 }; 489 490 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ 491 static CPUCacheInfo legacy_l2_cache_cpuid2 = { 492 .type = UNIFIED_CACHE, 493 .level = 2, 494 .size = 2 * MiB, 495 .line_size = 64, 496 .associativity = 8, 497 }; 498 499 500 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ 501 static CPUCacheInfo legacy_l2_cache_amd = { 502 .type = UNIFIED_CACHE, 503 .level = 2, 504 .size = 512 * KiB, 505 .line_size = 64, 506 .lines_per_tag = 1, 507 .associativity = 16, 508 .sets = 512, 509 .partitions = 1, 510 }; 511 512 /* Level 3 unified cache: */ 513 static CPUCacheInfo legacy_l3_cache = { 514 .type = UNIFIED_CACHE, 515 .level = 3, 516 .size = 16 * MiB, 517 .line_size = 64, 518 .associativity = 16, 519 .sets = 16384, 520 .partitions = 1, 521 .lines_per_tag = 1, 522 .self_init = true, 523 .inclusive = true, 524 .complex_indexing = true, 525 }; 526 527 /* TLB definitions: */ 528 529 #define L1_DTLB_2M_ASSOC 1 530 #define L1_DTLB_2M_ENTRIES 255 531 #define L1_DTLB_4K_ASSOC 1 532 #define L1_DTLB_4K_ENTRIES 255 533 534 #define L1_ITLB_2M_ASSOC 1 535 #define L1_ITLB_2M_ENTRIES 255 536 #define L1_ITLB_4K_ASSOC 1 537 #define L1_ITLB_4K_ENTRIES 255 538 539 #define L2_DTLB_2M_ASSOC 0 /* disabled */ 540 #define L2_DTLB_2M_ENTRIES 0 /* disabled */ 541 #define L2_DTLB_4K_ASSOC 4 542 #define L2_DTLB_4K_ENTRIES 512 543 544 #define L2_ITLB_2M_ASSOC 0 /* disabled */ 545 #define L2_ITLB_2M_ENTRIES 0 /* disabled */ 546 #define L2_ITLB_4K_ASSOC 4 547 #define L2_ITLB_4K_ENTRIES 512 548 549 /* CPUID Leaf 0x14 constants: */ 550 #define INTEL_PT_MAX_SUBLEAF 0x1 551 /* 552 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH 553 * MSR can be accessed; 554 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; 555 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation 556 * of Intel PT MSRs across warm reset; 557 * bit[03]: Support MTC timing packet and suppression of COFI-based packets; 558 */ 559 #define INTEL_PT_MINIMAL_EBX 0xf 560 /* 561 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and 562 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be 563 * accessed; 564 * bit[01]: ToPA tables can hold any number of output entries, up to the 565 * maximum allowed by the MaskOrTableOffset field of 566 * IA32_RTIT_OUTPUT_MASK_PTRS; 567 * bit[02]: Support Single-Range Output scheme; 568 */ 569 #define INTEL_PT_MINIMAL_ECX 0x7 570 /* generated packets which contain IP payloads have LIP values */ 571 #define INTEL_PT_IP_LIP (1 << 31) 572 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */ 573 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 574 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ 575 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ 576 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */ 577 578 /* CPUID Leaf 0x1D constants: */ 579 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 580 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 581 #define INTEL_AMX_BYTES_PER_TILE 0x400 582 #define INTEL_AMX_BYTES_PER_ROW 0x40 583 #define INTEL_AMX_TILE_MAX_NAMES 0x8 584 #define INTEL_AMX_TILE_MAX_ROWS 0x10 585 586 /* CPUID Leaf 0x1E constants: */ 587 #define INTEL_AMX_TMUL_MAX_K 0x10 588 #define INTEL_AMX_TMUL_MAX_N 0x40 589 590 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, 591 uint32_t vendor2, uint32_t vendor3) 592 { 593 int i; 594 for (i = 0; i < 4; i++) { 595 dst[i] = vendor1 >> (8 * i); 596 dst[i + 4] = vendor2 >> (8 * i); 597 dst[i + 8] = vendor3 >> (8 * i); 598 } 599 dst[CPUID_VENDOR_SZ] = '\0'; 600 } 601 602 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) 603 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \ 604 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) 605 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \ 606 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 607 CPUID_PSE36 | CPUID_FXSR) 608 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE) 609 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \ 610 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ 611 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ 612 CPUID_PAE | CPUID_SEP | CPUID_APIC) 613 614 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \ 615 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ 616 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ 617 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ 618 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE) 619 /* partly implemented: 620 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */ 621 /* missing: 622 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */ 623 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \ 624 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \ 625 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \ 626 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \ 627 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \ 628 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \ 629 CPUID_EXT_FMA) 630 /* missing: 631 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX, 632 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, 633 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA, 634 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */ 635 636 #ifdef TARGET_X86_64 637 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM) 638 #else 639 #define TCG_EXT2_X86_64_FEATURES 0 640 #endif 641 642 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \ 643 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ 644 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \ 645 TCG_EXT2_X86_64_FEATURES) 646 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \ 647 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) 648 #define TCG_EXT4_FEATURES 0 649 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \ 650 CPUID_SVM_SVME_ADDR_CHK) 651 #define TCG_KVM_FEATURES 0 652 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ 653 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ 654 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ 655 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \ 656 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2) 657 /* missing: 658 CPUID_7_0_EBX_HLE 659 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, 660 CPUID_7_0_EBX_RDSEED */ 661 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \ 662 /* CPUID_7_0_ECX_OSPKE is dynamic */ \ 663 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES) 664 #define TCG_7_0_EDX_FEATURES 0 665 #define TCG_7_1_EAX_FEATURES 0 666 #define TCG_APM_FEATURES 0 667 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT 668 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1) 669 /* missing: 670 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */ 671 #define TCG_14_0_ECX_FEATURES 0 672 #define TCG_SGX_12_0_EAX_FEATURES 0 673 #define TCG_SGX_12_0_EBX_FEATURES 0 674 #define TCG_SGX_12_1_EAX_FEATURES 0 675 676 FeatureWordInfo feature_word_info[FEATURE_WORDS] = { 677 [FEAT_1_EDX] = { 678 .type = CPUID_FEATURE_WORD, 679 .feat_names = { 680 "fpu", "vme", "de", "pse", 681 "tsc", "msr", "pae", "mce", 682 "cx8", "apic", NULL, "sep", 683 "mtrr", "pge", "mca", "cmov", 684 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, 685 NULL, "ds" /* Intel dts */, "acpi", "mmx", 686 "fxsr", "sse", "sse2", "ss", 687 "ht" /* Intel htt */, "tm", "ia64", "pbe", 688 }, 689 .cpuid = {.eax = 1, .reg = R_EDX, }, 690 .tcg_features = TCG_FEATURES, 691 }, 692 [FEAT_1_ECX] = { 693 .type = CPUID_FEATURE_WORD, 694 .feat_names = { 695 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor", 696 "ds-cpl", "vmx", "smx", "est", 697 "tm2", "ssse3", "cid", NULL, 698 "fma", "cx16", "xtpr", "pdcm", 699 NULL, "pcid", "dca", "sse4.1", 700 "sse4.2", "x2apic", "movbe", "popcnt", 701 "tsc-deadline", "aes", "xsave", NULL /* osxsave */, 702 "avx", "f16c", "rdrand", "hypervisor", 703 }, 704 .cpuid = { .eax = 1, .reg = R_ECX, }, 705 .tcg_features = TCG_EXT_FEATURES, 706 }, 707 /* Feature names that are already defined on feature_name[] but 708 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their 709 * names on feat_names below. They are copied automatically 710 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD. 711 */ 712 [FEAT_8000_0001_EDX] = { 713 .type = CPUID_FEATURE_WORD, 714 .feat_names = { 715 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */, 716 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */, 717 NULL /* cx8 */, NULL /* apic */, NULL, "syscall", 718 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */, 719 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */, 720 "nx", NULL, "mmxext", NULL /* mmx */, 721 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp", 722 NULL, "lm", "3dnowext", "3dnow", 723 }, 724 .cpuid = { .eax = 0x80000001, .reg = R_EDX, }, 725 .tcg_features = TCG_EXT2_FEATURES, 726 }, 727 [FEAT_8000_0001_ECX] = { 728 .type = CPUID_FEATURE_WORD, 729 .feat_names = { 730 "lahf-lm", "cmp-legacy", "svm", "extapic", 731 "cr8legacy", "abm", "sse4a", "misalignsse", 732 "3dnowprefetch", "osvw", "ibs", "xop", 733 "skinit", "wdt", NULL, "lwp", 734 "fma4", "tce", NULL, "nodeid-msr", 735 NULL, "tbm", "topoext", "perfctr-core", 736 "perfctr-nb", NULL, NULL, NULL, 737 NULL, NULL, NULL, NULL, 738 }, 739 .cpuid = { .eax = 0x80000001, .reg = R_ECX, }, 740 .tcg_features = TCG_EXT3_FEATURES, 741 /* 742 * TOPOEXT is always allowed but can't be enabled blindly by 743 * "-cpu host", as it requires consistent cache topology info 744 * to be provided so it doesn't confuse guests. 745 */ 746 .no_autoenable_flags = CPUID_EXT3_TOPOEXT, 747 }, 748 [FEAT_C000_0001_EDX] = { 749 .type = CPUID_FEATURE_WORD, 750 .feat_names = { 751 NULL, NULL, "xstore", "xstore-en", 752 NULL, NULL, "xcrypt", "xcrypt-en", 753 "ace2", "ace2-en", "phe", "phe-en", 754 "pmm", "pmm-en", NULL, NULL, 755 NULL, NULL, NULL, NULL, 756 NULL, NULL, NULL, NULL, 757 NULL, NULL, NULL, NULL, 758 NULL, NULL, NULL, NULL, 759 }, 760 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, }, 761 .tcg_features = TCG_EXT4_FEATURES, 762 }, 763 [FEAT_KVM] = { 764 .type = CPUID_FEATURE_WORD, 765 .feat_names = { 766 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock", 767 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt", 768 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi", 769 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id", 770 NULL, NULL, NULL, NULL, 771 NULL, NULL, NULL, NULL, 772 "kvmclock-stable-bit", NULL, NULL, NULL, 773 NULL, NULL, NULL, NULL, 774 }, 775 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, }, 776 .tcg_features = TCG_KVM_FEATURES, 777 }, 778 [FEAT_KVM_HINTS] = { 779 .type = CPUID_FEATURE_WORD, 780 .feat_names = { 781 "kvm-hint-dedicated", NULL, NULL, NULL, 782 NULL, NULL, NULL, NULL, 783 NULL, NULL, NULL, NULL, 784 NULL, NULL, NULL, NULL, 785 NULL, NULL, NULL, NULL, 786 NULL, NULL, NULL, NULL, 787 NULL, NULL, NULL, NULL, 788 NULL, NULL, NULL, NULL, 789 }, 790 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, }, 791 .tcg_features = TCG_KVM_FEATURES, 792 /* 793 * KVM hints aren't auto-enabled by -cpu host, they need to be 794 * explicitly enabled in the command-line. 795 */ 796 .no_autoenable_flags = ~0U, 797 }, 798 [FEAT_SVM] = { 799 .type = CPUID_FEATURE_WORD, 800 .feat_names = { 801 "npt", "lbrv", "svm-lock", "nrip-save", 802 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists", 803 NULL, NULL, "pause-filter", NULL, 804 "pfthreshold", "avic", NULL, "v-vmsave-vmload", 805 "vgif", NULL, NULL, NULL, 806 NULL, NULL, NULL, NULL, 807 NULL, NULL, NULL, NULL, 808 "svme-addr-chk", NULL, NULL, NULL, 809 }, 810 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, }, 811 .tcg_features = TCG_SVM_FEATURES, 812 }, 813 [FEAT_7_0_EBX] = { 814 .type = CPUID_FEATURE_WORD, 815 .feat_names = { 816 "fsgsbase", "tsc-adjust", "sgx", "bmi1", 817 "hle", "avx2", NULL, "smep", 818 "bmi2", "erms", "invpcid", "rtm", 819 NULL, NULL, "mpx", NULL, 820 "avx512f", "avx512dq", "rdseed", "adx", 821 "smap", "avx512ifma", "pcommit", "clflushopt", 822 "clwb", "intel-pt", "avx512pf", "avx512er", 823 "avx512cd", "sha-ni", "avx512bw", "avx512vl", 824 }, 825 .cpuid = { 826 .eax = 7, 827 .needs_ecx = true, .ecx = 0, 828 .reg = R_EBX, 829 }, 830 .tcg_features = TCG_7_0_EBX_FEATURES, 831 }, 832 [FEAT_7_0_ECX] = { 833 .type = CPUID_FEATURE_WORD, 834 .feat_names = { 835 NULL, "avx512vbmi", "umip", "pku", 836 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL, 837 "gfni", "vaes", "vpclmulqdq", "avx512vnni", 838 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, 839 "la57", NULL, NULL, NULL, 840 NULL, NULL, "rdpid", NULL, 841 "bus-lock-detect", "cldemote", NULL, "movdiri", 842 "movdir64b", NULL, "sgxlc", "pks", 843 }, 844 .cpuid = { 845 .eax = 7, 846 .needs_ecx = true, .ecx = 0, 847 .reg = R_ECX, 848 }, 849 .tcg_features = TCG_7_0_ECX_FEATURES, 850 }, 851 [FEAT_7_0_EDX] = { 852 .type = CPUID_FEATURE_WORD, 853 .feat_names = { 854 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", 855 "fsrm", NULL, NULL, NULL, 856 "avx512-vp2intersect", NULL, "md-clear", NULL, 857 NULL, NULL, "serialize", NULL, 858 "tsx-ldtrk", NULL, NULL /* pconfig */, "arch-lbr", 859 NULL, NULL, "amx-bf16", "avx512-fp16", 860 "amx-tile", "amx-int8", "spec-ctrl", "stibp", 861 NULL, "arch-capabilities", "core-capability", "ssbd", 862 }, 863 .cpuid = { 864 .eax = 7, 865 .needs_ecx = true, .ecx = 0, 866 .reg = R_EDX, 867 }, 868 .tcg_features = TCG_7_0_EDX_FEATURES, 869 }, 870 [FEAT_7_1_EAX] = { 871 .type = CPUID_FEATURE_WORD, 872 .feat_names = { 873 NULL, NULL, NULL, NULL, 874 "avx-vnni", "avx512-bf16", NULL, NULL, 875 NULL, NULL, NULL, NULL, 876 NULL, NULL, NULL, NULL, 877 NULL, NULL, NULL, NULL, 878 NULL, NULL, NULL, NULL, 879 NULL, NULL, NULL, NULL, 880 NULL, NULL, NULL, NULL, 881 }, 882 .cpuid = { 883 .eax = 7, 884 .needs_ecx = true, .ecx = 1, 885 .reg = R_EAX, 886 }, 887 .tcg_features = TCG_7_1_EAX_FEATURES, 888 }, 889 [FEAT_8000_0007_EDX] = { 890 .type = CPUID_FEATURE_WORD, 891 .feat_names = { 892 NULL, NULL, NULL, NULL, 893 NULL, NULL, NULL, NULL, 894 "invtsc", NULL, NULL, NULL, 895 NULL, NULL, NULL, NULL, 896 NULL, NULL, NULL, NULL, 897 NULL, NULL, NULL, NULL, 898 NULL, NULL, NULL, NULL, 899 NULL, NULL, NULL, NULL, 900 }, 901 .cpuid = { .eax = 0x80000007, .reg = R_EDX, }, 902 .tcg_features = TCG_APM_FEATURES, 903 .unmigratable_flags = CPUID_APM_INVTSC, 904 }, 905 [FEAT_8000_0008_EBX] = { 906 .type = CPUID_FEATURE_WORD, 907 .feat_names = { 908 "clzero", NULL, "xsaveerptr", NULL, 909 NULL, NULL, NULL, NULL, 910 NULL, "wbnoinvd", NULL, NULL, 911 "ibpb", NULL, "ibrs", "amd-stibp", 912 NULL, NULL, NULL, NULL, 913 NULL, NULL, NULL, NULL, 914 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL, 915 NULL, NULL, NULL, NULL, 916 }, 917 .cpuid = { .eax = 0x80000008, .reg = R_EBX, }, 918 .tcg_features = 0, 919 .unmigratable_flags = 0, 920 }, 921 [FEAT_XSAVE] = { 922 .type = CPUID_FEATURE_WORD, 923 .feat_names = { 924 "xsaveopt", "xsavec", "xgetbv1", "xsaves", 925 "xfd", NULL, NULL, NULL, 926 NULL, NULL, NULL, NULL, 927 NULL, NULL, NULL, NULL, 928 NULL, NULL, NULL, NULL, 929 NULL, NULL, NULL, NULL, 930 NULL, NULL, NULL, NULL, 931 NULL, NULL, NULL, NULL, 932 }, 933 .cpuid = { 934 .eax = 0xd, 935 .needs_ecx = true, .ecx = 1, 936 .reg = R_EAX, 937 }, 938 .tcg_features = TCG_XSAVE_FEATURES, 939 }, 940 [FEAT_XSAVE_XSS_LO] = { 941 .type = CPUID_FEATURE_WORD, 942 .feat_names = { 943 NULL, NULL, NULL, NULL, 944 NULL, NULL, NULL, NULL, 945 NULL, NULL, NULL, NULL, 946 NULL, NULL, NULL, NULL, 947 NULL, NULL, NULL, NULL, 948 NULL, NULL, NULL, NULL, 949 NULL, NULL, NULL, NULL, 950 NULL, NULL, NULL, NULL, 951 }, 952 .cpuid = { 953 .eax = 0xD, 954 .needs_ecx = true, 955 .ecx = 1, 956 .reg = R_ECX, 957 }, 958 }, 959 [FEAT_XSAVE_XSS_HI] = { 960 .type = CPUID_FEATURE_WORD, 961 .cpuid = { 962 .eax = 0xD, 963 .needs_ecx = true, 964 .ecx = 1, 965 .reg = R_EDX 966 }, 967 }, 968 [FEAT_6_EAX] = { 969 .type = CPUID_FEATURE_WORD, 970 .feat_names = { 971 NULL, NULL, "arat", NULL, 972 NULL, NULL, NULL, NULL, 973 NULL, NULL, NULL, NULL, 974 NULL, NULL, NULL, NULL, 975 NULL, NULL, NULL, NULL, 976 NULL, NULL, NULL, NULL, 977 NULL, NULL, NULL, NULL, 978 NULL, NULL, NULL, NULL, 979 }, 980 .cpuid = { .eax = 6, .reg = R_EAX, }, 981 .tcg_features = TCG_6_EAX_FEATURES, 982 }, 983 [FEAT_XSAVE_XCR0_LO] = { 984 .type = CPUID_FEATURE_WORD, 985 .cpuid = { 986 .eax = 0xD, 987 .needs_ecx = true, .ecx = 0, 988 .reg = R_EAX, 989 }, 990 .tcg_features = ~0U, 991 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK | 992 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | 993 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK | 994 XSTATE_PKRU_MASK, 995 }, 996 [FEAT_XSAVE_XCR0_HI] = { 997 .type = CPUID_FEATURE_WORD, 998 .cpuid = { 999 .eax = 0xD, 1000 .needs_ecx = true, .ecx = 0, 1001 .reg = R_EDX, 1002 }, 1003 .tcg_features = ~0U, 1004 }, 1005 /*Below are MSR exposed features*/ 1006 [FEAT_ARCH_CAPABILITIES] = { 1007 .type = MSR_FEATURE_WORD, 1008 .feat_names = { 1009 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry", 1010 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl", 1011 "taa-no", NULL, NULL, NULL, 1012 NULL, NULL, NULL, NULL, 1013 NULL, NULL, NULL, NULL, 1014 NULL, NULL, NULL, NULL, 1015 NULL, NULL, NULL, NULL, 1016 NULL, NULL, NULL, NULL, 1017 }, 1018 .msr = { 1019 .index = MSR_IA32_ARCH_CAPABILITIES, 1020 }, 1021 }, 1022 [FEAT_CORE_CAPABILITY] = { 1023 .type = MSR_FEATURE_WORD, 1024 .feat_names = { 1025 NULL, NULL, NULL, NULL, 1026 NULL, "split-lock-detect", NULL, NULL, 1027 NULL, NULL, NULL, NULL, 1028 NULL, NULL, NULL, NULL, 1029 NULL, NULL, NULL, NULL, 1030 NULL, NULL, NULL, NULL, 1031 NULL, NULL, NULL, NULL, 1032 NULL, NULL, NULL, NULL, 1033 }, 1034 .msr = { 1035 .index = MSR_IA32_CORE_CAPABILITY, 1036 }, 1037 }, 1038 [FEAT_PERF_CAPABILITIES] = { 1039 .type = MSR_FEATURE_WORD, 1040 .feat_names = { 1041 NULL, NULL, NULL, NULL, 1042 NULL, NULL, NULL, NULL, 1043 NULL, NULL, NULL, NULL, 1044 NULL, "full-width-write", NULL, NULL, 1045 NULL, NULL, NULL, NULL, 1046 NULL, NULL, NULL, NULL, 1047 NULL, NULL, NULL, NULL, 1048 NULL, NULL, NULL, NULL, 1049 }, 1050 .msr = { 1051 .index = MSR_IA32_PERF_CAPABILITIES, 1052 }, 1053 }, 1054 1055 [FEAT_VMX_PROCBASED_CTLS] = { 1056 .type = MSR_FEATURE_WORD, 1057 .feat_names = { 1058 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset", 1059 NULL, NULL, NULL, "vmx-hlt-exit", 1060 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit", 1061 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit", 1062 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit", 1063 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit", 1064 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf", 1065 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls", 1066 }, 1067 .msr = { 1068 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS, 1069 } 1070 }, 1071 1072 [FEAT_VMX_SECONDARY_CTLS] = { 1073 .type = MSR_FEATURE_WORD, 1074 .feat_names = { 1075 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit", 1076 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest", 1077 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit", 1078 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit", 1079 "vmx-rdseed-exit", "vmx-pml", NULL, NULL, 1080 "vmx-xsaves", NULL, NULL, NULL, 1081 NULL, "vmx-tsc-scaling", NULL, NULL, 1082 NULL, NULL, NULL, NULL, 1083 }, 1084 .msr = { 1085 .index = MSR_IA32_VMX_PROCBASED_CTLS2, 1086 } 1087 }, 1088 1089 [FEAT_VMX_PINBASED_CTLS] = { 1090 .type = MSR_FEATURE_WORD, 1091 .feat_names = { 1092 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit", 1093 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr", 1094 NULL, NULL, NULL, NULL, 1095 NULL, NULL, NULL, NULL, 1096 NULL, NULL, NULL, NULL, 1097 NULL, NULL, NULL, NULL, 1098 NULL, NULL, NULL, NULL, 1099 NULL, NULL, NULL, NULL, 1100 }, 1101 .msr = { 1102 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS, 1103 } 1104 }, 1105 1106 [FEAT_VMX_EXIT_CTLS] = { 1107 .type = MSR_FEATURE_WORD, 1108 /* 1109 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from 1110 * the LM CPUID bit. 1111 */ 1112 .feat_names = { 1113 NULL, NULL, "vmx-exit-nosave-debugctl", NULL, 1114 NULL, NULL, NULL, NULL, 1115 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL, 1116 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr", 1117 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat", 1118 "vmx-exit-save-efer", "vmx-exit-load-efer", 1119 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs", 1120 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL, 1121 NULL, "vmx-exit-load-pkrs", NULL, NULL, 1122 }, 1123 .msr = { 1124 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS, 1125 } 1126 }, 1127 1128 [FEAT_VMX_ENTRY_CTLS] = { 1129 .type = MSR_FEATURE_WORD, 1130 .feat_names = { 1131 NULL, NULL, "vmx-entry-noload-debugctl", NULL, 1132 NULL, NULL, NULL, NULL, 1133 NULL, "vmx-entry-ia32e-mode", NULL, NULL, 1134 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer", 1135 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL, 1136 NULL, NULL, "vmx-entry-load-pkrs", NULL, 1137 NULL, NULL, NULL, NULL, 1138 NULL, NULL, NULL, NULL, 1139 }, 1140 .msr = { 1141 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS, 1142 } 1143 }, 1144 1145 [FEAT_VMX_MISC] = { 1146 .type = MSR_FEATURE_WORD, 1147 .feat_names = { 1148 NULL, NULL, NULL, NULL, 1149 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown", 1150 "vmx-activity-wait-sipi", NULL, NULL, NULL, 1151 NULL, NULL, NULL, NULL, 1152 NULL, NULL, NULL, NULL, 1153 NULL, NULL, NULL, NULL, 1154 NULL, NULL, NULL, NULL, 1155 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL, 1156 }, 1157 .msr = { 1158 .index = MSR_IA32_VMX_MISC, 1159 } 1160 }, 1161 1162 [FEAT_VMX_EPT_VPID_CAPS] = { 1163 .type = MSR_FEATURE_WORD, 1164 .feat_names = { 1165 "vmx-ept-execonly", NULL, NULL, NULL, 1166 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5", 1167 NULL, NULL, NULL, NULL, 1168 NULL, NULL, NULL, NULL, 1169 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL, 1170 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL, 1171 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL, 1172 NULL, NULL, NULL, NULL, 1173 "vmx-invvpid", NULL, NULL, NULL, 1174 NULL, NULL, NULL, NULL, 1175 "vmx-invvpid-single-addr", "vmx-invept-single-context", 1176 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals", 1177 NULL, NULL, NULL, NULL, 1178 NULL, NULL, NULL, NULL, 1179 NULL, NULL, NULL, NULL, 1180 NULL, NULL, NULL, NULL, 1181 NULL, NULL, NULL, NULL, 1182 }, 1183 .msr = { 1184 .index = MSR_IA32_VMX_EPT_VPID_CAP, 1185 } 1186 }, 1187 1188 [FEAT_VMX_BASIC] = { 1189 .type = MSR_FEATURE_WORD, 1190 .feat_names = { 1191 [54] = "vmx-ins-outs", 1192 [55] = "vmx-true-ctls", 1193 }, 1194 .msr = { 1195 .index = MSR_IA32_VMX_BASIC, 1196 }, 1197 /* Just to be safe - we don't support setting the MSEG version field. */ 1198 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR, 1199 }, 1200 1201 [FEAT_VMX_VMFUNC] = { 1202 .type = MSR_FEATURE_WORD, 1203 .feat_names = { 1204 [0] = "vmx-eptp-switching", 1205 }, 1206 .msr = { 1207 .index = MSR_IA32_VMX_VMFUNC, 1208 } 1209 }, 1210 1211 [FEAT_14_0_ECX] = { 1212 .type = CPUID_FEATURE_WORD, 1213 .feat_names = { 1214 NULL, NULL, NULL, NULL, 1215 NULL, NULL, NULL, NULL, 1216 NULL, NULL, NULL, NULL, 1217 NULL, NULL, NULL, NULL, 1218 NULL, NULL, NULL, NULL, 1219 NULL, NULL, NULL, NULL, 1220 NULL, NULL, NULL, NULL, 1221 NULL, NULL, NULL, "intel-pt-lip", 1222 }, 1223 .cpuid = { 1224 .eax = 0x14, 1225 .needs_ecx = true, .ecx = 0, 1226 .reg = R_ECX, 1227 }, 1228 .tcg_features = TCG_14_0_ECX_FEATURES, 1229 }, 1230 1231 [FEAT_SGX_12_0_EAX] = { 1232 .type = CPUID_FEATURE_WORD, 1233 .feat_names = { 1234 "sgx1", "sgx2", NULL, NULL, 1235 NULL, NULL, NULL, NULL, 1236 NULL, NULL, NULL, NULL, 1237 NULL, NULL, NULL, NULL, 1238 NULL, NULL, NULL, NULL, 1239 NULL, NULL, NULL, NULL, 1240 NULL, NULL, NULL, NULL, 1241 NULL, NULL, NULL, NULL, 1242 }, 1243 .cpuid = { 1244 .eax = 0x12, 1245 .needs_ecx = true, .ecx = 0, 1246 .reg = R_EAX, 1247 }, 1248 .tcg_features = TCG_SGX_12_0_EAX_FEATURES, 1249 }, 1250 1251 [FEAT_SGX_12_0_EBX] = { 1252 .type = CPUID_FEATURE_WORD, 1253 .feat_names = { 1254 "sgx-exinfo" , NULL, NULL, NULL, 1255 NULL, NULL, NULL, NULL, 1256 NULL, NULL, NULL, NULL, 1257 NULL, NULL, NULL, NULL, 1258 NULL, NULL, NULL, NULL, 1259 NULL, NULL, NULL, NULL, 1260 NULL, NULL, NULL, NULL, 1261 NULL, NULL, NULL, NULL, 1262 }, 1263 .cpuid = { 1264 .eax = 0x12, 1265 .needs_ecx = true, .ecx = 0, 1266 .reg = R_EBX, 1267 }, 1268 .tcg_features = TCG_SGX_12_0_EBX_FEATURES, 1269 }, 1270 1271 [FEAT_SGX_12_1_EAX] = { 1272 .type = CPUID_FEATURE_WORD, 1273 .feat_names = { 1274 NULL, "sgx-debug", "sgx-mode64", NULL, 1275 "sgx-provisionkey", "sgx-tokenkey", NULL, "sgx-kss", 1276 NULL, NULL, NULL, NULL, 1277 NULL, NULL, NULL, NULL, 1278 NULL, NULL, NULL, NULL, 1279 NULL, NULL, NULL, NULL, 1280 NULL, NULL, NULL, NULL, 1281 NULL, NULL, NULL, NULL, 1282 }, 1283 .cpuid = { 1284 .eax = 0x12, 1285 .needs_ecx = true, .ecx = 1, 1286 .reg = R_EAX, 1287 }, 1288 .tcg_features = TCG_SGX_12_1_EAX_FEATURES, 1289 }, 1290 }; 1291 1292 typedef struct FeatureMask { 1293 FeatureWord index; 1294 uint64_t mask; 1295 } FeatureMask; 1296 1297 typedef struct FeatureDep { 1298 FeatureMask from, to; 1299 } FeatureDep; 1300 1301 static FeatureDep feature_dependencies[] = { 1302 { 1303 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES }, 1304 .to = { FEAT_ARCH_CAPABILITIES, ~0ull }, 1305 }, 1306 { 1307 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY }, 1308 .to = { FEAT_CORE_CAPABILITY, ~0ull }, 1309 }, 1310 { 1311 .from = { FEAT_1_ECX, CPUID_EXT_PDCM }, 1312 .to = { FEAT_PERF_CAPABILITIES, ~0ull }, 1313 }, 1314 { 1315 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1316 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull }, 1317 }, 1318 { 1319 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1320 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull }, 1321 }, 1322 { 1323 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1324 .to = { FEAT_VMX_EXIT_CTLS, ~0ull }, 1325 }, 1326 { 1327 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1328 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull }, 1329 }, 1330 { 1331 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1332 .to = { FEAT_VMX_MISC, ~0ull }, 1333 }, 1334 { 1335 .from = { FEAT_1_ECX, CPUID_EXT_VMX }, 1336 .to = { FEAT_VMX_BASIC, ~0ull }, 1337 }, 1338 { 1339 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM }, 1340 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE }, 1341 }, 1342 { 1343 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS }, 1344 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull }, 1345 }, 1346 { 1347 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES }, 1348 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES }, 1349 }, 1350 { 1351 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND }, 1352 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING }, 1353 }, 1354 { 1355 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID }, 1356 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID }, 1357 }, 1358 { 1359 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1360 .to = { FEAT_VMX_EXIT_CTLS, VMX_VM_EXIT_CLEAR_BNDCFGS }, 1361 }, 1362 { 1363 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_MPX }, 1364 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_BNDCFGS }, 1365 }, 1366 { 1367 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED }, 1368 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING }, 1369 }, 1370 { 1371 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT }, 1372 .to = { FEAT_14_0_ECX, ~0ull }, 1373 }, 1374 { 1375 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP }, 1376 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP }, 1377 }, 1378 { 1379 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1380 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull }, 1381 }, 1382 { 1383 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT }, 1384 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST }, 1385 }, 1386 { 1387 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID }, 1388 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 }, 1389 }, 1390 { 1391 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC }, 1392 .to = { FEAT_VMX_VMFUNC, ~0ull }, 1393 }, 1394 { 1395 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM }, 1396 .to = { FEAT_SVM, ~0ull }, 1397 }, 1398 }; 1399 1400 typedef struct X86RegisterInfo32 { 1401 /* Name of register */ 1402 const char *name; 1403 /* QAPI enum value register */ 1404 X86CPURegister32 qapi_enum; 1405 } X86RegisterInfo32; 1406 1407 #define REGISTER(reg) \ 1408 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } 1409 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { 1410 REGISTER(EAX), 1411 REGISTER(ECX), 1412 REGISTER(EDX), 1413 REGISTER(EBX), 1414 REGISTER(ESP), 1415 REGISTER(EBP), 1416 REGISTER(ESI), 1417 REGISTER(EDI), 1418 }; 1419 #undef REGISTER 1420 1421 /* CPUID feature bits available in XSS */ 1422 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK) 1423 1424 ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT] = { 1425 [XSTATE_FP_BIT] = { 1426 /* x87 FP state component is always enabled if XSAVE is supported */ 1427 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1428 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1429 }, 1430 [XSTATE_SSE_BIT] = { 1431 /* SSE state component is always enabled if XSAVE is supported */ 1432 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE, 1433 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), 1434 }, 1435 [XSTATE_YMM_BIT] = 1436 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, 1437 .size = sizeof(XSaveAVX) }, 1438 [XSTATE_BNDREGS_BIT] = 1439 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1440 .size = sizeof(XSaveBNDREG) }, 1441 [XSTATE_BNDCSR_BIT] = 1442 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, 1443 .size = sizeof(XSaveBNDCSR) }, 1444 [XSTATE_OPMASK_BIT] = 1445 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1446 .size = sizeof(XSaveOpmask) }, 1447 [XSTATE_ZMM_Hi256_BIT] = 1448 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1449 .size = sizeof(XSaveZMM_Hi256) }, 1450 [XSTATE_Hi16_ZMM_BIT] = 1451 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F, 1452 .size = sizeof(XSaveHi16_ZMM) }, 1453 [XSTATE_PKRU_BIT] = 1454 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU, 1455 .size = sizeof(XSavePKRU) }, 1456 [XSTATE_ARCH_LBR_BIT] = { 1457 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_ARCH_LBR, 1458 .offset = 0 /*supervisor mode component, offset = 0 */, 1459 .size = sizeof(XSavesArchLBR) }, 1460 [XSTATE_XTILE_CFG_BIT] = { 1461 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1462 .size = sizeof(XSaveXTILECFG), 1463 }, 1464 [XSTATE_XTILE_DATA_BIT] = { 1465 .feature = FEAT_7_0_EDX, .bits = CPUID_7_0_EDX_AMX_TILE, 1466 .size = sizeof(XSaveXTILEDATA) 1467 }, 1468 }; 1469 1470 uint32_t xsave_area_size(uint64_t mask, bool compacted) 1471 { 1472 uint64_t ret = x86_ext_save_areas[0].size; 1473 const ExtSaveArea *esa; 1474 uint32_t offset = 0; 1475 int i; 1476 1477 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 1478 esa = &x86_ext_save_areas[i]; 1479 if ((mask >> i) & 1) { 1480 offset = compacted ? ret : esa->offset; 1481 ret = MAX(ret, offset + esa->size); 1482 } 1483 } 1484 return ret; 1485 } 1486 1487 static inline bool accel_uses_host_cpuid(void) 1488 { 1489 return kvm_enabled() || hvf_enabled(); 1490 } 1491 1492 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) 1493 { 1494 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | 1495 cpu->env.features[FEAT_XSAVE_XCR0_LO]; 1496 } 1497 1498 /* Return name of 32-bit register, from a R_* constant */ 1499 static const char *get_register_name_32(unsigned int reg) 1500 { 1501 if (reg >= CPU_NB_REGS32) { 1502 return NULL; 1503 } 1504 return x86_reg_info_32[reg].name; 1505 } 1506 1507 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) 1508 { 1509 return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | 1510 cpu->env.features[FEAT_XSAVE_XSS_LO]; 1511 } 1512 1513 /* 1514 * Returns the set of feature flags that are supported and migratable by 1515 * QEMU, for a given FeatureWord. 1516 */ 1517 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w) 1518 { 1519 FeatureWordInfo *wi = &feature_word_info[w]; 1520 uint64_t r = 0; 1521 int i; 1522 1523 for (i = 0; i < 64; i++) { 1524 uint64_t f = 1ULL << i; 1525 1526 /* If the feature name is known, it is implicitly considered migratable, 1527 * unless it is explicitly set in unmigratable_flags */ 1528 if ((wi->migratable_flags & f) || 1529 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) { 1530 r |= f; 1531 } 1532 } 1533 return r; 1534 } 1535 1536 void host_cpuid(uint32_t function, uint32_t count, 1537 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) 1538 { 1539 uint32_t vec[4]; 1540 1541 #ifdef __x86_64__ 1542 asm volatile("cpuid" 1543 : "=a"(vec[0]), "=b"(vec[1]), 1544 "=c"(vec[2]), "=d"(vec[3]) 1545 : "0"(function), "c"(count) : "cc"); 1546 #elif defined(__i386__) 1547 asm volatile("pusha \n\t" 1548 "cpuid \n\t" 1549 "mov %%eax, 0(%2) \n\t" 1550 "mov %%ebx, 4(%2) \n\t" 1551 "mov %%ecx, 8(%2) \n\t" 1552 "mov %%edx, 12(%2) \n\t" 1553 "popa" 1554 : : "a"(function), "c"(count), "S"(vec) 1555 : "memory", "cc"); 1556 #else 1557 abort(); 1558 #endif 1559 1560 if (eax) 1561 *eax = vec[0]; 1562 if (ebx) 1563 *ebx = vec[1]; 1564 if (ecx) 1565 *ecx = vec[2]; 1566 if (edx) 1567 *edx = vec[3]; 1568 } 1569 1570 /* CPU class name definitions: */ 1571 1572 /* Return type name for a given CPU model name 1573 * Caller is responsible for freeing the returned string. 1574 */ 1575 static char *x86_cpu_type_name(const char *model_name) 1576 { 1577 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name); 1578 } 1579 1580 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model) 1581 { 1582 g_autofree char *typename = x86_cpu_type_name(cpu_model); 1583 return object_class_by_name(typename); 1584 } 1585 1586 static char *x86_cpu_class_get_model_name(X86CPUClass *cc) 1587 { 1588 const char *class_name = object_class_get_name(OBJECT_CLASS(cc)); 1589 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX)); 1590 return g_strndup(class_name, 1591 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX)); 1592 } 1593 1594 typedef struct X86CPUVersionDefinition { 1595 X86CPUVersion version; 1596 const char *alias; 1597 const char *note; 1598 PropValue *props; 1599 } X86CPUVersionDefinition; 1600 1601 /* Base definition for a CPU model */ 1602 typedef struct X86CPUDefinition { 1603 const char *name; 1604 uint32_t level; 1605 uint32_t xlevel; 1606 /* vendor is zero-terminated, 12 character ASCII string */ 1607 char vendor[CPUID_VENDOR_SZ + 1]; 1608 int family; 1609 int model; 1610 int stepping; 1611 int brand_id; 1612 FeatureWordArray features; 1613 const char *model_id; 1614 const CPUCaches *const cache_info; 1615 /* 1616 * Definitions for alternative versions of CPU model. 1617 * List is terminated by item with version == 0. 1618 * If NULL, version 1 will be registered automatically. 1619 */ 1620 const X86CPUVersionDefinition *versions; 1621 const char *deprecation_note; 1622 } X86CPUDefinition; 1623 1624 /* Reference to a specific CPU model version */ 1625 struct X86CPUModel { 1626 /* Base CPU definition */ 1627 const X86CPUDefinition *cpudef; 1628 /* CPU model version */ 1629 X86CPUVersion version; 1630 const char *note; 1631 /* 1632 * If true, this is an alias CPU model. 1633 * This matters only for "-cpu help" and query-cpu-definitions 1634 */ 1635 bool is_alias; 1636 }; 1637 1638 /* Get full model name for CPU version */ 1639 static char *x86_cpu_versioned_model_name(const X86CPUDefinition *cpudef, 1640 X86CPUVersion version) 1641 { 1642 assert(version > 0); 1643 return g_strdup_printf("%s-v%d", cpudef->name, (int)version); 1644 } 1645 1646 static const X86CPUVersionDefinition * 1647 x86_cpu_def_get_versions(const X86CPUDefinition *def) 1648 { 1649 /* When X86CPUDefinition::versions is NULL, we register only v1 */ 1650 static const X86CPUVersionDefinition default_version_list[] = { 1651 { 1 }, 1652 { /* end of list */ } 1653 }; 1654 1655 return def->versions ?: default_version_list; 1656 } 1657 1658 static const CPUCaches epyc_cache_info = { 1659 .l1d_cache = &(CPUCacheInfo) { 1660 .type = DATA_CACHE, 1661 .level = 1, 1662 .size = 32 * KiB, 1663 .line_size = 64, 1664 .associativity = 8, 1665 .partitions = 1, 1666 .sets = 64, 1667 .lines_per_tag = 1, 1668 .self_init = 1, 1669 .no_invd_sharing = true, 1670 }, 1671 .l1i_cache = &(CPUCacheInfo) { 1672 .type = INSTRUCTION_CACHE, 1673 .level = 1, 1674 .size = 64 * KiB, 1675 .line_size = 64, 1676 .associativity = 4, 1677 .partitions = 1, 1678 .sets = 256, 1679 .lines_per_tag = 1, 1680 .self_init = 1, 1681 .no_invd_sharing = true, 1682 }, 1683 .l2_cache = &(CPUCacheInfo) { 1684 .type = UNIFIED_CACHE, 1685 .level = 2, 1686 .size = 512 * KiB, 1687 .line_size = 64, 1688 .associativity = 8, 1689 .partitions = 1, 1690 .sets = 1024, 1691 .lines_per_tag = 1, 1692 }, 1693 .l3_cache = &(CPUCacheInfo) { 1694 .type = UNIFIED_CACHE, 1695 .level = 3, 1696 .size = 8 * MiB, 1697 .line_size = 64, 1698 .associativity = 16, 1699 .partitions = 1, 1700 .sets = 8192, 1701 .lines_per_tag = 1, 1702 .self_init = true, 1703 .inclusive = true, 1704 .complex_indexing = true, 1705 }, 1706 }; 1707 1708 static const CPUCaches epyc_rome_cache_info = { 1709 .l1d_cache = &(CPUCacheInfo) { 1710 .type = DATA_CACHE, 1711 .level = 1, 1712 .size = 32 * KiB, 1713 .line_size = 64, 1714 .associativity = 8, 1715 .partitions = 1, 1716 .sets = 64, 1717 .lines_per_tag = 1, 1718 .self_init = 1, 1719 .no_invd_sharing = true, 1720 }, 1721 .l1i_cache = &(CPUCacheInfo) { 1722 .type = INSTRUCTION_CACHE, 1723 .level = 1, 1724 .size = 32 * KiB, 1725 .line_size = 64, 1726 .associativity = 8, 1727 .partitions = 1, 1728 .sets = 64, 1729 .lines_per_tag = 1, 1730 .self_init = 1, 1731 .no_invd_sharing = true, 1732 }, 1733 .l2_cache = &(CPUCacheInfo) { 1734 .type = UNIFIED_CACHE, 1735 .level = 2, 1736 .size = 512 * KiB, 1737 .line_size = 64, 1738 .associativity = 8, 1739 .partitions = 1, 1740 .sets = 1024, 1741 .lines_per_tag = 1, 1742 }, 1743 .l3_cache = &(CPUCacheInfo) { 1744 .type = UNIFIED_CACHE, 1745 .level = 3, 1746 .size = 16 * MiB, 1747 .line_size = 64, 1748 .associativity = 16, 1749 .partitions = 1, 1750 .sets = 16384, 1751 .lines_per_tag = 1, 1752 .self_init = true, 1753 .inclusive = true, 1754 .complex_indexing = true, 1755 }, 1756 }; 1757 1758 static const CPUCaches epyc_milan_cache_info = { 1759 .l1d_cache = &(CPUCacheInfo) { 1760 .type = DATA_CACHE, 1761 .level = 1, 1762 .size = 32 * KiB, 1763 .line_size = 64, 1764 .associativity = 8, 1765 .partitions = 1, 1766 .sets = 64, 1767 .lines_per_tag = 1, 1768 .self_init = 1, 1769 .no_invd_sharing = true, 1770 }, 1771 .l1i_cache = &(CPUCacheInfo) { 1772 .type = INSTRUCTION_CACHE, 1773 .level = 1, 1774 .size = 32 * KiB, 1775 .line_size = 64, 1776 .associativity = 8, 1777 .partitions = 1, 1778 .sets = 64, 1779 .lines_per_tag = 1, 1780 .self_init = 1, 1781 .no_invd_sharing = true, 1782 }, 1783 .l2_cache = &(CPUCacheInfo) { 1784 .type = UNIFIED_CACHE, 1785 .level = 2, 1786 .size = 512 * KiB, 1787 .line_size = 64, 1788 .associativity = 8, 1789 .partitions = 1, 1790 .sets = 1024, 1791 .lines_per_tag = 1, 1792 }, 1793 .l3_cache = &(CPUCacheInfo) { 1794 .type = UNIFIED_CACHE, 1795 .level = 3, 1796 .size = 32 * MiB, 1797 .line_size = 64, 1798 .associativity = 16, 1799 .partitions = 1, 1800 .sets = 32768, 1801 .lines_per_tag = 1, 1802 .self_init = true, 1803 .inclusive = true, 1804 .complex_indexing = true, 1805 }, 1806 }; 1807 1808 /* The following VMX features are not supported by KVM and are left out in the 1809 * CPU definitions: 1810 * 1811 * Dual-monitor support (all processors) 1812 * Entry to SMM 1813 * Deactivate dual-monitor treatment 1814 * Number of CR3-target values 1815 * Shutdown activity state 1816 * Wait-for-SIPI activity state 1817 * PAUSE-loop exiting (Westmere and newer) 1818 * EPT-violation #VE (Broadwell and newer) 1819 * Inject event with insn length=0 (Skylake and newer) 1820 * Conceal non-root operation from PT 1821 * Conceal VM exits from PT 1822 * Conceal VM entries from PT 1823 * Enable ENCLS exiting 1824 * Mode-based execute control (XS/XU) 1825 s TSC scaling (Skylake Server and newer) 1826 * GPA translation for PT (IceLake and newer) 1827 * User wait and pause 1828 * ENCLV exiting 1829 * Load IA32_RTIT_CTL 1830 * Clear IA32_RTIT_CTL 1831 * Advanced VM-exit information for EPT violations 1832 * Sub-page write permissions 1833 * PT in VMX operation 1834 */ 1835 1836 static const X86CPUDefinition builtin_x86_defs[] = { 1837 { 1838 .name = "qemu64", 1839 .level = 0xd, 1840 .vendor = CPUID_VENDOR_AMD, 1841 .family = 15, 1842 .model = 107, 1843 .stepping = 1, 1844 .features[FEAT_1_EDX] = 1845 PPRO_FEATURES | 1846 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1847 CPUID_PSE36, 1848 .features[FEAT_1_ECX] = 1849 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1850 .features[FEAT_8000_0001_EDX] = 1851 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1852 .features[FEAT_8000_0001_ECX] = 1853 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM, 1854 .xlevel = 0x8000000A, 1855 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1856 }, 1857 { 1858 .name = "phenom", 1859 .level = 5, 1860 .vendor = CPUID_VENDOR_AMD, 1861 .family = 16, 1862 .model = 2, 1863 .stepping = 3, 1864 /* Missing: CPUID_HT */ 1865 .features[FEAT_1_EDX] = 1866 PPRO_FEATURES | 1867 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1868 CPUID_PSE36 | CPUID_VME, 1869 .features[FEAT_1_ECX] = 1870 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | 1871 CPUID_EXT_POPCNT, 1872 .features[FEAT_8000_0001_EDX] = 1873 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | 1874 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | 1875 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, 1876 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1877 CPUID_EXT3_CR8LEG, 1878 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1879 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ 1880 .features[FEAT_8000_0001_ECX] = 1881 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | 1882 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, 1883 /* Missing: CPUID_SVM_LBRV */ 1884 .features[FEAT_SVM] = 1885 CPUID_SVM_NPT, 1886 .xlevel = 0x8000001A, 1887 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" 1888 }, 1889 { 1890 .name = "core2duo", 1891 .level = 10, 1892 .vendor = CPUID_VENDOR_INTEL, 1893 .family = 6, 1894 .model = 15, 1895 .stepping = 11, 1896 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 1897 .features[FEAT_1_EDX] = 1898 PPRO_FEATURES | 1899 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1900 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, 1901 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, 1902 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ 1903 .features[FEAT_1_ECX] = 1904 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 1905 CPUID_EXT_CX16, 1906 .features[FEAT_8000_0001_EDX] = 1907 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1908 .features[FEAT_8000_0001_ECX] = 1909 CPUID_EXT3_LAHF_LM, 1910 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 1911 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1912 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1913 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1914 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1915 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 1916 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1917 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1918 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1919 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1920 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1921 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1922 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1923 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 1924 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 1925 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 1926 .features[FEAT_VMX_SECONDARY_CTLS] = 1927 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 1928 .xlevel = 0x80000008, 1929 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", 1930 }, 1931 { 1932 .name = "kvm64", 1933 .level = 0xd, 1934 .vendor = CPUID_VENDOR_INTEL, 1935 .family = 15, 1936 .model = 6, 1937 .stepping = 1, 1938 /* Missing: CPUID_HT */ 1939 .features[FEAT_1_EDX] = 1940 PPRO_FEATURES | CPUID_VME | 1941 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | 1942 CPUID_PSE36, 1943 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ 1944 .features[FEAT_1_ECX] = 1945 CPUID_EXT_SSE3 | CPUID_EXT_CX16, 1946 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ 1947 .features[FEAT_8000_0001_EDX] = 1948 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 1949 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, 1950 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A, 1951 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, 1952 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ 1953 .features[FEAT_8000_0001_ECX] = 1954 0, 1955 /* VMX features from Cedar Mill/Prescott */ 1956 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 1957 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 1958 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 1959 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 1960 VMX_PIN_BASED_NMI_EXITING, 1961 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 1962 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 1963 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 1964 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 1965 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 1966 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 1967 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 1968 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING, 1969 .xlevel = 0x80000008, 1970 .model_id = "Common KVM processor" 1971 }, 1972 { 1973 .name = "qemu32", 1974 .level = 4, 1975 .vendor = CPUID_VENDOR_INTEL, 1976 .family = 6, 1977 .model = 6, 1978 .stepping = 3, 1979 .features[FEAT_1_EDX] = 1980 PPRO_FEATURES, 1981 .features[FEAT_1_ECX] = 1982 CPUID_EXT_SSE3, 1983 .xlevel = 0x80000004, 1984 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 1985 }, 1986 { 1987 .name = "kvm32", 1988 .level = 5, 1989 .vendor = CPUID_VENDOR_INTEL, 1990 .family = 15, 1991 .model = 6, 1992 .stepping = 1, 1993 .features[FEAT_1_EDX] = 1994 PPRO_FEATURES | CPUID_VME | 1995 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, 1996 .features[FEAT_1_ECX] = 1997 CPUID_EXT_SSE3, 1998 .features[FEAT_8000_0001_ECX] = 1999 0, 2000 /* VMX features from Yonah */ 2001 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2002 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2003 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2004 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2005 VMX_PIN_BASED_NMI_EXITING, 2006 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2007 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2008 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2009 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2010 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2011 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2012 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2013 .xlevel = 0x80000008, 2014 .model_id = "Common 32-bit KVM processor" 2015 }, 2016 { 2017 .name = "coreduo", 2018 .level = 10, 2019 .vendor = CPUID_VENDOR_INTEL, 2020 .family = 6, 2021 .model = 14, 2022 .stepping = 8, 2023 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2024 .features[FEAT_1_EDX] = 2025 PPRO_FEATURES | CPUID_VME | 2026 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | 2027 CPUID_SS, 2028 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, 2029 * CPUID_EXT_PDCM, CPUID_EXT_VMX */ 2030 .features[FEAT_1_ECX] = 2031 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, 2032 .features[FEAT_8000_0001_EDX] = 2033 CPUID_EXT2_NX, 2034 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2035 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2036 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2037 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2038 VMX_PIN_BASED_NMI_EXITING, 2039 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2040 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2041 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2042 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2043 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING | 2044 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | 2045 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS, 2046 .xlevel = 0x80000008, 2047 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz", 2048 }, 2049 { 2050 .name = "486", 2051 .level = 1, 2052 .vendor = CPUID_VENDOR_INTEL, 2053 .family = 4, 2054 .model = 8, 2055 .stepping = 0, 2056 .features[FEAT_1_EDX] = 2057 I486_FEATURES, 2058 .xlevel = 0, 2059 .model_id = "", 2060 }, 2061 { 2062 .name = "pentium", 2063 .level = 1, 2064 .vendor = CPUID_VENDOR_INTEL, 2065 .family = 5, 2066 .model = 4, 2067 .stepping = 3, 2068 .features[FEAT_1_EDX] = 2069 PENTIUM_FEATURES, 2070 .xlevel = 0, 2071 .model_id = "", 2072 }, 2073 { 2074 .name = "pentium2", 2075 .level = 2, 2076 .vendor = CPUID_VENDOR_INTEL, 2077 .family = 6, 2078 .model = 5, 2079 .stepping = 2, 2080 .features[FEAT_1_EDX] = 2081 PENTIUM2_FEATURES, 2082 .xlevel = 0, 2083 .model_id = "", 2084 }, 2085 { 2086 .name = "pentium3", 2087 .level = 3, 2088 .vendor = CPUID_VENDOR_INTEL, 2089 .family = 6, 2090 .model = 7, 2091 .stepping = 3, 2092 .features[FEAT_1_EDX] = 2093 PENTIUM3_FEATURES, 2094 .xlevel = 0, 2095 .model_id = "", 2096 }, 2097 { 2098 /* http://users.atw.hu/instlatx64/AuthenticAMD/AuthenticAMD0000F4A_K8_Clawhammer_CPUID.txt */ 2099 .name = "athlon-64", 2100 .level = 1, 2101 .vendor = CPUID_VENDOR_AMD, 2102 .family = 15, 2103 .model = 4, 2104 .stepping = 10, 2105 .features[FEAT_1_EDX] = 2106 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 2107 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 2108 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 2109 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 2110 CPUID_PAT | CPUID_PSE36 | /*no: CPUID_PN |*/ CPUID_CLFLUSH | 2111 /*no: CPUID_DTS | CPUID_ACPI |*/ CPUID_MMX | 2112 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 2113 .features[FEAT_8000_0001_EDX] = 2114 (CPUID_EXT2_FPU | CPUID_EXT2_VME | CPUID_EXT2_DE | CPUID_EXT2_PSE | 2115 CPUID_EXT2_TSC | CPUID_EXT2_MSR | CPUID_EXT2_PAE | CPUID_EXT2_MCE | 2116 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | CPUID_EXT2_SYSCALL | 2117 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | CPUID_EXT2_MCA | CPUID_EXT2_CMOV | 2118 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | /*no: CPUID_EXT2_MP */ 2119 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_MMX | 2120 CPUID_EXT2_FXSR | /*no: CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1G | CPUID_EXT2_RTDSCP*/ 2121 CPUID_EXT2_LM | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_3DNOW) & 2122 ~CPUID_EXT2_AMD_ALIASES, 2123 /* todo cache info 0x80000005-6 */ 2124 .features[FEAT_8000_0007_EDX] = 0x0f, /*??*/ 2125 /*.phys_bits = 0x00003028,*/ 2126 .xlevel = 0x80000018, 2127 .brand_id = 0x106, 2128 .model_id = "AMD Athlon(tm) 64 Processor 2800+", 2129 }, 2130 { 2131 .name = "u3-64bit-minimal", 2132 .level = 1, 2133 .vendor = CPUID_VENDOR_AMD, 2134 .family = 15, 2135 .model = 4, 2136 .stepping = 10, 2137 .features[FEAT_1_EDX] = 2138 PENTIUM2_FEATURES | PPRO_FEATURES | CPUID_CLFLUSH /*sse2?*/, 2139 .features[FEAT_8000_0001_EDX] = 2140 /* NX: amd: since amd64, intel: P4 Prescott+ */ 2141 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_LM, 2142 .xlevel = 0x80000018, 2143 .model_id = "Fuck off", 2144 }, 2145 { 2146 .name = "athlon", 2147 .level = 2, 2148 .vendor = CPUID_VENDOR_AMD, 2149 .family = 6, 2150 .model = 2, 2151 .stepping = 3, 2152 .features[FEAT_1_EDX] = 2153 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | 2154 CPUID_MCA, 2155 .features[FEAT_8000_0001_EDX] = 2156 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, 2157 .xlevel = 0x80000008, 2158 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION, 2159 }, 2160 { 2161 .name = "n270", 2162 .level = 10, 2163 .vendor = CPUID_VENDOR_INTEL, 2164 .family = 6, 2165 .model = 28, 2166 .stepping = 2, 2167 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 2168 .features[FEAT_1_EDX] = 2169 PPRO_FEATURES | 2170 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | 2171 CPUID_ACPI | CPUID_SS, 2172 /* Some CPUs got no CPUID_SEP */ 2173 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, 2174 * CPUID_EXT_XTPR */ 2175 .features[FEAT_1_ECX] = 2176 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | 2177 CPUID_EXT_MOVBE, 2178 .features[FEAT_8000_0001_EDX] = 2179 CPUID_EXT2_NX, 2180 .features[FEAT_8000_0001_ECX] = 2181 CPUID_EXT3_LAHF_LM, 2182 .xlevel = 0x80000008, 2183 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", 2184 }, 2185 { 2186 .name = "Conroe", 2187 .level = 10, 2188 .vendor = CPUID_VENDOR_INTEL, 2189 .family = 6, 2190 .model = 15, 2191 .stepping = 3, 2192 .features[FEAT_1_EDX] = 2193 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2194 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2195 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2196 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2197 CPUID_DE | CPUID_FP87, 2198 .features[FEAT_1_ECX] = 2199 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2200 .features[FEAT_8000_0001_EDX] = 2201 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2202 .features[FEAT_8000_0001_ECX] = 2203 CPUID_EXT3_LAHF_LM, 2204 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2205 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE, 2206 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT, 2207 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2208 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2209 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2210 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2211 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2212 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2213 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2214 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2215 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2216 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2217 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2218 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2219 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2220 .features[FEAT_VMX_SECONDARY_CTLS] = 2221 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES, 2222 .xlevel = 0x80000008, 2223 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", 2224 }, 2225 { 2226 .name = "Penryn", 2227 .level = 10, 2228 .vendor = CPUID_VENDOR_INTEL, 2229 .family = 6, 2230 .model = 23, 2231 .stepping = 3, 2232 .features[FEAT_1_EDX] = 2233 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2234 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2235 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2236 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2237 CPUID_DE | CPUID_FP87, 2238 .features[FEAT_1_ECX] = 2239 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2240 CPUID_EXT_SSE3, 2241 .features[FEAT_8000_0001_EDX] = 2242 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 2243 .features[FEAT_8000_0001_ECX] = 2244 CPUID_EXT3_LAHF_LM, 2245 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS, 2246 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2247 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 2248 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT | 2249 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 2250 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2251 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2252 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS, 2253 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2254 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2255 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2256 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2257 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2258 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2259 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2260 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2261 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2262 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2263 .features[FEAT_VMX_SECONDARY_CTLS] = 2264 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2265 VMX_SECONDARY_EXEC_WBINVD_EXITING, 2266 .xlevel = 0x80000008, 2267 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", 2268 }, 2269 { 2270 .name = "Nehalem", 2271 .level = 11, 2272 .vendor = CPUID_VENDOR_INTEL, 2273 .family = 6, 2274 .model = 26, 2275 .stepping = 3, 2276 .features[FEAT_1_EDX] = 2277 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2278 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2279 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2280 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2281 CPUID_DE | CPUID_FP87, 2282 .features[FEAT_1_ECX] = 2283 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2284 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, 2285 .features[FEAT_8000_0001_EDX] = 2286 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2287 .features[FEAT_8000_0001_ECX] = 2288 CPUID_EXT3_LAHF_LM, 2289 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2290 MSR_VMX_BASIC_TRUE_CTLS, 2291 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2292 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2293 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2294 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2295 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2296 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2297 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2298 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2299 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2300 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2301 .features[FEAT_VMX_EXIT_CTLS] = 2302 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2303 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2304 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2305 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2306 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2307 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT, 2308 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2309 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2310 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2311 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2312 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2313 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2314 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2315 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2316 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2317 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2318 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2319 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2320 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2321 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2322 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2323 .features[FEAT_VMX_SECONDARY_CTLS] = 2324 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2325 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2326 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2327 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2328 VMX_SECONDARY_EXEC_ENABLE_VPID, 2329 .xlevel = 0x80000008, 2330 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)", 2331 .versions = (X86CPUVersionDefinition[]) { 2332 { .version = 1 }, 2333 { 2334 .version = 2, 2335 .alias = "Nehalem-IBRS", 2336 .props = (PropValue[]) { 2337 { "spec-ctrl", "on" }, 2338 { "model-id", 2339 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" }, 2340 { /* end of list */ } 2341 } 2342 }, 2343 { /* end of list */ } 2344 } 2345 }, 2346 { 2347 .name = "Westmere", 2348 .level = 11, 2349 .vendor = CPUID_VENDOR_INTEL, 2350 .family = 6, 2351 .model = 44, 2352 .stepping = 1, 2353 .features[FEAT_1_EDX] = 2354 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2355 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2356 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2357 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2358 CPUID_DE | CPUID_FP87, 2359 .features[FEAT_1_ECX] = 2360 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 2361 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2362 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 2363 .features[FEAT_8000_0001_EDX] = 2364 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, 2365 .features[FEAT_8000_0001_ECX] = 2366 CPUID_EXT3_LAHF_LM, 2367 .features[FEAT_6_EAX] = 2368 CPUID_6_EAX_ARAT, 2369 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2370 MSR_VMX_BASIC_TRUE_CTLS, 2371 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2372 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2373 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2374 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2375 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2376 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2377 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2378 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2379 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2380 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2381 .features[FEAT_VMX_EXIT_CTLS] = 2382 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2383 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2384 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2385 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2386 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2387 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2388 MSR_VMX_MISC_STORE_LMA, 2389 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2390 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2391 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2392 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2393 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2394 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2395 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2396 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2397 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2398 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2399 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2400 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2401 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2402 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2403 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2404 .features[FEAT_VMX_SECONDARY_CTLS] = 2405 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2406 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2407 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2408 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2409 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2410 .xlevel = 0x80000008, 2411 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)", 2412 .versions = (X86CPUVersionDefinition[]) { 2413 { .version = 1 }, 2414 { 2415 .version = 2, 2416 .alias = "Westmere-IBRS", 2417 .props = (PropValue[]) { 2418 { "spec-ctrl", "on" }, 2419 { "model-id", 2420 "Westmere E56xx/L56xx/X56xx (IBRS update)" }, 2421 { /* end of list */ } 2422 } 2423 }, 2424 { /* end of list */ } 2425 } 2426 }, 2427 { 2428 .name = "SandyBridge", 2429 .level = 0xd, 2430 .vendor = CPUID_VENDOR_INTEL, 2431 .family = 6, 2432 .model = 42, 2433 .stepping = 1, 2434 .features[FEAT_1_EDX] = 2435 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2436 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2437 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2438 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2439 CPUID_DE | CPUID_FP87, 2440 .features[FEAT_1_ECX] = 2441 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2442 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2443 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2444 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2445 CPUID_EXT_SSE3, 2446 .features[FEAT_8000_0001_EDX] = 2447 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2448 CPUID_EXT2_SYSCALL, 2449 .features[FEAT_8000_0001_ECX] = 2450 CPUID_EXT3_LAHF_LM, 2451 .features[FEAT_XSAVE] = 2452 CPUID_XSAVE_XSAVEOPT, 2453 .features[FEAT_6_EAX] = 2454 CPUID_6_EAX_ARAT, 2455 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2456 MSR_VMX_BASIC_TRUE_CTLS, 2457 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2458 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2459 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2460 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2461 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2462 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2463 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2464 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2465 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2466 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2467 .features[FEAT_VMX_EXIT_CTLS] = 2468 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2469 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2470 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2471 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2472 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2473 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2474 MSR_VMX_MISC_STORE_LMA, 2475 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2476 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2477 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2478 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2479 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2480 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2481 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2482 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2483 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2484 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2485 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2486 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2487 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2488 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2489 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2490 .features[FEAT_VMX_SECONDARY_CTLS] = 2491 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2492 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2493 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2494 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2495 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST, 2496 .xlevel = 0x80000008, 2497 .model_id = "Intel Xeon E312xx (Sandy Bridge)", 2498 .versions = (X86CPUVersionDefinition[]) { 2499 { .version = 1 }, 2500 { 2501 .version = 2, 2502 .alias = "SandyBridge-IBRS", 2503 .props = (PropValue[]) { 2504 { "spec-ctrl", "on" }, 2505 { "model-id", 2506 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" }, 2507 { /* end of list */ } 2508 } 2509 }, 2510 { /* end of list */ } 2511 } 2512 }, 2513 { 2514 .name = "IvyBridge", 2515 .level = 0xd, 2516 .vendor = CPUID_VENDOR_INTEL, 2517 .family = 6, 2518 .model = 58, 2519 .stepping = 9, 2520 .features[FEAT_1_EDX] = 2521 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2522 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2523 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2524 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2525 CPUID_DE | CPUID_FP87, 2526 .features[FEAT_1_ECX] = 2527 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2528 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT | 2529 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 2530 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 2531 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2532 .features[FEAT_7_0_EBX] = 2533 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | 2534 CPUID_7_0_EBX_ERMS, 2535 .features[FEAT_8000_0001_EDX] = 2536 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2537 CPUID_EXT2_SYSCALL, 2538 .features[FEAT_8000_0001_ECX] = 2539 CPUID_EXT3_LAHF_LM, 2540 .features[FEAT_XSAVE] = 2541 CPUID_XSAVE_XSAVEOPT, 2542 .features[FEAT_6_EAX] = 2543 CPUID_6_EAX_ARAT, 2544 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2545 MSR_VMX_BASIC_TRUE_CTLS, 2546 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2547 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2548 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2549 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2550 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2551 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2552 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2553 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2554 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2555 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, 2556 .features[FEAT_VMX_EXIT_CTLS] = 2557 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2558 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2559 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2560 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2561 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2562 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2563 MSR_VMX_MISC_STORE_LMA, 2564 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2565 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2566 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2567 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2568 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2569 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2570 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2571 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2572 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2573 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2574 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2575 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2576 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2577 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2578 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2579 .features[FEAT_VMX_SECONDARY_CTLS] = 2580 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2581 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2582 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2583 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2584 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2585 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2586 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2587 VMX_SECONDARY_EXEC_RDRAND_EXITING, 2588 .xlevel = 0x80000008, 2589 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)", 2590 .versions = (X86CPUVersionDefinition[]) { 2591 { .version = 1 }, 2592 { 2593 .version = 2, 2594 .alias = "IvyBridge-IBRS", 2595 .props = (PropValue[]) { 2596 { "spec-ctrl", "on" }, 2597 { "model-id", 2598 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" }, 2599 { /* end of list */ } 2600 } 2601 }, 2602 { /* end of list */ } 2603 } 2604 }, 2605 { 2606 .name = "Haswell", 2607 .level = 0xd, 2608 .vendor = CPUID_VENDOR_INTEL, 2609 .family = 6, 2610 .model = 60, 2611 .stepping = 4, 2612 .features[FEAT_1_EDX] = 2613 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2614 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2615 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2616 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2617 CPUID_DE | CPUID_FP87, 2618 .features[FEAT_1_ECX] = 2619 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2620 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2621 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2622 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2623 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2624 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2625 .features[FEAT_8000_0001_EDX] = 2626 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2627 CPUID_EXT2_SYSCALL, 2628 .features[FEAT_8000_0001_ECX] = 2629 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM, 2630 .features[FEAT_7_0_EBX] = 2631 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2632 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2633 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2634 CPUID_7_0_EBX_RTM, 2635 .features[FEAT_XSAVE] = 2636 CPUID_XSAVE_XSAVEOPT, 2637 .features[FEAT_6_EAX] = 2638 CPUID_6_EAX_ARAT, 2639 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2640 MSR_VMX_BASIC_TRUE_CTLS, 2641 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2642 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2643 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2644 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2645 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2646 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2647 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2648 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2649 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2650 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2651 .features[FEAT_VMX_EXIT_CTLS] = 2652 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2653 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2654 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2655 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2656 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2657 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2658 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2659 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2660 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2661 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2662 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2663 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2664 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2665 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2666 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2667 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2668 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2669 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2670 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2671 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2672 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2673 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2674 .features[FEAT_VMX_SECONDARY_CTLS] = 2675 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2676 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2677 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2678 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2679 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2680 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2681 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2682 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2683 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 2684 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2685 .xlevel = 0x80000008, 2686 .model_id = "Intel Core Processor (Haswell)", 2687 .versions = (X86CPUVersionDefinition[]) { 2688 { .version = 1 }, 2689 { 2690 .version = 2, 2691 .alias = "Haswell-noTSX", 2692 .props = (PropValue[]) { 2693 { "hle", "off" }, 2694 { "rtm", "off" }, 2695 { "stepping", "1" }, 2696 { "model-id", "Intel Core Processor (Haswell, no TSX)", }, 2697 { /* end of list */ } 2698 }, 2699 }, 2700 { 2701 .version = 3, 2702 .alias = "Haswell-IBRS", 2703 .props = (PropValue[]) { 2704 /* Restore TSX features removed by -v2 above */ 2705 { "hle", "on" }, 2706 { "rtm", "on" }, 2707 /* 2708 * Haswell and Haswell-IBRS had stepping=4 in 2709 * QEMU 4.0 and older 2710 */ 2711 { "stepping", "4" }, 2712 { "spec-ctrl", "on" }, 2713 { "model-id", 2714 "Intel Core Processor (Haswell, IBRS)" }, 2715 { /* end of list */ } 2716 } 2717 }, 2718 { 2719 .version = 4, 2720 .alias = "Haswell-noTSX-IBRS", 2721 .props = (PropValue[]) { 2722 { "hle", "off" }, 2723 { "rtm", "off" }, 2724 /* spec-ctrl was already enabled by -v3 above */ 2725 { "stepping", "1" }, 2726 { "model-id", 2727 "Intel Core Processor (Haswell, no TSX, IBRS)" }, 2728 { /* end of list */ } 2729 } 2730 }, 2731 { /* end of list */ } 2732 } 2733 }, 2734 { 2735 .name = "Broadwell", 2736 .level = 0xd, 2737 .vendor = CPUID_VENDOR_INTEL, 2738 .family = 6, 2739 .model = 61, 2740 .stepping = 2, 2741 .features[FEAT_1_EDX] = 2742 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2743 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2744 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2745 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2746 CPUID_DE | CPUID_FP87, 2747 .features[FEAT_1_ECX] = 2748 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2749 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2750 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2751 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2752 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2753 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2754 .features[FEAT_8000_0001_EDX] = 2755 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2756 CPUID_EXT2_SYSCALL, 2757 .features[FEAT_8000_0001_ECX] = 2758 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2759 .features[FEAT_7_0_EBX] = 2760 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2761 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2762 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2763 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2764 CPUID_7_0_EBX_SMAP, 2765 .features[FEAT_XSAVE] = 2766 CPUID_XSAVE_XSAVEOPT, 2767 .features[FEAT_6_EAX] = 2768 CPUID_6_EAX_ARAT, 2769 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2770 MSR_VMX_BASIC_TRUE_CTLS, 2771 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2772 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2773 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2774 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2775 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2776 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2777 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2778 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2779 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2780 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2781 .features[FEAT_VMX_EXIT_CTLS] = 2782 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2783 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2784 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2785 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2786 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2787 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2788 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2789 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2790 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2791 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 2792 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2793 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2794 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2795 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2796 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2797 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2798 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2799 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2800 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2801 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2802 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2803 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2804 .features[FEAT_VMX_SECONDARY_CTLS] = 2805 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2806 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2807 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2808 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2809 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2810 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 2811 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2812 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2813 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2814 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2815 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2816 .xlevel = 0x80000008, 2817 .model_id = "Intel Core Processor (Broadwell)", 2818 .versions = (X86CPUVersionDefinition[]) { 2819 { .version = 1 }, 2820 { 2821 .version = 2, 2822 .alias = "Broadwell-noTSX", 2823 .props = (PropValue[]) { 2824 { "hle", "off" }, 2825 { "rtm", "off" }, 2826 { "model-id", "Intel Core Processor (Broadwell, no TSX)", }, 2827 { /* end of list */ } 2828 }, 2829 }, 2830 { 2831 .version = 3, 2832 .alias = "Broadwell-IBRS", 2833 .props = (PropValue[]) { 2834 /* Restore TSX features removed by -v2 above */ 2835 { "hle", "on" }, 2836 { "rtm", "on" }, 2837 { "spec-ctrl", "on" }, 2838 { "model-id", 2839 "Intel Core Processor (Broadwell, IBRS)" }, 2840 { /* end of list */ } 2841 } 2842 }, 2843 { 2844 .version = 4, 2845 .alias = "Broadwell-noTSX-IBRS", 2846 .props = (PropValue[]) { 2847 { "hle", "off" }, 2848 { "rtm", "off" }, 2849 /* spec-ctrl was already enabled by -v3 above */ 2850 { "model-id", 2851 "Intel Core Processor (Broadwell, no TSX, IBRS)" }, 2852 { /* end of list */ } 2853 } 2854 }, 2855 { /* end of list */ } 2856 } 2857 }, 2858 { 2859 .name = "Skylake-Client", 2860 .level = 0xd, 2861 .vendor = CPUID_VENDOR_INTEL, 2862 .family = 6, 2863 .model = 94, 2864 .stepping = 3, 2865 .features[FEAT_1_EDX] = 2866 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2867 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2868 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2869 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2870 CPUID_DE | CPUID_FP87, 2871 .features[FEAT_1_ECX] = 2872 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2873 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2874 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2875 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2876 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2877 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2878 .features[FEAT_8000_0001_EDX] = 2879 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | 2880 CPUID_EXT2_SYSCALL, 2881 .features[FEAT_8000_0001_ECX] = 2882 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 2883 .features[FEAT_7_0_EBX] = 2884 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 2885 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 2886 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 2887 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 2888 CPUID_7_0_EBX_SMAP, 2889 /* XSAVES is added in version 4 */ 2890 .features[FEAT_XSAVE] = 2891 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 2892 CPUID_XSAVE_XGETBV1, 2893 .features[FEAT_6_EAX] = 2894 CPUID_6_EAX_ARAT, 2895 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 2896 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 2897 MSR_VMX_BASIC_TRUE_CTLS, 2898 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 2899 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 2900 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 2901 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 2902 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 2903 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 2904 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 2905 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 2906 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 2907 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 2908 .features[FEAT_VMX_EXIT_CTLS] = 2909 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 2910 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2911 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 2912 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 2913 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 2914 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 2915 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 2916 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 2917 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 2918 VMX_PIN_BASED_VMX_PREEMPTION_TIMER, 2919 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 2920 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 2921 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 2922 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 2923 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 2924 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 2925 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 2926 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 2927 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 2928 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 2929 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 2930 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 2931 .features[FEAT_VMX_SECONDARY_CTLS] = 2932 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2933 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 2934 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 2935 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 2936 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 2937 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 2938 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 2939 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 2940 .xlevel = 0x80000008, 2941 .model_id = "Intel Core Processor (Skylake)", 2942 .versions = (X86CPUVersionDefinition[]) { 2943 { .version = 1 }, 2944 { 2945 .version = 2, 2946 .alias = "Skylake-Client-IBRS", 2947 .props = (PropValue[]) { 2948 { "spec-ctrl", "on" }, 2949 { "model-id", 2950 "Intel Core Processor (Skylake, IBRS)" }, 2951 { /* end of list */ } 2952 } 2953 }, 2954 { 2955 .version = 3, 2956 .alias = "Skylake-Client-noTSX-IBRS", 2957 .props = (PropValue[]) { 2958 { "hle", "off" }, 2959 { "rtm", "off" }, 2960 { "model-id", 2961 "Intel Core Processor (Skylake, IBRS, no TSX)" }, 2962 { /* end of list */ } 2963 } 2964 }, 2965 { 2966 .version = 4, 2967 .note = "IBRS, XSAVES, no TSX", 2968 .props = (PropValue[]) { 2969 { "xsaves", "on" }, 2970 { "vmx-xsaves", "on" }, 2971 { /* end of list */ } 2972 } 2973 }, 2974 { /* end of list */ } 2975 } 2976 }, 2977 { 2978 .name = "Skylake-Server", 2979 .level = 0xd, 2980 .vendor = CPUID_VENDOR_INTEL, 2981 .family = 6, 2982 .model = 85, 2983 .stepping = 4, 2984 .features[FEAT_1_EDX] = 2985 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 2986 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 2987 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 2988 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 2989 CPUID_DE | CPUID_FP87, 2990 .features[FEAT_1_ECX] = 2991 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 2992 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 2993 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 2994 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 2995 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 2996 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 2997 .features[FEAT_8000_0001_EDX] = 2998 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 2999 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3000 .features[FEAT_8000_0001_ECX] = 3001 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3002 .features[FEAT_7_0_EBX] = 3003 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3004 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3005 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3006 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3007 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3008 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3009 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3010 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3011 .features[FEAT_7_0_ECX] = 3012 CPUID_7_0_ECX_PKU, 3013 /* XSAVES is added in version 5 */ 3014 .features[FEAT_XSAVE] = 3015 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3016 CPUID_XSAVE_XGETBV1, 3017 .features[FEAT_6_EAX] = 3018 CPUID_6_EAX_ARAT, 3019 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3020 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3021 MSR_VMX_BASIC_TRUE_CTLS, 3022 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3023 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3024 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3025 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3026 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3027 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3028 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3029 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3030 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3031 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3032 .features[FEAT_VMX_EXIT_CTLS] = 3033 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3034 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3035 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3036 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3037 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3038 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3039 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3040 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3041 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3042 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3043 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3044 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3045 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3046 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3047 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3048 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3049 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3050 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3051 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3052 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3053 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3054 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3055 .features[FEAT_VMX_SECONDARY_CTLS] = 3056 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3057 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3058 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3059 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3060 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3061 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3062 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3063 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3064 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3065 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3066 .xlevel = 0x80000008, 3067 .model_id = "Intel Xeon Processor (Skylake)", 3068 .versions = (X86CPUVersionDefinition[]) { 3069 { .version = 1 }, 3070 { 3071 .version = 2, 3072 .alias = "Skylake-Server-IBRS", 3073 .props = (PropValue[]) { 3074 /* clflushopt was not added to Skylake-Server-IBRS */ 3075 /* TODO: add -v3 including clflushopt */ 3076 { "clflushopt", "off" }, 3077 { "spec-ctrl", "on" }, 3078 { "model-id", 3079 "Intel Xeon Processor (Skylake, IBRS)" }, 3080 { /* end of list */ } 3081 } 3082 }, 3083 { 3084 .version = 3, 3085 .alias = "Skylake-Server-noTSX-IBRS", 3086 .props = (PropValue[]) { 3087 { "hle", "off" }, 3088 { "rtm", "off" }, 3089 { "model-id", 3090 "Intel Xeon Processor (Skylake, IBRS, no TSX)" }, 3091 { /* end of list */ } 3092 } 3093 }, 3094 { 3095 .version = 4, 3096 .props = (PropValue[]) { 3097 { "vmx-eptp-switching", "on" }, 3098 { /* end of list */ } 3099 } 3100 }, 3101 { 3102 .version = 5, 3103 .note = "IBRS, XSAVES, EPT switching, no TSX", 3104 .props = (PropValue[]) { 3105 { "xsaves", "on" }, 3106 { "vmx-xsaves", "on" }, 3107 { /* end of list */ } 3108 } 3109 }, 3110 { /* end of list */ } 3111 } 3112 }, 3113 { 3114 .name = "Cascadelake-Server", 3115 .level = 0xd, 3116 .vendor = CPUID_VENDOR_INTEL, 3117 .family = 6, 3118 .model = 85, 3119 .stepping = 6, 3120 .features[FEAT_1_EDX] = 3121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3125 CPUID_DE | CPUID_FP87, 3126 .features[FEAT_1_ECX] = 3127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3128 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3129 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3130 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3131 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3132 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3133 .features[FEAT_8000_0001_EDX] = 3134 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3135 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3136 .features[FEAT_8000_0001_ECX] = 3137 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3138 .features[FEAT_7_0_EBX] = 3139 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3140 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3141 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3142 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3143 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3144 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3145 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3146 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3147 .features[FEAT_7_0_ECX] = 3148 CPUID_7_0_ECX_PKU | 3149 CPUID_7_0_ECX_AVX512VNNI, 3150 .features[FEAT_7_0_EDX] = 3151 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3152 /* XSAVES is added in version 5 */ 3153 .features[FEAT_XSAVE] = 3154 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3155 CPUID_XSAVE_XGETBV1, 3156 .features[FEAT_6_EAX] = 3157 CPUID_6_EAX_ARAT, 3158 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3159 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3160 MSR_VMX_BASIC_TRUE_CTLS, 3161 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3162 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3163 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3164 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3165 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3166 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3167 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3168 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3169 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3170 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3171 .features[FEAT_VMX_EXIT_CTLS] = 3172 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3173 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3174 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3175 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3176 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3177 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3178 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3179 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3180 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3181 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3182 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3183 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3184 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3185 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3186 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3187 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3188 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3189 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3190 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3191 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3192 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3193 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3194 .features[FEAT_VMX_SECONDARY_CTLS] = 3195 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3196 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3197 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3198 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3199 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3200 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3201 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3202 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3203 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3204 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3205 .xlevel = 0x80000008, 3206 .model_id = "Intel Xeon Processor (Cascadelake)", 3207 .versions = (X86CPUVersionDefinition[]) { 3208 { .version = 1 }, 3209 { .version = 2, 3210 .note = "ARCH_CAPABILITIES", 3211 .props = (PropValue[]) { 3212 { "arch-capabilities", "on" }, 3213 { "rdctl-no", "on" }, 3214 { "ibrs-all", "on" }, 3215 { "skip-l1dfl-vmentry", "on" }, 3216 { "mds-no", "on" }, 3217 { /* end of list */ } 3218 }, 3219 }, 3220 { .version = 3, 3221 .alias = "Cascadelake-Server-noTSX", 3222 .note = "ARCH_CAPABILITIES, no TSX", 3223 .props = (PropValue[]) { 3224 { "hle", "off" }, 3225 { "rtm", "off" }, 3226 { /* end of list */ } 3227 }, 3228 }, 3229 { .version = 4, 3230 .note = "ARCH_CAPABILITIES, no TSX", 3231 .props = (PropValue[]) { 3232 { "vmx-eptp-switching", "on" }, 3233 { /* end of list */ } 3234 }, 3235 }, 3236 { .version = 5, 3237 .note = "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX", 3238 .props = (PropValue[]) { 3239 { "xsaves", "on" }, 3240 { "vmx-xsaves", "on" }, 3241 { /* end of list */ } 3242 }, 3243 }, 3244 { /* end of list */ } 3245 } 3246 }, 3247 { 3248 .name = "Cooperlake", 3249 .level = 0xd, 3250 .vendor = CPUID_VENDOR_INTEL, 3251 .family = 6, 3252 .model = 85, 3253 .stepping = 10, 3254 .features[FEAT_1_EDX] = 3255 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3256 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3257 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3258 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3259 CPUID_DE | CPUID_FP87, 3260 .features[FEAT_1_ECX] = 3261 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3262 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3263 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3264 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3265 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3266 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3267 .features[FEAT_8000_0001_EDX] = 3268 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3269 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3270 .features[FEAT_8000_0001_ECX] = 3271 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3272 .features[FEAT_7_0_EBX] = 3273 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3274 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3275 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3276 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3277 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3278 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3279 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3280 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3281 .features[FEAT_7_0_ECX] = 3282 CPUID_7_0_ECX_PKU | 3283 CPUID_7_0_ECX_AVX512VNNI, 3284 .features[FEAT_7_0_EDX] = 3285 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | 3286 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, 3287 .features[FEAT_ARCH_CAPABILITIES] = 3288 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | 3289 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | 3290 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO, 3291 .features[FEAT_7_1_EAX] = 3292 CPUID_7_1_EAX_AVX512_BF16, 3293 /* XSAVES is added in version 2 */ 3294 .features[FEAT_XSAVE] = 3295 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3296 CPUID_XSAVE_XGETBV1, 3297 .features[FEAT_6_EAX] = 3298 CPUID_6_EAX_ARAT, 3299 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3300 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3301 MSR_VMX_BASIC_TRUE_CTLS, 3302 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3303 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3304 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3305 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3306 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3307 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3308 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3309 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3310 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3311 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3312 .features[FEAT_VMX_EXIT_CTLS] = 3313 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3314 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3315 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3316 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3317 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3318 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3319 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3320 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3321 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3322 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3323 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3324 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3325 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3326 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3327 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3328 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3329 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3330 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3331 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3332 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3333 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3334 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3335 .features[FEAT_VMX_SECONDARY_CTLS] = 3336 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3337 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3338 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3339 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3340 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3341 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3342 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3343 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3344 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3345 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3346 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3347 .xlevel = 0x80000008, 3348 .model_id = "Intel Xeon Processor (Cooperlake)", 3349 .versions = (X86CPUVersionDefinition[]) { 3350 { .version = 1 }, 3351 { .version = 2, 3352 .note = "XSAVES", 3353 .props = (PropValue[]) { 3354 { "xsaves", "on" }, 3355 { "vmx-xsaves", "on" }, 3356 { /* end of list */ } 3357 }, 3358 }, 3359 { /* end of list */ } 3360 } 3361 }, 3362 { 3363 .name = "Icelake-Server", 3364 .level = 0xd, 3365 .vendor = CPUID_VENDOR_INTEL, 3366 .family = 6, 3367 .model = 134, 3368 .stepping = 0, 3369 .features[FEAT_1_EDX] = 3370 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3371 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3372 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3373 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3374 CPUID_DE | CPUID_FP87, 3375 .features[FEAT_1_ECX] = 3376 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3377 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3378 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3379 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3380 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3381 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3382 .features[FEAT_8000_0001_EDX] = 3383 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3384 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3385 .features[FEAT_8000_0001_ECX] = 3386 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3387 .features[FEAT_8000_0008_EBX] = 3388 CPUID_8000_0008_EBX_WBNOINVD, 3389 .features[FEAT_7_0_EBX] = 3390 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | 3391 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | 3392 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | 3393 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | 3394 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | 3395 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | 3396 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | 3397 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, 3398 .features[FEAT_7_0_ECX] = 3399 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | 3400 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI | 3401 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ | 3402 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG | 3403 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57, 3404 .features[FEAT_7_0_EDX] = 3405 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3406 /* XSAVES is added in version 5 */ 3407 .features[FEAT_XSAVE] = 3408 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3409 CPUID_XSAVE_XGETBV1, 3410 .features[FEAT_6_EAX] = 3411 CPUID_6_EAX_ARAT, 3412 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */ 3413 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3414 MSR_VMX_BASIC_TRUE_CTLS, 3415 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3416 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3417 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3418 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3419 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3420 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3421 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3422 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3423 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3424 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3425 .features[FEAT_VMX_EXIT_CTLS] = 3426 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3427 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3428 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3429 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3430 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3431 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3432 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3433 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3434 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3435 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3436 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3437 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3438 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3439 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3440 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3441 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3442 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3443 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3444 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3445 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3446 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3447 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3448 .features[FEAT_VMX_SECONDARY_CTLS] = 3449 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3450 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3451 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3452 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3453 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3454 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3455 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3456 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3457 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS, 3458 .xlevel = 0x80000008, 3459 .model_id = "Intel Xeon Processor (Icelake)", 3460 .versions = (X86CPUVersionDefinition[]) { 3461 { .version = 1 }, 3462 { 3463 .version = 2, 3464 .note = "no TSX", 3465 .alias = "Icelake-Server-noTSX", 3466 .props = (PropValue[]) { 3467 { "hle", "off" }, 3468 { "rtm", "off" }, 3469 { /* end of list */ } 3470 }, 3471 }, 3472 { 3473 .version = 3, 3474 .props = (PropValue[]) { 3475 { "arch-capabilities", "on" }, 3476 { "rdctl-no", "on" }, 3477 { "ibrs-all", "on" }, 3478 { "skip-l1dfl-vmentry", "on" }, 3479 { "mds-no", "on" }, 3480 { "pschange-mc-no", "on" }, 3481 { "taa-no", "on" }, 3482 { /* end of list */ } 3483 }, 3484 }, 3485 { 3486 .version = 4, 3487 .props = (PropValue[]) { 3488 { "sha-ni", "on" }, 3489 { "avx512ifma", "on" }, 3490 { "rdpid", "on" }, 3491 { "fsrm", "on" }, 3492 { "vmx-rdseed-exit", "on" }, 3493 { "vmx-pml", "on" }, 3494 { "vmx-eptp-switching", "on" }, 3495 { "model", "106" }, 3496 { /* end of list */ } 3497 }, 3498 }, 3499 { 3500 .version = 5, 3501 .note = "XSAVES", 3502 .props = (PropValue[]) { 3503 { "xsaves", "on" }, 3504 { "vmx-xsaves", "on" }, 3505 { /* end of list */ } 3506 }, 3507 }, 3508 { 3509 .version = 6, 3510 .note = "5-level EPT", 3511 .props = (PropValue[]) { 3512 { "vmx-page-walk-5", "on" }, 3513 { /* end of list */ } 3514 }, 3515 }, 3516 { /* end of list */ } 3517 } 3518 }, 3519 { 3520 .name = "Denverton", 3521 .level = 21, 3522 .vendor = CPUID_VENDOR_INTEL, 3523 .family = 6, 3524 .model = 95, 3525 .stepping = 1, 3526 .features[FEAT_1_EDX] = 3527 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | 3528 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | 3529 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3530 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR | 3531 CPUID_SSE | CPUID_SSE2, 3532 .features[FEAT_1_ECX] = 3533 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3534 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 | 3535 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3536 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | 3537 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND, 3538 .features[FEAT_8000_0001_EDX] = 3539 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | 3540 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, 3541 .features[FEAT_8000_0001_ECX] = 3542 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3543 .features[FEAT_7_0_EBX] = 3544 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS | 3545 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP | 3546 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI, 3547 .features[FEAT_7_0_EDX] = 3548 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES | 3549 CPUID_7_0_EDX_SPEC_CTRL_SSBD, 3550 /* XSAVES is added in version 3 */ 3551 .features[FEAT_XSAVE] = 3552 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1, 3553 .features[FEAT_6_EAX] = 3554 CPUID_6_EAX_ARAT, 3555 .features[FEAT_ARCH_CAPABILITIES] = 3556 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY, 3557 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3558 MSR_VMX_BASIC_TRUE_CTLS, 3559 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3560 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3561 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3562 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3563 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3564 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3565 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3566 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3567 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3568 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3569 .features[FEAT_VMX_EXIT_CTLS] = 3570 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3571 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3572 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3573 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3574 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3575 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3576 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3577 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3578 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3579 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3580 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3581 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3582 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3583 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3584 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3585 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3586 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3587 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3588 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3589 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3590 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3591 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3592 .features[FEAT_VMX_SECONDARY_CTLS] = 3593 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3594 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3595 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3596 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3597 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3598 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3599 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3600 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3601 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3602 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3603 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3604 .xlevel = 0x80000008, 3605 .model_id = "Intel Atom Processor (Denverton)", 3606 .versions = (X86CPUVersionDefinition[]) { 3607 { .version = 1 }, 3608 { 3609 .version = 2, 3610 .note = "no MPX, no MONITOR", 3611 .props = (PropValue[]) { 3612 { "monitor", "off" }, 3613 { "mpx", "off" }, 3614 { /* end of list */ }, 3615 }, 3616 }, 3617 { 3618 .version = 3, 3619 .note = "XSAVES, no MPX, no MONITOR", 3620 .props = (PropValue[]) { 3621 { "xsaves", "on" }, 3622 { "vmx-xsaves", "on" }, 3623 { /* end of list */ }, 3624 }, 3625 }, 3626 { /* end of list */ }, 3627 }, 3628 }, 3629 { 3630 .name = "Snowridge", 3631 .level = 27, 3632 .vendor = CPUID_VENDOR_INTEL, 3633 .family = 6, 3634 .model = 134, 3635 .stepping = 1, 3636 .features[FEAT_1_EDX] = 3637 /* missing: CPUID_PN CPUID_IA64 */ 3638 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ 3639 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | 3640 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE | 3641 CPUID_CX8 | CPUID_APIC | CPUID_SEP | 3642 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | 3643 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | 3644 CPUID_MMX | 3645 CPUID_FXSR | CPUID_SSE | CPUID_SSE2, 3646 .features[FEAT_1_ECX] = 3647 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR | 3648 CPUID_EXT_SSSE3 | 3649 CPUID_EXT_CX16 | 3650 CPUID_EXT_SSE41 | 3651 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | 3652 CPUID_EXT_POPCNT | 3653 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE | 3654 CPUID_EXT_RDRAND, 3655 .features[FEAT_8000_0001_EDX] = 3656 CPUID_EXT2_SYSCALL | 3657 CPUID_EXT2_NX | 3658 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3659 CPUID_EXT2_LM, 3660 .features[FEAT_8000_0001_ECX] = 3661 CPUID_EXT3_LAHF_LM | 3662 CPUID_EXT3_3DNOWPREFETCH, 3663 .features[FEAT_7_0_EBX] = 3664 CPUID_7_0_EBX_FSGSBASE | 3665 CPUID_7_0_EBX_SMEP | 3666 CPUID_7_0_EBX_ERMS | 3667 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */ 3668 CPUID_7_0_EBX_RDSEED | 3669 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3670 CPUID_7_0_EBX_CLWB | 3671 CPUID_7_0_EBX_SHA_NI, 3672 .features[FEAT_7_0_ECX] = 3673 CPUID_7_0_ECX_UMIP | 3674 /* missing bit 5 */ 3675 CPUID_7_0_ECX_GFNI | 3676 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE | 3677 CPUID_7_0_ECX_MOVDIR64B, 3678 .features[FEAT_7_0_EDX] = 3679 CPUID_7_0_EDX_SPEC_CTRL | 3680 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD | 3681 CPUID_7_0_EDX_CORE_CAPABILITY, 3682 .features[FEAT_CORE_CAPABILITY] = 3683 MSR_CORE_CAP_SPLIT_LOCK_DETECT, 3684 /* XSAVES is added in version 3 */ 3685 .features[FEAT_XSAVE] = 3686 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3687 CPUID_XSAVE_XGETBV1, 3688 .features[FEAT_6_EAX] = 3689 CPUID_6_EAX_ARAT, 3690 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS | 3691 MSR_VMX_BASIC_TRUE_CTLS, 3692 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE | 3693 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT | 3694 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER, 3695 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY | 3696 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | 3697 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT | 3698 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT | 3699 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | 3700 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT | 3701 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS, 3702 .features[FEAT_VMX_EXIT_CTLS] = 3703 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | 3704 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 3705 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER | 3706 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | 3707 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER, 3708 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT | 3709 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT, 3710 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK | 3711 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS | 3712 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR, 3713 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING | 3714 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | 3715 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | 3716 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | 3717 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING | 3718 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING | 3719 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS | 3720 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING | 3721 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS | 3722 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING | 3723 VMX_CPU_BASED_MONITOR_TRAP_FLAG | 3724 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, 3725 .features[FEAT_VMX_SECONDARY_CTLS] = 3726 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 3727 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT | 3728 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP | 3729 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 3730 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | 3731 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | 3732 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 3733 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID | 3734 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS | 3735 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML, 3736 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING, 3737 .xlevel = 0x80000008, 3738 .model_id = "Intel Atom Processor (SnowRidge)", 3739 .versions = (X86CPUVersionDefinition[]) { 3740 { .version = 1 }, 3741 { 3742 .version = 2, 3743 .props = (PropValue[]) { 3744 { "mpx", "off" }, 3745 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" }, 3746 { /* end of list */ }, 3747 }, 3748 }, 3749 { 3750 .version = 3, 3751 .note = "XSAVES, no MPX", 3752 .props = (PropValue[]) { 3753 { "xsaves", "on" }, 3754 { "vmx-xsaves", "on" }, 3755 { /* end of list */ }, 3756 }, 3757 }, 3758 { 3759 .version = 4, 3760 .note = "no split lock detect, no core-capability", 3761 .props = (PropValue[]) { 3762 { "split-lock-detect", "off" }, 3763 { "core-capability", "off" }, 3764 { /* end of list */ }, 3765 }, 3766 }, 3767 { /* end of list */ }, 3768 }, 3769 }, 3770 { 3771 .name = "KnightsMill", 3772 .level = 0xd, 3773 .vendor = CPUID_VENDOR_INTEL, 3774 .family = 6, 3775 .model = 133, 3776 .stepping = 0, 3777 .features[FEAT_1_EDX] = 3778 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | 3779 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | 3780 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | 3781 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | 3782 CPUID_PSE | CPUID_DE | CPUID_FP87, 3783 .features[FEAT_1_ECX] = 3784 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3785 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | 3786 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | 3787 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 3788 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | 3789 CPUID_EXT_F16C | CPUID_EXT_RDRAND, 3790 .features[FEAT_8000_0001_EDX] = 3791 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | 3792 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3793 .features[FEAT_8000_0001_ECX] = 3794 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, 3795 .features[FEAT_7_0_EBX] = 3796 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3797 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | 3798 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F | 3799 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF | 3800 CPUID_7_0_EBX_AVX512ER, 3801 .features[FEAT_7_0_ECX] = 3802 CPUID_7_0_ECX_AVX512_VPOPCNTDQ, 3803 .features[FEAT_7_0_EDX] = 3804 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS, 3805 .features[FEAT_XSAVE] = 3806 CPUID_XSAVE_XSAVEOPT, 3807 .features[FEAT_6_EAX] = 3808 CPUID_6_EAX_ARAT, 3809 .xlevel = 0x80000008, 3810 .model_id = "Intel Xeon Phi Processor (Knights Mill)", 3811 }, 3812 { 3813 .name = "Opteron_G1", 3814 .level = 5, 3815 .vendor = CPUID_VENDOR_AMD, 3816 .family = 15, 3817 .model = 6, 3818 .stepping = 1, 3819 .features[FEAT_1_EDX] = 3820 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3821 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3822 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3823 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3824 CPUID_DE | CPUID_FP87, 3825 .features[FEAT_1_ECX] = 3826 CPUID_EXT_SSE3, 3827 .features[FEAT_8000_0001_EDX] = 3828 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3829 .xlevel = 0x80000008, 3830 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)", 3831 }, 3832 { 3833 .name = "Opteron_G2", 3834 .level = 5, 3835 .vendor = CPUID_VENDOR_AMD, 3836 .family = 15, 3837 .model = 6, 3838 .stepping = 1, 3839 .features[FEAT_1_EDX] = 3840 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3841 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3842 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3843 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3844 CPUID_DE | CPUID_FP87, 3845 .features[FEAT_1_ECX] = 3846 CPUID_EXT_CX16 | CPUID_EXT_SSE3, 3847 .features[FEAT_8000_0001_EDX] = 3848 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, 3849 .features[FEAT_8000_0001_ECX] = 3850 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3851 .xlevel = 0x80000008, 3852 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)", 3853 }, 3854 { 3855 .name = "Opteron_G3", 3856 .level = 5, 3857 .vendor = CPUID_VENDOR_AMD, 3858 .family = 16, 3859 .model = 2, 3860 .stepping = 3, 3861 .features[FEAT_1_EDX] = 3862 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3863 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3864 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3865 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3866 CPUID_DE | CPUID_FP87, 3867 .features[FEAT_1_ECX] = 3868 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | 3869 CPUID_EXT_SSE3, 3870 .features[FEAT_8000_0001_EDX] = 3871 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL | 3872 CPUID_EXT2_RDTSCP, 3873 .features[FEAT_8000_0001_ECX] = 3874 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | 3875 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, 3876 .xlevel = 0x80000008, 3877 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)", 3878 }, 3879 { 3880 .name = "Opteron_G4", 3881 .level = 0xd, 3882 .vendor = CPUID_VENDOR_AMD, 3883 .family = 21, 3884 .model = 1, 3885 .stepping = 2, 3886 .features[FEAT_1_EDX] = 3887 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3888 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3889 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3890 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3891 CPUID_DE | CPUID_FP87, 3892 .features[FEAT_1_ECX] = 3893 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | 3894 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3895 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | 3896 CPUID_EXT_SSE3, 3897 .features[FEAT_8000_0001_EDX] = 3898 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3899 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3900 .features[FEAT_8000_0001_ECX] = 3901 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3902 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3903 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3904 CPUID_EXT3_LAHF_LM, 3905 .features[FEAT_SVM] = 3906 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3907 /* no xsaveopt! */ 3908 .xlevel = 0x8000001A, 3909 .model_id = "AMD Opteron 62xx class CPU", 3910 }, 3911 { 3912 .name = "Opteron_G5", 3913 .level = 0xd, 3914 .vendor = CPUID_VENDOR_AMD, 3915 .family = 21, 3916 .model = 2, 3917 .stepping = 0, 3918 .features[FEAT_1_EDX] = 3919 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | 3920 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | 3921 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | 3922 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | 3923 CPUID_DE | CPUID_FP87, 3924 .features[FEAT_1_ECX] = 3925 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE | 3926 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | 3927 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | 3928 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3929 .features[FEAT_8000_0001_EDX] = 3930 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX | 3931 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP, 3932 .features[FEAT_8000_0001_ECX] = 3933 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP | 3934 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | 3935 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | 3936 CPUID_EXT3_LAHF_LM, 3937 .features[FEAT_SVM] = 3938 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3939 /* no xsaveopt! */ 3940 .xlevel = 0x8000001A, 3941 .model_id = "AMD Opteron 63xx class CPU", 3942 }, 3943 { 3944 .name = "EPYC", 3945 .level = 0xd, 3946 .vendor = CPUID_VENDOR_AMD, 3947 .family = 23, 3948 .model = 1, 3949 .stepping = 2, 3950 .features[FEAT_1_EDX] = 3951 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 3952 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 3953 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 3954 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 3955 CPUID_VME | CPUID_FP87, 3956 .features[FEAT_1_ECX] = 3957 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 3958 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 3959 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 3960 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 3961 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 3962 .features[FEAT_8000_0001_EDX] = 3963 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 3964 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 3965 CPUID_EXT2_SYSCALL, 3966 .features[FEAT_8000_0001_ECX] = 3967 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 3968 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 3969 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 3970 CPUID_EXT3_TOPOEXT, 3971 .features[FEAT_7_0_EBX] = 3972 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 3973 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 3974 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 3975 CPUID_7_0_EBX_SHA_NI, 3976 .features[FEAT_XSAVE] = 3977 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 3978 CPUID_XSAVE_XGETBV1, 3979 .features[FEAT_6_EAX] = 3980 CPUID_6_EAX_ARAT, 3981 .features[FEAT_SVM] = 3982 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 3983 .xlevel = 0x8000001E, 3984 .model_id = "AMD EPYC Processor", 3985 .cache_info = &epyc_cache_info, 3986 .versions = (X86CPUVersionDefinition[]) { 3987 { .version = 1 }, 3988 { 3989 .version = 2, 3990 .alias = "EPYC-IBPB", 3991 .props = (PropValue[]) { 3992 { "ibpb", "on" }, 3993 { "model-id", 3994 "AMD EPYC Processor (with IBPB)" }, 3995 { /* end of list */ } 3996 } 3997 }, 3998 { 3999 .version = 3, 4000 .props = (PropValue[]) { 4001 { "ibpb", "on" }, 4002 { "perfctr-core", "on" }, 4003 { "clzero", "on" }, 4004 { "xsaveerptr", "on" }, 4005 { "xsaves", "on" }, 4006 { "model-id", 4007 "AMD EPYC Processor" }, 4008 { /* end of list */ } 4009 } 4010 }, 4011 { /* end of list */ } 4012 } 4013 }, 4014 { 4015 .name = "Dhyana", 4016 .level = 0xd, 4017 .vendor = CPUID_VENDOR_HYGON, 4018 .family = 24, 4019 .model = 0, 4020 .stepping = 1, 4021 .features[FEAT_1_EDX] = 4022 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4023 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4024 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4025 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4026 CPUID_VME | CPUID_FP87, 4027 .features[FEAT_1_ECX] = 4028 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4029 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT | 4030 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4031 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4032 CPUID_EXT_MONITOR | CPUID_EXT_SSE3, 4033 .features[FEAT_8000_0001_EDX] = 4034 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4035 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4036 CPUID_EXT2_SYSCALL, 4037 .features[FEAT_8000_0001_ECX] = 4038 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4039 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4040 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4041 CPUID_EXT3_TOPOEXT, 4042 .features[FEAT_8000_0008_EBX] = 4043 CPUID_8000_0008_EBX_IBPB, 4044 .features[FEAT_7_0_EBX] = 4045 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4046 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4047 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT, 4048 /* XSAVES is added in version 2 */ 4049 .features[FEAT_XSAVE] = 4050 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4051 CPUID_XSAVE_XGETBV1, 4052 .features[FEAT_6_EAX] = 4053 CPUID_6_EAX_ARAT, 4054 .features[FEAT_SVM] = 4055 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4056 .xlevel = 0x8000001E, 4057 .model_id = "Hygon Dhyana Processor", 4058 .cache_info = &epyc_cache_info, 4059 .versions = (X86CPUVersionDefinition[]) { 4060 { .version = 1 }, 4061 { .version = 2, 4062 .note = "XSAVES", 4063 .props = (PropValue[]) { 4064 { "xsaves", "on" }, 4065 { /* end of list */ } 4066 }, 4067 }, 4068 { /* end of list */ } 4069 } 4070 }, 4071 { 4072 .name = "EPYC-Rome", 4073 .level = 0xd, 4074 .vendor = CPUID_VENDOR_AMD, 4075 .family = 23, 4076 .model = 49, 4077 .stepping = 0, 4078 .features[FEAT_1_EDX] = 4079 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4080 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4081 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4082 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4083 CPUID_VME | CPUID_FP87, 4084 .features[FEAT_1_ECX] = 4085 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4086 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4087 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4088 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4089 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, 4090 .features[FEAT_8000_0001_EDX] = 4091 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4092 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4093 CPUID_EXT2_SYSCALL, 4094 .features[FEAT_8000_0001_ECX] = 4095 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4096 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4097 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4098 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4099 .features[FEAT_8000_0008_EBX] = 4100 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4101 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4102 CPUID_8000_0008_EBX_STIBP, 4103 .features[FEAT_7_0_EBX] = 4104 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4105 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4106 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4107 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB, 4108 .features[FEAT_7_0_ECX] = 4109 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID, 4110 .features[FEAT_XSAVE] = 4111 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4112 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4113 .features[FEAT_6_EAX] = 4114 CPUID_6_EAX_ARAT, 4115 .features[FEAT_SVM] = 4116 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE, 4117 .xlevel = 0x8000001E, 4118 .model_id = "AMD EPYC-Rome Processor", 4119 .cache_info = &epyc_rome_cache_info, 4120 .versions = (X86CPUVersionDefinition[]) { 4121 { .version = 1 }, 4122 { 4123 .version = 2, 4124 .props = (PropValue[]) { 4125 { "ibrs", "on" }, 4126 { "amd-ssbd", "on" }, 4127 { /* end of list */ } 4128 } 4129 }, 4130 { /* end of list */ } 4131 } 4132 }, 4133 { 4134 .name = "EPYC-Milan", 4135 .level = 0xd, 4136 .vendor = CPUID_VENDOR_AMD, 4137 .family = 25, 4138 .model = 1, 4139 .stepping = 1, 4140 .features[FEAT_1_EDX] = 4141 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | 4142 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE | 4143 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE | 4144 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE | 4145 CPUID_VME | CPUID_FP87, 4146 .features[FEAT_1_ECX] = 4147 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX | 4148 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT | 4149 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | 4150 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | 4151 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | 4152 CPUID_EXT_PCID, 4153 .features[FEAT_8000_0001_EDX] = 4154 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | 4155 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX | 4156 CPUID_EXT2_SYSCALL, 4157 .features[FEAT_8000_0001_ECX] = 4158 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH | 4159 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | 4160 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | 4161 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE, 4162 .features[FEAT_8000_0008_EBX] = 4163 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR | 4164 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB | 4165 CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP | 4166 CPUID_8000_0008_EBX_AMD_SSBD, 4167 .features[FEAT_7_0_EBX] = 4168 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 | 4169 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED | 4170 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT | 4171 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS | 4172 CPUID_7_0_EBX_INVPCID, 4173 .features[FEAT_7_0_ECX] = 4174 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU, 4175 .features[FEAT_7_0_EDX] = 4176 CPUID_7_0_EDX_FSRM, 4177 .features[FEAT_XSAVE] = 4178 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | 4179 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES, 4180 .features[FEAT_6_EAX] = 4181 CPUID_6_EAX_ARAT, 4182 .features[FEAT_SVM] = 4183 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK, 4184 .xlevel = 0x8000001E, 4185 .model_id = "AMD EPYC-Milan Processor", 4186 .cache_info = &epyc_milan_cache_info, 4187 }, 4188 }; 4189 4190 /* 4191 * We resolve CPU model aliases using -v1 when using "-machine 4192 * none", but this is just for compatibility while libvirt isn't 4193 * adapted to resolve CPU model versions before creating VMs. 4194 * See "Runnability guarantee of CPU models" at 4195 * docs/about/deprecated.rst. 4196 */ 4197 X86CPUVersion default_cpu_version = 1; 4198 4199 void x86_cpu_set_default_version(X86CPUVersion version) 4200 { 4201 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */ 4202 assert(version != CPU_VERSION_AUTO); 4203 default_cpu_version = version; 4204 } 4205 4206 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model) 4207 { 4208 int v = 0; 4209 const X86CPUVersionDefinition *vdef = 4210 x86_cpu_def_get_versions(model->cpudef); 4211 while (vdef->version) { 4212 v = vdef->version; 4213 vdef++; 4214 } 4215 return v; 4216 } 4217 4218 /* Return the actual version being used for a specific CPU model */ 4219 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) 4220 { 4221 X86CPUVersion v = model->version; 4222 if (v == CPU_VERSION_AUTO) { 4223 v = default_cpu_version; 4224 } 4225 if (v == CPU_VERSION_LATEST) { 4226 return x86_cpu_model_last_version(model); 4227 } 4228 return v; 4229 } 4230 4231 static Property max_x86_cpu_properties[] = { 4232 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), 4233 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), 4234 DEFINE_PROP_END_OF_LIST() 4235 }; 4236 4237 static void max_x86_cpu_class_init(ObjectClass *oc, void *data) 4238 { 4239 DeviceClass *dc = DEVICE_CLASS(oc); 4240 X86CPUClass *xcc = X86_CPU_CLASS(oc); 4241 4242 xcc->ordering = 9; 4243 4244 xcc->model_description = 4245 "Enables all features supported by the accelerator in the current host"; 4246 4247 device_class_set_props(dc, max_x86_cpu_properties); 4248 } 4249 4250 static void max_x86_cpu_initfn(Object *obj) 4251 { 4252 X86CPU *cpu = X86_CPU(obj); 4253 4254 /* We can't fill the features array here because we don't know yet if 4255 * "migratable" is true or false. 4256 */ 4257 cpu->max_features = true; 4258 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort); 4259 4260 /* 4261 * these defaults are used for TCG and all other accelerators 4262 * besides KVM and HVF, which overwrite these values 4263 */ 4264 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD, 4265 &error_abort); 4266 #ifdef TARGET_X86_64 4267 object_property_set_int(OBJECT(cpu), "family", 15, &error_abort); 4268 object_property_set_int(OBJECT(cpu), "model", 107, &error_abort); 4269 object_property_set_int(OBJECT(cpu), "stepping", 1, &error_abort); 4270 #else 4271 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort); 4272 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort); 4273 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort); 4274 #endif 4275 object_property_set_str(OBJECT(cpu), "model-id", 4276 "QEMU TCG CPU version " QEMU_HW_VERSION, 4277 &error_abort); 4278 } 4279 4280 static const TypeInfo max_x86_cpu_type_info = { 4281 .name = X86_CPU_TYPE_NAME("max"), 4282 .parent = TYPE_X86_CPU, 4283 .instance_init = max_x86_cpu_initfn, 4284 .class_init = max_x86_cpu_class_init, 4285 }; 4286 4287 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) 4288 { 4289 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); 4290 4291 switch (f->type) { 4292 case CPUID_FEATURE_WORD: 4293 { 4294 const char *reg = get_register_name_32(f->cpuid.reg); 4295 assert(reg); 4296 return g_strdup_printf("CPUID.%02XH:%s", 4297 f->cpuid.eax, reg); 4298 } 4299 case MSR_FEATURE_WORD: 4300 return g_strdup_printf("MSR(%02XH)", 4301 f->msr.index); 4302 } 4303 4304 return NULL; 4305 } 4306 4307 static bool x86_cpu_have_filtered_features(X86CPU *cpu) 4308 { 4309 FeatureWord w; 4310 4311 for (w = 0; w < FEATURE_WORDS; w++) { 4312 if (cpu->filtered_features[w]) { 4313 return true; 4314 } 4315 } 4316 4317 return false; 4318 } 4319 4320 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask, 4321 const char *verbose_prefix) 4322 { 4323 CPUX86State *env = &cpu->env; 4324 FeatureWordInfo *f = &feature_word_info[w]; 4325 int i; 4326 4327 if (!cpu->force_features) { 4328 env->features[w] &= ~mask; 4329 } 4330 cpu->filtered_features[w] |= mask; 4331 4332 if (!verbose_prefix) { 4333 return; 4334 } 4335 4336 for (i = 0; i < 64; ++i) { 4337 if ((1ULL << i) & mask) { 4338 g_autofree char *feat_word_str = feature_word_description(f, i); 4339 warn_report("%s: %s%s%s [bit %d]", 4340 verbose_prefix, 4341 feat_word_str, 4342 f->feat_names[i] ? "." : "", 4343 f->feat_names[i] ? f->feat_names[i] : "", i); 4344 } 4345 } 4346 } 4347 4348 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, 4349 const char *name, void *opaque, 4350 Error **errp) 4351 { 4352 X86CPU *cpu = X86_CPU(obj); 4353 CPUX86State *env = &cpu->env; 4354 int64_t value; 4355 4356 value = (env->cpuid_version >> 8) & 0xf; 4357 if (value == 0xf) { 4358 value += (env->cpuid_version >> 20) & 0xff; 4359 } 4360 visit_type_int(v, name, &value, errp); 4361 } 4362 4363 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, 4364 const char *name, void *opaque, 4365 Error **errp) 4366 { 4367 X86CPU *cpu = X86_CPU(obj); 4368 CPUX86State *env = &cpu->env; 4369 const int64_t min = 0; 4370 const int64_t max = 0xff + 0xf; 4371 int64_t value; 4372 4373 if (!visit_type_int(v, name, &value, errp)) { 4374 return; 4375 } 4376 if (value < min || value > max) { 4377 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4378 name ? name : "null", value, min, max); 4379 return; 4380 } 4381 4382 env->cpuid_version &= ~0xff00f00; 4383 if (value > 0x0f) { 4384 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); 4385 } else { 4386 env->cpuid_version |= value << 8; 4387 } 4388 } 4389 4390 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, 4391 const char *name, void *opaque, 4392 Error **errp) 4393 { 4394 X86CPU *cpu = X86_CPU(obj); 4395 CPUX86State *env = &cpu->env; 4396 int64_t value; 4397 4398 value = (env->cpuid_version >> 4) & 0xf; 4399 value |= ((env->cpuid_version >> 16) & 0xf) << 4; 4400 visit_type_int(v, name, &value, errp); 4401 } 4402 4403 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, 4404 const char *name, void *opaque, 4405 Error **errp) 4406 { 4407 X86CPU *cpu = X86_CPU(obj); 4408 CPUX86State *env = &cpu->env; 4409 const int64_t min = 0; 4410 const int64_t max = 0xff; 4411 int64_t value; 4412 4413 if (!visit_type_int(v, name, &value, errp)) { 4414 return; 4415 } 4416 if (value < min || value > max) { 4417 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4418 name ? name : "null", value, min, max); 4419 return; 4420 } 4421 4422 env->cpuid_version &= ~0xf00f0; 4423 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); 4424 } 4425 4426 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, 4427 const char *name, void *opaque, 4428 Error **errp) 4429 { 4430 X86CPU *cpu = X86_CPU(obj); 4431 CPUX86State *env = &cpu->env; 4432 int64_t value; 4433 4434 value = env->cpuid_version & 0xf; 4435 visit_type_int(v, name, &value, errp); 4436 } 4437 4438 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, 4439 const char *name, void *opaque, 4440 Error **errp) 4441 { 4442 X86CPU *cpu = X86_CPU(obj); 4443 CPUX86State *env = &cpu->env; 4444 const int64_t min = 0; 4445 const int64_t max = 0xf; 4446 int64_t value; 4447 4448 if (!visit_type_int(v, name, &value, errp)) { 4449 return; 4450 } 4451 if (value < min || value > max) { 4452 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4453 name ? name : "null", value, min, max); 4454 return; 4455 } 4456 4457 env->cpuid_version &= ~0xf; 4458 env->cpuid_version |= value & 0xf; 4459 } 4460 4461 static void x86_cpuid_version_get_brand_id(Object *obj, Visitor *v, 4462 const char *name, void *opaque, 4463 Error **errp) 4464 { 4465 X86CPU *cpu = X86_CPU(obj); 4466 CPUX86State *env = &cpu->env; 4467 int64_t value; 4468 4469 value = env->cpuid_brand_id; 4470 visit_type_int(v, name, &value, errp); 4471 } 4472 4473 static void x86_cpuid_version_set_brand_id(Object *obj, Visitor *v, 4474 const char *name, void *opaque, 4475 Error **errp) 4476 { 4477 X86CPU *cpu = X86_CPU(obj); 4478 CPUX86State *env = &cpu->env; 4479 const int64_t min = 0; 4480 const int64_t max = 0xffff; 4481 int64_t value; 4482 4483 if (!visit_type_int(v, name, &value, errp)) { 4484 return; 4485 } 4486 if (value < min || value > max) { 4487 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4488 name ? name : "null", value, min, max); 4489 return; 4490 } 4491 4492 env->cpuid_brand_id = value; 4493 } 4494 4495 4496 static char *x86_cpuid_get_vendor(Object *obj, Error **errp) 4497 { 4498 X86CPU *cpu = X86_CPU(obj); 4499 CPUX86State *env = &cpu->env; 4500 char *value; 4501 4502 value = g_malloc(CPUID_VENDOR_SZ + 1); 4503 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2, 4504 env->cpuid_vendor3); 4505 return value; 4506 } 4507 4508 static void x86_cpuid_set_vendor(Object *obj, const char *value, 4509 Error **errp) 4510 { 4511 X86CPU *cpu = X86_CPU(obj); 4512 CPUX86State *env = &cpu->env; 4513 int i; 4514 4515 if (strlen(value) != CPUID_VENDOR_SZ) { 4516 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value); 4517 return; 4518 } 4519 4520 env->cpuid_vendor1 = 0; 4521 env->cpuid_vendor2 = 0; 4522 env->cpuid_vendor3 = 0; 4523 for (i = 0; i < 4; i++) { 4524 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i); 4525 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); 4526 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); 4527 } 4528 } 4529 4530 static char *x86_cpuid_get_model_id(Object *obj, Error **errp) 4531 { 4532 X86CPU *cpu = X86_CPU(obj); 4533 CPUX86State *env = &cpu->env; 4534 char *value; 4535 int i; 4536 4537 value = g_malloc(48 + 1); 4538 for (i = 0; i < 48; i++) { 4539 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); 4540 } 4541 value[48] = '\0'; 4542 return value; 4543 } 4544 4545 static void x86_cpuid_set_model_id(Object *obj, const char *model_id, 4546 Error **errp) 4547 { 4548 X86CPU *cpu = X86_CPU(obj); 4549 CPUX86State *env = &cpu->env; 4550 int c, len, i; 4551 4552 if (model_id == NULL) { 4553 model_id = ""; 4554 } 4555 len = strlen(model_id); 4556 memset(env->cpuid_model, 0, 48); 4557 for (i = 0; i < 48; i++) { 4558 if (i >= len) { 4559 c = '\0'; 4560 } else { 4561 c = (uint8_t)model_id[i]; 4562 } 4563 env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); 4564 } 4565 } 4566 4567 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name, 4568 void *opaque, Error **errp) 4569 { 4570 X86CPU *cpu = X86_CPU(obj); 4571 int64_t value; 4572 4573 value = cpu->env.tsc_khz * 1000; 4574 visit_type_int(v, name, &value, errp); 4575 } 4576 4577 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name, 4578 void *opaque, Error **errp) 4579 { 4580 X86CPU *cpu = X86_CPU(obj); 4581 const int64_t min = 0; 4582 const int64_t max = INT64_MAX; 4583 int64_t value; 4584 4585 if (!visit_type_int(v, name, &value, errp)) { 4586 return; 4587 } 4588 if (value < min || value > max) { 4589 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "", 4590 name ? name : "null", value, min, max); 4591 return; 4592 } 4593 4594 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000; 4595 } 4596 4597 /* Generic getter for "feature-words" and "filtered-features" properties */ 4598 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, 4599 const char *name, void *opaque, 4600 Error **errp) 4601 { 4602 uint64_t *array = (uint64_t *)opaque; 4603 FeatureWord w; 4604 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { }; 4605 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { }; 4606 X86CPUFeatureWordInfoList *list = NULL; 4607 4608 for (w = 0; w < FEATURE_WORDS; w++) { 4609 FeatureWordInfo *wi = &feature_word_info[w]; 4610 /* 4611 * We didn't have MSR features when "feature-words" was 4612 * introduced. Therefore skipped other type entries. 4613 */ 4614 if (wi->type != CPUID_FEATURE_WORD) { 4615 continue; 4616 } 4617 X86CPUFeatureWordInfo *qwi = &word_infos[w]; 4618 qwi->cpuid_input_eax = wi->cpuid.eax; 4619 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx; 4620 qwi->cpuid_input_ecx = wi->cpuid.ecx; 4621 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum; 4622 qwi->features = array[w]; 4623 4624 /* List will be in reverse order, but order shouldn't matter */ 4625 list_entries[w].next = list; 4626 list_entries[w].value = &word_infos[w]; 4627 list = &list_entries[w]; 4628 } 4629 4630 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp); 4631 } 4632 4633 /* Convert all '_' in a feature string option name to '-', to make feature 4634 * name conform to QOM property naming rule, which uses '-' instead of '_'. 4635 */ 4636 static inline void feat2prop(char *s) 4637 { 4638 while ((s = strchr(s, '_'))) { 4639 *s = '-'; 4640 } 4641 } 4642 4643 /* Return the feature property name for a feature flag bit */ 4644 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr) 4645 { 4646 const char *name; 4647 /* XSAVE components are automatically enabled by other features, 4648 * so return the original feature name instead 4649 */ 4650 if (w == FEAT_XSAVE_XCR0_LO || w == FEAT_XSAVE_XCR0_HI) { 4651 int comp = (w == FEAT_XSAVE_XCR0_HI) ? bitnr + 32 : bitnr; 4652 4653 if (comp < ARRAY_SIZE(x86_ext_save_areas) && 4654 x86_ext_save_areas[comp].bits) { 4655 w = x86_ext_save_areas[comp].feature; 4656 bitnr = ctz32(x86_ext_save_areas[comp].bits); 4657 } 4658 } 4659 4660 assert(bitnr < 64); 4661 assert(w < FEATURE_WORDS); 4662 name = feature_word_info[w].feat_names[bitnr]; 4663 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD)); 4664 return name; 4665 } 4666 4667 /* Compatibily hack to maintain legacy +-feat semantic, 4668 * where +-feat overwrites any feature set by 4669 * feat=on|feat even if the later is parsed after +-feat 4670 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled) 4671 */ 4672 static GList *plus_features, *minus_features; 4673 4674 static gint compare_string(gconstpointer a, gconstpointer b) 4675 { 4676 return g_strcmp0(a, b); 4677 } 4678 4679 /* Parse "+feature,-feature,feature=foo" CPU feature string 4680 */ 4681 static void x86_cpu_parse_featurestr(const char *typename, char *features, 4682 Error **errp) 4683 { 4684 char *featurestr; /* Single 'key=value" string being parsed */ 4685 static bool cpu_globals_initialized; 4686 bool ambiguous = false; 4687 4688 if (cpu_globals_initialized) { 4689 return; 4690 } 4691 cpu_globals_initialized = true; 4692 4693 if (!features) { 4694 return; 4695 } 4696 4697 for (featurestr = strtok(features, ","); 4698 featurestr; 4699 featurestr = strtok(NULL, ",")) { 4700 const char *name; 4701 const char *val = NULL; 4702 char *eq = NULL; 4703 char num[32]; 4704 GlobalProperty *prop; 4705 4706 /* Compatibility syntax: */ 4707 if (featurestr[0] == '+') { 4708 plus_features = g_list_append(plus_features, 4709 g_strdup(featurestr + 1)); 4710 continue; 4711 } else if (featurestr[0] == '-') { 4712 minus_features = g_list_append(minus_features, 4713 g_strdup(featurestr + 1)); 4714 continue; 4715 } 4716 4717 eq = strchr(featurestr, '='); 4718 if (eq) { 4719 *eq++ = 0; 4720 val = eq; 4721 } else { 4722 val = "on"; 4723 } 4724 4725 feat2prop(featurestr); 4726 name = featurestr; 4727 4728 if (g_list_find_custom(plus_features, name, compare_string)) { 4729 warn_report("Ambiguous CPU model string. " 4730 "Don't mix both \"+%s\" and \"%s=%s\"", 4731 name, name, val); 4732 ambiguous = true; 4733 } 4734 if (g_list_find_custom(minus_features, name, compare_string)) { 4735 warn_report("Ambiguous CPU model string. " 4736 "Don't mix both \"-%s\" and \"%s=%s\"", 4737 name, name, val); 4738 ambiguous = true; 4739 } 4740 4741 /* Special case: */ 4742 if (!strcmp(name, "tsc-freq")) { 4743 int ret; 4744 uint64_t tsc_freq; 4745 4746 ret = qemu_strtosz_metric(val, NULL, &tsc_freq); 4747 if (ret < 0 || tsc_freq > INT64_MAX) { 4748 error_setg(errp, "bad numerical value %s", val); 4749 return; 4750 } 4751 snprintf(num, sizeof(num), "%" PRId64, tsc_freq); 4752 val = num; 4753 name = "tsc-frequency"; 4754 } 4755 4756 prop = g_new0(typeof(*prop), 1); 4757 prop->driver = typename; 4758 prop->property = g_strdup(name); 4759 prop->value = g_strdup(val); 4760 qdev_prop_register_global(prop); 4761 } 4762 4763 if (ambiguous) { 4764 warn_report("Compatibility of ambiguous CPU model " 4765 "strings won't be kept on future QEMU versions"); 4766 } 4767 } 4768 4769 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose); 4770 4771 /* Build a list with the name of all features on a feature word array */ 4772 static void x86_cpu_list_feature_names(FeatureWordArray features, 4773 strList **list) 4774 { 4775 strList **tail = list; 4776 FeatureWord w; 4777 4778 for (w = 0; w < FEATURE_WORDS; w++) { 4779 uint64_t filtered = features[w]; 4780 int i; 4781 for (i = 0; i < 64; i++) { 4782 if (filtered & (1ULL << i)) { 4783 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i))); 4784 } 4785 } 4786 } 4787 } 4788 4789 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v, 4790 const char *name, void *opaque, 4791 Error **errp) 4792 { 4793 X86CPU *xc = X86_CPU(obj); 4794 strList *result = NULL; 4795 4796 x86_cpu_list_feature_names(xc->filtered_features, &result); 4797 visit_type_strList(v, "unavailable-features", &result, errp); 4798 } 4799 4800 /* Check for missing features that may prevent the CPU class from 4801 * running using the current machine and accelerator. 4802 */ 4803 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc, 4804 strList **list) 4805 { 4806 strList **tail = list; 4807 X86CPU *xc; 4808 Error *err = NULL; 4809 4810 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 4811 QAPI_LIST_APPEND(tail, g_strdup("kvm")); 4812 return; 4813 } 4814 4815 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc))); 4816 4817 x86_cpu_expand_features(xc, &err); 4818 if (err) { 4819 /* Errors at x86_cpu_expand_features should never happen, 4820 * but in case it does, just report the model as not 4821 * runnable at all using the "type" property. 4822 */ 4823 QAPI_LIST_APPEND(tail, g_strdup("type")); 4824 error_free(err); 4825 } 4826 4827 x86_cpu_filter_features(xc, false); 4828 4829 x86_cpu_list_feature_names(xc->filtered_features, tail); 4830 4831 object_unref(OBJECT(xc)); 4832 } 4833 4834 /* Print all cpuid feature names in featureset 4835 */ 4836 static void listflags(GList *features) 4837 { 4838 size_t len = 0; 4839 GList *tmp; 4840 4841 for (tmp = features; tmp; tmp = tmp->next) { 4842 const char *name = tmp->data; 4843 if ((len + strlen(name) + 1) >= 75) { 4844 qemu_printf("\n"); 4845 len = 0; 4846 } 4847 qemu_printf("%s%s", len == 0 ? " " : " ", name); 4848 len += strlen(name) + 1; 4849 } 4850 qemu_printf("\n"); 4851 } 4852 4853 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */ 4854 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b) 4855 { 4856 ObjectClass *class_a = (ObjectClass *)a; 4857 ObjectClass *class_b = (ObjectClass *)b; 4858 X86CPUClass *cc_a = X86_CPU_CLASS(class_a); 4859 X86CPUClass *cc_b = X86_CPU_CLASS(class_b); 4860 int ret; 4861 4862 if (cc_a->ordering != cc_b->ordering) { 4863 ret = cc_a->ordering - cc_b->ordering; 4864 } else { 4865 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a); 4866 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b); 4867 ret = strcmp(name_a, name_b); 4868 } 4869 return ret; 4870 } 4871 4872 static GSList *get_sorted_cpu_model_list(void) 4873 { 4874 GSList *list = object_class_get_list(TYPE_X86_CPU, false); 4875 list = g_slist_sort(list, x86_cpu_list_compare); 4876 return list; 4877 } 4878 4879 static char *x86_cpu_class_get_model_id(X86CPUClass *xc) 4880 { 4881 Object *obj = object_new_with_class(OBJECT_CLASS(xc)); 4882 char *r = object_property_get_str(obj, "model-id", &error_abort); 4883 object_unref(obj); 4884 return r; 4885 } 4886 4887 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc) 4888 { 4889 X86CPUVersion version; 4890 4891 if (!cc->model || !cc->model->is_alias) { 4892 return NULL; 4893 } 4894 version = x86_cpu_model_resolve_version(cc->model); 4895 if (version <= 0) { 4896 return NULL; 4897 } 4898 return x86_cpu_versioned_model_name(cc->model->cpudef, version); 4899 } 4900 4901 static void x86_cpu_list_entry(gpointer data, gpointer user_data) 4902 { 4903 ObjectClass *oc = data; 4904 X86CPUClass *cc = X86_CPU_CLASS(oc); 4905 g_autofree char *name = x86_cpu_class_get_model_name(cc); 4906 g_autofree char *desc = g_strdup(cc->model_description); 4907 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc); 4908 g_autofree char *model_id = x86_cpu_class_get_model_id(cc); 4909 4910 if (!desc && alias_of) { 4911 if (cc->model && cc->model->version == CPU_VERSION_AUTO) { 4912 desc = g_strdup("(alias configured by machine type)"); 4913 } else { 4914 desc = g_strdup_printf("(alias of %s)", alias_of); 4915 } 4916 } 4917 if (!desc && cc->model && cc->model->note) { 4918 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note); 4919 } 4920 if (!desc) { 4921 desc = g_strdup_printf("%s", model_id); 4922 } 4923 4924 if (cc->model && cc->model->cpudef->deprecation_note) { 4925 g_autofree char *olddesc = desc; 4926 desc = g_strdup_printf("%s (deprecated)", olddesc); 4927 } 4928 4929 qemu_printf("x86 %-20s %s\n", name, desc); 4930 } 4931 4932 /* list available CPU models and flags */ 4933 void x86_cpu_list(void) 4934 { 4935 int i, j; 4936 GSList *list; 4937 GList *names = NULL; 4938 4939 qemu_printf("Available CPUs:\n"); 4940 list = get_sorted_cpu_model_list(); 4941 g_slist_foreach(list, x86_cpu_list_entry, NULL); 4942 g_slist_free(list); 4943 4944 names = NULL; 4945 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) { 4946 FeatureWordInfo *fw = &feature_word_info[i]; 4947 for (j = 0; j < 64; j++) { 4948 if (fw->feat_names[j]) { 4949 names = g_list_append(names, (gpointer)fw->feat_names[j]); 4950 } 4951 } 4952 } 4953 4954 names = g_list_sort(names, (GCompareFunc)strcmp); 4955 4956 qemu_printf("\nRecognized CPUID flags:\n"); 4957 listflags(names); 4958 qemu_printf("\n"); 4959 g_list_free(names); 4960 } 4961 4962 static void x86_cpu_definition_entry(gpointer data, gpointer user_data) 4963 { 4964 ObjectClass *oc = data; 4965 X86CPUClass *cc = X86_CPU_CLASS(oc); 4966 CpuDefinitionInfoList **cpu_list = user_data; 4967 CpuDefinitionInfo *info; 4968 4969 info = g_malloc0(sizeof(*info)); 4970 info->name = x86_cpu_class_get_model_name(cc); 4971 x86_cpu_class_check_missing_features(cc, &info->unavailable_features); 4972 info->has_unavailable_features = true; 4973 info->q_typename = g_strdup(object_class_get_name(oc)); 4974 info->migration_safe = cc->migration_safe; 4975 info->has_migration_safe = true; 4976 info->q_static = cc->static_model; 4977 if (cc->model && cc->model->cpudef->deprecation_note) { 4978 info->deprecated = true; 4979 } else { 4980 info->deprecated = false; 4981 } 4982 /* 4983 * Old machine types won't report aliases, so that alias translation 4984 * doesn't break compatibility with previous QEMU versions. 4985 */ 4986 if (default_cpu_version != CPU_VERSION_LEGACY) { 4987 info->alias_of = x86_cpu_class_get_alias_of(cc); 4988 info->has_alias_of = !!info->alias_of; 4989 } 4990 4991 QAPI_LIST_PREPEND(*cpu_list, info); 4992 } 4993 4994 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 4995 { 4996 CpuDefinitionInfoList *cpu_list = NULL; 4997 GSList *list = get_sorted_cpu_model_list(); 4998 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list); 4999 g_slist_free(list); 5000 return cpu_list; 5001 } 5002 5003 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, 5004 bool migratable_only) 5005 { 5006 FeatureWordInfo *wi = &feature_word_info[w]; 5007 uint64_t r = 0; 5008 5009 if (kvm_enabled()) { 5010 switch (wi->type) { 5011 case CPUID_FEATURE_WORD: 5012 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax, 5013 wi->cpuid.ecx, 5014 wi->cpuid.reg); 5015 break; 5016 case MSR_FEATURE_WORD: 5017 r = kvm_arch_get_supported_msr_feature(kvm_state, 5018 wi->msr.index); 5019 break; 5020 } 5021 } else if (hvf_enabled()) { 5022 if (wi->type != CPUID_FEATURE_WORD) { 5023 return 0; 5024 } 5025 r = hvf_get_supported_cpuid(wi->cpuid.eax, 5026 wi->cpuid.ecx, 5027 wi->cpuid.reg); 5028 } else if (tcg_enabled()) { 5029 r = wi->tcg_features; 5030 } else { 5031 return ~0; 5032 } 5033 #ifndef TARGET_X86_64 5034 if (w == FEAT_8000_0001_EDX) { 5035 r &= ~CPUID_EXT2_LM; 5036 } 5037 #endif 5038 if (migratable_only) { 5039 r &= x86_cpu_get_migratable_flags(w); 5040 } 5041 return r; 5042 } 5043 5044 static void x86_cpu_get_supported_cpuid(uint32_t func, uint32_t index, 5045 uint32_t *eax, uint32_t *ebx, 5046 uint32_t *ecx, uint32_t *edx) 5047 { 5048 if (kvm_enabled()) { 5049 *eax = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EAX); 5050 *ebx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EBX); 5051 *ecx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_ECX); 5052 *edx = kvm_arch_get_supported_cpuid(kvm_state, func, index, R_EDX); 5053 } else if (hvf_enabled()) { 5054 *eax = hvf_get_supported_cpuid(func, index, R_EAX); 5055 *ebx = hvf_get_supported_cpuid(func, index, R_EBX); 5056 *ecx = hvf_get_supported_cpuid(func, index, R_ECX); 5057 *edx = hvf_get_supported_cpuid(func, index, R_EDX); 5058 } else { 5059 *eax = 0; 5060 *ebx = 0; 5061 *ecx = 0; 5062 *edx = 0; 5063 } 5064 } 5065 5066 static void x86_cpu_get_cache_cpuid(uint32_t func, uint32_t index, 5067 uint32_t *eax, uint32_t *ebx, 5068 uint32_t *ecx, uint32_t *edx) 5069 { 5070 uint32_t level, unused; 5071 5072 /* Only return valid host leaves. */ 5073 switch (func) { 5074 case 2: 5075 case 4: 5076 host_cpuid(0, 0, &level, &unused, &unused, &unused); 5077 break; 5078 case 0x80000005: 5079 case 0x80000006: 5080 case 0x8000001d: 5081 host_cpuid(0x80000000, 0, &level, &unused, &unused, &unused); 5082 break; 5083 default: 5084 return; 5085 } 5086 5087 if (func > level) { 5088 *eax = 0; 5089 *ebx = 0; 5090 *ecx = 0; 5091 *edx = 0; 5092 } else { 5093 host_cpuid(func, index, eax, ebx, ecx, edx); 5094 } 5095 } 5096 5097 /* 5098 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5099 */ 5100 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props) 5101 { 5102 PropValue *pv; 5103 for (pv = props; pv->prop; pv++) { 5104 if (!pv->value) { 5105 continue; 5106 } 5107 object_property_parse(OBJECT(cpu), pv->prop, pv->value, 5108 &error_abort); 5109 } 5110 } 5111 5112 /* 5113 * Apply properties for the CPU model version specified in model. 5114 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5115 */ 5116 5117 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model) 5118 { 5119 const X86CPUVersionDefinition *vdef; 5120 X86CPUVersion version = x86_cpu_model_resolve_version(model); 5121 5122 if (version == CPU_VERSION_LEGACY) { 5123 return; 5124 } 5125 5126 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) { 5127 PropValue *p; 5128 5129 for (p = vdef->props; p && p->prop; p++) { 5130 object_property_parse(OBJECT(cpu), p->prop, p->value, 5131 &error_abort); 5132 } 5133 5134 if (vdef->version == version) { 5135 break; 5136 } 5137 } 5138 5139 /* 5140 * If we reached the end of the list, version number was invalid 5141 */ 5142 assert(vdef->version == version); 5143 } 5144 5145 /* 5146 * Load data from X86CPUDefinition into a X86CPU object. 5147 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. 5148 */ 5149 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model) 5150 { 5151 const X86CPUDefinition *def = model->cpudef; 5152 CPUX86State *env = &cpu->env; 5153 FeatureWord w; 5154 5155 /*NOTE: any property set by this function should be returned by 5156 * x86_cpu_static_props(), so static expansion of 5157 * query-cpu-model-expansion is always complete. 5158 */ 5159 5160 /* CPU models only set _minimum_ values for level/xlevel: */ 5161 object_property_set_uint(OBJECT(cpu), "min-level", def->level, 5162 &error_abort); 5163 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel, 5164 &error_abort); 5165 5166 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort); 5167 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort); 5168 object_property_set_int(OBJECT(cpu), "stepping", def->stepping, 5169 &error_abort); 5170 object_property_set_str(OBJECT(cpu), "model-id", def->model_id, 5171 &error_abort); 5172 object_property_set_int(OBJECT(cpu), "brand-id", def->brand_id, 5173 &error_abort); 5174 for (w = 0; w < FEATURE_WORDS; w++) { 5175 env->features[w] = def->features[w]; 5176 } 5177 5178 /* legacy-cache defaults to 'off' if CPU model provides cache info */ 5179 cpu->legacy_cache = !def->cache_info; 5180 5181 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR; 5182 5183 /* sysenter isn't supported in compatibility mode on AMD, 5184 * syscall isn't supported in compatibility mode on Intel. 5185 * Normally we advertise the actual CPU vendor, but you can 5186 * override this using the 'vendor' property if you want to use 5187 * KVM's sysenter/syscall emulation in compatibility mode and 5188 * when doing cross vendor migration 5189 */ 5190 5191 /* 5192 * vendor property is set here but then overloaded with the 5193 * host cpu vendor for KVM and HVF. 5194 */ 5195 object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort); 5196 5197 x86_cpu_apply_version_props(cpu, model); 5198 5199 /* 5200 * Properties in versioned CPU model are not user specified features. 5201 * We can simply clear env->user_features here since it will be filled later 5202 * in x86_cpu_expand_features() based on plus_features and minus_features. 5203 */ 5204 memset(&env->user_features, 0, sizeof(env->user_features)); 5205 } 5206 5207 static gchar *x86_gdb_arch_name(CPUState *cs) 5208 { 5209 #ifdef TARGET_X86_64 5210 return g_strdup("i386:x86-64"); 5211 #else 5212 return g_strdup("i386"); 5213 #endif 5214 } 5215 5216 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data) 5217 { 5218 X86CPUModel *model = data; 5219 X86CPUClass *xcc = X86_CPU_CLASS(oc); 5220 CPUClass *cc = CPU_CLASS(oc); 5221 5222 xcc->model = model; 5223 xcc->migration_safe = true; 5224 cc->deprecation_note = model->cpudef->deprecation_note; 5225 } 5226 5227 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model) 5228 { 5229 g_autofree char *typename = x86_cpu_type_name(name); 5230 TypeInfo ti = { 5231 .name = typename, 5232 .parent = TYPE_X86_CPU, 5233 .class_init = x86_cpu_cpudef_class_init, 5234 .class_data = model, 5235 }; 5236 5237 type_register(&ti); 5238 } 5239 5240 5241 /* 5242 * register builtin_x86_defs; 5243 * "max", "base" and subclasses ("host") are not registered here. 5244 * See x86_cpu_register_types for all model registrations. 5245 */ 5246 static void x86_register_cpudef_types(const X86CPUDefinition *def) 5247 { 5248 X86CPUModel *m; 5249 const X86CPUVersionDefinition *vdef; 5250 5251 /* AMD aliases are handled at runtime based on CPUID vendor, so 5252 * they shouldn't be set on the CPU model table. 5253 */ 5254 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES)); 5255 /* catch mistakes instead of silently truncating model_id when too long */ 5256 assert(def->model_id && strlen(def->model_id) <= 48); 5257 5258 /* Unversioned model: */ 5259 m = g_new0(X86CPUModel, 1); 5260 m->cpudef = def; 5261 m->version = CPU_VERSION_AUTO; 5262 m->is_alias = true; 5263 x86_register_cpu_model_type(def->name, m); 5264 5265 /* Versioned models: */ 5266 5267 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) { 5268 X86CPUModel *m = g_new0(X86CPUModel, 1); 5269 g_autofree char *name = 5270 x86_cpu_versioned_model_name(def, vdef->version); 5271 m->cpudef = def; 5272 m->version = vdef->version; 5273 m->note = vdef->note; 5274 x86_register_cpu_model_type(name, m); 5275 5276 if (vdef->alias) { 5277 X86CPUModel *am = g_new0(X86CPUModel, 1); 5278 am->cpudef = def; 5279 am->version = vdef->version; 5280 am->is_alias = true; 5281 x86_register_cpu_model_type(vdef->alias, am); 5282 } 5283 } 5284 5285 } 5286 5287 uint32_t cpu_x86_virtual_addr_width(CPUX86State *env) 5288 { 5289 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) { 5290 return 57; /* 57 bits virtual */ 5291 } else { 5292 return 48; /* 48 bits virtual */ 5293 } 5294 } 5295 5296 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, 5297 uint32_t *eax, uint32_t *ebx, 5298 uint32_t *ecx, uint32_t *edx) 5299 { 5300 X86CPU *cpu = env_archcpu(env); 5301 CPUState *cs = env_cpu(env); 5302 uint32_t die_offset; 5303 uint32_t limit; 5304 uint32_t signature[3]; 5305 X86CPUTopoInfo topo_info; 5306 5307 topo_info.dies_per_pkg = env->nr_dies; 5308 topo_info.cores_per_die = cs->nr_cores; 5309 topo_info.threads_per_core = cs->nr_threads; 5310 5311 /* Calculate & apply limits for different index ranges */ 5312 if (index >= 0xC0000000) { 5313 limit = env->cpuid_xlevel2; 5314 } else if (index >= 0x80000000) { 5315 limit = env->cpuid_xlevel; 5316 } else if (index >= 0x40000000) { 5317 limit = 0x40000001; 5318 } else { 5319 limit = env->cpuid_level; 5320 } 5321 5322 if (index > limit) { 5323 /* Intel documentation states that invalid EAX input will 5324 * return the same information as EAX=cpuid_level 5325 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID) 5326 */ 5327 index = env->cpuid_level; 5328 } 5329 5330 switch(index) { 5331 case 0: 5332 *eax = env->cpuid_level; 5333 *ebx = env->cpuid_vendor1; 5334 *edx = env->cpuid_vendor2; 5335 *ecx = env->cpuid_vendor3; 5336 break; 5337 case 1: 5338 *eax = env->cpuid_version; 5339 *ebx = (cpu->apic_id << 24) | 5340 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ 5341 *ecx = env->features[FEAT_1_ECX]; 5342 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) { 5343 *ecx |= CPUID_EXT_OSXSAVE; 5344 } 5345 *edx = env->features[FEAT_1_EDX]; 5346 if (cs->nr_cores * cs->nr_threads > 1) { 5347 *ebx |= (cs->nr_cores * cs->nr_threads) << 16; 5348 *edx |= CPUID_HT; 5349 } 5350 if (!cpu->enable_pmu) { 5351 *ecx &= ~CPUID_EXT_PDCM; 5352 } 5353 break; 5354 case 2: 5355 /* cache info: needed for Pentium Pro compatibility */ 5356 if (cpu->cache_info_passthrough) { 5357 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5358 break; 5359 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5360 *eax = *ebx = *ecx = *edx = 0; 5361 break; 5362 } 5363 *eax = 1; /* Number of CPUID[EAX=2] calls required */ 5364 *ebx = 0; 5365 if (!cpu->enable_l3_cache) { 5366 *ecx = 0; 5367 } else { 5368 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache); 5369 } 5370 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) | 5371 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) | 5372 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache)); 5373 break; 5374 case 4: 5375 /* cache info: needed for Core compatibility */ 5376 if (cpu->cache_info_passthrough) { 5377 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5378 /* 5379 * QEMU has its own number of cores/logical cpus, 5380 * set 24..14, 31..26 bit to configured values 5381 */ 5382 if (*eax & 31) { 5383 int host_vcpus_per_cache = 1 + ((*eax & 0x3FFC000) >> 14); 5384 int vcpus_per_socket = env->nr_dies * cs->nr_cores * 5385 cs->nr_threads; 5386 if (cs->nr_cores > 1) { 5387 *eax &= ~0xFC000000; 5388 *eax |= (pow2ceil(cs->nr_cores) - 1) << 26; 5389 } 5390 if (host_vcpus_per_cache > vcpus_per_socket) { 5391 *eax &= ~0x3FFC000; 5392 *eax |= (pow2ceil(vcpus_per_socket) - 1) << 14; 5393 } 5394 } 5395 } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { 5396 *eax = *ebx = *ecx = *edx = 0; 5397 } else { 5398 *eax = 0; 5399 switch (count) { 5400 case 0: /* L1 dcache info */ 5401 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, 5402 1, cs->nr_cores, 5403 eax, ebx, ecx, edx); 5404 break; 5405 case 1: /* L1 icache info */ 5406 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, 5407 1, cs->nr_cores, 5408 eax, ebx, ecx, edx); 5409 break; 5410 case 2: /* L2 cache info */ 5411 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, 5412 cs->nr_threads, cs->nr_cores, 5413 eax, ebx, ecx, edx); 5414 break; 5415 case 3: /* L3 cache info */ 5416 die_offset = apicid_die_offset(&topo_info); 5417 if (cpu->enable_l3_cache) { 5418 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, 5419 (1 << die_offset), cs->nr_cores, 5420 eax, ebx, ecx, edx); 5421 break; 5422 } 5423 /* fall through */ 5424 default: /* end of info */ 5425 *eax = *ebx = *ecx = *edx = 0; 5426 break; 5427 } 5428 } 5429 break; 5430 case 5: 5431 /* MONITOR/MWAIT Leaf */ 5432 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ 5433 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */ 5434 *ecx = cpu->mwait.ecx; /* flags */ 5435 *edx = cpu->mwait.edx; /* mwait substates */ 5436 break; 5437 case 6: 5438 /* Thermal and Power Leaf */ 5439 *eax = env->features[FEAT_6_EAX]; 5440 *ebx = 0; 5441 *ecx = 0; 5442 *edx = 0; 5443 break; 5444 case 7: 5445 /* Structured Extended Feature Flags Enumeration Leaf */ 5446 if (count == 0) { 5447 /* Maximum ECX value for sub-leaves */ 5448 *eax = env->cpuid_level_func7; 5449 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */ 5450 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */ 5451 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) { 5452 *ecx |= CPUID_7_0_ECX_OSPKE; 5453 } 5454 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */ 5455 5456 /* 5457 * SGX cannot be emulated in software. If hardware does not 5458 * support enabling SGX and/or SGX flexible launch control, 5459 * then we need to update the VM's CPUID values accordingly. 5460 */ 5461 if ((*ebx & CPUID_7_0_EBX_SGX) && 5462 (!kvm_enabled() || 5463 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_EBX) & 5464 CPUID_7_0_EBX_SGX))) { 5465 *ebx &= ~CPUID_7_0_EBX_SGX; 5466 } 5467 5468 if ((*ecx & CPUID_7_0_ECX_SGX_LC) && 5469 (!(*ebx & CPUID_7_0_EBX_SGX) || !kvm_enabled() || 5470 !(kvm_arch_get_supported_cpuid(cs->kvm_state, 0x7, 0, R_ECX) & 5471 CPUID_7_0_ECX_SGX_LC))) { 5472 *ecx &= ~CPUID_7_0_ECX_SGX_LC; 5473 } 5474 } else if (count == 1) { 5475 *eax = env->features[FEAT_7_1_EAX]; 5476 *ebx = 0; 5477 *ecx = 0; 5478 *edx = 0; 5479 } else { 5480 *eax = 0; 5481 *ebx = 0; 5482 *ecx = 0; 5483 *edx = 0; 5484 } 5485 break; 5486 case 9: 5487 /* Direct Cache Access Information Leaf */ 5488 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */ 5489 *ebx = 0; 5490 *ecx = 0; 5491 *edx = 0; 5492 break; 5493 case 0xA: 5494 /* Architectural Performance Monitoring Leaf */ 5495 if (accel_uses_host_cpuid() && cpu->enable_pmu) { 5496 x86_cpu_get_supported_cpuid(0xA, count, eax, ebx, ecx, edx); 5497 } else { 5498 *eax = 0; 5499 *ebx = 0; 5500 *ecx = 0; 5501 *edx = 0; 5502 } 5503 break; 5504 case 0xB: 5505 /* Extended Topology Enumeration Leaf */ 5506 if (!cpu->enable_cpuid_0xb) { 5507 *eax = *ebx = *ecx = *edx = 0; 5508 break; 5509 } 5510 5511 *ecx = count & 0xff; 5512 *edx = cpu->apic_id; 5513 5514 switch (count) { 5515 case 0: 5516 *eax = apicid_core_offset(&topo_info); 5517 *ebx = cs->nr_threads; 5518 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5519 break; 5520 case 1: 5521 *eax = apicid_pkg_offset(&topo_info); 5522 *ebx = cs->nr_cores * cs->nr_threads; 5523 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5524 break; 5525 default: 5526 *eax = 0; 5527 *ebx = 0; 5528 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5529 } 5530 5531 assert(!(*eax & ~0x1f)); 5532 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5533 break; 5534 case 0x1C: 5535 if (accel_uses_host_cpuid() && cpu->enable_pmu && 5536 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5537 x86_cpu_get_supported_cpuid(0x1C, 0, eax, ebx, ecx, edx); 5538 *edx = 0; 5539 } 5540 break; 5541 case 0x1F: 5542 /* V2 Extended Topology Enumeration Leaf */ 5543 if (env->nr_dies < 2) { 5544 *eax = *ebx = *ecx = *edx = 0; 5545 break; 5546 } 5547 5548 *ecx = count & 0xff; 5549 *edx = cpu->apic_id; 5550 switch (count) { 5551 case 0: 5552 *eax = apicid_core_offset(&topo_info); 5553 *ebx = cs->nr_threads; 5554 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT; 5555 break; 5556 case 1: 5557 *eax = apicid_die_offset(&topo_info); 5558 *ebx = cs->nr_cores * cs->nr_threads; 5559 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE; 5560 break; 5561 case 2: 5562 *eax = apicid_pkg_offset(&topo_info); 5563 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads; 5564 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE; 5565 break; 5566 default: 5567 *eax = 0; 5568 *ebx = 0; 5569 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID; 5570 } 5571 assert(!(*eax & ~0x1f)); 5572 *ebx &= 0xffff; /* The count doesn't need to be reliable. */ 5573 break; 5574 case 0xD: { 5575 /* Processor Extended State */ 5576 *eax = 0; 5577 *ebx = 0; 5578 *ecx = 0; 5579 *edx = 0; 5580 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 5581 break; 5582 } 5583 5584 if (count == 0) { 5585 *ecx = xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), false); 5586 *eax = env->features[FEAT_XSAVE_XCR0_LO]; 5587 *edx = env->features[FEAT_XSAVE_XCR0_HI]; 5588 /* 5589 * The initial value of xcr0 and ebx == 0, On host without kvm 5590 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0 5591 * even through guest update xcr0, this will crash some legacy guest 5592 * (e.g., CentOS 6), So set ebx == ecx to workaroud it. 5593 */ 5594 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, false); 5595 } else if (count == 1) { 5596 uint64_t xstate = x86_cpu_xsave_xcr0_components(cpu) | 5597 x86_cpu_xsave_xss_components(cpu); 5598 5599 *eax = env->features[FEAT_XSAVE]; 5600 *ebx = xsave_area_size(xstate, true); 5601 *ecx = env->features[FEAT_XSAVE_XSS_LO]; 5602 *edx = env->features[FEAT_XSAVE_XSS_HI]; 5603 if (kvm_enabled() && cpu->enable_pmu && 5604 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR) && 5605 (*eax & CPUID_XSAVE_XSAVES)) { 5606 *ecx |= XSTATE_ARCH_LBR_MASK; 5607 } else { 5608 *ecx &= ~XSTATE_ARCH_LBR_MASK; 5609 } 5610 } else if (count == 0xf && 5611 accel_uses_host_cpuid() && cpu->enable_pmu && 5612 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) { 5613 x86_cpu_get_supported_cpuid(0xD, count, eax, ebx, ecx, edx); 5614 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { 5615 const ExtSaveArea *esa = &x86_ext_save_areas[count]; 5616 5617 if (x86_cpu_xsave_xcr0_components(cpu) & (1ULL << count)) { 5618 *eax = esa->size; 5619 *ebx = esa->offset; 5620 *ecx = esa->ecx & 5621 (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); 5622 } else if (x86_cpu_xsave_xss_components(cpu) & (1ULL << count)) { 5623 *eax = esa->size; 5624 *ebx = 0; 5625 *ecx = 1; 5626 } 5627 } 5628 break; 5629 } 5630 case 0x12: 5631 #ifndef CONFIG_USER_ONLY 5632 if (!kvm_enabled() || 5633 !(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX)) { 5634 *eax = *ebx = *ecx = *edx = 0; 5635 break; 5636 } 5637 5638 /* 5639 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve 5640 * the EPC properties, e.g. confidentiality and integrity, from the 5641 * host's first EPC section, i.e. assume there is one EPC section or 5642 * that all EPC sections have the same security properties. 5643 */ 5644 if (count > 1) { 5645 uint64_t epc_addr, epc_size; 5646 5647 if (sgx_epc_get_section(count - 2, &epc_addr, &epc_size)) { 5648 *eax = *ebx = *ecx = *edx = 0; 5649 break; 5650 } 5651 host_cpuid(index, 2, eax, ebx, ecx, edx); 5652 *eax = (uint32_t)(epc_addr & 0xfffff000) | 0x1; 5653 *ebx = (uint32_t)(epc_addr >> 32); 5654 *ecx = (uint32_t)(epc_size & 0xfffff000) | (*ecx & 0xf); 5655 *edx = (uint32_t)(epc_size >> 32); 5656 break; 5657 } 5658 5659 /* 5660 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware 5661 * and KVM, i.e. QEMU cannot emulate features to override what KVM 5662 * supports. Features can be further restricted by userspace, but not 5663 * made more permissive. 5664 */ 5665 x86_cpu_get_supported_cpuid(0x12, count, eax, ebx, ecx, edx); 5666 5667 if (count == 0) { 5668 *eax &= env->features[FEAT_SGX_12_0_EAX]; 5669 *ebx &= env->features[FEAT_SGX_12_0_EBX]; 5670 } else { 5671 *eax &= env->features[FEAT_SGX_12_1_EAX]; 5672 *ebx &= 0; /* ebx reserve */ 5673 *ecx &= env->features[FEAT_XSAVE_XSS_LO]; 5674 *edx &= env->features[FEAT_XSAVE_XSS_HI]; 5675 5676 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */ 5677 *ecx |= XSTATE_FP_MASK | XSTATE_SSE_MASK; 5678 5679 /* Access to PROVISIONKEY requires additional credentials. */ 5680 if ((*eax & (1U << 4)) && 5681 !kvm_enable_sgx_provisioning(cs->kvm_state)) { 5682 *eax &= ~(1U << 4); 5683 } 5684 } 5685 #endif 5686 break; 5687 case 0x14: { 5688 /* Intel Processor Trace Enumeration */ 5689 *eax = 0; 5690 *ebx = 0; 5691 *ecx = 0; 5692 *edx = 0; 5693 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) || 5694 !kvm_enabled()) { 5695 break; 5696 } 5697 5698 if (count == 0) { 5699 *eax = INTEL_PT_MAX_SUBLEAF; 5700 *ebx = INTEL_PT_MINIMAL_EBX; 5701 *ecx = INTEL_PT_MINIMAL_ECX; 5702 if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) { 5703 *ecx |= CPUID_14_0_ECX_LIP; 5704 } 5705 } else if (count == 1) { 5706 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; 5707 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; 5708 } 5709 break; 5710 } 5711 case 0x1D: { 5712 /* AMX TILE */ 5713 *eax = 0; 5714 *ebx = 0; 5715 *ecx = 0; 5716 *edx = 0; 5717 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5718 break; 5719 } 5720 5721 if (count == 0) { 5722 /* Highest numbered palette subleaf */ 5723 *eax = INTEL_AMX_TILE_MAX_SUBLEAF; 5724 } else if (count == 1) { 5725 *eax = INTEL_AMX_TOTAL_TILE_BYTES | 5726 (INTEL_AMX_BYTES_PER_TILE << 16); 5727 *ebx = INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES << 16); 5728 *ecx = INTEL_AMX_TILE_MAX_ROWS; 5729 } 5730 break; 5731 } 5732 case 0x1E: { 5733 /* AMX TMUL */ 5734 *eax = 0; 5735 *ebx = 0; 5736 *ecx = 0; 5737 *edx = 0; 5738 if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { 5739 break; 5740 } 5741 5742 if (count == 0) { 5743 /* Highest numbered palette subleaf */ 5744 *ebx = INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); 5745 } 5746 break; 5747 } 5748 case 0x40000000: 5749 /* 5750 * CPUID code in kvm_arch_init_vcpu() ignores stuff 5751 * set here, but we restrict to TCG none the less. 5752 */ 5753 if (tcg_enabled() && cpu->expose_tcg) { 5754 memcpy(signature, "TCGTCGTCGTCG", 12); 5755 *eax = 0x40000001; 5756 *ebx = signature[0]; 5757 *ecx = signature[1]; 5758 *edx = signature[2]; 5759 } else { 5760 *eax = 0; 5761 *ebx = 0; 5762 *ecx = 0; 5763 *edx = 0; 5764 } 5765 break; 5766 case 0x40000001: 5767 *eax = 0; 5768 *ebx = 0; 5769 *ecx = 0; 5770 *edx = 0; 5771 break; 5772 case 0x80000000: 5773 *eax = env->cpuid_xlevel; 5774 *ebx = env->cpuid_vendor1; 5775 *edx = env->cpuid_vendor2; 5776 *ecx = env->cpuid_vendor3; 5777 break; 5778 case 0x80000001: 5779 *eax = env->cpuid_version; 5780 *ebx = env->cpuid_brand_id; 5781 *ecx = env->features[FEAT_8000_0001_ECX]; 5782 *edx = env->features[FEAT_8000_0001_EDX]; 5783 5784 /* The Linux kernel checks for the CMPLegacy bit and 5785 * discards multiple thread information if it is set. 5786 * So don't set it here for Intel to make Linux guests happy. 5787 */ 5788 if (cs->nr_cores * cs->nr_threads > 1) { 5789 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 || 5790 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 || 5791 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) { 5792 *ecx |= 1 << 1; /* CmpLegacy bit */ 5793 } 5794 } 5795 break; 5796 case 0x80000002: 5797 case 0x80000003: 5798 case 0x80000004: 5799 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; 5800 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; 5801 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; 5802 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; 5803 break; 5804 case 0x80000005: 5805 /* cache info (L1 cache) */ 5806 if (cpu->cache_info_passthrough) { 5807 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5808 break; 5809 } 5810 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | 5811 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); 5812 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | 5813 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); 5814 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache); 5815 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache); 5816 break; 5817 case 0x80000006: 5818 /* cache info (L2 cache) */ 5819 if (cpu->cache_info_passthrough) { 5820 x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); 5821 break; 5822 } 5823 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | 5824 (L2_DTLB_2M_ENTRIES << 16) | 5825 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | 5826 (L2_ITLB_2M_ENTRIES); 5827 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | 5828 (L2_DTLB_4K_ENTRIES << 16) | 5829 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | 5830 (L2_ITLB_4K_ENTRIES); 5831 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, 5832 cpu->enable_l3_cache ? 5833 env->cache_info_amd.l3_cache : NULL, 5834 ecx, edx); 5835 break; 5836 case 0x80000007: 5837 *eax = 0; 5838 *ebx = 0; 5839 *ecx = 0; 5840 *edx = env->features[FEAT_8000_0007_EDX]; 5841 break; 5842 case 0x80000008: 5843 /* virtual & phys address size in low 2 bytes. */ 5844 *eax = cpu->phys_bits; 5845 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 5846 /* 64 bit processor */ 5847 *eax |= (cpu_x86_virtual_addr_width(env) << 8); 5848 } 5849 *ebx = env->features[FEAT_8000_0008_EBX]; 5850 if (cs->nr_cores * cs->nr_threads > 1) { 5851 /* 5852 * Bits 15:12 is "The number of bits in the initial 5853 * Core::X86::Apic::ApicId[ApicId] value that indicate 5854 * thread ID within a package". 5855 * Bits 7:0 is "The number of threads in the package is NC+1" 5856 */ 5857 *ecx = (apicid_pkg_offset(&topo_info) << 12) | 5858 ((cs->nr_cores * cs->nr_threads) - 1); 5859 } else { 5860 *ecx = 0; 5861 } 5862 *edx = 0; 5863 break; 5864 case 0x8000000A: 5865 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 5866 *eax = 0x00000001; /* SVM Revision */ 5867 *ebx = 0x00000010; /* nr of ASIDs */ 5868 *ecx = 0; 5869 *edx = env->features[FEAT_SVM]; /* optional features */ 5870 } else { 5871 *eax = 0; 5872 *ebx = 0; 5873 *ecx = 0; 5874 *edx = 0; 5875 } 5876 break; 5877 case 0x8000001D: 5878 *eax = 0; 5879 if (cpu->cache_info_passthrough) { 5880 x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); 5881 break; 5882 } 5883 switch (count) { 5884 case 0: /* L1 dcache info */ 5885 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, 5886 &topo_info, eax, ebx, ecx, edx); 5887 break; 5888 case 1: /* L1 icache info */ 5889 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, 5890 &topo_info, eax, ebx, ecx, edx); 5891 break; 5892 case 2: /* L2 cache info */ 5893 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, 5894 &topo_info, eax, ebx, ecx, edx); 5895 break; 5896 case 3: /* L3 cache info */ 5897 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, 5898 &topo_info, eax, ebx, ecx, edx); 5899 break; 5900 default: /* end of info */ 5901 *eax = *ebx = *ecx = *edx = 0; 5902 break; 5903 } 5904 break; 5905 case 0x8000001E: 5906 if (cpu->core_id <= 255) { 5907 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); 5908 } else { 5909 *eax = 0; 5910 *ebx = 0; 5911 *ecx = 0; 5912 *edx = 0; 5913 } 5914 break; 5915 case 0xC0000000: 5916 *eax = env->cpuid_xlevel2; 5917 *ebx = 0; 5918 *ecx = 0; 5919 *edx = 0; 5920 break; 5921 case 0xC0000001: 5922 /* Support for VIA CPU's CPUID instruction */ 5923 *eax = env->cpuid_version; 5924 *ebx = 0; 5925 *ecx = 0; 5926 *edx = env->features[FEAT_C000_0001_EDX]; 5927 break; 5928 case 0xC0000002: 5929 case 0xC0000003: 5930 case 0xC0000004: 5931 /* Reserved for the future, and now filled with zero */ 5932 *eax = 0; 5933 *ebx = 0; 5934 *ecx = 0; 5935 *edx = 0; 5936 break; 5937 case 0x8000001F: 5938 *eax = *ebx = *ecx = *edx = 0; 5939 if (sev_enabled()) { 5940 *eax = 0x2; 5941 *eax |= sev_es_enabled() ? 0x8 : 0; 5942 *ebx = sev_get_cbit_position(); 5943 *ebx |= sev_get_reduced_phys_bits() << 6; 5944 } 5945 break; 5946 default: 5947 /* reserved values: zero */ 5948 *eax = 0; 5949 *ebx = 0; 5950 *ecx = 0; 5951 *edx = 0; 5952 break; 5953 } 5954 } 5955 5956 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State *env) 5957 { 5958 #ifndef CONFIG_USER_ONLY 5959 /* Those default values are defined in Skylake HW */ 5960 env->msr_ia32_sgxlepubkeyhash[0] = 0xa6053e051270b7acULL; 5961 env->msr_ia32_sgxlepubkeyhash[1] = 0x6cfbe8ba8b3b413dULL; 5962 env->msr_ia32_sgxlepubkeyhash[2] = 0xc4916d99f2b3735dULL; 5963 env->msr_ia32_sgxlepubkeyhash[3] = 0xd4f8c05909f9bb3bULL; 5964 #endif 5965 } 5966 5967 static void x86_cpu_reset(DeviceState *dev) 5968 { 5969 CPUState *s = CPU(dev); 5970 X86CPU *cpu = X86_CPU(s); 5971 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); 5972 CPUX86State *env = &cpu->env; 5973 target_ulong cr4; 5974 uint64_t xcr0; 5975 int i; 5976 5977 xcc->parent_reset(dev); 5978 5979 memset(env, 0, offsetof(CPUX86State, end_reset_fields)); 5980 5981 env->old_exception = -1; 5982 5983 /* init to reset state */ 5984 env->int_ctl = 0; 5985 env->hflags2 |= HF2_GIF_MASK; 5986 env->hflags2 |= HF2_VGIF_MASK; 5987 env->hflags &= ~HF_GUEST_MASK; 5988 5989 cpu_x86_update_cr0(env, 0x60000010); 5990 env->a20_mask = ~0x0; 5991 env->smbase = 0x30000; 5992 env->msr_smi_count = 0; 5993 5994 env->idt.limit = 0xffff; 5995 env->gdt.limit = 0xffff; 5996 env->ldt.limit = 0xffff; 5997 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT); 5998 env->tr.limit = 0xffff; 5999 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT); 6000 6001 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, 6002 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | 6003 DESC_R_MASK | DESC_A_MASK); 6004 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, 6005 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6006 DESC_A_MASK); 6007 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, 6008 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6009 DESC_A_MASK); 6010 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, 6011 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6012 DESC_A_MASK); 6013 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, 6014 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6015 DESC_A_MASK); 6016 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, 6017 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | 6018 DESC_A_MASK); 6019 6020 env->eip = 0xfff0; 6021 env->regs[R_EDX] = env->cpuid_version; 6022 6023 env->eflags = 0x2; 6024 6025 /* FPU init */ 6026 for (i = 0; i < 8; i++) { 6027 env->fptags[i] = 1; 6028 } 6029 cpu_set_fpuc(env, 0x37f); 6030 6031 env->mxcsr = 0x1f80; 6032 /* All units are in INIT state. */ 6033 env->xstate_bv = 0; 6034 6035 env->pat = 0x0007040600070406ULL; 6036 6037 if (kvm_enabled()) { 6038 /* 6039 * KVM handles TSC = 0 specially and thinks we are hot-plugging 6040 * a new CPU, use 1 instead to force a reset. 6041 */ 6042 if (env->tsc != 0) { 6043 env->tsc = 1; 6044 } 6045 } else { 6046 env->tsc = 0; 6047 } 6048 6049 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; 6050 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) { 6051 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT; 6052 } 6053 6054 memset(env->dr, 0, sizeof(env->dr)); 6055 env->dr[6] = DR6_FIXED_1; 6056 env->dr[7] = DR7_FIXED_1; 6057 cpu_breakpoint_remove_all(s, BP_CPU); 6058 cpu_watchpoint_remove_all(s, BP_CPU); 6059 6060 cr4 = 0; 6061 xcr0 = XSTATE_FP_MASK; 6062 6063 #ifdef CONFIG_USER_ONLY 6064 /* Enable all the features for user-mode. */ 6065 if (env->features[FEAT_1_EDX] & CPUID_SSE) { 6066 xcr0 |= XSTATE_SSE_MASK; 6067 } 6068 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6069 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6070 if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { 6071 continue; 6072 } 6073 if (env->features[esa->feature] & esa->bits) { 6074 xcr0 |= 1ull << i; 6075 } 6076 } 6077 6078 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) { 6079 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK; 6080 } 6081 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) { 6082 cr4 |= CR4_FSGSBASE_MASK; 6083 } 6084 #endif 6085 6086 env->xcr0 = xcr0; 6087 cpu_x86_update_cr4(env, cr4); 6088 6089 /* 6090 * SDM 11.11.5 requires: 6091 * - IA32_MTRR_DEF_TYPE MSR.E = 0 6092 * - IA32_MTRR_PHYSMASKn.V = 0 6093 * All other bits are undefined. For simplification, zero it all. 6094 */ 6095 env->mtrr_deftype = 0; 6096 memset(env->mtrr_var, 0, sizeof(env->mtrr_var)); 6097 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed)); 6098 6099 env->interrupt_injected = -1; 6100 env->exception_nr = -1; 6101 env->exception_pending = 0; 6102 env->exception_injected = 0; 6103 env->exception_has_payload = false; 6104 env->exception_payload = 0; 6105 env->nmi_injected = false; 6106 env->triple_fault_pending = false; 6107 #if !defined(CONFIG_USER_ONLY) 6108 /* We hard-wire the BSP to the first CPU. */ 6109 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0); 6110 6111 s->halted = !cpu_is_bsp(cpu); 6112 6113 if (kvm_enabled()) { 6114 kvm_arch_reset_vcpu(cpu); 6115 } 6116 6117 x86_cpu_set_sgxlepubkeyhash(env); 6118 6119 env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT; 6120 6121 #endif 6122 } 6123 6124 void x86_cpu_after_reset(X86CPU *cpu) 6125 { 6126 #ifndef CONFIG_USER_ONLY 6127 if (kvm_enabled()) { 6128 kvm_arch_after_reset_vcpu(cpu); 6129 } 6130 6131 if (cpu->apic_state) { 6132 device_cold_reset(cpu->apic_state); 6133 } 6134 #endif 6135 } 6136 6137 static void mce_init(X86CPU *cpu) 6138 { 6139 CPUX86State *cenv = &cpu->env; 6140 unsigned int bank; 6141 6142 if (((cenv->cpuid_version >> 8) & 0xf) >= 6 6143 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == 6144 (CPUID_MCE | CPUID_MCA)) { 6145 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF | 6146 (cpu->enable_lmce ? MCG_LMCE_P : 0); 6147 cenv->mcg_ctl = ~(uint64_t)0; 6148 for (bank = 0; bank < MCE_BANKS_DEF; bank++) { 6149 cenv->mce_banks[bank * 4] = ~(uint64_t)0; 6150 } 6151 } 6152 } 6153 6154 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value) 6155 { 6156 if (*min < value) { 6157 *min = value; 6158 } 6159 } 6160 6161 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */ 6162 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w) 6163 { 6164 CPUX86State *env = &cpu->env; 6165 FeatureWordInfo *fi = &feature_word_info[w]; 6166 uint32_t eax = fi->cpuid.eax; 6167 uint32_t region = eax & 0xF0000000; 6168 6169 assert(feature_word_info[w].type == CPUID_FEATURE_WORD); 6170 if (!env->features[w]) { 6171 return; 6172 } 6173 6174 switch (region) { 6175 case 0x00000000: 6176 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax); 6177 break; 6178 case 0x80000000: 6179 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax); 6180 break; 6181 case 0xC0000000: 6182 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax); 6183 break; 6184 } 6185 6186 if (eax == 7) { 6187 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7, 6188 fi->cpuid.ecx); 6189 } 6190 } 6191 6192 /* Calculate XSAVE components based on the configured CPU feature flags */ 6193 static void x86_cpu_enable_xsave_components(X86CPU *cpu) 6194 { 6195 CPUX86State *env = &cpu->env; 6196 int i; 6197 uint64_t mask; 6198 static bool request_perm; 6199 6200 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { 6201 env->features[FEAT_XSAVE_XCR0_LO] = 0; 6202 env->features[FEAT_XSAVE_XCR0_HI] = 0; 6203 return; 6204 } 6205 6206 mask = 0; 6207 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { 6208 const ExtSaveArea *esa = &x86_ext_save_areas[i]; 6209 if (env->features[esa->feature] & esa->bits) { 6210 mask |= (1ULL << i); 6211 } 6212 } 6213 6214 /* Only request permission for first vcpu */ 6215 if (kvm_enabled() && !request_perm) { 6216 kvm_request_xsave_components(cpu, mask); 6217 request_perm = true; 6218 } 6219 6220 env->features[FEAT_XSAVE_XCR0_LO] = mask & CPUID_XSTATE_XCR0_MASK; 6221 env->features[FEAT_XSAVE_XCR0_HI] = mask >> 32; 6222 env->features[FEAT_XSAVE_XSS_LO] = mask & CPUID_XSTATE_XSS_MASK; 6223 env->features[FEAT_XSAVE_XSS_HI] = mask >> 32; 6224 } 6225 6226 /***** Steps involved on loading and filtering CPUID data 6227 * 6228 * When initializing and realizing a CPU object, the steps 6229 * involved in setting up CPUID data are: 6230 * 6231 * 1) Loading CPU model definition (X86CPUDefinition). This is 6232 * implemented by x86_cpu_load_model() and should be completely 6233 * transparent, as it is done automatically by instance_init. 6234 * No code should need to look at X86CPUDefinition structs 6235 * outside instance_init. 6236 * 6237 * 2) CPU expansion. This is done by realize before CPUID 6238 * filtering, and will make sure host/accelerator data is 6239 * loaded for CPU models that depend on host capabilities 6240 * (e.g. "host"). Done by x86_cpu_expand_features(). 6241 * 6242 * 3) CPUID filtering. This initializes extra data related to 6243 * CPUID, and checks if the host supports all capabilities 6244 * required by the CPU. Runnability of a CPU model is 6245 * determined at this step. Done by x86_cpu_filter_features(). 6246 * 6247 * Some operations don't require all steps to be performed. 6248 * More precisely: 6249 * 6250 * - CPU instance creation (instance_init) will run only CPU 6251 * model loading. CPU expansion can't run at instance_init-time 6252 * because host/accelerator data may be not available yet. 6253 * - CPU realization will perform both CPU model expansion and CPUID 6254 * filtering, and return an error in case one of them fails. 6255 * - query-cpu-definitions needs to run all 3 steps. It needs 6256 * to run CPUID filtering, as the 'unavailable-features' 6257 * field is set based on the filtering results. 6258 * - The query-cpu-model-expansion QMP command only needs to run 6259 * CPU model loading and CPU expansion. It should not filter 6260 * any CPUID data based on host capabilities. 6261 */ 6262 6263 /* Expand CPU configuration data, based on configured features 6264 * and host/accelerator capabilities when appropriate. 6265 */ 6266 void x86_cpu_expand_features(X86CPU *cpu, Error **errp) 6267 { 6268 CPUX86State *env = &cpu->env; 6269 FeatureWord w; 6270 int i; 6271 GList *l; 6272 6273 for (l = plus_features; l; l = l->next) { 6274 const char *prop = l->data; 6275 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) { 6276 return; 6277 } 6278 } 6279 6280 for (l = minus_features; l; l = l->next) { 6281 const char *prop = l->data; 6282 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) { 6283 return; 6284 } 6285 } 6286 6287 /*TODO: Now cpu->max_features doesn't overwrite features 6288 * set using QOM properties, and we can convert 6289 * plus_features & minus_features to global properties 6290 * inside x86_cpu_parse_featurestr() too. 6291 */ 6292 if (cpu->max_features) { 6293 for (w = 0; w < FEATURE_WORDS; w++) { 6294 /* Override only features that weren't set explicitly 6295 * by the user. 6296 */ 6297 env->features[w] |= 6298 x86_cpu_get_supported_feature_word(w, cpu->migratable) & 6299 ~env->user_features[w] & 6300 ~feature_word_info[w].no_autoenable_flags; 6301 } 6302 } 6303 6304 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) { 6305 FeatureDep *d = &feature_dependencies[i]; 6306 if (!(env->features[d->from.index] & d->from.mask)) { 6307 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask; 6308 6309 /* Not an error unless the dependent feature was added explicitly. */ 6310 mark_unavailable_features(cpu, d->to.index, 6311 unavailable_features & env->user_features[d->to.index], 6312 "This feature depends on other features that were not requested"); 6313 6314 env->features[d->to.index] &= ~unavailable_features; 6315 } 6316 } 6317 6318 if (!kvm_enabled() || !cpu->expose_kvm) { 6319 env->features[FEAT_KVM] = 0; 6320 } 6321 6322 x86_cpu_enable_xsave_components(cpu); 6323 6324 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */ 6325 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX); 6326 if (cpu->full_cpuid_auto_level) { 6327 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX); 6328 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX); 6329 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX); 6330 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX); 6331 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX); 6332 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX); 6333 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX); 6334 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX); 6335 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX); 6336 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX); 6337 x86_cpu_adjust_feat_level(cpu, FEAT_SVM); 6338 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); 6339 6340 /* Intel Processor Trace requires CPUID[0x14] */ 6341 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { 6342 if (cpu->intel_pt_auto_level) { 6343 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); 6344 } else if (cpu->env.cpuid_min_level < 0x14) { 6345 mark_unavailable_features(cpu, FEAT_7_0_EBX, 6346 CPUID_7_0_EBX_INTEL_PT, 6347 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\""); 6348 } 6349 } 6350 6351 /* 6352 * Intel CPU topology with multi-dies support requires CPUID[0x1F]. 6353 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect 6354 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless 6355 * cpu->vendor_cpuid_only has been unset for compatibility with older 6356 * machine types. 6357 */ 6358 if ((env->nr_dies > 1) && 6359 (IS_INTEL_CPU(env) || !cpu->vendor_cpuid_only)) { 6360 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F); 6361 } 6362 6363 /* SVM requires CPUID[0x8000000A] */ 6364 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { 6365 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); 6366 } 6367 6368 /* SEV requires CPUID[0x8000001F] */ 6369 if (sev_enabled()) { 6370 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F); 6371 } 6372 6373 /* SGX requires CPUID[0x12] for EPC enumeration */ 6374 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SGX) { 6375 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x12); 6376 } 6377 } 6378 6379 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */ 6380 if (env->cpuid_level_func7 == UINT32_MAX) { 6381 env->cpuid_level_func7 = env->cpuid_min_level_func7; 6382 } 6383 if (env->cpuid_level == UINT32_MAX) { 6384 env->cpuid_level = env->cpuid_min_level; 6385 } 6386 if (env->cpuid_xlevel == UINT32_MAX) { 6387 env->cpuid_xlevel = env->cpuid_min_xlevel; 6388 } 6389 if (env->cpuid_xlevel2 == UINT32_MAX) { 6390 env->cpuid_xlevel2 = env->cpuid_min_xlevel2; 6391 } 6392 6393 if (kvm_enabled()) { 6394 kvm_hyperv_expand_features(cpu, errp); 6395 } 6396 } 6397 6398 /* 6399 * Finishes initialization of CPUID data, filters CPU feature 6400 * words based on host availability of each feature. 6401 * 6402 * Returns: 0 if all flags are supported by the host, non-zero otherwise. 6403 */ 6404 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose) 6405 { 6406 CPUX86State *env = &cpu->env; 6407 FeatureWord w; 6408 const char *prefix = NULL; 6409 6410 if (verbose) { 6411 prefix = accel_uses_host_cpuid() 6412 ? "host doesn't support requested feature" 6413 : "TCG doesn't support requested feature"; 6414 } 6415 6416 for (w = 0; w < FEATURE_WORDS; w++) { 6417 uint64_t host_feat = 6418 x86_cpu_get_supported_feature_word(w, false); 6419 uint64_t requested_features = env->features[w]; 6420 uint64_t unavailable_features = requested_features & ~host_feat; 6421 mark_unavailable_features(cpu, w, unavailable_features, prefix); 6422 } 6423 6424 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && 6425 kvm_enabled()) { 6426 KVMState *s = CPU(cpu)->kvm_state; 6427 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); 6428 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); 6429 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); 6430 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); 6431 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); 6432 6433 if (!eax_0 || 6434 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) || 6435 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) || 6436 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) || 6437 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < 6438 INTEL_PT_ADDR_RANGES_NUM) || 6439 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) != 6440 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) || 6441 ((ecx_0 & CPUID_14_0_ECX_LIP) != 6442 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) { 6443 /* 6444 * Processor Trace capabilities aren't configurable, so if the 6445 * host can't emulate the capabilities we report on 6446 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host. 6447 */ 6448 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix); 6449 } 6450 } 6451 } 6452 6453 static void x86_cpu_hyperv_realize(X86CPU *cpu) 6454 { 6455 size_t len; 6456 6457 /* Hyper-V vendor id */ 6458 if (!cpu->hyperv_vendor) { 6459 object_property_set_str(OBJECT(cpu), "hv-vendor-id", "Microsoft Hv", 6460 &error_abort); 6461 } 6462 len = strlen(cpu->hyperv_vendor); 6463 if (len > 12) { 6464 warn_report("hv-vendor-id truncated to 12 characters"); 6465 len = 12; 6466 } 6467 memset(cpu->hyperv_vendor_id, 0, 12); 6468 memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len); 6469 6470 /* 'Hv#1' interface identification*/ 6471 cpu->hyperv_interface_id[0] = 0x31237648; 6472 cpu->hyperv_interface_id[1] = 0; 6473 cpu->hyperv_interface_id[2] = 0; 6474 cpu->hyperv_interface_id[3] = 0; 6475 6476 /* Hypervisor implementation limits */ 6477 cpu->hyperv_limits[0] = 64; 6478 cpu->hyperv_limits[1] = 0; 6479 cpu->hyperv_limits[2] = 0; 6480 } 6481 6482 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) 6483 { 6484 CPUState *cs = CPU(dev); 6485 X86CPU *cpu = X86_CPU(dev); 6486 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6487 CPUX86State *env = &cpu->env; 6488 Error *local_err = NULL; 6489 static bool ht_warned; 6490 unsigned requested_lbr_fmt; 6491 6492 if (cpu->apic_id == UNASSIGNED_APIC_ID) { 6493 error_setg(errp, "apic-id property was not initialized properly"); 6494 return; 6495 } 6496 6497 /* 6498 * Process Hyper-V enlightenments. 6499 * Note: this currently has to happen before the expansion of CPU features. 6500 */ 6501 x86_cpu_hyperv_realize(cpu); 6502 6503 x86_cpu_expand_features(cpu, &local_err); 6504 if (local_err) { 6505 goto out; 6506 } 6507 6508 /* 6509 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT 6510 * with user-provided setting. 6511 */ 6512 if (cpu->lbr_fmt != ~PERF_CAP_LBR_FMT) { 6513 if ((cpu->lbr_fmt & PERF_CAP_LBR_FMT) != cpu->lbr_fmt) { 6514 error_setg(errp, "invalid lbr-fmt"); 6515 return; 6516 } 6517 env->features[FEAT_PERF_CAPABILITIES] &= ~PERF_CAP_LBR_FMT; 6518 env->features[FEAT_PERF_CAPABILITIES] |= cpu->lbr_fmt; 6519 } 6520 6521 /* 6522 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and 6523 * 3)vPMU LBR format matches that of host setting. 6524 */ 6525 requested_lbr_fmt = 6526 env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_LBR_FMT; 6527 if (requested_lbr_fmt && kvm_enabled()) { 6528 uint64_t host_perf_cap = 6529 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES, false); 6530 unsigned host_lbr_fmt = host_perf_cap & PERF_CAP_LBR_FMT; 6531 6532 if (!cpu->enable_pmu) { 6533 error_setg(errp, "vPMU: LBR is unsupported without pmu=on"); 6534 return; 6535 } 6536 if (requested_lbr_fmt != host_lbr_fmt) { 6537 error_setg(errp, "vPMU: the lbr-fmt value (0x%x) does not match " 6538 "the host value (0x%x).", 6539 requested_lbr_fmt, host_lbr_fmt); 6540 return; 6541 } 6542 } 6543 6544 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid); 6545 6546 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) { 6547 error_setg(&local_err, 6548 accel_uses_host_cpuid() ? 6549 "Host doesn't support requested features" : 6550 "TCG doesn't support requested features"); 6551 goto out; 6552 } 6553 6554 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on 6555 * CPUID[1].EDX. 6556 */ 6557 if (IS_AMD_CPU(env)) { 6558 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES; 6559 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX] 6560 & CPUID_EXT2_AMD_ALIASES); 6561 } 6562 6563 x86_cpu_set_sgxlepubkeyhash(env); 6564 6565 /* 6566 * note: the call to the framework needs to happen after feature expansion, 6567 * but before the checks/modifications to ucode_rev, mwait, phys_bits. 6568 * These may be set by the accel-specific code, 6569 * and the results are subsequently checked / assumed in this function. 6570 */ 6571 cpu_exec_realizefn(cs, &local_err); 6572 if (local_err != NULL) { 6573 error_propagate(errp, local_err); 6574 return; 6575 } 6576 6577 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) { 6578 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6579 error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name); 6580 goto out; 6581 } 6582 6583 if (cpu->ucode_rev == 0) { 6584 /* 6585 * The default is the same as KVM's. Note that this check 6586 * needs to happen after the evenual setting of ucode_rev in 6587 * accel-specific code in cpu_exec_realizefn. 6588 */ 6589 if (IS_AMD_CPU(env)) { 6590 cpu->ucode_rev = 0x01000065; 6591 } else { 6592 cpu->ucode_rev = 0x100000000ULL; 6593 } 6594 } 6595 6596 /* 6597 * mwait extended info: needed for Core compatibility 6598 * We always wake on interrupt even if host does not have the capability. 6599 * 6600 * requires the accel-specific code in cpu_exec_realizefn to 6601 * have already acquired the CPUID data into cpu->mwait. 6602 */ 6603 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; 6604 6605 /* For 64bit systems think about the number of physical bits to present. 6606 * ideally this should be the same as the host; anything other than matching 6607 * the host can cause incorrect guest behaviour. 6608 * QEMU used to pick the magic value of 40 bits that corresponds to 6609 * consumer AMD devices but nothing else. 6610 * 6611 * Note that this code assumes features expansion has already been done 6612 * (as it checks for CPUID_EXT2_LM), and also assumes that potential 6613 * phys_bits adjustments to match the host have been already done in 6614 * accel-specific code in cpu_exec_realizefn. 6615 */ 6616 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { 6617 if (cpu->phys_bits && 6618 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || 6619 cpu->phys_bits < 32)) { 6620 error_setg(errp, "phys-bits should be between 32 and %u " 6621 " (but is %u)", 6622 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); 6623 return; 6624 } 6625 /* 6626 * 0 means it was not explicitly set by the user (or by machine 6627 * compat_props or by the host code in host-cpu.c). 6628 * In this case, the default is the value used by TCG (40). 6629 */ 6630 if (cpu->phys_bits == 0) { 6631 cpu->phys_bits = TCG_PHYS_ADDR_BITS; 6632 } 6633 } else { 6634 /* For 32 bit systems don't use the user set value, but keep 6635 * phys_bits consistent with what we tell the guest. 6636 */ 6637 if (cpu->phys_bits != 0) { 6638 error_setg(errp, "phys-bits is not user-configurable in 32 bit"); 6639 return; 6640 } 6641 6642 if (env->features[FEAT_1_EDX] & CPUID_PSE36) { 6643 cpu->phys_bits = 36; 6644 } else { 6645 cpu->phys_bits = 32; 6646 } 6647 } 6648 6649 /* Cache information initialization */ 6650 if (!cpu->legacy_cache) { 6651 if (!xcc->model || !xcc->model->cpudef->cache_info) { 6652 g_autofree char *name = x86_cpu_class_get_model_name(xcc); 6653 error_setg(errp, 6654 "CPU model '%s' doesn't support legacy-cache=off", name); 6655 return; 6656 } 6657 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd = 6658 *xcc->model->cpudef->cache_info; 6659 } else { 6660 /* Build legacy cache information */ 6661 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache; 6662 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache; 6663 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2; 6664 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache; 6665 6666 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache; 6667 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache; 6668 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache; 6669 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache; 6670 6671 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd; 6672 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd; 6673 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd; 6674 env->cache_info_amd.l3_cache = &legacy_l3_cache; 6675 } 6676 6677 #ifndef CONFIG_USER_ONLY 6678 MachineState *ms = MACHINE(qdev_get_machine()); 6679 qemu_register_reset(x86_cpu_machine_reset_cb, cpu); 6680 6681 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) { 6682 x86_cpu_apic_create(cpu, &local_err); 6683 if (local_err != NULL) { 6684 goto out; 6685 } 6686 } 6687 #endif 6688 6689 mce_init(cpu); 6690 6691 qemu_init_vcpu(cs); 6692 6693 /* 6694 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU 6695 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX 6696 * based on inputs (sockets,cores,threads), it is still better to give 6697 * users a warning. 6698 * 6699 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise 6700 * cs->nr_threads hasn't be populated yet and the checking is incorrect. 6701 */ 6702 if (IS_AMD_CPU(env) && 6703 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) && 6704 cs->nr_threads > 1 && !ht_warned) { 6705 warn_report("This family of AMD CPU doesn't support " 6706 "hyperthreading(%d)", 6707 cs->nr_threads); 6708 error_printf("Please configure -smp options properly" 6709 " or try enabling topoext feature.\n"); 6710 ht_warned = true; 6711 } 6712 6713 #ifndef CONFIG_USER_ONLY 6714 x86_cpu_apic_realize(cpu, &local_err); 6715 if (local_err != NULL) { 6716 goto out; 6717 } 6718 #endif /* !CONFIG_USER_ONLY */ 6719 cpu_reset(cs); 6720 6721 xcc->parent_realize(dev, &local_err); 6722 6723 out: 6724 if (local_err != NULL) { 6725 error_propagate(errp, local_err); 6726 return; 6727 } 6728 } 6729 6730 static void x86_cpu_unrealizefn(DeviceState *dev) 6731 { 6732 X86CPU *cpu = X86_CPU(dev); 6733 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev); 6734 6735 #ifndef CONFIG_USER_ONLY 6736 cpu_remove_sync(CPU(dev)); 6737 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev); 6738 #endif 6739 6740 if (cpu->apic_state) { 6741 object_unparent(OBJECT(cpu->apic_state)); 6742 cpu->apic_state = NULL; 6743 } 6744 6745 xcc->parent_unrealize(dev); 6746 } 6747 6748 typedef struct BitProperty { 6749 FeatureWord w; 6750 uint64_t mask; 6751 } BitProperty; 6752 6753 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name, 6754 void *opaque, Error **errp) 6755 { 6756 X86CPU *cpu = X86_CPU(obj); 6757 BitProperty *fp = opaque; 6758 uint64_t f = cpu->env.features[fp->w]; 6759 bool value = (f & fp->mask) == fp->mask; 6760 visit_type_bool(v, name, &value, errp); 6761 } 6762 6763 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name, 6764 void *opaque, Error **errp) 6765 { 6766 DeviceState *dev = DEVICE(obj); 6767 X86CPU *cpu = X86_CPU(obj); 6768 BitProperty *fp = opaque; 6769 bool value; 6770 6771 if (dev->realized) { 6772 qdev_prop_set_after_realize(dev, name, errp); 6773 return; 6774 } 6775 6776 if (!visit_type_bool(v, name, &value, errp)) { 6777 return; 6778 } 6779 6780 if (value) { 6781 cpu->env.features[fp->w] |= fp->mask; 6782 } else { 6783 cpu->env.features[fp->w] &= ~fp->mask; 6784 } 6785 cpu->env.user_features[fp->w] |= fp->mask; 6786 } 6787 6788 /* Register a boolean property to get/set a single bit in a uint32_t field. 6789 * 6790 * The same property name can be registered multiple times to make it affect 6791 * multiple bits in the same FeatureWord. In that case, the getter will return 6792 * true only if all bits are set. 6793 */ 6794 static void x86_cpu_register_bit_prop(X86CPUClass *xcc, 6795 const char *prop_name, 6796 FeatureWord w, 6797 int bitnr) 6798 { 6799 ObjectClass *oc = OBJECT_CLASS(xcc); 6800 BitProperty *fp; 6801 ObjectProperty *op; 6802 uint64_t mask = (1ULL << bitnr); 6803 6804 op = object_class_property_find(oc, prop_name); 6805 if (op) { 6806 fp = op->opaque; 6807 assert(fp->w == w); 6808 fp->mask |= mask; 6809 } else { 6810 fp = g_new0(BitProperty, 1); 6811 fp->w = w; 6812 fp->mask = mask; 6813 object_class_property_add(oc, prop_name, "bool", 6814 x86_cpu_get_bit_prop, 6815 x86_cpu_set_bit_prop, 6816 NULL, fp); 6817 } 6818 } 6819 6820 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc, 6821 FeatureWord w, 6822 int bitnr) 6823 { 6824 FeatureWordInfo *fi = &feature_word_info[w]; 6825 const char *name = fi->feat_names[bitnr]; 6826 6827 if (!name) { 6828 return; 6829 } 6830 6831 /* Property names should use "-" instead of "_". 6832 * Old names containing underscores are registered as aliases 6833 * using object_property_add_alias() 6834 */ 6835 assert(!strchr(name, '_')); 6836 /* aliases don't use "|" delimiters anymore, they are registered 6837 * manually using object_property_add_alias() */ 6838 assert(!strchr(name, '|')); 6839 x86_cpu_register_bit_prop(xcc, name, w, bitnr); 6840 } 6841 6842 static void x86_cpu_post_initfn(Object *obj) 6843 { 6844 accel_cpu_instance_init(CPU(obj)); 6845 } 6846 6847 static void x86_cpu_initfn(Object *obj) 6848 { 6849 X86CPU *cpu = X86_CPU(obj); 6850 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj); 6851 CPUX86State *env = &cpu->env; 6852 6853 env->nr_dies = 1; 6854 cpu_set_cpustate_pointers(cpu); 6855 6856 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo", 6857 x86_cpu_get_feature_words, 6858 NULL, NULL, (void *)env->features); 6859 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo", 6860 x86_cpu_get_feature_words, 6861 NULL, NULL, (void *)cpu->filtered_features); 6862 6863 object_property_add_alias(obj, "sse3", obj, "pni"); 6864 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq"); 6865 object_property_add_alias(obj, "sse4-1", obj, "sse4.1"); 6866 object_property_add_alias(obj, "sse4-2", obj, "sse4.2"); 6867 object_property_add_alias(obj, "xd", obj, "nx"); 6868 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt"); 6869 object_property_add_alias(obj, "i64", obj, "lm"); 6870 6871 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl"); 6872 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust"); 6873 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt"); 6874 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm"); 6875 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy"); 6876 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr"); 6877 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core"); 6878 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb"); 6879 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay"); 6880 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu"); 6881 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf"); 6882 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int"); 6883 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time"); 6884 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi"); 6885 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt"); 6886 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control"); 6887 object_property_add_alias(obj, "svm_lock", obj, "svm-lock"); 6888 object_property_add_alias(obj, "nrip_save", obj, "nrip-save"); 6889 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale"); 6890 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean"); 6891 object_property_add_alias(obj, "pause_filter", obj, "pause-filter"); 6892 object_property_add_alias(obj, "sse4_1", obj, "sse4.1"); 6893 object_property_add_alias(obj, "sse4_2", obj, "sse4.2"); 6894 6895 object_property_add_alias(obj, "hv-apicv", obj, "hv-avic"); 6896 cpu->lbr_fmt = ~PERF_CAP_LBR_FMT; 6897 object_property_add_alias(obj, "lbr_fmt", obj, "lbr-fmt"); 6898 6899 if (xcc->model) { 6900 x86_cpu_load_model(cpu, xcc->model); 6901 } 6902 } 6903 6904 static int64_t x86_cpu_get_arch_id(CPUState *cs) 6905 { 6906 X86CPU *cpu = X86_CPU(cs); 6907 6908 return cpu->apic_id; 6909 } 6910 6911 #if !defined(CONFIG_USER_ONLY) 6912 static bool x86_cpu_get_paging_enabled(const CPUState *cs) 6913 { 6914 X86CPU *cpu = X86_CPU(cs); 6915 6916 return cpu->env.cr[0] & CR0_PG_MASK; 6917 } 6918 #endif /* !CONFIG_USER_ONLY */ 6919 6920 static void x86_cpu_set_pc(CPUState *cs, vaddr value) 6921 { 6922 X86CPU *cpu = X86_CPU(cs); 6923 6924 cpu->env.eip = value; 6925 } 6926 6927 static vaddr x86_cpu_get_pc(CPUState *cs) 6928 { 6929 X86CPU *cpu = X86_CPU(cs); 6930 6931 /* Match cpu_get_tb_cpu_state. */ 6932 return cpu->env.eip + cpu->env.segs[R_CS].base; 6933 } 6934 6935 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request) 6936 { 6937 X86CPU *cpu = X86_CPU(cs); 6938 CPUX86State *env = &cpu->env; 6939 6940 #if !defined(CONFIG_USER_ONLY) 6941 if (interrupt_request & CPU_INTERRUPT_POLL) { 6942 return CPU_INTERRUPT_POLL; 6943 } 6944 #endif 6945 if (interrupt_request & CPU_INTERRUPT_SIPI) { 6946 return CPU_INTERRUPT_SIPI; 6947 } 6948 6949 if (env->hflags2 & HF2_GIF_MASK) { 6950 if ((interrupt_request & CPU_INTERRUPT_SMI) && 6951 !(env->hflags & HF_SMM_MASK)) { 6952 return CPU_INTERRUPT_SMI; 6953 } else if ((interrupt_request & CPU_INTERRUPT_NMI) && 6954 !(env->hflags2 & HF2_NMI_MASK)) { 6955 return CPU_INTERRUPT_NMI; 6956 } else if (interrupt_request & CPU_INTERRUPT_MCE) { 6957 return CPU_INTERRUPT_MCE; 6958 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 6959 (((env->hflags2 & HF2_VINTR_MASK) && 6960 (env->hflags2 & HF2_HIF_MASK)) || 6961 (!(env->hflags2 & HF2_VINTR_MASK) && 6962 (env->eflags & IF_MASK && 6963 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { 6964 return CPU_INTERRUPT_HARD; 6965 #if !defined(CONFIG_USER_ONLY) 6966 } else if (env->hflags2 & HF2_VGIF_MASK) { 6967 if((interrupt_request & CPU_INTERRUPT_VIRQ) && 6968 (env->eflags & IF_MASK) && 6969 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 6970 return CPU_INTERRUPT_VIRQ; 6971 } 6972 #endif 6973 } 6974 } 6975 6976 return 0; 6977 } 6978 6979 static bool x86_cpu_has_work(CPUState *cs) 6980 { 6981 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0; 6982 } 6983 6984 static void x86_disas_set_info(CPUState *cs, disassemble_info *info) 6985 { 6986 X86CPU *cpu = X86_CPU(cs); 6987 CPUX86State *env = &cpu->env; 6988 6989 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64 6990 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386 6991 : bfd_mach_i386_i8086); 6992 6993 info->cap_arch = CS_ARCH_X86; 6994 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64 6995 : env->hflags & HF_CS32_MASK ? CS_MODE_32 6996 : CS_MODE_16); 6997 info->cap_insn_unit = 1; 6998 info->cap_insn_split = 8; 6999 } 7000 7001 void x86_update_hflags(CPUX86State *env) 7002 { 7003 uint32_t hflags; 7004 #define HFLAG_COPY_MASK \ 7005 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \ 7006 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \ 7007 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \ 7008 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK) 7009 7010 hflags = env->hflags & HFLAG_COPY_MASK; 7011 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK; 7012 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT); 7013 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) & 7014 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK); 7015 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK)); 7016 7017 if (env->cr[4] & CR4_OSFXSR_MASK) { 7018 hflags |= HF_OSFXSR_MASK; 7019 } 7020 7021 if (env->efer & MSR_EFER_LMA) { 7022 hflags |= HF_LMA_MASK; 7023 } 7024 7025 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) { 7026 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK; 7027 } else { 7028 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >> 7029 (DESC_B_SHIFT - HF_CS32_SHIFT); 7030 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >> 7031 (DESC_B_SHIFT - HF_SS32_SHIFT); 7032 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) || 7033 !(hflags & HF_CS32_MASK)) { 7034 hflags |= HF_ADDSEG_MASK; 7035 } else { 7036 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base | 7037 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT; 7038 } 7039 } 7040 env->hflags = hflags; 7041 } 7042 7043 static Property x86_cpu_properties[] = { 7044 #ifdef CONFIG_USER_ONLY 7045 /* apic_id = 0 by default for *-user, see commit 9886e834 */ 7046 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0), 7047 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0), 7048 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0), 7049 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0), 7050 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0), 7051 #else 7052 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID), 7053 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1), 7054 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1), 7055 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1), 7056 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1), 7057 #endif 7058 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID), 7059 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false), 7060 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU, lbr_fmt, PERF_CAP_LBR_FMT), 7061 7062 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts, 7063 HYPERV_SPINLOCK_NEVER_NOTIFY), 7064 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features, 7065 HYPERV_FEAT_RELAXED, 0), 7066 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features, 7067 HYPERV_FEAT_VAPIC, 0), 7068 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features, 7069 HYPERV_FEAT_TIME, 0), 7070 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features, 7071 HYPERV_FEAT_CRASH, 0), 7072 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features, 7073 HYPERV_FEAT_RESET, 0), 7074 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features, 7075 HYPERV_FEAT_VPINDEX, 0), 7076 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features, 7077 HYPERV_FEAT_RUNTIME, 0), 7078 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features, 7079 HYPERV_FEAT_SYNIC, 0), 7080 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features, 7081 HYPERV_FEAT_STIMER, 0), 7082 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features, 7083 HYPERV_FEAT_FREQUENCIES, 0), 7084 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features, 7085 HYPERV_FEAT_REENLIGHTENMENT, 0), 7086 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features, 7087 HYPERV_FEAT_TLBFLUSH, 0), 7088 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features, 7089 HYPERV_FEAT_EVMCS, 0), 7090 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features, 7091 HYPERV_FEAT_IPI, 0), 7092 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features, 7093 HYPERV_FEAT_STIMER_DIRECT, 0), 7094 DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, 7095 HYPERV_FEAT_AVIC, 0), 7096 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, 7097 HYPERV_FEAT_MSR_BITMAP, 0), 7098 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, 7099 HYPERV_FEAT_XMM_INPUT, 0), 7100 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, 7101 HYPERV_FEAT_TLBFLUSH_EXT, 0), 7102 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, 7103 HYPERV_FEAT_TLBFLUSH_DIRECT, 0), 7104 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, 7105 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), 7106 DEFINE_PROP_BIT64("hv-syndbg", X86CPU, hyperv_features, 7107 HYPERV_FEAT_SYNDBG, 0), 7108 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), 7109 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU, hyperv_enforce_cpuid, false), 7110 7111 /* WS2008R2 identify by default */ 7112 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU, hyperv_ver_id_build, 7113 0x3839), 7114 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU, hyperv_ver_id_major, 7115 0x000A), 7116 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU, hyperv_ver_id_minor, 7117 0x0000), 7118 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU, hyperv_ver_id_sp, 0), 7119 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU, hyperv_ver_id_sb, 0), 7120 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU, hyperv_ver_id_sn, 0), 7121 7122 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true), 7123 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), 7124 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false), 7125 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), 7126 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), 7127 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), 7128 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0), 7129 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), 7130 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7, 7131 UINT32_MAX), 7132 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX), 7133 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX), 7134 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX), 7135 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), 7136 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), 7137 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), 7138 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), 7139 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true), 7140 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), 7141 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), 7142 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU, vendor_cpuid_only, true), 7143 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), 7144 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), 7145 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration, 7146 false), 7147 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU, kvm_pv_enforce_cpuid, 7148 false), 7149 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), 7150 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true), 7151 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count, 7152 true), 7153 /* 7154 * lecacy_cache defaults to true unless the CPU model provides its 7155 * own cache information (see x86_cpu_load_def()). 7156 */ 7157 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true), 7158 7159 /* 7160 * From "Requirements for Implementing the Microsoft 7161 * Hypervisor Interface": 7162 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7163 * 7164 * "Starting with Windows Server 2012 and Windows 8, if 7165 * CPUID.40000005.EAX contains a value of -1, Windows assumes that 7166 * the hypervisor imposes no specific limit to the number of VPs. 7167 * In this case, Windows Server 2012 guest VMs may use more than 7168 * 64 VPs, up to the maximum supported number of processors applicable 7169 * to the specific Windows version being used." 7170 */ 7171 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), 7172 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only, 7173 false), 7174 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, 7175 true), 7176 DEFINE_PROP_END_OF_LIST() 7177 }; 7178 7179 #ifndef CONFIG_USER_ONLY 7180 #include "hw/core/sysemu-cpu-ops.h" 7181 7182 static const struct SysemuCPUOps i386_sysemu_ops = { 7183 .get_memory_mapping = x86_cpu_get_memory_mapping, 7184 .get_paging_enabled = x86_cpu_get_paging_enabled, 7185 .get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug, 7186 .asidx_from_attrs = x86_asidx_from_attrs, 7187 .get_crash_info = x86_cpu_get_crash_info, 7188 .write_elf32_note = x86_cpu_write_elf32_note, 7189 .write_elf64_note = x86_cpu_write_elf64_note, 7190 .write_elf32_qemunote = x86_cpu_write_elf32_qemunote, 7191 .write_elf64_qemunote = x86_cpu_write_elf64_qemunote, 7192 .legacy_vmsd = &vmstate_x86_cpu, 7193 }; 7194 #endif 7195 7196 static void x86_cpu_common_class_init(ObjectClass *oc, void *data) 7197 { 7198 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7199 CPUClass *cc = CPU_CLASS(oc); 7200 DeviceClass *dc = DEVICE_CLASS(oc); 7201 FeatureWord w; 7202 7203 device_class_set_parent_realize(dc, x86_cpu_realizefn, 7204 &xcc->parent_realize); 7205 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn, 7206 &xcc->parent_unrealize); 7207 device_class_set_props(dc, x86_cpu_properties); 7208 7209 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset); 7210 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; 7211 7212 cc->class_by_name = x86_cpu_class_by_name; 7213 cc->parse_features = x86_cpu_parse_featurestr; 7214 cc->has_work = x86_cpu_has_work; 7215 cc->dump_state = x86_cpu_dump_state; 7216 cc->set_pc = x86_cpu_set_pc; 7217 cc->get_pc = x86_cpu_get_pc; 7218 cc->gdb_read_register = x86_cpu_gdb_read_register; 7219 cc->gdb_write_register = x86_cpu_gdb_write_register; 7220 cc->get_arch_id = x86_cpu_get_arch_id; 7221 7222 #ifndef CONFIG_USER_ONLY 7223 cc->sysemu_ops = &i386_sysemu_ops; 7224 #endif /* !CONFIG_USER_ONLY */ 7225 7226 cc->gdb_arch_name = x86_gdb_arch_name; 7227 #ifdef TARGET_X86_64 7228 cc->gdb_core_xml_file = "i386-64bit.xml"; 7229 cc->gdb_num_core_regs = 66; 7230 #else 7231 cc->gdb_core_xml_file = "i386-32bit.xml"; 7232 cc->gdb_num_core_regs = 50; 7233 #endif 7234 cc->disas_set_info = x86_disas_set_info; 7235 7236 dc->user_creatable = true; 7237 7238 object_class_property_add(oc, "family", "int", 7239 x86_cpuid_version_get_family, 7240 x86_cpuid_version_set_family, NULL, NULL); 7241 object_class_property_add(oc, "model", "int", 7242 x86_cpuid_version_get_model, 7243 x86_cpuid_version_set_model, NULL, NULL); 7244 object_class_property_add(oc, "stepping", "int", 7245 x86_cpuid_version_get_stepping, 7246 x86_cpuid_version_set_stepping, NULL, NULL); 7247 object_class_property_add(oc, "brand-id", "int", 7248 x86_cpuid_version_get_brand_id, 7249 x86_cpuid_version_set_brand_id, NULL, NULL); 7250 object_class_property_add_str(oc, "vendor", 7251 x86_cpuid_get_vendor, 7252 x86_cpuid_set_vendor); 7253 object_class_property_add_str(oc, "model-id", 7254 x86_cpuid_get_model_id, 7255 x86_cpuid_set_model_id); 7256 object_class_property_add(oc, "tsc-frequency", "int", 7257 x86_cpuid_get_tsc_freq, 7258 x86_cpuid_set_tsc_freq, NULL, NULL); 7259 /* 7260 * The "unavailable-features" property has the same semantics as 7261 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions" 7262 * QMP command: they list the features that would have prevented the 7263 * CPU from running if the "enforce" flag was set. 7264 */ 7265 object_class_property_add(oc, "unavailable-features", "strList", 7266 x86_cpu_get_unavailable_features, 7267 NULL, NULL, NULL); 7268 7269 #if !defined(CONFIG_USER_ONLY) 7270 object_class_property_add(oc, "crash-information", "GuestPanicInformation", 7271 x86_cpu_get_crash_info_qom, NULL, NULL, NULL); 7272 #endif 7273 7274 for (w = 0; w < FEATURE_WORDS; w++) { 7275 int bitnr; 7276 for (bitnr = 0; bitnr < 64; bitnr++) { 7277 x86_cpu_register_feature_bit_props(xcc, w, bitnr); 7278 } 7279 } 7280 } 7281 7282 static const TypeInfo x86_cpu_type_info = { 7283 .name = TYPE_X86_CPU, 7284 .parent = TYPE_CPU, 7285 .instance_size = sizeof(X86CPU), 7286 .instance_init = x86_cpu_initfn, 7287 .instance_post_init = x86_cpu_post_initfn, 7288 7289 .abstract = true, 7290 .class_size = sizeof(X86CPUClass), 7291 .class_init = x86_cpu_common_class_init, 7292 }; 7293 7294 /* "base" CPU model, used by query-cpu-model-expansion */ 7295 static void x86_cpu_base_class_init(ObjectClass *oc, void *data) 7296 { 7297 X86CPUClass *xcc = X86_CPU_CLASS(oc); 7298 7299 xcc->static_model = true; 7300 xcc->migration_safe = true; 7301 xcc->model_description = "base CPU model type with no features enabled"; 7302 xcc->ordering = 8; 7303 } 7304 7305 static const TypeInfo x86_base_cpu_type_info = { 7306 .name = X86_CPU_TYPE_NAME("base"), 7307 .parent = TYPE_X86_CPU, 7308 .class_init = x86_cpu_base_class_init, 7309 }; 7310 7311 static void x86_cpu_register_types(void) 7312 { 7313 int i; 7314 7315 type_register_static(&x86_cpu_type_info); 7316 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { 7317 x86_register_cpudef_types(&builtin_x86_defs[i]); 7318 } 7319 type_register_static(&max_x86_cpu_type_info); 7320 type_register_static(&x86_base_cpu_type_info); 7321 } 7322 7323 type_init(x86_cpu_register_types)