cpu.h (5021B)
1 /* 2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef HEXAGON_CPU_H 19 #define HEXAGON_CPU_H 20 21 #include "fpu/softfloat-types.h" 22 23 #include "exec/cpu-defs.h" 24 #include "hex_regs.h" 25 #include "mmvec/mmvec.h" 26 #include "qom/object.h" 27 #include "hw/core/cpu.h" 28 29 #define NUM_PREGS 4 30 #define TOTAL_PER_THREAD_REGS 64 31 32 #define SLOTS_MAX 4 33 #define STORES_MAX 2 34 #define REG_WRITES_MAX 32 35 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ 36 #define VSTORES_MAX 2 37 38 #define TYPE_HEXAGON_CPU "hexagon-cpu" 39 40 #define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU 41 #define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) 42 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU 43 44 #define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") 45 46 #define MMU_USER_IDX 0 47 48 typedef struct { 49 target_ulong va; 50 uint8_t width; 51 uint32_t data32; 52 uint64_t data64; 53 } MemLog; 54 55 typedef struct { 56 target_ulong va; 57 int size; 58 DECLARE_BITMAP(mask, MAX_VEC_SIZE_BYTES) QEMU_ALIGNED(16); 59 MMVector data QEMU_ALIGNED(16); 60 } VStoreLog; 61 62 #define EXEC_STATUS_OK 0x0000 63 #define EXEC_STATUS_STOP 0x0002 64 #define EXEC_STATUS_REPLAY 0x0010 65 #define EXEC_STATUS_LOCKED 0x0020 66 #define EXEC_STATUS_EXCEPTION 0x0100 67 68 69 #define EXCEPTION_DETECTED (env->status & EXEC_STATUS_EXCEPTION) 70 #define REPLAY_DETECTED (env->status & EXEC_STATUS_REPLAY) 71 #define CLEAR_EXCEPTION (env->status &= (~EXEC_STATUS_EXCEPTION)) 72 #define SET_EXCEPTION (env->status |= EXEC_STATUS_EXCEPTION) 73 74 /* Maximum number of vector temps in a packet */ 75 #define VECTOR_TEMPS_MAX 4 76 77 typedef struct CPUArchState { 78 target_ulong gpr[TOTAL_PER_THREAD_REGS]; 79 target_ulong pred[NUM_PREGS]; 80 target_ulong branch_taken; 81 target_ulong next_PC; 82 83 /* For comparing with LLDB on target - see adjust_stack_ptrs function */ 84 target_ulong last_pc_dumped; 85 target_ulong stack_start; 86 87 uint8_t slot_cancelled; 88 target_ulong new_value[TOTAL_PER_THREAD_REGS]; 89 90 /* 91 * Only used when HEX_DEBUG is on, but unconditionally included 92 * to reduce recompile time when turning HEX_DEBUG on/off. 93 */ 94 target_ulong this_PC; 95 target_ulong reg_written[TOTAL_PER_THREAD_REGS]; 96 97 target_ulong new_pred_value[NUM_PREGS]; 98 target_ulong pred_written; 99 100 MemLog mem_log_stores[STORES_MAX]; 101 target_ulong pkt_has_store_s1; 102 target_ulong dczero_addr; 103 104 float_status fp_status; 105 106 target_ulong llsc_addr; 107 target_ulong llsc_val; 108 uint64_t llsc_val_i64; 109 110 MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16); 111 MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 112 MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16); 113 114 VRegMask VRegs_updated; 115 116 MMQReg QRegs[NUM_QREGS] QEMU_ALIGNED(16); 117 MMQReg future_QRegs[NUM_QREGS] QEMU_ALIGNED(16); 118 QRegMask QRegs_updated; 119 120 /* Temporaries used within instructions */ 121 MMVectorPair VuuV QEMU_ALIGNED(16); 122 MMVectorPair VvvV QEMU_ALIGNED(16); 123 MMVectorPair VxxV QEMU_ALIGNED(16); 124 MMVector vtmp QEMU_ALIGNED(16); 125 MMQReg qtmp QEMU_ALIGNED(16); 126 127 VStoreLog vstore[VSTORES_MAX]; 128 target_ulong vstore_pending[VSTORES_MAX]; 129 bool vtcm_pending; 130 VTCMStoreLog vtcm_log; 131 } CPUHexagonState; 132 133 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) 134 135 typedef struct HexagonCPUClass { 136 /*< private >*/ 137 CPUClass parent_class; 138 /*< public >*/ 139 DeviceRealize parent_realize; 140 DeviceReset parent_reset; 141 } HexagonCPUClass; 142 143 struct ArchCPU { 144 /*< private >*/ 145 CPUState parent_obj; 146 /*< public >*/ 147 CPUNegativeOffsetState neg; 148 CPUHexagonState env; 149 150 bool lldb_compat; 151 target_ulong lldb_stack_adjust; 152 }; 153 154 #include "cpu_bits.h" 155 156 static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, target_ulong *pc, 157 target_ulong *cs_base, uint32_t *flags) 158 { 159 *pc = env->gpr[HEX_REG_PC]; 160 *cs_base = 0; 161 #ifdef CONFIG_USER_ONLY 162 *flags = 0; 163 #else 164 #error System mode not supported on Hexagon yet 165 #endif 166 } 167 168 static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) 169 { 170 #ifdef CONFIG_USER_ONLY 171 return MMU_USER_IDX; 172 #else 173 #error System mode not supported on Hexagon yet 174 #endif 175 } 176 177 typedef HexagonCPU ArchCPU; 178 179 void hexagon_translate_init(void); 180 181 #include "exec/cpu-all.h" 182 183 #endif /* HEXAGON_CPU_H */