insn.decode (6995B)
1 # 2 # AVR instruction decode definitions. 3 # 4 # Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com> 5 # 6 # This library is free software; you can redistribute it and/or 7 # modify it under the terms of the GNU Lesser General Public 8 # License as published by the Free Software Foundation; either 9 # version 2.1 of the License, or (at your option) any later version. 10 # 11 # This library is distributed in the hope that it will be useful, 12 # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 # Lesser General Public License for more details. 15 # 16 # You should have received a copy of the GNU Lesser General Public 17 # License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 # 19 20 # 21 # regs_16_31_by_one = [16 .. 31] 22 # regs_16_23_by_one = [16 .. 23] 23 # regs_24_30_by_two = [24, 26, 28, 30] 24 # regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30] 25 26 %rd 4:5 27 %rr 9:1 0:4 28 29 %rd_a 4:4 !function=to_regs_16_31_by_one 30 %rd_b 4:3 !function=to_regs_16_23_by_one 31 %rd_c 4:2 !function=to_regs_24_30_by_two 32 %rr_a 0:4 !function=to_regs_16_31_by_one 33 %rr_b 0:3 !function=to_regs_16_23_by_one 34 35 %imm6 6:2 0:4 36 %imm8 8:4 0:4 37 38 %io_imm 9:2 0:4 39 %ldst_d_imm 13:1 10:2 0:3 40 41 42 &rd_rr rd rr 43 &rd_imm rd imm 44 45 @op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr 46 @op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6 47 @op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8 48 @fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b 49 50 # 51 # Arithmetic Instructions 52 # 53 ADD 0000 11 . ..... .... @op_rd_rr 54 ADC 0001 11 . ..... .... @op_rd_rr 55 ADIW 1001 0110 .. .. .... @op_rd_imm6 56 SUB 0001 10 . ..... .... @op_rd_rr 57 SUBI 0101 .... .... .... @op_rd_imm8 58 SBC 0000 10 . ..... .... @op_rd_rr 59 SBCI 0100 .... .... .... @op_rd_imm8 60 SBIW 1001 0111 .. .. .... @op_rd_imm6 61 AND 0010 00 . ..... .... @op_rd_rr 62 ANDI 0111 .... .... .... @op_rd_imm8 63 OR 0010 10 . ..... .... @op_rd_rr 64 ORI 0110 .... .... .... @op_rd_imm8 65 EOR 0010 01 . ..... .... @op_rd_rr 66 COM 1001 010 rd:5 0000 67 NEG 1001 010 rd:5 0001 68 INC 1001 010 rd:5 0011 69 DEC 1001 010 rd:5 1010 70 MUL 1001 11 . ..... .... @op_rd_rr 71 MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a 72 MULSU 0000 0011 0 ... 0 ... @fmul 73 FMUL 0000 0011 0 ... 1 ... @fmul 74 FMULS 0000 0011 1 ... 0 ... @fmul 75 FMULSU 0000 0011 1 ... 1 ... @fmul 76 DES 1001 0100 imm:4 1011 77 78 # 79 # Branch Instructions 80 # 81 82 # The 22-bit immediate is partially in the opcode word, 83 # and partially in the next. Use append_16 to build the 84 # complete 22-bit value. 85 %imm_call 4:5 0:1 !function=append_16 86 87 @op_bit .... .... . bit:3 .... 88 @op_bit_imm .... .. imm:s7 bit:3 89 90 RJMP 1100 imm:s12 91 IJMP 1001 0100 0000 1001 92 EIJMP 1001 0100 0001 1001 93 JMP 1001 010 ..... 110 . imm=%imm_call 94 RCALL 1101 imm:s12 95 ICALL 1001 0101 0000 1001 96 EICALL 1001 0101 0001 1001 97 CALL 1001 010 ..... 111 . imm=%imm_call 98 RET 1001 0101 0000 1000 99 RETI 1001 0101 0001 1000 100 CPSE 0001 00 . ..... .... @op_rd_rr 101 CP 0001 01 . ..... .... @op_rd_rr 102 CPC 0000 01 . ..... .... @op_rd_rr 103 CPI 0011 .... .... .... @op_rd_imm8 104 SBRC 1111 110 rr:5 0 bit:3 105 SBRS 1111 111 rr:5 0 bit:3 106 SBIC 1001 1001 reg:5 bit:3 107 SBIS 1001 1011 reg:5 bit:3 108 BRBS 1111 00 ....... ... @op_bit_imm 109 BRBC 1111 01 ....... ... @op_bit_imm 110 111 # 112 # Data Transfer Instructions 113 # 114 115 %rd_d 4:4 !function=to_regs_00_30_by_two 116 %rr_d 0:4 !function=to_regs_00_30_by_two 117 118 @io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm 119 @ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm 120 121 # The 16-bit immediate is completely in the next word. 122 # Fields cannot be defined with no bits, so we cannot play 123 # the same trick and append to a zero-bit value. 124 # Defer reading the immediate until trans_{LDS,STS}. 125 @ldst_s .... ... rd:5 .... imm=0 126 127 MOV 0010 11 . ..... .... @op_rd_rr 128 MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d 129 LDI 1110 .... .... .... @op_rd_imm8 130 LDS 1001 000 ..... 0000 @ldst_s 131 LDX1 1001 000 rd:5 1100 132 LDX2 1001 000 rd:5 1101 133 LDX3 1001 000 rd:5 1110 134 LDY2 1001 000 rd:5 1001 135 LDY3 1001 000 rd:5 1010 136 LDZ2 1001 000 rd:5 0001 137 LDZ3 1001 000 rd:5 0010 138 LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d 139 LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d 140 STS 1001 001 ..... 0000 @ldst_s 141 STX1 1001 001 rr:5 1100 142 STX2 1001 001 rr:5 1101 143 STX3 1001 001 rr:5 1110 144 STY2 1001 001 rd:5 1001 145 STY3 1001 001 rd:5 1010 146 STZ2 1001 001 rd:5 0001 147 STZ3 1001 001 rd:5 0010 148 STDY 10 . 0 .. 1 ..... 1 ... @ldst_d 149 STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d 150 LPM1 1001 0101 1100 1000 151 LPM2 1001 000 rd:5 0100 152 LPMX 1001 000 rd:5 0101 153 ELPM1 1001 0101 1101 1000 154 ELPM2 1001 000 rd:5 0110 155 ELPMX 1001 000 rd:5 0111 156 SPM 1001 0101 1110 1000 157 SPMX 1001 0101 1111 1000 158 IN 1011 0 .. ..... .... @io_rd_imm 159 OUT 1011 1 .. ..... .... @io_rd_imm 160 PUSH 1001 001 rd:5 1111 161 POP 1001 000 rd:5 1111 162 XCH 1001 001 rd:5 0100 163 LAC 1001 001 rd:5 0110 164 LAS 1001 001 rd:5 0101 165 LAT 1001 001 rd:5 0111 166 167 # 168 # Bit and Bit-test Instructions 169 # 170 LSR 1001 010 rd:5 0110 171 ROR 1001 010 rd:5 0111 172 ASR 1001 010 rd:5 0101 173 SWAP 1001 010 rd:5 0010 174 SBI 1001 1010 reg:5 bit:3 175 CBI 1001 1000 reg:5 bit:3 176 BST 1111 101 rd:5 0 bit:3 177 BLD 1111 100 rd:5 0 bit:3 178 BSET 1001 0100 0 bit:3 1000 179 BCLR 1001 0100 1 bit:3 1000 180 181 # 182 # MCU Control Instructions 183 # 184 BREAK 1001 0101 1001 1000 185 NOP 0000 0000 0000 0000 186 SLEEP 1001 0101 1000 1000 187 WDR 1001 0101 1010 1000