cpu.c (12303B)
1 /* 2 * QEMU AVR CPU 3 * 4 * Copyright (c) 2019-2020 Michael Rolnik 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/qemu-print.h" 24 #include "exec/exec-all.h" 25 #include "cpu.h" 26 #include "disas/dis-asm.h" 27 28 static void avr_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 AVRCPU *cpu = AVR_CPU(cs); 31 32 cpu->env.pc_w = value / 2; /* internally PC points to words */ 33 } 34 35 static vaddr avr_cpu_get_pc(CPUState *cs) 36 { 37 AVRCPU *cpu = AVR_CPU(cs); 38 39 return cpu->env.pc_w * 2; 40 } 41 42 static bool avr_cpu_has_work(CPUState *cs) 43 { 44 AVRCPU *cpu = AVR_CPU(cs); 45 CPUAVRState *env = &cpu->env; 46 47 return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET)) 48 && cpu_interrupts_enabled(env); 49 } 50 51 static void avr_cpu_synchronize_from_tb(CPUState *cs, 52 const TranslationBlock *tb) 53 { 54 AVRCPU *cpu = AVR_CPU(cs); 55 CPUAVRState *env = &cpu->env; 56 57 env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */ 58 } 59 60 static void avr_restore_state_to_opc(CPUState *cs, 61 const TranslationBlock *tb, 62 const uint64_t *data) 63 { 64 AVRCPU *cpu = AVR_CPU(cs); 65 CPUAVRState *env = &cpu->env; 66 67 env->pc_w = data[0]; 68 } 69 70 static void avr_cpu_reset(DeviceState *ds) 71 { 72 CPUState *cs = CPU(ds); 73 AVRCPU *cpu = AVR_CPU(cs); 74 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu); 75 CPUAVRState *env = &cpu->env; 76 77 mcc->parent_reset(ds); 78 79 env->pc_w = 0; 80 env->sregI = 1; 81 env->sregC = 0; 82 env->sregZ = 0; 83 env->sregN = 0; 84 env->sregV = 0; 85 env->sregS = 0; 86 env->sregH = 0; 87 env->sregT = 0; 88 89 env->rampD = 0; 90 env->rampX = 0; 91 env->rampY = 0; 92 env->rampZ = 0; 93 env->eind = 0; 94 env->sp = 0; 95 96 env->skip = 0; 97 98 memset(env->r, 0, sizeof(env->r)); 99 } 100 101 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 102 { 103 info->mach = bfd_arch_avr; 104 info->print_insn = avr_print_insn; 105 } 106 107 static void avr_cpu_realizefn(DeviceState *dev, Error **errp) 108 { 109 CPUState *cs = CPU(dev); 110 AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev); 111 Error *local_err = NULL; 112 113 cpu_exec_realizefn(cs, &local_err); 114 if (local_err != NULL) { 115 error_propagate(errp, local_err); 116 return; 117 } 118 qemu_init_vcpu(cs); 119 cpu_reset(cs); 120 121 mcc->parent_realize(dev, errp); 122 } 123 124 static void avr_cpu_set_int(void *opaque, int irq, int level) 125 { 126 AVRCPU *cpu = opaque; 127 CPUAVRState *env = &cpu->env; 128 CPUState *cs = CPU(cpu); 129 uint64_t mask = (1ull << irq); 130 131 if (level) { 132 env->intsrc |= mask; 133 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 134 } else { 135 env->intsrc &= ~mask; 136 if (env->intsrc == 0) { 137 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 138 } 139 } 140 } 141 142 static void avr_cpu_initfn(Object *obj) 143 { 144 AVRCPU *cpu = AVR_CPU(obj); 145 146 cpu_set_cpustate_pointers(cpu); 147 148 /* Set the number of interrupts supported by the CPU. */ 149 qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int, 150 sizeof(cpu->env.intsrc) * 8); 151 } 152 153 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) 154 { 155 ObjectClass *oc; 156 157 oc = object_class_by_name(cpu_model); 158 if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL || 159 object_class_is_abstract(oc)) { 160 oc = NULL; 161 } 162 return oc; 163 } 164 165 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) 166 { 167 AVRCPU *cpu = AVR_CPU(cs); 168 CPUAVRState *env = &cpu->env; 169 int i; 170 171 qemu_fprintf(f, "\n"); 172 qemu_fprintf(f, "PC: %06x\n", env->pc_w * 2); /* PC points to words */ 173 qemu_fprintf(f, "SP: %04x\n", env->sp); 174 qemu_fprintf(f, "rampD: %02x\n", env->rampD >> 16); 175 qemu_fprintf(f, "rampX: %02x\n", env->rampX >> 16); 176 qemu_fprintf(f, "rampY: %02x\n", env->rampY >> 16); 177 qemu_fprintf(f, "rampZ: %02x\n", env->rampZ >> 16); 178 qemu_fprintf(f, "EIND: %02x\n", env->eind >> 16); 179 qemu_fprintf(f, "X: %02x%02x\n", env->r[27], env->r[26]); 180 qemu_fprintf(f, "Y: %02x%02x\n", env->r[29], env->r[28]); 181 qemu_fprintf(f, "Z: %02x%02x\n", env->r[31], env->r[30]); 182 qemu_fprintf(f, "SREG: [ %c %c %c %c %c %c %c %c ]\n", 183 env->sregI ? 'I' : '-', 184 env->sregT ? 'T' : '-', 185 env->sregH ? 'H' : '-', 186 env->sregS ? 'S' : '-', 187 env->sregV ? 'V' : '-', 188 env->sregN ? '-' : 'N', /* Zf has negative logic */ 189 env->sregZ ? 'Z' : '-', 190 env->sregC ? 'I' : '-'); 191 qemu_fprintf(f, "SKIP: %02x\n", env->skip); 192 193 qemu_fprintf(f, "\n"); 194 for (i = 0; i < ARRAY_SIZE(env->r); i++) { 195 qemu_fprintf(f, "R[%02d]: %02x ", i, env->r[i]); 196 197 if ((i % 8) == 7) { 198 qemu_fprintf(f, "\n"); 199 } 200 } 201 qemu_fprintf(f, "\n"); 202 } 203 204 #include "hw/core/sysemu-cpu-ops.h" 205 206 static const struct SysemuCPUOps avr_sysemu_ops = { 207 .get_phys_page_debug = avr_cpu_get_phys_page_debug, 208 }; 209 210 #include "hw/core/tcg-cpu-ops.h" 211 212 static const struct TCGCPUOps avr_tcg_ops = { 213 .initialize = avr_cpu_tcg_init, 214 .synchronize_from_tb = avr_cpu_synchronize_from_tb, 215 .restore_state_to_opc = avr_restore_state_to_opc, 216 .cpu_exec_interrupt = avr_cpu_exec_interrupt, 217 .tlb_fill = avr_cpu_tlb_fill, 218 .do_interrupt = avr_cpu_do_interrupt, 219 }; 220 221 static void avr_cpu_class_init(ObjectClass *oc, void *data) 222 { 223 DeviceClass *dc = DEVICE_CLASS(oc); 224 CPUClass *cc = CPU_CLASS(oc); 225 AVRCPUClass *mcc = AVR_CPU_CLASS(oc); 226 227 device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize); 228 device_class_set_parent_reset(dc, avr_cpu_reset, &mcc->parent_reset); 229 230 cc->class_by_name = avr_cpu_class_by_name; 231 232 cc->has_work = avr_cpu_has_work; 233 cc->dump_state = avr_cpu_dump_state; 234 cc->set_pc = avr_cpu_set_pc; 235 cc->get_pc = avr_cpu_get_pc; 236 dc->vmsd = &vms_avr_cpu; 237 cc->sysemu_ops = &avr_sysemu_ops; 238 cc->disas_set_info = avr_cpu_disas_set_info; 239 cc->gdb_read_register = avr_cpu_gdb_read_register; 240 cc->gdb_write_register = avr_cpu_gdb_write_register; 241 cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint; 242 cc->gdb_num_core_regs = 35; 243 cc->gdb_core_xml_file = "avr-cpu.xml"; 244 cc->tcg_ops = &avr_tcg_ops; 245 } 246 247 /* 248 * Setting features of AVR core type avr5 249 * -------------------------------------- 250 * 251 * This type of AVR core is present in the following AVR MCUs: 252 * 253 * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c, 254 * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162, 255 * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, 256 * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, 257 * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb, 258 * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323, 259 * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, 260 * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, 261 * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa, 262 * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1, 263 * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644, 264 * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, 265 * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, 266 * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p, 267 * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2, 268 * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216, 269 * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000 270 */ 271 static void avr_avr5_initfn(Object *obj) 272 { 273 AVRCPU *cpu = AVR_CPU(obj); 274 CPUAVRState *env = &cpu->env; 275 276 set_avr_feature(env, AVR_FEATURE_LPM); 277 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 278 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 279 set_avr_feature(env, AVR_FEATURE_SRAM); 280 set_avr_feature(env, AVR_FEATURE_BREAK); 281 282 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 283 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 284 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 285 set_avr_feature(env, AVR_FEATURE_LPMX); 286 set_avr_feature(env, AVR_FEATURE_MOVW); 287 set_avr_feature(env, AVR_FEATURE_MUL); 288 } 289 290 /* 291 * Setting features of AVR core type avr51 292 * -------------------------------------- 293 * 294 * This type of AVR core is present in the following AVR MCUs: 295 * 296 * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p, 297 * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286, 298 * at90usb1287 299 */ 300 static void avr_avr51_initfn(Object *obj) 301 { 302 AVRCPU *cpu = AVR_CPU(obj); 303 CPUAVRState *env = &cpu->env; 304 305 set_avr_feature(env, AVR_FEATURE_LPM); 306 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 307 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 308 set_avr_feature(env, AVR_FEATURE_SRAM); 309 set_avr_feature(env, AVR_FEATURE_BREAK); 310 311 set_avr_feature(env, AVR_FEATURE_2_BYTE_PC); 312 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 313 set_avr_feature(env, AVR_FEATURE_RAMPZ); 314 set_avr_feature(env, AVR_FEATURE_ELPMX); 315 set_avr_feature(env, AVR_FEATURE_ELPM); 316 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 317 set_avr_feature(env, AVR_FEATURE_LPMX); 318 set_avr_feature(env, AVR_FEATURE_MOVW); 319 set_avr_feature(env, AVR_FEATURE_MUL); 320 } 321 322 /* 323 * Setting features of AVR core type avr6 324 * -------------------------------------- 325 * 326 * This type of AVR core is present in the following AVR MCUs: 327 * 328 * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2 329 */ 330 static void avr_avr6_initfn(Object *obj) 331 { 332 AVRCPU *cpu = AVR_CPU(obj); 333 CPUAVRState *env = &cpu->env; 334 335 set_avr_feature(env, AVR_FEATURE_LPM); 336 set_avr_feature(env, AVR_FEATURE_IJMP_ICALL); 337 set_avr_feature(env, AVR_FEATURE_ADIW_SBIW); 338 set_avr_feature(env, AVR_FEATURE_SRAM); 339 set_avr_feature(env, AVR_FEATURE_BREAK); 340 341 set_avr_feature(env, AVR_FEATURE_3_BYTE_PC); 342 set_avr_feature(env, AVR_FEATURE_2_BYTE_SP); 343 set_avr_feature(env, AVR_FEATURE_RAMPZ); 344 set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL); 345 set_avr_feature(env, AVR_FEATURE_ELPMX); 346 set_avr_feature(env, AVR_FEATURE_ELPM); 347 set_avr_feature(env, AVR_FEATURE_JMP_CALL); 348 set_avr_feature(env, AVR_FEATURE_LPMX); 349 set_avr_feature(env, AVR_FEATURE_MOVW); 350 set_avr_feature(env, AVR_FEATURE_MUL); 351 } 352 353 typedef struct AVRCPUInfo { 354 const char *name; 355 void (*initfn)(Object *obj); 356 } AVRCPUInfo; 357 358 359 static void avr_cpu_list_entry(gpointer data, gpointer user_data) 360 { 361 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 362 363 qemu_printf("%s\n", typename); 364 } 365 366 void avr_cpu_list(void) 367 { 368 GSList *list; 369 list = object_class_get_list_sorted(TYPE_AVR_CPU, false); 370 g_slist_foreach(list, avr_cpu_list_entry, NULL); 371 g_slist_free(list); 372 } 373 374 #define DEFINE_AVR_CPU_TYPE(model, initfn) \ 375 { \ 376 .parent = TYPE_AVR_CPU, \ 377 .instance_init = initfn, \ 378 .name = AVR_CPU_TYPE_NAME(model), \ 379 } 380 381 static const TypeInfo avr_cpu_type_info[] = { 382 { 383 .name = TYPE_AVR_CPU, 384 .parent = TYPE_CPU, 385 .instance_size = sizeof(AVRCPU), 386 .instance_init = avr_cpu_initfn, 387 .class_size = sizeof(AVRCPUClass), 388 .class_init = avr_cpu_class_init, 389 .abstract = true, 390 }, 391 DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn), 392 DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn), 393 DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn), 394 }; 395 396 DEFINE_TYPES(avr_cpu_type_info)