translate.h (22646B)
1 #ifndef TARGET_ARM_TRANSLATE_H 2 #define TARGET_ARM_TRANSLATE_H 3 4 #include "exec/translator.h" 5 #include "internals.h" 6 7 8 /* internal defines */ 9 10 /* 11 * Save pc_save across a branch, so that we may restore the value from 12 * before the branch at the point the label is emitted. 13 */ 14 typedef struct DisasLabel { 15 TCGLabel *label; 16 target_ulong pc_save; 17 } DisasLabel; 18 19 typedef struct DisasContext { 20 DisasContextBase base; 21 const ARMISARegisters *isar; 22 23 /* The address of the current instruction being translated. */ 24 target_ulong pc_curr; 25 /* 26 * For TARGET_TB_PCREL, the full value of cpu_pc is not known 27 * (although the page offset is known). For convenience, the 28 * translation loop uses the full virtual address that triggered 29 * the translation, from base.pc_start through pc_curr. 30 * For efficiency, we do not update cpu_pc for every instruction. 31 * Instead, pc_save has the value of pc_curr at the time of the 32 * last update to cpu_pc, which allows us to compute the addend 33 * needed to bring cpu_pc current: pc_curr - pc_save. 34 * If cpu_pc now contains the destination of an indirect branch, 35 * pc_save contains -1 to indicate that relative updates are no 36 * longer possible. 37 */ 38 target_ulong pc_save; 39 target_ulong page_start; 40 uint32_t insn; 41 /* Nonzero if this instruction has been conditionally skipped. */ 42 int condjmp; 43 /* The label that will be jumped to when the instruction is skipped. */ 44 DisasLabel condlabel; 45 /* Thumb-2 conditional execution bits. */ 46 int condexec_mask; 47 int condexec_cond; 48 /* M-profile ECI/ICI exception-continuable instruction state */ 49 int eci; 50 /* 51 * trans_ functions for insns which are continuable should set this true 52 * after decode (ie after any UNDEF checks) 53 */ 54 bool eci_handled; 55 int sctlr_b; 56 MemOp be_data; 57 #if !defined(CONFIG_USER_ONLY) 58 int user; 59 #endif 60 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ 61 uint8_t tbii; /* TBI1|TBI0 for insns */ 62 uint8_t tbid; /* TBI1|TBI0 for data */ 63 uint8_t tcma; /* TCMA1|TCMA0 for MTE */ 64 bool ns; /* Use non-secure CPREG bank on access */ 65 int fp_excp_el; /* FP exception EL or 0 if enabled */ 66 int sve_excp_el; /* SVE exception EL or 0 if enabled */ 67 int sme_excp_el; /* SME exception EL or 0 if enabled */ 68 int vl; /* current vector length in bytes */ 69 int svl; /* current streaming vector length in bytes */ 70 bool vfp_enabled; /* FP enabled via FPSCR.EN */ 71 int vec_len; 72 int vec_stride; 73 bool v7m_handler_mode; 74 bool v8m_secure; /* true if v8M and we're in Secure mode */ 75 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ 76 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ 77 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ 78 bool v7m_lspact; /* FPCCR.LSPACT set */ 79 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI 80 * so that top level loop can generate correct syndrome information. 81 */ 82 uint32_t svc_imm; 83 int current_el; 84 GHashTable *cp_regs; 85 uint64_t features; /* CPU features bits */ 86 bool aarch64; 87 bool thumb; 88 /* Because unallocated encodings generate different exception syndrome 89 * information from traps due to FP being disabled, we can't do a single 90 * "is fp access disabled" check at a high level in the decode tree. 91 * To help in catching bugs where the access check was forgotten in some 92 * code path, we set this flag when the access check is done, and assert 93 * that it is set at the point where we actually touch the FP regs. 94 */ 95 bool fp_access_checked; 96 bool sve_access_checked; 97 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub 98 * single-step support). 99 */ 100 bool ss_active; 101 bool pstate_ss; 102 /* True if the insn just emitted was a load-exclusive instruction 103 * (necessary for syndrome information for single step exceptions), 104 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*. 105 */ 106 bool is_ldex; 107 /* True if AccType_UNPRIV should be used for LDTR et al */ 108 bool unpriv; 109 /* True if v8.3-PAuth is active. */ 110 bool pauth_active; 111 /* True if v8.5-MTE access to tags is enabled. */ 112 bool ata; 113 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */ 114 bool mte_active[2]; 115 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */ 116 bool bt; 117 /* True if any CP15 access is trapped by HSTR_EL2 */ 118 bool hstr_active; 119 /* True if memory operations require alignment */ 120 bool align_mem; 121 /* True if PSTATE.IL is set */ 122 bool pstate_il; 123 /* True if PSTATE.SM is set. */ 124 bool pstate_sm; 125 /* True if PSTATE.ZA is set. */ 126 bool pstate_za; 127 /* True if non-streaming insns should raise an SME Streaming exception. */ 128 bool sme_trap_nonstreaming; 129 /* True if the current instruction is non-streaming. */ 130 bool is_nonstreaming; 131 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */ 132 bool mve_no_pred; 133 /* 134 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. 135 * < 0, set by the current instruction. 136 */ 137 int8_t btype; 138 /* A copy of cpu->dcz_blocksize. */ 139 uint8_t dcz_blocksize; 140 /* True if this page is guarded. */ 141 bool guarded_page; 142 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ 143 int c15_cpar; 144 /* TCG op of the current insn_start. */ 145 TCGOp *insn_start; 146 #define TMP_A64_MAX 16 147 int tmp_a64_count; 148 TCGv_i64 tmp_a64[TMP_A64_MAX]; 149 } DisasContext; 150 151 typedef struct DisasCompare { 152 TCGCond cond; 153 TCGv_i32 value; 154 bool value_global; 155 } DisasCompare; 156 157 /* Share the TCG temporaries common between 32 and 64 bit modes. */ 158 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; 159 extern TCGv_i64 cpu_exclusive_addr; 160 extern TCGv_i64 cpu_exclusive_val; 161 162 /* 163 * Constant expanders for the decoders. 164 */ 165 166 static inline int negate(DisasContext *s, int x) 167 { 168 return -x; 169 } 170 171 static inline int plus_1(DisasContext *s, int x) 172 { 173 return x + 1; 174 } 175 176 static inline int plus_2(DisasContext *s, int x) 177 { 178 return x + 2; 179 } 180 181 static inline int plus_12(DisasContext *s, int x) 182 { 183 return x + 12; 184 } 185 186 static inline int times_2(DisasContext *s, int x) 187 { 188 return x * 2; 189 } 190 191 static inline int times_4(DisasContext *s, int x) 192 { 193 return x * 4; 194 } 195 196 static inline int times_2_plus_1(DisasContext *s, int x) 197 { 198 return x * 2 + 1; 199 } 200 201 static inline int rsub_64(DisasContext *s, int x) 202 { 203 return 64 - x; 204 } 205 206 static inline int rsub_32(DisasContext *s, int x) 207 { 208 return 32 - x; 209 } 210 211 static inline int rsub_16(DisasContext *s, int x) 212 { 213 return 16 - x; 214 } 215 216 static inline int rsub_8(DisasContext *s, int x) 217 { 218 return 8 - x; 219 } 220 221 static inline int neon_3same_fp_size(DisasContext *s, int x) 222 { 223 /* Convert 0==fp32, 1==fp16 into a MO_* value */ 224 return MO_32 - x; 225 } 226 227 static inline int arm_dc_feature(DisasContext *dc, int feature) 228 { 229 return (dc->features & (1ULL << feature)) != 0; 230 } 231 232 static inline int get_mem_index(DisasContext *s) 233 { 234 return arm_to_core_mmu_idx(s->mmu_idx); 235 } 236 237 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) 238 { 239 /* We don't need to save all of the syndrome so we mask and shift 240 * out unneeded bits to help the sleb128 encoder do a better job. 241 */ 242 syn &= ARM_INSN_START_WORD2_MASK; 243 syn >>= ARM_INSN_START_WORD2_SHIFT; 244 245 /* We check and clear insn_start_idx to catch multiple updates. */ 246 assert(s->insn_start != NULL); 247 tcg_set_insn_start_param(s->insn_start, 2, syn); 248 s->insn_start = NULL; 249 } 250 251 static inline int curr_insn_len(DisasContext *s) 252 { 253 return s->base.pc_next - s->pc_curr; 254 } 255 256 /* is_jmp field values */ 257 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 258 /* CPU state was modified dynamically; exit to main loop for interrupts. */ 259 #define DISAS_UPDATE_EXIT DISAS_TARGET_1 260 /* These instructions trap after executing, so the A32/T32 decoder must 261 * defer them until after the conditional execution state has been updated. 262 * WFI also needs special handling when single-stepping. 263 */ 264 #define DISAS_WFI DISAS_TARGET_2 265 #define DISAS_SWI DISAS_TARGET_3 266 /* WFE */ 267 #define DISAS_WFE DISAS_TARGET_4 268 #define DISAS_HVC DISAS_TARGET_5 269 #define DISAS_SMC DISAS_TARGET_6 270 #define DISAS_YIELD DISAS_TARGET_7 271 /* M profile branch which might be an exception return (and so needs 272 * custom end-of-TB code) 273 */ 274 #define DISAS_BX_EXCRET DISAS_TARGET_8 275 /* 276 * For instructions which want an immediate exit to the main loop, as opposed 277 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this 278 * doesn't write the PC on exiting the translation loop so you need to ensure 279 * something (gen_a64_update_pc or runtime helper) has done so before we reach 280 * return from cpu_tb_exec. 281 */ 282 #define DISAS_EXIT DISAS_TARGET_9 283 /* CPU state was modified dynamically; no need to exit, but do not chain. */ 284 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 285 286 #ifdef TARGET_AARCH64 287 void a64_translate_init(void); 288 void gen_a64_update_pc(DisasContext *s, target_long diff); 289 extern const TranslatorOps aarch64_translator_ops; 290 #else 291 static inline void a64_translate_init(void) 292 { 293 } 294 295 static inline void gen_a64_update_pc(DisasContext *s, target_long diff) 296 { 297 } 298 #endif 299 300 void arm_test_cc(DisasCompare *cmp, int cc); 301 void arm_free_cc(DisasCompare *cmp); 302 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label); 303 void arm_gen_test_cc(int cc, TCGLabel *label); 304 MemOp pow2_align(unsigned i); 305 void unallocated_encoding(DisasContext *s); 306 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp, 307 uint32_t syn, uint32_t target_el); 308 void gen_exception_insn(DisasContext *s, target_long pc_diff, 309 int excp, uint32_t syn); 310 311 /* Return state of Alternate Half-precision flag, caller frees result */ 312 static inline TCGv_i32 get_ahp_flag(void) 313 { 314 TCGv_i32 ret = tcg_temp_new_i32(); 315 316 tcg_gen_ld_i32(ret, cpu_env, 317 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR])); 318 tcg_gen_extract_i32(ret, ret, 26, 1); 319 320 return ret; 321 } 322 323 /* Set bits within PSTATE. */ 324 static inline void set_pstate_bits(uint32_t bits) 325 { 326 TCGv_i32 p = tcg_temp_new_i32(); 327 328 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 329 330 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 331 tcg_gen_ori_i32(p, p, bits); 332 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 333 tcg_temp_free_i32(p); 334 } 335 336 /* Clear bits within PSTATE. */ 337 static inline void clear_pstate_bits(uint32_t bits) 338 { 339 TCGv_i32 p = tcg_temp_new_i32(); 340 341 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); 342 343 tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 344 tcg_gen_andi_i32(p, p, ~bits); 345 tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); 346 tcg_temp_free_i32(p); 347 } 348 349 /* If the singlestep state is Active-not-pending, advance to Active-pending. */ 350 static inline void gen_ss_advance(DisasContext *s) 351 { 352 if (s->ss_active) { 353 s->pstate_ss = 0; 354 clear_pstate_bits(PSTATE_SS); 355 } 356 } 357 358 /* Generate an architectural singlestep exception */ 359 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) 360 { 361 /* Fill in the same_el field of the syndrome in the helper. */ 362 uint32_t syn = syn_swstep(false, isv, ex); 363 gen_helper_exception_swstep(cpu_env, tcg_constant_i32(syn)); 364 } 365 366 /* 367 * Given a VFP floating point constant encoded into an 8 bit immediate in an 368 * instruction, expand it to the actual constant value of the specified 369 * size, as per the VFPExpandImm() pseudocode in the Arm ARM. 370 */ 371 uint64_t vfp_expand_imm(int size, uint8_t imm8); 372 373 /* Vector operations shared between ARM and AArch64. */ 374 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 375 uint32_t opr_sz, uint32_t max_sz); 376 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 377 uint32_t opr_sz, uint32_t max_sz); 378 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 379 uint32_t opr_sz, uint32_t max_sz); 380 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 381 uint32_t opr_sz, uint32_t max_sz); 382 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 383 uint32_t opr_sz, uint32_t max_sz); 384 385 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 386 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 387 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 388 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 389 390 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 391 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 392 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 393 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 394 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 395 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 396 397 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 398 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 399 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); 400 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 401 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); 402 403 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 404 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 405 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 406 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 407 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 408 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 409 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 410 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 411 412 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 413 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 414 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 415 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 416 417 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 418 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 419 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 420 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 421 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 422 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 423 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 424 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 425 426 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 427 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 428 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs, 429 int64_t shift, uint32_t opr_sz, uint32_t max_sz); 430 431 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 432 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 433 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 434 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 435 436 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 437 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 438 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 439 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 440 441 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 442 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 443 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, 444 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz); 445 446 /* 447 * Forward to the isar_feature_* tests given a DisasContext pointer. 448 */ 449 #define dc_isar_feature(name, ctx) \ 450 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); }) 451 452 /* Note that the gvec expanders operate on offsets + sizes. */ 453 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t); 454 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t, 455 uint32_t, uint32_t); 456 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t, 457 uint32_t, uint32_t, uint32_t); 458 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t, 459 uint32_t, uint32_t, uint32_t); 460 461 /* Function prototype for gen_ functions for calling Neon helpers */ 462 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32); 463 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); 464 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); 465 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 466 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32, 467 TCGv_i32, TCGv_i32); 468 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); 469 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); 470 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); 471 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); 472 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); 473 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32); 474 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr); 475 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); 476 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); 477 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64); 478 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); 479 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); 480 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); 481 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp); 482 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift); 483 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32); 484 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift); 485 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); 486 487 /** 488 * arm_tbflags_from_tb: 489 * @tb: the TranslationBlock 490 * 491 * Extract the flag values from @tb. 492 */ 493 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb) 494 { 495 return (CPUARMTBFlags){ tb->flags, tb->cs_base }; 496 } 497 498 /* 499 * Enum for argument to fpstatus_ptr(). 500 */ 501 typedef enum ARMFPStatusFlavour { 502 FPST_FPCR, 503 FPST_FPCR_F16, 504 FPST_STD, 505 FPST_STD_F16, 506 } ARMFPStatusFlavour; 507 508 /** 509 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field 510 * 511 * We have multiple softfloat float_status fields in the Arm CPU state struct 512 * (see the comment in cpu.h for details). Return a TCGv_ptr which has 513 * been set up to point to the requested field in the CPU state struct. 514 * The options are: 515 * 516 * FPST_FPCR 517 * for non-FP16 operations controlled by the FPCR 518 * FPST_FPCR_F16 519 * for operations controlled by the FPCR where FPCR.FZ16 is to be used 520 * FPST_STD 521 * for A32/T32 Neon operations using the "standard FPSCR value" 522 * FPST_STD_F16 523 * as FPST_STD, but where FPCR.FZ16 is to be used 524 */ 525 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour) 526 { 527 TCGv_ptr statusptr = tcg_temp_new_ptr(); 528 int offset; 529 530 switch (flavour) { 531 case FPST_FPCR: 532 offset = offsetof(CPUARMState, vfp.fp_status); 533 break; 534 case FPST_FPCR_F16: 535 offset = offsetof(CPUARMState, vfp.fp_status_f16); 536 break; 537 case FPST_STD: 538 offset = offsetof(CPUARMState, vfp.standard_fp_status); 539 break; 540 case FPST_STD_F16: 541 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16); 542 break; 543 default: 544 g_assert_not_reached(); 545 } 546 tcg_gen_addi_ptr(statusptr, cpu_env, offset); 547 return statusptr; 548 } 549 550 /** 551 * finalize_memop: 552 * @s: DisasContext 553 * @opc: size+sign+align of the memory operation 554 * 555 * Build the complete MemOp for a memory operation, including alignment 556 * and endianness. 557 * 558 * If (op & MO_AMASK) then the operation already contains the required 559 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally 560 * unaligned operation, e.g. for AccType_NORMAL. 561 * 562 * In the latter case, there are configuration bits that require alignment, 563 * and this is applied here. Note that there is no way to indicate that 564 * no alignment should ever be enforced; this must be handled manually. 565 */ 566 static inline MemOp finalize_memop(DisasContext *s, MemOp opc) 567 { 568 if (s->align_mem && !(opc & MO_AMASK)) { 569 opc |= MO_ALIGN; 570 } 571 return opc | s->be_data; 572 } 573 574 /** 575 * asimd_imm_const: Expand an encoded SIMD constant value 576 * 577 * Expand a SIMD constant value. This is essentially the pseudocode 578 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for 579 * VMVN and VBIC (when cmode < 14 && op == 1). 580 * 581 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32; 582 * callers must catch this; we return the 64-bit constant value defined 583 * for AArch64. 584 * 585 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but 586 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; 587 * we produce an immediate constant value of 0 in these cases. 588 */ 589 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op); 590 591 /* 592 * gen_disas_label: 593 * Create a label and cache a copy of pc_save. 594 */ 595 static inline DisasLabel gen_disas_label(DisasContext *s) 596 { 597 return (DisasLabel){ 598 .label = gen_new_label(), 599 .pc_save = s->pc_save, 600 }; 601 } 602 603 /* 604 * set_disas_label: 605 * Emit a label and restore the cached copy of pc_save. 606 */ 607 static inline void set_disas_label(DisasContext *s, DisasLabel l) 608 { 609 gen_set_label(l.label); 610 s->pc_save = l.pc_save; 611 } 612 613 /* 614 * Helpers for implementing sets of trans_* functions. 615 * Defer the implementation of NAME to FUNC, with optional extra arguments. 616 */ 617 #define TRANS(NAME, FUNC, ...) \ 618 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 619 { return FUNC(s, __VA_ARGS__); } 620 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \ 621 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 622 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); } 623 624 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \ 625 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \ 626 { \ 627 s->is_nonstreaming = true; \ 628 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \ 629 } 630 631 #endif /* TARGET_ARM_TRANSLATE_H */