sve.decode (78754B)
1 # AArch64 SVE instruction descriptions 2 # 3 # Copyright (c) 2017 Linaro, Ltd 4 # 5 # This library is free software; you can redistribute it and/or 6 # modify it under the terms of the GNU Lesser General Public 7 # License as published by the Free Software Foundation; either 8 # version 2.1 of the License, or (at your option) any later version. 9 # 10 # This library is distributed in the hope that it will be useful, 11 # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 # Lesser General Public License for more details. 14 # 15 # You should have received a copy of the GNU Lesser General Public 16 # License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18 # 19 # This file is processed by scripts/decodetree.py 20 # 21 22 ########################################################################### 23 # Named fields. These are primarily for disjoint fields. 24 25 %imm4_16_p1 16:4 !function=plus_1 26 %imm6_22_5 22:1 5:5 27 %imm7_22_16 22:2 16:5 28 %imm8_16_10 16:5 10:3 29 %imm9_16_10 16:s6 10:3 30 %size_23 23:2 31 %dtype_23_13 23:2 13:2 32 %index3_22_19 22:1 19:2 33 %index3_19_11 19:2 11:1 34 %index2_20_11 20:1 11:1 35 36 # A combination of tsz:imm3 -- extract esize. 37 %tszimm_esz 22:2 5:5 !function=tszimm_esz 38 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3) 39 %tszimm_shr 22:2 5:5 !function=tszimm_shr 40 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize 41 %tszimm_shl 22:2 5:5 !function=tszimm_shl 42 43 # Similarly for the tszh/tszl pair at 22/16 for zzi 44 %tszimm16_esz 22:2 16:5 !function=tszimm_esz 45 %tszimm16_shr 22:2 16:5 !function=tszimm_shr 46 %tszimm16_shl 22:2 16:5 !function=tszimm_shl 47 48 # Signed 8-bit immediate, optionally shifted left by 8. 49 %sh8_i8s 5:9 !function=expand_imm_sh8s 50 # Unsigned 8-bit immediate, optionally shifted left by 8. 51 %sh8_i8u 5:9 !function=expand_imm_sh8u 52 53 # Unsigned load of msz into esz=2, represented as a dtype. 54 %msz_dtype 23:2 !function=msz_dtype 55 56 # Either a copy of rd (at bit 0), or a different source 57 # as propagated via the MOVPRFX instruction. 58 %reg_movprfx 0:5 59 60 ########################################################################### 61 # Named attribute sets. These are used to make nice(er) names 62 # when creating helpers common to those for the individual 63 # instruction patterns. 64 65 &rr_esz rd rn esz 66 &rri rd rn imm 67 &rr_dbm rd rn dbm 68 &rrri rd rn rm imm 69 &rri_esz rd rn imm esz 70 &rrri_esz rd rn rm imm esz 71 &rrr_esz rd rn rm esz 72 &rrx_esz rd rn rm index esz 73 &rpr_esz rd pg rn esz 74 &rpr_s rd pg rn s 75 &rprr_s rd pg rn rm s 76 &rprr_esz rd pg rn rm esz 77 &rrrr_esz rd ra rn rm esz 78 &rrxr_esz rd rn rm ra index esz 79 &rprrr_esz rd pg rn rm ra esz 80 &rpri_esz rd pg rn imm esz 81 &ptrue rd esz pat s 82 &incdec_cnt rd pat esz imm d u 83 &incdec2_cnt rd rn pat esz imm d u 84 &incdec_pred rd pg esz d u 85 &incdec2_pred rd rn pg esz d u 86 &rprr_load rd pg rn rm dtype nreg 87 &rpri_load rd pg rn imm dtype nreg 88 &rprr_store rd pg rn rm msz esz nreg 89 &rpri_store rd pg rn imm msz esz nreg 90 &rprr_gather_load rd pg rn rm esz msz u ff xs scale 91 &rpri_gather_load rd pg rn imm esz msz u ff 92 &rprr_scatter_store rd pg rn rm esz msz xs scale 93 &rpri_scatter_store rd pg rn imm esz msz 94 95 ########################################################################### 96 # Named instruction formats. These are generally used to 97 # reduce the amount of duplication between instruction patterns. 98 99 # Two operand with unused vector element size 100 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0 101 102 # Two operand 103 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz 104 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz 105 106 # Two operand with governing predicate, flags setting 107 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s 108 @pd_pg_pn_s0 ........ . . ...... .. pg:4 . rn:4 . rd:4 &rpr_s s=0 109 110 # Three operand with unused vector element size 111 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 112 113 # Three predicate operand, with governing predicate, flag setting 114 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s 115 116 # Three operand, vector element size 117 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz 118 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz 119 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \ 120 &rrr_esz rn=%reg_movprfx 121 @rdn_rm_e0 ........ .. ...... ...... rm:5 rd:5 \ 122 &rrr_esz rn=%reg_movprfx esz=0 123 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \ 124 &rri_esz rn=%reg_movprfx imm=%sh8_i8u 125 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \ 126 &rri_esz rn=%reg_movprfx 127 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \ 128 &rri_esz rn=%reg_movprfx 129 130 # Four operand, vector element size 131 @rda_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 \ 132 &rrrr_esz ra=%reg_movprfx 133 134 # Four operand with unused vector element size 135 @rda_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 \ 136 &rrrr_esz esz=0 ra=%reg_movprfx 137 @rdn_ra_rm_e0 ........ ... rm:5 ... ... ra:5 rd:5 \ 138 &rrrr_esz esz=0 rn=%reg_movprfx 139 140 # Three operand with "memory" size, aka immediate left shift 141 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri 142 143 # Two register operand, with governing predicate, vector element size 144 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \ 145 &rprr_esz rn=%reg_movprfx 146 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \ 147 &rprr_esz rm=%reg_movprfx 148 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz 149 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz 150 151 # Three register operand, with governing predicate, vector element size 152 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \ 153 &rprrr_esz ra=%reg_movprfx 154 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \ 155 &rprrr_esz rn=%reg_movprfx 156 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \ 157 &rprrr_esz rn=%reg_movprfx 158 @rd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 &rprr_esz 159 160 # One register operand, with governing predicate, vector element size 161 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz 162 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz 163 @pd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 . rd:4 &rpr_esz 164 165 # One register operand, with governing predicate, no vector element size 166 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0 167 168 # Two register operands with a 6-bit signed immediate. 169 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri 170 171 # Two register operand, one immediate operand, with predicate, 172 # element size encoded as TSZHL. 173 @rdn_pg_tszimm_shl ........ .. ... ... ... pg:3 ..... rd:5 \ 174 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shl 175 @rdn_pg_tszimm_shr ........ .. ... ... ... pg:3 ..... rd:5 \ 176 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz imm=%tszimm_shr 177 178 # Similarly without predicate. 179 @rd_rn_tszimm_shl ........ .. ... ... ...... rn:5 rd:5 \ 180 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shl 181 @rd_rn_tszimm_shr ........ .. ... ... ...... rn:5 rd:5 \ 182 &rri_esz esz=%tszimm16_esz imm=%tszimm16_shr 183 184 # Two register operand, one immediate operand, with 4-bit predicate. 185 # User must fill in imm. 186 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \ 187 &rpri_esz rn=%reg_movprfx 188 189 # Two register operand, one one-bit floating-point operand. 190 @rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \ 191 &rpri_esz rn=%reg_movprfx 192 193 # Two register operand, one encoded bitmask. 194 @rdn_dbm ........ .. .... dbm:13 rd:5 \ 195 &rr_dbm rn=%reg_movprfx 196 197 # Predicate output, vector and immediate input, 198 # controlling predicate, element size. 199 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz 200 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz 201 202 # Basic Load/Store with 9-bit immediate offset 203 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \ 204 &rri imm=%imm9_16_10 205 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \ 206 &rri imm=%imm9_16_10 207 208 # One register, pattern, and uint4+1. 209 # User must fill in U and D. 210 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 211 &incdec_cnt imm=%imm4_16_p1 212 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \ 213 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx 214 215 # One register, predicate. 216 # User must fill in U and D. 217 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred 218 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \ 219 &incdec2_pred rn=%reg_movprfx 220 221 # Loads; user must fill in NREG. 222 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load 223 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load 224 225 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \ 226 &rprr_load dtype=%msz_dtype 227 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \ 228 &rpri_load dtype=%msz_dtype 229 230 # Gather Loads. 231 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 232 &rprr_gather_load xs=2 233 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 234 &rprr_gather_load 235 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 236 &rprr_gather_load 237 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 238 &rprr_gather_load 239 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 240 &rprr_gather_load xs=2 241 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \ 242 &rprr_gather_load xs=2 243 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \ 244 &rpri_gather_load 245 246 # Stores; user must fill in ESZ, MSZ, NREG as needed. 247 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store 248 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store 249 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \ 250 &rprr_store nreg=0 251 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \ 252 &rprr_scatter_store 253 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \ 254 &rpri_scatter_store 255 256 # Two registers and a scalar by N-bit index 257 @rrx_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 258 &rrx_esz index=%index3_22_19 259 @rrx_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 &rrx_esz 260 @rrx_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 &rrx_esz 261 262 # Two registers and a scalar by N-bit index, alternate 263 @rrx_3a ........ .. . .. rm:3 ...... rn:5 rd:5 \ 264 &rrx_esz index=%index3_19_11 265 @rrx_2a ........ .. . . rm:4 ...... rn:5 rd:5 \ 266 &rrx_esz index=%index2_20_11 267 268 # Three registers and a scalar by N-bit index 269 @rrxr_3 ........ .. . .. rm:3 ...... rn:5 rd:5 \ 270 &rrxr_esz ra=%reg_movprfx index=%index3_22_19 271 @rrxr_2 ........ .. . index:2 rm:3 ...... rn:5 rd:5 \ 272 &rrxr_esz ra=%reg_movprfx 273 @rrxr_1 ........ .. . index:1 rm:4 ...... rn:5 rd:5 \ 274 &rrxr_esz ra=%reg_movprfx 275 276 # Three registers and a scalar by N-bit index, alternate 277 @rrxr_3a ........ .. ... rm:3 ...... rn:5 rd:5 \ 278 &rrxr_esz ra=%reg_movprfx index=%index3_19_11 279 @rrxr_2a ........ .. .. rm:4 ...... rn:5 rd:5 \ 280 &rrxr_esz ra=%reg_movprfx index=%index2_20_11 281 282 ########################################################################### 283 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml. 284 285 ### SVE Integer Arithmetic - Binary Predicated Group 286 287 # SVE bitwise logical vector operations (predicated) 288 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm 289 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm 290 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm 291 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm 292 293 # SVE integer add/subtract vectors (predicated) 294 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm 295 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm 296 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR 297 298 # SVE integer min/max/difference (predicated) 299 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm 300 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm 301 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm 302 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm 303 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm 304 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm 305 306 # SVE integer multiply/divide (predicated) 307 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm 308 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm 309 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm 310 # Note that divide requires size >= 2; below 2 is unallocated. 311 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm 312 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm 313 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR 314 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR 315 316 ### SVE Integer Reduction Group 317 318 # SVE bitwise logical reduction (predicated) 319 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn 320 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn 321 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn 322 323 # SVE constructive prefix (predicated) 324 MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn 325 MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn 326 327 # SVE integer add reduction (predicated) 328 # Note that saddv requires size != 3. 329 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn 330 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn 331 332 # SVE integer min/max reduction (predicated) 333 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn 334 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn 335 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn 336 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn 337 338 ### SVE Shift by Immediate - Predicated Group 339 340 # SVE bitwise shift by immediate (predicated) 341 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... @rdn_pg_tszimm_shr 342 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... @rdn_pg_tszimm_shr 343 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... @rdn_pg_tszimm_shl 344 ASRD 00000100 .. 000 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 345 SQSHL_zpzi 00000100 .. 000 110 100 ... .. ... ..... @rdn_pg_tszimm_shl 346 UQSHL_zpzi 00000100 .. 000 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 347 SRSHR 00000100 .. 001 100 100 ... .. ... ..... @rdn_pg_tszimm_shr 348 URSHR 00000100 .. 001 101 100 ... .. ... ..... @rdn_pg_tszimm_shr 349 SQSHLU 00000100 .. 001 111 100 ... .. ... ..... @rdn_pg_tszimm_shl 350 351 # SVE bitwise shift by vector (predicated) 352 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 353 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 354 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 355 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR 356 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR 357 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR 358 359 # SVE bitwise shift by wide elements (predicated) 360 # Note these require size != 3. 361 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 362 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 363 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 364 365 ### SVE Integer Arithmetic - Unary Predicated Group 366 367 # SVE unary bit operations (predicated) 368 # Note esz != 0 for FABS and FNEG. 369 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn 370 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn 371 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn 372 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn 373 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn 374 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn 375 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn 376 377 # SVE integer unary operations (predicated) 378 # Note esz > original size for extensions. 379 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn 380 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn 381 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn 382 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn 383 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn 384 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn 385 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn 386 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn 387 388 ### SVE Floating Point Compare - Vectors Group 389 390 # SVE floating-point compare vectors 391 FCMGE_ppzz 01100101 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 392 FCMGT_ppzz 01100101 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 393 FCMEQ_ppzz 01100101 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 394 FCMNE_ppzz 01100101 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 395 FCMUO_ppzz 01100101 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 396 FACGE_ppzz 01100101 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 397 FACGT_ppzz 01100101 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 398 399 ### SVE Integer Multiply-Add Group 400 401 # SVE integer multiply-add writing addend (predicated) 402 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm 403 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm 404 405 # SVE integer multiply-add writing multiplicand (predicated) 406 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD 407 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB 408 409 ### SVE Integer Arithmetic - Unpredicated Group 410 411 # SVE integer add/subtract vectors (unpredicated) 412 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm 413 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm 414 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm 415 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm 416 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm 417 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm 418 419 ### SVE Logical - Unpredicated Group 420 421 # SVE bitwise logical operations (unpredicated) 422 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 423 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 424 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 425 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0 426 427 XAR 00000100 .. 1 ..... 001 101 rm:5 rd:5 &rrri_esz \ 428 rn=%reg_movprfx esz=%tszimm16_esz imm=%tszimm16_shr 429 430 # SVE2 bitwise ternary operations 431 EOR3 00000100 00 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 432 BSL 00000100 00 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 433 BCAX 00000100 01 1 ..... 001 110 ..... ..... @rdn_ra_rm_e0 434 BSL1N 00000100 01 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 435 BSL2N 00000100 10 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 436 NBSL 00000100 11 1 ..... 001 111 ..... ..... @rdn_ra_rm_e0 437 438 ### SVE Index Generation Group 439 440 # SVE index generation (immediate start, immediate increment) 441 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5 442 443 # SVE index generation (immediate start, register increment) 444 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5 445 446 # SVE index generation (register start, immediate increment) 447 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 448 449 # SVE index generation (register start, register increment) 450 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm 451 452 ### SVE / Streaming SVE Stack Allocation Group 453 454 # SVE stack frame adjustment 455 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 456 ADDSVL 00000100 001 ..... 01011 ...... ..... @rd_rn_i6 457 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 458 ADDSPL 00000100 011 ..... 01011 ...... ..... @rd_rn_i6 459 460 # SVE stack frame size 461 RDVL 00000100 101 11111 01010 imm:s6 rd:5 462 RDSVL 00000100 101 11111 01011 imm:s6 rd:5 463 464 ### SVE Bitwise Shift - Unpredicated Group 465 466 # SVE bitwise shift by immediate (unpredicated) 467 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... @rd_rn_tszimm_shr 468 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... @rd_rn_tszimm_shr 469 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... @rd_rn_tszimm_shl 470 471 # SVE bitwise shift by wide elements (unpredicated) 472 # Note esz != 3 473 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm 474 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm 475 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm 476 477 ### SVE Compute Vector Address Group 478 479 # SVE vector address generation 480 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 481 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 482 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 483 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm 484 485 ### SVE Integer Misc - Unpredicated Group 486 487 # SVE constructive prefix (unpredicated) 488 MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5 489 490 # SVE floating-point exponential accelerator 491 # Note esz != 0 492 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn 493 494 # SVE floating-point trig select coefficient 495 # Note esz != 0 496 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm 497 498 ### SVE Element Count Group 499 500 # SVE element count 501 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1 502 503 # SVE inc/dec register by element count 504 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1 505 506 # SVE saturating inc/dec register by element count 507 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 508 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt 509 510 # SVE inc/dec vector by element count 511 # Note this requires esz != 0. 512 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1 513 514 # SVE saturating inc/dec vector by element count 515 # Note these require esz != 0. 516 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt 517 518 ### SVE Bitwise Immediate Group 519 520 # SVE bitwise logical with immediate (unpredicated) 521 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm 522 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm 523 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm 524 525 # SVE broadcast bitmask immediate 526 DUPM 00000101 11 0000 dbm:13 rd:5 527 528 ### SVE Integer Wide Immediate - Predicated Group 529 530 # SVE copy floating-point immediate (predicated) 531 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4 532 533 # SVE copy integer immediate (predicated) 534 { 535 INVALID 00000101 00 01 ---- 01 1 -------- ----- 536 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s 537 } 538 { 539 INVALID 00000101 00 01 ---- 00 1 -------- ----- 540 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s 541 } 542 543 ### SVE Permute - Extract Group 544 545 # SVE extract vector (destructive) 546 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \ 547 &rrri rn=%reg_movprfx imm=%imm8_16_10 548 549 # SVE2 extract vector (constructive) 550 EXT_sve2 00000101 011 ..... 000 ... rn:5 rd:5 \ 551 &rri imm=%imm8_16_10 552 553 ### SVE Permute - Unpredicated Group 554 555 # SVE broadcast general register 556 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn 557 558 # SVE broadcast indexed element 559 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \ 560 &rri imm=%imm7_22_16 561 562 # SVE insert SIMD&FP scalar register 563 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm 564 565 # SVE insert general register 566 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm 567 568 # SVE reverse vector elements 569 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn 570 571 # SVE vector table lookup 572 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm 573 574 # SVE unpack vector elements 575 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5 576 577 # SVE2 Table Lookup (three sources) 578 579 TBL_sve2 00000101 .. 1 ..... 001010 ..... ..... @rd_rn_rm 580 TBX 00000101 .. 1 ..... 001011 ..... ..... @rd_rn_rm 581 582 ### SVE Permute - Predicates Group 583 584 # SVE permute predicate elements 585 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm 586 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm 587 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm 588 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm 589 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm 590 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm 591 592 # SVE reverse predicate elements 593 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn 594 595 # SVE unpack predicate elements 596 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0 597 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0 598 599 ### SVE Permute - Interleaving Group 600 601 # SVE permute vector elements 602 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 603 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 604 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 605 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 606 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 607 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 608 609 # SVE2 permute vector segments 610 ZIP1_q 00000101 10 1 ..... 000 000 ..... ..... @rd_rn_rm_e0 611 ZIP2_q 00000101 10 1 ..... 000 001 ..... ..... @rd_rn_rm_e0 612 UZP1_q 00000101 10 1 ..... 000 010 ..... ..... @rd_rn_rm_e0 613 UZP2_q 00000101 10 1 ..... 000 011 ..... ..... @rd_rn_rm_e0 614 TRN1_q 00000101 10 1 ..... 000 110 ..... ..... @rd_rn_rm_e0 615 TRN2_q 00000101 10 1 ..... 000 111 ..... ..... @rd_rn_rm_e0 616 617 ### SVE Permute - Predicated Group 618 619 # SVE compress active elements 620 # Note esz >= 2 621 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn 622 623 # SVE conditionally broadcast element to vector 624 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm 625 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm 626 627 # SVE conditionally copy element to SIMD&FP scalar 628 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn 629 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn 630 631 # SVE conditionally copy element to general register 632 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn 633 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn 634 635 # SVE copy element to SIMD&FP scalar register 636 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn 637 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn 638 639 # SVE copy element to general register 640 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn 641 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn 642 643 # SVE copy element from SIMD&FP scalar register 644 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn 645 646 # SVE copy element from general register to vector (predicated) 647 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn 648 649 # SVE reverse within elements 650 # Note esz >= operation size 651 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn 652 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn 653 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn 654 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn 655 REVD 00000101 00 1011 10 100 ... ..... ..... @rd_pg_rn_e0 656 657 # SVE vector splice (predicated, destructive) 658 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm 659 660 # SVE2 vector splice (predicated, constructive) 661 SPLICE_sve2 00000101 .. 101 101 100 ... ..... ..... @rd_pg_rn 662 663 ### SVE Select Vectors Group 664 665 # SVE select vector elements (predicated) 666 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm 667 668 ### SVE Integer Compare - Vectors Group 669 670 # SVE integer compare_vectors 671 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm 672 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm 673 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 674 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 675 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm 676 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm 677 678 # SVE integer compare with wide elements 679 # Note these require esz != 3. 680 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm 681 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm 682 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm 683 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm 684 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm 685 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm 686 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm 687 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm 688 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm 689 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm 690 691 ### SVE Integer Compare - Unsigned Immediate Group 692 693 # SVE integer compare with unsigned immediate 694 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7 695 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7 696 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7 697 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7 698 699 ### SVE Integer Compare - Signed Immediate Group 700 701 # SVE integer compare with signed immediate 702 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5 703 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5 704 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5 705 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5 706 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5 707 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5 708 709 ### SVE Predicate Logical Operations Group 710 711 # SVE predicate logical operations 712 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 713 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 714 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 715 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 716 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s 717 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s 718 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s 719 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s 720 721 ### SVE Predicate Misc Group 722 723 # SVE predicate test 724 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000 725 726 # SVE predicate initialize 727 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4 728 729 # SVE initialize FFR 730 SETFFR 00100101 0010 1100 1001 0000 0000 0000 731 732 # SVE zero predicate register 733 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4 734 735 # SVE predicate read from FFR (predicated) 736 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4 737 738 # SVE predicate read from FFR (unpredicated) 739 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4 740 741 # SVE FFR write from predicate (WRFFR) 742 WRFFR 00100101 0010 1000 1001 000 rn:4 00000 743 744 # SVE predicate first active 745 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0 746 747 # SVE predicate next active 748 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn 749 750 ### SVE Partition Break Group 751 752 # SVE propagate break from previous partition 753 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s 754 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s 755 756 # SVE partition break condition 757 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 758 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s 759 BRKA_m 00100101 00 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 760 BRKB_m 00100101 10 01000001 .... 0 .... 1 .... @pd_pg_pn_s0 761 762 # SVE propagate break to next partition 763 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s 764 765 ### SVE Predicate Count Group 766 767 # SVE predicate count 768 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn 769 770 # SVE inc/dec register by predicate count 771 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1 772 773 # SVE inc/dec vector by predicate count 774 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1 775 776 # SVE saturating inc/dec register by predicate count 777 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred 778 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred 779 780 # SVE saturating inc/dec vector by predicate count 781 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred 782 783 ### SVE Integer Compare - Scalars Group 784 785 # SVE conditionally terminate scalars 786 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000 787 788 # SVE integer compare scalar count and limit 789 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 lt:1 rn:5 eq:1 rd:4 790 791 # SVE2 pointer conflict compare 792 WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4 793 794 ### SVE Integer Wide Immediate - Unpredicated Group 795 796 # SVE broadcast floating-point immediate (unpredicated) 797 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5 798 799 # SVE broadcast integer immediate (unpredicated) 800 { 801 INVALID 00100101 00 111 00 011 1 -------- ----- 802 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s 803 } 804 805 # SVE integer add/subtract immediate (unpredicated) 806 { 807 INVALID 00100101 00 100 000 11 1 -------- ----- 808 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u 809 } 810 { 811 INVALID 00100101 00 100 001 11 1 -------- ----- 812 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u 813 } 814 { 815 INVALID 00100101 00 100 011 11 1 -------- ----- 816 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u 817 } 818 { 819 INVALID 00100101 00 100 100 11 1 -------- ----- 820 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u 821 } 822 { 823 INVALID 00100101 00 100 101 11 1 -------- ----- 824 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u 825 } 826 { 827 INVALID 00100101 00 100 110 11 1 -------- ----- 828 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u 829 } 830 { 831 INVALID 00100101 00 100 111 11 1 -------- ----- 832 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u 833 } 834 835 # SVE integer min/max immediate (unpredicated) 836 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s 837 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u 838 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s 839 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u 840 841 # SVE integer multiply immediate (unpredicated) 842 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s 843 844 # SVE integer dot product (unpredicated) 845 DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ 846 ra=%reg_movprfx 847 848 # SVE2 complex dot product (vectors) 849 CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=%reg_movprfx 850 851 #### SVE Multiply - Indexed 852 853 # SVE integer dot product (indexed) 854 SDOT_zzxw_s 01000100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 855 SDOT_zzxw_d 01000100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 856 UDOT_zzxw_s 01000100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 857 UDOT_zzxw_d 01000100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 858 859 # SVE2 integer multiply-add (indexed) 860 MLA_zzxz_h 01000100 0. 1 ..... 000010 ..... ..... @rrxr_3 esz=1 861 MLA_zzxz_s 01000100 10 1 ..... 000010 ..... ..... @rrxr_2 esz=2 862 MLA_zzxz_d 01000100 11 1 ..... 000010 ..... ..... @rrxr_1 esz=3 863 MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... ..... @rrxr_3 esz=1 864 MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2 865 MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3 866 867 # SVE2 saturating multiply-add high (indexed) 868 SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1 869 SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2 870 SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3 871 SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1 872 SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2 873 SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3 874 875 # SVE mixed sign dot product (indexed) 876 USDOT_zzxw_s 01000100 10 1 ..... 000110 ..... ..... @rrxr_2 esz=2 877 SUDOT_zzxw_s 01000100 10 1 ..... 000111 ..... ..... @rrxr_2 esz=2 878 879 # SVE2 saturating multiply-add (indexed) 880 SQDMLALB_zzxw_s 01000100 10 1 ..... 0010.0 ..... ..... @rrxr_3a esz=2 881 SQDMLALB_zzxw_d 01000100 11 1 ..... 0010.0 ..... ..... @rrxr_2a esz=3 882 SQDMLALT_zzxw_s 01000100 10 1 ..... 0010.1 ..... ..... @rrxr_3a esz=2 883 SQDMLALT_zzxw_d 01000100 11 1 ..... 0010.1 ..... ..... @rrxr_2a esz=3 884 SQDMLSLB_zzxw_s 01000100 10 1 ..... 0011.0 ..... ..... @rrxr_3a esz=2 885 SQDMLSLB_zzxw_d 01000100 11 1 ..... 0011.0 ..... ..... @rrxr_2a esz=3 886 SQDMLSLT_zzxw_s 01000100 10 1 ..... 0011.1 ..... ..... @rrxr_3a esz=2 887 SQDMLSLT_zzxw_d 01000100 11 1 ..... 0011.1 ..... ..... @rrxr_2a esz=3 888 889 # SVE2 complex integer dot product (indexed) 890 CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ 891 ra=%reg_movprfx 892 CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ 893 ra=%reg_movprfx 894 895 # SVE2 complex integer multiply-add (indexed) 896 CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ 897 ra=%reg_movprfx 898 CMLA_zzxz_s 01000100 11 1 index:1 rm:4 0110 rot:2 rn:5 rd:5 \ 899 ra=%reg_movprfx 900 901 # SVE2 complex saturating integer multiply-add (indexed) 902 SQRDCMLAH_zzxz_h 01000100 10 1 index:2 rm:3 0111 rot:2 rn:5 rd:5 \ 903 ra=%reg_movprfx 904 SQRDCMLAH_zzxz_s 01000100 11 1 index:1 rm:4 0111 rot:2 rn:5 rd:5 \ 905 ra=%reg_movprfx 906 907 # SVE2 multiply-add long (indexed) 908 SMLALB_zzxw_s 01000100 10 1 ..... 1000.0 ..... ..... @rrxr_3a esz=2 909 SMLALB_zzxw_d 01000100 11 1 ..... 1000.0 ..... ..... @rrxr_2a esz=3 910 SMLALT_zzxw_s 01000100 10 1 ..... 1000.1 ..... ..... @rrxr_3a esz=2 911 SMLALT_zzxw_d 01000100 11 1 ..... 1000.1 ..... ..... @rrxr_2a esz=3 912 UMLALB_zzxw_s 01000100 10 1 ..... 1001.0 ..... ..... @rrxr_3a esz=2 913 UMLALB_zzxw_d 01000100 11 1 ..... 1001.0 ..... ..... @rrxr_2a esz=3 914 UMLALT_zzxw_s 01000100 10 1 ..... 1001.1 ..... ..... @rrxr_3a esz=2 915 UMLALT_zzxw_d 01000100 11 1 ..... 1001.1 ..... ..... @rrxr_2a esz=3 916 SMLSLB_zzxw_s 01000100 10 1 ..... 1010.0 ..... ..... @rrxr_3a esz=2 917 SMLSLB_zzxw_d 01000100 11 1 ..... 1010.0 ..... ..... @rrxr_2a esz=3 918 SMLSLT_zzxw_s 01000100 10 1 ..... 1010.1 ..... ..... @rrxr_3a esz=2 919 SMLSLT_zzxw_d 01000100 11 1 ..... 1010.1 ..... ..... @rrxr_2a esz=3 920 UMLSLB_zzxw_s 01000100 10 1 ..... 1011.0 ..... ..... @rrxr_3a esz=2 921 UMLSLB_zzxw_d 01000100 11 1 ..... 1011.0 ..... ..... @rrxr_2a esz=3 922 UMLSLT_zzxw_s 01000100 10 1 ..... 1011.1 ..... ..... @rrxr_3a esz=2 923 UMLSLT_zzxw_d 01000100 11 1 ..... 1011.1 ..... ..... @rrxr_2a esz=3 924 925 # SVE2 integer multiply long (indexed) 926 SMULLB_zzx_s 01000100 10 1 ..... 1100.0 ..... ..... @rrx_3a esz=2 927 SMULLB_zzx_d 01000100 11 1 ..... 1100.0 ..... ..... @rrx_2a esz=3 928 SMULLT_zzx_s 01000100 10 1 ..... 1100.1 ..... ..... @rrx_3a esz=2 929 SMULLT_zzx_d 01000100 11 1 ..... 1100.1 ..... ..... @rrx_2a esz=3 930 UMULLB_zzx_s 01000100 10 1 ..... 1101.0 ..... ..... @rrx_3a esz=2 931 UMULLB_zzx_d 01000100 11 1 ..... 1101.0 ..... ..... @rrx_2a esz=3 932 UMULLT_zzx_s 01000100 10 1 ..... 1101.1 ..... ..... @rrx_3a esz=2 933 UMULLT_zzx_d 01000100 11 1 ..... 1101.1 ..... ..... @rrx_2a esz=3 934 935 # SVE2 saturating multiply (indexed) 936 SQDMULLB_zzx_s 01000100 10 1 ..... 1110.0 ..... ..... @rrx_3a esz=2 937 SQDMULLB_zzx_d 01000100 11 1 ..... 1110.0 ..... ..... @rrx_2a esz=3 938 SQDMULLT_zzx_s 01000100 10 1 ..... 1110.1 ..... ..... @rrx_3a esz=2 939 SQDMULLT_zzx_d 01000100 11 1 ..... 1110.1 ..... ..... @rrx_2a esz=3 940 941 # SVE2 saturating multiply high (indexed) 942 SQDMULH_zzx_h 01000100 0. 1 ..... 111100 ..... ..... @rrx_3 esz=1 943 SQDMULH_zzx_s 01000100 10 1 ..... 111100 ..... ..... @rrx_2 esz=2 944 SQDMULH_zzx_d 01000100 11 1 ..... 111100 ..... ..... @rrx_1 esz=3 945 SQRDMULH_zzx_h 01000100 0. 1 ..... 111101 ..... ..... @rrx_3 esz=1 946 SQRDMULH_zzx_s 01000100 10 1 ..... 111101 ..... ..... @rrx_2 esz=2 947 SQRDMULH_zzx_d 01000100 11 1 ..... 111101 ..... ..... @rrx_1 esz=3 948 949 # SVE2 integer multiply (indexed) 950 MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1 951 MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2 952 MUL_zzx_d 01000100 11 1 ..... 111110 ..... ..... @rrx_1 esz=3 953 954 # SVE floating-point complex add (predicated) 955 FCADD 01100100 esz:2 00000 rot:1 100 pg:3 rm:5 rd:5 \ 956 rn=%reg_movprfx 957 958 # SVE floating-point complex multiply-add (predicated) 959 FCMLA_zpzzz 01100100 esz:2 0 rm:5 0 rot:2 pg:3 rn:5 rd:5 \ 960 ra=%reg_movprfx 961 962 # SVE floating-point complex multiply-add (indexed) 963 FCMLA_zzxz 01100100 10 1 index:2 rm:3 0001 rot:2 rn:5 rd:5 \ 964 ra=%reg_movprfx esz=1 965 FCMLA_zzxz 01100100 11 1 index:1 rm:4 0001 rot:2 rn:5 rd:5 \ 966 ra=%reg_movprfx esz=2 967 968 ### SVE FP Multiply-Add Indexed Group 969 970 # SVE floating-point multiply-add (indexed) 971 FMLA_zzxz 01100100 0. 1 ..... 000000 ..... ..... @rrxr_3 esz=1 972 FMLA_zzxz 01100100 10 1 ..... 000000 ..... ..... @rrxr_2 esz=2 973 FMLA_zzxz 01100100 11 1 ..... 000000 ..... ..... @rrxr_1 esz=3 974 FMLS_zzxz 01100100 0. 1 ..... 000001 ..... ..... @rrxr_3 esz=1 975 FMLS_zzxz 01100100 10 1 ..... 000001 ..... ..... @rrxr_2 esz=2 976 FMLS_zzxz 01100100 11 1 ..... 000001 ..... ..... @rrxr_1 esz=3 977 978 ### SVE FP Multiply Indexed Group 979 980 # SVE floating-point multiply (indexed) 981 FMUL_zzx 01100100 0. 1 ..... 001000 ..... ..... @rrx_3 esz=1 982 FMUL_zzx 01100100 10 1 ..... 001000 ..... ..... @rrx_2 esz=2 983 FMUL_zzx 01100100 11 1 ..... 001000 ..... ..... @rrx_1 esz=3 984 985 ### SVE FP Fast Reduction Group 986 987 FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn 988 FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn 989 FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn 990 FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn 991 FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn 992 993 ## SVE Floating Point Unary Operations - Unpredicated Group 994 995 FRECPE 01100101 .. 001 110 001100 ..... ..... @rd_rn 996 FRSQRTE 01100101 .. 001 111 001100 ..... ..... @rd_rn 997 998 ### SVE FP Compare with Zero Group 999 1000 FCMGE_ppz0 01100101 .. 0100 00 001 ... ..... 0 .... @pd_pg_rn 1001 FCMGT_ppz0 01100101 .. 0100 00 001 ... ..... 1 .... @pd_pg_rn 1002 FCMLT_ppz0 01100101 .. 0100 01 001 ... ..... 0 .... @pd_pg_rn 1003 FCMLE_ppz0 01100101 .. 0100 01 001 ... ..... 1 .... @pd_pg_rn 1004 FCMEQ_ppz0 01100101 .. 0100 10 001 ... ..... 0 .... @pd_pg_rn 1005 FCMNE_ppz0 01100101 .. 0100 11 001 ... ..... 0 .... @pd_pg_rn 1006 1007 ### SVE FP Accumulating Reduction Group 1008 1009 # SVE floating-point serial reduction (predicated) 1010 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm 1011 1012 ### SVE Floating Point Arithmetic - Unpredicated Group 1013 1014 # SVE floating-point arithmetic (unpredicated) 1015 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm 1016 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm 1017 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm 1018 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm 1019 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm 1020 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm 1021 1022 ### SVE FP Arithmetic Predicated Group 1023 1024 # SVE floating-point arithmetic (predicated) 1025 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm 1026 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm 1027 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm 1028 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR 1029 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm 1030 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm 1031 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm 1032 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm 1033 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm 1034 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm 1035 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm 1036 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR 1037 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm 1038 1039 # SVE floating-point arithmetic with immediate (predicated) 1040 FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1 1041 FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1 1042 FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1 1043 FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1 1044 FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1 1045 FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1 1046 FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1 1047 FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1 1048 1049 # SVE floating-point trig multiply-add coefficient 1050 FTMAD 01100101 esz:2 010 imm:3 100000 rm:5 rd:5 rn=%reg_movprfx 1051 1052 ### SVE FP Multiply-Add Group 1053 1054 # SVE floating-point multiply-accumulate writing addend 1055 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm 1056 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm 1057 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm 1058 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm 1059 1060 # SVE floating-point multiply-accumulate writing multiplicand 1061 # Alter the operand extraction order and reuse the helpers from above. 1062 # FMAD, FMSB, FNMAD, FNMS 1063 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra 1064 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra 1065 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra 1066 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra 1067 1068 ### SVE FP Unary Operations Predicated Group 1069 1070 # SVE floating-point convert precision 1071 FCVT_sh 01100101 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1072 FCVT_hs 01100101 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1073 BFCVT 01100101 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1074 FCVT_dh 01100101 11 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1075 FCVT_hd 01100101 11 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1076 FCVT_ds 01100101 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1077 FCVT_sd 01100101 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1078 1079 # SVE floating-point convert to integer 1080 FCVTZS_hh 01100101 01 011 01 0 101 ... ..... ..... @rd_pg_rn_e0 1081 FCVTZU_hh 01100101 01 011 01 1 101 ... ..... ..... @rd_pg_rn_e0 1082 FCVTZS_hs 01100101 01 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1083 FCVTZU_hs 01100101 01 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1084 FCVTZS_hd 01100101 01 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1085 FCVTZU_hd 01100101 01 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1086 FCVTZS_ss 01100101 10 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1087 FCVTZU_ss 01100101 10 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1088 FCVTZS_ds 01100101 11 011 00 0 101 ... ..... ..... @rd_pg_rn_e0 1089 FCVTZU_ds 01100101 11 011 00 1 101 ... ..... ..... @rd_pg_rn_e0 1090 FCVTZS_sd 01100101 11 011 10 0 101 ... ..... ..... @rd_pg_rn_e0 1091 FCVTZU_sd 01100101 11 011 10 1 101 ... ..... ..... @rd_pg_rn_e0 1092 FCVTZS_dd 01100101 11 011 11 0 101 ... ..... ..... @rd_pg_rn_e0 1093 FCVTZU_dd 01100101 11 011 11 1 101 ... ..... ..... @rd_pg_rn_e0 1094 1095 # SVE floating-point round to integral value 1096 FRINTN 01100101 .. 000 000 101 ... ..... ..... @rd_pg_rn 1097 FRINTP 01100101 .. 000 001 101 ... ..... ..... @rd_pg_rn 1098 FRINTM 01100101 .. 000 010 101 ... ..... ..... @rd_pg_rn 1099 FRINTZ 01100101 .. 000 011 101 ... ..... ..... @rd_pg_rn 1100 FRINTA 01100101 .. 000 100 101 ... ..... ..... @rd_pg_rn 1101 FRINTX 01100101 .. 000 110 101 ... ..... ..... @rd_pg_rn 1102 FRINTI 01100101 .. 000 111 101 ... ..... ..... @rd_pg_rn 1103 1104 # SVE floating-point unary operations 1105 FRECPX 01100101 .. 001 100 101 ... ..... ..... @rd_pg_rn 1106 FSQRT 01100101 .. 001 101 101 ... ..... ..... @rd_pg_rn 1107 1108 # SVE integer convert to floating-point 1109 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0 1110 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1111 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1112 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1113 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0 1114 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0 1115 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0 1116 1117 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0 1118 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1119 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1120 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1121 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0 1122 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0 1123 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0 1124 1125 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group 1126 1127 # SVE load predicate register 1128 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9 1129 1130 # SVE load vector register 1131 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9 1132 1133 # SVE load and broadcast element 1134 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \ 1135 &rpri_load dtype=%dtype_23_13 nreg=0 1136 1137 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets) 1138 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets) 1139 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \ 1140 @rprr_g_load_xs_u esz=2 msz=0 scale=0 1141 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \ 1142 @rprr_g_load_xs_u_sc esz=2 msz=1 1143 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \ 1144 @rprr_g_load_xs_sc esz=2 msz=2 u=1 1145 1146 # SVE 32-bit gather load (vector plus immediate) 1147 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \ 1148 @rpri_g_load esz=2 1149 1150 ### SVE Memory Contiguous Load Group 1151 1152 # SVE contiguous load (scalar plus scalar) 1153 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0 1154 1155 # SVE contiguous first-fault load (scalar plus scalar) 1156 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0 1157 1158 # SVE contiguous load (scalar plus immediate) 1159 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0 1160 1161 # SVE contiguous non-fault load (scalar plus immediate) 1162 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0 1163 1164 # SVE contiguous non-temporal load (scalar plus scalar) 1165 # LDNT1B, LDNT1H, LDNT1W, LDNT1D 1166 # SVE load multiple structures (scalar plus scalar) 1167 # LD2B, LD2H, LD2W, LD2D; etc. 1168 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz 1169 1170 # SVE contiguous non-temporal load (scalar plus immediate) 1171 # LDNT1B, LDNT1H, LDNT1W, LDNT1D 1172 # SVE load multiple structures (scalar plus immediate) 1173 # LD2B, LD2H, LD2W, LD2D; etc. 1174 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz 1175 1176 # SVE load and broadcast quadword (scalar plus scalar) 1177 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \ 1178 @rprr_load_msz nreg=0 1179 LD1RO_zprr 1010010 .. 01 ..... 000 ... ..... ..... \ 1180 @rprr_load_msz nreg=0 1181 1182 # SVE load and broadcast quadword (scalar plus immediate) 1183 # LD1RQB, LD1RQH, LD1RQS, LD1RQD 1184 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \ 1185 @rpri_load_msz nreg=0 1186 LD1RO_zpri 1010010 .. 01 0.... 001 ... ..... ..... \ 1187 @rpri_load_msz nreg=0 1188 1189 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets) 1190 PRF_ns 1000010 00 -1 ----- 0-- --- ----- 0 ---- 1191 1192 # SVE 32-bit gather prefetch (vector plus immediate) 1193 PRF_ns 1000010 -- 00 ----- 111 --- ----- 0 ---- 1194 1195 # SVE contiguous prefetch (scalar plus immediate) 1196 PRF 1000010 11 1- ----- 0-- --- ----- 0 ---- 1197 1198 # SVE contiguous prefetch (scalar plus scalar) 1199 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ---- 1200 1201 ### SVE Memory 64-bit Gather Group 1202 1203 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets) 1204 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets) 1205 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \ 1206 @rprr_g_load_xs_u esz=3 msz=0 scale=0 1207 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \ 1208 @rprr_g_load_xs_u_sc esz=3 msz=1 1209 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \ 1210 @rprr_g_load_xs_u_sc esz=3 msz=2 1211 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \ 1212 @rprr_g_load_xs_sc esz=3 msz=3 u=1 1213 1214 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets) 1215 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets) 1216 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \ 1217 @rprr_g_load_u esz=3 msz=0 scale=0 1218 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \ 1219 @rprr_g_load_u_sc esz=3 msz=1 1220 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \ 1221 @rprr_g_load_u_sc esz=3 msz=2 1222 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \ 1223 @rprr_g_load_sc esz=3 msz=3 u=1 1224 1225 # SVE 64-bit gather load (vector plus immediate) 1226 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \ 1227 @rpri_g_load esz=3 1228 1229 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets) 1230 PRF_ns 1100010 00 11 ----- 1-- --- ----- 0 ---- 1231 1232 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets) 1233 PRF_ns 1100010 00 -1 ----- 0-- --- ----- 0 ---- 1234 1235 # SVE 64-bit gather prefetch (vector plus immediate) 1236 PRF_ns 1100010 -- 00 ----- 111 --- ----- 0 ---- 1237 1238 ### SVE Memory Store Group 1239 1240 # SVE store predicate register 1241 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9 1242 1243 # SVE store vector register 1244 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9 1245 1246 # SVE contiguous store (scalar plus immediate) 1247 # ST1B, ST1H, ST1W, ST1D; require msz <= esz 1248 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \ 1249 @rpri_store_msz nreg=0 1250 1251 # SVE contiguous store (scalar plus scalar) 1252 # ST1B, ST1H, ST1W, ST1D; require msz <= esz 1253 # Enumerate msz lest we conflict with STR_zri. 1254 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \ 1255 @rprr_store_esz_n0 msz=0 1256 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \ 1257 @rprr_store_esz_n0 msz=1 1258 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \ 1259 @rprr_store_esz_n0 msz=2 1260 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \ 1261 @rprr_store msz=3 esz=3 nreg=0 1262 1263 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0) 1264 # SVE store multiple structures (scalar plus immediate) (nreg != 0) 1265 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \ 1266 @rpri_store_msz esz=%size_23 1267 1268 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0) 1269 # SVE store multiple structures (scalar plus scalar) (nreg != 0) 1270 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \ 1271 @rprr_store esz=%size_23 1272 1273 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets) 1274 # Require msz > 0 && msz <= esz. 1275 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \ 1276 @rprr_scatter_store xs=0 esz=2 scale=1 1277 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \ 1278 @rprr_scatter_store xs=1 esz=2 scale=1 1279 1280 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets) 1281 # Require msz <= esz. 1282 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \ 1283 @rprr_scatter_store xs=0 esz=2 scale=0 1284 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \ 1285 @rprr_scatter_store xs=1 esz=2 scale=0 1286 1287 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset) 1288 # Require msz > 0 1289 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \ 1290 @rprr_scatter_store xs=2 esz=3 scale=1 1291 1292 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset) 1293 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \ 1294 @rprr_scatter_store xs=2 esz=3 scale=0 1295 1296 # SVE 64-bit scatter store (vector plus immediate) 1297 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \ 1298 @rpri_scatter_store esz=3 1299 1300 # SVE 32-bit scatter store (vector plus immediate) 1301 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \ 1302 @rpri_scatter_store esz=2 1303 1304 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset) 1305 # Require msz > 0 1306 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \ 1307 @rprr_scatter_store xs=0 esz=3 scale=1 1308 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \ 1309 @rprr_scatter_store xs=1 esz=3 scale=1 1310 1311 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset) 1312 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \ 1313 @rprr_scatter_store xs=0 esz=3 scale=0 1314 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \ 1315 @rprr_scatter_store xs=1 esz=3 scale=0 1316 1317 #### SVE2 Support 1318 1319 ### SVE2 Integer Multiply - Unpredicated 1320 1321 # SVE2 integer multiply vectors (unpredicated) 1322 MUL_zzz 00000100 .. 1 ..... 0110 00 ..... ..... @rd_rn_rm 1323 SMULH_zzz 00000100 .. 1 ..... 0110 10 ..... ..... @rd_rn_rm 1324 UMULH_zzz 00000100 .. 1 ..... 0110 11 ..... ..... @rd_rn_rm 1325 PMUL_zzz 00000100 00 1 ..... 0110 01 ..... ..... @rd_rn_rm_e0 1326 1327 # SVE2 signed saturating doubling multiply high (unpredicated) 1328 SQDMULH_zzz 00000100 .. 1 ..... 0111 00 ..... ..... @rd_rn_rm 1329 SQRDMULH_zzz 00000100 .. 1 ..... 0111 01 ..... ..... @rd_rn_rm 1330 1331 ### SVE2 Integer - Predicated 1332 1333 SADALP_zpzz 01000100 .. 000 100 101 ... ..... ..... @rdm_pg_rn 1334 UADALP_zpzz 01000100 .. 000 101 101 ... ..... ..... @rdm_pg_rn 1335 1336 ### SVE2 integer unary operations (predicated) 1337 1338 URECPE 01000100 .. 000 000 101 ... ..... ..... @rd_pg_rn 1339 URSQRTE 01000100 .. 000 001 101 ... ..... ..... @rd_pg_rn 1340 SQABS 01000100 .. 001 000 101 ... ..... ..... @rd_pg_rn 1341 SQNEG 01000100 .. 001 001 101 ... ..... ..... @rd_pg_rn 1342 1343 ### SVE2 saturating/rounding bitwise shift left (predicated) 1344 1345 SRSHL 01000100 .. 000 010 100 ... ..... ..... @rdn_pg_rm 1346 URSHL 01000100 .. 000 011 100 ... ..... ..... @rdn_pg_rm 1347 SRSHL 01000100 .. 000 110 100 ... ..... ..... @rdm_pg_rn # SRSHLR 1348 URSHL 01000100 .. 000 111 100 ... ..... ..... @rdm_pg_rn # URSHLR 1349 1350 SQSHL 01000100 .. 001 000 100 ... ..... ..... @rdn_pg_rm 1351 UQSHL 01000100 .. 001 001 100 ... ..... ..... @rdn_pg_rm 1352 SQSHL 01000100 .. 001 100 100 ... ..... ..... @rdm_pg_rn # SQSHLR 1353 UQSHL 01000100 .. 001 101 100 ... ..... ..... @rdm_pg_rn # UQSHLR 1354 1355 SQRSHL 01000100 .. 001 010 100 ... ..... ..... @rdn_pg_rm 1356 UQRSHL 01000100 .. 001 011 100 ... ..... ..... @rdn_pg_rm 1357 SQRSHL 01000100 .. 001 110 100 ... ..... ..... @rdm_pg_rn # SQRSHLR 1358 UQRSHL 01000100 .. 001 111 100 ... ..... ..... @rdm_pg_rn # UQRSHLR 1359 1360 ### SVE2 integer halving add/subtract (predicated) 1361 1362 SHADD 01000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm 1363 UHADD 01000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm 1364 SHSUB 01000100 .. 010 010 100 ... ..... ..... @rdn_pg_rm 1365 UHSUB 01000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm 1366 SRHADD 01000100 .. 010 100 100 ... ..... ..... @rdn_pg_rm 1367 URHADD 01000100 .. 010 101 100 ... ..... ..... @rdn_pg_rm 1368 SHSUB 01000100 .. 010 110 100 ... ..... ..... @rdm_pg_rn # SHSUBR 1369 UHSUB 01000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # UHSUBR 1370 1371 ### SVE2 integer pairwise arithmetic 1372 1373 ADDP 01000100 .. 010 001 101 ... ..... ..... @rdn_pg_rm 1374 SMAXP 01000100 .. 010 100 101 ... ..... ..... @rdn_pg_rm 1375 UMAXP 01000100 .. 010 101 101 ... ..... ..... @rdn_pg_rm 1376 SMINP 01000100 .. 010 110 101 ... ..... ..... @rdn_pg_rm 1377 UMINP 01000100 .. 010 111 101 ... ..... ..... @rdn_pg_rm 1378 1379 ### SVE2 saturating add/subtract (predicated) 1380 1381 SQADD_zpzz 01000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm 1382 UQADD_zpzz 01000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm 1383 SQSUB_zpzz 01000100 .. 011 010 100 ... ..... ..... @rdn_pg_rm 1384 UQSUB_zpzz 01000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm 1385 SUQADD 01000100 .. 011 100 100 ... ..... ..... @rdn_pg_rm 1386 USQADD 01000100 .. 011 101 100 ... ..... ..... @rdn_pg_rm 1387 SQSUB_zpzz 01000100 .. 011 110 100 ... ..... ..... @rdm_pg_rn # SQSUBR 1388 UQSUB_zpzz 01000100 .. 011 111 100 ... ..... ..... @rdm_pg_rn # UQSUBR 1389 1390 #### SVE2 Widening Integer Arithmetic 1391 1392 ## SVE2 integer add/subtract long 1393 1394 SADDLB 01000101 .. 0 ..... 00 0000 ..... ..... @rd_rn_rm 1395 SADDLT 01000101 .. 0 ..... 00 0001 ..... ..... @rd_rn_rm 1396 UADDLB 01000101 .. 0 ..... 00 0010 ..... ..... @rd_rn_rm 1397 UADDLT 01000101 .. 0 ..... 00 0011 ..... ..... @rd_rn_rm 1398 1399 SSUBLB 01000101 .. 0 ..... 00 0100 ..... ..... @rd_rn_rm 1400 SSUBLT 01000101 .. 0 ..... 00 0101 ..... ..... @rd_rn_rm 1401 USUBLB 01000101 .. 0 ..... 00 0110 ..... ..... @rd_rn_rm 1402 USUBLT 01000101 .. 0 ..... 00 0111 ..... ..... @rd_rn_rm 1403 1404 SABDLB 01000101 .. 0 ..... 00 1100 ..... ..... @rd_rn_rm 1405 SABDLT 01000101 .. 0 ..... 00 1101 ..... ..... @rd_rn_rm 1406 UABDLB 01000101 .. 0 ..... 00 1110 ..... ..... @rd_rn_rm 1407 UABDLT 01000101 .. 0 ..... 00 1111 ..... ..... @rd_rn_rm 1408 1409 ## SVE2 integer add/subtract interleaved long 1410 1411 SADDLBT 01000101 .. 0 ..... 1000 00 ..... ..... @rd_rn_rm 1412 SSUBLBT 01000101 .. 0 ..... 1000 10 ..... ..... @rd_rn_rm 1413 SSUBLTB 01000101 .. 0 ..... 1000 11 ..... ..... @rd_rn_rm 1414 1415 ## SVE2 integer add/subtract wide 1416 1417 SADDWB 01000101 .. 0 ..... 010 000 ..... ..... @rd_rn_rm 1418 SADDWT 01000101 .. 0 ..... 010 001 ..... ..... @rd_rn_rm 1419 UADDWB 01000101 .. 0 ..... 010 010 ..... ..... @rd_rn_rm 1420 UADDWT 01000101 .. 0 ..... 010 011 ..... ..... @rd_rn_rm 1421 1422 SSUBWB 01000101 .. 0 ..... 010 100 ..... ..... @rd_rn_rm 1423 SSUBWT 01000101 .. 0 ..... 010 101 ..... ..... @rd_rn_rm 1424 USUBWB 01000101 .. 0 ..... 010 110 ..... ..... @rd_rn_rm 1425 USUBWT 01000101 .. 0 ..... 010 111 ..... ..... @rd_rn_rm 1426 1427 ## SVE2 integer multiply long 1428 1429 SQDMULLB_zzz 01000101 .. 0 ..... 011 000 ..... ..... @rd_rn_rm 1430 SQDMULLT_zzz 01000101 .. 0 ..... 011 001 ..... ..... @rd_rn_rm 1431 PMULLB 01000101 .. 0 ..... 011 010 ..... ..... @rd_rn_rm 1432 PMULLT 01000101 .. 0 ..... 011 011 ..... ..... @rd_rn_rm 1433 SMULLB_zzz 01000101 .. 0 ..... 011 100 ..... ..... @rd_rn_rm 1434 SMULLT_zzz 01000101 .. 0 ..... 011 101 ..... ..... @rd_rn_rm 1435 UMULLB_zzz 01000101 .. 0 ..... 011 110 ..... ..... @rd_rn_rm 1436 UMULLT_zzz 01000101 .. 0 ..... 011 111 ..... ..... @rd_rn_rm 1437 1438 ## SVE2 bitwise shift left long 1439 1440 # Note bit23 == 0 is handled by esz > 0 in do_sve2_shll_tb. 1441 SSHLLB 01000101 .. 0 ..... 1010 00 ..... ..... @rd_rn_tszimm_shl 1442 SSHLLT 01000101 .. 0 ..... 1010 01 ..... ..... @rd_rn_tszimm_shl 1443 USHLLB 01000101 .. 0 ..... 1010 10 ..... ..... @rd_rn_tszimm_shl 1444 USHLLT 01000101 .. 0 ..... 1010 11 ..... ..... @rd_rn_tszimm_shl 1445 1446 ## SVE2 bitwise exclusive-or interleaved 1447 1448 EORBT 01000101 .. 0 ..... 10010 0 ..... ..... @rd_rn_rm 1449 EORTB 01000101 .. 0 ..... 10010 1 ..... ..... @rd_rn_rm 1450 1451 ## SVE integer matrix multiply accumulate 1452 1453 SMMLA 01000101 00 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 1454 USMMLA 01000101 10 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 1455 UMMLA 01000101 11 0 ..... 10011 0 ..... ..... @rda_rn_rm_e0 1456 1457 ## SVE2 bitwise permute 1458 1459 BEXT 01000101 .. 0 ..... 1011 00 ..... ..... @rd_rn_rm 1460 BDEP 01000101 .. 0 ..... 1011 01 ..... ..... @rd_rn_rm 1461 BGRP 01000101 .. 0 ..... 1011 10 ..... ..... @rd_rn_rm 1462 1463 #### SVE2 Accumulate 1464 1465 ## SVE2 complex integer add 1466 1467 CADD_rot90 01000101 .. 00000 0 11011 0 ..... ..... @rdn_rm 1468 CADD_rot270 01000101 .. 00000 0 11011 1 ..... ..... @rdn_rm 1469 SQCADD_rot90 01000101 .. 00000 1 11011 0 ..... ..... @rdn_rm 1470 SQCADD_rot270 01000101 .. 00000 1 11011 1 ..... ..... @rdn_rm 1471 1472 ## SVE2 integer absolute difference and accumulate long 1473 1474 SABALB 01000101 .. 0 ..... 1100 00 ..... ..... @rda_rn_rm 1475 SABALT 01000101 .. 0 ..... 1100 01 ..... ..... @rda_rn_rm 1476 UABALB 01000101 .. 0 ..... 1100 10 ..... ..... @rda_rn_rm 1477 UABALT 01000101 .. 0 ..... 1100 11 ..... ..... @rda_rn_rm 1478 1479 ## SVE2 integer add/subtract long with carry 1480 1481 # ADC and SBC decoded via size in helper dispatch. 1482 ADCLB 01000101 .. 0 ..... 11010 0 ..... ..... @rda_rn_rm 1483 ADCLT 01000101 .. 0 ..... 11010 1 ..... ..... @rda_rn_rm 1484 1485 ## SVE2 bitwise shift right and accumulate 1486 1487 # TODO: Use @rda and %reg_movprfx here. 1488 SSRA 01000101 .. 0 ..... 1110 00 ..... ..... @rd_rn_tszimm_shr 1489 USRA 01000101 .. 0 ..... 1110 01 ..... ..... @rd_rn_tszimm_shr 1490 SRSRA 01000101 .. 0 ..... 1110 10 ..... ..... @rd_rn_tszimm_shr 1491 URSRA 01000101 .. 0 ..... 1110 11 ..... ..... @rd_rn_tszimm_shr 1492 1493 ## SVE2 bitwise shift and insert 1494 1495 SRI 01000101 .. 0 ..... 11110 0 ..... ..... @rd_rn_tszimm_shr 1496 SLI 01000101 .. 0 ..... 11110 1 ..... ..... @rd_rn_tszimm_shl 1497 1498 ## SVE2 integer absolute difference and accumulate 1499 1500 # TODO: Use @rda and %reg_movprfx here. 1501 SABA 01000101 .. 0 ..... 11111 0 ..... ..... @rd_rn_rm 1502 UABA 01000101 .. 0 ..... 11111 1 ..... ..... @rd_rn_rm 1503 1504 #### SVE2 Narrowing 1505 1506 ## SVE2 saturating extract narrow 1507 1508 # Bits 23, 18-16 are zero, limited in the translator via esz < 3 & imm == 0. 1509 SQXTNB 01000101 .. 1 ..... 010 000 ..... ..... @rd_rn_tszimm_shl 1510 SQXTNT 01000101 .. 1 ..... 010 001 ..... ..... @rd_rn_tszimm_shl 1511 UQXTNB 01000101 .. 1 ..... 010 010 ..... ..... @rd_rn_tszimm_shl 1512 UQXTNT 01000101 .. 1 ..... 010 011 ..... ..... @rd_rn_tszimm_shl 1513 SQXTUNB 01000101 .. 1 ..... 010 100 ..... ..... @rd_rn_tszimm_shl 1514 SQXTUNT 01000101 .. 1 ..... 010 101 ..... ..... @rd_rn_tszimm_shl 1515 1516 ## SVE2 bitwise shift right narrow 1517 1518 # Bit 23 == 0 is handled by esz > 0 in the translator. 1519 SQSHRUNB 01000101 .. 1 ..... 00 0000 ..... ..... @rd_rn_tszimm_shr 1520 SQSHRUNT 01000101 .. 1 ..... 00 0001 ..... ..... @rd_rn_tszimm_shr 1521 SQRSHRUNB 01000101 .. 1 ..... 00 0010 ..... ..... @rd_rn_tszimm_shr 1522 SQRSHRUNT 01000101 .. 1 ..... 00 0011 ..... ..... @rd_rn_tszimm_shr 1523 SHRNB 01000101 .. 1 ..... 00 0100 ..... ..... @rd_rn_tszimm_shr 1524 SHRNT 01000101 .. 1 ..... 00 0101 ..... ..... @rd_rn_tszimm_shr 1525 RSHRNB 01000101 .. 1 ..... 00 0110 ..... ..... @rd_rn_tszimm_shr 1526 RSHRNT 01000101 .. 1 ..... 00 0111 ..... ..... @rd_rn_tszimm_shr 1527 SQSHRNB 01000101 .. 1 ..... 00 1000 ..... ..... @rd_rn_tszimm_shr 1528 SQSHRNT 01000101 .. 1 ..... 00 1001 ..... ..... @rd_rn_tszimm_shr 1529 SQRSHRNB 01000101 .. 1 ..... 00 1010 ..... ..... @rd_rn_tszimm_shr 1530 SQRSHRNT 01000101 .. 1 ..... 00 1011 ..... ..... @rd_rn_tszimm_shr 1531 UQSHRNB 01000101 .. 1 ..... 00 1100 ..... ..... @rd_rn_tszimm_shr 1532 UQSHRNT 01000101 .. 1 ..... 00 1101 ..... ..... @rd_rn_tszimm_shr 1533 UQRSHRNB 01000101 .. 1 ..... 00 1110 ..... ..... @rd_rn_tszimm_shr 1534 UQRSHRNT 01000101 .. 1 ..... 00 1111 ..... ..... @rd_rn_tszimm_shr 1535 1536 ## SVE2 integer add/subtract narrow high part 1537 1538 ADDHNB 01000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm 1539 ADDHNT 01000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm 1540 RADDHNB 01000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm 1541 RADDHNT 01000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm 1542 SUBHNB 01000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm 1543 SUBHNT 01000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm 1544 RSUBHNB 01000101 .. 1 ..... 011 110 ..... ..... @rd_rn_rm 1545 RSUBHNT 01000101 .. 1 ..... 011 111 ..... ..... @rd_rn_rm 1546 1547 ### SVE2 Character Match 1548 1549 MATCH 01000101 .. 1 ..... 100 ... ..... 0 .... @pd_pg_rn_rm 1550 NMATCH 01000101 .. 1 ..... 100 ... ..... 1 .... @pd_pg_rn_rm 1551 1552 ### SVE2 Histogram Computation 1553 1554 HISTCNT 01000101 .. 1 ..... 110 ... ..... ..... @rd_pg_rn_rm 1555 HISTSEG 01000101 .. 1 ..... 101 000 ..... ..... @rd_rn_rm 1556 1557 ## SVE2 floating-point pairwise operations 1558 1559 FADDP 01100100 .. 010 00 0 100 ... ..... ..... @rdn_pg_rm 1560 FMAXNMP 01100100 .. 010 10 0 100 ... ..... ..... @rdn_pg_rm 1561 FMINNMP 01100100 .. 010 10 1 100 ... ..... ..... @rdn_pg_rm 1562 FMAXP 01100100 .. 010 11 0 100 ... ..... ..... @rdn_pg_rm 1563 FMINP 01100100 .. 010 11 1 100 ... ..... ..... @rdn_pg_rm 1564 1565 #### SVE Integer Multiply-Add (unpredicated) 1566 1567 ## SVE2 saturating multiply-add long 1568 1569 SQDMLALB_zzzw 01000100 .. 0 ..... 0110 00 ..... ..... @rda_rn_rm 1570 SQDMLALT_zzzw 01000100 .. 0 ..... 0110 01 ..... ..... @rda_rn_rm 1571 SQDMLSLB_zzzw 01000100 .. 0 ..... 0110 10 ..... ..... @rda_rn_rm 1572 SQDMLSLT_zzzw 01000100 .. 0 ..... 0110 11 ..... ..... @rda_rn_rm 1573 1574 ## SVE2 saturating multiply-add interleaved long 1575 1576 SQDMLALBT 01000100 .. 0 ..... 00001 0 ..... ..... @rda_rn_rm 1577 SQDMLSLBT 01000100 .. 0 ..... 00001 1 ..... ..... @rda_rn_rm 1578 1579 ## SVE2 saturating multiply-add high 1580 1581 SQRDMLAH_zzzz 01000100 .. 0 ..... 01110 0 ..... ..... @rda_rn_rm 1582 SQRDMLSH_zzzz 01000100 .. 0 ..... 01110 1 ..... ..... @rda_rn_rm 1583 1584 ## SVE2 integer multiply-add long 1585 1586 SMLALB_zzzw 01000100 .. 0 ..... 010 000 ..... ..... @rda_rn_rm 1587 SMLALT_zzzw 01000100 .. 0 ..... 010 001 ..... ..... @rda_rn_rm 1588 UMLALB_zzzw 01000100 .. 0 ..... 010 010 ..... ..... @rda_rn_rm 1589 UMLALT_zzzw 01000100 .. 0 ..... 010 011 ..... ..... @rda_rn_rm 1590 SMLSLB_zzzw 01000100 .. 0 ..... 010 100 ..... ..... @rda_rn_rm 1591 SMLSLT_zzzw 01000100 .. 0 ..... 010 101 ..... ..... @rda_rn_rm 1592 UMLSLB_zzzw 01000100 .. 0 ..... 010 110 ..... ..... @rda_rn_rm 1593 UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..... @rda_rn_rm 1594 1595 ## SVE2 complex integer multiply-add 1596 1597 CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=%reg_movprfx 1598 SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=%reg_movprfx 1599 1600 ## SVE mixed sign dot product 1601 1602 USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm 1603 1604 ### SVE2 floating point matrix multiply accumulate 1605 BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 1606 FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 1607 FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_e0 1608 1609 ### SVE2 Memory Gather Load Group 1610 1611 # SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets) 1612 LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \ 1613 &rprr_gather_load xs=2 esz=3 scale=0 ff=0 1614 1615 # SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets) 1616 LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \ 1617 &rprr_gather_load xs=0 esz=2 scale=0 ff=0 1618 1619 ### SVE2 Memory Store Group 1620 1621 # SVE2 64-bit scatter non-temporal store (vector plus scalar) 1622 STNT1_zprz 1110010 .. 00 ..... 001 ... ..... ..... \ 1623 @rprr_scatter_store xs=2 esz=3 scale=0 1624 1625 # SVE2 32-bit scatter non-temporal store (vector plus scalar) 1626 STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \ 1627 @rprr_scatter_store xs=0 esz=2 scale=0 1628 1629 ### SVE2 Crypto Extensions 1630 1631 # SVE2 crypto unary operations 1632 # AESMC and AESIMC 1633 AESMC 01000101 00 10000011100 decrypt:1 00000 rd:5 1634 1635 # SVE2 crypto destructive binary operations 1636 AESE 01000101 00 10001 0 11100 0 ..... ..... @rdn_rm_e0 1637 AESD 01000101 00 10001 0 11100 1 ..... ..... @rdn_rm_e0 1638 SM4E 01000101 00 10001 1 11100 0 ..... ..... @rdn_rm_e0 1639 1640 # SVE2 crypto constructive binary operations 1641 SM4EKEY 01000101 00 1 ..... 11110 0 ..... ..... @rd_rn_rm_e0 1642 RAX1 01000101 00 1 ..... 11110 1 ..... ..... @rd_rn_rm_e0 1643 1644 ### SVE2 floating-point convert precision odd elements 1645 FCVTXNT_ds 01100100 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1646 FCVTX_ds 01100101 00 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1647 FCVTNT_sh 01100100 10 0010 00 101 ... ..... ..... @rd_pg_rn_e0 1648 BFCVTNT 01100100 10 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1649 FCVTLT_hs 01100100 10 0010 01 101 ... ..... ..... @rd_pg_rn_e0 1650 FCVTNT_ds 01100100 11 0010 10 101 ... ..... ..... @rd_pg_rn_e0 1651 FCVTLT_sd 01100100 11 0010 11 101 ... ..... ..... @rd_pg_rn_e0 1652 1653 ### SVE2 floating-point convert to integer 1654 FLOGB 01100101 00 011 esz:2 0101 pg:3 rn:5 rd:5 &rpr_esz 1655 1656 ### SVE2 floating-point multiply-add long (vectors) 1657 FMLALB_zzzw 01100100 10 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 1658 FMLALT_zzzw 01100100 10 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_e0 1659 FMLSLB_zzzw 01100100 10 1 ..... 10 1 00 0 ..... ..... @rda_rn_rm_e0 1660 FMLSLT_zzzw 01100100 10 1 ..... 10 1 00 1 ..... ..... @rda_rn_rm_e0 1661 1662 BFMLALB_zzzw 01100100 11 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 1663 BFMLALT_zzzw 01100100 11 1 ..... 10 0 00 1 ..... ..... @rda_rn_rm_e0 1664 1665 ### SVE2 floating-point bfloat16 dot-product 1666 BFDOT_zzzz 01100100 01 1 ..... 10 0 00 0 ..... ..... @rda_rn_rm_e0 1667 1668 ### SVE2 floating-point multiply-add long (indexed) 1669 FMLALB_zzxw 01100100 10 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1670 FMLALT_zzxw 01100100 10 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1671 FMLSLB_zzxw 01100100 10 1 ..... 0110.0 ..... ..... @rrxr_3a esz=2 1672 FMLSLT_zzxw 01100100 10 1 ..... 0110.1 ..... ..... @rrxr_3a esz=2 1673 BFMLALB_zzxw 01100100 11 1 ..... 0100.0 ..... ..... @rrxr_3a esz=2 1674 BFMLALT_zzxw 01100100 11 1 ..... 0100.1 ..... ..... @rrxr_3a esz=2 1675 1676 ### SVE2 floating-point bfloat16 dot-product (indexed) 1677 BFDOT_zzxz 01100100 01 1 ..... 010000 ..... ..... @rrxr_2 esz=2 1678 1679 ### SVE broadcast predicate element 1680 1681 &psel esz pd pn pm rv imm 1682 %psel_rv 16:2 !function=plus_12 1683 %psel_imm_b 22:2 19:2 1684 %psel_imm_h 22:2 20:1 1685 %psel_imm_s 22:2 1686 %psel_imm_d 23:1 1687 @psel ........ .. . ... .. .. pn:4 . pm:4 . pd:4 \ 1688 &psel rv=%psel_rv 1689 1690 PSEL 00100101 .. 1 ..1 .. 01 .... 0 .... 0 .... \ 1691 @psel esz=0 imm=%psel_imm_b 1692 PSEL 00100101 .. 1 .10 .. 01 .... 0 .... 0 .... \ 1693 @psel esz=1 imm=%psel_imm_h 1694 PSEL 00100101 .. 1 100 .. 01 .... 0 .... 0 .... \ 1695 @psel esz=2 imm=%psel_imm_s 1696 PSEL 00100101 .1 1 000 .. 01 .... 0 .... 0 .... \ 1697 @psel esz=3 imm=%psel_imm_d 1698 1699 ### SVE clamp 1700 1701 SCLAMP 01000100 .. 0 ..... 110000 ..... ..... @rda_rn_rm 1702 UCLAMP 01000100 .. 0 ..... 110001 ..... ..... @rda_rn_rm