sme-fa64.decode (2900B)
1 # AArch64 SME allowed instruction decoding 2 # 3 # Copyright (c) 2022 Linaro, Ltd 4 # 5 # This library is free software; you can redistribute it and/or 6 # modify it under the terms of the GNU Lesser General Public 7 # License as published by the Free Software Foundation; either 8 # version 2.1 of the License, or (at your option) any later version. 9 # 10 # This library is distributed in the hope that it will be useful, 11 # but WITHOUT ANY WARRANTY; without even the implied warranty of 12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 # Lesser General Public License for more details. 14 # 15 # You should have received a copy of the GNU Lesser General Public 16 # License along with this library; if not, see <http://www.gnu.org/licenses/>. 17 18 # 19 # This file is processed by scripts/decodetree.py 20 # 21 22 # These patterns are taken from Appendix E1.1 of DDI0616 A.a, 23 # Arm Architecture Reference Manual Supplement, 24 # The Scalable Matrix Extension (SME), for Armv9-A 25 26 { 27 [ 28 OK 0-00 1110 0000 0001 0010 11-- ---- ---- # SMOV W|Xd,Vn.B[0] 29 OK 0-00 1110 0000 0010 0010 11-- ---- ---- # SMOV W|Xd,Vn.H[0] 30 OK 0100 1110 0000 0100 0010 11-- ---- ---- # SMOV Xd,Vn.S[0] 31 OK 0000 1110 0000 0001 0011 11-- ---- ---- # UMOV Wd,Vn.B[0] 32 OK 0000 1110 0000 0010 0011 11-- ---- ---- # UMOV Wd,Vn.H[0] 33 OK 0000 1110 0000 0100 0011 11-- ---- ---- # UMOV Wd,Vn.S[0] 34 OK 0100 1110 0000 1000 0011 11-- ---- ---- # UMOV Xd,Vn.D[0] 35 ] 36 FAIL 0--0 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD vector operations 37 } 38 39 { 40 [ 41 OK 0101 1110 --1- ---- 11-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar) 42 OK 0101 1110 -10- ---- 00-1 11-- ---- ---- # FMULX/FRECPS/FRSQRTS (scalar, FP16) 43 OK 01-1 1110 1-10 0001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar) 44 OK 01-1 1110 1111 1001 11-1 10-- ---- ---- # FRECPE/FRSQRTE/FRECPX (scalar, FP16) 45 ] 46 FAIL 01-1 111- ---- ---- ---- ---- ---- ---- # Advanced SIMD single-element operations 47 } 48 49 FAIL 0-00 110- ---- ---- ---- ---- ---- ---- # Advanced SIMD structure load/store 50 FAIL 1100 1110 ---- ---- ---- ---- ---- ---- # Advanced SIMD cryptography extensions 51 FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS 52 53 # These are the "avoidance of doubt" final table of Illegal Advanced SIMD instructions 54 # We don't actually need to include these, as the default is OK. 55 # -001 111- ---- ---- ---- ---- ---- ---- # Scalar floating-point operations 56 # --10 110- ---- ---- ---- ---- ---- ---- # Load/store pair of FP registers 57 # --01 1100 ---- ---- ---- ---- ---- ---- # Load FP register (PC-relative literal) 58 # --11 1100 --0- ---- ---- ---- ---- ---- # Load/store FP register (unscaled imm) 59 # --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset) 60 # --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)