machine.c (29601B)
1 #include "qemu/osdep.h" 2 #include "cpu.h" 3 #include "qemu/error-report.h" 4 #include "sysemu/kvm.h" 5 #include "kvm_arm.h" 6 #include "internals.h" 7 #include "migration/cpu.h" 8 9 static bool vfp_needed(void *opaque) 10 { 11 ARMCPU *cpu = opaque; 12 13 return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) 14 ? cpu_isar_feature(aa64_fp_simd, cpu) 15 : cpu_isar_feature(aa32_vfp_simd, cpu)); 16 } 17 18 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, 19 const VMStateField *field) 20 { 21 ARMCPU *cpu = opaque; 22 CPUARMState *env = &cpu->env; 23 uint32_t val = qemu_get_be32(f); 24 25 vfp_set_fpscr(env, val); 26 return 0; 27 } 28 29 static int put_fpscr(QEMUFile *f, void *opaque, size_t size, 30 const VMStateField *field, JSONWriter *vmdesc) 31 { 32 ARMCPU *cpu = opaque; 33 CPUARMState *env = &cpu->env; 34 35 qemu_put_be32(f, vfp_get_fpscr(env)); 36 return 0; 37 } 38 39 static const VMStateInfo vmstate_fpscr = { 40 .name = "fpscr", 41 .get = get_fpscr, 42 .put = put_fpscr, 43 }; 44 45 static const VMStateDescription vmstate_vfp = { 46 .name = "cpu/vfp", 47 .version_id = 3, 48 .minimum_version_id = 3, 49 .needed = vfp_needed, 50 .fields = (VMStateField[]) { 51 /* For compatibility, store Qn out of Zn here. */ 52 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[0].d, ARMCPU, 0, 2), 53 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[1].d, ARMCPU, 0, 2), 54 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[2].d, ARMCPU, 0, 2), 55 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[3].d, ARMCPU, 0, 2), 56 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[4].d, ARMCPU, 0, 2), 57 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[5].d, ARMCPU, 0, 2), 58 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[6].d, ARMCPU, 0, 2), 59 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[7].d, ARMCPU, 0, 2), 60 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[8].d, ARMCPU, 0, 2), 61 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[9].d, ARMCPU, 0, 2), 62 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[10].d, ARMCPU, 0, 2), 63 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[11].d, ARMCPU, 0, 2), 64 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[12].d, ARMCPU, 0, 2), 65 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[13].d, ARMCPU, 0, 2), 66 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[14].d, ARMCPU, 0, 2), 67 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[15].d, ARMCPU, 0, 2), 68 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[16].d, ARMCPU, 0, 2), 69 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[17].d, ARMCPU, 0, 2), 70 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[18].d, ARMCPU, 0, 2), 71 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[19].d, ARMCPU, 0, 2), 72 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[20].d, ARMCPU, 0, 2), 73 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[21].d, ARMCPU, 0, 2), 74 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[22].d, ARMCPU, 0, 2), 75 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[23].d, ARMCPU, 0, 2), 76 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[24].d, ARMCPU, 0, 2), 77 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[25].d, ARMCPU, 0, 2), 78 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[26].d, ARMCPU, 0, 2), 79 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[27].d, ARMCPU, 0, 2), 80 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[28].d, ARMCPU, 0, 2), 81 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[29].d, ARMCPU, 0, 2), 82 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[30].d, ARMCPU, 0, 2), 83 VMSTATE_UINT64_SUB_ARRAY(env.vfp.zregs[31].d, ARMCPU, 0, 2), 84 85 /* The xregs array is a little awkward because element 1 (FPSCR) 86 * requires a specific accessor, so we have to split it up in 87 * the vmstate: 88 */ 89 VMSTATE_UINT32(env.vfp.xregs[0], ARMCPU), 90 VMSTATE_UINT32_SUB_ARRAY(env.vfp.xregs, ARMCPU, 2, 14), 91 { 92 .name = "fpscr", 93 .version_id = 0, 94 .size = sizeof(uint32_t), 95 .info = &vmstate_fpscr, 96 .flags = VMS_SINGLE, 97 .offset = 0, 98 }, 99 VMSTATE_END_OF_LIST() 100 } 101 }; 102 103 static bool iwmmxt_needed(void *opaque) 104 { 105 ARMCPU *cpu = opaque; 106 CPUARMState *env = &cpu->env; 107 108 return arm_feature(env, ARM_FEATURE_IWMMXT); 109 } 110 111 static const VMStateDescription vmstate_iwmmxt = { 112 .name = "cpu/iwmmxt", 113 .version_id = 1, 114 .minimum_version_id = 1, 115 .needed = iwmmxt_needed, 116 .fields = (VMStateField[]) { 117 VMSTATE_UINT64_ARRAY(env.iwmmxt.regs, ARMCPU, 16), 118 VMSTATE_UINT32_ARRAY(env.iwmmxt.cregs, ARMCPU, 16), 119 VMSTATE_END_OF_LIST() 120 } 121 }; 122 123 #ifdef TARGET_AARCH64 124 /* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, 125 * and ARMPredicateReg is actively empty. This triggers errors 126 * in the expansion of the VMSTATE macros. 127 */ 128 129 static bool sve_needed(void *opaque) 130 { 131 ARMCPU *cpu = opaque; 132 133 return cpu_isar_feature(aa64_sve, cpu); 134 } 135 136 /* The first two words of each Zreg is stored in VFP state. */ 137 static const VMStateDescription vmstate_zreg_hi_reg = { 138 .name = "cpu/sve/zreg_hi", 139 .version_id = 1, 140 .minimum_version_id = 1, 141 .fields = (VMStateField[]) { 142 VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), 143 VMSTATE_END_OF_LIST() 144 } 145 }; 146 147 static const VMStateDescription vmstate_preg_reg = { 148 .name = "cpu/sve/preg", 149 .version_id = 1, 150 .minimum_version_id = 1, 151 .fields = (VMStateField[]) { 152 VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), 153 VMSTATE_END_OF_LIST() 154 } 155 }; 156 157 static const VMStateDescription vmstate_sve = { 158 .name = "cpu/sve", 159 .version_id = 1, 160 .minimum_version_id = 1, 161 .needed = sve_needed, 162 .fields = (VMStateField[]) { 163 VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, 164 vmstate_zreg_hi_reg, ARMVectorReg), 165 VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, 166 vmstate_preg_reg, ARMPredicateReg), 167 VMSTATE_END_OF_LIST() 168 } 169 }; 170 171 static const VMStateDescription vmstate_vreg = { 172 .name = "vreg", 173 .version_id = 1, 174 .minimum_version_id = 1, 175 .fields = (VMStateField[]) { 176 VMSTATE_UINT64_ARRAY(d, ARMVectorReg, ARM_MAX_VQ * 2), 177 VMSTATE_END_OF_LIST() 178 } 179 }; 180 181 static bool za_needed(void *opaque) 182 { 183 ARMCPU *cpu = opaque; 184 185 /* 186 * When ZA storage is disabled, its contents are discarded. 187 * It will be zeroed when ZA storage is re-enabled. 188 */ 189 return FIELD_EX64(cpu->env.svcr, SVCR, ZA); 190 } 191 192 static const VMStateDescription vmstate_za = { 193 .name = "cpu/sme", 194 .version_id = 1, 195 .minimum_version_id = 1, 196 .needed = za_needed, 197 .fields = (VMStateField[]) { 198 VMSTATE_STRUCT_ARRAY(env.zarray, ARMCPU, ARM_MAX_VQ * 16, 0, 199 vmstate_vreg, ARMVectorReg), 200 VMSTATE_END_OF_LIST() 201 } 202 }; 203 #endif /* AARCH64 */ 204 205 static bool serror_needed(void *opaque) 206 { 207 ARMCPU *cpu = opaque; 208 CPUARMState *env = &cpu->env; 209 210 return env->serror.pending != 0; 211 } 212 213 static const VMStateDescription vmstate_serror = { 214 .name = "cpu/serror", 215 .version_id = 1, 216 .minimum_version_id = 1, 217 .needed = serror_needed, 218 .fields = (VMStateField[]) { 219 VMSTATE_UINT8(env.serror.pending, ARMCPU), 220 VMSTATE_UINT8(env.serror.has_esr, ARMCPU), 221 VMSTATE_UINT64(env.serror.esr, ARMCPU), 222 VMSTATE_END_OF_LIST() 223 } 224 }; 225 226 static bool irq_line_state_needed(void *opaque) 227 { 228 return true; 229 } 230 231 static const VMStateDescription vmstate_irq_line_state = { 232 .name = "cpu/irq-line-state", 233 .version_id = 1, 234 .minimum_version_id = 1, 235 .needed = irq_line_state_needed, 236 .fields = (VMStateField[]) { 237 VMSTATE_UINT32(env.irq_line_state, ARMCPU), 238 VMSTATE_END_OF_LIST() 239 } 240 }; 241 242 static bool m_needed(void *opaque) 243 { 244 ARMCPU *cpu = opaque; 245 CPUARMState *env = &cpu->env; 246 247 return arm_feature(env, ARM_FEATURE_M); 248 } 249 250 static const VMStateDescription vmstate_m_faultmask_primask = { 251 .name = "cpu/m/faultmask-primask", 252 .version_id = 1, 253 .minimum_version_id = 1, 254 .needed = m_needed, 255 .fields = (VMStateField[]) { 256 VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), 257 VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), 258 VMSTATE_END_OF_LIST() 259 } 260 }; 261 262 /* CSSELR is in a subsection because we didn't implement it previously. 263 * Migration from an old implementation will leave it at zero, which 264 * is OK since the only CPUs in the old implementation make the 265 * register RAZ/WI. 266 * Since there was no version of QEMU which implemented the CSSELR for 267 * just non-secure, we transfer both banks here rather than putting 268 * the secure banked version in the m-security subsection. 269 */ 270 static bool csselr_vmstate_validate(void *opaque, int version_id) 271 { 272 ARMCPU *cpu = opaque; 273 274 return cpu->env.v7m.csselr[M_REG_NS] <= R_V7M_CSSELR_INDEX_MASK 275 && cpu->env.v7m.csselr[M_REG_S] <= R_V7M_CSSELR_INDEX_MASK; 276 } 277 278 static bool m_csselr_needed(void *opaque) 279 { 280 ARMCPU *cpu = opaque; 281 282 return !arm_v7m_csselr_razwi(cpu); 283 } 284 285 static const VMStateDescription vmstate_m_csselr = { 286 .name = "cpu/m/csselr", 287 .version_id = 1, 288 .minimum_version_id = 1, 289 .needed = m_csselr_needed, 290 .fields = (VMStateField[]) { 291 VMSTATE_UINT32_ARRAY(env.v7m.csselr, ARMCPU, M_REG_NUM_BANKS), 292 VMSTATE_VALIDATE("CSSELR is valid", csselr_vmstate_validate), 293 VMSTATE_END_OF_LIST() 294 } 295 }; 296 297 static const VMStateDescription vmstate_m_scr = { 298 .name = "cpu/m/scr", 299 .version_id = 1, 300 .minimum_version_id = 1, 301 .needed = m_needed, 302 .fields = (VMStateField[]) { 303 VMSTATE_UINT32(env.v7m.scr[M_REG_NS], ARMCPU), 304 VMSTATE_END_OF_LIST() 305 } 306 }; 307 308 static const VMStateDescription vmstate_m_other_sp = { 309 .name = "cpu/m/other-sp", 310 .version_id = 1, 311 .minimum_version_id = 1, 312 .needed = m_needed, 313 .fields = (VMStateField[]) { 314 VMSTATE_UINT32(env.v7m.other_sp, ARMCPU), 315 VMSTATE_END_OF_LIST() 316 } 317 }; 318 319 static bool m_v8m_needed(void *opaque) 320 { 321 ARMCPU *cpu = opaque; 322 CPUARMState *env = &cpu->env; 323 324 return arm_feature(env, ARM_FEATURE_M) && arm_feature(env, ARM_FEATURE_V8); 325 } 326 327 static const VMStateDescription vmstate_m_v8m = { 328 .name = "cpu/m/v8m", 329 .version_id = 1, 330 .minimum_version_id = 1, 331 .needed = m_v8m_needed, 332 .fields = (VMStateField[]) { 333 VMSTATE_UINT32_ARRAY(env.v7m.msplim, ARMCPU, M_REG_NUM_BANKS), 334 VMSTATE_UINT32_ARRAY(env.v7m.psplim, ARMCPU, M_REG_NUM_BANKS), 335 VMSTATE_END_OF_LIST() 336 } 337 }; 338 339 static const VMStateDescription vmstate_m_fp = { 340 .name = "cpu/m/fp", 341 .version_id = 1, 342 .minimum_version_id = 1, 343 .needed = vfp_needed, 344 .fields = (VMStateField[]) { 345 VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), 346 VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), 347 VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), 348 VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), 349 VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), 350 VMSTATE_END_OF_LIST() 351 } 352 }; 353 354 static bool mve_needed(void *opaque) 355 { 356 ARMCPU *cpu = opaque; 357 358 return cpu_isar_feature(aa32_mve, cpu); 359 } 360 361 static const VMStateDescription vmstate_m_mve = { 362 .name = "cpu/m/mve", 363 .version_id = 1, 364 .minimum_version_id = 1, 365 .needed = mve_needed, 366 .fields = (VMStateField[]) { 367 VMSTATE_UINT32(env.v7m.vpr, ARMCPU), 368 VMSTATE_UINT32(env.v7m.ltpsize, ARMCPU), 369 VMSTATE_END_OF_LIST() 370 }, 371 }; 372 373 static const VMStateDescription vmstate_m = { 374 .name = "cpu/m", 375 .version_id = 4, 376 .minimum_version_id = 4, 377 .needed = m_needed, 378 .fields = (VMStateField[]) { 379 VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), 380 VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), 381 VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), 382 VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), 383 VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), 384 VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), 385 VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), 386 VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), 387 VMSTATE_UINT32(env.v7m.bfar, ARMCPU), 388 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), 389 VMSTATE_INT32(env.v7m.exception, ARMCPU), 390 VMSTATE_END_OF_LIST() 391 }, 392 .subsections = (const VMStateDescription*[]) { 393 &vmstate_m_faultmask_primask, 394 &vmstate_m_csselr, 395 &vmstate_m_scr, 396 &vmstate_m_other_sp, 397 &vmstate_m_v8m, 398 &vmstate_m_fp, 399 &vmstate_m_mve, 400 NULL 401 } 402 }; 403 404 static bool thumb2ee_needed(void *opaque) 405 { 406 ARMCPU *cpu = opaque; 407 CPUARMState *env = &cpu->env; 408 409 return arm_feature(env, ARM_FEATURE_THUMB2EE); 410 } 411 412 static const VMStateDescription vmstate_thumb2ee = { 413 .name = "cpu/thumb2ee", 414 .version_id = 1, 415 .minimum_version_id = 1, 416 .needed = thumb2ee_needed, 417 .fields = (VMStateField[]) { 418 VMSTATE_UINT32(env.teecr, ARMCPU), 419 VMSTATE_UINT32(env.teehbr, ARMCPU), 420 VMSTATE_END_OF_LIST() 421 } 422 }; 423 424 static bool pmsav7_needed(void *opaque) 425 { 426 ARMCPU *cpu = opaque; 427 CPUARMState *env = &cpu->env; 428 429 return arm_feature(env, ARM_FEATURE_PMSA) && 430 arm_feature(env, ARM_FEATURE_V7) && 431 !arm_feature(env, ARM_FEATURE_V8); 432 } 433 434 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 435 { 436 ARMCPU *cpu = opaque; 437 438 return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; 439 } 440 441 static const VMStateDescription vmstate_pmsav7 = { 442 .name = "cpu/pmsav7", 443 .version_id = 1, 444 .minimum_version_id = 1, 445 .needed = pmsav7_needed, 446 .fields = (VMStateField[]) { 447 VMSTATE_VARRAY_UINT32(env.pmsav7.drbar, ARMCPU, pmsav7_dregion, 0, 448 vmstate_info_uint32, uint32_t), 449 VMSTATE_VARRAY_UINT32(env.pmsav7.drsr, ARMCPU, pmsav7_dregion, 0, 450 vmstate_info_uint32, uint32_t), 451 VMSTATE_VARRAY_UINT32(env.pmsav7.dracr, ARMCPU, pmsav7_dregion, 0, 452 vmstate_info_uint32, uint32_t), 453 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate), 454 VMSTATE_END_OF_LIST() 455 } 456 }; 457 458 static bool pmsav7_rnr_needed(void *opaque) 459 { 460 ARMCPU *cpu = opaque; 461 CPUARMState *env = &cpu->env; 462 463 /* For R profile cores pmsav7.rnr is migrated via the cpreg 464 * "RGNR" definition in helper.h. For M profile we have to 465 * migrate it separately. 466 */ 467 return arm_feature(env, ARM_FEATURE_M); 468 } 469 470 static const VMStateDescription vmstate_pmsav7_rnr = { 471 .name = "cpu/pmsav7-rnr", 472 .version_id = 1, 473 .minimum_version_id = 1, 474 .needed = pmsav7_rnr_needed, 475 .fields = (VMStateField[]) { 476 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), 477 VMSTATE_END_OF_LIST() 478 } 479 }; 480 481 static bool pmsav8_needed(void *opaque) 482 { 483 ARMCPU *cpu = opaque; 484 CPUARMState *env = &cpu->env; 485 486 return arm_feature(env, ARM_FEATURE_PMSA) && 487 arm_feature(env, ARM_FEATURE_V8); 488 } 489 490 static const VMStateDescription vmstate_pmsav8 = { 491 .name = "cpu/pmsav8", 492 .version_id = 1, 493 .minimum_version_id = 1, 494 .needed = pmsav8_needed, 495 .fields = (VMStateField[]) { 496 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dregion, 497 0, vmstate_info_uint32, uint32_t), 498 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dregion, 499 0, vmstate_info_uint32, uint32_t), 500 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), 501 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), 502 VMSTATE_END_OF_LIST() 503 } 504 }; 505 506 static bool s_rnr_vmstate_validate(void *opaque, int version_id) 507 { 508 ARMCPU *cpu = opaque; 509 510 return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; 511 } 512 513 static bool sau_rnr_vmstate_validate(void *opaque, int version_id) 514 { 515 ARMCPU *cpu = opaque; 516 517 return cpu->env.sau.rnr < cpu->sau_sregion; 518 } 519 520 static bool m_security_needed(void *opaque) 521 { 522 ARMCPU *cpu = opaque; 523 CPUARMState *env = &cpu->env; 524 525 return arm_feature(env, ARM_FEATURE_M_SECURITY); 526 } 527 528 static const VMStateDescription vmstate_m_security = { 529 .name = "cpu/m-security", 530 .version_id = 1, 531 .minimum_version_id = 1, 532 .needed = m_security_needed, 533 .fields = (VMStateField[]) { 534 VMSTATE_UINT32(env.v7m.secure, ARMCPU), 535 VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), 536 VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), 537 VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), 538 VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), 539 VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), 540 VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), 541 VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), 542 VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), 543 VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), 544 VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dregion, 545 0, vmstate_info_uint32, uint32_t), 546 VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion, 547 0, vmstate_info_uint32, uint32_t), 548 VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), 549 VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate), 550 VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), 551 VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), 552 VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), 553 VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), 554 VMSTATE_UINT32(env.v7m.sfsr, ARMCPU), 555 VMSTATE_UINT32(env.v7m.sfar, ARMCPU), 556 VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0, 557 vmstate_info_uint32, uint32_t), 558 VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0, 559 vmstate_info_uint32, uint32_t), 560 VMSTATE_UINT32(env.sau.rnr, ARMCPU), 561 VMSTATE_VALIDATE("SAU_RNR is valid", sau_rnr_vmstate_validate), 562 VMSTATE_UINT32(env.sau.ctrl, ARMCPU), 563 VMSTATE_UINT32(env.v7m.scr[M_REG_S], ARMCPU), 564 /* AIRCR is not secure-only, but our implementation is R/O if the 565 * security extension is unimplemented, so we migrate it here. 566 */ 567 VMSTATE_UINT32(env.v7m.aircr, ARMCPU), 568 VMSTATE_END_OF_LIST() 569 } 570 }; 571 572 static int get_cpsr(QEMUFile *f, void *opaque, size_t size, 573 const VMStateField *field) 574 { 575 ARMCPU *cpu = opaque; 576 CPUARMState *env = &cpu->env; 577 uint32_t val = qemu_get_be32(f); 578 579 if (arm_feature(env, ARM_FEATURE_M)) { 580 if (val & XPSR_EXCP) { 581 /* This is a CPSR format value from an older QEMU. (We can tell 582 * because values transferred in XPSR format always have zero 583 * for the EXCP field, and CPSR format will always have bit 4 584 * set in CPSR_M.) Rearrange it into XPSR format. The significant 585 * differences are that the T bit is not in the same place, the 586 * primask/faultmask info may be in the CPSR I and F bits, and 587 * we do not want the mode bits. 588 * We know that this cleanup happened before v8M, so there 589 * is no complication with banked primask/faultmask. 590 */ 591 uint32_t newval = val; 592 593 assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); 594 595 newval &= (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); 596 if (val & CPSR_T) { 597 newval |= XPSR_T; 598 } 599 /* If the I or F bits are set then this is a migration from 600 * an old QEMU which still stored the M profile FAULTMASK 601 * and PRIMASK in env->daif. For a new QEMU, the data is 602 * transferred using the vmstate_m_faultmask_primask subsection. 603 */ 604 if (val & CPSR_F) { 605 env->v7m.faultmask[M_REG_NS] = 1; 606 } 607 if (val & CPSR_I) { 608 env->v7m.primask[M_REG_NS] = 1; 609 } 610 val = newval; 611 } 612 /* Ignore the low bits, they are handled by vmstate_m. */ 613 xpsr_write(env, val, ~XPSR_EXCP); 614 return 0; 615 } 616 617 env->aarch64 = ((val & PSTATE_nRW) == 0); 618 619 if (is_a64(env)) { 620 pstate_write(env, val); 621 return 0; 622 } 623 624 cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); 625 return 0; 626 } 627 628 static int put_cpsr(QEMUFile *f, void *opaque, size_t size, 629 const VMStateField *field, JSONWriter *vmdesc) 630 { 631 ARMCPU *cpu = opaque; 632 CPUARMState *env = &cpu->env; 633 uint32_t val; 634 635 if (arm_feature(env, ARM_FEATURE_M)) { 636 /* The low 9 bits are v7m.exception, which is handled by vmstate_m. */ 637 val = xpsr_read(env) & ~XPSR_EXCP; 638 } else if (is_a64(env)) { 639 val = pstate_read(env); 640 } else { 641 val = cpsr_read(env); 642 } 643 644 qemu_put_be32(f, val); 645 return 0; 646 } 647 648 static const VMStateInfo vmstate_cpsr = { 649 .name = "cpsr", 650 .get = get_cpsr, 651 .put = put_cpsr, 652 }; 653 654 static int get_power(QEMUFile *f, void *opaque, size_t size, 655 const VMStateField *field) 656 { 657 ARMCPU *cpu = opaque; 658 bool powered_off = qemu_get_byte(f); 659 cpu->power_state = powered_off ? PSCI_OFF : PSCI_ON; 660 return 0; 661 } 662 663 static int put_power(QEMUFile *f, void *opaque, size_t size, 664 const VMStateField *field, JSONWriter *vmdesc) 665 { 666 ARMCPU *cpu = opaque; 667 668 /* Migration should never happen while we transition power states */ 669 670 if (cpu->power_state == PSCI_ON || 671 cpu->power_state == PSCI_OFF) { 672 bool powered_off = (cpu->power_state == PSCI_OFF) ? true : false; 673 qemu_put_byte(f, powered_off); 674 return 0; 675 } else { 676 return 1; 677 } 678 } 679 680 static const VMStateInfo vmstate_powered_off = { 681 .name = "powered_off", 682 .get = get_power, 683 .put = put_power, 684 }; 685 686 static int cpu_pre_save(void *opaque) 687 { 688 ARMCPU *cpu = opaque; 689 690 if (!kvm_enabled()) { 691 pmu_op_start(&cpu->env); 692 } 693 694 if (kvm_enabled()) { 695 if (!write_kvmstate_to_list(cpu)) { 696 /* This should never fail */ 697 g_assert_not_reached(); 698 } 699 700 /* 701 * kvm_arm_cpu_pre_save() must be called after 702 * write_kvmstate_to_list() 703 */ 704 kvm_arm_cpu_pre_save(cpu); 705 } else { 706 if (!write_cpustate_to_list(cpu, false)) { 707 /* This should never fail. */ 708 g_assert_not_reached(); 709 } 710 } 711 712 cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len; 713 memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, 714 cpu->cpreg_array_len * sizeof(uint64_t)); 715 memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, 716 cpu->cpreg_array_len * sizeof(uint64_t)); 717 718 return 0; 719 } 720 721 static int cpu_post_save(void *opaque) 722 { 723 ARMCPU *cpu = opaque; 724 725 if (!kvm_enabled()) { 726 pmu_op_finish(&cpu->env); 727 } 728 729 return 0; 730 } 731 732 static int cpu_pre_load(void *opaque) 733 { 734 ARMCPU *cpu = opaque; 735 CPUARMState *env = &cpu->env; 736 737 /* 738 * Pre-initialize irq_line_state to a value that's never valid as 739 * real data, so cpu_post_load() can tell whether we've seen the 740 * irq-line-state subsection in the incoming migration state. 741 */ 742 env->irq_line_state = UINT32_MAX; 743 744 if (!kvm_enabled()) { 745 pmu_op_start(&cpu->env); 746 } 747 748 return 0; 749 } 750 751 static int cpu_post_load(void *opaque, int version_id) 752 { 753 ARMCPU *cpu = opaque; 754 CPUARMState *env = &cpu->env; 755 int i, v; 756 757 /* 758 * Handle migration compatibility from old QEMU which didn't 759 * send the irq-line-state subsection. A QEMU without it did not 760 * implement the HCR_EL2.{VI,VF} bits as generating interrupts, 761 * so for TCG the line state matches the bits set in cs->interrupt_request. 762 * For KVM the line state is not stored in cs->interrupt_request 763 * and so this will leave irq_line_state as 0, but this is OK because 764 * we only need to care about it for TCG. 765 */ 766 if (env->irq_line_state == UINT32_MAX) { 767 CPUState *cs = CPU(cpu); 768 769 env->irq_line_state = cs->interrupt_request & 770 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ | 771 CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VFIQ); 772 } 773 774 /* Update the values list from the incoming migration data. 775 * Anything in the incoming data which we don't know about is 776 * a migration failure; anything we know about but the incoming 777 * data doesn't specify retains its current (reset) value. 778 * The indexes list remains untouched -- we only inspect the 779 * incoming migration index list so we can match the values array 780 * entries with the right slots in our own values array. 781 */ 782 783 for (i = 0, v = 0; i < cpu->cpreg_array_len 784 && v < cpu->cpreg_vmstate_array_len; i++) { 785 if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { 786 /* register in our list but not incoming : skip it */ 787 continue; 788 } 789 if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { 790 /* register in their list but not ours: fail migration */ 791 return -1; 792 } 793 /* matching register, copy the value over */ 794 cpu->cpreg_values[i] = cpu->cpreg_vmstate_values[v]; 795 v++; 796 } 797 798 if (kvm_enabled()) { 799 if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { 800 return -1; 801 } 802 /* Note that it's OK for the TCG side not to know about 803 * every register in the list; KVM is authoritative if 804 * we're using it. 805 */ 806 write_list_to_cpustate(cpu); 807 kvm_arm_cpu_post_load(cpu); 808 } else { 809 if (!write_list_to_cpustate(cpu)) { 810 return -1; 811 } 812 } 813 814 hw_breakpoint_update_all(cpu); 815 hw_watchpoint_update_all(cpu); 816 817 /* 818 * TCG gen_update_fp_context() relies on the invariant that 819 * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; 820 * forbid bogus incoming data with some other value. 821 */ 822 if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { 823 if (extract32(env->v7m.fpdscr[M_REG_NS], 824 FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || 825 extract32(env->v7m.fpdscr[M_REG_S], 826 FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { 827 return -1; 828 } 829 } 830 831 /* 832 * Misaligned thumb pc is architecturally impossible. 833 * We have an assert in thumb_tr_translate_insn to verify this. 834 * Fail an incoming migrate to avoid this assert. 835 */ 836 if (!is_a64(env) && env->thumb && (env->regs[15] & 1)) { 837 return -1; 838 } 839 840 if (!kvm_enabled()) { 841 pmu_op_finish(&cpu->env); 842 } 843 arm_rebuild_hflags(&cpu->env); 844 845 return 0; 846 } 847 848 const VMStateDescription vmstate_arm_cpu = { 849 .name = "cpu", 850 .version_id = 22, 851 .minimum_version_id = 22, 852 .pre_save = cpu_pre_save, 853 .post_save = cpu_post_save, 854 .pre_load = cpu_pre_load, 855 .post_load = cpu_post_load, 856 .fields = (VMStateField[]) { 857 VMSTATE_UINT32_ARRAY(env.regs, ARMCPU, 16), 858 VMSTATE_UINT64_ARRAY(env.xregs, ARMCPU, 32), 859 VMSTATE_UINT64(env.pc, ARMCPU), 860 { 861 .name = "cpsr", 862 .version_id = 0, 863 .size = sizeof(uint32_t), 864 .info = &vmstate_cpsr, 865 .flags = VMS_SINGLE, 866 .offset = 0, 867 }, 868 VMSTATE_UINT32(env.spsr, ARMCPU), 869 VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8), 870 VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 8), 871 VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 8), 872 VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), 873 VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), 874 VMSTATE_UINT64_ARRAY(env.elr_el, ARMCPU, 4), 875 VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), 876 /* The length-check must come before the arrays to avoid 877 * incoming data possibly overflowing the array. 878 */ 879 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), 880 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, 881 cpreg_vmstate_array_len, 882 0, vmstate_info_uint64, uint64_t), 883 VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, 884 cpreg_vmstate_array_len, 885 0, vmstate_info_uint64, uint64_t), 886 VMSTATE_UINT64(env.exclusive_addr, ARMCPU), 887 VMSTATE_UINT64(env.exclusive_val, ARMCPU), 888 VMSTATE_UINT64(env.exclusive_high, ARMCPU), 889 VMSTATE_UNUSED(sizeof(uint64_t)), 890 VMSTATE_UINT32(env.exception.syndrome, ARMCPU), 891 VMSTATE_UINT32(env.exception.fsr, ARMCPU), 892 VMSTATE_UINT64(env.exception.vaddress, ARMCPU), 893 VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), 894 VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), 895 { 896 .name = "power_state", 897 .version_id = 0, 898 .size = sizeof(bool), 899 .info = &vmstate_powered_off, 900 .flags = VMS_SINGLE, 901 .offset = 0, 902 }, 903 VMSTATE_END_OF_LIST() 904 }, 905 .subsections = (const VMStateDescription*[]) { 906 &vmstate_vfp, 907 &vmstate_iwmmxt, 908 &vmstate_m, 909 &vmstate_thumb2ee, 910 /* pmsav7_rnr must come before pmsav7 so that we have the 911 * region number before we test it in the VMSTATE_VALIDATE 912 * in vmstate_pmsav7. 913 */ 914 &vmstate_pmsav7_rnr, 915 &vmstate_pmsav7, 916 &vmstate_pmsav8, 917 &vmstate_m_security, 918 #ifdef TARGET_AARCH64 919 &vmstate_sve, 920 &vmstate_za, 921 #endif 922 &vmstate_serror, 923 &vmstate_irq_line_state, 924 NULL 925 } 926 };