cpu_tcg.c (42275B)
1 /* 2 * QEMU ARM TCG CPUs. 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This code is licensed under the GNU GPL v2 or later. 7 * 8 * SPDX-License-Identifier: GPL-2.0-or-later 9 */ 10 11 #include "qemu/osdep.h" 12 #include "cpu.h" 13 #ifdef CONFIG_TCG 14 #include "hw/core/tcg-cpu-ops.h" 15 #endif /* CONFIG_TCG */ 16 #include "internals.h" 17 #include "target/arm/idau.h" 18 #if !defined(CONFIG_USER_ONLY) 19 #include "hw/boards.h" 20 #endif 21 #include "cpregs.h" 22 23 24 /* Share AArch32 -cpu max features with AArch64. */ 25 void aa32_max_features(ARMCPU *cpu) 26 { 27 uint32_t t; 28 29 /* Add additional features supported by QEMU */ 30 t = cpu->isar.id_isar5; 31 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ 32 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ 33 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ 34 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1); 35 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ 36 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ 37 cpu->isar.id_isar5 = t; 38 39 t = cpu->isar.id_isar6; 40 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ 41 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ 42 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ 43 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ 44 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ 45 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ 46 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ 47 cpu->isar.id_isar6 = t; 48 49 t = cpu->isar.mvfr1; 50 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ 51 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ 52 cpu->isar.mvfr1 = t; 53 54 t = cpu->isar.mvfr2; 55 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ 56 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ 57 cpu->isar.mvfr2 = t; 58 59 t = cpu->isar.id_mmfr3; 60 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ 61 cpu->isar.id_mmfr3 = t; 62 63 t = cpu->isar.id_mmfr4; 64 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ 65 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ 66 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ 67 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */ 68 cpu->isar.id_mmfr4 = t; 69 70 t = cpu->isar.id_mmfr5; 71 t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */ 72 cpu->isar.id_mmfr5 = t; 73 74 t = cpu->isar.id_pfr0; 75 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ 76 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ 77 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ 78 cpu->isar.id_pfr0 = t; 79 80 t = cpu->isar.id_pfr2; 81 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ 82 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ 83 cpu->isar.id_pfr2 = t; 84 85 t = cpu->isar.id_dfr0; 86 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ 87 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ 88 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ 89 cpu->isar.id_dfr0 = t; 90 } 91 92 #ifndef CONFIG_USER_ONLY 93 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 94 { 95 ARMCPU *cpu = env_archcpu(env); 96 97 /* Number of cores is in [25:24]; otherwise we RAZ */ 98 return (cpu->core_count - 1) << 24; 99 } 100 101 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = { 102 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64, 103 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2, 104 .access = PL1_RW, .readfn = l2ctlr_read, 105 .writefn = arm_cp_write_ignore }, 106 { .name = "L2CTLR", 107 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2, 108 .access = PL1_RW, .readfn = l2ctlr_read, 109 .writefn = arm_cp_write_ignore }, 110 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64, 111 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3, 112 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 113 { .name = "L2ECTLR", 114 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3, 115 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 116 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH, 117 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0, 118 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 119 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64, 120 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0, 121 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 122 { .name = "CPUACTLR", 123 .cp = 15, .opc1 = 0, .crm = 15, 124 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 125 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64, 126 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1, 127 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 128 { .name = "CPUECTLR", 129 .cp = 15, .opc1 = 1, .crm = 15, 130 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 131 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64, 132 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2, 133 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 134 { .name = "CPUMERRSR", 135 .cp = 15, .opc1 = 2, .crm = 15, 136 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 137 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64, 138 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3, 139 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 140 { .name = "L2MERRSR", 141 .cp = 15, .opc1 = 3, .crm = 15, 142 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, 143 }; 144 145 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) 146 { 147 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); 148 } 149 #endif /* !CONFIG_USER_ONLY */ 150 151 /* CPU models. These are not needed for the AArch64 linux-user build. */ 152 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) 153 154 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 155 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 156 { 157 CPUClass *cc = CPU_GET_CLASS(cs); 158 ARMCPU *cpu = ARM_CPU(cs); 159 CPUARMState *env = &cpu->env; 160 bool ret = false; 161 162 /* 163 * ARMv7-M interrupt masking works differently than -A or -R. 164 * There is no FIQ/IRQ distinction. Instead of I and F bits 165 * masking FIQ and IRQ interrupts, an exception is taken only 166 * if it is higher priority than the current execution priority 167 * (which depends on state like BASEPRI, FAULTMASK and the 168 * currently active exception). 169 */ 170 if (interrupt_request & CPU_INTERRUPT_HARD 171 && (armv7m_nvic_can_take_pending_exception(env->nvic))) { 172 cs->exception_index = EXCP_IRQ; 173 cc->tcg_ops->do_interrupt(cs); 174 ret = true; 175 } 176 return ret; 177 } 178 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 179 180 static void arm926_initfn(Object *obj) 181 { 182 ARMCPU *cpu = ARM_CPU(obj); 183 184 cpu->dtb_compatible = "arm,arm926"; 185 set_feature(&cpu->env, ARM_FEATURE_V5); 186 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 187 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 188 cpu->midr = 0x41069265; 189 cpu->reset_fpsid = 0x41011090; 190 cpu->ctr = 0x1dd20d2; 191 cpu->reset_sctlr = 0x00090078; 192 193 /* 194 * ARMv5 does not have the ID_ISAR registers, but we can still 195 * set the field to indicate Jazelle support within QEMU. 196 */ 197 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 198 /* 199 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 200 * support even though ARMv5 doesn't have this register. 201 */ 202 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 203 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 204 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 205 } 206 207 static void arm946_initfn(Object *obj) 208 { 209 ARMCPU *cpu = ARM_CPU(obj); 210 211 cpu->dtb_compatible = "arm,arm946"; 212 set_feature(&cpu->env, ARM_FEATURE_V5); 213 set_feature(&cpu->env, ARM_FEATURE_PMSA); 214 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 215 cpu->midr = 0x41059461; 216 cpu->ctr = 0x0f004006; 217 cpu->reset_sctlr = 0x00000078; 218 } 219 220 static void arm1026_initfn(Object *obj) 221 { 222 ARMCPU *cpu = ARM_CPU(obj); 223 224 cpu->dtb_compatible = "arm,arm1026"; 225 set_feature(&cpu->env, ARM_FEATURE_V5); 226 set_feature(&cpu->env, ARM_FEATURE_AUXCR); 227 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 228 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); 229 cpu->midr = 0x4106a262; 230 cpu->reset_fpsid = 0x410110a0; 231 cpu->ctr = 0x1dd20d2; 232 cpu->reset_sctlr = 0x00090078; 233 cpu->reset_auxcr = 1; 234 235 /* 236 * ARMv5 does not have the ID_ISAR registers, but we can still 237 * set the field to indicate Jazelle support within QEMU. 238 */ 239 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1); 240 /* 241 * Similarly, we need to set MVFR0 fields to enable vfp and short vector 242 * support even though ARMv5 doesn't have this register. 243 */ 244 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 245 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); 246 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); 247 248 { 249 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */ 250 ARMCPRegInfo ifar = { 251 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, 252 .access = PL1_RW, 253 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns), 254 .resetvalue = 0 255 }; 256 define_one_arm_cp_reg(cpu, &ifar); 257 } 258 } 259 260 static void arm1136_r2_initfn(Object *obj) 261 { 262 ARMCPU *cpu = ARM_CPU(obj); 263 /* 264 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an 265 * older core than plain "arm1136". In particular this does not 266 * have the v6K features. 267 * These ID register values are correct for 1136 but may be wrong 268 * for 1136_r2 (in particular r0p2 does not actually implement most 269 * of the ID registers). 270 */ 271 272 cpu->dtb_compatible = "arm,arm1136"; 273 set_feature(&cpu->env, ARM_FEATURE_V6); 274 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 275 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 276 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 277 cpu->midr = 0x4107b362; 278 cpu->reset_fpsid = 0x410120b4; 279 cpu->isar.mvfr0 = 0x11111111; 280 cpu->isar.mvfr1 = 0x00000000; 281 cpu->ctr = 0x1dd20d2; 282 cpu->reset_sctlr = 0x00050078; 283 cpu->isar.id_pfr0 = 0x111; 284 cpu->isar.id_pfr1 = 0x1; 285 cpu->isar.id_dfr0 = 0x2; 286 cpu->id_afr0 = 0x3; 287 cpu->isar.id_mmfr0 = 0x01130003; 288 cpu->isar.id_mmfr1 = 0x10030302; 289 cpu->isar.id_mmfr2 = 0x01222110; 290 cpu->isar.id_isar0 = 0x00140011; 291 cpu->isar.id_isar1 = 0x12002111; 292 cpu->isar.id_isar2 = 0x11231111; 293 cpu->isar.id_isar3 = 0x01102131; 294 cpu->isar.id_isar4 = 0x141; 295 cpu->reset_auxcr = 7; 296 } 297 298 static void arm1136_initfn(Object *obj) 299 { 300 ARMCPU *cpu = ARM_CPU(obj); 301 302 cpu->dtb_compatible = "arm,arm1136"; 303 set_feature(&cpu->env, ARM_FEATURE_V6K); 304 set_feature(&cpu->env, ARM_FEATURE_V6); 305 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 306 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 307 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 308 cpu->midr = 0x4117b363; 309 cpu->reset_fpsid = 0x410120b4; 310 cpu->isar.mvfr0 = 0x11111111; 311 cpu->isar.mvfr1 = 0x00000000; 312 cpu->ctr = 0x1dd20d2; 313 cpu->reset_sctlr = 0x00050078; 314 cpu->isar.id_pfr0 = 0x111; 315 cpu->isar.id_pfr1 = 0x1; 316 cpu->isar.id_dfr0 = 0x2; 317 cpu->id_afr0 = 0x3; 318 cpu->isar.id_mmfr0 = 0x01130003; 319 cpu->isar.id_mmfr1 = 0x10030302; 320 cpu->isar.id_mmfr2 = 0x01222110; 321 cpu->isar.id_isar0 = 0x00140011; 322 cpu->isar.id_isar1 = 0x12002111; 323 cpu->isar.id_isar2 = 0x11231111; 324 cpu->isar.id_isar3 = 0x01102131; 325 cpu->isar.id_isar4 = 0x141; 326 cpu->reset_auxcr = 7; 327 } 328 329 static void arm1176_initfn(Object *obj) 330 { 331 ARMCPU *cpu = ARM_CPU(obj); 332 333 cpu->dtb_compatible = "arm,arm1176"; 334 set_feature(&cpu->env, ARM_FEATURE_V6K); 335 set_feature(&cpu->env, ARM_FEATURE_VAPA); 336 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 337 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); 338 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); 339 set_feature(&cpu->env, ARM_FEATURE_EL3); 340 cpu->midr = 0x410fb767; 341 cpu->reset_fpsid = 0x410120b5; 342 cpu->isar.mvfr0 = 0x11111111; 343 cpu->isar.mvfr1 = 0x00000000; 344 cpu->ctr = 0x1dd20d2; 345 cpu->reset_sctlr = 0x00050078; 346 cpu->isar.id_pfr0 = 0x111; 347 cpu->isar.id_pfr1 = 0x11; 348 cpu->isar.id_dfr0 = 0x33; 349 cpu->id_afr0 = 0; 350 cpu->isar.id_mmfr0 = 0x01130003; 351 cpu->isar.id_mmfr1 = 0x10030302; 352 cpu->isar.id_mmfr2 = 0x01222100; 353 cpu->isar.id_isar0 = 0x0140011; 354 cpu->isar.id_isar1 = 0x12002111; 355 cpu->isar.id_isar2 = 0x11231121; 356 cpu->isar.id_isar3 = 0x01102131; 357 cpu->isar.id_isar4 = 0x01141; 358 cpu->reset_auxcr = 7; 359 } 360 361 static void arm11mpcore_initfn(Object *obj) 362 { 363 ARMCPU *cpu = ARM_CPU(obj); 364 365 cpu->dtb_compatible = "arm,arm11mpcore"; 366 set_feature(&cpu->env, ARM_FEATURE_V6K); 367 set_feature(&cpu->env, ARM_FEATURE_VAPA); 368 set_feature(&cpu->env, ARM_FEATURE_MPIDR); 369 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 370 cpu->midr = 0x410fb022; 371 cpu->reset_fpsid = 0x410120b4; 372 cpu->isar.mvfr0 = 0x11111111; 373 cpu->isar.mvfr1 = 0x00000000; 374 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ 375 cpu->isar.id_pfr0 = 0x111; 376 cpu->isar.id_pfr1 = 0x1; 377 cpu->isar.id_dfr0 = 0; 378 cpu->id_afr0 = 0x2; 379 cpu->isar.id_mmfr0 = 0x01100103; 380 cpu->isar.id_mmfr1 = 0x10020302; 381 cpu->isar.id_mmfr2 = 0x01222000; 382 cpu->isar.id_isar0 = 0x00100011; 383 cpu->isar.id_isar1 = 0x12002111; 384 cpu->isar.id_isar2 = 0x11221011; 385 cpu->isar.id_isar3 = 0x01102131; 386 cpu->isar.id_isar4 = 0x141; 387 cpu->reset_auxcr = 1; 388 } 389 390 static const ARMCPRegInfo cortexa8_cp_reginfo[] = { 391 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, 392 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 393 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 394 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 395 }; 396 397 static void cortex_a8_initfn(Object *obj) 398 { 399 ARMCPU *cpu = ARM_CPU(obj); 400 401 cpu->dtb_compatible = "arm,cortex-a8"; 402 set_feature(&cpu->env, ARM_FEATURE_V7); 403 set_feature(&cpu->env, ARM_FEATURE_NEON); 404 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 405 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 406 set_feature(&cpu->env, ARM_FEATURE_EL3); 407 cpu->midr = 0x410fc080; 408 cpu->reset_fpsid = 0x410330c0; 409 cpu->isar.mvfr0 = 0x11110222; 410 cpu->isar.mvfr1 = 0x00011111; 411 cpu->ctr = 0x82048004; 412 cpu->reset_sctlr = 0x00c50078; 413 cpu->isar.id_pfr0 = 0x1031; 414 cpu->isar.id_pfr1 = 0x11; 415 cpu->isar.id_dfr0 = 0x400; 416 cpu->id_afr0 = 0; 417 cpu->isar.id_mmfr0 = 0x31100003; 418 cpu->isar.id_mmfr1 = 0x20000000; 419 cpu->isar.id_mmfr2 = 0x01202000; 420 cpu->isar.id_mmfr3 = 0x11; 421 cpu->isar.id_isar0 = 0x00101111; 422 cpu->isar.id_isar1 = 0x12112111; 423 cpu->isar.id_isar2 = 0x21232031; 424 cpu->isar.id_isar3 = 0x11112131; 425 cpu->isar.id_isar4 = 0x00111142; 426 cpu->isar.dbgdidr = 0x15141000; 427 cpu->clidr = (1 << 27) | (2 << 24) | 3; 428 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */ 429 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */ 430 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */ 431 cpu->reset_auxcr = 2; 432 cpu->isar.reset_pmcr_el0 = 0x41002000; 433 define_arm_cp_regs(cpu, cortexa8_cp_reginfo); 434 } 435 436 static const ARMCPRegInfo cortexa9_cp_reginfo[] = { 437 /* 438 * power_control should be set to maximum latency. Again, 439 * default to 0 and set by private hook 440 */ 441 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, 442 .access = PL1_RW, .resetvalue = 0, 443 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) }, 444 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1, 445 .access = PL1_RW, .resetvalue = 0, 446 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) }, 447 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2, 448 .access = PL1_RW, .resetvalue = 0, 449 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) }, 450 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, 451 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 452 /* TLB lockdown control */ 453 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2, 454 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 455 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4, 456 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP }, 457 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2, 458 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 459 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2, 460 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 461 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2, 462 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST }, 463 }; 464 465 static void cortex_a9_initfn(Object *obj) 466 { 467 ARMCPU *cpu = ARM_CPU(obj); 468 469 cpu->dtb_compatible = "arm,cortex-a9"; 470 set_feature(&cpu->env, ARM_FEATURE_V7); 471 set_feature(&cpu->env, ARM_FEATURE_NEON); 472 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 473 set_feature(&cpu->env, ARM_FEATURE_EL3); 474 /* 475 * Note that A9 supports the MP extensions even for 476 * A9UP and single-core A9MP (which are both different 477 * and valid configurations; we don't model A9UP). 478 */ 479 set_feature(&cpu->env, ARM_FEATURE_V7MP); 480 set_feature(&cpu->env, ARM_FEATURE_CBAR); 481 cpu->midr = 0x410fc090; 482 cpu->reset_fpsid = 0x41033090; 483 cpu->isar.mvfr0 = 0x11110222; 484 cpu->isar.mvfr1 = 0x01111111; 485 cpu->ctr = 0x80038003; 486 cpu->reset_sctlr = 0x00c50078; 487 cpu->isar.id_pfr0 = 0x1031; 488 cpu->isar.id_pfr1 = 0x11; 489 cpu->isar.id_dfr0 = 0x000; 490 cpu->id_afr0 = 0; 491 cpu->isar.id_mmfr0 = 0x00100103; 492 cpu->isar.id_mmfr1 = 0x20000000; 493 cpu->isar.id_mmfr2 = 0x01230000; 494 cpu->isar.id_mmfr3 = 0x00002111; 495 cpu->isar.id_isar0 = 0x00101111; 496 cpu->isar.id_isar1 = 0x13112111; 497 cpu->isar.id_isar2 = 0x21232041; 498 cpu->isar.id_isar3 = 0x11112131; 499 cpu->isar.id_isar4 = 0x00111142; 500 cpu->isar.dbgdidr = 0x35141000; 501 cpu->clidr = (1 << 27) | (1 << 24) | 3; 502 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */ 503 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */ 504 cpu->isar.reset_pmcr_el0 = 0x41093000; 505 define_arm_cp_regs(cpu, cortexa9_cp_reginfo); 506 } 507 508 #ifndef CONFIG_USER_ONLY 509 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) 510 { 511 MachineState *ms = MACHINE(qdev_get_machine()); 512 513 /* 514 * Linux wants the number of processors from here. 515 * Might as well set the interrupt-controller bit too. 516 */ 517 return ((ms->smp.cpus - 1) << 24) | (1 << 23); 518 } 519 #endif 520 521 static const ARMCPRegInfo cortexa15_cp_reginfo[] = { 522 #ifndef CONFIG_USER_ONLY 523 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, 524 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, 525 .writefn = arm_cp_write_ignore, }, 526 #endif 527 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, 528 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, 529 }; 530 531 static void cortex_a7_initfn(Object *obj) 532 { 533 ARMCPU *cpu = ARM_CPU(obj); 534 535 cpu->dtb_compatible = "arm,cortex-a7"; 536 set_feature(&cpu->env, ARM_FEATURE_V7VE); 537 set_feature(&cpu->env, ARM_FEATURE_NEON); 538 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 539 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 540 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 541 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 542 set_feature(&cpu->env, ARM_FEATURE_EL2); 543 set_feature(&cpu->env, ARM_FEATURE_EL3); 544 set_feature(&cpu->env, ARM_FEATURE_PMU); 545 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; 546 cpu->midr = 0x410fc075; 547 cpu->reset_fpsid = 0x41023075; 548 cpu->isar.mvfr0 = 0x10110222; 549 cpu->isar.mvfr1 = 0x11111111; 550 cpu->ctr = 0x84448003; 551 cpu->reset_sctlr = 0x00c50078; 552 cpu->isar.id_pfr0 = 0x00001131; 553 cpu->isar.id_pfr1 = 0x00011011; 554 cpu->isar.id_dfr0 = 0x02010555; 555 cpu->id_afr0 = 0x00000000; 556 cpu->isar.id_mmfr0 = 0x10101105; 557 cpu->isar.id_mmfr1 = 0x40000000; 558 cpu->isar.id_mmfr2 = 0x01240000; 559 cpu->isar.id_mmfr3 = 0x02102211; 560 /* 561 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but 562 * table 4-41 gives 0x02101110, which includes the arm div insns. 563 */ 564 cpu->isar.id_isar0 = 0x02101110; 565 cpu->isar.id_isar1 = 0x13112111; 566 cpu->isar.id_isar2 = 0x21232041; 567 cpu->isar.id_isar3 = 0x11112131; 568 cpu->isar.id_isar4 = 0x10011142; 569 cpu->isar.dbgdidr = 0x3515f005; 570 cpu->isar.dbgdevid = 0x01110f13; 571 cpu->isar.dbgdevid1 = 0x1; 572 cpu->clidr = 0x0a200023; 573 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 574 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 575 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 576 cpu->isar.reset_pmcr_el0 = 0x41072000; 577 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ 578 } 579 580 static void cortex_a15_initfn(Object *obj) 581 { 582 ARMCPU *cpu = ARM_CPU(obj); 583 584 cpu->dtb_compatible = "arm,cortex-a15"; 585 set_feature(&cpu->env, ARM_FEATURE_V7VE); 586 set_feature(&cpu->env, ARM_FEATURE_NEON); 587 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); 588 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 589 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 590 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 591 set_feature(&cpu->env, ARM_FEATURE_EL2); 592 set_feature(&cpu->env, ARM_FEATURE_EL3); 593 set_feature(&cpu->env, ARM_FEATURE_PMU); 594 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; 595 /* r4p0 cpu, not requiring expensive tlb flush errata */ 596 cpu->midr = 0x414fc0f0; 597 cpu->revidr = 0x0; 598 cpu->reset_fpsid = 0x410430f0; 599 cpu->isar.mvfr0 = 0x10110222; 600 cpu->isar.mvfr1 = 0x11111111; 601 cpu->ctr = 0x8444c004; 602 cpu->reset_sctlr = 0x00c50078; 603 cpu->isar.id_pfr0 = 0x00001131; 604 cpu->isar.id_pfr1 = 0x00011011; 605 cpu->isar.id_dfr0 = 0x02010555; 606 cpu->id_afr0 = 0x00000000; 607 cpu->isar.id_mmfr0 = 0x10201105; 608 cpu->isar.id_mmfr1 = 0x20000000; 609 cpu->isar.id_mmfr2 = 0x01240000; 610 cpu->isar.id_mmfr3 = 0x02102211; 611 cpu->isar.id_isar0 = 0x02101110; 612 cpu->isar.id_isar1 = 0x13112111; 613 cpu->isar.id_isar2 = 0x21232041; 614 cpu->isar.id_isar3 = 0x11112131; 615 cpu->isar.id_isar4 = 0x10011142; 616 cpu->isar.dbgdidr = 0x3515f021; 617 cpu->isar.dbgdevid = 0x01110f13; 618 cpu->isar.dbgdevid1 = 0x0; 619 cpu->clidr = 0x0a200023; 620 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */ 621 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */ 622 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */ 623 cpu->isar.reset_pmcr_el0 = 0x410F3000; 624 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); 625 } 626 627 static void cortex_m0_initfn(Object *obj) 628 { 629 ARMCPU *cpu = ARM_CPU(obj); 630 set_feature(&cpu->env, ARM_FEATURE_V6); 631 set_feature(&cpu->env, ARM_FEATURE_M); 632 633 cpu->midr = 0x410cc200; 634 635 /* 636 * These ID register values are not guest visible, because 637 * we do not implement the Main Extension. They must be set 638 * to values corresponding to the Cortex-M0's implemented 639 * features, because QEMU generally controls its emulation 640 * by looking at ID register fields. We use the same values as 641 * for the M3. 642 */ 643 cpu->isar.id_pfr0 = 0x00000030; 644 cpu->isar.id_pfr1 = 0x00000200; 645 cpu->isar.id_dfr0 = 0x00100000; 646 cpu->id_afr0 = 0x00000000; 647 cpu->isar.id_mmfr0 = 0x00000030; 648 cpu->isar.id_mmfr1 = 0x00000000; 649 cpu->isar.id_mmfr2 = 0x00000000; 650 cpu->isar.id_mmfr3 = 0x00000000; 651 cpu->isar.id_isar0 = 0x01141110; 652 cpu->isar.id_isar1 = 0x02111000; 653 cpu->isar.id_isar2 = 0x21112231; 654 cpu->isar.id_isar3 = 0x01111110; 655 cpu->isar.id_isar4 = 0x01310102; 656 cpu->isar.id_isar5 = 0x00000000; 657 cpu->isar.id_isar6 = 0x00000000; 658 } 659 660 static void cortex_m3_initfn(Object *obj) 661 { 662 ARMCPU *cpu = ARM_CPU(obj); 663 set_feature(&cpu->env, ARM_FEATURE_V7); 664 set_feature(&cpu->env, ARM_FEATURE_M); 665 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 666 cpu->midr = 0x410fc231; 667 cpu->pmsav7_dregion = 8; 668 cpu->isar.id_pfr0 = 0x00000030; 669 cpu->isar.id_pfr1 = 0x00000200; 670 cpu->isar.id_dfr0 = 0x00100000; 671 cpu->id_afr0 = 0x00000000; 672 cpu->isar.id_mmfr0 = 0x00000030; 673 cpu->isar.id_mmfr1 = 0x00000000; 674 cpu->isar.id_mmfr2 = 0x00000000; 675 cpu->isar.id_mmfr3 = 0x00000000; 676 cpu->isar.id_isar0 = 0x01141110; 677 cpu->isar.id_isar1 = 0x02111000; 678 cpu->isar.id_isar2 = 0x21112231; 679 cpu->isar.id_isar3 = 0x01111110; 680 cpu->isar.id_isar4 = 0x01310102; 681 cpu->isar.id_isar5 = 0x00000000; 682 cpu->isar.id_isar6 = 0x00000000; 683 } 684 685 static void cortex_m4_initfn(Object *obj) 686 { 687 ARMCPU *cpu = ARM_CPU(obj); 688 689 set_feature(&cpu->env, ARM_FEATURE_V7); 690 set_feature(&cpu->env, ARM_FEATURE_M); 691 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 692 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 693 cpu->midr = 0x410fc240; /* r0p0 */ 694 cpu->pmsav7_dregion = 8; 695 cpu->isar.mvfr0 = 0x10110021; 696 cpu->isar.mvfr1 = 0x11000011; 697 cpu->isar.mvfr2 = 0x00000000; 698 cpu->isar.id_pfr0 = 0x00000030; 699 cpu->isar.id_pfr1 = 0x00000200; 700 cpu->isar.id_dfr0 = 0x00100000; 701 cpu->id_afr0 = 0x00000000; 702 cpu->isar.id_mmfr0 = 0x00000030; 703 cpu->isar.id_mmfr1 = 0x00000000; 704 cpu->isar.id_mmfr2 = 0x00000000; 705 cpu->isar.id_mmfr3 = 0x00000000; 706 cpu->isar.id_isar0 = 0x01141110; 707 cpu->isar.id_isar1 = 0x02111000; 708 cpu->isar.id_isar2 = 0x21112231; 709 cpu->isar.id_isar3 = 0x01111110; 710 cpu->isar.id_isar4 = 0x01310102; 711 cpu->isar.id_isar5 = 0x00000000; 712 cpu->isar.id_isar6 = 0x00000000; 713 } 714 715 static void cortex_m7_initfn(Object *obj) 716 { 717 ARMCPU *cpu = ARM_CPU(obj); 718 719 set_feature(&cpu->env, ARM_FEATURE_V7); 720 set_feature(&cpu->env, ARM_FEATURE_M); 721 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 722 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 723 cpu->midr = 0x411fc272; /* r1p2 */ 724 cpu->pmsav7_dregion = 8; 725 cpu->isar.mvfr0 = 0x10110221; 726 cpu->isar.mvfr1 = 0x12000011; 727 cpu->isar.mvfr2 = 0x00000040; 728 cpu->isar.id_pfr0 = 0x00000030; 729 cpu->isar.id_pfr1 = 0x00000200; 730 cpu->isar.id_dfr0 = 0x00100000; 731 cpu->id_afr0 = 0x00000000; 732 cpu->isar.id_mmfr0 = 0x00100030; 733 cpu->isar.id_mmfr1 = 0x00000000; 734 cpu->isar.id_mmfr2 = 0x01000000; 735 cpu->isar.id_mmfr3 = 0x00000000; 736 cpu->isar.id_isar0 = 0x01101110; 737 cpu->isar.id_isar1 = 0x02112000; 738 cpu->isar.id_isar2 = 0x20232231; 739 cpu->isar.id_isar3 = 0x01111131; 740 cpu->isar.id_isar4 = 0x01310132; 741 cpu->isar.id_isar5 = 0x00000000; 742 cpu->isar.id_isar6 = 0x00000000; 743 } 744 745 static void cortex_m33_initfn(Object *obj) 746 { 747 ARMCPU *cpu = ARM_CPU(obj); 748 749 set_feature(&cpu->env, ARM_FEATURE_V8); 750 set_feature(&cpu->env, ARM_FEATURE_M); 751 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 752 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 753 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 754 cpu->midr = 0x410fd213; /* r0p3 */ 755 cpu->pmsav7_dregion = 16; 756 cpu->sau_sregion = 8; 757 cpu->isar.mvfr0 = 0x10110021; 758 cpu->isar.mvfr1 = 0x11000011; 759 cpu->isar.mvfr2 = 0x00000040; 760 cpu->isar.id_pfr0 = 0x00000030; 761 cpu->isar.id_pfr1 = 0x00000210; 762 cpu->isar.id_dfr0 = 0x00200000; 763 cpu->id_afr0 = 0x00000000; 764 cpu->isar.id_mmfr0 = 0x00101F40; 765 cpu->isar.id_mmfr1 = 0x00000000; 766 cpu->isar.id_mmfr2 = 0x01000000; 767 cpu->isar.id_mmfr3 = 0x00000000; 768 cpu->isar.id_isar0 = 0x01101110; 769 cpu->isar.id_isar1 = 0x02212000; 770 cpu->isar.id_isar2 = 0x20232232; 771 cpu->isar.id_isar3 = 0x01111131; 772 cpu->isar.id_isar4 = 0x01310132; 773 cpu->isar.id_isar5 = 0x00000000; 774 cpu->isar.id_isar6 = 0x00000000; 775 cpu->clidr = 0x00000000; 776 cpu->ctr = 0x8000c000; 777 } 778 779 static void cortex_m55_initfn(Object *obj) 780 { 781 ARMCPU *cpu = ARM_CPU(obj); 782 783 set_feature(&cpu->env, ARM_FEATURE_V8); 784 set_feature(&cpu->env, ARM_FEATURE_V8_1M); 785 set_feature(&cpu->env, ARM_FEATURE_M); 786 set_feature(&cpu->env, ARM_FEATURE_M_MAIN); 787 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); 788 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); 789 cpu->midr = 0x410fd221; /* r0p1 */ 790 cpu->revidr = 0; 791 cpu->pmsav7_dregion = 16; 792 cpu->sau_sregion = 8; 793 /* These are the MVFR* values for the FPU + full MVE configuration */ 794 cpu->isar.mvfr0 = 0x10110221; 795 cpu->isar.mvfr1 = 0x12100211; 796 cpu->isar.mvfr2 = 0x00000040; 797 cpu->isar.id_pfr0 = 0x20000030; 798 cpu->isar.id_pfr1 = 0x00000230; 799 cpu->isar.id_dfr0 = 0x10200000; 800 cpu->id_afr0 = 0x00000000; 801 cpu->isar.id_mmfr0 = 0x00111040; 802 cpu->isar.id_mmfr1 = 0x00000000; 803 cpu->isar.id_mmfr2 = 0x01000000; 804 cpu->isar.id_mmfr3 = 0x00000011; 805 cpu->isar.id_isar0 = 0x01103110; 806 cpu->isar.id_isar1 = 0x02212000; 807 cpu->isar.id_isar2 = 0x20232232; 808 cpu->isar.id_isar3 = 0x01111131; 809 cpu->isar.id_isar4 = 0x01310132; 810 cpu->isar.id_isar5 = 0x00000000; 811 cpu->isar.id_isar6 = 0x00000000; 812 cpu->clidr = 0x00000000; /* caches not implemented */ 813 cpu->ctr = 0x8303c003; 814 } 815 816 static const ARMCPRegInfo cortexr5_cp_reginfo[] = { 817 /* Dummy the TCM region regs for the moment */ 818 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, 819 .access = PL1_RW, .type = ARM_CP_CONST }, 820 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, 821 .access = PL1_RW, .type = ARM_CP_CONST }, 822 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5, 823 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP }, 824 }; 825 826 static void cortex_r5_initfn(Object *obj) 827 { 828 ARMCPU *cpu = ARM_CPU(obj); 829 830 set_feature(&cpu->env, ARM_FEATURE_V7); 831 set_feature(&cpu->env, ARM_FEATURE_V7MP); 832 set_feature(&cpu->env, ARM_FEATURE_PMSA); 833 set_feature(&cpu->env, ARM_FEATURE_PMU); 834 cpu->midr = 0x411fc153; /* r1p3 */ 835 cpu->isar.id_pfr0 = 0x0131; 836 cpu->isar.id_pfr1 = 0x001; 837 cpu->isar.id_dfr0 = 0x010400; 838 cpu->id_afr0 = 0x0; 839 cpu->isar.id_mmfr0 = 0x0210030; 840 cpu->isar.id_mmfr1 = 0x00000000; 841 cpu->isar.id_mmfr2 = 0x01200000; 842 cpu->isar.id_mmfr3 = 0x0211; 843 cpu->isar.id_isar0 = 0x02101111; 844 cpu->isar.id_isar1 = 0x13112111; 845 cpu->isar.id_isar2 = 0x21232141; 846 cpu->isar.id_isar3 = 0x01112131; 847 cpu->isar.id_isar4 = 0x0010142; 848 cpu->isar.id_isar5 = 0x0; 849 cpu->isar.id_isar6 = 0x0; 850 cpu->mp_is_up = true; 851 cpu->pmsav7_dregion = 16; 852 cpu->isar.reset_pmcr_el0 = 0x41151800; 853 define_arm_cp_regs(cpu, cortexr5_cp_reginfo); 854 } 855 856 static void cortex_r5f_initfn(Object *obj) 857 { 858 ARMCPU *cpu = ARM_CPU(obj); 859 860 cortex_r5_initfn(obj); 861 cpu->isar.mvfr0 = 0x10110221; 862 cpu->isar.mvfr1 = 0x00000011; 863 } 864 865 static void ti925t_initfn(Object *obj) 866 { 867 ARMCPU *cpu = ARM_CPU(obj); 868 set_feature(&cpu->env, ARM_FEATURE_V4T); 869 set_feature(&cpu->env, ARM_FEATURE_OMAPCP); 870 cpu->midr = ARM_CPUID_TI925T; 871 cpu->ctr = 0x5109149; 872 cpu->reset_sctlr = 0x00000070; 873 } 874 875 static void sa1100_initfn(Object *obj) 876 { 877 ARMCPU *cpu = ARM_CPU(obj); 878 879 cpu->dtb_compatible = "intel,sa1100"; 880 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 881 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 882 cpu->midr = 0x4401A11B; 883 cpu->reset_sctlr = 0x00000070; 884 } 885 886 static void sa1110_initfn(Object *obj) 887 { 888 ARMCPU *cpu = ARM_CPU(obj); 889 set_feature(&cpu->env, ARM_FEATURE_STRONGARM); 890 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); 891 cpu->midr = 0x6901B119; 892 cpu->reset_sctlr = 0x00000070; 893 } 894 895 static void pxa250_initfn(Object *obj) 896 { 897 ARMCPU *cpu = ARM_CPU(obj); 898 899 cpu->dtb_compatible = "marvell,xscale"; 900 set_feature(&cpu->env, ARM_FEATURE_V5); 901 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 902 cpu->midr = 0x69052100; 903 cpu->ctr = 0xd172172; 904 cpu->reset_sctlr = 0x00000078; 905 } 906 907 static void pxa255_initfn(Object *obj) 908 { 909 ARMCPU *cpu = ARM_CPU(obj); 910 911 cpu->dtb_compatible = "marvell,xscale"; 912 set_feature(&cpu->env, ARM_FEATURE_V5); 913 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 914 cpu->midr = 0x69052d00; 915 cpu->ctr = 0xd172172; 916 cpu->reset_sctlr = 0x00000078; 917 } 918 919 static void pxa260_initfn(Object *obj) 920 { 921 ARMCPU *cpu = ARM_CPU(obj); 922 923 cpu->dtb_compatible = "marvell,xscale"; 924 set_feature(&cpu->env, ARM_FEATURE_V5); 925 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 926 cpu->midr = 0x69052903; 927 cpu->ctr = 0xd172172; 928 cpu->reset_sctlr = 0x00000078; 929 } 930 931 static void pxa261_initfn(Object *obj) 932 { 933 ARMCPU *cpu = ARM_CPU(obj); 934 935 cpu->dtb_compatible = "marvell,xscale"; 936 set_feature(&cpu->env, ARM_FEATURE_V5); 937 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 938 cpu->midr = 0x69052d05; 939 cpu->ctr = 0xd172172; 940 cpu->reset_sctlr = 0x00000078; 941 } 942 943 static void pxa262_initfn(Object *obj) 944 { 945 ARMCPU *cpu = ARM_CPU(obj); 946 947 cpu->dtb_compatible = "marvell,xscale"; 948 set_feature(&cpu->env, ARM_FEATURE_V5); 949 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 950 cpu->midr = 0x69052d06; 951 cpu->ctr = 0xd172172; 952 cpu->reset_sctlr = 0x00000078; 953 } 954 955 static void pxa270a0_initfn(Object *obj) 956 { 957 ARMCPU *cpu = ARM_CPU(obj); 958 959 cpu->dtb_compatible = "marvell,xscale"; 960 set_feature(&cpu->env, ARM_FEATURE_V5); 961 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 962 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 963 cpu->midr = 0x69054110; 964 cpu->ctr = 0xd172172; 965 cpu->reset_sctlr = 0x00000078; 966 } 967 968 static void pxa270a1_initfn(Object *obj) 969 { 970 ARMCPU *cpu = ARM_CPU(obj); 971 972 cpu->dtb_compatible = "marvell,xscale"; 973 set_feature(&cpu->env, ARM_FEATURE_V5); 974 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 975 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 976 cpu->midr = 0x69054111; 977 cpu->ctr = 0xd172172; 978 cpu->reset_sctlr = 0x00000078; 979 } 980 981 static void pxa270b0_initfn(Object *obj) 982 { 983 ARMCPU *cpu = ARM_CPU(obj); 984 985 cpu->dtb_compatible = "marvell,xscale"; 986 set_feature(&cpu->env, ARM_FEATURE_V5); 987 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 988 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 989 cpu->midr = 0x69054112; 990 cpu->ctr = 0xd172172; 991 cpu->reset_sctlr = 0x00000078; 992 } 993 994 static void pxa270b1_initfn(Object *obj) 995 { 996 ARMCPU *cpu = ARM_CPU(obj); 997 998 cpu->dtb_compatible = "marvell,xscale"; 999 set_feature(&cpu->env, ARM_FEATURE_V5); 1000 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1001 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1002 cpu->midr = 0x69054113; 1003 cpu->ctr = 0xd172172; 1004 cpu->reset_sctlr = 0x00000078; 1005 } 1006 1007 static void pxa270c0_initfn(Object *obj) 1008 { 1009 ARMCPU *cpu = ARM_CPU(obj); 1010 1011 cpu->dtb_compatible = "marvell,xscale"; 1012 set_feature(&cpu->env, ARM_FEATURE_V5); 1013 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1014 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1015 cpu->midr = 0x69054114; 1016 cpu->ctr = 0xd172172; 1017 cpu->reset_sctlr = 0x00000078; 1018 } 1019 1020 static void pxa270c5_initfn(Object *obj) 1021 { 1022 ARMCPU *cpu = ARM_CPU(obj); 1023 1024 cpu->dtb_compatible = "marvell,xscale"; 1025 set_feature(&cpu->env, ARM_FEATURE_V5); 1026 set_feature(&cpu->env, ARM_FEATURE_XSCALE); 1027 set_feature(&cpu->env, ARM_FEATURE_IWMMXT); 1028 cpu->midr = 0x69054117; 1029 cpu->ctr = 0xd172172; 1030 cpu->reset_sctlr = 0x00000078; 1031 } 1032 1033 #ifdef CONFIG_TCG 1034 static const struct TCGCPUOps arm_v7m_tcg_ops = { 1035 .initialize = arm_translate_init, 1036 .synchronize_from_tb = arm_cpu_synchronize_from_tb, 1037 .debug_excp_handler = arm_debug_excp_handler, 1038 .restore_state_to_opc = arm_restore_state_to_opc, 1039 1040 #ifdef CONFIG_USER_ONLY 1041 .record_sigsegv = arm_cpu_record_sigsegv, 1042 .record_sigbus = arm_cpu_record_sigbus, 1043 #else 1044 .tlb_fill = arm_cpu_tlb_fill, 1045 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt, 1046 .do_interrupt = arm_v7m_cpu_do_interrupt, 1047 .do_transaction_failed = arm_cpu_do_transaction_failed, 1048 .do_unaligned_access = arm_cpu_do_unaligned_access, 1049 .adjust_watchpoint_address = arm_adjust_watchpoint_address, 1050 .debug_check_watchpoint = arm_debug_check_watchpoint, 1051 .debug_check_breakpoint = arm_debug_check_breakpoint, 1052 #endif /* !CONFIG_USER_ONLY */ 1053 }; 1054 #endif /* CONFIG_TCG */ 1055 1056 static void arm_v7m_class_init(ObjectClass *oc, void *data) 1057 { 1058 ARMCPUClass *acc = ARM_CPU_CLASS(oc); 1059 CPUClass *cc = CPU_CLASS(oc); 1060 1061 acc->info = data; 1062 #ifdef CONFIG_TCG 1063 cc->tcg_ops = &arm_v7m_tcg_ops; 1064 #endif /* CONFIG_TCG */ 1065 1066 cc->gdb_core_xml_file = "arm-m-profile.xml"; 1067 } 1068 1069 #ifndef TARGET_AARCH64 1070 /* 1071 * -cpu max: a CPU with as many features enabled as our emulation supports. 1072 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; 1073 * this only needs to handle 32 bits, and need not care about KVM. 1074 */ 1075 static void arm_max_initfn(Object *obj) 1076 { 1077 ARMCPU *cpu = ARM_CPU(obj); 1078 1079 /* aarch64_a57_initfn, advertising none of the aarch64 features */ 1080 cpu->dtb_compatible = "arm,cortex-a57"; 1081 set_feature(&cpu->env, ARM_FEATURE_V8); 1082 set_feature(&cpu->env, ARM_FEATURE_NEON); 1083 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); 1084 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); 1085 set_feature(&cpu->env, ARM_FEATURE_EL2); 1086 set_feature(&cpu->env, ARM_FEATURE_EL3); 1087 set_feature(&cpu->env, ARM_FEATURE_PMU); 1088 cpu->midr = 0x411fd070; 1089 cpu->revidr = 0x00000000; 1090 cpu->reset_fpsid = 0x41034070; 1091 cpu->isar.mvfr0 = 0x10110222; 1092 cpu->isar.mvfr1 = 0x12111111; 1093 cpu->isar.mvfr2 = 0x00000043; 1094 cpu->ctr = 0x8444c004; 1095 cpu->reset_sctlr = 0x00c50838; 1096 cpu->isar.id_pfr0 = 0x00000131; 1097 cpu->isar.id_pfr1 = 0x00011011; 1098 cpu->isar.id_dfr0 = 0x03010066; 1099 cpu->id_afr0 = 0x00000000; 1100 cpu->isar.id_mmfr0 = 0x10101105; 1101 cpu->isar.id_mmfr1 = 0x40000000; 1102 cpu->isar.id_mmfr2 = 0x01260000; 1103 cpu->isar.id_mmfr3 = 0x02102211; 1104 cpu->isar.id_isar0 = 0x02101110; 1105 cpu->isar.id_isar1 = 0x13112111; 1106 cpu->isar.id_isar2 = 0x21232042; 1107 cpu->isar.id_isar3 = 0x01112131; 1108 cpu->isar.id_isar4 = 0x00011142; 1109 cpu->isar.id_isar5 = 0x00011121; 1110 cpu->isar.id_isar6 = 0; 1111 cpu->isar.dbgdidr = 0x3516d000; 1112 cpu->isar.dbgdevid = 0x00110f13; 1113 cpu->isar.dbgdevid1 = 0x2; 1114 cpu->isar.reset_pmcr_el0 = 0x41013000; 1115 cpu->clidr = 0x0a200023; 1116 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ 1117 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ 1118 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ 1119 define_cortex_a72_a57_a53_cp_reginfo(cpu); 1120 1121 aa32_max_features(cpu); 1122 1123 #ifdef CONFIG_USER_ONLY 1124 /* 1125 * Break with true ARMv8 and add back old-style VFP short-vector support. 1126 * Only do this for user-mode, where -cpu max is the default, so that 1127 * older v6 and v7 programs are more likely to work without adjustment. 1128 */ 1129 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); 1130 #endif 1131 } 1132 #endif /* !TARGET_AARCH64 */ 1133 1134 static const ARMCPUInfo arm_tcg_cpus[] = { 1135 { .name = "arm926", .initfn = arm926_initfn }, 1136 { .name = "arm946", .initfn = arm946_initfn }, 1137 { .name = "arm1026", .initfn = arm1026_initfn }, 1138 /* 1139 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an 1140 * older core than plain "arm1136". In particular this does not 1141 * have the v6K features. 1142 */ 1143 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn }, 1144 { .name = "arm1136", .initfn = arm1136_initfn }, 1145 { .name = "arm1176", .initfn = arm1176_initfn }, 1146 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, 1147 { .name = "cortex-a7", .initfn = cortex_a7_initfn }, 1148 { .name = "cortex-a8", .initfn = cortex_a8_initfn }, 1149 { .name = "cortex-a9", .initfn = cortex_a9_initfn }, 1150 { .name = "cortex-a15", .initfn = cortex_a15_initfn }, 1151 { .name = "cortex-m0", .initfn = cortex_m0_initfn, 1152 .class_init = arm_v7m_class_init }, 1153 { .name = "cortex-m3", .initfn = cortex_m3_initfn, 1154 .class_init = arm_v7m_class_init }, 1155 { .name = "cortex-m4", .initfn = cortex_m4_initfn, 1156 .class_init = arm_v7m_class_init }, 1157 { .name = "cortex-m7", .initfn = cortex_m7_initfn, 1158 .class_init = arm_v7m_class_init }, 1159 { .name = "cortex-m33", .initfn = cortex_m33_initfn, 1160 .class_init = arm_v7m_class_init }, 1161 { .name = "cortex-m55", .initfn = cortex_m55_initfn, 1162 .class_init = arm_v7m_class_init }, 1163 { .name = "cortex-r5", .initfn = cortex_r5_initfn }, 1164 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, 1165 { .name = "ti925t", .initfn = ti925t_initfn }, 1166 { .name = "sa1100", .initfn = sa1100_initfn }, 1167 { .name = "sa1110", .initfn = sa1110_initfn }, 1168 { .name = "pxa250", .initfn = pxa250_initfn }, 1169 { .name = "pxa255", .initfn = pxa255_initfn }, 1170 { .name = "pxa260", .initfn = pxa260_initfn }, 1171 { .name = "pxa261", .initfn = pxa261_initfn }, 1172 { .name = "pxa262", .initfn = pxa262_initfn }, 1173 /* "pxa270" is an alias for "pxa270-a0" */ 1174 { .name = "pxa270", .initfn = pxa270a0_initfn }, 1175 { .name = "pxa270-a0", .initfn = pxa270a0_initfn }, 1176 { .name = "pxa270-a1", .initfn = pxa270a1_initfn }, 1177 { .name = "pxa270-b0", .initfn = pxa270b0_initfn }, 1178 { .name = "pxa270-b1", .initfn = pxa270b1_initfn }, 1179 { .name = "pxa270-c0", .initfn = pxa270c0_initfn }, 1180 { .name = "pxa270-c5", .initfn = pxa270c5_initfn }, 1181 #ifndef TARGET_AARCH64 1182 { .name = "max", .initfn = arm_max_initfn }, 1183 #endif 1184 #ifdef CONFIG_USER_ONLY 1185 { .name = "any", .initfn = arm_max_initfn }, 1186 #endif 1187 }; 1188 1189 static const TypeInfo idau_interface_type_info = { 1190 .name = TYPE_IDAU_INTERFACE, 1191 .parent = TYPE_INTERFACE, 1192 .class_size = sizeof(IDAUInterfaceClass), 1193 }; 1194 1195 static void arm_tcg_cpu_register_types(void) 1196 { 1197 size_t i; 1198 1199 type_register_static(&idau_interface_type_info); 1200 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { 1201 arm_cpu_register(&arm_tcg_cpus[i]); 1202 } 1203 } 1204 1205 type_init(arm_tcg_cpu_register_types) 1206 1207 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */