qemu

FORK: QEMU emulator
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host-signal.h (1831B)


      1 /*
      2  * host-signal.h: signal info dependent on the host architecture
      3  *
      4  * Copyright (c) 2003-2005 Fabrice Bellard
      5  * Copyright (c) 2021 Linaro Limited
      6  *
      7  * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
      8  * See the COPYING file in the top-level directory.
      9  */
     10 
     11 #ifndef MIPS_HOST_SIGNAL_H
     12 #define MIPS_HOST_SIGNAL_H
     13 
     14 /* The third argument to a SA_SIGINFO handler is ucontext_t. */
     15 typedef ucontext_t host_sigcontext;
     16 
     17 static inline uintptr_t host_signal_pc(host_sigcontext *uc)
     18 {
     19     return uc->uc_mcontext.pc;
     20 }
     21 
     22 static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
     23 {
     24     uc->uc_mcontext.pc = pc;
     25 }
     26 
     27 static inline void *host_signal_mask(host_sigcontext *uc)
     28 {
     29     return &uc->uc_sigmask;
     30 }
     31 
     32 #if defined(__misp16) || defined(__mips_micromips)
     33 #error "Unsupported encoding"
     34 #endif
     35 
     36 static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
     37 {
     38     uint32_t insn = *(uint32_t *)host_signal_pc(uc);
     39 
     40     /* Detect all store instructions at program counter. */
     41     switch ((insn >> 26) & 077) {
     42     case 050: /* SB */
     43     case 051: /* SH */
     44     case 052: /* SWL */
     45     case 053: /* SW */
     46     case 054: /* SDL */
     47     case 055: /* SDR */
     48     case 056: /* SWR */
     49     case 070: /* SC */
     50     case 071: /* SWC1 */
     51     case 074: /* SCD */
     52     case 075: /* SDC1 */
     53     case 077: /* SD */
     54 #if !defined(__mips_isa_rev) || __mips_isa_rev < 6
     55     case 072: /* SWC2 */
     56     case 076: /* SDC2 */
     57 #endif
     58         return true;
     59     case 023: /* COP1X */
     60         /*
     61          * Required in all versions of MIPS64 since
     62          * MIPS64r1 and subsequent versions of MIPS32r2.
     63          */
     64         switch (insn & 077) {
     65         case 010: /* SWXC1 */
     66         case 011: /* SDXC1 */
     67         case 015: /* SUXC1 */
     68             return true;
     69         }
     70         break;
     71     }
     72     return false;
     73 }
     74 
     75 #endif