qemu

FORK: QEMU emulator
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host-signal.h (2818B)


      1 /*
      2  * host-signal.h: signal info dependent on the host architecture
      3  *
      4  * Copyright (c) 2003-2005 Fabrice Bellard
      5  * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
      6  *
      7  * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
      8  * See the COPYING file in the top-level directory.
      9  */
     10 
     11 #ifndef LOONGARCH64_HOST_SIGNAL_H
     12 #define LOONGARCH64_HOST_SIGNAL_H
     13 
     14 /* The third argument to a SA_SIGINFO handler is ucontext_t. */
     15 typedef ucontext_t host_sigcontext;
     16 
     17 static inline uintptr_t host_signal_pc(host_sigcontext *uc)
     18 {
     19     return uc->uc_mcontext.__pc;
     20 }
     21 
     22 static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
     23 {
     24     uc->uc_mcontext.__pc = pc;
     25 }
     26 
     27 static inline void *host_signal_mask(host_sigcontext *uc)
     28 {
     29     return &uc->uc_sigmask;
     30 }
     31 
     32 static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
     33 {
     34     const uint32_t *pinsn = (const uint32_t *)host_signal_pc(uc);
     35     uint32_t insn = pinsn[0];
     36 
     37     /* Detect store by reading the instruction at the program counter.  */
     38     switch ((insn >> 26) & 0b111111) {
     39     case 0b001000: /* {ll,sc}.[wd] */
     40         switch ((insn >> 24) & 0b11) {
     41         case 0b01: /* sc.w */
     42         case 0b11: /* sc.d */
     43             return true;
     44         }
     45         break;
     46     case 0b001001: /* {ld,st}ox4.[wd] ({ld,st}ptr.[wd]) */
     47         switch ((insn >> 24) & 0b11) {
     48         case 0b01: /* stox4.w (stptr.w) */
     49         case 0b11: /* stox4.d (stptr.d) */
     50             return true;
     51         }
     52         break;
     53     case 0b001010: /* {ld,st}.* family */
     54         switch ((insn >> 22) & 0b1111) {
     55         case 0b0100: /* st.b */
     56         case 0b0101: /* st.h */
     57         case 0b0110: /* st.w */
     58         case 0b0111: /* st.d */
     59         case 0b1101: /* fst.s */
     60         case 0b1111: /* fst.d */
     61             return true;
     62         }
     63         break;
     64     case 0b001110: /* indexed, atomic, bounds-checking memory operations */
     65         switch ((insn >> 15) & 0b11111111111) {
     66         case 0b00000100000: /* stx.b */
     67         case 0b00000101000: /* stx.h */
     68         case 0b00000110000: /* stx.w */
     69         case 0b00000111000: /* stx.d */
     70         case 0b00001110000: /* fstx.s */
     71         case 0b00001111000: /* fstx.d */
     72         case 0b00011101100: /* fstgt.s */
     73         case 0b00011101101: /* fstgt.d */
     74         case 0b00011101110: /* fstle.s */
     75         case 0b00011101111: /* fstle.d */
     76         case 0b00011111000: /* stgt.b */
     77         case 0b00011111001: /* stgt.h */
     78         case 0b00011111010: /* stgt.w */
     79         case 0b00011111011: /* stgt.d */
     80         case 0b00011111100: /* stle.b */
     81         case 0b00011111101: /* stle.h */
     82         case 0b00011111110: /* stle.w */
     83         case 0b00011111111: /* stle.d */
     84         case 0b00011000000 ... 0b00011100011: /* am* insns */
     85             return true;
     86         }
     87         break;
     88     }
     89 
     90     return false;
     91 }
     92 
     93 #endif