ehci-regs.h (3894B)
1 #ifndef HW_USB_EHCI_REGS_H 2 #define HW_USB_EHCI_REGS_H 3 4 /* Capability Registers Base Address - section 2.2 */ 5 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ 6 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ 7 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */ 8 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */ 9 #define EECP HCCPARAMS + 1 10 #define HCSPPORTROUTE1 0x000c 11 #define HCSPPORTROUTE2 0x0010 12 13 #define USBCMD 0x0000 14 #define USBCMD_RUNSTOP (1 << 0) // run / Stop 15 #define USBCMD_HCRESET (1 << 1) // HC Reset 16 #define USBCMD_FLS (3 << 2) // Frame List Size 17 #define USBCMD_FLS_SH 2 // Frame List Size Shift 18 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable 19 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable 20 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell 21 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset 22 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count 23 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable 24 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control 25 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift 26 27 #define USBSTS 0x0004 28 #define USBSTS_RO_MASK 0x0000003f 29 #define USBSTS_INT (1 << 0) // USB Interrupt 30 #define USBSTS_ERRINT (1 << 1) // Error Interrupt 31 #define USBSTS_PCD (1 << 2) // Port Change Detect 32 #define USBSTS_FLR (1 << 3) // Frame List Rollover 33 #define USBSTS_HSE (1 << 4) // Host System Error 34 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance 35 #define USBSTS_HALT (1 << 12) // HC Halted 36 #define USBSTS_REC (1 << 13) // Reclamation 37 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status 38 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status 39 40 /* 41 * Interrupt enable bits correspond to the interrupt active bits in USBSTS 42 * so no need to redefine here. 43 */ 44 #define USBINTR 0x0008 45 #define USBINTR_MASK 0x0000003f 46 47 #define FRINDEX 0x000c 48 #define CTRLDSSEGMENT 0x0010 49 #define PERIODICLISTBASE 0x0014 50 #define ASYNCLISTADDR 0x0018 51 #define ASYNCLISTADDR_MASK 0xffffffe0 52 53 #define CONFIGFLAG 0x0040 54 55 /* 56 * Bits that are reserved or are read-only are masked out of values 57 * written to us by software 58 */ 59 #define PORTSC_RO_MASK 0x007001c0 60 #define PORTSC_RWC_MASK 0x0000002a 61 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable 62 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable 63 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable 64 #define PORTSC_PTC (15 << 16) // Port Test Control 65 #define PORTSC_PTC_SH 16 // Port Test Control shift 66 #define PORTSC_PIC (3 << 14) // Port Indicator Control 67 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift 68 #define PORTSC_POWNER (1 << 13) // Port Owner 69 #define PORTSC_PPOWER (1 << 12) // Port Power 70 #define PORTSC_LINESTAT (3 << 10) // Port Line Status 71 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift 72 #define PORTSC_PRESET (1 << 8) // Port Reset 73 #define PORTSC_SUSPEND (1 << 7) // Port Suspend 74 #define PORTSC_FPRES (1 << 6) // Force Port Resume 75 #define PORTSC_OCC (1 << 5) // Over Current Change 76 #define PORTSC_OCA (1 << 4) // Over Current Active 77 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change 78 #define PORTSC_PED (1 << 2) // Port Enable/Disable 79 #define PORTSC_CSC (1 << 1) // Connect Status Change 80 #define PORTSC_CONNECT (1 << 0) // Current Connect Status 81 82 #endif /* HW_USB_EHCI_REGS_H */