qemu

FORK: QEMU emulator
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xlnx-versal-ospi.h (3398B)

      1 /*
      2  * Header file for the Xilinx Versal's OSPI controller
      3  *
      4  * Copyright (C) 2021 Xilinx Inc
      5  * Written by Francisco Iglesias <francisco.iglesias@xilinx.com>
      6  *
      7  * Permission is hereby granted, free of charge, to any person obtaining a copy
      8  * of this software and associated documentation files (the "Software"), to deal
      9  * in the Software without restriction, including without limitation the rights
     10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     11  * copies of the Software, and to permit persons to whom the Software is
     12  * furnished to do so, subject to the following conditions:
     13  *
     14  * The above copyright notice and this permission notice shall be included in
     15  * all copies or substantial portions of the Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     23  * THE SOFTWARE.
     24  */
     25 
     26 /*
     27  * This is a model of Xilinx Versal's Octal SPI flash memory controller
     28  * documented in Versal's Technical Reference manual [1] and the Versal ACAP
     29  * Register reference [2].
     30  *
     31  * References:
     32  *
     33  * [1] Versal ACAP Technical Reference Manual,
     34  *     https://www.xilinx.com/support/documentation/architecture-manuals/am011-versal-acap-trm.pdf
     35  *
     36  * [2] Versal ACAP Register Reference,
     37  *     https://www.xilinx.com/html_docs/registers/am012/am012-versal-register-reference.html#mod___ospi.html
     38  *
     39  *
     40  * QEMU interface:
     41  * + sysbus MMIO region 0: MemoryRegion for the device's registers
     42  * + sysbus MMIO region 1: MemoryRegion for flash memory linear address space
     43  *   (data transfer).
     44  * + sysbus IRQ 0: Device interrupt.
     45  * + Named GPIO input "ospi-mux-sel": 0: enables indirect access mode
     46  *   and 1: enables direct access mode.
     47  * + Property "dac-with-indac": Allow both direct accesses and indirect
     48  *   accesses simultaneously.
     49  * + Property "indac-write-disabled": Disable indirect access writes.
     50  */
     51 
     52 #ifndef XLNX_VERSAL_OSPI_H
     53 #define XLNX_VERSAL_OSPI_H
     54 
     55 #include "hw/register.h"
     56 #include "hw/ssi/ssi.h"
     57 #include "qemu/fifo8.h"
     58 #include "hw/dma/xlnx_csu_dma.h"
     59 
     60 #define TYPE_XILINX_VERSAL_OSPI "xlnx.versal-ospi"
     61 
     62 OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalOspi, XILINX_VERSAL_OSPI)
     63 
     64 #define XILINX_VERSAL_OSPI_R_MAX (0xfc / 4 + 1)
     65 
     66 /*
     67  * Indirect operations
     68  */
     69 typedef struct IndOp {
     70     uint32_t flash_addr;
     71     uint32_t num_bytes;
     72     uint32_t done_bytes;
     73     bool completed;
     74 } IndOp;
     75 
     76 struct XlnxVersalOspi {
     77     SysBusDevice parent_obj;
     78 
     79     MemoryRegion iomem;
     80     MemoryRegion iomem_dac;
     81 
     82     uint8_t num_cs;
     83     qemu_irq *cs_lines;
     84 
     85     SSIBus *spi;
     86 
     87     Fifo8 rx_fifo;
     88     Fifo8 tx_fifo;
     89 
     90     Fifo8 rx_sram;
     91     Fifo8 tx_sram;
     92 
     93     qemu_irq irq;
     94 
     95     XlnxCSUDMA *dma_src;
     96     bool ind_write_disabled;
     97     bool dac_with_indac;
     98     bool dac_enable;
     99     bool src_dma_inprog;
    100 
    101     IndOp rd_ind_op[2];
    102     IndOp wr_ind_op[2];
    103 
    104     uint32_t regs[XILINX_VERSAL_OSPI_R_MAX];
    105     RegisterInfo regs_info[XILINX_VERSAL_OSPI_R_MAX];
    106 
    107     /* Maximum inferred membank size is 512 bytes */
    108     uint8_t stig_membank[512];
    109 };
    110 
    111 #endif /* XLNX_VERSAL_OSPI_H */