qemu

FORK: QEMU emulator
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aspeed_smc.h (3334B)

      1 /*
      2  * ASPEED AST2400 SMC Controller (SPI Flash Only)
      3  *
      4  * Copyright (C) 2016 IBM Corp.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a copy
      7  * of this software and associated documentation files (the "Software"), to deal
      8  * in the Software without restriction, including without limitation the rights
      9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10  * copies of the Software, and to permit persons to whom the Software is
     11  * furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22  * THE SOFTWARE.
     23  */
     24 
     25 #ifndef ASPEED_SMC_H
     26 #define ASPEED_SMC_H
     27 
     28 #include "hw/ssi/ssi.h"
     29 #include "hw/sysbus.h"
     30 #include "qom/object.h"
     31 
     32 struct AspeedSMCState;
     33 struct AspeedSMCClass;
     34 
     35 #define TYPE_ASPEED_SMC_FLASH "aspeed.smc.flash"
     36 OBJECT_DECLARE_SIMPLE_TYPE(AspeedSMCFlash, ASPEED_SMC_FLASH)
     37 struct AspeedSMCFlash {
     38     SysBusDevice parent_obj;
     39 
     40     struct AspeedSMCState *controller;
     41     struct AspeedSMCClass *asc;
     42     uint8_t cs;
     43 
     44     MemoryRegion mmio;
     45 };
     46 
     47 #define TYPE_ASPEED_SMC "aspeed.smc"
     48 OBJECT_DECLARE_TYPE(AspeedSMCState, AspeedSMCClass, ASPEED_SMC)
     49 
     50 #define ASPEED_SMC_R_MAX        (0x100 / 4)
     51 #define ASPEED_SMC_CS_MAX       5
     52 
     53 struct AspeedSMCState {
     54     SysBusDevice parent_obj;
     55 
     56     MemoryRegion mmio;
     57     MemoryRegion mmio_flash_container;
     58     MemoryRegion mmio_flash;
     59 
     60     qemu_irq irq;
     61 
     62     qemu_irq *cs_lines;
     63     bool inject_failure;
     64 
     65     SSIBus *spi;
     66 
     67     uint32_t regs[ASPEED_SMC_R_MAX];
     68 
     69     /* depends on the controller type */
     70     uint8_t r_conf;
     71     uint8_t r_ce_ctrl;
     72     uint8_t r_ctrl0;
     73     uint8_t r_timings;
     74     uint8_t conf_enable_w0;
     75 
     76     AddressSpace flash_as;
     77     MemoryRegion *dram_mr;
     78     AddressSpace dram_as;
     79 
     80     AspeedSMCFlash flashes[ASPEED_SMC_CS_MAX];
     81 
     82     uint8_t snoop_index;
     83     uint8_t snoop_dummies;
     84 };
     85 
     86 typedef struct AspeedSegments {
     87     hwaddr addr;
     88     uint32_t size;
     89 } AspeedSegments;
     90 
     91 struct AspeedSMCClass {
     92     SysBusDeviceClass parent_obj;
     93 
     94     uint8_t r_conf;
     95     uint8_t r_ce_ctrl;
     96     uint8_t r_ctrl0;
     97     uint8_t r_timings;
     98     uint8_t nregs_timings;
     99     uint8_t conf_enable_w0;
    100     uint8_t cs_num_max;
    101     const uint32_t *resets;
    102     const AspeedSegments *segments;
    103     uint32_t segment_addr_mask;
    104     hwaddr flash_window_base;
    105     uint32_t flash_window_size;
    106     uint32_t features;
    107     hwaddr dma_flash_mask;
    108     hwaddr dma_dram_mask;
    109     uint32_t nregs;
    110     uint32_t (*segment_to_reg)(const AspeedSMCState *s,
    111                                const AspeedSegments *seg);
    112     void (*reg_to_segment)(const AspeedSMCState *s, uint32_t reg,
    113                            AspeedSegments *seg);
    114     void (*dma_ctrl)(AspeedSMCState *s, uint32_t value);
    115     int (*addr_width)(const AspeedSMCState *s);
    116 };
    117 
    118 #endif /* ASPEED_SMC_H */