qemu

FORK: QEMU emulator
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npcm7xx_sdhci.h (1896B)


      1 /*
      2  * NPCM7xx SD-3.0 / eMMC-4.51 Host Controller
      3  *
      4  * Copyright (c) 2021 Google LLC
      5  *
      6  * This program is free software; you can redistribute it and/or modify it
      7  * under the terms of the GNU General Public License as published by the
      8  * Free Software Foundation; either version 2 of the License, or
      9  * (at your option) any later version.
     10  *
     11  * This program is distributed in the hope that it will be useful, but WITHOUT
     12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
     13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
     14  * for more details.
     15  */
     16 
     17 #ifndef NPCM7XX_SDHCI_H
     18 #define NPCM7XX_SDHCI_H
     19 
     20 #include "hw/sd/sdhci.h"
     21 #include "qom/object.h"
     22 
     23 #define TYPE_NPCM7XX_SDHCI "npcm7xx.sdhci"
     24 #define NPCM7XX_PRSTVALS_SIZE 6
     25 #define NPCM7XX_PRSTVALS 0x60
     26 #define NPCM7XX_PRSTVALS_0 0x0
     27 #define NPCM7XX_PRSTVALS_1 0x2
     28 #define NPCM7XX_PRSTVALS_2 0x4
     29 #define NPCM7XX_PRSTVALS_3 0x6
     30 #define NPCM7XX_PRSTVALS_4 0x8
     31 #define NPCM7XX_PRSTVALS_5 0xA
     32 #define NPCM7XX_BOOTTOCTRL 0x10
     33 #define NPCM7XX_SDHCI_REGSIZE 0x20
     34 
     35 #define NPCM7XX_PRSNTS_RESET 0x04A00000
     36 #define NPCM7XX_BLKGAP_RESET 0x80
     37 #define NPCM7XX_CAPAB_RESET 0x0100200161EE0399
     38 #define NPCM7XX_MAXCURR_RESET 0x0000000000000005
     39 #define NPCM7XX_HCVER_RESET 0x1002
     40 
     41 #define NPCM7XX_PRSTVALS_0_RESET 0x0040
     42 #define NPCM7XX_PRSTVALS_1_RESET 0x0001
     43 #define NPCM7XX_PRSTVALS_3_RESET 0x0001
     44 
     45 OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSDHCIState, NPCM7XX_SDHCI)
     46 
     47 typedef struct NPCM7xxRegs {
     48     /* Preset Values Register Field, read-only */
     49     uint16_t prstvals[NPCM7XX_PRSTVALS_SIZE];
     50     /* Boot Timeout Control Register, read-write */
     51     uint32_t boottoctrl;
     52 } NPCM7xxRegisters;
     53 
     54 typedef struct NPCM7xxSDHCIState {
     55     SysBusDevice parent;
     56 
     57     MemoryRegion container;
     58     MemoryRegion iomem;
     59     BusState *bus;
     60     NPCM7xxRegisters regs;
     61 
     62     SDHCIState sdhci;
     63 } NPCM7xxSDHCIState;
     64 
     65 #endif /* NPCM7XX_SDHCI_H */