qemu

FORK: QEMU emulator
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allwinner-sdhost.h (4177B)


      1 /*
      2  * Allwinner (sun4i and above) SD Host Controller emulation
      3  *
      4  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
      5  *
      6  * This program is free software: you can redistribute it and/or modify
      7  * it under the terms of the GNU General Public License as published by
      8  * the Free Software Foundation, either version 2 of the License, or
      9  * (at your option) any later version.
     10  *
     11  * This program is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     14  * GNU General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU General Public License
     17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
     18  */
     19 
     20 #ifndef HW_SD_ALLWINNER_SDHOST_H
     21 #define HW_SD_ALLWINNER_SDHOST_H
     22 
     23 #include "qom/object.h"
     24 #include "hw/sysbus.h"
     25 #include "hw/sd/sd.h"
     26 
     27 /**
     28  * Object model types
     29  * @{
     30  */
     31 
     32 /** Generic Allwinner SD Host Controller (abstract) */
     33 #define TYPE_AW_SDHOST "allwinner-sdhost"
     34 
     35 /** Allwinner sun4i family (A10, A12) */
     36 #define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
     37 
     38 /** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
     39 #define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
     40 
     41 /** @} */
     42 
     43 /**
     44  * Object model macros
     45  * @{
     46  */
     47 
     48 OBJECT_DECLARE_TYPE(AwSdHostState, AwSdHostClass, AW_SDHOST)
     49 
     50 /** @} */
     51 
     52 /**
     53  * Allwinner SD Host Controller object instance state.
     54  */
     55 struct AwSdHostState {
     56     /*< private >*/
     57     SysBusDevice busdev;
     58     /*< public >*/
     59 
     60     /** Secure Digital (SD) bus, which connects to SD card (if present) */
     61     SDBus sdbus;
     62 
     63     /** Maps I/O registers in physical memory */
     64     MemoryRegion iomem;
     65 
     66     /** Interrupt output signal to notify CPU */
     67     qemu_irq irq;
     68 
     69     /** Memory region where DMA transfers are done */
     70     MemoryRegion *dma_mr;
     71 
     72     /** Address space used internally for DMA transfers */
     73     AddressSpace dma_as;
     74 
     75     /** Number of bytes left in current DMA transfer */
     76     uint32_t transfer_cnt;
     77 
     78     /**
     79      * @name Hardware Registers
     80      * @{
     81      */
     82 
     83     uint32_t global_ctl;        /**< Global Control */
     84     uint32_t clock_ctl;         /**< Clock Control */
     85     uint32_t timeout;           /**< Timeout */
     86     uint32_t bus_width;         /**< Bus Width */
     87     uint32_t block_size;        /**< Block Size */
     88     uint32_t byte_count;        /**< Byte Count */
     89 
     90     uint32_t command;           /**< Command */
     91     uint32_t command_arg;       /**< Command Argument */
     92     uint32_t response[4];       /**< Command Response */
     93 
     94     uint32_t irq_mask;          /**< Interrupt Mask */
     95     uint32_t irq_status;        /**< Raw Interrupt Status */
     96     uint32_t status;            /**< Status */
     97 
     98     uint32_t fifo_wlevel;       /**< FIFO Water Level */
     99     uint32_t fifo_func_sel;     /**< FIFO Function Select */
    100     uint32_t debug_enable;      /**< Debug Enable */
    101     uint32_t auto12_arg;        /**< Auto Command 12 Argument */
    102     uint32_t newtiming_set;     /**< SD New Timing Set */
    103     uint32_t newtiming_debug;   /**< SD New Timing Debug */
    104     uint32_t hardware_rst;      /**< Hardware Reset */
    105     uint32_t dmac;              /**< Internal DMA Controller Control */
    106     uint32_t desc_base;         /**< Descriptor List Base Address */
    107     uint32_t dmac_status;       /**< Internal DMA Controller Status */
    108     uint32_t dmac_irq;          /**< Internal DMA Controller IRQ Enable */
    109     uint32_t card_threshold;    /**< Card Threshold Control */
    110     uint32_t startbit_detect;   /**< eMMC DDR Start Bit Detection Control */
    111     uint32_t response_crc;      /**< Response CRC */
    112     uint32_t data_crc[8];       /**< Data CRC */
    113     uint32_t status_crc;        /**< Status CRC */
    114 
    115     /** @} */
    116 
    117 };
    118 
    119 /**
    120  * Allwinner SD Host Controller class-level struct.
    121  *
    122  * This struct is filled by each sunxi device specific code
    123  * such that the generic code can use this struct to support
    124  * all devices.
    125  */
    126 struct AwSdHostClass {
    127     /*< private >*/
    128     SysBusDeviceClass parent_class;
    129     /*< public >*/
    130 
    131     /** Maximum buffer size in bytes per DMA descriptor */
    132     size_t max_desc_size;
    133     bool   is_sun4i;
    134 
    135 };
    136 
    137 #endif /* HW_SD_ALLWINNER_SDHOST_H */