sifive_e.h (2478B)
1 /* 2 * SiFive E series machine interface 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef HW_SIFIVE_E_H 20 #define HW_SIFIVE_E_H 21 22 #include "hw/riscv/riscv_hart.h" 23 #include "hw/riscv/sifive_cpu.h" 24 #include "hw/gpio/sifive_gpio.h" 25 #include "hw/boards.h" 26 27 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" 28 #define RISCV_E_SOC(obj) \ 29 OBJECT_CHECK(SiFiveESoCState, (obj), TYPE_RISCV_E_SOC) 30 31 typedef struct SiFiveESoCState { 32 /*< private >*/ 33 DeviceState parent_obj; 34 35 /*< public >*/ 36 RISCVHartArrayState cpus; 37 DeviceState *plic; 38 SIFIVEGPIOState gpio; 39 MemoryRegion xip_mem; 40 MemoryRegion mask_rom; 41 } SiFiveESoCState; 42 43 typedef struct SiFiveEState { 44 /*< private >*/ 45 MachineState parent_obj; 46 47 /*< public >*/ 48 SiFiveESoCState soc; 49 bool revb; 50 } SiFiveEState; 51 52 #define TYPE_RISCV_E_MACHINE MACHINE_TYPE_NAME("sifive_e") 53 #define RISCV_E_MACHINE(obj) \ 54 OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) 55 56 enum { 57 SIFIVE_E_DEV_DEBUG, 58 SIFIVE_E_DEV_MROM, 59 SIFIVE_E_DEV_OTP, 60 SIFIVE_E_DEV_CLINT, 61 SIFIVE_E_DEV_PLIC, 62 SIFIVE_E_DEV_AON, 63 SIFIVE_E_DEV_PRCI, 64 SIFIVE_E_DEV_OTP_CTRL, 65 SIFIVE_E_DEV_GPIO0, 66 SIFIVE_E_DEV_UART0, 67 SIFIVE_E_DEV_QSPI0, 68 SIFIVE_E_DEV_PWM0, 69 SIFIVE_E_DEV_UART1, 70 SIFIVE_E_DEV_QSPI1, 71 SIFIVE_E_DEV_PWM1, 72 SIFIVE_E_DEV_QSPI2, 73 SIFIVE_E_DEV_PWM2, 74 SIFIVE_E_DEV_XIP, 75 SIFIVE_E_DEV_DTIM 76 }; 77 78 enum { 79 SIFIVE_E_UART0_IRQ = 3, 80 SIFIVE_E_UART1_IRQ = 4, 81 SIFIVE_E_GPIO0_IRQ0 = 8 82 }; 83 84 #define SIFIVE_E_PLIC_HART_CONFIG "M" 85 #define SIFIVE_E_PLIC_NUM_SOURCES 127 86 #define SIFIVE_E_PLIC_NUM_PRIORITIES 7 87 #define SIFIVE_E_PLIC_PRIORITY_BASE 0x04 88 #define SIFIVE_E_PLIC_PENDING_BASE 0x1000 89 #define SIFIVE_E_PLIC_ENABLE_BASE 0x2000 90 #define SIFIVE_E_PLIC_ENABLE_STRIDE 0x80 91 #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 92 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 93 94 #endif