qemu

FORK: QEMU emulator
git clone https://git.neptards.moe/neptards/qemu.git
Log | Files | Refs | Submodules | LICENSE

ppc4xx.h (4381B)

      1 /*
      2  * QEMU PowerPC 4xx emulation shared definitions
      3  *
      4  * Copyright (c) 2007 Jocelyn Mayer
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a copy
      7  * of this software and associated documentation files (the "Software"), to deal
      8  * in the Software without restriction, including without limitation the rights
      9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
     10  * copies of the Software, and to permit persons to whom the Software is
     11  * furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
     19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
     22  * THE SOFTWARE.
     23  */
     24 
     25 #ifndef PPC4XX_H
     26 #define PPC4XX_H
     27 
     28 #include "hw/ppc/ppc.h"
     29 #include "exec/memory.h"
     30 #include "hw/sysbus.h"
     31 
     32 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost"
     33 
     34 /*
     35  * Generic DCR device
     36  */
     37 #define TYPE_PPC4xx_DCR_DEVICE "ppc4xx-dcr-device"
     38 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxDcrDeviceState, PPC4xx_DCR_DEVICE);
     39 struct Ppc4xxDcrDeviceState {
     40     SysBusDevice parent_obj;
     41 
     42     PowerPCCPU *cpu;
     43 };
     44 
     45 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque,
     46                          dcr_read_cb dcr_read, dcr_write_cb dcr_write);
     47 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu,
     48                         Error **errp);
     49 
     50 /* Memory Access Layer (MAL) */
     51 #define TYPE_PPC4xx_MAL "ppc4xx-mal"
     52 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxMalState, PPC4xx_MAL);
     53 struct Ppc4xxMalState {
     54     Ppc4xxDcrDeviceState parent_obj;
     55 
     56     qemu_irq irqs[4];
     57     uint32_t cfg;
     58     uint32_t esr;
     59     uint32_t ier;
     60     uint32_t txcasr;
     61     uint32_t txcarr;
     62     uint32_t txeobisr;
     63     uint32_t txdeir;
     64     uint32_t rxcasr;
     65     uint32_t rxcarr;
     66     uint32_t rxeobisr;
     67     uint32_t rxdeir;
     68     uint32_t *txctpr;
     69     uint32_t *rxctpr;
     70     uint32_t *rcbs;
     71     uint8_t  txcnum;
     72     uint8_t  rxcnum;
     73 };
     74 
     75 /* Peripheral local bus arbitrer */
     76 #define TYPE_PPC4xx_PLB "ppc4xx-plb"
     77 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxPlbState, PPC4xx_PLB);
     78 struct Ppc4xxPlbState {
     79     Ppc4xxDcrDeviceState parent_obj;
     80 
     81     uint32_t acr;
     82     uint32_t bear;
     83     uint32_t besr;
     84 };
     85 
     86 /* Peripheral controller */
     87 #define TYPE_PPC4xx_EBC "ppc4xx-ebc"
     88 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxEbcState, PPC4xx_EBC);
     89 struct Ppc4xxEbcState {
     90     Ppc4xxDcrDeviceState parent_obj;
     91 
     92     uint32_t addr;
     93     uint32_t bcr[8];
     94     uint32_t bap[8];
     95     uint32_t bear;
     96     uint32_t besr0;
     97     uint32_t besr1;
     98     uint32_t cfg;
     99 };
    100 
    101 /* SDRAM DDR controller */
    102 typedef struct {
    103     MemoryRegion ram;
    104     MemoryRegion container; /* used for clipping */
    105     hwaddr base;
    106     hwaddr size;
    107     uint32_t bcr;
    108 } Ppc4xxSdramBank;
    109 
    110 #define SDR0_DDR0_DDRM_ENCODE(n)  ((((unsigned long)(n)) & 0x03) << 29)
    111 #define SDR0_DDR0_DDRM_DDR1       0x20000000
    112 #define SDR0_DDR0_DDRM_DDR2       0x40000000
    113 
    114 #define TYPE_PPC4xx_SDRAM_DDR "ppc4xx-sdram-ddr"
    115 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdrState, PPC4xx_SDRAM_DDR);
    116 struct Ppc4xxSdramDdrState {
    117     Ppc4xxDcrDeviceState parent_obj;
    118 
    119     MemoryRegion *dram_mr;
    120     uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
    121     Ppc4xxSdramBank bank[4];
    122     qemu_irq irq;
    123 
    124     uint32_t addr;
    125     uint32_t besr0;
    126     uint32_t besr1;
    127     uint32_t bear;
    128     uint32_t cfg;
    129     uint32_t status;
    130     uint32_t rtr;
    131     uint32_t pmit;
    132     uint32_t tr;
    133     uint32_t ecccfg;
    134     uint32_t eccesr;
    135 };
    136 
    137 void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s);
    138 
    139 /* SDRAM DDR2 controller */
    140 #define TYPE_PPC4xx_SDRAM_DDR2 "ppc4xx-sdram-ddr2"
    141 OBJECT_DECLARE_SIMPLE_TYPE(Ppc4xxSdramDdr2State, PPC4xx_SDRAM_DDR2);
    142 struct Ppc4xxSdramDdr2State {
    143     Ppc4xxDcrDeviceState parent_obj;
    144 
    145     MemoryRegion *dram_mr;
    146     uint32_t nbanks; /* Banks to use from 4, e.g. when board has less slots */
    147     Ppc4xxSdramBank bank[4];
    148 
    149     uint32_t addr;
    150     uint32_t mcopt2;
    151 };
    152 
    153 void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s);
    154 
    155 #endif /* PPC4XX_H */