pnv_xscom.h (5715B)
1 /* 2 * QEMU PowerPC PowerNV XSCOM bus definitions 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_XSCOM_H 21 #define PPC_PNV_XSCOM_H 22 23 #include "qom/object.h" 24 25 typedef struct PnvXScomInterface PnvXScomInterface; 26 27 #define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface" 28 #define PNV_XSCOM_INTERFACE(obj) \ 29 INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE) 30 typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass; 31 DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE, 32 TYPE_PNV_XSCOM_INTERFACE) 33 34 struct PnvXScomInterfaceClass { 35 InterfaceClass parent; 36 int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset); 37 }; 38 39 /* 40 * Layout of the XSCOM PCB addresses of EX core 1 (POWER 8) 41 * 42 * GPIO 0x1100xxxx 43 * SCOM 0x1101xxxx 44 * OHA 0x1102xxxx 45 * CLOCK CTL 0x1103xxxx 46 * FIR 0x1104xxxx 47 * THERM 0x1105xxxx 48 * <reserved> 0x1106xxxx 49 * .. 50 * 0x110Exxxx 51 * PCB SLAVE 0x110Fxxxx 52 */ 53 54 #define PNV_XSCOM_EX_CORE_BASE 0x10000000ull 55 56 #define PNV_XSCOM_EX_BASE(core) \ 57 (PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24)) 58 #define PNV_XSCOM_EX_SIZE 0x100000 59 60 #define PNV_XSCOM_LPC_BASE 0xb0020 61 #define PNV_XSCOM_LPC_SIZE 0x4 62 63 #define PNV_XSCOM_PSIHB_BASE 0x2010900 64 #define PNV_XSCOM_PSIHB_SIZE 0x20 65 66 #define PNV_XSCOM_OCC_BASE 0x0066000 67 #define PNV_XSCOM_OCC_SIZE 0x6000 68 69 #define PNV_XSCOM_PBA_BASE 0x2013f00 70 #define PNV_XSCOM_PBA_SIZE 0x40 71 72 #define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000 73 #define PNV_XSCOM_PBCQ_NEST_SIZE 0x46 74 75 #define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000 76 #define PNV_XSCOM_PBCQ_PCI_SIZE 0x15 77 78 #define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00 79 #define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5 80 81 /* 82 * Layout of the XSCOM PCB addresses (POWER 9) 83 */ 84 #define PNV9_XSCOM_EC_BASE(core) \ 85 ((uint64_t)(((core) & 0x1F) + 0x20) << 24) 86 #define PNV9_XSCOM_EC_SIZE 0x100000 87 88 #define PNV9_XSCOM_EQ_BASE(core) \ 89 ((uint64_t)(((core) & 0x1C) + 0x40) << 22) 90 #define PNV9_XSCOM_EQ_SIZE 0x100000 91 92 #define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE 93 #define PNV9_XSCOM_OCC_SIZE 0x8000 94 95 #define PNV9_XSCOM_SBE_CTRL_BASE 0x00050008 96 #define PNV9_XSCOM_SBE_CTRL_SIZE 0x1 97 98 #define PNV9_XSCOM_SBE_MBOX_BASE 0x000D0050 99 #define PNV9_XSCOM_SBE_MBOX_SIZE 0x16 100 101 #define PNV9_XSCOM_PBA_BASE 0x5012b00 102 #define PNV9_XSCOM_PBA_SIZE 0x40 103 104 #define PNV9_XSCOM_PSIHB_BASE 0x5012900 105 #define PNV9_XSCOM_PSIHB_SIZE 0x100 106 107 #define PNV9_XSCOM_XIVE_BASE 0x5013000 108 #define PNV9_XSCOM_XIVE_SIZE 0x300 109 110 #define PNV9_XSCOM_PEC_NEST_BASE 0x4010c00 111 #define PNV9_XSCOM_PEC_NEST_SIZE 0x100 112 113 #define PNV9_XSCOM_PEC_PCI_BASE 0xd010800 114 #define PNV9_XSCOM_PEC_PCI_SIZE 0x200 115 116 /* XSCOM PCI "pass-through" window to PHB SCOM */ 117 #define PNV9_XSCOM_PEC_PCI_STK0 0x100 118 #define PNV9_XSCOM_PEC_PCI_STK1 0x140 119 #define PNV9_XSCOM_PEC_PCI_STK2 0x180 120 121 /* 122 * Layout of the XSCOM PCB addresses (POWER 10) 123 */ 124 #define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2)) 125 #define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24) 126 #define PNV10_XSCOM_EC(proc) \ 127 ((0x2 << 16) | ((1 << (3 - (proc))) << 12)) 128 129 #define PNV10_XSCOM_EQ_BASE(core) \ 130 ((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core))) 131 #define PNV10_XSCOM_EQ_SIZE 0x100000 132 133 #define PNV10_XSCOM_EC_BASE(core) \ 134 ((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3)) 135 #define PNV10_XSCOM_EC_SIZE 0x100000 136 137 #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 138 #define PNV10_XSCOM_PSIHB_SIZE 0x100 139 140 #define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE 141 #define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE 142 143 #define PNV10_XSCOM_SBE_CTRL_BASE PNV9_XSCOM_SBE_CTRL_BASE 144 #define PNV10_XSCOM_SBE_CTRL_SIZE PNV9_XSCOM_SBE_CTRL_SIZE 145 146 #define PNV10_XSCOM_SBE_MBOX_BASE PNV9_XSCOM_SBE_MBOX_BASE 147 #define PNV10_XSCOM_SBE_MBOX_SIZE PNV9_XSCOM_SBE_MBOX_SIZE 148 149 #define PNV10_XSCOM_PBA_BASE 0x01010CDA 150 #define PNV10_XSCOM_PBA_SIZE 0x40 151 152 #define PNV10_XSCOM_XIVE2_BASE 0x2010800 153 #define PNV10_XSCOM_XIVE2_SIZE 0x400 154 155 #define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */ 156 #define PNV10_XSCOM_PEC_NEST_SIZE 0x100 157 158 #define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */ 159 #define PNV10_XSCOM_PEC_PCI_SIZE 0x200 160 161 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); 162 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, 163 uint64_t xscom_base, uint64_t xscom_size, 164 const char *compat, int compat_size); 165 166 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, 167 MemoryRegion *mr); 168 void pnv_xscom_region_init(MemoryRegion *mr, 169 Object *owner, 170 const MemoryRegionOps *ops, 171 void *opaque, 172 const char *name, 173 uint64_t size); 174 175 #endif /* PPC_PNV_XSCOM_H */