qemu

FORK: QEMU emulator
git clone https://git.neptards.moe/neptards/qemu.git
Log | Files | Refs | Submodules | LICENSE

pnv_occ.h (1899B)


      1 /*
      2  * QEMU PowerPC PowerNV Emulation of a few OCC related registers
      3  *
      4  * Copyright (c) 2015-2022, IBM Corporation.
      5  *
      6  * This library is free software; you can redistribute it and/or
      7  * modify it under the terms of the GNU Lesser General Public
      8  * License as published by the Free Software Foundation; either
      9  * version 2.1 of the License, or (at your option) any later version.
     10  *
     11  * This library is distributed in the hope that it will be useful,
     12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     14  * Lesser General Public License for more details.
     15  *
     16  * You should have received a copy of the GNU Lesser General Public
     17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
     18  */
     19 
     20 #ifndef PPC_PNV_OCC_H
     21 #define PPC_PNV_OCC_H
     22 
     23 #include "qom/object.h"
     24 
     25 #define TYPE_PNV_OCC "pnv-occ"
     26 OBJECT_DECLARE_TYPE(PnvOCC, PnvOCCClass,
     27                     PNV_OCC)
     28 #define TYPE_PNV8_OCC TYPE_PNV_OCC "-POWER8"
     29 DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
     30                          TYPE_PNV8_OCC)
     31 #define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
     32 DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
     33                          TYPE_PNV9_OCC)
     34 #define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
     35 DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
     36 
     37 #define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
     38 #define PNV_OCC_SENSOR_DATA_BLOCK_SIZE   0x00025800
     39 
     40 struct PnvOCC {
     41     DeviceState xd;
     42 
     43     /* OCC Misc interrupt */
     44     uint64_t occmisc;
     45 
     46     qemu_irq psi_irq;
     47 
     48     MemoryRegion xscom_regs;
     49     MemoryRegion sram_regs;
     50 };
     51 
     52 struct PnvOCCClass {
     53     DeviceClass parent_class;
     54 
     55     int xscom_size;
     56     const MemoryRegionOps *xscom_ops;
     57 };
     58 
     59 #define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i)                               \
     60     (PNV_OCC_SENSOR_DATA_BLOCK_OFFSET + (i) * PNV_OCC_SENSOR_DATA_BLOCK_SIZE)
     61 
     62 #endif /* PPC_PNV_OCC_H */