pnv.h (12255B)
1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_PNV_H 21 #define PPC_PNV_H 22 23 #include "hw/boards.h" 24 #include "hw/sysbus.h" 25 #include "hw/ipmi/ipmi.h" 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv_pnor.h" 28 #include "hw/ppc/pnv_psi.h" 29 #include "hw/ppc/pnv_occ.h" 30 #include "hw/ppc/pnv_sbe.h" 31 #include "hw/ppc/pnv_homer.h" 32 #include "hw/ppc/pnv_xive.h" 33 #include "hw/ppc/pnv_core.h" 34 #include "hw/pci-host/pnv_phb3.h" 35 #include "hw/pci-host/pnv_phb4.h" 36 #include "hw/pci-host/pnv_phb.h" 37 #include "qom/object.h" 38 39 #define TYPE_PNV_CHIP "pnv-chip" 40 OBJECT_DECLARE_TYPE(PnvChip, PnvChipClass, 41 PNV_CHIP) 42 43 struct PnvChip { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 uint32_t chip_id; 49 uint64_t ram_start; 50 uint64_t ram_size; 51 52 uint32_t nr_cores; 53 uint32_t nr_threads; 54 uint64_t cores_mask; 55 PnvCore **cores; 56 57 uint32_t num_pecs; 58 59 MemoryRegion xscom_mmio; 60 MemoryRegion xscom; 61 AddressSpace xscom_as; 62 63 MemoryRegion *fw_mr; 64 gchar *dt_isa_nodename; 65 }; 66 67 #define TYPE_PNV8_CHIP "pnv8-chip" 68 typedef struct Pnv8Chip Pnv8Chip; 69 DECLARE_INSTANCE_CHECKER(Pnv8Chip, PNV8_CHIP, 70 TYPE_PNV8_CHIP) 71 72 struct Pnv8Chip { 73 /*< private >*/ 74 PnvChip parent_obj; 75 76 /*< public >*/ 77 MemoryRegion icp_mmio; 78 79 PnvLpcController lpc; 80 Pnv8Psi psi; 81 PnvOCC occ; 82 PnvHomer homer; 83 84 #define PNV8_CHIP_PHB3_MAX 4 85 /* 86 * The array is used to allow quick access to the phbs by 87 * pnv_ics_get_child() and pnv_ics_resend_child(). 88 */ 89 PnvPHB *phbs[PNV8_CHIP_PHB3_MAX]; 90 uint32_t num_phbs; 91 92 XICSFabric *xics; 93 }; 94 95 #define TYPE_PNV9_CHIP "pnv9-chip" 96 typedef struct Pnv9Chip Pnv9Chip; 97 DECLARE_INSTANCE_CHECKER(Pnv9Chip, PNV9_CHIP, 98 TYPE_PNV9_CHIP) 99 100 struct Pnv9Chip { 101 /*< private >*/ 102 PnvChip parent_obj; 103 104 /*< public >*/ 105 PnvXive xive; 106 Pnv9Psi psi; 107 PnvLpcController lpc; 108 PnvOCC occ; 109 PnvSBE sbe; 110 PnvHomer homer; 111 112 uint32_t nr_quads; 113 PnvQuad *quads; 114 115 #define PNV9_CHIP_MAX_PEC 3 116 PnvPhb4PecState pecs[PNV9_CHIP_MAX_PEC]; 117 }; 118 119 /* 120 * A SMT8 fused core is a pair of SMT4 cores. 121 */ 122 #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 123 #define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 124 125 #define TYPE_PNV10_CHIP "pnv10-chip" 126 typedef struct Pnv10Chip Pnv10Chip; 127 DECLARE_INSTANCE_CHECKER(Pnv10Chip, PNV10_CHIP, 128 TYPE_PNV10_CHIP) 129 130 struct Pnv10Chip { 131 /*< private >*/ 132 PnvChip parent_obj; 133 134 /*< public >*/ 135 PnvXive2 xive; 136 Pnv9Psi psi; 137 PnvLpcController lpc; 138 PnvOCC occ; 139 PnvSBE sbe; 140 PnvHomer homer; 141 142 uint32_t nr_quads; 143 PnvQuad *quads; 144 145 #define PNV10_CHIP_MAX_PEC 2 146 PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC]; 147 }; 148 149 #define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) 150 #define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) 151 152 struct PnvChipClass { 153 /*< private >*/ 154 SysBusDeviceClass parent_class; 155 156 /*< public >*/ 157 uint64_t chip_cfam_id; 158 uint64_t cores_mask; 159 uint32_t num_pecs; 160 uint32_t num_phbs; 161 162 DeviceRealize parent_realize; 163 164 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 165 void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); 166 void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); 167 void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); 168 void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); 169 ISABus *(*isa_create)(PnvChip *chip, Error **errp); 170 void (*dt_populate)(PnvChip *chip, void *fdt); 171 void (*pic_print_info)(PnvChip *chip, Monitor *mon); 172 uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); 173 uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); 174 }; 175 176 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP 177 #define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX 178 179 #define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1") 180 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E, 181 TYPE_PNV_CHIP_POWER8E) 182 183 #define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0") 184 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8, 185 TYPE_PNV_CHIP_POWER8) 186 187 #define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0") 188 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL, 189 TYPE_PNV_CHIP_POWER8NVL) 190 191 #define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0") 192 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9, 193 TYPE_PNV_CHIP_POWER9) 194 195 #define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0") 196 DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, 197 TYPE_PNV_CHIP_POWER10) 198 199 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); 200 201 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") 202 typedef struct PnvMachineClass PnvMachineClass; 203 typedef struct PnvMachineState PnvMachineState; 204 DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass, 205 PNV_MACHINE, TYPE_PNV_MACHINE) 206 207 208 struct PnvMachineClass { 209 /*< private >*/ 210 MachineClass parent_class; 211 212 /*< public >*/ 213 const char *compat; 214 int compat_size; 215 216 void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); 217 }; 218 219 struct PnvMachineState { 220 /*< private >*/ 221 MachineState parent_obj; 222 223 uint32_t initrd_base; 224 long initrd_size; 225 226 uint32_t num_chips; 227 PnvChip **chips; 228 229 ISABus *isa_bus; 230 uint32_t cpld_irqstate; 231 232 IPMIBmc *bmc; 233 Notifier powerdown_notifier; 234 235 PnvPnor *pnor; 236 237 hwaddr fw_load_addr; 238 }; 239 240 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); 241 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp); 242 243 #define PNV_FDT_ADDR 0x01000000 244 #define PNV_TIMEBASE_FREQ 512000000ULL 245 246 /* 247 * BMC helpers 248 */ 249 void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); 250 void pnv_bmc_powerdown(IPMIBmc *bmc); 251 IPMIBmc *pnv_bmc_create(PnvPnor *pnor); 252 IPMIBmc *pnv_bmc_find(Error **errp); 253 void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); 254 255 /* 256 * POWER8 MMIO base addresses 257 */ 258 #define PNV_XSCOM_SIZE 0x800000000ull 259 #define PNV_XSCOM_BASE(chip) \ 260 (0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 261 262 #define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 263 #define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull 264 #define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \ 265 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 266 267 #define PNV_HOMER_SIZE 0x0000000000400000ull 268 #define PNV_HOMER_BASE(chip) \ 269 (0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE) 270 271 272 /* 273 * XSCOM 0x20109CA defines the ICP BAR: 274 * 275 * 0:29 : bits 14 to 43 of address to define 1 MB region. 276 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 277 * 31:63 : Constant 0 278 * 279 * Usually defined as : 280 * 281 * 0xffffe00200000000 -> 0x0003ffff80000000 282 * 0xffffe00600000000 -> 0x0003ffff80100000 283 * 0xffffe02200000000 -> 0x0003ffff80800000 284 * 0xffffe02600000000 -> 0x0003ffff80900000 285 */ 286 #define PNV_ICP_SIZE 0x0000000000100000ull 287 #define PNV_ICP_BASE(chip) \ 288 (0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE) 289 290 291 #define PNV_PSIHB_SIZE 0x0000000000100000ull 292 #define PNV_PSIHB_BASE(chip) \ 293 (0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE) 294 295 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 296 #define PNV_PSIHB_FSP_BASE(chip) \ 297 (0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \ 298 PNV_PSIHB_FSP_SIZE) 299 300 /* 301 * POWER9 MMIO base addresses 302 */ 303 #define PNV9_CHIP_BASE(chip, base) \ 304 ((base) + ((uint64_t) (chip)->chip_id << 42)) 305 306 #define PNV9_XIVE_VC_SIZE 0x0000008000000000ull 307 #define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull) 308 309 #define PNV9_XIVE_PC_SIZE 0x0000001000000000ull 310 #define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull) 311 312 #define PNV9_LPCM_SIZE 0x0000000100000000ull 313 #define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull) 314 315 #define PNV9_PSIHB_SIZE 0x0000000000100000ull 316 #define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull) 317 318 #define PNV9_XIVE_IC_SIZE 0x0000000000080000ull 319 #define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull) 320 321 #define PNV9_XIVE_TM_SIZE 0x0000000000040000ull 322 #define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull) 323 324 #define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull 325 #define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull) 326 327 #define PNV9_XSCOM_SIZE 0x0000000400000000ull 328 #define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull) 329 330 #define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 331 #define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull 332 #define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \ 333 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 334 335 #define PNV9_HOMER_SIZE 0x0000000000400000ull 336 #define PNV9_HOMER_BASE(chip) \ 337 (0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE) 338 339 /* 340 * POWER10 MMIO base addresses - 16TB stride per chip 341 */ 342 #define PNV10_CHIP_BASE(chip, base) \ 343 ((base) + ((uint64_t) (chip)->chip_id << 44)) 344 345 #define PNV10_XSCOM_SIZE 0x0000000400000000ull 346 #define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull) 347 348 #define PNV10_LPCM_SIZE 0x0000000100000000ull 349 #define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull) 350 351 #define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull 352 #define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull) 353 354 #define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull 355 #define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull) 356 357 #define PNV10_PSIHB_SIZE 0x0000000000100000ull 358 #define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull) 359 360 #define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull 361 #define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull) 362 363 #define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull 364 #define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull) 365 366 #define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull 367 #define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull) 368 369 #define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull 370 #define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull) 371 372 #define PNV10_XIVE2_END_SIZE 0x0000020000000000ull 373 #define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull) 374 375 #define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull 376 #define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull 377 #define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \ 378 PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id)) 379 380 #define PNV10_HOMER_SIZE 0x0000000000400000ull 381 #define PNV10_HOMER_BASE(chip) \ 382 (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE) 383 384 #endif /* PPC_PNV_H */