pci_bridge.h (6685B)
1 /* 2 * QEMU PCI bridge 3 * 4 * Copyright (c) 2004 Fabrice Bellard 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 19 * 20 * split out pci bus specific stuff from pci.[hc] to pci_bridge.[hc] 21 * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> 22 * VA Linux Systems Japan K.K. 23 * 24 */ 25 26 #ifndef QEMU_PCI_BRIDGE_H 27 #define QEMU_PCI_BRIDGE_H 28 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/cxl/cxl.h" 32 #include "qom/object.h" 33 34 typedef struct PCIBridgeWindows PCIBridgeWindows; 35 36 /* 37 * Aliases for each of the address space windows that the bridge 38 * can forward. Mapped into the bridge's parent's address space, 39 * as subregions. 40 */ 41 struct PCIBridgeWindows { 42 MemoryRegion alias_pref_mem; 43 MemoryRegion alias_mem; 44 MemoryRegion alias_io; 45 /* 46 * When bridge control VGA forwarding is enabled, bridges will 47 * provide positive decode on the PCI VGA defined I/O port and 48 * MMIO ranges. When enabled forwarding is only qualified on the 49 * I/O and memory enable bits in the bridge command register. 50 */ 51 MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS]; 52 }; 53 54 #define TYPE_PCI_BRIDGE "base-pci-bridge" 55 OBJECT_DECLARE_SIMPLE_TYPE(PCIBridge, PCI_BRIDGE) 56 57 struct PCIBridge { 58 /*< private >*/ 59 PCIDevice parent_obj; 60 /*< public >*/ 61 62 /* private member */ 63 PCIBus sec_bus; 64 /* 65 * Memory regions for the bridge's address spaces. These regions are not 66 * directly added to system_memory/system_io or its descendants. 67 * Bridge's secondary bus points to these, so that devices 68 * under the bridge see these regions as its address spaces. 69 * The regions are as large as the entire address space - 70 * they don't take into account any windows. 71 */ 72 MemoryRegion address_space_mem; 73 MemoryRegion address_space_io; 74 75 PCIBridgeWindows *windows; 76 77 pci_map_irq_fn map_irq; 78 const char *bus_name; 79 }; 80 81 #define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr" 82 #define PCI_BRIDGE_DEV_PROP_MSI "msi" 83 #define PCI_BRIDGE_DEV_PROP_SHPC "shpc" 84 typedef struct CXLHost CXLHost; 85 86 struct PXBDev { 87 /*< private >*/ 88 PCIDevice parent_obj; 89 /*< public >*/ 90 91 uint8_t bus_nr; 92 uint16_t numa_node; 93 bool bypass_iommu; 94 struct cxl_dev { 95 CXLHost *cxl_host_bridge; /* Pointer to a CXLHost */ 96 } cxl; 97 }; 98 99 typedef struct PXBDev PXBDev; 100 #define TYPE_PXB_CXL_DEVICE "pxb-cxl" 101 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_CXL_DEV, 102 TYPE_PXB_CXL_DEVICE) 103 104 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset, 105 uint16_t svid, uint16_t ssid, 106 Error **errp); 107 108 PCIDevice *pci_bridge_get_device(PCIBus *bus); 109 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br); 110 111 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type); 112 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type); 113 114 void pci_bridge_update_mappings(PCIBridge *br); 115 void pci_bridge_write_config(PCIDevice *d, 116 uint32_t address, uint32_t val, int len); 117 void pci_bridge_disable_base_limit(PCIDevice *dev); 118 void pci_bridge_reset(DeviceState *qdev); 119 120 void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename); 121 void pci_bridge_exitfn(PCIDevice *pci_dev); 122 123 void pci_bridge_dev_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 124 Error **errp); 125 void pci_bridge_dev_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 126 Error **errp); 127 void pci_bridge_dev_unplug_request_cb(HotplugHandler *hotplug_dev, 128 DeviceState *dev, Error **errp); 129 130 /* 131 * before qdev initialization(qdev_init()), this function sets bus_name and 132 * map_irq callback which are necessary for pci_bridge_initfn() to 133 * initialize bus. 134 */ 135 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name, 136 pci_map_irq_fn map_irq); 137 138 /* TODO: add this define to pci_regs.h in linux and then in qemu. */ 139 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */ 140 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */ 141 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */ 142 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ 143 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ 144 145 typedef struct PCIBridgeQemuCap { 146 uint8_t id; /* Standard PCI capability header field */ 147 uint8_t next; /* Standard PCI capability header field */ 148 uint8_t len; /* Standard PCI vendor-specific capability header field */ 149 uint8_t type; /* Red Hat vendor-specific capability type. 150 Types are defined with REDHAT_PCI_CAP_ prefix */ 151 152 uint32_t bus_res; /* Minimum number of buses to reserve */ 153 uint64_t io; /* IO space to reserve */ 154 uint32_t mem; /* Non-prefetchable memory to reserve */ 155 /* At most one of the following two fields may be set to a value 156 * different from -1 */ 157 uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) */ 158 uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) */ 159 } PCIBridgeQemuCap; 160 161 #define REDHAT_PCI_CAP_TYPE_OFFSET 3 162 #define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 163 164 /* 165 * PCI BUS/IO/MEM/PREFMEM additional resources recorded as a 166 * capability in PCI configuration space to reserve on firmware init. 167 */ 168 typedef struct PCIResReserve { 169 uint32_t bus; 170 uint64_t io; 171 uint64_t mem_non_pref; 172 uint64_t mem_pref_32; 173 uint64_t mem_pref_64; 174 } PCIResReserve; 175 176 #define REDHAT_PCI_CAP_RES_RESERVE_BUS_RES 4 177 #define REDHAT_PCI_CAP_RES_RESERVE_IO 8 178 #define REDHAT_PCI_CAP_RES_RESERVE_MEM 16 179 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_32 20 180 #define REDHAT_PCI_CAP_RES_RESERVE_PREF_MEM_64 24 181 #define REDHAT_PCI_CAP_RES_RESERVE_CAP_SIZE 32 182 183 int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, 184 PCIResReserve res_reserve, Error **errp); 185 186 #endif /* QEMU_PCI_BRIDGE_H */