pnv_phb4_regs.h (23828B)
1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2013-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB4_REGS_H 11 #define PCI_HOST_PNV_PHB4_REGS_H 12 13 /* 14 * PEC XSCOM registers 15 * 16 * There a 3 PECs in P9. Each PEC can have several PHBs. Each PEC has some 17 * "global" registers and some "per-stack" (per-PHB) registers. Those are 18 * organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each 19 * range contains both some "PEC" registers and some "per-stack" registers. 20 * 21 * Finally the PCI range also contains an additional range per stack that 22 * passes through to some of the PHB own registers. 23 * 24 * PEC0 can contain 1 PHB (PHB0) 25 * PEC1 can contain 2 PHBs (PHB1 and PHB2) 26 * PEC2 can contain 3 PHBs (PHB3, PHB4 and PHB5) 27 */ 28 29 /* 30 * This is the "stack" offset, it's the offset from a given range base 31 * to the first "per-stack" registers and also the stride between 32 * stacks, thus for PEC2, the global registers are at offset 0, the 33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc.... 34 * 35 * It is *also* the offset to the pass-through SCOM region but in this case 36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc.. 37 */ 38 #define PEC_STACK_OFFSET 0x40 39 40 /* XSCOM Nest global registers */ 41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00 42 #define PEC_NEST_DROP_PRIO_CTRL 0x01 43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02 44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03 45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04 46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05 47 #define PEC_NEST_PBCQ_PRED_VEC_TIMEOUT 0x06 48 #define PEC_NEST_CAPP_CTRL 0x07 49 #define PEC_NEST_PBCQ_READ_STK_OVR 0x08 50 #define PEC_NEST_PBCQ_WRITE_STK_OVR 0x09 51 #define PEC_NEST_PBCQ_STORE_STK_OVR 0x0a 52 #define PEC_NEST_PBCQ_RETRY_BKOFF_CTRL 0x0b 53 54 /* XSCOM Nest per-stack registers */ 55 #define PEC_NEST_STK_PCI_NEST_FIR 0x00 56 #define PEC_NEST_STK_PCI_NEST_FIR_CLR 0x01 57 #define PEC_NEST_STK_PCI_NEST_FIR_SET 0x02 58 #define PEC_NEST_STK_PCI_NEST_FIR_MSK 0x03 59 #define PEC_NEST_STK_PCI_NEST_FIR_MSKC 0x04 60 #define PEC_NEST_STK_PCI_NEST_FIR_MSKS 0x05 61 #define PEC_NEST_STK_PCI_NEST_FIR_ACT0 0x06 62 #define PEC_NEST_STK_PCI_NEST_FIR_ACT1 0x07 63 #define PEC_NEST_STK_PCI_NEST_FIR_WOF 0x08 64 #define PEC_NEST_STK_ERR_REPORT_0 0x0a 65 #define PEC_NEST_STK_ERR_REPORT_1 0x0b 66 #define PEC_NEST_STK_PBCQ_GNRL_STATUS 0x0c 67 #define PEC_NEST_STK_PBCQ_MODE 0x0d 68 #define PEC_NEST_STK_MMIO_BAR0 0x0e 69 #define PEC_NEST_STK_MMIO_BAR0_MASK 0x0f 70 #define PEC_NEST_STK_MMIO_BAR1 0x10 71 #define PEC_NEST_STK_MMIO_BAR1_MASK 0x11 72 #define PEC_NEST_STK_PHB_REGS_BAR 0x12 73 #define PEC_NEST_STK_INT_BAR 0x13 74 #define PEC_NEST_STK_BAR_EN 0x14 75 #define PEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0) 76 #define PEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1) 77 #define PEC_NEST_STK_BAR_EN_PHB PPC_BIT(2) 78 #define PEC_NEST_STK_BAR_EN_INT PPC_BIT(3) 79 #define PEC_NEST_STK_DATA_FRZ_TYPE 0x15 80 #define PEC_NEST_STK_PBCQ_TUN_BAR 0x16 81 82 /* XSCOM PCI global registers */ 83 #define PEC_PCI_PBAIB_HW_CONFIG 0x00 84 #define PEC_PCI_PBAIB_READ_STK_OVR 0x02 85 86 /* XSCOM PCI per-stack registers */ 87 #define PEC_PCI_STK_PCI_FIR 0x00 88 #define PEC_PCI_STK_PCI_FIR_CLR 0x01 89 #define PEC_PCI_STK_PCI_FIR_SET 0x02 90 #define PEC_PCI_STK_PCI_FIR_MSK 0x03 91 #define PEC_PCI_STK_PCI_FIR_MSKC 0x04 92 #define PEC_PCI_STK_PCI_FIR_MSKS 0x05 93 #define PEC_PCI_STK_PCI_FIR_ACT0 0x06 94 #define PEC_PCI_STK_PCI_FIR_ACT1 0x07 95 #define PEC_PCI_STK_PCI_FIR_WOF 0x08 96 #define PEC_PCI_STK_ETU_RESET 0x0a 97 #define PEC_PCI_STK_PBAIB_ERR_REPORT 0x0b 98 #define PEC_PCI_STK_PBAIB_TX_CMD_CRED 0x0d 99 #define PEC_PCI_STK_PBAIB_TX_DAT_CRED 0x0e 100 101 /* 102 * PHB "SCOM" registers. This is accessed via the above window 103 * and provides a backdoor to the PHB when the AIB bus is not 104 * functional. Some of these directly map some of the PHB MMIO 105 * registers, some are specific and allow indirect access to a 106 * wider range of PHB registers 107 */ 108 #define PHB_SCOM_HV_IND_ADDR 0x00 109 #define PHB_SCOM_HV_IND_ADDR_VALID PPC_BIT(0) 110 #define PHB_SCOM_HV_IND_ADDR_4B PPC_BIT(1) 111 #define PHB_SCOM_HV_IND_ADDR_AUTOINC PPC_BIT(2) 112 #define PHB_SCOM_HV_IND_ADDR_ADDR PPC_BITMASK(51, 63) 113 #define PHB_SCOM_HV_IND_DATA 0x01 114 #define PHB_SCOM_ETU_LEM_FIR 0x08 115 #define PHB_SCOM_ETU_LEM_FIR_AND 0x09 116 #define PHB_SCOM_ETU_LEM_FIR_OR 0x0a 117 #define PHB_SCOM_ETU_LEM_FIR_MSK 0x0b 118 #define PHB_SCOM_ETU_LEM_ERR_MSK_AND 0x0c 119 #define PHB_SCOM_ETU_LEM_ERR_MSK_OR 0x0d 120 #define PHB_SCOM_ETU_LEM_ACT0 0x0e 121 #define PHB_SCOM_ETU_LEM_ACT1 0x0f 122 #define PHB_SCOM_ETU_LEM_WOF 0x10 123 #define PHB_SCOM_ETU_PMON_CONFIG 0x17 124 #define PHB_SCOM_ETU_PMON_CTR0 0x18 125 #define PHB_SCOM_ETU_PMON_CTR1 0x19 126 #define PHB_SCOM_ETU_PMON_CTR2 0x1a 127 #define PHB_SCOM_ETU_PMON_CTR3 0x1b 128 129 130 /* 131 * PHB MMIO registers 132 */ 133 134 /* PHB Fundamental register set A */ 135 #define PHB_LSI_SOURCE_ID 0x100 136 #define PHB_LSI_SRC_ID PPC_BITMASK(4, 12) 137 #define PHB_DMA_CHAN_STATUS 0x110 138 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 139 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 140 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 141 #define PHB_CPU_LOADSTORE_STATUS 0x120 142 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 143 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 144 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 145 #define PHB_CONFIG_DATA 0x130 146 #define PHB_LOCK0 0x138 147 #define PHB_CONFIG_ADDRESS 0x140 148 #define PHB_CA_ENABLE PPC_BIT(0) 149 #define PHB_CA_STATUS PPC_BITMASK(1, 3) 150 #define PHB_CA_STATUS_GOOD 0 151 #define PHB_CA_STATUS_UR 1 152 #define PHB_CA_STATUS_CRS 2 153 #define PHB_CA_STATUS_CA 4 154 #define PHB_CA_BUS PPC_BITMASK(4, 11) 155 #define PHB_CA_DEV PPC_BITMASK(12, 16) 156 #define PHB_CA_FUNC PPC_BITMASK(17, 19) 157 #define PHB_CA_BDFN PPC_BITMASK(4, 19) /* bus,dev,func */ 158 #define PHB_CA_REG PPC_BITMASK(20, 31) 159 #define PHB_CA_PE PPC_BITMASK(39, 47) 160 #define PHB_LOCK1 0x148 161 #define PHB_PHB4_CONFIG 0x160 162 #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8) 163 #define PHB_PHB4C_64BIT_MSI_EN PPC_BIT(14) 164 #define PHB_RTT_BAR 0x168 165 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 166 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(8, 46) 167 #define PHB_PELTV_BAR 0x188 168 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 169 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8, 50) 170 #define PHB_M32_START_ADDR 0x1a0 171 #define PHB_PEST_BAR 0x1a8 172 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 173 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8, 51) 174 #define PHB_ASN_CMPM 0x1C0 175 #define PHB_ASN_CMPM_ENABLE PPC_BIT(63) 176 #define PHB_CAPI_CMPM 0x1C8 177 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) 178 #define PHB_M64_AOMASK 0x1d0 179 #define PHB_M64_UPPER_BITS 0x1f0 180 #define PHB_NXLATE_PREFIX 0x1f8 181 #define PHB_DMARD_SYNC 0x200 182 #define PHB_DMARD_SYNC_START PPC_BIT(0) 183 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 184 #define PHB_RTC_INVALIDATE 0x208 185 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 186 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) 187 #define PHB_TCE_KILL 0x210 188 #define PHB_TCE_KILL_ALL PPC_BIT(0) 189 #define PHB_TCE_KILL_PE PPC_BIT(1) 190 #define PHB_TCE_KILL_ONE PPC_BIT(2) 191 #define PHB_TCE_KILL_PSEL PPC_BIT(3) 192 #define PHB_TCE_KILL_64K 0x1000 /* Address override */ 193 #define PHB_TCE_KILL_2M 0x2000 /* Address override */ 194 #define PHB_TCE_KILL_1G 0x3000 /* Address override */ 195 #define PHB_TCE_KILL_PENUM PPC_BITMASK(55, 63) 196 #define PHB_TCE_SPEC_CTL 0x218 197 #define PHB_IODA_ADDR 0x220 198 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 199 #define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15) 200 #define PHB_IODA_AD_MIST_PWV PPC_BITMASK(28, 31) 201 #define PHB_IODA_AD_TADR PPC_BITMASK(54, 63) 202 #define PHB_IODA_DATA0 0x228 203 #define PHB_PHB4_GEN_CAP 0x250 204 #define PHB_PHB4_TCE_CAP 0x258 205 #define PHB_PHB4_IRQ_CAP 0x260 206 #define PHB_PHB4_EEH_CAP 0x268 207 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 208 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 209 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 210 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 211 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 212 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 213 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 214 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 215 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 216 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16, 63) 217 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 218 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4, 11) 219 #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4, 19) 220 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63) 221 #define PHB_ETU_ERR_SUMMARY 0x2c8 222 #define PHB_INT_NOTIFY_ADDR 0x300 223 #define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */ 224 #define PHB_INT_NOTIFY_INDEX 0x308 225 226 /* Fundamental register set B */ 227 #define PHB_VERSION 0x800 228 #define PHB_CTRLR 0x810 229 #define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */ 230 #define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */ 231 #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) 232 #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) 233 #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) 234 #define PHB_CTRLR_MMIO_EEH_DISABLE PPC_BIT(14) 235 #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15) 236 #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16) 237 #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17, 19) 238 #define TVT_DD1_1_PER_PE 0 239 #define TVT_DD1_2_PER_PE 1 240 #define TVT_DD1_4_PER_PE 2 241 #define TVT_DD1_8_PER_PE 3 242 #define TVT_DD1_16_PER_PE 4 243 #define TVT_2_PER_PE 0 244 #define TVT_4_PER_PE 1 245 #define TVT_8_PER_PE 2 246 #define TVT_16_PER_PE 3 247 #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28, 31) 248 #define PHB_AIB_FENCE_CTRL 0x860 249 #define PHB_TCE_TAG_ENABLE 0x868 250 #define PHB_TCE_WATERMARK 0x870 251 #define PHB_TIMEOUT_CTRL1 0x878 252 #define PHB_TIMEOUT_CTRL2 0x880 253 #define PHB_Q_DMA_R 0x888 254 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 255 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 256 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 257 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 258 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 259 #define PHB_Q_DMA_R_TCE_KILL_STATUS PPC_BIT(7) 260 #define PHB_TCE_TAG_STATUS 0x908 261 262 /* FIR & Error registers */ 263 #define PHB_LEM_FIR_ACCUM 0xc00 264 #define PHB_LEM_FIR_AND_MASK 0xc08 265 #define PHB_LEM_FIR_OR_MASK 0xc10 266 #define PHB_LEM_ERROR_MASK 0xc18 267 #define PHB_LEM_ERROR_AND_MASK 0xc20 268 #define PHB_LEM_ERROR_OR_MASK 0xc28 269 #define PHB_LEM_ACTION0 0xc30 270 #define PHB_LEM_ACTION1 0xc38 271 #define PHB_LEM_WOF 0xc40 272 #define PHB_ERR_STATUS 0xc80 273 #define PHB_ERR1_STATUS 0xc88 274 #define PHB_ERR_INJECT 0xc90 275 #define PHB_ERR_LEM_ENABLE 0xc98 276 #define PHB_ERR_IRQ_ENABLE 0xca0 277 #define PHB_ERR_FREEZE_ENABLE 0xca8 278 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 279 #define PHB_ERR_LOG_0 0xcc0 280 #define PHB_ERR_LOG_1 0xcc8 281 #define PHB_ERR_STATUS_MASK 0xcd0 282 #define PHB_ERR1_STATUS_MASK 0xcd8 283 284 #define PHB_TXE_ERR_STATUS 0xd00 285 #define PHB_TXE_ERR1_STATUS 0xd08 286 #define PHB_TXE_ERR_INJECT 0xd10 287 #define PHB_TXE_ERR_LEM_ENABLE 0xd18 288 #define PHB_TXE_ERR_IRQ_ENABLE 0xd20 289 #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28 290 #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30 291 #define PHB_TXE_ERR_LOG_0 0xd40 292 #define PHB_TXE_ERR_LOG_1 0xd48 293 #define PHB_TXE_ERR_STATUS_MASK 0xd50 294 #define PHB_TXE_ERR1_STATUS_MASK 0xd58 295 296 #define PHB_RXE_ARB_ERR_STATUS 0xd80 297 #define PHB_RXE_ARB_ERR1_STATUS 0xd88 298 #define PHB_RXE_ARB_ERR_INJECT 0xd90 299 #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98 300 #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0 301 #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8 302 #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0 303 #define PHB_RXE_ARB_ERR_LOG_0 0xdc0 304 #define PHB_RXE_ARB_ERR_LOG_1 0xdc8 305 #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0 306 #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8 307 308 #define PHB_RXE_MRG_ERR_STATUS 0xe00 309 #define PHB_RXE_MRG_ERR1_STATUS 0xe08 310 #define PHB_RXE_MRG_ERR_INJECT 0xe10 311 #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18 312 #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20 313 #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28 314 #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30 315 #define PHB_RXE_MRG_ERR_LOG_0 0xe40 316 #define PHB_RXE_MRG_ERR_LOG_1 0xe48 317 #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50 318 #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58 319 320 #define PHB_RXE_TCE_ERR_STATUS 0xe80 321 #define PHB_RXE_TCE_ERR1_STATUS 0xe88 322 #define PHB_RXE_TCE_ERR_INJECT 0xe90 323 #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98 324 #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0 325 #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8 326 #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0 327 #define PHB_RXE_TCE_ERR_LOG_0 0xec0 328 #define PHB_RXE_TCE_ERR_LOG_1 0xec8 329 #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0 330 #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8 331 332 /* Performance monitor & Debug registers */ 333 #define PHB_TRACE_CONTROL 0xf80 334 #define PHB_PERFMON_CONFIG 0xf88 335 #define PHB_PERFMON_CTR0 0xf90 336 #define PHB_PERFMON_CTR1 0xf98 337 #define PHB_PERFMON_CTR2 0xfa0 338 #define PHB_PERFMON_CTR3 0xfa8 339 340 /* Root complex config space memory mapped */ 341 #define PHB_RC_CONFIG_BASE 0x1000 342 #define PHB_RC_CONFIG_SIZE 0x800 343 344 /* PHB4 REGB registers */ 345 346 /* PBL core */ 347 #define PHB_PBL_CONTROL 0x1800 348 #define PHB_PBL_TIMEOUT_CTRL 0x1810 349 #define PHB_PBL_NPTAG_ENABLE 0x1820 350 #define PHB_PBL_NBW_CMP_MASK 0x1830 351 #define PHB_PBL_NBW_MASK_ENABLE PPC_BIT(63) 352 #define PHB_PBL_SYS_LINK_INIT 0x1838 353 #define PHB_PBL_BUF_STATUS 0x1840 354 #define PHB_PBL_ERR_STATUS 0x1900 355 #define PHB_PBL_ERR1_STATUS 0x1908 356 #define PHB_PBL_ERR_INJECT 0x1910 357 #define PHB_PBL_ERR_INF_ENABLE 0x1920 358 #define PHB_PBL_ERR_ERC_ENABLE 0x1928 359 #define PHB_PBL_ERR_FAT_ENABLE 0x1930 360 #define PHB_PBL_ERR_LOG_0 0x1940 361 #define PHB_PBL_ERR_LOG_1 0x1948 362 #define PHB_PBL_ERR_STATUS_MASK 0x1950 363 #define PHB_PBL_ERR1_STATUS_MASK 0x1958 364 365 /* PCI-E stack */ 366 #define PHB_PCIE_SCR 0x1A00 367 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) 368 #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) 369 370 371 #define PHB_PCIE_CRESET 0x1A10 372 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) 373 #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) 374 #define PHB_PCIE_CRESET_PBL PPC_BIT(2) 375 #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) 376 #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) 377 378 379 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 380 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) 381 382 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 383 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) 384 #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36, 39) 385 #define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24, 27) 386 #define PHB_PCIE_DLP_LTSSM_RESET 0 387 #define PHB_PCIE_DLP_LTSSM_DETECT 1 388 #define PHB_PCIE_DLP_LTSSM_POLLING 2 389 #define PHB_PCIE_DLP_LTSSM_CONFIG 3 390 #define PHB_PCIE_DLP_LTSSM_L0 4 391 #define PHB_PCIE_DLP_LTSSM_REC 5 392 #define PHB_PCIE_DLP_LTSSM_L1 6 393 #define PHB_PCIE_DLP_LTSSM_L2 7 394 #define PHB_PCIE_DLP_LTSSM_HOTRESET 8 395 #define PHB_PCIE_DLP_LTSSM_DISABLED 9 396 #define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 397 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) 398 #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) 399 #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) 400 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 401 402 #define PHB_PCIE_DLP_CTL 0x1A78 403 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) 404 #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) 405 406 #define PHB_PCIE_DLP_TRWCTL 0x1A80 407 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) 408 409 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 410 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 411 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 412 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 413 414 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 415 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 416 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 417 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 418 #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 419 #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 420 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ 421 #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ 422 #define PHB_PCIE_TRACE_CTRL 0x1B20 423 #define PHB_PCIE_MISC_STRAP 0x1B30 424 425 /* Error */ 426 #define PHB_REGB_ERR_STATUS 0x1C00 427 #define PHB_REGB_ERR1_STATUS 0x1C08 428 #define PHB_REGB_ERR_INJECT 0x1C10 429 #define PHB_REGB_ERR_INF_ENABLE 0x1C20 430 #define PHB_REGB_ERR_ERC_ENABLE 0x1C28 431 #define PHB_REGB_ERR_FAT_ENABLE 0x1C30 432 #define PHB_REGB_ERR_LOG_0 0x1C40 433 #define PHB_REGB_ERR_LOG_1 0x1C48 434 #define PHB_REGB_ERR_STATUS_MASK 0x1C50 435 #define PHB_REGB_ERR1_STATUS_MASK 0x1C58 436 437 /* 438 * IODA3 on-chip tables 439 */ 440 441 #define IODA3_TBL_LIST 1 442 #define IODA3_TBL_MIST 2 443 #define IODA3_TBL_RCAM 5 444 #define IODA3_TBL_MRT 6 445 #define IODA3_TBL_PESTA 7 446 #define IODA3_TBL_PESTB 8 447 #define IODA3_TBL_TVT 9 448 #define IODA3_TBL_TCR 10 449 #define IODA3_TBL_TDR 11 450 #define IODA3_TBL_MBT 16 451 #define IODA3_TBL_MDT 17 452 #define IODA3_TBL_PEEV 20 453 454 /* LIST */ 455 #define IODA3_LIST_P PPC_BIT(6) 456 #define IODA3_LIST_Q PPC_BIT(7) 457 #define IODA3_LIST_STATE PPC_BIT(14) 458 459 /* MIST */ 460 #define IODA3_MIST_P3 PPC_BIT(48 + 0) 461 #define IODA3_MIST_Q3 PPC_BIT(48 + 1) 462 #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15) 463 464 /* TVT */ 465 #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0, 47) 466 #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48, 50) 467 #define IODA3_TVE_1_LEVEL 0 468 #define IODA3_TVE_2_LEVELS 1 469 #define IODA3_TVE_3_LEVELS 2 470 #define IODA3_TVE_4_LEVELS 3 471 #define IODA3_TVE_5_LEVELS 4 472 #define IODA3_TVT_TCE_TABLE_SIZE PPC_BITMASK(51, 55) 473 #define IODA3_TVT_NON_TRANSLATE_50 PPC_BIT(56) 474 #define IODA3_TVT_IO_PSIZE PPC_BITMASK(59, 63) 475 476 /* PESTA */ 477 #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0) 478 #define IODA3_PESTA_TRANS_TYPE PPC_BITMASK(5, 7) 479 #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4 480 #define IODA3_PESTA_CA_CMPLT_TMT PPC_BIT(8) 481 #define IODA3_PESTA_UR PPC_BIT(9) 482 483 /* PESTB */ 484 #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0) 485 486 /* MDT */ 487 /* FIXME: check this field with Eric and add a B, C and D */ 488 #define IODA3_MDT_PE_A PPC_BITMASK(0, 15) 489 #define IODA3_MDT_PE_B PPC_BITMASK(16, 31) 490 #define IODA3_MDT_PE_C PPC_BITMASK(32, 47) 491 #define IODA3_MDT_PE_D PPC_BITMASK(48, 63) 492 493 /* MBT */ 494 #define IODA3_MBT0_ENABLE PPC_BIT(0) 495 #define IODA3_MBT0_TYPE PPC_BIT(1) 496 #define IODA3_MBT0_TYPE_M32 IODA3_MBT0_TYPE 497 #define IODA3_MBT0_TYPE_M64 0 498 #define IODA3_MBT0_MODE PPC_BITMASK(2, 3) 499 #define IODA3_MBT0_MODE_PE_SEG 0 500 #define IODA3_MBT0_MODE_MDT 1 501 #define IODA3_MBT0_MODE_SINGLE_PE 2 502 #define IODA3_MBT0_SEG_DIV PPC_BITMASK(4, 5) 503 #define IODA3_MBT0_SEG_DIV_MAX 0 504 #define IODA3_MBT0_SEG_DIV_128 1 505 #define IODA3_MBT0_SEG_DIV_64 2 506 #define IODA3_MBT0_SEG_DIV_8 3 507 #define IODA3_MBT0_MDT_COLUMN PPC_BITMASK(4, 5) 508 #define IODA3_MBT0_BASE_ADDR PPC_BITMASK(8, 51) 509 510 #define IODA3_MBT1_ENABLE PPC_BIT(0) 511 #define IODA3_MBT1_MASK PPC_BITMASK(8, 51) 512 #define IODA3_MBT1_SEG_BASE PPC_BITMASK(55, 63) 513 #define IODA3_MBT1_SINGLE_PE_NUM PPC_BITMASK(55, 63) 514 515 /* 516 * IODA3 in-memory tables 517 */ 518 519 /* 520 * PEST 521 * 522 * 2x8 bytes entries, PEST0 and PEST1 523 */ 524 525 #define IODA3_PEST0_MMIO_CAUSE PPC_BIT(2) 526 #define IODA3_PEST0_CFG_READ PPC_BIT(3) 527 #define IODA3_PEST0_CFG_WRITE PPC_BIT(4) 528 #define IODA3_PEST0_TTYPE PPC_BITMASK(5, 7) 529 #define PEST_TTYPE_DMA_WRITE 0 530 #define PEST_TTYPE_MSI 1 531 #define PEST_TTYPE_DMA_READ 2 532 #define PEST_TTYPE_DMA_READ_RESP 3 533 #define PEST_TTYPE_MMIO_LOAD 4 534 #define PEST_TTYPE_MMIO_STORE 5 535 #define PEST_TTYPE_OTHER 7 536 #define IODA3_PEST0_CA_RETURN PPC_BIT(8) 537 #define IODA3_PEST0_UR_RETURN PPC_BIT(9) 538 #define IODA3_PEST0_PCIE_NONFATAL PPC_BIT(10) 539 #define IODA3_PEST0_PCIE_FATAL PPC_BIT(11) 540 #define IODA3_PEST0_PARITY_UE PPC_BIT(13) 541 #define IODA3_PEST0_PCIE_CORRECTABLE PPC_BIT(14) 542 #define IODA3_PEST0_PCIE_INTERRUPT PPC_BIT(15) 543 #define IODA3_PEST0_MMIO_XLATE PPC_BIT(16) 544 #define IODA3_PEST0_IODA3_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 545 #define IODA3_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 546 #define IODA3_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 547 #define IODA3_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 548 #define IODA3_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 549 #define IODA3_PEST0_LEM_BIT PPC_BITMASK(26, 31) 550 #define IODA3_PEST0_RID PPC_BITMASK(32, 47) 551 #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48, 63) 552 553 #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) 554 555 556 #endif /* PCI_HOST_PNV_PHB4_REGS_H */