pnv_phb3_regs.h (18289B)
1 /* 2 * QEMU PowerPC PowerNV (POWER8) PHB3 model 3 * 4 * Copyright (c) 2013-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef PCI_HOST_PNV_PHB3_REGS_H 11 #define PCI_HOST_PNV_PHB3_REGS_H 12 13 #include "qemu/host-utils.h" 14 15 /* 16 * PBCQ XSCOM registers 17 */ 18 19 #define PBCQ_NEST_IRSN_COMPARE 0x1a 20 #define PBCQ_NEST_IRSN_COMP PPC_BITMASK(0, 18) 21 #define PBCQ_NEST_IRSN_MASK 0x1b 22 #define PBCQ_NEST_LSI_SRC_ID 0x1f 23 #define PBCQ_NEST_LSI_SRC PPC_BITMASK(0, 7) 24 #define PBCQ_NEST_REGS_COUNT 0x46 25 #define PBCQ_NEST_MMIO_BAR0 0x40 26 #define PBCQ_NEST_MMIO_BAR1 0x41 27 #define PBCQ_NEST_PHB_BAR 0x42 28 #define PBCQ_NEST_MMIO_MASK0 0x43 29 #define PBCQ_NEST_MMIO_MASK1 0x44 30 #define PBCQ_NEST_BAR_EN 0x45 31 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0) 32 #define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1) 33 #define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2) 34 #define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3) 35 #define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4) 36 37 #define PBCQ_PCI_REGS_COUNT 0x15 38 #define PBCQ_PCI_BAR2 0x0b 39 40 #define PBCQ_SPCI_REGS_COUNT 0x5 41 #define PBCQ_SPCI_ASB_ADDR 0x0 42 #define PBCQ_SPCI_ASB_STATUS 0x1 43 #define PBCQ_SPCI_ASB_DATA 0x2 44 #define PBCQ_SPCI_AIB_CAPP_EN 0x3 45 #define PBCQ_SPCI_CAPP_SEC_TMR 0x4 46 47 /* 48 * PHB MMIO registers 49 */ 50 51 /* PHB Fundamental register set A */ 52 #define PHB_LSI_SOURCE_ID 0x100 53 #define PHB_LSI_SRC_ID PPC_BITMASK(5, 12) 54 #define PHB_DMA_CHAN_STATUS 0x110 55 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 56 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 57 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 58 #define PHB_CPU_LOADSTORE_STATUS 0x120 59 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 60 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 61 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 62 #define PHB_DMA_MSI_NODE_ID 0x128 63 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) 64 #define PHB_DMAMSI_NID PPC_BITMASK(24, 31) 65 #define PHB_CONFIG_DATA 0x130 66 #define PHB_LOCK0 0x138 67 #define PHB_CONFIG_ADDRESS 0x140 68 #define PHB_CA_ENABLE PPC_BIT(0) 69 #define PHB_CA_BUS PPC_BITMASK(4, 11) 70 #define PHB_CA_DEV PPC_BITMASK(12, 16) 71 #define PHB_CA_FUNC PPC_BITMASK(17, 19) 72 #define PHB_CA_REG PPC_BITMASK(20, 31) 73 #define PHB_CA_PE PPC_BITMASK(40, 47) 74 #define PHB_LOCK1 0x148 75 #define PHB_IVT_BAR 0x150 76 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) 77 #define PHB_IVT_BASE_ADDRESS_MASK PPC_BITMASK(14, 48) 78 #define PHB_IVT_LENGTH_MASK PPC_BITMASK(52, 63) 79 #define PHB_RBA_BAR 0x158 80 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) 81 #define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14, 55) 82 #define PHB_PHB3_CONFIG 0x160 83 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2) 84 #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8) 85 #define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14) 86 #define PHB_PHB3C_M32_EN PPC_BIT(16) 87 #define PHB_RTT_BAR 0x168 88 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 89 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(14, 46) 90 #define PHB_PELTV_BAR 0x188 91 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 92 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(14, 50) 93 #define PHB_M32_BASE_ADDR 0x190 94 #define PHB_M32_BASE_MASK 0x198 95 #define PHB_M32_START_ADDR 0x1a0 96 #define PHB_PEST_BAR 0x1a8 97 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 98 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(14, 51) 99 #define PHB_M64_UPPER_BITS 0x1f0 100 #define PHB_INTREP_TIMER 0x1f8 101 #define PHB_DMARD_SYNC 0x200 102 #define PHB_DMARD_SYNC_START PPC_BIT(0) 103 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 104 #define PHB_RTC_INVALIDATE 0x208 105 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 106 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) 107 #define PHB_TCE_KILL 0x210 108 #define PHB_TCE_KILL_ALL PPC_BIT(0) 109 #define PHB_TCE_SPEC_CTL 0x218 110 #define PHB_IODA_ADDR 0x220 111 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 112 #define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15) 113 #define PHB_IODA_AD_TADR PPC_BITMASK(55, 63) 114 #define PHB_IODA_DATA0 0x228 115 #define PHB_FFI_REQUEST 0x238 116 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) 117 #define PHB_FFI_REQUEST_ISN PPC_BITMASK(49, 59) 118 #define PHB_FFI_LOCK 0x240 119 #define PHB_FFI_LOCK_STATE PPC_BIT(0) 120 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ 121 #define PHB_PHB3_GEN_CAP 0x250 122 #define PHB_PHB3_TCE_CAP 0x258 123 #define PHB_PHB3_IRQ_CAP 0x260 124 #define PHB_PHB3_EEH_CAP 0x268 125 #define PHB_IVC_INVALIDATE 0x2a0 126 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0) 127 #define PHB_IVC_INVALIDATE_SID PPC_BITMASK(16, 31) 128 #define PHB_IVC_UPDATE 0x2a8 129 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0) 130 #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1) 131 #define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2) 132 #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3) 133 #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4) 134 #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5) 135 #define PHB_IVC_UPDATE_GEN_MATCH PPC_BITMASK(6, 7) 136 #define PHB_IVC_UPDATE_SERVER PPC_BITMASK(8, 23) 137 #define PHB_IVC_UPDATE_PRI PPC_BITMASK(24, 31) 138 #define PHB_IVC_UPDATE_GEN PPC_BITMASK(32, 33) 139 #define PHB_IVC_UPDATE_P PPC_BITMASK(34, 34) 140 #define PHB_IVC_UPDATE_Q PPC_BITMASK(35, 35) 141 #define PHB_IVC_UPDATE_SID PPC_BITMASK(48, 63) 142 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 143 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 144 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 145 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 146 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 147 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 148 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 149 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 150 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 151 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16, 63) 152 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 153 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4, 11) 154 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63) 155 #define PHB_ETU_ERR_SUMMARY 0x2c8 156 157 /* UTL registers */ 158 #define UTL_SYS_BUS_CONTROL 0x400 159 #define UTL_STATUS 0x408 160 #define UTL_SYS_BUS_AGENT_STATUS 0x410 161 #define UTL_SYS_BUS_AGENT_ERR_SEVERITY 0x418 162 #define UTL_SYS_BUS_AGENT_IRQ_EN 0x420 163 #define UTL_SYS_BUS_BURST_SZ_CONF 0x440 164 #define UTL_REVISION_ID 0x448 165 #define UTL_BCLK_DOMAIN_DBG1 0x460 166 #define UTL_BCLK_DOMAIN_DBG2 0x468 167 #define UTL_BCLK_DOMAIN_DBG3 0x470 168 #define UTL_BCLK_DOMAIN_DBG4 0x478 169 #define UTL_BCLK_DOMAIN_DBG5 0x480 170 #define UTL_BCLK_DOMAIN_DBG6 0x488 171 #define UTL_OUT_POST_HDR_BUF_ALLOC 0x4c0 172 #define UTL_OUT_POST_DAT_BUF_ALLOC 0x4d0 173 #define UTL_IN_POST_HDR_BUF_ALLOC 0x4e0 174 #define UTL_IN_POST_DAT_BUF_ALLOC 0x4f0 175 #define UTL_OUT_NP_BUF_ALLOC 0x500 176 #define UTL_IN_NP_BUF_ALLOC 0x510 177 #define UTL_PCIE_TAGS_ALLOC 0x520 178 #define UTL_GBIF_READ_TAGS_ALLOC 0x530 179 #define UTL_PCIE_PORT_CONTROL 0x540 180 #define UTL_PCIE_PORT_STATUS 0x548 181 #define UTL_PCIE_PORT_ERROR_SEV 0x550 182 #define UTL_PCIE_PORT_IRQ_EN 0x558 183 #define UTL_RC_STATUS 0x560 184 #define UTL_RC_ERR_SEVERITY 0x568 185 #define UTL_RC_IRQ_EN 0x570 186 #define UTL_EP_STATUS 0x578 187 #define UTL_EP_ERR_SEVERITY 0x580 188 #define UTL_EP_ERR_IRQ_EN 0x588 189 #define UTL_PCI_PM_CTRL1 0x590 190 #define UTL_PCI_PM_CTRL2 0x598 191 #define UTL_GP_CTL1 0x5a0 192 #define UTL_GP_CTL2 0x5a8 193 #define UTL_PCLK_DOMAIN_DBG1 0x5b0 194 #define UTL_PCLK_DOMAIN_DBG2 0x5b8 195 #define UTL_PCLK_DOMAIN_DBG3 0x5c0 196 #define UTL_PCLK_DOMAIN_DBG4 0x5c8 197 198 /* PCI-E Stack registers */ 199 #define PHB_PCIE_SYSTEM_CONFIG 0x600 200 #define PHB_PCIE_BUS_NUMBER 0x608 201 #define PHB_PCIE_SYSTEM_TEST 0x618 202 #define PHB_PCIE_LINK_MANAGEMENT 0x630 203 #define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8) 204 #define PHB_PCIE_DLP_TRAIN_CTL 0x640 205 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1) 206 #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16) 207 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 208 #define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21) 209 #define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22) 210 #define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23) 211 #define PHB_PCIE_SLOP_LOOPBACK_STATUS 0x648 212 #define PHB_PCIE_SYS_LINK_INIT 0x668 213 #define PHB_PCIE_UTL_CONFIG 0x670 214 #define PHB_PCIE_DLP_CONTROL 0x678 215 #define PHB_PCIE_UTL_ERRLOG1 0x680 216 #define PHB_PCIE_UTL_ERRLOG2 0x688 217 #define PHB_PCIE_UTL_ERRLOG3 0x690 218 #define PHB_PCIE_UTL_ERRLOG4 0x698 219 #define PHB_PCIE_DLP_ERRLOG1 0x6a0 220 #define PHB_PCIE_DLP_ERRLOG2 0x6a8 221 #define PHB_PCIE_DLP_ERR_STATUS 0x6b0 222 #define PHB_PCIE_DLP_ERR_COUNTERS 0x6b8 223 #define PHB_PCIE_UTL_ERR_INJECT 0x6c0 224 #define PHB_PCIE_TLDLP_ERR_INJECT 0x6c8 225 #define PHB_PCIE_LANE_EQ_CNTL0 0x6d0 226 #define PHB_PCIE_LANE_EQ_CNTL1 0x6d8 227 #define PHB_PCIE_LANE_EQ_CNTL2 0x6e0 228 #define PHB_PCIE_LANE_EQ_CNTL3 0x6e8 229 #define PHB_PCIE_STRAPPING 0x700 230 231 /* Fundamental register set B */ 232 #define PHB_VERSION 0x800 233 #define PHB_RESET 0x808 234 #define PHB_CONTROL 0x810 235 #define PHB_CTRL_IVE_128_BYTES PPC_BIT(24) 236 #define PHB_AIB_RX_CRED_INIT_TIMER 0x818 237 #define PHB_AIB_RX_CMD_CRED 0x820 238 #define PHB_AIB_RX_DATA_CRED 0x828 239 #define PHB_AIB_TX_CMD_CRED 0x830 240 #define PHB_AIB_TX_DATA_CRED 0x838 241 #define PHB_AIB_TX_CHAN_MAPPING 0x840 242 #define PHB_AIB_TAG_ENABLE 0x858 243 #define PHB_AIB_FENCE_CTRL 0x860 244 #define PHB_TCE_TAG_ENABLE 0x868 245 #define PHB_TCE_WATERMARK 0x870 246 #define PHB_TIMEOUT_CTRL1 0x878 247 #define PHB_TIMEOUT_CTRL2 0x880 248 #define PHB_Q_DMA_R 0x888 249 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 250 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 251 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 252 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 253 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 254 #define PHB_AIB_TAG_STATUS 0x900 255 #define PHB_TCE_TAG_STATUS 0x908 256 257 /* FIR & Error registers */ 258 #define PHB_LEM_FIR_ACCUM 0xc00 259 #define PHB_LEM_FIR_AND_MASK 0xc08 260 #define PHB_LEM_FIR_OR_MASK 0xc10 261 #define PHB_LEM_ERROR_MASK 0xc18 262 #define PHB_LEM_ERROR_AND_MASK 0xc20 263 #define PHB_LEM_ERROR_OR_MASK 0xc28 264 #define PHB_LEM_ACTION0 0xc30 265 #define PHB_LEM_ACTION1 0xc38 266 #define PHB_LEM_WOF 0xc40 267 #define PHB_ERR_STATUS 0xc80 268 #define PHB_ERR1_STATUS 0xc88 269 #define PHB_ERR_INJECT 0xc90 270 #define PHB_ERR_LEM_ENABLE 0xc98 271 #define PHB_ERR_IRQ_ENABLE 0xca0 272 #define PHB_ERR_FREEZE_ENABLE 0xca8 273 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 274 #define PHB_ERR_LOG_0 0xcc0 275 #define PHB_ERR_LOG_1 0xcc8 276 #define PHB_ERR_STATUS_MASK 0xcd0 277 #define PHB_ERR1_STATUS_MASK 0xcd8 278 279 #define PHB_OUT_ERR_STATUS 0xd00 280 #define PHB_OUT_ERR1_STATUS 0xd08 281 #define PHB_OUT_ERR_INJECT 0xd10 282 #define PHB_OUT_ERR_LEM_ENABLE 0xd18 283 #define PHB_OUT_ERR_IRQ_ENABLE 0xd20 284 #define PHB_OUT_ERR_FREEZE_ENABLE 0xd28 285 #define PHB_OUT_ERR_AIB_FENCE_ENABLE 0xd30 286 #define PHB_OUT_ERR_LOG_0 0xd40 287 #define PHB_OUT_ERR_LOG_1 0xd48 288 #define PHB_OUT_ERR_STATUS_MASK 0xd50 289 #define PHB_OUT_ERR1_STATUS_MASK 0xd58 290 291 #define PHB_INA_ERR_STATUS 0xd80 292 #define PHB_INA_ERR1_STATUS 0xd88 293 #define PHB_INA_ERR_INJECT 0xd90 294 #define PHB_INA_ERR_LEM_ENABLE 0xd98 295 #define PHB_INA_ERR_IRQ_ENABLE 0xda0 296 #define PHB_INA_ERR_FREEZE_ENABLE 0xda8 297 #define PHB_INA_ERR_AIB_FENCE_ENABLE 0xdb0 298 #define PHB_INA_ERR_LOG_0 0xdc0 299 #define PHB_INA_ERR_LOG_1 0xdc8 300 #define PHB_INA_ERR_STATUS_MASK 0xdd0 301 #define PHB_INA_ERR1_STATUS_MASK 0xdd8 302 303 #define PHB_INB_ERR_STATUS 0xe00 304 #define PHB_INB_ERR1_STATUS 0xe08 305 #define PHB_INB_ERR_INJECT 0xe10 306 #define PHB_INB_ERR_LEM_ENABLE 0xe18 307 #define PHB_INB_ERR_IRQ_ENABLE 0xe20 308 #define PHB_INB_ERR_FREEZE_ENABLE 0xe28 309 #define PHB_INB_ERR_AIB_FENCE_ENABLE 0xe30 310 #define PHB_INB_ERR_LOG_0 0xe40 311 #define PHB_INB_ERR_LOG_1 0xe48 312 #define PHB_INB_ERR_STATUS_MASK 0xe50 313 #define PHB_INB_ERR1_STATUS_MASK 0xe58 314 315 /* Performance monitor & Debug registers */ 316 #define PHB_TRACE_CONTROL 0xf80 317 #define PHB_PERFMON_CONFIG 0xf88 318 #define PHB_PERFMON_CTR0 0xf90 319 #define PHB_PERFMON_CTR1 0xf98 320 #define PHB_PERFMON_CTR2 0xfa0 321 #define PHB_PERFMON_CTR3 0xfa8 322 #define PHB_HOTPLUG_OVERRIDE 0xfb0 323 #define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9) 324 #define PHB_HPOVR_PRESENCE_A PPC_BIT(10) 325 #define PHB_HPOVR_PRESENCE_B PPC_BIT(11) 326 #define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12) 327 #define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13) 328 #define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14) 329 330 /* 331 * IODA2 on-chip tables 332 */ 333 334 #define IODA2_TBL_LIST 1 335 #define IODA2_TBL_LXIVT 2 336 #define IODA2_TBL_IVC_CAM 3 337 #define IODA2_TBL_RBA 4 338 #define IODA2_TBL_RCAM 5 339 #define IODA2_TBL_MRT 6 340 #define IODA2_TBL_PESTA 7 341 #define IODA2_TBL_PESTB 8 342 #define IODA2_TBL_TVT 9 343 #define IODA2_TBL_TCAM 10 344 #define IODA2_TBL_TDR 11 345 #define IODA2_TBL_M64BT 16 346 #define IODA2_TBL_M32DT 17 347 #define IODA2_TBL_PEEV 20 348 349 /* LXIVT */ 350 #define IODA2_LXIVT_SERVER PPC_BITMASK(8, 23) 351 #define IODA2_LXIVT_PRIORITY PPC_BITMASK(24, 31) 352 #define IODA2_LXIVT_NODE_ID PPC_BITMASK(56, 63) 353 354 /* IVT */ 355 #define IODA2_IVT_SERVER PPC_BITMASK(0, 23) 356 #define IODA2_IVT_PRIORITY PPC_BITMASK(24, 31) 357 #define IODA2_IVT_GEN PPC_BITMASK(37, 38) 358 #define IODA2_IVT_P PPC_BITMASK(39, 39) 359 #define IODA2_IVT_Q PPC_BITMASK(47, 47) 360 #define IODA2_IVT_PE PPC_BITMASK(48, 63) 361 362 /* TVT */ 363 #define IODA2_TVT_TABLE_ADDR PPC_BITMASK(0, 47) 364 #define IODA2_TVT_NUM_LEVELS PPC_BITMASK(48, 50) 365 #define IODA2_TVE_1_LEVEL 0 366 #define IODA2_TVE_2_LEVELS 1 367 #define IODA2_TVE_3_LEVELS 2 368 #define IODA2_TVE_4_LEVELS 3 369 #define IODA2_TVE_5_LEVELS 4 370 #define IODA2_TVT_TCE_TABLE_SIZE PPC_BITMASK(51, 55) 371 #define IODA2_TVT_IO_PSIZE PPC_BITMASK(59, 63) 372 373 /* PESTA */ 374 #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0) 375 376 /* PESTB */ 377 #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0) 378 379 /* M32DT */ 380 #define IODA2_M32DT_PE PPC_BITMASK(8, 15) 381 382 /* M64BT */ 383 #define IODA2_M64BT_ENABLE PPC_BIT(0) 384 #define IODA2_M64BT_SINGLE_PE PPC_BIT(1) 385 #define IODA2_M64BT_BASE PPC_BITMASK(2, 31) 386 #define IODA2_M64BT_MASK PPC_BITMASK(34, 63) 387 #define IODA2_M64BT_SINGLE_BASE PPC_BITMASK(2, 26) 388 #define IODA2_M64BT_PE_HI PPC_BITMASK(27, 31) 389 #define IODA2_M64BT_SINGLE_MASK PPC_BITMASK(34, 58) 390 #define IODA2_M64BT_PE_LOW PPC_BITMASK(59, 63) 391 392 /* 393 * IODA2 in-memory tables 394 */ 395 396 /* 397 * PEST 398 * 399 * 2x8 bytes entries, PEST0 and PEST1 400 */ 401 402 #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2) 403 #define IODA2_PEST0_CFG_READ PPC_BIT(3) 404 #define IODA2_PEST0_CFG_WRITE PPC_BIT(4) 405 #define IODA2_PEST0_TTYPE PPC_BITMASK(5, 7) 406 #define PEST_TTYPE_DMA_WRITE 0 407 #define PEST_TTYPE_MSI 1 408 #define PEST_TTYPE_DMA_READ 2 409 #define PEST_TTYPE_DMA_READ_RESP 3 410 #define PEST_TTYPE_MMIO_LOAD 4 411 #define PEST_TTYPE_MMIO_STORE 5 412 #define PEST_TTYPE_OTHER 7 413 #define IODA2_PEST0_CA_RETURN PPC_BIT(8) 414 #define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */ 415 #define IODA2_PEST0_UR_RETURN PPC_BIT(9) 416 #define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10) 417 #define IODA2_PEST0_UTL_FATAL PPC_BIT(11) 418 #define IODA2_PEST0_PARITY_UE PPC_BIT(13) 419 #define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14) 420 #define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15) 421 #define IODA2_PEST0_MMIO_XLATE PPC_BIT(16) 422 #define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 423 #define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 424 #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 425 #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 426 #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 427 #define IODA2_PEST0_LEM_BIT PPC_BITMASK(26, 31) 428 #define IODA2_PEST0_RID PPC_BITMASK(32, 47) 429 #define IODA2_PEST0_MSI_DATA PPC_BITMASK(48, 63) 430 431 #define IODA2_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) 432 433 434 #endif /* PCI_HOST_PNV_PHB3_REGS_H */