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pnv_phb3.h (4408B)

      1 /*
      2  * QEMU PowerPC PowerNV (POWER8) PHB3 model
      3  *
      4  * Copyright (c) 2014-2020, IBM Corporation.
      5  *
      6  * This code is licensed under the GPL version 2 or later. See the
      7  * COPYING file in the top-level directory.
      8  */
      9 
     10 #ifndef PCI_HOST_PNV_PHB3_H
     11 #define PCI_HOST_PNV_PHB3_H
     12 
     13 #include "hw/pci/pcie_host.h"
     14 #include "hw/pci/pcie_port.h"
     15 #include "hw/ppc/xics.h"
     16 #include "qom/object.h"
     17 #include "hw/pci-host/pnv_phb.h"
     18 
     19 typedef struct PnvPHB3 PnvPHB3;
     20 typedef struct PnvChip PnvChip;
     21 
     22 /*
     23  * PHB3 XICS Source for MSIs
     24  */
     25 #define TYPE_PHB3_MSI "phb3-msi"
     26 typedef struct Phb3MsiState Phb3MsiState;
     27 DECLARE_INSTANCE_CHECKER(Phb3MsiState, PHB3_MSI,
     28                          TYPE_PHB3_MSI)
     29 
     30 #define PHB3_MAX_MSI     2048
     31 
     32 struct Phb3MsiState {
     33     ICSState ics;
     34     qemu_irq *qirqs;
     35 
     36     PnvPHB3 *phb;
     37     uint64_t rba[PHB3_MAX_MSI / 64];
     38     uint32_t rba_sum;
     39 };
     40 
     41 void pnv_phb3_msi_update_config(Phb3MsiState *msis, uint32_t base,
     42                                 uint32_t count);
     43 void pnv_phb3_msi_send(Phb3MsiState *msis, uint64_t addr, uint16_t data,
     44                        int32_t dev_pe);
     45 void pnv_phb3_msi_ffi(Phb3MsiState *msis, uint64_t val);
     46 void pnv_phb3_msi_pic_print_info(Phb3MsiState *msis, Monitor *mon);
     47 
     48 
     49 /*
     50  * We have one such address space wrapper per possible device under
     51  * the PHB since they need to be assigned statically at qemu device
     52  * creation time. The relationship to a PE is done later dynamically.
     53  * This means we can potentially create a lot of these guys. Q35
     54  * stores them as some kind of radix tree but we never really need to
     55  * do fast lookups so instead we simply keep a QLIST of them for now,
     56  * we can add the radix if needed later on.
     57  *
     58  * We do cache the PE number to speed things up a bit though.
     59  */
     60 typedef struct PnvPhb3DMASpace {
     61     PCIBus *bus;
     62     uint8_t devfn;
     63     int pe_num;         /* Cached PE number */
     64 #define PHB_INVALID_PE (-1)
     65     PnvPHB3 *phb;
     66     AddressSpace dma_as;
     67     IOMMUMemoryRegion dma_mr;
     68     MemoryRegion msi32_mr;
     69     MemoryRegion msi64_mr;
     70     QLIST_ENTRY(PnvPhb3DMASpace) list;
     71 } PnvPhb3DMASpace;
     72 
     73 /*
     74  * PHB3 Power Bus Common Queue
     75  */
     76 #define TYPE_PNV_PBCQ "pnv-pbcq"
     77 OBJECT_DECLARE_SIMPLE_TYPE(PnvPBCQState, PNV_PBCQ)
     78 
     79 struct PnvPBCQState {
     80     DeviceState parent;
     81 
     82     uint32_t nest_xbase;
     83     uint32_t spci_xbase;
     84     uint32_t pci_xbase;
     85 #define PBCQ_NEST_REGS_COUNT    0x46
     86 #define PBCQ_PCI_REGS_COUNT     0x15
     87 #define PBCQ_SPCI_REGS_COUNT    0x5
     88 
     89     uint64_t nest_regs[PBCQ_NEST_REGS_COUNT];
     90     uint64_t spci_regs[PBCQ_SPCI_REGS_COUNT];
     91     uint64_t pci_regs[PBCQ_PCI_REGS_COUNT];
     92     MemoryRegion mmbar0;
     93     MemoryRegion mmbar1;
     94     MemoryRegion phbbar;
     95     uint64_t mmio0_base;
     96     uint64_t mmio0_size;
     97     uint64_t mmio1_base;
     98     uint64_t mmio1_size;
     99     PnvPHB3 *phb;
    100 
    101     MemoryRegion xscom_nest_regs;
    102     MemoryRegion xscom_pci_regs;
    103     MemoryRegion xscom_spci_regs;
    104 };
    105 
    106 /*
    107  * PHB3 PCIe Root Bus
    108  */
    109 #define TYPE_PNV_PHB3_ROOT_BUS "pnv-phb3-root"
    110 struct PnvPHB3RootBus {
    111     PCIBus parent;
    112 
    113     uint32_t chip_id;
    114     uint32_t phb_id;
    115 };
    116 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3RootBus, PNV_PHB3_ROOT_BUS)
    117 
    118 /*
    119  * PHB3 PCIe Host Bridge for PowerNV machines (POWER8)
    120  */
    121 #define TYPE_PNV_PHB3 "pnv-phb3"
    122 OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3)
    123 
    124 #define PNV_PHB3_NUM_M64      16
    125 #define PNV_PHB3_NUM_REGS     (0x1000 >> 3)
    126 #define PNV_PHB3_NUM_LSI      8
    127 #define PNV_PHB3_NUM_PE       256
    128 
    129 #define PCI_MMIO_TOTAL_SIZE   (0x1ull << 60)
    130 
    131 struct PnvPHB3 {
    132     DeviceState parent;
    133 
    134     PnvPHB *phb_base;
    135 
    136     uint32_t chip_id;
    137     uint32_t phb_id;
    138     char bus_path[8];
    139 
    140     uint64_t regs[PNV_PHB3_NUM_REGS];
    141     MemoryRegion mr_regs;
    142 
    143     MemoryRegion mr_m32;
    144     MemoryRegion mr_m64[PNV_PHB3_NUM_M64];
    145     MemoryRegion pci_mmio;
    146     MemoryRegion pci_io;
    147 
    148     uint64_t ioda_LIST[8];
    149     uint64_t ioda_LXIVT[8];
    150     uint64_t ioda_TVT[512];
    151     uint64_t ioda_M64BT[16];
    152     uint64_t ioda_MDT[256];
    153     uint64_t ioda_PEEV[4];
    154 
    155     uint32_t total_irq;
    156     ICSState lsis;
    157     qemu_irq *qirqs;
    158     Phb3MsiState msis;
    159 
    160     PnvPBCQState pbcq;
    161 
    162     QLIST_HEAD(, PnvPhb3DMASpace) dma_spaces;
    163 
    164     PnvChip *chip;
    165 };
    166 
    167 uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size);
    168 void pnv_phb3_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size);
    169 void pnv_phb3_update_regions(PnvPHB3 *phb);
    170 void pnv_phb3_remap_irqs(PnvPHB3 *phb);
    171 void pnv_phb3_bus_init(DeviceState *dev, PnvPHB3 *phb);
    172 
    173 #endif /* PCI_HOST_PNV_PHB3_H */