npcm7xx_gcr.h (2384B)
1 /* 2 * Nuvoton NPCM7xx System Global Control Registers. 3 * 4 * Copyright 2020 Google LLC 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * for more details. 15 */ 16 #ifndef NPCM7XX_GCR_H 17 #define NPCM7XX_GCR_H 18 19 #include "exec/memory.h" 20 #include "hw/sysbus.h" 21 22 /* 23 * NPCM7XX PWRON STRAP bit fields 24 * 12: SPI0 powered by VSBV3 at 1.8V 25 * 11: System flash attached to BMC 26 * 10: BSP alternative pins. 27 * 9:8: Flash UART command route enabled. 28 * 7: Security enabled. 29 * 6: HI-Z state control. 30 * 5: ECC disabled. 31 * 4: Reserved 32 * 3: JTAG2 enabled. 33 * 2:0: CPU and DRAM clock frequency. 34 */ 35 #define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) 36 #define NPCM7XX_PWRON_STRAP_SFAB BIT(11) 37 #define NPCM7XX_PWRON_STRAP_BSPA BIT(10) 38 #define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) 39 #define FUP_NORM_UART2 3 40 #define FUP_PROG_UART3 2 41 #define FUP_PROG_UART2 1 42 #define FUP_NORM_UART3 0 43 #define NPCM7XX_PWRON_STRAP_SECEN BIT(7) 44 #define NPCM7XX_PWRON_STRAP_HIZ BIT(6) 45 #define NPCM7XX_PWRON_STRAP_ECC BIT(5) 46 #define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) 47 #define NPCM7XX_PWRON_STRAP_J2EN BIT(3) 48 #define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) 49 #define CKFRQ_SKIPINIT 0x000 50 #define CKFRQ_DEFAULT 0x111 51 52 /* 53 * Number of registers in our device state structure. Don't change this without 54 * incrementing the version_id in the vmstate. 55 */ 56 #define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t)) 57 58 typedef struct NPCM7xxGCRState { 59 SysBusDevice parent; 60 61 MemoryRegion iomem; 62 63 uint32_t regs[NPCM7XX_GCR_NR_REGS]; 64 65 uint32_t reset_pwron; 66 uint32_t reset_mdlr; 67 uint32_t reset_intcr3; 68 } NPCM7xxGCRState; 69 70 #define TYPE_NPCM7XX_GCR "npcm7xx-gcr" 71 #define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR) 72 73 #endif /* NPCM7XX_GCR_H */