ioapic_internal.h (4114B)
1 /* 2 * IOAPIC emulation logic - internal interfaces 3 * 4 * Copyright (c) 2004-2005 Fabrice Bellard 5 * Copyright (c) 2009 Xiantao Zhang, Intel 6 * Copyright (c) 2011 Jan Kiszka, Siemens AG 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef QEMU_IOAPIC_INTERNAL_H 23 #define QEMU_IOAPIC_INTERNAL_H 24 25 #include "exec/memory.h" 26 #include "hw/sysbus.h" 27 #include "qemu/notify.h" 28 #include "qom/object.h" 29 30 #define MAX_IOAPICS 2 31 32 #define IOAPIC_LVT_DEST_SHIFT 56 33 #define IOAPIC_LVT_DEST_IDX_SHIFT 48 34 #define IOAPIC_LVT_MASKED_SHIFT 16 35 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15 36 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14 37 #define IOAPIC_LVT_POLARITY_SHIFT 13 38 #define IOAPIC_LVT_DELIV_STATUS_SHIFT 12 39 #define IOAPIC_LVT_DEST_MODE_SHIFT 11 40 #define IOAPIC_LVT_DELIV_MODE_SHIFT 8 41 42 #define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT) 43 #define IOAPIC_LVT_TRIGGER_MODE (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT) 44 #define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT) 45 #define IOAPIC_LVT_POLARITY (1 << IOAPIC_LVT_POLARITY_SHIFT) 46 #define IOAPIC_LVT_DELIV_STATUS (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT) 47 #define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT) 48 #define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT) 49 50 /* Bits that are read-only for IOAPIC entry */ 51 #define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \ 52 IOAPIC_LVT_DELIV_STATUS) 53 #define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS) 54 55 #define IOAPIC_TRIGGER_EDGE 0 56 #define IOAPIC_TRIGGER_LEVEL 1 57 58 /*io{apic,sapic} delivery mode*/ 59 #define IOAPIC_DM_FIXED 0x0 60 #define IOAPIC_DM_LOWEST_PRIORITY 0x1 61 #define IOAPIC_DM_PMI 0x2 62 #define IOAPIC_DM_NMI 0x4 63 #define IOAPIC_DM_INIT 0x5 64 #define IOAPIC_DM_SIPI 0x6 65 #define IOAPIC_DM_EXTINT 0x7 66 #define IOAPIC_DM_MASK 0x7 67 68 #define IOAPIC_VECTOR_MASK 0xff 69 70 #define IOAPIC_IOREGSEL 0x00 71 #define IOAPIC_IOWIN 0x10 72 #define IOAPIC_EOI 0x40 73 74 #define IOAPIC_REG_ID 0x00 75 #define IOAPIC_REG_VER 0x01 76 #define IOAPIC_REG_ARB 0x02 77 #define IOAPIC_REG_REDTBL_BASE 0x10 78 #define IOAPIC_ID 0x00 79 80 #define IOAPIC_ID_SHIFT 24 81 #define IOAPIC_ID_MASK 0xf 82 83 #define IOAPIC_VER_ENTRIES_SHIFT 16 84 85 86 #define TYPE_IOAPIC_COMMON "ioapic-common" 87 OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON) 88 89 struct IOAPICCommonClass { 90 SysBusDeviceClass parent_class; 91 92 DeviceRealize realize; 93 DeviceUnrealize unrealize; 94 void (*pre_save)(IOAPICCommonState *s); 95 void (*post_load)(IOAPICCommonState *s); 96 }; 97 98 struct IOAPICCommonState { 99 SysBusDevice busdev; 100 MemoryRegion io_memory; 101 uint8_t id; 102 uint8_t ioregsel; 103 uint32_t irr; 104 uint64_t ioredtbl[IOAPIC_NUM_PINS]; 105 Notifier machine_done; 106 uint8_t version; 107 uint64_t irq_count[IOAPIC_NUM_PINS]; 108 int irq_level[IOAPIC_NUM_PINS]; 109 int irq_eoi[IOAPIC_NUM_PINS]; 110 QEMUTimer *delayed_ioapic_service_timer; 111 }; 112 113 void ioapic_reset_common(DeviceState *dev); 114 115 void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level); 116 117 #endif /* QEMU_IOAPIC_INTERNAL_H */