intel_iommu.h (10820B)
1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 25 #include "hw/i386/x86-iommu.h" 26 #include "qemu/iova-tree.h" 27 #include "qom/object.h" 28 29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 30 OBJECT_DECLARE_SIMPLE_TYPE(IntelIOMMUState, INTEL_IOMMU_DEVICE) 31 32 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 33 34 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 35 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 36 37 #define VTD_PCI_BUS_MAX 256 38 #define VTD_PCI_SLOT_MAX 32 39 #define VTD_PCI_FUNC_MAX 8 40 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 41 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 42 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 43 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 44 45 #define DMAR_REG_SIZE 0x230 46 #define VTD_HOST_AW_39BIT 39 47 #define VTD_HOST_AW_48BIT 48 48 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT 49 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) 50 51 #define DMAR_REPORT_F_INTR (1) 52 53 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 54 #define VTD_MSI_ADDR_HI_SHIFT (32) 55 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 56 57 typedef struct VTDContextEntry VTDContextEntry; 58 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 59 typedef struct VTDAddressSpace VTDAddressSpace; 60 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 61 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 62 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 63 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; 64 typedef struct VTDPASIDEntry VTDPASIDEntry; 65 66 /* Context-Entry */ 67 struct VTDContextEntry { 68 union { 69 struct { 70 uint64_t lo; 71 uint64_t hi; 72 }; 73 struct { 74 uint64_t val[4]; 75 }; 76 }; 77 }; 78 79 struct VTDContextCacheEntry { 80 /* The cache entry is obsolete if 81 * context_cache_gen!=IntelIOMMUState.context_cache_gen 82 */ 83 uint32_t context_cache_gen; 84 struct VTDContextEntry context_entry; 85 }; 86 87 /* PASID Directory Entry */ 88 struct VTDPASIDDirEntry { 89 uint64_t val; 90 }; 91 92 /* PASID Table Entry */ 93 struct VTDPASIDEntry { 94 uint64_t val[8]; 95 }; 96 97 struct VTDAddressSpace { 98 PCIBus *bus; 99 uint8_t devfn; 100 uint32_t pasid; 101 AddressSpace as; 102 IOMMUMemoryRegion iommu; 103 MemoryRegion root; /* The root container of the device */ 104 MemoryRegion nodmar; /* The alias of shared nodmar MR */ 105 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 106 MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ 107 IntelIOMMUState *iommu_state; 108 VTDContextCacheEntry context_cache_entry; 109 QLIST_ENTRY(VTDAddressSpace) next; 110 /* Superset of notifier flags that this address space has */ 111 IOMMUNotifierFlag notifier_flags; 112 IOVATree *iova_tree; /* Traces mapped IOVA ranges */ 113 }; 114 115 struct VTDIOTLBEntry { 116 uint64_t gfn; 117 uint16_t domain_id; 118 uint32_t pasid; 119 uint64_t slpte; 120 uint64_t mask; 121 uint8_t access_flags; 122 }; 123 124 /* VT-d Source-ID Qualifier types */ 125 enum { 126 VTD_SQ_FULL = 0x00, /* Full SID verification */ 127 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 128 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 129 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 130 VTD_SQ_MAX, 131 }; 132 133 /* VT-d Source Validation Types */ 134 enum { 135 VTD_SVT_NONE = 0x00, /* No validation */ 136 VTD_SVT_ALL = 0x01, /* Do full validation */ 137 VTD_SVT_BUS = 0x02, /* Validate bus range */ 138 VTD_SVT_MAX, 139 }; 140 141 /* Interrupt Remapping Table Entry Definition */ 142 union VTD_IR_TableEntry { 143 struct { 144 #if HOST_BIG_ENDIAN 145 uint32_t __reserved_1:8; /* Reserved 1 */ 146 uint32_t vector:8; /* Interrupt Vector */ 147 uint32_t irte_mode:1; /* IRTE Mode */ 148 uint32_t __reserved_0:3; /* Reserved 0 */ 149 uint32_t __avail:4; /* Available spaces for software */ 150 uint32_t delivery_mode:3; /* Delivery Mode */ 151 uint32_t trigger_mode:1; /* Trigger Mode */ 152 uint32_t redir_hint:1; /* Redirection Hint */ 153 uint32_t dest_mode:1; /* Destination Mode */ 154 uint32_t fault_disable:1; /* Fault Processing Disable */ 155 uint32_t present:1; /* Whether entry present/available */ 156 #else 157 uint32_t present:1; /* Whether entry present/available */ 158 uint32_t fault_disable:1; /* Fault Processing Disable */ 159 uint32_t dest_mode:1; /* Destination Mode */ 160 uint32_t redir_hint:1; /* Redirection Hint */ 161 uint32_t trigger_mode:1; /* Trigger Mode */ 162 uint32_t delivery_mode:3; /* Delivery Mode */ 163 uint32_t __avail:4; /* Available spaces for software */ 164 uint32_t __reserved_0:3; /* Reserved 0 */ 165 uint32_t irte_mode:1; /* IRTE Mode */ 166 uint32_t vector:8; /* Interrupt Vector */ 167 uint32_t __reserved_1:8; /* Reserved 1 */ 168 #endif 169 uint32_t dest_id; /* Destination ID */ 170 uint16_t source_id; /* Source-ID */ 171 #if HOST_BIG_ENDIAN 172 uint64_t __reserved_2:44; /* Reserved 2 */ 173 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 174 uint64_t sid_q:2; /* Source-ID Qualifier */ 175 #else 176 uint64_t sid_q:2; /* Source-ID Qualifier */ 177 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 178 uint64_t __reserved_2:44; /* Reserved 2 */ 179 #endif 180 } QEMU_PACKED irte; 181 uint64_t data[2]; 182 }; 183 184 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 185 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 186 187 /* Programming format for MSI/MSI-X addresses */ 188 union VTD_IR_MSIAddress { 189 struct { 190 #if HOST_BIG_ENDIAN 191 uint32_t __head:12; /* Should always be: 0x0fee */ 192 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 193 uint32_t int_mode:1; /* Interrupt format */ 194 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 195 uint32_t index_h:1; /* Interrupt index bit 15 */ 196 uint32_t __not_care:2; 197 #else 198 uint32_t __not_care:2; 199 uint32_t index_h:1; /* Interrupt index bit 15 */ 200 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 201 uint32_t int_mode:1; /* Interrupt format */ 202 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 203 uint32_t __head:12; /* Should always be: 0x0fee */ 204 #endif 205 } QEMU_PACKED addr; 206 uint32_t data; 207 }; 208 209 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 210 #define VTD_IR_MSI_DATA (0) 211 212 /* The iommu (DMAR) device state struct */ 213 struct IntelIOMMUState { 214 X86IOMMUState x86_iommu; 215 MemoryRegion csrmem; 216 MemoryRegion mr_nodmar; 217 MemoryRegion mr_ir; 218 MemoryRegion mr_sys_alias; 219 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 220 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 221 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 222 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 223 uint32_t version; 224 225 bool caching_mode; /* RO - is cap CM enabled? */ 226 bool scalable_mode; /* RO - is Scalable Mode supported? */ 227 bool snoop_control; /* RO - is SNP filed supported? */ 228 229 dma_addr_t root; /* Current root table pointer */ 230 bool root_scalable; /* Type of root table (scalable or not) */ 231 bool dmar_enabled; /* Set if DMA remapping is enabled */ 232 233 uint16_t iq_head; /* Current invalidation queue head */ 234 uint16_t iq_tail; /* Current invalidation queue tail */ 235 dma_addr_t iq; /* Current invalidation queue pointer */ 236 uint16_t iq_size; /* IQ Size in number of entries */ 237 bool iq_dw; /* IQ descriptor width 256bit or not */ 238 bool qi_enabled; /* Set if the QI is enabled */ 239 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 240 241 /* The index of the Fault Recording Register to be used next. 242 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 243 */ 244 uint16_t next_frcd_reg; 245 246 uint64_t cap; /* The value of capability reg */ 247 uint64_t ecap; /* The value of extended capability reg */ 248 249 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 250 GHashTable *iotlb; /* IOTLB */ 251 252 GHashTable *vtd_address_spaces; /* VTD address spaces */ 253 VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space cache */ 254 /* list of registered notifiers */ 255 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; 256 257 /* interrupt remapping */ 258 bool intr_enabled; /* Whether guest enabled IR */ 259 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 260 uint32_t intr_size; /* Number of IR table entries */ 261 bool intr_eime; /* Extended interrupt mode enabled */ 262 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 263 bool buggy_eim; /* Force buggy EIM unless eim=off */ 264 uint8_t aw_bits; /* Host/IOVA address width (in bits) */ 265 bool dma_drain; /* Whether DMA r/w draining enabled */ 266 bool dma_translation; /* Whether DMA translation supported */ 267 bool pasid; /* Whether to support PASID */ 268 269 /* 270 * Protects IOMMU states in general. Currently it protects the 271 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. 272 */ 273 QemuMutex iommu_lock; 274 }; 275 276 /* Find the VTD Address space associated with the given bus pointer, 277 * create a new one if none exists 278 */ 279 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, 280 int devfn, unsigned int pasid); 281 282 #endif